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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.04.2021 14:35:04
-- Design Name: 
-- Module Name: MemoireDonnees - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MemoireDonnees is
    Generic (Nb_bits : Natural;
             Addr_size : Natural;
             Mem_size : Natural);
    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
           RW : in STD_LOGIC;
           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           RST : in STD_LOGIC;
           CLK : in STD_LOGIC;
           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end MemoireDonnees;

architecture Behavioral of MemoireDonnees is
    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
begin
    process
    begin
        wait until CLK'event and CLK = '1';
        if (RST = '0') then
            MEMORY <= (others => '0');
        else 
            if (RW = '0') then
                MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
            end if;
        end if;
    end process;
    
    D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
end Behavioral;