diff --git a/PROJ_DEUX/DebugConfig/Simu_STM32F103RB_1.0.0.dbgconf b/PROJ_DEUX/DebugConfig/Simu_STM32F103RB_1.0.0.dbgconf new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/PROJ_DEUX/DebugConfig/Simu_STM32F103RB_1.0.0.dbgconf @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/PROJ_DEUX/Etape1a.c b/PROJ_DEUX/Etape1a.c new file mode 100644 index 0000000..e69de29 diff --git a/PROJ_DEUX/Project.uvguix.nmouk b/PROJ_DEUX/Project.uvguix.nmouk new file mode 100644 index 0000000..d004728 --- /dev/null +++ b/PROJ_DEUX/Project.uvguix.nmouk @@ -0,0 +1,1860 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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diff --git a/PROJ_DEUX/Project.uvoptx b/PROJ_DEUX/Project.uvoptx new file mode 100644 index 0000000..8100f62 --- /dev/null +++ b/PROJ_DEUX/Project.uvoptx @@ -0,0 +1,279 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Simu + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 5 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=1312,154,1733,580,1)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U066CFF574857847167074929 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOB + 35905 + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Sources + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\Src\startup-rvds.s + startup-rvds.s + 0 + 0 + + + 1 + 2 + 1 + 1 + 0 + 0 + .\Src\principal.c + principal.c + 0 + 0 + + + 1 + 3 + 2 + 0 + 0 + 0 + .\callback.s + callback.s + 0 + 0 + + + 1 + 4 + 4 + 0 + 0 + 0 + .\Src\gassp72.lib + gassp72.lib + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +
diff --git a/PROJ_DEUX/Project.uvprojx b/PROJ_DEUX/Project.uvprojx new file mode 100644 index 0000000..381d2ae --- /dev/null +++ b/PROJ_DEUX/Project.uvprojx @@ -0,0 +1,427 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Simu + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + 0 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + + + + + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Obj\ + CHTI + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --C99 + STM32F103xB,USE_FULL_LL_DRIVER + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Sources + + + startup-rvds.s + 2 + .\Src\startup-rvds.s + + + principal.c + 1 + .\Src\principal.c + + + callback.s + 2 + .\callback.s + + + gassp72.lib + 4 + .\Src\gassp72.lib + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + +
diff --git a/PROJ_DEUX/RTE/_Simu/RTE_Components.h b/PROJ_DEUX/RTE/_Simu/RTE_Components.h new file mode 100644 index 0000000..a0349ff --- /dev/null +++ b/PROJ_DEUX/RTE/_Simu/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Project' + * Target: 'Simu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/PROJ_DEUX/Src/gassp72.h b/PROJ_DEUX/Src/gassp72.h new file mode 100644 index 0000000..6cfaee4 --- /dev/null +++ b/PROJ_DEUX/Src/gassp72.h @@ -0,0 +1,115 @@ +/** + * Bibliotheque GASSP 2013-02-15 + * + * GPIO - ADC - Sequenceur - System Timer - PWM - 72 MHz + * + */ + +// STM32F10X_CL : pour le STM32F107 "Communication Line" +// STM32F10X_MD : pour le STM32F103 "Medium Density" + +//#define STM32F10X_MD // 2019 fix for Keil 5.23 + +#include "stm32f10x.h" + +// horloge systeme (config statique a 72 MHz pour le STM32F103) ------------ +void CLOCK_Configure(void); + +// Timers 1, 2, 3, 4 ------------------------------------------------------- +// la duree entre deux debordements successifs doit etre donnnee en periodes +// d'horloge CPU (typiquement 72 MHz) +void Timer_1234_Init_ff( TIM_TypeDef *Timer, u32 Duree_ticks ); + +// activation d'une fonction de traitement de l'interruption timer (callback) +void Active_IT_Debordement_Timer( TIM_TypeDef *Timer, char Prio, void (*IT_function)(void) ); + +// bloque le timer +#define Bloque_Timer(Timer) Timer->CR1=(Timer->CR1)&~(1<<0) + +// Lance timer +#define Run_Timer(Timer) Timer->CR1=(Timer->CR1)|(1<<0) + +// PWM (basee sur un des Timers 1, 2, 3, 4 --------------------------------- +// la periode doit etre donnee en periodes d'horloge CPU (typiquement 72 MHz) +// la fonction rend la pleine echelle ou resolution, c'est a dire la plage +// de valeurs acceptees pour moduler la largeur d'impulsion +vu16 PWM_Init_ff( TIM_TypeDef *Timer, char Voie, u32 Periode_ticks ); + +// Timer systeme "SysTick" ------------------------------------------------- + +// la periode doit etre donnee en periodes d'horloge CPU (typiquement 72 MHz) +void Systick_Period_ff( unsigned int Periode_ticks ); + +// activation d'une fonction de traitement de l'interruption timer (callback) +void Systick_Prio_IT( char Prio, void (*Systick_function)(void) ); + +#define SysTick_On ((SysTick->CTRL)=(SysTick->CTRL)|1<<0) +#define SysTick_Off ((SysTick->CTRL)=(SysTick->CTRL)& ~(1<<0)) +#define SysTick_Enable_IT ((SysTick->CTRL)=(SysTick->CTRL)|1<<1) +#define SysTick_Disable_IT ((SysTick->CTRL)=(SysTick->CTRL)& ~(1<<1)) + +// ADC - DMA --------------------------------------------------------------- +// Analog-to-Digital Conversion, Direct Memory Access + +// la duree d'echantillonnage doit etre donnee en periodes d'horloge CPU (typiquement 72 MHz) +// la fonction rend la duree totale de conversion (meme unites) +u32 Init_TimingADC_ActiveADC_ff( ADC_TypeDef * ADC, u32 Duree_Ech_ticks ); + +// choix d'un canal ADC unique +void Single_Channel_ADC( ADC_TypeDef * ADC, char Voie_ADC ); + +// la periode de repetition des acquisitions doit etre donnee en periodes d'horloge CPU +// Les sources de déclenchement possibles : +#define TIM1_CC1 0 +#define TIM1_CC2 1 +#define TIM1_CC3 2 +#define TIM2_CC2 3 +#define TIM4_CC4 5 +void Init_Conversion_On_Trig_Timer_ff( ADC_TypeDef * ADC, char Source, u32 Periode_ticks ); + +// initialisation d'acquisition en mode DMA +// Ptr_Table_DMA doit pointer sur un espace memoire suffisant pour le nombre d'ech. demande +void Init_ADC1_DMA1( char Circ, vu16 *Ptr_Table_DMA ); + + +// Lance une DMA sur le nombre de points spécifie. Les resultats seront stockes +// dans la zone de RAM écrite est indiquée lors de l'appel de la fonction Init_ADC1_DMA1 +void Start_DMA1( u16 NbEchDMA ); + +// arret DMA +#define Stop_DMA1 DMA1_Channel1->CCR =(DMA1_Channel1->CCR) &~0x1; + +// fonction d'attente (bloquante) +// la duree depend de la periode d'acquisition et du nombre d'echantillons +void Wait_On_End_Of_DMA1(void); + + +// GPIO -------------------------------------------------------------------- + +// Sens +#define INPUT 'i' +#define OUTPUT 'o' + +// Techno pour pin en entrée (INPUT) +#define ANALOG 0 +#define INPUT_FLOATING 1 +#define INPUT_PULL_DOWN_UP 2 + +// Techno pour pin en sortie (OUTPUT) +#define OUTPUT_PPULL 0 +#define OUTPUT_OPDRAIN 1 +#define ALT_PPULL 2 +#define ALT_OPDRAIN 3 + +// La fonction initialise n'importe quelle broche de port (entrée, sortie, techno....) +// Exemple : +// Port_IO_Init(GPIOB, 8, OUTPUT, OUTPUT_PPULL); +// Place le bit 8 du port B en sortie Push-pull +// Renvoie 0 si tout est OK, et 1 s'il y a un problème (plage d'entrée non respectée) +char GPIO_Configure(GPIO_TypeDef * Port, int Broche, int Sens, int Techno); + +// Spécifier le numéro de broche (0 à 15) +// exemple : Port_IO_Set(GPIOB,8); +#define GPIO_Set(GPIO,Broche) GPIO->BSRR=(0x01<BRR=(0x01<>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + +; +; Enable UsageFault, MemFault and Busfault interrupts +; +_SHCSR EQU 0xE000ED24 ; SHCSR is located at address 0xE000ED24 + LDR.W R0, =_SHCSR + LDR R1, [R0] ; Read CPACR + ORR R1, R1, #(0x7 << 16) ; Set bits 16,17,18 to enable usagefault, busfault, memfault interrupts + STR R1, [R0] ; Write back the modified value to the CPACR + DSB ; Wait for store to complete + +; +; Set priority grouping (PRIGROUP) in AIRCR to 3 (16 levels for group priority and 0 for subpriority) +; +_AIRCR EQU 0xE000ED0C +_AIRCR_VAL EQU 0x05FA0300 + LDR.W R0, =_AIRCR + LDR.W R1, =_AIRCR_VAL + STR R1,[R0] + +; +; Finaly, jump to main function (void main (void)) +; + LDR R0, =__main + BX R0 + ENDP + +SystemInit PROC + EXPORT SystemInit [WEAK] + BX LR + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/PROJ_DEUX/callback.s b/PROJ_DEUX/callback.s new file mode 100644 index 0000000..07192a2 --- /dev/null +++ b/PROJ_DEUX/callback.s @@ -0,0 +1,38 @@ +; ce programme est pour l'assembleur RealView (Keil) + thumb + area madata, data, readwrite + export echelon +echelon dcd 0 + + area moncode, code, readonly + export timer_callback + +timer_callback proc + +GPIOB_BSRR equ 0x40010C10 ; Bit Set/Reset register + + ldr r2, =echelon + ldr r0,[r2] + CBZ r0, misea1 + + +; mise a zero de PB1 + ldr r3, =GPIOB_BSRR + mov r1, #0x00020000 + str r1, [r3] + add r0, #-1 + str r0,[r2] + B finn + +; mise a 1 de PB1 +misea1 ldr r3, =GPIOB_BSRR + mov r1, #0x00000002 + str r1, [r3] + add r0, #1 + str r0,[r2] +; N.B. le registre BSRR est write-only, on ne peut pas le relire + +finn bx lr; + endp +; + end diff --git a/PROJ_UN/Project.uvguix.nmouk b/PROJ_UN/Project.uvguix.nmouk new file mode 100644 index 0000000..7519864 --- /dev/null +++ b/PROJ_UN/Project.uvguix.nmouk @@ -0,0 +1,1887 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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diff --git a/PROJ_UN/Project.uvoptx b/PROJ_UN/Project.uvoptx index dec68ac..b087c2e 100644 --- a/PROJ_UN/Project.uvoptx +++ b/PROJ_UN/Project.uvoptx @@ -101,6 +101,8 @@ 0 0 1 + 0 + 0 5 @@ -190,6 +192,10 @@ + + + + System Viewer\GPIOB @@ -198,6 +204,7 @@ 1 + 0 0 2 10000000 diff --git a/PROJ_UN/Project.uvprojx b/PROJ_UN/Project.uvprojx index 8196123..17e19da 100644 --- a/PROJ_UN/Project.uvprojx +++ b/PROJ_UN/Project.uvprojx @@ -11,11 +11,12 @@ 0x4 ARM-ADS 5060422::V5.06 update 4 (build 422)::ARMCC + 0 STM32F103RB STMicroelectronics - Keil.STM32F1xx_DFP.2.2.0 + Keil.STM32F1xx_DFP.2.3.0 http://www.keil.com/pack/ IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") @@ -183,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -323,6 +325,7 @@ 0 0 0 + 0 0 1 1