From 6d91d3c4aef82d7553499f03d670c1be80508222 Mon Sep 17 00:00:00 2001 From: Clement Marce Date: Mon, 27 Mar 2023 14:33:50 +0200 Subject: [PATCH] ADC begin --- Drivers/Include/Driver_Timer.h | 2 ++ Drivers/Sources/Driver_ADC.c | 8 ++++-- Drivers/Sources/Driver_Timer.c | 8 ++++++ GPIO_Test/GPIO_Test.uvoptx | 48 +++++----------------------------- GPIO_Test/GPIO_Test.uvprojx | 30 --------------------- GPIO_Test/Sources/Main.c | 9 +++++-- 6 files changed, 29 insertions(+), 76 deletions(-) diff --git a/Drivers/Include/Driver_Timer.h b/Drivers/Include/Driver_Timer.h index 0a5285c..0c0dd8a 100644 --- a/Drivers/Include/Driver_Timer.h +++ b/Drivers/Include/Driver_Timer.h @@ -14,5 +14,7 @@ typedef struct void MyTimer_Base_Init(MyTimer_Struct_TypeDef * Timer); void MyTimer_Base_Start(TIM_TypeDef * Timer); void MyTimer_Base_Stop(TIM_TypeDef * Timer); +void MyTimer_PWM( MyTimer_Struct_TypeDef * Timer, uint16_t cycle); + #endif diff --git a/Drivers/Sources/Driver_ADC.c b/Drivers/Sources/Driver_ADC.c index 2b98820..f76579e 100644 --- a/Drivers/Sources/Driver_ADC.c +++ b/Drivers/Sources/Driver_ADC.c @@ -4,11 +4,15 @@ void MyADC_Base_Init(MyADC_Struct_TypeDef * ADC){ RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6; //Division par 6 de la clock (72MHz) pour l'ADC (14MHz max) if(ADC->ADC == ADC1){ RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; //Enable Clock ADC1 - ADC1->CR2= ADC_CR2_ADON; //Enable ADC1 + ADC1->CR2 |= ADC_CR2_ADON; //Enable ADC1 ADC1->SQR1&= ADC_SQR1_L; ADC1->SQR3|= 8; - }else{ + }else if(ADC->ADC == ADC2){ + RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; //Enable Clock ADC1 + ADC1->CR2 |= ADC_CR2_ADON; //Enable ADC1 + ADC1->SQR1&= ADC_SQR1_L; + ADC1->SQR3|= 8; } } diff --git a/Drivers/Sources/Driver_Timer.c b/Drivers/Sources/Driver_Timer.c index 338e3e7..397d2b0 100644 --- a/Drivers/Sources/Driver_Timer.c +++ b/Drivers/Sources/Driver_Timer.c @@ -36,3 +36,11 @@ void MyTimer_Base_Stop(TIM_TypeDef * Timer){ } +//------------------------PWM----------------------// +void MyTimer_PWM( MyTimer_Struct_TypeDef * Timer, uint16_t cycle){ + Timer->Timer->CCMR1 &= ~TIM_CCMR1_OC1M_0; //Configuration du canal CH1 + Timer->Timer->CCMR1 |= TIM_CCMR1_OC1M_1| TIM_CCMR1_OC1M_2; // Ajouter 110 aux bits OC1M (registre CCMR1) + + Timer->Timer->CCER |= TIM_CCER_CC1E; // Canal CH1 validé par bit CC1E (registre CCER) + Timer->Timer->CCR1 = (cycle * Timer->ARR) / 100; // Fixer la durée à 20% +} diff --git a/GPIO_Test/GPIO_Test.uvoptx b/GPIO_Test/GPIO_Test.uvoptx index ec4c140..5116dce 100644 --- a/GPIO_Test/GPIO_Test.uvoptx +++ b/GPIO_Test/GPIO_Test.uvoptx @@ -75,7 +75,7 @@ 1 0 - 1 + 0 18 @@ -125,7 +125,7 @@ 0 DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=297,604,718,1031,0)(121=-1,-1,-1,-1,0)(122=546,289,967,716,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=997,343,1591,1094,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=297,604,718,1031,0)(121=-1,-1,-1,-1,0)(122=546,289,967,716,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=708,449,1302,1200,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) 0 @@ -164,7 +164,7 @@ 0 0 0 - 1 + 0 0 0 0 @@ -263,7 +263,7 @@ 1 0 - 0 + 1 18 @@ -422,42 +422,6 @@ 1 3 - 5 - 0 - 0 - 0 - ..\Drivers\Include\Driver_GPIO.h - Driver_GPIO.h - 0 - 0 - - - 1 - 4 - 5 - 0 - 0 - 0 - ..\Drivers\Include\Driver_Timer.h - Driver_Timer.h - 0 - 0 - - - 1 - 5 - 5 - 0 - 0 - 0 - ..\Drivers\Include\Driver_ADC.h - Driver_ADC.h - 0 - 0 - - - 1 - 6 1 0 0 @@ -477,9 +441,9 @@ 0 2 - 7 + 4 1 - 1 + 0 0 0 .\Sources\Main.c diff --git a/GPIO_Test/GPIO_Test.uvprojx b/GPIO_Test/GPIO_Test.uvprojx index cb76430..6f98ab7 100644 --- a/GPIO_Test/GPIO_Test.uvprojx +++ b/GPIO_Test/GPIO_Test.uvprojx @@ -393,21 +393,6 @@ 1 ..\Drivers\Sources\Driver_Timer.c - - Driver_GPIO.h - 5 - ..\Drivers\Include\Driver_GPIO.h - - - Driver_Timer.h - 5 - ..\Drivers\Include\Driver_Timer.h - - - Driver_ADC.h - 5 - ..\Drivers\Include\Driver_ADC.h - Driver_ADC.c 1 @@ -820,21 +805,6 @@ 1 ..\Drivers\Sources\Driver_Timer.c - - Driver_GPIO.h - 5 - ..\Drivers\Include\Driver_GPIO.h - - - Driver_Timer.h - 5 - ..\Drivers\Include\Driver_Timer.h - - - Driver_ADC.h - 5 - ..\Drivers\Include\Driver_ADC.h - Driver_ADC.c 1 diff --git a/GPIO_Test/Sources/Main.c b/GPIO_Test/Sources/Main.c index 3840be6..7bebe97 100644 --- a/GPIO_Test/Sources/Main.c +++ b/GPIO_Test/Sources/Main.c @@ -6,8 +6,8 @@ int main (void){ MyTimer_Struct_TypeDef TIM500ms; //Init Timer 2 et Test TIM500ms.Timer = TIM2; - TIM500ms.PSC = 0xD2F0; // =0.5ms(calculé à partir de la fréquence du micro) - TIM500ms.ARR = 1000; + TIM500ms.PSC = 7200; // =0.5ms(calculé à partir de la fréquence du micro) + TIM500ms.ARR = 5000; MyTimer_Base_Init(&TIM500ms); TIM2->DIER |= 1<< 0 ; //INTERRUPTION PERIPH @@ -16,7 +16,12 @@ int main (void){ NVIC->IP[TIM2_IRQn] = 2<< 4 ; MyTimer_Base_Start(TIM500ms.Timer); + + MyTimer_PWM(&TIM500ms, 50); + + //Boucle infinie de la réponse de la LED à l'état BP + while(1){ } }