From e0ad961c444cdb7ad887a71e62ad3f0f00297f17 Mon Sep 17 00:00:00 2001 From: Cavailles Kevin Date: Mon, 30 Mar 2020 12:18:59 +0200 Subject: [PATCH] maj format --- Activite_1_1/Project.uvoptx | 316 +++++++++++++++++++ Activite_1_1/Project.uvprojx | 437 +++++++++++++++++++++++++++ Activite_1_1/Src/principal.c | 31 ++ Activite_1_1/Src/signalCarre.s | 45 +++ Activite_1_1/Systeme/startup-rvds.s | 335 +++++++++++++++++++++ Activite_2_1/Project.uvoptx | 373 +++++++++++++++++++++++ Activite_2_1/Project.uvprojx | 447 +++++++++++++++++++++++++++ Activite_2_1/Src/calculCarre.s | 30 ++ Activite_2_1/Src/principal.c | 41 +++ Activite_2_1/Src/signalCarre.s | 45 +++ Activite_2_1/Src/table_sin_cos.s | 136 +++++++++ Activite_2_1/Systeme/startup-rvds.s | 335 +++++++++++++++++++++ Activite_2_2/Project.uvoptx | 401 ++++++++++++++++++++++++ Activite_2_2/Project.uvprojx | 452 ++++++++++++++++++++++++++++ Activite_2_2/Src/calcul_dft.s | 64 ++++ Activite_2_2/Src/principal.c | 38 +++ Activite_2_2/Src/signal.s | 76 +++++ Activite_2_2/Src/signalCarre.s | 45 +++ Activite_2_2/Src/table_sin_cos.s | 136 +++++++++ Activite_2_2/Systeme/startup-rvds.s | 335 +++++++++++++++++++++ README.md | 8 +- 21 files changed, 4122 insertions(+), 4 deletions(-) create mode 100644 Activite_1_1/Project.uvoptx create mode 100644 Activite_1_1/Project.uvprojx create mode 100644 Activite_1_1/Src/principal.c create mode 100644 Activite_1_1/Src/signalCarre.s create mode 100644 Activite_1_1/Systeme/startup-rvds.s create mode 100644 Activite_2_1/Project.uvoptx create mode 100644 Activite_2_1/Project.uvprojx create mode 100644 Activite_2_1/Src/calculCarre.s create mode 100644 Activite_2_1/Src/principal.c create mode 100644 Activite_2_1/Src/signalCarre.s create mode 100644 Activite_2_1/Src/table_sin_cos.s create mode 100644 Activite_2_1/Systeme/startup-rvds.s create mode 100644 Activite_2_2/Project.uvoptx create mode 100644 Activite_2_2/Project.uvprojx create mode 100644 Activite_2_2/Src/calcul_dft.s create mode 100644 Activite_2_2/Src/principal.c create mode 100644 Activite_2_2/Src/signal.s create mode 100644 Activite_2_2/Src/signalCarre.s create mode 100644 Activite_2_2/Src/table_sin_cos.s create mode 100644 Activite_2_2/Systeme/startup-rvds.s diff --git a/Activite_1_1/Project.uvoptx b/Activite_1_1/Project.uvoptx new file mode 100644 index 0000000..7955bdb --- /dev/null +++ b/Activite_1_1/Project.uvoptx @@ -0,0 +1,316 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Simu + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=1013,199,1434,626,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=1151,0,1745,751,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U066CFF574857847167074929 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) + + + + + + 0 + 1 + tab + + + 1 + 1 + ReK + + + + + 1 + 10 + 0x08001F28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + 0 + ((portb & 0x00000002) >> 1 & 0x2) >> 1 + FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028706F7274622026203078303030303030303229203E3E2031000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F1000000000000000000000000000000000000000941E0008 + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Sources + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\Src\principal.c + principal.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\Src\signalCarre.s + signalCarre.s + 0 + 0 + + + + + System + 1 + 0 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + .\Systeme\startup-rvds.s + startup-rvds.s + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + ..\GASSP72\gassp72.lib + gassp72.lib + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/Activite_1_1/Project.uvprojx b/Activite_1_1/Project.uvprojx new file mode 100644 index 0000000..2f661f4 --- /dev/null +++ b/Activite_1_1/Project.uvprojx @@ -0,0 +1,437 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Simu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + + + + + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Obj\ + CHTI + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --C99 + STM32F103xB,USE_FULL_LL_DRIVER + + ..\GASSP72 + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Sources + + + principal.c + 1 + .\Src\principal.c + + + signalCarre.s + 2 + .\Src\signalCarre.s + + + + + System + + + startup-rvds.s + 2 + .\Systeme\startup-rvds.s + + + + + Driver + + + gassp72.lib + 4 + ..\GASSP72\gassp72.lib + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/Activite_1_1/Src/principal.c b/Activite_1_1/Src/principal.c new file mode 100644 index 0000000..fc58239 --- /dev/null +++ b/Activite_1_1/Src/principal.c @@ -0,0 +1,31 @@ +#include "gassp72.h" + +extern void timer_callback(void); + +int etat = 0x00020000; + + +int main(void) +{ + + u32 Periode_en_Tck = 7200000; + + // activation de la PLL qui multiplie la fréquence du quartz par 9 + CLOCK_Configure(); + // config port PB1 pour être utilisé en sortie + GPIO_Configure(GPIOB, 1, OUTPUT, OUTPUT_PPULL); + // initialisation du timer 4 + // Periode_en_Tck doit fournir la durée entre interruptions, + // exprimée en périodes Tck de l'horloge principale du STM32 (72 MHz) + Timer_1234_Init_ff( TIM4, Periode_en_Tck ); + // enregistrement de la fonction de traitement de l'interruption timer + // ici le 2 est la priorité, timer_callback est l'adresse de cette fonction, a créér en asm, + // cette fonction doit être conforme à l'AAPCS + Active_IT_Debordement_Timer( TIM4, 2, timer_callback ); + // lancement du timer + Run_Timer( TIM4 ); + while (1) + { + + } +} diff --git a/Activite_1_1/Src/signalCarre.s b/Activite_1_1/Src/signalCarre.s new file mode 100644 index 0000000..dd689cd --- /dev/null +++ b/Activite_1_1/Src/signalCarre.s @@ -0,0 +1,45 @@ +; ce programme est pour l'assembleur RealView (Keil) + thumb + area moncode, code, readonly + export timer_callback + extern etat +; + + +GPIOB_BSRR equ 0x40010C10 ; Bit Set/Reset register + + +timer_callback proc + +; mise a 1 de PB1 + push {lr} + + ldr r1, =etat ;chargement de la variable etat + ldr r1, [r1] + ldr r3, =GPIOB_BSRR + cmp r1, #0x00020000 ;if(etat == 0){etat =1}else{etat=0} + beq eq + bne noteq + +gdc ldr r0, =etat + str r1, [r0] ;on met à jour etat + str r1, [r3] ;et GPIOB_BSRR + +; N.B. le registre BSRR est write-only, on ne peut pas le relire + + pop {lr} + bx lr + endp + +eq + mov r1, #0x00000002 + b gdc + +noteq + mov r1, #0x00020000 + b gdc + + + + end + \ No newline at end of file diff --git a/Activite_1_1/Systeme/startup-rvds.s b/Activite_1_1/Systeme/startup-rvds.s new file mode 100644 index 0000000..e47e649 --- /dev/null +++ b/Activite_1_1/Systeme/startup-rvds.s @@ -0,0 +1,335 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + +; +; Enable UsageFault, MemFault and Busfault interrupts +; +_SHCSR EQU 0xE000ED24 ; SHCSR is located at address 0xE000ED24 + LDR.W R0, =_SHCSR + LDR R1, [R0] ; Read CPACR + ORR R1, R1, #(0x7 << 16) ; Set bits 16,17,18 to enable usagefault, busfault, memfault interrupts + STR R1, [R0] ; Write back the modified value to the CPACR + DSB ; Wait for store to complete + +; +; Set priority grouping (PRIGROUP) in AIRCR to 3 (16 levels for group priority and 0 for subpriority) +; +_AIRCR EQU 0xE000ED0C +_AIRCR_VAL EQU 0x05FA0300 + LDR.W R0, =_AIRCR + LDR.W R1, =_AIRCR_VAL + STR R1,[R0] + +; +; Finaly, jump to main function (void main (void)) +; + LDR R0, =__main + BX R0 + ENDP + +SystemInit PROC + EXPORT SystemInit [WEAK] + BX LR + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Activite_2_1/Project.uvoptx b/Activite_2_1/Project.uvoptx new file mode 100644 index 0000000..979fd46 --- /dev/null +++ b/Activite_2_1/Project.uvoptx @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Simu + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=1013,199,1434,626,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=1151,0,1745,751,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U066CFF574857847167074929 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) + + + + + 0 + 0 + 16 + 1 +
134225476
+ 0 + 0 + 0 + 0 + 0 + 1 + .\Src\principal.c + + \\CHTI\Src/principal.c\16 + + + 1 + 0 + 22 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + .\Src\principal.c + + + + + + + 0 + 1 + tab + + + 1 + 1 + i + + + + + 1 + 10 + 0x08001F28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + 0 + ((portb & 0x00000002) >> 1 & 0x2) >> 1 + FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028706F7274622026203078303030303030303229203E3E2031000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F1000000000000000000000000000000000000000941E0008 + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Sources + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\Src\principal.c + principal.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\Src\calculCarre.s + calculCarre.s + 0 + 0 + + + 1 + 3 + 2 + 0 + 0 + 0 + .\Src\signalCarre.s + signalCarre.s + 0 + 0 + + + + + System + 1 + 0 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + .\Systeme\startup-rvds.s + startup-rvds.s + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + ..\GASSP72\gassp72.lib + gassp72.lib + 0 + 0 + + + 3 + 6 + 2 + 0 + 0 + 0 + .\Src\table_sin_cos.s + table_sin_cos.s + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/Activite_2_1/Project.uvprojx b/Activite_2_1/Project.uvprojx new file mode 100644 index 0000000..ef5d6ad --- /dev/null +++ b/Activite_2_1/Project.uvprojx @@ -0,0 +1,447 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Simu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + + + + + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Obj\ + CHTI + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --C99 + STM32F103xB,USE_FULL_LL_DRIVER + + ..\GASSP72 + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Sources + + + principal.c + 1 + .\Src\principal.c + + + calculCarre.s + 2 + .\Src\calculCarre.s + + + signalCarre.s + 2 + .\Src\signalCarre.s + + + + + System + + + startup-rvds.s + 2 + .\Systeme\startup-rvds.s + + + + + Driver + + + gassp72.lib + 4 + ..\GASSP72\gassp72.lib + + + table_sin_cos.s + 2 + .\Src\table_sin_cos.s + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/Activite_2_1/Src/calculCarre.s b/Activite_2_1/Src/calculCarre.s new file mode 100644 index 0000000..fdacae7 --- /dev/null +++ b/Activite_2_1/Src/calculCarre.s @@ -0,0 +1,30 @@ +; ce programme est pour l'assembleur RealView (Keil) + thumb + area moncode, code, readonly + export calcul_carre + import TabCos + import TabSin +; + +calcul_carre proc + + push {r4} + push {r5} + + ldr r4, =TabSin ;on charge les tables sin et cos + ldr r5, =TabCos + ldrh r2, [r4, r0, LSL #1] ;on récupère la i-ème valeur de chacune des tables + ldrh r0, [r5, r0, LSL #1] + + mul r0, r0 ;on effectue le calcul cos²+sin² + mul r2, r2 + + add r0, r2 + + pop {r5} + pop {r4} + + bx lr + endp + + end \ No newline at end of file diff --git a/Activite_2_1/Src/principal.c b/Activite_2_1/Src/principal.c new file mode 100644 index 0000000..b6f5f6e --- /dev/null +++ b/Activite_2_1/Src/principal.c @@ -0,0 +1,41 @@ +#include "gassp72.h" + +extern void timer_callback(void); + +int etat = 0x00020000; + + +extern int calcul_carre(int); +int tab[64]; + + +int main(void) +{ + + for(int i=0; i<64; i++){ + tab[i]= calcul_carre(i); + } + + + + u32 Periode_en_Tck = 7200000; + + // activation de la PLL qui multiplie la fréquence du quartz par 9 + CLOCK_Configure(); + // config port PB1 pour être utilisé en sortie + GPIO_Configure(GPIOB, 1, OUTPUT, OUTPUT_PPULL); + // initialisation du timer 4 + // Periode_en_Tck doit fournir la durée entre interruptions, + // exprimée en périodes Tck de l'horloge principale du STM32 (72 MHz) + Timer_1234_Init_ff( TIM4, Periode_en_Tck ); + // enregistrement de la fonction de traitement de l'interruption timer + // ici le 2 est la priorité, timer_callback est l'adresse de cette fonction, a créér en asm, + // cette fonction doit être conforme à l'AAPCS + Active_IT_Debordement_Timer( TIM4, 2, timer_callback ); + // lancement du timer + Run_Timer( TIM4 ); + while (1) + { + + } +} diff --git a/Activite_2_1/Src/signalCarre.s b/Activite_2_1/Src/signalCarre.s new file mode 100644 index 0000000..dd689cd --- /dev/null +++ b/Activite_2_1/Src/signalCarre.s @@ -0,0 +1,45 @@ +; ce programme est pour l'assembleur RealView (Keil) + thumb + area moncode, code, readonly + export timer_callback + extern etat +; + + +GPIOB_BSRR equ 0x40010C10 ; Bit Set/Reset register + + +timer_callback proc + +; mise a 1 de PB1 + push {lr} + + ldr r1, =etat ;chargement de la variable etat + ldr r1, [r1] + ldr r3, =GPIOB_BSRR + cmp r1, #0x00020000 ;if(etat == 0){etat =1}else{etat=0} + beq eq + bne noteq + +gdc ldr r0, =etat + str r1, [r0] ;on met à jour etat + str r1, [r3] ;et GPIOB_BSRR + +; N.B. le registre BSRR est write-only, on ne peut pas le relire + + pop {lr} + bx lr + endp + +eq + mov r1, #0x00000002 + b gdc + +noteq + mov r1, #0x00020000 + b gdc + + + + end + \ No newline at end of file diff --git a/Activite_2_1/Src/table_sin_cos.s b/Activite_2_1/Src/table_sin_cos.s new file mode 100644 index 0000000..cd1d094 --- /dev/null +++ b/Activite_2_1/Src/table_sin_cos.s @@ -0,0 +1,136 @@ + AREA Trigo, DATA, READONLY + export TabSin + export TabCos + +TabCos + DCW 32767 ; 0 0x7fff 0.99997 + DCW 32610 ; 1 0x7f62 0.99518 + DCW 32138 ; 2 0x7d8a 0.98077 + DCW 31357 ; 3 0x7a7d 0.95694 + DCW 30274 ; 4 0x7642 0.92389 + DCW 28899 ; 5 0x70e3 0.88193 + DCW 27246 ; 6 0x6a6e 0.83148 + DCW 25330 ; 7 0x62f2 0.77301 + DCW 23170 ; 8 0x5a82 0.70709 + DCW 20788 ; 9 0x5134 0.63440 + DCW 18205 ; 10 0x471d 0.55557 + DCW 15447 ; 11 0x3c57 0.47141 + DCW 12540 ; 12 0x30fc 0.38269 + DCW 9512 ; 13 0x2528 0.29028 + DCW 6393 ; 14 0x18f9 0.19510 + DCW 3212 ; 15 0x0c8c 0.09802 + DCW 0 ; 16 0x0000 0.00000 + DCW -3212 ; 17 0xf374 -0.09802 + DCW -6393 ; 18 0xe707 -0.19510 + DCW -9512 ; 19 0xdad8 -0.29028 + DCW -12540 ; 20 0xcf04 -0.38269 + DCW -15447 ; 21 0xc3a9 -0.47141 + DCW -18205 ; 22 0xb8e3 -0.55557 + DCW -20788 ; 23 0xaecc -0.63440 + DCW -23170 ; 24 0xa57e -0.70709 + DCW -25330 ; 25 0x9d0e -0.77301 + DCW -27246 ; 26 0x9592 -0.83148 + DCW -28899 ; 27 0x8f1d -0.88193 + DCW -30274 ; 28 0x89be -0.92389 + DCW -31357 ; 29 0x8583 -0.95694 + DCW -32138 ; 30 0x8276 -0.98077 + DCW -32610 ; 31 0x809e -0.99518 + DCW -32768 ; 32 0x8000 -1.00000 + DCW -32610 ; 33 0x809e -0.99518 + DCW -32138 ; 34 0x8276 -0.98077 + DCW -31357 ; 35 0x8583 -0.95694 + DCW -30274 ; 36 0x89be -0.92389 + DCW -28899 ; 37 0x8f1d -0.88193 + DCW -27246 ; 38 0x9592 -0.83148 + DCW -25330 ; 39 0x9d0e -0.77301 + DCW -23170 ; 40 0xa57e -0.70709 + DCW -20788 ; 41 0xaecc -0.63440 + DCW -18205 ; 42 0xb8e3 -0.55557 + DCW -15447 ; 43 0xc3a9 -0.47141 + DCW -12540 ; 44 0xcf04 -0.38269 + DCW -9512 ; 45 0xdad8 -0.29028 + DCW -6393 ; 46 0xe707 -0.19510 + DCW -3212 ; 47 0xf374 -0.09802 + DCW 0 ; 48 0x0000 0.00000 + DCW 3212 ; 49 0x0c8c 0.09802 + DCW 6393 ; 50 0x18f9 0.19510 + DCW 9512 ; 51 0x2528 0.29028 + DCW 12540 ; 52 0x30fc 0.38269 + DCW 15447 ; 53 0x3c57 0.47141 + DCW 18205 ; 54 0x471d 0.55557 + DCW 20788 ; 55 0x5134 0.63440 + DCW 23170 ; 56 0x5a82 0.70709 + DCW 25330 ; 57 0x62f2 0.77301 + DCW 27246 ; 58 0x6a6e 0.83148 + DCW 28899 ; 59 0x70e3 0.88193 + DCW 30274 ; 60 0x7642 0.92389 + DCW 31357 ; 61 0x7a7d 0.95694 + DCW 32138 ; 62 0x7d8a 0.98077 + DCW 32610 ; 63 0x7f62 0.99518 +TabSin + DCW 0 ; 0 0x0000 0.00000 + DCW 3212 ; 1 0x0c8c 0.09802 + DCW 6393 ; 2 0x18f9 0.19510 + DCW 9512 ; 3 0x2528 0.29028 + DCW 12540 ; 4 0x30fc 0.38269 + DCW 15447 ; 5 0x3c57 0.47141 + DCW 18205 ; 6 0x471d 0.55557 + DCW 20788 ; 7 0x5134 0.63440 + DCW 23170 ; 8 0x5a82 0.70709 + DCW 25330 ; 9 0x62f2 0.77301 + DCW 27246 ; 10 0x6a6e 0.83148 + DCW 28899 ; 11 0x70e3 0.88193 + DCW 30274 ; 12 0x7642 0.92389 + DCW 31357 ; 13 0x7a7d 0.95694 + DCW 32138 ; 14 0x7d8a 0.98077 + DCW 32610 ; 15 0x7f62 0.99518 + DCW 32767 ; 16 0x7fff 0.99997 + DCW 32610 ; 17 0x7f62 0.99518 + DCW 32138 ; 18 0x7d8a 0.98077 + DCW 31357 ; 19 0x7a7d 0.95694 + DCW 30274 ; 20 0x7642 0.92389 + DCW 28899 ; 21 0x70e3 0.88193 + DCW 27246 ; 22 0x6a6e 0.83148 + DCW 25330 ; 23 0x62f2 0.77301 + DCW 23170 ; 24 0x5a82 0.70709 + DCW 20788 ; 25 0x5134 0.63440 + DCW 18205 ; 26 0x471d 0.55557 + DCW 15447 ; 27 0x3c57 0.47141 + DCW 12540 ; 28 0x30fc 0.38269 + DCW 9512 ; 29 0x2528 0.29028 + DCW 6393 ; 30 0x18f9 0.19510 + DCW 3212 ; 31 0x0c8c 0.09802 + DCW 0 ; 32 0x0000 0.00000 + DCW -3212 ; 33 0xf374 -0.09802 + DCW -6393 ; 34 0xe707 -0.19510 + DCW -9512 ; 35 0xdad8 -0.29028 + DCW -12540 ; 36 0xcf04 -0.38269 + DCW -15447 ; 37 0xc3a9 -0.47141 + DCW -18205 ; 38 0xb8e3 -0.55557 + DCW -20788 ; 39 0xaecc -0.63440 + DCW -23170 ; 40 0xa57e -0.70709 + DCW -25330 ; 41 0x9d0e -0.77301 + DCW -27246 ; 42 0x9592 -0.83148 + DCW -28899 ; 43 0x8f1d -0.88193 + DCW -30274 ; 44 0x89be -0.92389 + DCW -31357 ; 45 0x8583 -0.95694 + DCW -32138 ; 46 0x8276 -0.98077 + DCW -32610 ; 47 0x809e -0.99518 + DCW -32768 ; 48 0x8000 -1.00000 + DCW -32610 ; 49 0x809e -0.99518 + DCW -32138 ; 50 0x8276 -0.98077 + DCW -31357 ; 51 0x8583 -0.95694 + DCW -30274 ; 52 0x89be -0.92389 + DCW -28899 ; 53 0x8f1d -0.88193 + DCW -27246 ; 54 0x9592 -0.83148 + DCW -25330 ; 55 0x9d0e -0.77301 + DCW -23170 ; 56 0xa57e -0.70709 + DCW -20788 ; 57 0xaecc -0.63440 + DCW -18205 ; 58 0xb8e3 -0.55557 + DCW -15447 ; 59 0xc3a9 -0.47141 + DCW -12540 ; 60 0xcf04 -0.38269 + DCW -9512 ; 61 0xdad8 -0.29028 + DCW -6393 ; 62 0xe707 -0.19510 + DCW -3212 ; 63 0xf374 -0.09802 + + END diff --git a/Activite_2_1/Systeme/startup-rvds.s b/Activite_2_1/Systeme/startup-rvds.s new file mode 100644 index 0000000..e47e649 --- /dev/null +++ b/Activite_2_1/Systeme/startup-rvds.s @@ -0,0 +1,335 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + +; +; Enable UsageFault, MemFault and Busfault interrupts +; +_SHCSR EQU 0xE000ED24 ; SHCSR is located at address 0xE000ED24 + LDR.W R0, =_SHCSR + LDR R1, [R0] ; Read CPACR + ORR R1, R1, #(0x7 << 16) ; Set bits 16,17,18 to enable usagefault, busfault, memfault interrupts + STR R1, [R0] ; Write back the modified value to the CPACR + DSB ; Wait for store to complete + +; +; Set priority grouping (PRIGROUP) in AIRCR to 3 (16 levels for group priority and 0 for subpriority) +; +_AIRCR EQU 0xE000ED0C +_AIRCR_VAL EQU 0x05FA0300 + LDR.W R0, =_AIRCR + LDR.W R1, =_AIRCR_VAL + STR R1,[R0] + +; +; Finaly, jump to main function (void main (void)) +; + LDR R0, =__main + BX R0 + ENDP + +SystemInit PROC + EXPORT SystemInit [WEAK] + BX LR + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Activite_2_2/Project.uvoptx b/Activite_2_2/Project.uvoptx new file mode 100644 index 0000000..321d6fc --- /dev/null +++ b/Activite_2_2/Project.uvoptx @@ -0,0 +1,401 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Simu + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=1013,199,1434,626,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=1151,0,1745,751,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U066CFF574857847167074929 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) + + + + + 0 + 0 + 18 + 1 +
134225484
+ 0 + 0 + 0 + 0 + 0 + 1 + .\Src\principal.c + + \\CHTI\Src/principal.c\18 + + + 1 + 0 + 31 + 1 +
134225568
+ 0 + 0 + 0 + 0 + 0 + 1 + .\Src\calcul_dft.s + + \\CHTI\Src/calcul_dft.s\31 + + + 2 + 0 + 19 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + .\Src\principal.c + + + + + + + 0 + 1 + tab + + + 1 + 1 + res_dft + + + + + 1 + 10 + 0x08001F28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + 0 + ((portb & 0x00000002) >> 1 & 0x2) >> 1 + FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028706F7274622026203078303030303030303229203E3E2031000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F1000000000000000000000000000000000000000941E0008 + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Sources + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\Src\principal.c + principal.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\Src\calcul_dft.s + calcul_dft.s + 0 + 0 + + + 1 + 3 + 2 + 0 + 0 + 0 + .\Src\signalCarre.s + signalCarre.s + 0 + 0 + + + + + System + 1 + 0 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + .\Systeme\startup-rvds.s + startup-rvds.s + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + ..\GASSP72\gassp72.lib + gassp72.lib + 0 + 0 + + + 3 + 6 + 2 + 0 + 0 + 0 + .\Src\table_sin_cos.s + table_sin_cos.s + 0 + 0 + + + 3 + 7 + 2 + 0 + 0 + 0 + .\Src\signal.s + signal.s + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/Activite_2_2/Project.uvprojx b/Activite_2_2/Project.uvprojx new file mode 100644 index 0000000..c8979e5 --- /dev/null +++ b/Activite_2_2/Project.uvprojx @@ -0,0 +1,452 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Simu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + + + + + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Obj\ + CHTI + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --C99 + STM32F103xB,USE_FULL_LL_DRIVER + + ..\GASSP72 + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Sources + + + principal.c + 1 + .\Src\principal.c + + + calcul_dft.s + 2 + .\Src\calcul_dft.s + + + signalCarre.s + 2 + .\Src\signalCarre.s + + + + + System + + + startup-rvds.s + 2 + .\Systeme\startup-rvds.s + + + + + Driver + + + gassp72.lib + 4 + ..\GASSP72\gassp72.lib + + + table_sin_cos.s + 2 + .\Src\table_sin_cos.s + + + signal.s + 2 + .\Src\signal.s + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/Activite_2_2/Src/calcul_dft.s b/Activite_2_2/Src/calcul_dft.s new file mode 100644 index 0000000..45db3e4 --- /dev/null +++ b/Activite_2_2/Src/calcul_dft.s @@ -0,0 +1,64 @@ +; ce programme est pour l'assembleur RealView (Keil) + thumb + area moncode, code, readonly + export calcul_dft_moitie + export calcul_dft + import TabCos + import TabSin +; + + +calcul_dft proc + push {lr} + + ;push {r1} + + ldr r2, =TabCos + bl calcul_dft_moitie ;recuperation Re(k) dans r0 + + ;pop {r1} + + ;push {r0} ;mise de Re(k) dans la pile + + ;ldr r2, =TabSin + ;bl calcul_dft_moitie ;mise de -Im(k) dans r0 + + ;mul r0, r0, r0 ;(-Im(k))² + + ;pop {r1} ;mise de Re(k) dans r1 + ;mul r1, r1, r1 ;Re(k)² + ;add r0, r0, r1 ;addition de Re(k)² + Im(k)² + pop {lr} + bx lr + endp + +calcul_dft_moitie proc + push {lr,r4-r6} + + + mov r4, r0 + mov r5, r2 + mov r6, r1 + + mov r3, #0 ;i=0 dans r3 + mov r0, #0 ;resultat de la somme dans r0 +boucle ldrh r2, [r4, r3, LSL #1] ;chargement de x(i) + + mul r1, r3, r6 ;multiplication ik dans r1 + and r1, r1, #63 ;modulo de ik par 64 + + ldrh r1, [r5, r1, LSL #1] ;chargement de cos(ik..) + mul r12, r1, r2 ;multiplication x(i)cos(ik..) + add r0, r0, r12 ;ajout dans la somme + add r3, #1 ;incrementation de i + cmp r3, #64 ;test de i + bne boucle + beq sortie + +sortie + + pop {lr,r4-r6} + bx lr + endp + + end \ No newline at end of file diff --git a/Activite_2_2/Src/principal.c b/Activite_2_2/Src/principal.c new file mode 100644 index 0000000..79ac973 --- /dev/null +++ b/Activite_2_2/Src/principal.c @@ -0,0 +1,38 @@ +#include "gassp72.h" + +extern void timer_callback(void); +extern short TabSig[]; +int etat = 0x00020000; + + +extern int calcul_carre(int); +extern int calcul_dft(short *, int); +int res_dft; + + +int main(void) +{ + res_dft = calcul_dft(TabSig,1); + + + u32 Periode_en_Tck = 7200000; + + // activation de la PLL qui multiplie la fréquence du quartz par 9 + CLOCK_Configure(); + // config port PB1 pour être utilisé en sortie + GPIO_Configure(GPIOB, 1, OUTPUT, OUTPUT_PPULL); + // initialisation du timer 4 + // Periode_en_Tck doit fournir la durée entre interruptions, + // exprimée en périodes Tck de l'horloge principale du STM32 (72 MHz) + Timer_1234_Init_ff( TIM4, Periode_en_Tck ); + // enregistrement de la fonction de traitement de l'interruption timer + // ici le 2 est la priorité, timer_callback est l'adresse de cette fonction, a créér en asm, + // cette fonction doit être conforme à l'AAPCS + Active_IT_Debordement_Timer( TIM4, 2, timer_callback ); + // lancement du timer + Run_Timer( TIM4 ); + while (1) + { + + } +} diff --git a/Activite_2_2/Src/signal.s b/Activite_2_2/Src/signal.s new file mode 100644 index 0000000..46ce7e5 --- /dev/null +++ b/Activite_2_2/Src/signal.s @@ -0,0 +1,76 @@ + AREA Signal, DATA, READONLY + export TabSig +; fonction cosinus, frequence relative 1, phase -45 degres, amplitude max +; valeurs attendues pour k = 1 : +; Re 0x5A82562C env +sqrt(0.5) * 2^31 +; Im 0x5A82562C env +sqrt(0.5) * 2^31 +; M2 0x3FFFCDE5 env 2^30 +; pour 1 < k < 63 +; M2 < 0x0000000F + +TabSig + dcw 0x0da8 ; 0 3496 0.85352 + dcw 0x0e2f ; 1 3631 0.88647 + dcw 0x0ea7 ; 2 3751 0.91577 + dcw 0x0f0e ; 3 3854 0.94092 + dcw 0x0f64 ; 4 3940 0.96191 + dcw 0x0fa8 ; 5 4008 0.97852 + dcw 0x0fd9 ; 6 4057 0.99048 + dcw 0x0ff6 ; 7 4086 0.99756 + dcw 0x0fff ; 8 4095 0.99976 + dcw 0x0ff6 ; 9 4086 0.99756 + dcw 0x0fd9 ; 10 4057 0.99048 + dcw 0x0fa8 ; 11 4008 0.97852 + dcw 0x0f64 ; 12 3940 0.96191 + dcw 0x0f0e ; 13 3854 0.94092 + dcw 0x0ea7 ; 14 3751 0.91577 + dcw 0x0e2f ; 15 3631 0.88647 + dcw 0x0da8 ; 16 3496 0.85352 + dcw 0x0d13 ; 17 3347 0.81714 + dcw 0x0c72 ; 18 3186 0.77783 + dcw 0x0bc5 ; 19 3013 0.73560 + dcw 0x0b10 ; 20 2832 0.69141 + dcw 0x0a53 ; 21 2643 0.64526 + dcw 0x0990 ; 22 2448 0.59766 + dcw 0x08c9 ; 23 2249 0.54907 + dcw 0x0800 ; 24 2048 0.50000 + dcw 0x0737 ; 25 1847 0.45093 + dcw 0x0670 ; 26 1648 0.40234 + dcw 0x05ad ; 27 1453 0.35474 + dcw 0x04f0 ; 28 1264 0.30859 + dcw 0x043b ; 29 1083 0.26440 + dcw 0x038e ; 30 910 0.22217 + dcw 0x02ed ; 31 749 0.18286 + dcw 0x0258 ; 32 600 0.14648 + dcw 0x01d1 ; 33 465 0.11353 + dcw 0x0159 ; 34 345 0.08423 + dcw 0x00f2 ; 35 242 0.05908 + dcw 0x009c ; 36 156 0.03809 + dcw 0x0058 ; 37 88 0.02148 + dcw 0x0027 ; 38 39 0.00952 + dcw 0x000a ; 39 10 0.00244 + dcw 0x0000 ; 40 0 0.00000 + dcw 0x000a ; 41 10 0.00244 + dcw 0x0027 ; 42 39 0.00952 + dcw 0x0058 ; 43 88 0.02148 + dcw 0x009c ; 44 156 0.03809 + dcw 0x00f2 ; 45 242 0.05908 + dcw 0x0159 ; 46 345 0.08423 + dcw 0x01d1 ; 47 465 0.11353 + dcw 0x0258 ; 48 600 0.14648 + dcw 0x02ed ; 49 749 0.18286 + dcw 0x038e ; 50 910 0.22217 + dcw 0x043b ; 51 1083 0.26440 + dcw 0x04f0 ; 52 1264 0.30859 + dcw 0x05ad ; 53 1453 0.35474 + dcw 0x0670 ; 54 1648 0.40234 + dcw 0x0737 ; 55 1847 0.45093 + dcw 0x0800 ; 56 2048 0.50000 + dcw 0x08c9 ; 57 2249 0.54907 + dcw 0x0990 ; 58 2448 0.59766 + dcw 0x0a53 ; 59 2643 0.64526 + dcw 0x0b10 ; 60 2832 0.69141 + dcw 0x0bc5 ; 61 3013 0.73560 + dcw 0x0c72 ; 62 3186 0.77783 + dcw 0x0d13 ; 63 3347 0.81714 + end diff --git a/Activite_2_2/Src/signalCarre.s b/Activite_2_2/Src/signalCarre.s new file mode 100644 index 0000000..dd689cd --- /dev/null +++ b/Activite_2_2/Src/signalCarre.s @@ -0,0 +1,45 @@ +; ce programme est pour l'assembleur RealView (Keil) + thumb + area moncode, code, readonly + export timer_callback + extern etat +; + + +GPIOB_BSRR equ 0x40010C10 ; Bit Set/Reset register + + +timer_callback proc + +; mise a 1 de PB1 + push {lr} + + ldr r1, =etat ;chargement de la variable etat + ldr r1, [r1] + ldr r3, =GPIOB_BSRR + cmp r1, #0x00020000 ;if(etat == 0){etat =1}else{etat=0} + beq eq + bne noteq + +gdc ldr r0, =etat + str r1, [r0] ;on met à jour etat + str r1, [r3] ;et GPIOB_BSRR + +; N.B. le registre BSRR est write-only, on ne peut pas le relire + + pop {lr} + bx lr + endp + +eq + mov r1, #0x00000002 + b gdc + +noteq + mov r1, #0x00020000 + b gdc + + + + end + \ No newline at end of file diff --git a/Activite_2_2/Src/table_sin_cos.s b/Activite_2_2/Src/table_sin_cos.s new file mode 100644 index 0000000..cd1d094 --- /dev/null +++ b/Activite_2_2/Src/table_sin_cos.s @@ -0,0 +1,136 @@ + AREA Trigo, DATA, READONLY + export TabSin + export TabCos + +TabCos + DCW 32767 ; 0 0x7fff 0.99997 + DCW 32610 ; 1 0x7f62 0.99518 + DCW 32138 ; 2 0x7d8a 0.98077 + DCW 31357 ; 3 0x7a7d 0.95694 + DCW 30274 ; 4 0x7642 0.92389 + DCW 28899 ; 5 0x70e3 0.88193 + DCW 27246 ; 6 0x6a6e 0.83148 + DCW 25330 ; 7 0x62f2 0.77301 + DCW 23170 ; 8 0x5a82 0.70709 + DCW 20788 ; 9 0x5134 0.63440 + DCW 18205 ; 10 0x471d 0.55557 + DCW 15447 ; 11 0x3c57 0.47141 + DCW 12540 ; 12 0x30fc 0.38269 + DCW 9512 ; 13 0x2528 0.29028 + DCW 6393 ; 14 0x18f9 0.19510 + DCW 3212 ; 15 0x0c8c 0.09802 + DCW 0 ; 16 0x0000 0.00000 + DCW -3212 ; 17 0xf374 -0.09802 + DCW -6393 ; 18 0xe707 -0.19510 + DCW -9512 ; 19 0xdad8 -0.29028 + DCW -12540 ; 20 0xcf04 -0.38269 + DCW -15447 ; 21 0xc3a9 -0.47141 + DCW -18205 ; 22 0xb8e3 -0.55557 + DCW -20788 ; 23 0xaecc -0.63440 + DCW -23170 ; 24 0xa57e -0.70709 + DCW -25330 ; 25 0x9d0e -0.77301 + DCW -27246 ; 26 0x9592 -0.83148 + DCW -28899 ; 27 0x8f1d -0.88193 + DCW -30274 ; 28 0x89be -0.92389 + DCW -31357 ; 29 0x8583 -0.95694 + DCW -32138 ; 30 0x8276 -0.98077 + DCW -32610 ; 31 0x809e -0.99518 + DCW -32768 ; 32 0x8000 -1.00000 + DCW -32610 ; 33 0x809e -0.99518 + DCW -32138 ; 34 0x8276 -0.98077 + DCW -31357 ; 35 0x8583 -0.95694 + DCW -30274 ; 36 0x89be -0.92389 + DCW -28899 ; 37 0x8f1d -0.88193 + DCW -27246 ; 38 0x9592 -0.83148 + DCW -25330 ; 39 0x9d0e -0.77301 + DCW -23170 ; 40 0xa57e -0.70709 + DCW -20788 ; 41 0xaecc -0.63440 + DCW -18205 ; 42 0xb8e3 -0.55557 + DCW -15447 ; 43 0xc3a9 -0.47141 + DCW -12540 ; 44 0xcf04 -0.38269 + DCW -9512 ; 45 0xdad8 -0.29028 + DCW -6393 ; 46 0xe707 -0.19510 + DCW -3212 ; 47 0xf374 -0.09802 + DCW 0 ; 48 0x0000 0.00000 + DCW 3212 ; 49 0x0c8c 0.09802 + DCW 6393 ; 50 0x18f9 0.19510 + DCW 9512 ; 51 0x2528 0.29028 + DCW 12540 ; 52 0x30fc 0.38269 + DCW 15447 ; 53 0x3c57 0.47141 + DCW 18205 ; 54 0x471d 0.55557 + DCW 20788 ; 55 0x5134 0.63440 + DCW 23170 ; 56 0x5a82 0.70709 + DCW 25330 ; 57 0x62f2 0.77301 + DCW 27246 ; 58 0x6a6e 0.83148 + DCW 28899 ; 59 0x70e3 0.88193 + DCW 30274 ; 60 0x7642 0.92389 + DCW 31357 ; 61 0x7a7d 0.95694 + DCW 32138 ; 62 0x7d8a 0.98077 + DCW 32610 ; 63 0x7f62 0.99518 +TabSin + DCW 0 ; 0 0x0000 0.00000 + DCW 3212 ; 1 0x0c8c 0.09802 + DCW 6393 ; 2 0x18f9 0.19510 + DCW 9512 ; 3 0x2528 0.29028 + DCW 12540 ; 4 0x30fc 0.38269 + DCW 15447 ; 5 0x3c57 0.47141 + DCW 18205 ; 6 0x471d 0.55557 + DCW 20788 ; 7 0x5134 0.63440 + DCW 23170 ; 8 0x5a82 0.70709 + DCW 25330 ; 9 0x62f2 0.77301 + DCW 27246 ; 10 0x6a6e 0.83148 + DCW 28899 ; 11 0x70e3 0.88193 + DCW 30274 ; 12 0x7642 0.92389 + DCW 31357 ; 13 0x7a7d 0.95694 + DCW 32138 ; 14 0x7d8a 0.98077 + DCW 32610 ; 15 0x7f62 0.99518 + DCW 32767 ; 16 0x7fff 0.99997 + DCW 32610 ; 17 0x7f62 0.99518 + DCW 32138 ; 18 0x7d8a 0.98077 + DCW 31357 ; 19 0x7a7d 0.95694 + DCW 30274 ; 20 0x7642 0.92389 + DCW 28899 ; 21 0x70e3 0.88193 + DCW 27246 ; 22 0x6a6e 0.83148 + DCW 25330 ; 23 0x62f2 0.77301 + DCW 23170 ; 24 0x5a82 0.70709 + DCW 20788 ; 25 0x5134 0.63440 + DCW 18205 ; 26 0x471d 0.55557 + DCW 15447 ; 27 0x3c57 0.47141 + DCW 12540 ; 28 0x30fc 0.38269 + DCW 9512 ; 29 0x2528 0.29028 + DCW 6393 ; 30 0x18f9 0.19510 + DCW 3212 ; 31 0x0c8c 0.09802 + DCW 0 ; 32 0x0000 0.00000 + DCW -3212 ; 33 0xf374 -0.09802 + DCW -6393 ; 34 0xe707 -0.19510 + DCW -9512 ; 35 0xdad8 -0.29028 + DCW -12540 ; 36 0xcf04 -0.38269 + DCW -15447 ; 37 0xc3a9 -0.47141 + DCW -18205 ; 38 0xb8e3 -0.55557 + DCW -20788 ; 39 0xaecc -0.63440 + DCW -23170 ; 40 0xa57e -0.70709 + DCW -25330 ; 41 0x9d0e -0.77301 + DCW -27246 ; 42 0x9592 -0.83148 + DCW -28899 ; 43 0x8f1d -0.88193 + DCW -30274 ; 44 0x89be -0.92389 + DCW -31357 ; 45 0x8583 -0.95694 + DCW -32138 ; 46 0x8276 -0.98077 + DCW -32610 ; 47 0x809e -0.99518 + DCW -32768 ; 48 0x8000 -1.00000 + DCW -32610 ; 49 0x809e -0.99518 + DCW -32138 ; 50 0x8276 -0.98077 + DCW -31357 ; 51 0x8583 -0.95694 + DCW -30274 ; 52 0x89be -0.92389 + DCW -28899 ; 53 0x8f1d -0.88193 + DCW -27246 ; 54 0x9592 -0.83148 + DCW -25330 ; 55 0x9d0e -0.77301 + DCW -23170 ; 56 0xa57e -0.70709 + DCW -20788 ; 57 0xaecc -0.63440 + DCW -18205 ; 58 0xb8e3 -0.55557 + DCW -15447 ; 59 0xc3a9 -0.47141 + DCW -12540 ; 60 0xcf04 -0.38269 + DCW -9512 ; 61 0xdad8 -0.29028 + DCW -6393 ; 62 0xe707 -0.19510 + DCW -3212 ; 63 0xf374 -0.09802 + + END diff --git a/Activite_2_2/Systeme/startup-rvds.s b/Activite_2_2/Systeme/startup-rvds.s new file mode 100644 index 0000000..e47e649 --- /dev/null +++ b/Activite_2_2/Systeme/startup-rvds.s @@ -0,0 +1,335 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + +; +; Enable UsageFault, MemFault and Busfault interrupts +; +_SHCSR EQU 0xE000ED24 ; SHCSR is located at address 0xE000ED24 + LDR.W R0, =_SHCSR + LDR R1, [R0] ; Read CPACR + ORR R1, R1, #(0x7 << 16) ; Set bits 16,17,18 to enable usagefault, busfault, memfault interrupts + STR R1, [R0] ; Write back the modified value to the CPACR + DSB ; Wait for store to complete + +; +; Set priority grouping (PRIGROUP) in AIRCR to 3 (16 levels for group priority and 0 for subpriority) +; +_AIRCR EQU 0xE000ED0C +_AIRCR_VAL EQU 0x05FA0300 + LDR.W R0, =_AIRCR + LDR.W R1, =_AIRCR_VAL + STR R1,[R0] + +; +; Finaly, jump to main function (void main (void)) +; + LDR R0, =__main + BX R0 + ENDP + +SystemInit PROC + EXPORT SystemInit [WEAK] + BX LR + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/README.md b/README.md index dad711b..d5901fc 100644 --- a/README.md +++ b/README.md @@ -4,8 +4,8 @@ Binôme : Cavailles Kévin / Dumaz Clément Classe : 3_MIC_C -2.2 Calcul DFT : En cours +Activite_1_1 : Validé +Activite_2_1 : Validé +Activite_2_2 : En cours + -Ce qui a été fait : -- 1.1 Signal carré de précision -- 2.1 Préliminaire : Tables trigo