67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
#include "stm32f10x.h"
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#include "PWM.h"
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void MyTimer_PWM(TIM_TypeDef *Timer, char Channel) { // Activer PWM sur un output
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// preload
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Timer->CR1 |= TIM_CR1_ARPE;
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switch (Channel) {
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case 1:
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// Config o channel 1 in "PWM Mode 1" and enable preload of CCR1
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Timer->CCMR1 &= ~TIM_CCMR1_OC1M; // clean bit modes
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Timer->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; // Mode PWM 1
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Timer->CCMR1 |= TIM_CCMR1_OC1PE; // enable preload
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// enable exit 1 (Output enable)
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Timer->CCER |= TIM_CCER_CC1E;
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break;
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case 2:
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Timer->CCMR1 &= ~TIM_CCMR1_OC2M;
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Timer->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1;
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Timer->CCMR1 |= TIM_CCMR1_OC2PE;
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Timer->CCER |= TIM_CCER_CC2E;
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break;
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case 3:
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Timer->CCMR2 &= ~TIM_CCMR2_OC3M;
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Timer->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1;
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Timer->CCMR2 |= TIM_CCMR2_OC3PE;
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Timer->CCER |= TIM_CCER_CC3E;
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break;
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case 4:
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Timer->CCMR2 &= ~TIM_CCMR2_OC4M;
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Timer->CCMR2 |= TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1;
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Timer->CCMR2 |= TIM_CCMR2_OC4PE;
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Timer->CCER |= TIM_CCER_CC4E;
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break;
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}
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// special case(specific timers)
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if (Timer == TIM1 || Timer == TIM8) {
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Timer->BDTR |= TIM_BDTR_MOE;
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}
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}
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void MyTimer_Set_DutyCycle(TIM_TypeDef *Timer, char Channel, float DutyCycle_Percent) {
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unsigned short ccr_value;
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// Percentages between 0 and 100
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if (DutyCycle_Percent > 100.0) DutyCycle_Percent = 100.0;
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if (DutyCycle_Percent < 0.0) DutyCycle_Percent = 0.0;
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// calcule of crr
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ccr_value = (unsigned short)((DutyCycle_Percent / 100.0) * (Timer->ARR));
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// Assigner le valaur pour le registre de comparison pour le channel qui est pertient
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switch (Channel) {
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case 1:
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Timer->CCR1 = ccr_value;
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break;
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case 2:
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Timer->CCR2 = ccr_value;
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break;
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case 3:
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Timer->CCR3 = ccr_value;
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break;
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case 4:
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Timer->CCR4 = ccr_value;
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break;
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}
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}
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