diff --git a/NicolasYarno/MyGPIO.c b/NicolasYarno/MyGPIO.c
new file mode 100644
index 0000000..27c0a82
--- /dev/null
+++ b/NicolasYarno/MyGPIO.c
@@ -0,0 +1,39 @@
+#include "stm32f10x.h"
+
+
+void GPIO_configure(GPIO_TypeDef *GPIO ,int pin, char mode){
+	if (mode == 1) { // output push pull 2MHZ
+		GPIO->CRL = (GPIO->CRL & ~(0xF<<pin*4)) | (0x2<<pin*4); 
+	}
+	if (mode == 2) { // input pullup 
+		GPIO->CRL = (GPIO->CRL & ~(0xF<<pin*4)) | (0x8<<pin*4); 
+		GPIO->ODR |= (1<<pin);
+	}
+}
+
+
+
+void allume_led (GPIO_TypeDef *GPIO , char GPIO_Pin){
+	GPIO->ODR |= (1<<GPIO_Pin); 
+};
+
+void eteindre_led (GPIO_TypeDef *GPIO , char GPIO_Pin){
+	GPIO->ODR &= ~(1<<GPIO_Pin); 
+};
+
+void toggle_pin (GPIO_TypeDef *GPIO , char GPIO_Pin){
+	if ((GPIO->ODR & (1<<GPIO_Pin)) == 0)
+		GPIO->ODR |= (1<<GPIO_Pin);  
+	else
+		GPIO->ODR &= ~(1<<GPIO_Pin); 
+};
+
+
+int GPIO_bouton_read (GPIO_TypeDef *GPIO , char GPIO_Pin ){
+	if ((GPIO->IDR & (1<<GPIO_Pin)) == 0) {
+	return 0;
+	}
+		else{
+			return 1;
+	}
+};
diff --git a/NicolasYarno/MyPWM.c b/NicolasYarno/MyPWM.c
new file mode 100644
index 0000000..06d7405
Binary files /dev/null and b/NicolasYarno/MyPWM.c differ
diff --git a/NicolasYarno/MyUart.c b/NicolasYarno/MyUart.c
new file mode 100644
index 0000000..3645750
--- /dev/null
+++ b/NicolasYarno/MyUart.c
@@ -0,0 +1,6 @@
+#include "stm32f10x.h"
+
+
+void My_USART_Config(USART_TypeDef* USARTx, uint32_t baudrate) {
+
+    uint32_t f_clk = 0;
\ No newline at end of file
diff --git a/NicolasYarno/Mytimer.c b/NicolasYarno/Mytimer.c
new file mode 100644
index 0000000..0cecd25
--- /dev/null
+++ b/NicolasYarno/Mytimer.c
@@ -0,0 +1,61 @@
+#include "stm32f10x.h"
+
+void MyTimer_Base_Init (TIM_TypeDef * Timer , unsigned short ValARR , unsigned short ValPSC ){
+	Timer->ARR = ValARR; 
+  Timer->PSC = ValPSC;
+};
+/*
+TIM2_CH1
+PWM mode 2 by writing OC1M=’111’ in the TIMx_CCMR1
+
+he PWM mode can be selected independently on each channel (one PWM per OCx
+output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
+TIMx_CCMRx register. You must enable the corresponding preload register by setting the
+OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
+upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register
+
+110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
+else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
+TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
+
+void MyTimer_PWM( TIM_TypeDef * Timer, char Channel){ 
+Timer->CCMR1
+	
+	
+	
+};
+*/
+
+
+void (*pFnc) (void);
+
+void MyTimer_ActiveIT (TIM_TypeDef * Timer , char prio, void (*IT_function)(void)){
+		Timer->DIER |= TIM_DIER_UIE;
+    IRQn_Type IRQn;
+    if (Timer == TIM2) IRQn = TIM2_IRQn;
+    else if (Timer == TIM3) IRQn = TIM3_IRQn;
+    else if (Timer == TIM4) IRQn = TIM4_IRQn;
+	NVIC_EnableIRQ(IRQn);
+	NVIC_SetPriority(IRQn, prio);
+	
+	pFnc = IT_function;
+};
+
+
+void TIM2_IRQHandler(void){	
+	if (pFnc != 0){
+		(*pFnc) (); /* appel indirect de la fonction */
+	}
+	TIM2->SR &= ~TIM_SR_UIF;
+};
+
+
+void TIM3_IRQHandler(void){
+	TIM3->SR &= ~TIM_SR_UIF;
+
+};
+
+void TIM4_IRQHandler(void){
+	TIM4->SR &= ~TIM_SR_UIF;
+
+};