129 lines
2.8 KiB
C
129 lines
2.8 KiB
C
#include "Driver_Timer.h"
|
|
#include "stm32f10x.h"
|
|
#include "stdio.h"
|
|
/* Timer init function */
|
|
void MyTimer_Base_Init(MyTimer_Struct_TypeDef * Timer)
|
|
{
|
|
/* Reset the selected Timer */
|
|
if(Timer->Timer == TIM1)
|
|
{
|
|
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
|
|
}
|
|
else if(Timer->Timer == TIM2)
|
|
{
|
|
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
|
|
}
|
|
else if(Timer->Timer == TIM3)
|
|
{
|
|
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
|
|
}
|
|
else if(Timer->Timer == TIM4)
|
|
{
|
|
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
|
|
}
|
|
|
|
Timer->Timer->PSC = Timer->PSC;
|
|
Timer->Timer->ARR = Timer->ARR;
|
|
}
|
|
|
|
|
|
void MyTimer_Start(MyTimer_Struct_TypeDef * Timer)
|
|
{
|
|
Timer->Timer->CR1 |= TIM_CR1_CEN;
|
|
}
|
|
|
|
void MyTimer_Stop(MyTimer_Struct_TypeDef * Timer)
|
|
{
|
|
Timer->Timer->CR1 &= ~TIM_CR1_CEN;
|
|
}
|
|
|
|
// Note : PWM Tested on PA0
|
|
void MyTimer_ConfigurePWM(MyTimer_Struct_TypeDef *Timer, uint8_t channel, uint16_t duty_cycle) {
|
|
|
|
uint16_t CCR_Value = (duty_cycle * TIM2->ARR) / 100;
|
|
|
|
// Configurer le Timer en mode PWM
|
|
|
|
|
|
// Configurer le Channel
|
|
if (channel == 1) {
|
|
Timer->Timer->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
|
|
Timer->Timer->CCMR1 |= TIM_CCMR1_OC1PE; // activer la précharge du registre de comparaison
|
|
Timer->Timer->CCER |= TIM_CCER_CC1E;
|
|
Timer->Timer->CCR1 = CCR_Value;
|
|
} else if (channel == 2) {
|
|
Timer->Timer->CCMR1 = TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1;
|
|
Timer->Timer->CCMR1 |= TIM_CCMR1_OC2PE; // activer la précharge du registre de comparaison
|
|
Timer->Timer->CCER |= TIM_CCER_CC2E;
|
|
Timer->Timer->CCR2 = CCR_Value;
|
|
} else if (channel == 3) {
|
|
Timer->Timer->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1;
|
|
Timer->Timer->CCMR2 |= TIM_CCMR2_OC3PE; // activer la précharge du registre de comparaison
|
|
Timer->Timer->CCER |= TIM_CCER_CC3E;
|
|
Timer->Timer->CCER &= ~TIM_CCER_CC3P;
|
|
Timer->Timer->CCR3 = CCR_Value;
|
|
} else if (channel == 4) {
|
|
Timer->Timer->CCMR2 = TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1;
|
|
Timer->Timer->CCMR2 |= TIM_CCMR2_OC4PE; // activer la précharge du registre de comparaison
|
|
Timer->Timer->CCER |= TIM_CCER_CC4E;
|
|
Timer->Timer->CCR4 = CCR_Value;
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
void Bug (void)
|
|
{
|
|
while(1);
|
|
}
|
|
|
|
void (*TIM2_fx) (void) = &Bug;
|
|
void (*TIM3_fx) (void) = &Bug;
|
|
void (*TIM4_fx) (void) = &Bug;
|
|
|
|
void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void))
|
|
{
|
|
Timer->DIER |= TIM_DIER_UIE;
|
|
if(Timer == TIM1)
|
|
{
|
|
}
|
|
if(Timer == TIM2)
|
|
{
|
|
NVIC_EnableIRQ(TIM2_IRQn);
|
|
NVIC_SetPriority(TIM2_IRQn, Prio);
|
|
TIM2_fx = IT_function;
|
|
}
|
|
if(Timer == TIM3)
|
|
{
|
|
NVIC_EnableIRQ(TIM3_IRQn);
|
|
NVIC_SetPriority(TIM3_IRQn, Prio);
|
|
TIM3_fx = IT_function;
|
|
}
|
|
if(Timer == TIM4)
|
|
{
|
|
NVIC_EnableIRQ(TIM4_IRQn);
|
|
NVIC_SetPriority(TIM4_IRQn, Prio);
|
|
TIM4_fx = IT_function;
|
|
}
|
|
}
|
|
|
|
void TIM2_IRQHandler (void)
|
|
{
|
|
TIM2->SR &= ~TIM_SR_UIF;
|
|
(*TIM2_fx)();
|
|
}
|
|
|
|
void TIM3_IRQHandler (void)
|
|
{
|
|
TIM3->SR &= ~TIM_SR_UIF;
|
|
(*TIM3_fx)();
|
|
}
|
|
|
|
void TIM4_IRQHandler (void)
|
|
{
|
|
TIM3->SR &= ~TIM_SR_UIF;
|
|
(*TIM4_fx)();
|
|
}
|
|
|