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bm_data_test.vhd 2.8KB

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  1. --------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 13:17:22 04/16/2021
  6. -- Design Name:
  7. -- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd
  8. -- Project Name: ALU
  9. -- Target Device:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- VHDL Test Bench Created by ISE for module: bm_data
  14. --
  15. -- Dependencies:
  16. --
  17. -- Revision:
  18. -- Revision 0.01 - File Created
  19. -- Additional Comments:
  20. --
  21. -- Notes:
  22. -- This testbench has been automatically generated using types std_logic and
  23. -- std_logic_vector for the ports of the unit under test. Xilinx recommends
  24. -- that these types always be used for the top-level I/O of a design in order
  25. -- to guarantee that the testbench will bind correctly to the post-implementation
  26. -- simulation model.
  27. --------------------------------------------------------------------------------
  28. LIBRARY ieee;
  29. USE ieee.std_logic_1164.ALL;
  30. -- Uncomment the following library declaration if using
  31. -- arithmetic functions with Signed or Unsigned values
  32. --USE ieee.numeric_std.ALL;
  33. ENTITY bm_data_test IS
  34. END bm_data_test;
  35. ARCHITECTURE behavior OF bm_data_test IS
  36. -- Component Declaration for the Unit Under Test (UUT)
  37. COMPONENT bm_data
  38. PORT(
  39. IN_addr : IN std_logic_vector(7 downto 0);
  40. IN_data : IN std_logic_vector(7 downto 0);
  41. RW : IN std_logic;
  42. RST : IN std_logic;
  43. CLK : IN std_logic;
  44. OUT_data : OUT std_logic_vector(7 downto 0)
  45. );
  46. END COMPONENT;
  47. --Inputs
  48. signal IN_addr : std_logic_vector(7 downto 0) := (others => '0');
  49. signal IN_data : std_logic_vector(7 downto 0) := (others => '0');
  50. signal RW : std_logic := '0';
  51. signal RST : std_logic := '0';
  52. signal CLK : std_logic := '0';
  53. --Outputs
  54. signal OUT_data : std_logic_vector(7 downto 0);
  55. -- Clock period definitions
  56. constant CLK_period : time := 10 ns;
  57. BEGIN
  58. -- Instantiate the Unit Under Test (UUT)
  59. uut: bm_data PORT MAP (
  60. IN_addr => IN_addr,
  61. IN_data => IN_data,
  62. RW => RW,
  63. RST => RST,
  64. CLK => CLK,
  65. OUT_data => OUT_data
  66. );
  67. -- Clock process definitions
  68. CLK_process :process
  69. begin
  70. CLK <= '0';
  71. wait for CLK_period/2;
  72. CLK <= '1';
  73. wait for CLK_period/2;
  74. end process;
  75. -- Stimulus process
  76. stim_proc: process
  77. begin
  78. -- hold reset state for 100 ns.
  79. wait for 100 ns;
  80. wait for CLK_period*10;
  81. RST <= '1';
  82. IN_addr <= "00000001";
  83. IN_data <= "00000001";
  84. wait for 30 ns;
  85. IN_addr <= "00000010";
  86. IN_data <= "00000010";
  87. RW <= '1';
  88. wait for 30 ns;
  89. IN_addr <= "00000001";
  90. wait for 30 ns;
  91. IN_addr <= "00000000";
  92. wait for 30 ns;
  93. RST <= '0';
  94. wait;
  95. end process;
  96. END;