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alu_test.vhd 3.0KB

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  1. --------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 10:50:53 04/13/2021
  6. -- Design Name:
  7. -- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd
  8. -- Project Name: ALU
  9. -- Target Device:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- VHDL Test Bench Created by ISE for module: alu
  14. --
  15. -- Dependencies:
  16. --
  17. -- Revision:
  18. -- Revision 0.01 - File Created
  19. -- Additional Comments:
  20. --
  21. -- Notes:
  22. -- This testbench has been automatically generated using types std_logic and
  23. -- std_logic_vector for the ports of the unit under test. Xilinx recommends
  24. -- that these types always be used for the top-level I/O of a design in order
  25. -- to guarantee that the testbench will bind correctly to the post-implementation
  26. -- simulation model.
  27. --------------------------------------------------------------------------------
  28. LIBRARY ieee;
  29. USE ieee.std_logic_1164.ALL;
  30. -- Uncomment the following library declaration if using
  31. -- arithmetic functions with Signed or Unsigned values
  32. --USE ieee.numeric_std.ALL;
  33. ENTITY alu_test IS
  34. END alu_test;
  35. ARCHITECTURE behavior OF alu_test IS
  36. -- Component Declaration for the Unit Under Test (UUT)
  37. COMPONENT alu
  38. PORT(
  39. A : IN std_logic_vector(7 downto 0);
  40. B : IN std_logic_vector(7 downto 0);
  41. Ctrl_Alu : IN std_logic_vector(2 downto 0);
  42. N : OUT std_logic;
  43. O : OUT std_logic;
  44. Z : OUT std_logic;
  45. C : OUT std_logic;
  46. S : OUT std_logic_vector(7 downto 0)
  47. );
  48. END COMPONENT;
  49. --Inputs
  50. signal A : std_logic_vector(7 downto 0) := (others => '0');
  51. signal B : std_logic_vector(7 downto 0) := (others => '0');
  52. signal Ctrl_Alu : std_logic_vector(2 downto 0) := (others => '0');
  53. --Outputs
  54. signal N : std_logic;
  55. signal O : std_logic;
  56. signal Z : std_logic;
  57. signal C : std_logic;
  58. signal S : std_logic_vector(7 downto 0);
  59. -- No clocks detected in port list. Replace <clock> below with
  60. -- appropriate port name
  61. BEGIN
  62. -- Instantiate the Unit Under Test (UUT)
  63. uut: alu PORT MAP (
  64. A => A,
  65. B => B,
  66. Ctrl_Alu => Ctrl_Alu,
  67. N => N,
  68. O => O,
  69. Z => Z,
  70. C => C,
  71. S => S
  72. );
  73. -- Stimulus process
  74. stim_proc: process
  75. begin
  76. -- hold reset state for 100 ns.
  77. -- 3 op on random numbers
  78. wait for 100 ns;
  79. A<="00000111";
  80. B<="00000011";
  81. wait for 100 ns;
  82. Ctrl_Alu<="001";
  83. wait for 30 ns;
  84. Ctrl_Alu<="010";
  85. wait for 30 ns;
  86. Ctrl_Alu<="011";
  87. wait for 30 ns;
  88. Ctrl_Alu<="000";
  89. wait for 30 ns;
  90. A<="11111111";
  91. B<="11111111";
  92. -- test carry
  93. wait for 100 ns;
  94. Ctrl_Alu<="001";
  95. -- test multiply
  96. wait for 30 ns;
  97. Ctrl_Alu<="011";
  98. --test null
  99. wait for 30 ns;
  100. Ctrl_Alu<="010";
  101. wait for 30 ns;
  102. Ctrl_Alu<="000";
  103. wait for 30 ns;
  104. -- test less than 0
  105. A<="00000001";
  106. wait for 30 ns;
  107. Ctrl_Alu<="010";
  108. wait;
  109. end process;
  110. END;