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br_test.vhd 3.1KB

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  1. --------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 09:35:26 04/15/2021
  6. -- Design Name:
  7. -- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br_test.vhd
  8. -- Project Name: ALU
  9. -- Target Device:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- VHDL Test Bench Created by ISE for module: br
  14. --
  15. -- Dependencies:
  16. --
  17. -- Revision:
  18. -- Revision 0.01 - File Created
  19. -- Additional Comments:
  20. --
  21. -- Notes:
  22. -- This testbench has been automatically generated using types std_logic and
  23. -- std_logic_vector for the ports of the unit under test. Xilinx recommends
  24. -- that these types always be used for the top-level I/O of a design in order
  25. -- to guarantee that the testbench will bind correctly to the post-implementation
  26. -- simulation model.
  27. --------------------------------------------------------------------------------
  28. LIBRARY ieee;
  29. USE ieee.std_logic_1164.ALL;
  30. -- Uncomment the following library declaration if using
  31. -- arithmetic functions with Signed or Unsigned values
  32. --USE ieee.numeric_std.ALL;
  33. ENTITY br_test IS
  34. END br_test;
  35. ARCHITECTURE behavior OF br_test IS
  36. -- Component Declaration for the Unit Under Test (UUT)
  37. COMPONENT br
  38. PORT(
  39. A_addr : IN std_logic_vector(3 downto 0);
  40. B_addr : IN std_logic_vector(3 downto 0);
  41. W_addr : IN std_logic_vector(3 downto 0);
  42. W : IN std_logic;
  43. Data : IN std_logic_vector(7 downto 0);
  44. RST : IN std_logic;
  45. CLK : IN std_logic;
  46. QA : OUT std_logic_vector(7 downto 0);
  47. QB : OUT std_logic_vector(7 downto 0)
  48. );
  49. END COMPONENT;
  50. --Inputs
  51. signal A_addr : std_logic_vector(3 downto 0) := (others => '0');
  52. signal B_addr : std_logic_vector(3 downto 0) := (others => '0');
  53. signal W_addr : std_logic_vector(3 downto 0) := (others => '0');
  54. signal W : std_logic := '0';
  55. signal Data : std_logic_vector(7 downto 0) := (others => '0');
  56. signal RST : std_logic := '0';
  57. signal CLK : std_logic := '0';
  58. --Outputs
  59. signal QA : std_logic_vector(7 downto 0);
  60. signal QB : std_logic_vector(7 downto 0);
  61. -- Clock period definitions
  62. constant CLK_period : time := 10 ns;
  63. BEGIN
  64. -- Instantiate the Unit Under Test (UUT)
  65. uut: br PORT MAP (
  66. A_addr => A_addr,
  67. B_addr => B_addr,
  68. W_addr => W_addr,
  69. W => W,
  70. Data => Data,
  71. RST => RST,
  72. CLK => CLK,
  73. QA => QA,
  74. QB => QB
  75. );
  76. -- Clock process definitions
  77. CLK_process :process
  78. begin
  79. CLK <= '0';
  80. wait for CLK_period/2;
  81. CLK <= '1';
  82. wait for CLK_period/2;
  83. end process;
  84. -- Stimulus process
  85. stim_proc: process
  86. begin
  87. -- hold reset state for 100 ns.
  88. wait for 100 ns;
  89. wait for CLK_period*10;
  90. RST <= '1';
  91. wait for 100 ns ;
  92. DATA <= "10000000";
  93. wait for 100 ns ;
  94. W_addr <= "0000";
  95. wait for 100 ns ;
  96. W <= '1';
  97. wait for 100 ns ;
  98. W <= '0';
  99. wait for 100 ns ;
  100. A_addr <= "0000" ;
  101. B_addr <= "0001" ;
  102. wait;
  103. end process;
  104. END;