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bm_instr_test.vhd 2.3KB

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  1. --------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 10:42:17 04/15/2021
  6. -- Design Name:
  7. -- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd
  8. -- Project Name: ALU
  9. -- Target Device:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- VHDL Test Bench Created by ISE for module: bm_instr
  14. --
  15. -- Dependencies:
  16. --
  17. -- Revision:
  18. -- Revision 0.01 - File Created
  19. -- Additional Comments:
  20. --
  21. -- Notes:
  22. -- This testbench has been automatically generated using types std_logic and
  23. -- std_logic_vector for the ports of the unit under test. Xilinx recommends
  24. -- that these types always be used for the top-level I/O of a design in order
  25. -- to guarantee that the testbench will bind correctly to the post-implementation
  26. -- simulation model.
  27. --------------------------------------------------------------------------------
  28. LIBRARY ieee;
  29. USE ieee.std_logic_1164.ALL;
  30. -- Uncomment the following library declaration if using
  31. -- arithmetic functions with Signed or Unsigned values
  32. --USE ieee.numeric_std.ALL;
  33. ENTITY bm_instr_test IS
  34. END bm_instr_test;
  35. ARCHITECTURE behavior OF bm_instr_test IS
  36. -- Component Declaration for the Unit Under Test (UUT)
  37. COMPONENT bm_instr
  38. PORT(
  39. IN_addr : IN std_logic_vector(7 downto 0);
  40. OUT_data : OUT std_logic_vector(7 downto 0);
  41. CLK : IN std_logic
  42. );
  43. END COMPONENT;
  44. --Inputs
  45. signal IN_addr : std_logic_vector(7 downto 0) := (others => '0');
  46. signal CLK : std_logic := '0';
  47. --Outputs
  48. signal OUT_data : std_logic_vector(7 downto 0);
  49. -- Clock period definitions
  50. constant CLK_period : time := 10 ns;
  51. BEGIN
  52. -- Instantiate the Unit Under Test (UUT)
  53. uut: bm_instr PORT MAP (
  54. IN_addr => IN_addr,
  55. OUT_data => OUT_data,
  56. CLK => CLK
  57. );
  58. -- Clock process definitions
  59. CLK_process :process
  60. begin
  61. CLK <= '0';
  62. wait for CLK_period/2;
  63. CLK <= '1';
  64. wait for CLK_period/2;
  65. end process;
  66. -- Stimulus process
  67. stim_proc: process
  68. begin
  69. -- hold reset state for 100 ns.
  70. wait for 100 ns;
  71. wait for CLK_period*10;
  72. IN_addr <= "00000001";
  73. wait for 100 ns;
  74. IN_addr <= "00001001";
  75. wait;
  76. end process;
  77. END;