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bm_instr.vhd 1010B

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 10:40:07 04/15/2021
  6. -- Design Name:
  7. -- Module Name: bm_instr - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  23. use IEEE.NUMERIC_STD.ALL;
  24. entity bm_instr is
  25. Port ( IN_addr : in STD_LOGIC_VECTOR (7 downto 0);
  26. OUT_data : out STD_LOGIC_VECTOR (7 downto 0);
  27. CLK : in STD_LOGIC);
  28. end bm_instr;
  29. architecture Behavioral of bm_instr is
  30. type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
  31. signal instr_memory: mem := (1 => "00000001", others =>"00000000");
  32. begin
  33. OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));
  34. end Behavioral;