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bm.vhd 1.3KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 10:32:11 04/15/2021
  6. -- Design Name:
  7. -- Module Name: bm_data - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  23. use IEEE.NUMERIC_STD.ALL;
  24. entity bm_data is
  25. Port ( IN_addr : in STD_LOGIC_VECTOR (7 downto 0);
  26. IN_data : in STD_LOGIC_VECTOR (7 downto 0);
  27. RW : in STD_LOGIC;
  28. RST : in STD_LOGIC;
  29. CLK : in STD_LOGIC;
  30. OUT_data : out STD_LOGIC_VECTOR (7 downto 0));
  31. end bm_data;
  32. architecture Behavioral of bm_data is
  33. type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
  34. signal data_memory: mem;
  35. begin
  36. process
  37. begin
  38. wait until rising_edge(CLK);
  39. if RW = '1' then
  40. OUT_data <= data_memory(to_integer(unsigned(IN_addr)));
  41. else
  42. data_memory(to_integer(unsigned(IN_addr))) <= IN_data;
  43. end if;
  44. if RST='0' then
  45. registres <= (others => "00000000");
  46. end if;
  47. end process;
  48. end Behavioral;