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-- Company: 
-- Engineer:
--
-- Create Date:   10:42:17 04/15/2021
-- Design Name:   
-- Module Name:   /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd
-- Project Name:  ALU
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: bm_instr
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY bm_instr_test IS
END bm_instr_test;
 
ARCHITECTURE behavior OF bm_instr_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT bm_instr
    PORT(
         IN_addr : IN  std_logic_vector(7 downto 0);
         OUT_data : OUT  std_logic_vector(31 downto 0);
         CLK : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal IN_addr : std_logic_vector(7 downto 0) := (others => '0');
   signal CLK : std_logic := '0';

 	--Outputs
   signal OUT_data : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: bm_instr PORT MAP (
          IN_addr => IN_addr,
          OUT_data => OUT_data,
          CLK => CLK
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for CLK_period*10;

      IN_addr <= "00000001";
		wait for 100 ns;
		
		IN_addr <= "00001001";
		

      wait;
   end process;

END;