----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:40:07 04/15/2021 
-- Design Name: 
-- Module Name:    bm_instr - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;


entity bm_instr is
    Port ( IN_addr : in  STD_LOGIC_VECTOR (7 downto 0);
           OUT_data : out  STD_LOGIC_VECTOR (7 downto 0);
           CLK : in  STD_LOGIC);
end bm_instr;

architecture Behavioral of bm_instr is

type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
signal instr_memory: mem := (1 => "00000001", others =>"00000000");

begin

		OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));



end Behavioral;