Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test" ISim O.87xd (signature 0x8ddf5b5d) Number of CPUs detected in this system: 12 Turning on mult-threading, number of parallel sub-compilation jobs: 24 Determining compilation order of HDL files Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd" into library work Starting static elaboration Completed static elaboration Fuse Memory Usage: 98520 KB Fuse CPU Usage: 760 ms Compiling package standard Compiling package std_logic_1164 Compiling package std_logic_arith Compiling package std_logic_unsigned Compiling package numeric_std Compiling architecture behavioral of entity bm_instr [bm_instr_default] Compiling architecture behavioral of entity pipeline [pipeline_default] Compiling architecture behavioral of entity br [br_default] Compiling architecture behavioral of entity alu [alu_default] Compiling architecture behavioral of entity bm_data [bm_data_default] Compiling architecture behavioral of entity processeur [processeur_default] Compiling architecture behavior of entity process_test Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 18 VHDL Units Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe Fuse Memory Usage: 1723208 KB Fuse CPU Usage: 850 ms GCC CPU Usage: 120 ms