| processeur Project Status | |||
| Project File: | ALU.xise | Parser Errors: | No Errors |
| Module Name: | processeur | Implementation State: | Mapped |
| Target Device: | xc6slx16-3csg324 |
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X 2 Errors (2 new) |
| Product Version: | ISE 13.4 |
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9 Warnings (9 new) |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary | [-] | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | mar. mai 18 16:14:40 2021 | 0 | 8 Warnings (8 new) | 7 Infos (7 new) | |
| Translation Report | Current | mar. mai 18 16:15:06 2021 | 0 | 1 Warning (1 new) | 0 | |
| Map Report | Current | mar. mai 18 16:15:09 2021 | X 2 Errors (2 new) | 0 | 0 | |
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | mar. mai 18 16:20:52 2021 | |