From 2b20dd8bc4d69db3f4582edbcd0088e5747cbbb9 Mon Sep 17 00:00:00 2001 From: Mathieu Fortineau Date: Wed, 3 Dec 2025 08:19:23 +0100 Subject: [PATCH] Premier Commit --- .gitignore | 30 + ADC/Application/principal.c | 39 + ADC/Drivertest.uvoptx | 446 ++++ ADC/RTE/Device/STM32F103RB/RTE_Device.h | 1828 +++++++++++++++++ .../STM32F103RB/RTE_Device.h.base@1.1.2 | 1828 +++++++++++++++++ ...M32F101_102_103_105_107.dbgconf.base@1.0.0 | 36 + .../Device/STM32F103RB/startup_stm32f10x_md.s | 308 +++ .../startup_stm32f10x_md.s.base@1.0.1 | 308 +++ ADC/RTE/Device/STM32F103RB/system_stm32f10x.c | 1092 ++++++++++ .../STM32F103RB/system_stm32f10x.c.base@1.0.1 | 1092 ++++++++++ ADC/RTE/_Reel/RTE_Components.h | 20 + ADC/RTE/_Simulation/RTE_Components.h | 20 + ADC/adc.uvoptx | 396 ++++ ADC/adc.uvprojx | 892 ++++++++ ADC/projetLEDD.uvoptx | 450 ++++ ADC/reel.ini | 1 + ADC/simu.ini | 1 + ADC/timer.uvoptx | 551 +++++ Drivers.zip | Bin 0 -> 3230 bytes Drivers/MyTimer.c | 113 + Drivers/MyTimer.h | 13 + Drivers/MyUART.h | 11 + Drivers/My_UART.c | 87 + Drivers/adc.c | 19 + Drivers/adc.h | 9 + Drivers/gpio.c | 73 + Drivers/gpio.h | 20 + Drivertest/Application/principal.c | 46 + Drivertest/Drivertest.uvoptx | 512 +++++ Drivertest/Drivertest.uvprojx | 922 +++++++++ .../RTE/Device/STM32F103RB/RTE_Device.h | 1828 +++++++++++++++++ .../STM32F103RB/RTE_Device.h.base@1.1.2 | 1828 +++++++++++++++++ ...M32F101_102_103_105_107.dbgconf.base@1.0.0 | 36 + .../Device/STM32F103RB/startup_stm32f10x_md.s | 308 +++ .../startup_stm32f10x_md.s.base@1.0.1 | 308 +++ .../RTE/Device/STM32F103RB/system_stm32f10x.c | 1092 ++++++++++ .../STM32F103RB/system_stm32f10x.c.base@1.0.1 | 1092 ++++++++++ Drivertest/RTE/_Reel/RTE_Components.h | 20 + Drivertest/RTE/_Simulation/RTE_Components.h | 20 + Drivertest/projetLEDD.uvoptx | 450 ++++ Drivertest/reel.ini | 1 + Drivertest/simu.ini | 1 + ProjetVide.zip | Bin 0 -> 7941 bytes projetLEDD/Application/principal.c | 22 + .../RTE/Device/STM32F103RB/RTE_Device.h | 1828 +++++++++++++++++ .../STM32F103RB/RTE_Device.h.base@1.1.2 | 1828 +++++++++++++++++ ...M32F101_102_103_105_107.dbgconf.base@1.0.0 | 36 + .../Device/STM32F103RB/startup_stm32f10x_md.s | 308 +++ .../startup_stm32f10x_md.s.base@1.0.1 | 308 +++ .../RTE/Device/STM32F103RB/system_stm32f10x.c | 1092 ++++++++++ .../STM32F103RB/system_stm32f10x.c.base@1.0.1 | 1092 ++++++++++ projetLEDD/RTE/_Reel/RTE_Components.h | 20 + projetLEDD/RTE/_Simulation/RTE_Components.h | 20 + projetLEDD/projetLEDD.uvoptx | 450 ++++ projetLEDD/projetLEDD.uvprojx | 892 ++++++++ projetLEDD/reel.ini | 1 + projetLEDD/simu.ini | 1 + timer/Application/principal.c | 46 + timer/Drivertest.uvoptx | 446 ++++ timer/RTE/Device/STM32F103RB/RTE_Device.h | 1828 +++++++++++++++++ .../STM32F103RB/RTE_Device.h.base@1.1.2 | 1828 +++++++++++++++++ ...M32F101_102_103_105_107.dbgconf.base@1.0.0 | 36 + .../Device/STM32F103RB/startup_stm32f10x_md.s | 308 +++ .../startup_stm32f10x_md.s.base@1.0.1 | 308 +++ .../RTE/Device/STM32F103RB/system_stm32f10x.c | 1092 ++++++++++ .../STM32F103RB/system_stm32f10x.c.base@1.0.1 | 1092 ++++++++++ timer/RTE/_Reel/RTE_Components.h | 20 + timer/RTE/_Simulation/RTE_Components.h | 20 + timer/projetLEDD.uvoptx | 450 ++++ timer/reel.ini | 1 + timer/simu.ini | 1 + timer/timer.uvoptx | 543 +++++ timer/timer.uvprojx | 912 ++++++++ 73 files changed, 34976 insertions(+) create mode 100644 .gitignore create mode 100644 ADC/Application/principal.c create mode 100644 ADC/Drivertest.uvoptx create mode 100644 ADC/RTE/Device/STM32F103RB/RTE_Device.h create mode 100644 ADC/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 create mode 100644 ADC/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 create mode 100644 ADC/RTE/Device/STM32F103RB/startup_stm32f10x_md.s create mode 100644 ADC/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 create mode 100644 ADC/RTE/Device/STM32F103RB/system_stm32f10x.c create mode 100644 ADC/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 create mode 100644 ADC/RTE/_Reel/RTE_Components.h create mode 100644 ADC/RTE/_Simulation/RTE_Components.h create mode 100644 ADC/adc.uvoptx create mode 100644 ADC/adc.uvprojx create mode 100644 ADC/projetLEDD.uvoptx create mode 100644 ADC/reel.ini create mode 100644 ADC/simu.ini create mode 100644 ADC/timer.uvoptx create mode 100644 Drivers.zip create mode 100644 Drivers/MyTimer.c create mode 100644 Drivers/MyTimer.h create mode 100644 Drivers/MyUART.h create mode 100644 Drivers/My_UART.c create mode 100644 Drivers/adc.c create mode 100644 Drivers/adc.h create mode 100644 Drivers/gpio.c create mode 100644 Drivers/gpio.h create mode 100644 Drivertest/Application/principal.c create mode 100644 Drivertest/Drivertest.uvoptx create mode 100644 Drivertest/Drivertest.uvprojx create mode 100644 Drivertest/RTE/Device/STM32F103RB/RTE_Device.h create mode 100644 Drivertest/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 create mode 100644 Drivertest/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 create mode 100644 Drivertest/RTE/Device/STM32F103RB/startup_stm32f10x_md.s create mode 100644 Drivertest/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 create mode 100644 Drivertest/RTE/Device/STM32F103RB/system_stm32f10x.c create mode 100644 Drivertest/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 create mode 100644 Drivertest/RTE/_Reel/RTE_Components.h create mode 100644 Drivertest/RTE/_Simulation/RTE_Components.h create mode 100644 Drivertest/projetLEDD.uvoptx create mode 100644 Drivertest/reel.ini create mode 100644 Drivertest/simu.ini create mode 100644 ProjetVide.zip create mode 100644 projetLEDD/Application/principal.c create mode 100644 projetLEDD/RTE/Device/STM32F103RB/RTE_Device.h create mode 100644 projetLEDD/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 create mode 100644 projetLEDD/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 create mode 100644 projetLEDD/RTE/Device/STM32F103RB/startup_stm32f10x_md.s create mode 100644 projetLEDD/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 create mode 100644 projetLEDD/RTE/Device/STM32F103RB/system_stm32f10x.c create mode 100644 projetLEDD/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 create mode 100644 projetLEDD/RTE/_Reel/RTE_Components.h create mode 100644 projetLEDD/RTE/_Simulation/RTE_Components.h create mode 100644 projetLEDD/projetLEDD.uvoptx create mode 100644 projetLEDD/projetLEDD.uvprojx create mode 100644 projetLEDD/reel.ini create mode 100644 projetLEDD/simu.ini create mode 100644 timer/Application/principal.c create mode 100644 timer/Drivertest.uvoptx create mode 100644 timer/RTE/Device/STM32F103RB/RTE_Device.h create mode 100644 timer/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 create mode 100644 timer/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 create mode 100644 timer/RTE/Device/STM32F103RB/startup_stm32f10x_md.s create mode 100644 timer/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 create mode 100644 timer/RTE/Device/STM32F103RB/system_stm32f10x.c create mode 100644 timer/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 create mode 100644 timer/RTE/_Reel/RTE_Components.h create mode 100644 timer/RTE/_Simulation/RTE_Components.h create mode 100644 timer/projetLEDD.uvoptx create mode 100644 timer/reel.ini create mode 100644 timer/simu.ini create mode 100644 timer/timer.uvoptx create mode 100644 timer/timer.uvprojx diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a2e229f --- /dev/null +++ b/.gitignore @@ -0,0 +1,30 @@ +*.obj +*.o +*.bin +*.list +*.map +*.mk +*.makefile +*.o +*.su +*.d +*.elf +*.scvd +*.crf +*.map +*.sct +*.dbgconf +*.axf +*.htm +*.lnp +*.dep +*.uvguix.* +*.lst +*.iex +**/Objects/ +**/Listings/ +**/Debug/ + + + + diff --git a/ADC/Application/principal.c b/ADC/Application/principal.c new file mode 100644 index 0000000..9de5300 --- /dev/null +++ b/ADC/Application/principal.c @@ -0,0 +1,39 @@ +#include "stm32f10x.h" +#include "gpio.h" +#include "MyTimer.h" + +void clignot(void){ + gpio_toggle(GPIOA,13); +} + +int main ( void ) +{ + //RCC->APB2ENR |= (0x01 << 2) | (0x01 << 3) | (0x01 << 4) ; +// TIM2->CR1 |= 1; +// TIM2->ARR=6000; +// TIM2->PSC=6000; + +// MyTimer_Base_Init(TIM2,6000,6000); +// TIM2->DIER |= 1;//tim2 transmet flag uif +// MyTimer_ActiveIT(TIM2, 4, clignot); +// NVIC->ISER[0] |= NVIC_ISER_SETENA_25; //tim2 ligne 28 +// TIM2->CCR1 = 2000; +// MyTimer_PWM(TIM2, 1); + + + MyTimer_Base_Init(TIM4,720,1); + TIM2->DIER |= 1;//tim2 transmet flag uif + NVIC->ISER[0] |= NVIC_ISER_SETENA_25; //tim2 ligne 28 + TIM4->CCR1 = 2000; + MyTimer_PWM(TIM4, 1); + MyTimer_PWM_Setup(TIM4,20,1); + + gpio_init( GPIOB, 6 , AltOut_Ppull); + + while (1) + { + + } +} + + diff --git a/ADC/Drivertest.uvoptx b/ADC/Drivertest.uvoptx new file mode 100644 index 0000000..77497b8 --- /dev/null +++ b/ADC/Drivertest.uvoptx @@ -0,0 +1,446 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Reel + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Simulation + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + .\simu.ini + + + + + + BIN\UL2CM3.DLL + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1101,123,1522,550,1)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + 0 + 5 + 1 +
134219392
+ 0 + 0 + 0 + 0 + 0 + 1 + U:\4AE\µC\Drivertest\Application\principal.c + + \\ProjetVide\Application/principal.c\5 + + + 1 + 0 + 8 + 1 +
134219422
+ 0 + 0 + 0 + 0 + 0 + 1 + U:\4AE\µC\Drivertest\Application\principal.c + + \\ProjetVide\Application/principal.c\8 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Application + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\Application\principal.c + principal.c + 0 + 0 + + + + + Services + 0 + 0 + 0 + 0 + + + + Drivers + 1 + 0 + 0 + 0 + + 3 + 2 + 1 + 0 + 0 + 0 + ..\Drivers\gpio.c + gpio.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/ADC/RTE/Device/STM32F103RB/RTE_Device.h b/ADC/RTE/Device/STM32F103RB/RTE_Device.h new file mode 100644 index 0000000..70c8002 --- /dev/null +++ b/ADC/RTE/Device/STM32F103RB/RTE_Device.h @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/ADC/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 b/ADC/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 new file mode 100644 index 0000000..70c8002 --- /dev/null +++ b/ADC/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/ADC/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 b/ADC/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 new file mode 100644 index 0000000..9c4804d --- /dev/null +++ b/ADC/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/ADC/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/ADC/RTE/Device/STM32F103RB/startup_stm32f10x_md.s new file mode 100644 index 0000000..3db5920 --- /dev/null +++ b/ADC/RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/ADC/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 b/ADC/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 new file mode 100644 index 0000000..3db5920 --- /dev/null +++ b/ADC/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/ADC/RTE/Device/STM32F103RB/system_stm32f10x.c b/ADC/RTE/Device/STM32F103RB/system_stm32f10x.c new file mode 100644 index 0000000..3301967 --- /dev/null +++ b/ADC/RTE/Device/STM32F103RB/system_stm32f10x.c @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/ADC/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 b/ADC/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 new file mode 100644 index 0000000..3301967 --- /dev/null +++ b/ADC/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/ADC/RTE/_Reel/RTE_Components.h b/ADC/RTE/_Reel/RTE_Components.h new file mode 100644 index 0000000..e14b2f6 --- /dev/null +++ b/ADC/RTE/_Reel/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'projetLEDD' + * Target: 'Reel' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ADC/RTE/_Simulation/RTE_Components.h b/ADC/RTE/_Simulation/RTE_Components.h new file mode 100644 index 0000000..30d8459 --- /dev/null +++ b/ADC/RTE/_Simulation/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'projetLEDD' + * Target: 'Simulation' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ADC/adc.uvoptx b/ADC/adc.uvoptx new file mode 100644 index 0000000..b3babe6 --- /dev/null +++ b/ADC/adc.uvoptx @@ -0,0 +1,396 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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+void (*pointeur_fonction_Timer2)(void); +void (*pointeur_fonction_Timer3)(void); +void (*pointeur_fonction_Timer4)(void); + +void MyTimer_Base_Init(TIM_TypeDef *Timer, unsigned short ValARR, unsigned short ValPSC) +{ + if (Timer == TIM2) + { + RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; + } + else if (Timer == TIM3) + { + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; + } + else if (Timer == TIM4) + { + RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; + } + else if (Timer == TIM1) + { + RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; + } + MyTimer_Base_Start(Timer); + Timer->ARR=ValARR-1; + Timer->PSC=ValPSC-1; +} + +void MyTimer_ActiveIT(TIM_TypeDef * Timer, char Prio, void (*interrupt) (void)) +{ + if (Timer == TIM2) + { + NVIC->IPR[28] = Prio<<4; + pointeur_fonction_Timer2=interrupt; + } + else if (Timer == TIM3) + { + NVIC->IPR[29] = Prio<<4; + pointeur_fonction_Timer3=interrupt; + } + else if (Timer == TIM4) + { + NVIC->IPR[30] = Prio<<4; + pointeur_fonction_Timer4=interrupt; + } + else if (Timer == TIM1) + { + NVIC->IPR[25] = Prio<<4; + pointeur_fonction_Timer1=interrupt; + } +} + +void MyTimer_PWM(TIM_TypeDef * Timer, char Channel) +{ + if (Timer == TIM2 || Timer == TIM3 || Timer == TIM4) + { + if (Channel == 1 || Channel == 2) + { + Timer->CCMR1 &= ~(0x1 << 8*(Channel - 1)); + Timer->CCMR1 |= (6 << 4); + Timer->CCER |= (1 << 4*(Channel - 1)); + } + else if (Channel == 3 || Channel == 4) + { + Timer->CCMR2 &= ~(0x1 << 8*(Channel - 3)); + Timer->CCMR2 |= (6 << 4); + Timer->CCER |= (1 << 4*(Channel - 3)); + } + } +} + +void MyTimer_PWM_Setup(TIM_TypeDef * Timer, char dutycycle, char channel) +{ + + if (channel ==1){ + Timer->CCR1 = ((Timer->ARR)*(dutycycle))/100; + }else if (channel ==2){ + Timer->CCR2 = (Timer->ARR*(dutycycle))/100; + }else if (channel ==3){ + Timer->CCR3 = (Timer->ARR*(dutycycle))/100; + }else if (channel ==4){ + Timer->CCR4 = (Timer->ARR*(dutycycle))/100; + } + +} + +void TIM1_UP_IRQHandler(void) +{ + TIM1->SR &= ~TIM_SR_UIF; + pointeur_fonction_Timer1(); + +} + +void TIM2_IRQHandler(void) +{ + TIM2->SR &= ~TIM_SR_UIF; + pointeur_fonction_Timer2(); +} + +void TIM3_IRQHandler(void) +{ + TIM3->SR &= ~TIM_SR_UIF; + pointeur_fonction_Timer3(); +} +void TIM4_IRQHandler(void) +{ + TIM4->SR &= ~TIM_SR_UIF; + pointeur_fonction_Timer4(); +} + diff --git a/Drivers/MyTimer.h b/Drivers/MyTimer.h new file mode 100644 index 0000000..ae19380 --- /dev/null +++ b/Drivers/MyTimer.h @@ -0,0 +1,13 @@ +#ifndef TIMER_H +#define TIMER_H + +#include "stm32f10x.h" + +void MyTimer_Base_Init(TIM_TypeDef *Timer, unsigned short ValARR, unsigned short ValPSC); +void MyTimer_ActiveIT(TIM_TypeDef * Timer, char Prio, void (*interrupt) (void)); +void MyTimer_PWM(TIM_TypeDef * Timer, char Channel); +void MyTimer_PWM_Setup(TIM_TypeDef * Timer, char dutycycle, char channel); +#define MyTimer_Base_Start(Timer) Timer->CR1 |= 1 +#define MyTimer_Base_Stop(Timer) Timer->CR1 &= 0 + +#endif \ No newline at end of file diff --git a/Drivers/MyUART.h b/Drivers/MyUART.h new file mode 100644 index 0000000..3ccf159 --- /dev/null +++ b/Drivers/MyUART.h @@ -0,0 +1,11 @@ +#ifndef MyUART_H +#define MyUART_H + +#include "stm32f10x.h" + +void MyUART_Init(USART_TypeDef *USART); +void MyUART_Emission(USART_TypeDef *USART, char data); +void MyUART_Activ_IT(USART_TypeDef *USART, char Prio, void (*interrupt) (void)); +char MyUART_Get(USART_TypeDef *USART); + +#endif \ No newline at end of file diff --git a/Drivers/My_UART.c b/Drivers/My_UART.c new file mode 100644 index 0000000..d79233b --- /dev/null +++ b/Drivers/My_UART.c @@ -0,0 +1,87 @@ +#include "stm32f10x.h" + + +void (*pointeur_fonction_USART1)(void); +void (*pointeur_fonction_USART2)(void); +void (*pointeur_fonction_USART3)(void); + + +void MyUART_Init(USART_TypeDef *USART) +{ + if (USART == USART1){ + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + NVIC->ISER[1] |= (0x1 << 5); + NVIC->IPR[44]=10; + USART->BRR=72000000/9600; + + }else if (USART == USART2){ + RCC->APB1ENR |= RCC_APB1ENR_USART2EN; + NVIC->ISER[1] |= (0x1 << 6); + NVIC->IPR[44]=10; + USART->BRR=36000000/9600; + + }else if (USART == USART3){ + RCC->APB1ENR |= RCC_APB1ENR_USART3EN; + NVIC->ISER[1] |= (0x1 << 7); + NVIC->IPR[44]=10; + USART->BRR=36000000/9600; + + } + + USART -> CR1 |= USART_CR1_UE; //uart enable +// USART->CR1 |= USART_CR1_M; //donnee de 8 bits ???????????????? + USART -> CR1 |= USART_CR1_TE; //transmission enable + USART -> CR1 |= USART_CR1_RE; //recp enable + USART -> CR1 |= USART_CR1_RXNEIE; //interruption recep enable + +} + +char MyUART_Get(USART_TypeDef *USART) +{ + return USART->DR; +} + +void MyUART_Activ_IT(USART_TypeDef *USART, char Prio, void (*interrupt) (void)){ + if (USART == USART1){ + NVIC->ISER[1] |= (0x1 << 5); + NVIC->IPR[44] = Prio<<4; + pointeur_fonction_USART1=interrupt; + + }else if (USART == USART2){ + NVIC->ISER[1] |= (0x1 << 6); + NVIC->IPR[45]=Prio<<4; + pointeur_fonction_USART2=interrupt; + + }else if (USART == USART3){ + NVIC->ISER[1] |= (0x1 << 7); + NVIC->IPR[46]=Prio<<4; + pointeur_fonction_USART3=interrupt; + } +} + +void MyUART_Emission(USART_TypeDef *USART, char data){ + USART->DR=data; +// int i = 0; +// while (data[i]!=0){ +// USART->DR = data[i]; +// while ((USART->SR & (0x1 << 0x7))==0){ +// ; +// } +// i++; +// } +} + +void USART1_IRQHandler (void) +{ + pointeur_fonction_USART1(); +} + +void USART2_IRQHandler (void) +{ + pointeur_fonction_USART2(); +} + +void USART3_IRQHandler (void) +{ + pointeur_fonction_USART3(); +} \ No newline at end of file diff --git a/Drivers/adc.c b/Drivers/adc.c new file mode 100644 index 0000000..e1bed5f --- /dev/null +++ b/Drivers/adc.c @@ -0,0 +1,19 @@ +#include "adc.h" +#include "stm32f10x.h" + + +void ADC_Base_Init(ADC_TypeDef * ADC, char channel) +{ + RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6;//divise par 6 freq adcs + ADC->SQR3 |= channel; + ADC->CR2 |= ADC_CR2_ADON;//ADON + ADC->CR2 |= ADC_CR2_EXTTRIG;//Extrig + ADC->CR2 &= ~(0x1<<1);//discoutinuous + ADC->CR1 |= ADC_CR1_EOCIE;//interrupt enable + ADC->CR2 |= ADC_CR2_EXTSEL_0 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_2;//SWSTART +} + + + + +void ADC_Read(ADC_TypeDef * ADC); \ No newline at end of file diff --git a/Drivers/adc.h b/Drivers/adc.h new file mode 100644 index 0000000..c737399 --- /dev/null +++ b/Drivers/adc.h @@ -0,0 +1,9 @@ +#ifndef ADC_H +#define ADC_H + +#include "stm32f10x.h" + +void ADC_Base_Init(ADC_TypeDef * ADC,char channel); +void ADC_Read(ADC_TypeDef * ADC); + +#endif \ No newline at end of file diff --git a/Drivers/gpio.c b/Drivers/gpio.c new file mode 100644 index 0000000..81d6d69 --- /dev/null +++ b/Drivers/gpio.c @@ -0,0 +1,73 @@ +#include "gpio.h" + +void gpio_init( GPIO_TypeDef* gpio, char pin, char conf) +{ + if(gpio == GPIOA){ + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;//lance GPIOA + }else if (gpio == GPIOB){ + RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; + }else if (gpio == GPIOC){ + RCC->APB2ENR |= RCC_APB2ENR_IOPCEN; + } + //RCC->APB2ENR |= (0x01 << 2) | (0x01 << 3) | (0x01 << 4) ;//fait tourner tous les gpio + if(conf == 0x8){ + if (pin < 8) + { + gpio->CRL= gpio->CRL &~(0xF<<(pin*4)); + gpio->CRL= gpio->CRL | conf<<(pin*4); + gpio->ODR&=~(0x1<CRH= gpio->CRH &~(0xF<<((pin-8)*4)); + gpio->CRH= gpio->CRH | conf<<((pin-8)*4); + gpio->ODR&=~(0x1<CRL= gpio->CRL &~(0xF<<(pin*4)); + gpio->CRL= gpio->CRL | conf<<(pin*4); + gpio->ODR&=(0x1<CRH= gpio->CRH &~(0xF<<((pin-8)*4)); + gpio->CRH= gpio->CRH | conf<<((pin-8)*4); + gpio->ODR&=(0x1<CRL= gpio->CRL &~(0xF<<(pin*4)); + gpio->CRL= gpio->CRL | conf<<(pin*4); + } + else{ + gpio->CRH= gpio->CRH &~(0xF<<((pin-8)*4)); + gpio->CRH= gpio->CRH | conf<<((pin-8)*4); + } + } +} + + +int gpio_read(GPIO_TypeDef *gpio, char gpio_Pin) +{ + return (gpio->IDR)&(0x1<BSRR = (0x1 << gpio_Pin); +} + +void gpio_reset(GPIO_TypeDef *gpio, char gpio_Pin) +{ + gpio->BSRR = (0x1 << (gpio_Pin + 16)); +} + +void gpio_toggle(GPIO_TypeDef *gpio, char gpio_Pin) +{ + if(((gpio->ODR)&(0x1<APB2ENR |= (0x01 << 2) | (0x01 << 3) | (0x01 << 4) ; +// gpio_init(GPIOA,13,Out_Ppull); +// gpio_set(GPIOA,3); +// gpio_toggle(GPIOA,3); +// gpio_set(GPIOA,14); +// char car=5; + gpio_init(GPIOA,6,0xA); + gpio_init(GPIOA,11,2); + gpio_init(GPIOA,10,4); + MyUART_Init(USART1); + MyUART_Activ_IT(USART1, 10, MyUART_Reception); + //MyUART_Emission(USART1,car); + MyTimer_Base_Init(TIM3,3600,1); + MyTimer_PWM(TIM3,1); + + + + while (1) + { + //MyTimer_PWM_Setup(TIM3,toto,1); + } +} \ No newline at end of file diff --git a/Drivertest/Drivertest.uvoptx b/Drivertest/Drivertest.uvoptx new file mode 100644 index 0000000..2c2331d --- /dev/null +++ b/Drivertest/Drivertest.uvoptx @@ -0,0 +1,512 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Simulation + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + .\simu.ini + + + + + + BIN\UL2CM3.DLL + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + 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1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + 0 + ((porta & 0x00000040) >> 6 & 0x40) >> 6 + 00800000000000000000000000000000E0FFEF400100000000000000000000000000000028706F7274612026203078303030303030343029203E3E2036000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F0B00000000000000000000000000000000000000A4080008 + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Reel + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + .\simu.ini + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=1402,186,1996,880,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U066BFF545152717267243741 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 -WK0-R0 + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1101,123,1522,550,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=780,143,1374,894,0)(133=-1,-1,-1,-1,0)(160=1109,286,1557,700,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + + 0 + 1 + toto,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Application + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\Application\principal.c + principal.c + 0 + 0 + + + + + Services + 0 + 0 + 0 + 0 + + + + Drivers + 1 + 0 + 0 + 0 + + 3 + 2 + 1 + 1 + 0 + 0 + ..\Drivers\gpio.c + gpio.c + 0 + 0 + + + 3 + 3 + 1 + 0 + 0 + 0 + ..\Drivers\My_UART.c + My_UART.c + 0 + 0 + + + 3 + 4 + 5 + 0 + 0 + 0 + ..\Drivers\MyUART.h + MyUART.h + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\Drivers\MyTimer.c + MyTimer.c + 0 + 0 + + + 3 + 6 + 5 + 0 + 0 + 0 + ..\Drivers\MyTimer.h + MyTimer.h + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/Drivertest/Drivertest.uvprojx b/Drivertest/Drivertest.uvprojx new file mode 100644 index 0000000..976a98c --- /dev/null +++ b/Drivertest/Drivertest.uvprojx @@ -0,0 +1,922 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Simulation + 0x4 + ARM-ADS + 6230000::V6.23::ARMCLANG + 1 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.4.1 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + 4231 + $$Device:STM32F103RB$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + ProjetVide + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\Drivers;..\projetLEDD + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application + + + principal.c + 1 + .\Application\principal.c + + + + + Services + + + Drivers + + + gpio.c + 1 + ..\Drivers\gpio.c + + + My_UART.c + 1 + ..\Drivers\My_UART.c + + + MyUART.h + 5 + ..\Drivers\MyUART.h + + + MyTimer.c + 1 + ..\Drivers\MyTimer.c + + + MyTimer.h + 5 + ..\Drivers\MyTimer.h + + + + + ::CMSIS + + + ::Device + + + + + Reel + 0x4 + ARM-ADS + 6230000::V6.23::ARMCLANG + 1 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.4.1 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + 4231 + $$Device:STM32F103RB$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + ProjetVide + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\Drivers;..\projetLEDD + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application + + + principal.c + 1 + .\Application\principal.c + + + + + Services + + + Drivers + + + gpio.c + 1 + ..\Drivers\gpio.c + + + My_UART.c + 1 + ..\Drivers\My_UART.c + + + MyUART.h + 5 + ..\Drivers\MyUART.h + + + MyTimer.c + 1 + ..\Drivers\MyTimer.c + + + MyTimer.h + 5 + ..\Drivers\MyTimer.h + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F103RB\RTE_Device.h + + + + + + + + + RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + + + + + + + RTE\Device\STM32F103RB\system_stm32f10x.c + + + + + + + + + + + + + + Projet3FISA + 1 + ProjetVide + + + + + diff --git a/Drivertest/RTE/Device/STM32F103RB/RTE_Device.h b/Drivertest/RTE/Device/STM32F103RB/RTE_Device.h new file mode 100644 index 0000000..70c8002 --- /dev/null +++ b/Drivertest/RTE/Device/STM32F103RB/RTE_Device.h @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/Drivertest/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 b/Drivertest/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 new file mode 100644 index 0000000..70c8002 --- /dev/null +++ b/Drivertest/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/Drivertest/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 b/Drivertest/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 new file mode 100644 index 0000000..9c4804d --- /dev/null +++ b/Drivertest/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/Drivertest/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/Drivertest/RTE/Device/STM32F103RB/startup_stm32f10x_md.s new file mode 100644 index 0000000..3db5920 --- /dev/null +++ b/Drivertest/RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/Drivertest/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 b/Drivertest/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 new file mode 100644 index 0000000..3db5920 --- /dev/null +++ b/Drivertest/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/Drivertest/RTE/Device/STM32F103RB/system_stm32f10x.c b/Drivertest/RTE/Device/STM32F103RB/system_stm32f10x.c new file mode 100644 index 0000000..3301967 --- /dev/null +++ b/Drivertest/RTE/Device/STM32F103RB/system_stm32f10x.c @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivertest/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 b/Drivertest/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 new file mode 100644 index 0000000..3301967 --- /dev/null +++ b/Drivertest/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivertest/RTE/_Reel/RTE_Components.h b/Drivertest/RTE/_Reel/RTE_Components.h new file mode 100644 index 0000000..e14b2f6 --- /dev/null +++ b/Drivertest/RTE/_Reel/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'projetLEDD' + * Target: 'Reel' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivertest/RTE/_Simulation/RTE_Components.h b/Drivertest/RTE/_Simulation/RTE_Components.h new file mode 100644 index 0000000..30d8459 --- /dev/null +++ b/Drivertest/RTE/_Simulation/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'projetLEDD' + * Target: 'Simulation' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivertest/projetLEDD.uvoptx b/Drivertest/projetLEDD.uvoptx new file mode 100644 index 0000000..942c0a0 --- /dev/null +++ b/Drivertest/projetLEDD.uvoptx @@ -0,0 +1,450 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Reel + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + .\simu.ini + + + + + .\reel.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=638,234,1284,907,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1333,301,1754,706,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U066EFF323535474B43174430 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 -WK0-R0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Simulation + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + .\simu.ini + + + + + .\simu.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + 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b/projetLEDD/RTE/Device/STM32F103RB/RTE_Device.h @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/projetLEDD/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 b/projetLEDD/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 new file mode 100644 index 0000000..70c8002 --- /dev/null +++ b/projetLEDD/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/projetLEDD/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 b/projetLEDD/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 new file mode 100644 index 0000000..9c4804d --- /dev/null +++ b/projetLEDD/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/projetLEDD/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/projetLEDD/RTE/Device/STM32F103RB/startup_stm32f10x_md.s new file mode 100644 index 0000000..3db5920 --- /dev/null +++ b/projetLEDD/RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/projetLEDD/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 b/projetLEDD/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 new file mode 100644 index 0000000..3db5920 --- /dev/null +++ b/projetLEDD/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/projetLEDD/RTE/Device/STM32F103RB/system_stm32f10x.c b/projetLEDD/RTE/Device/STM32F103RB/system_stm32f10x.c new file mode 100644 index 0000000..3301967 --- /dev/null +++ b/projetLEDD/RTE/Device/STM32F103RB/system_stm32f10x.c @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/projetLEDD/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 b/projetLEDD/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 new file mode 100644 index 0000000..3301967 --- /dev/null +++ b/projetLEDD/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/projetLEDD/RTE/_Reel/RTE_Components.h b/projetLEDD/RTE/_Reel/RTE_Components.h new file mode 100644 index 0000000..e14b2f6 --- /dev/null +++ b/projetLEDD/RTE/_Reel/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'projetLEDD' + * Target: 'Reel' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/projetLEDD/RTE/_Simulation/RTE_Components.h b/projetLEDD/RTE/_Simulation/RTE_Components.h new file mode 100644 index 0000000..30d8459 --- /dev/null +++ b/projetLEDD/RTE/_Simulation/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'projetLEDD' + * Target: 'Simulation' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/projetLEDD/projetLEDD.uvoptx b/projetLEDD/projetLEDD.uvoptx new file mode 100644 index 0000000..942c0a0 --- /dev/null +++ b/projetLEDD/projetLEDD.uvoptx @@ -0,0 +1,450 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Reel + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + .\simu.ini + + + + + .\reel.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=638,234,1284,907,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1333,301,1754,706,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U066EFF323535474B43174430 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 -WK0-R0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Simulation + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + .\simu.ini + + + + + .\simu.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=638,234,1284,907,0)(110=1199,192,1419,652,0)(111=1025,230,1245,690,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=835,180,1256,607,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Application + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\Application\principal.c + principal.c + 0 + 0 + + + + + Services + 0 + 0 + 0 + 0 + + + + Drivers + 1 + 0 + 0 + 0 + + 3 + 2 + 5 + 0 + 0 + 0 + ..\Drivers\gpio.h + gpio.h + 0 + 0 + + + 3 + 3 + 1 + 0 + 0 + 0 + ..\Drivers\gpio.c + gpio.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/projetLEDD/projetLEDD.uvprojx b/projetLEDD/projetLEDD.uvprojx new file mode 100644 index 0000000..9c83c24 --- /dev/null +++ b/projetLEDD/projetLEDD.uvprojx @@ -0,0 +1,892 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Reel + 0x4 + ARM-ADS + 6230000::V6.23::ARMCLANG + 1 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.4.1 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + 4231 + $$Device:STM32F103RB$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Projet3FISA + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application + + + principal.c + 1 + .\Application\principal.c + + + + + Services + + + Drivers + + + gpio.h + 5 + ..\Drivers\gpio.h + + + gpio.c + 1 + ..\Drivers\gpio.c + + + + + ::CMSIS + + + ::Device + + + + + Simulation + 0x4 + ARM-ADS + 6230000::V6.23::ARMCLANG + 1 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.4.1 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + 4231 + $$Device:STM32F103RB$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + ProjetVide + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\Drivers;..\projetLEDD + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application + + + principal.c + 1 + .\Application\principal.c + + + + + Services + + + Drivers + + + gpio.h + 5 + ..\Drivers\gpio.h + + + gpio.c + 1 + ..\Drivers\gpio.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F103RB\RTE_Device.h + + + + + + + + + RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + + + + + + + RTE\Device\STM32F103RB\system_stm32f10x.c + + + + + + + + + + + + + + Projet3FISA + 1 + ProjetVide + + + + + diff --git a/projetLEDD/reel.ini b/projetLEDD/reel.ini new file mode 100644 index 0000000..7442113 --- /dev/null +++ b/projetLEDD/reel.ini @@ -0,0 +1 @@ +OSC = 8000000 diff --git a/projetLEDD/simu.ini b/projetLEDD/simu.ini new file mode 100644 index 0000000..7442113 --- /dev/null +++ b/projetLEDD/simu.ini @@ -0,0 +1 @@ +OSC = 8000000 diff --git a/timer/Application/principal.c b/timer/Application/principal.c new file mode 100644 index 0000000..2b2c342 --- /dev/null +++ b/timer/Application/principal.c @@ -0,0 +1,46 @@ +#include "stm32f10x.h" +#include "gpio.h" +#include "MyTimer.h" +#include "adc.h" + +void clignot(void){ + gpio_toggle(GPIOA,13); +} + +int main ( void ) +{ + //RCC->APB2ENR |= (0x01 << 2) | (0x01 << 3) | (0x01 << 4) ; +// TIM2->CR1 |= 1; +// TIM2->ARR=6000; +// TIM2->PSC=6000; + +// MyTimer_Base_Init(TIM2,6000,6000); +// TIM2->DIER |= 1;//tim2 transmet flag uif +// MyTimer_ActiveIT(TIM2, 4, clignot); +// NVIC->ISER[0] |= NVIC_ISER_SETENA_25; //tim2 ligne 28 +// TIM2->CCR1 = 2000; +// MyTimer_PWM(TIM2, 1); + + +// MyTimer_Base_Init(TIM4,720,1); +// TIM2->DIER |= 1;//tim2 transmet flag uif +// NVIC->ISER[0] |= NVIC_ISER_SETENA_25; //tim2 ligne 28 +// TIM4->CCR1 = 2000; +// MyTimer_PWM(TIM4, 1); +// MyTimer_PWM_Setup(TIM4,20,1); +// +// gpio_init( GPIOB, 6 , AltOut_Ppull); + + +// ADC + + + ADC_Base_Init(ADC1,1); + + while (1) + { + + } +} + + diff --git a/timer/Drivertest.uvoptx b/timer/Drivertest.uvoptx new file mode 100644 index 0000000..77497b8 --- /dev/null +++ b/timer/Drivertest.uvoptx @@ -0,0 +1,446 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Reel + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Simulation + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + .\simu.ini + + + + + + BIN\UL2CM3.DLL + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1101,123,1522,550,1)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + 0 + 5 + 1 +
134219392
+ 0 + 0 + 0 + 0 + 0 + 1 + U:\4AE\µC\Drivertest\Application\principal.c + + \\ProjetVide\Application/principal.c\5 + + + 1 + 0 + 8 + 1 +
134219422
+ 0 + 0 + 0 + 0 + 0 + 1 + U:\4AE\µC\Drivertest\Application\principal.c + + \\ProjetVide\Application/principal.c\8 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Application + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\Application\principal.c + principal.c + 0 + 0 + + + + + Services + 0 + 0 + 0 + 0 + + + + Drivers + 1 + 0 + 0 + 0 + + 3 + 2 + 1 + 0 + 0 + 0 + ..\Drivers\gpio.c + gpio.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/timer/RTE/Device/STM32F103RB/RTE_Device.h b/timer/RTE/Device/STM32F103RB/RTE_Device.h new file mode 100644 index 0000000..70c8002 --- /dev/null +++ b/timer/RTE/Device/STM32F103RB/RTE_Device.h @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/timer/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 b/timer/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 new file mode 100644 index 0000000..70c8002 --- /dev/null +++ b/timer/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/timer/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 b/timer/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 new file mode 100644 index 0000000..9c4804d --- /dev/null +++ b/timer/RTE/Device/STM32F103RB/STM32F101_102_103_105_107.dbgconf.base@1.0.0 @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/timer/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/timer/RTE/Device/STM32F103RB/startup_stm32f10x_md.s new file mode 100644 index 0000000..3db5920 --- /dev/null +++ b/timer/RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/timer/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 b/timer/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 new file mode 100644 index 0000000..3db5920 --- /dev/null +++ b/timer/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.base@1.0.1 @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/timer/RTE/Device/STM32F103RB/system_stm32f10x.c b/timer/RTE/Device/STM32F103RB/system_stm32f10x.c new file mode 100644 index 0000000..3301967 --- /dev/null +++ b/timer/RTE/Device/STM32F103RB/system_stm32f10x.c @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/timer/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 b/timer/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 new file mode 100644 index 0000000..3301967 --- /dev/null +++ b/timer/RTE/Device/STM32F103RB/system_stm32f10x.c.base@1.0.1 @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/timer/RTE/_Reel/RTE_Components.h b/timer/RTE/_Reel/RTE_Components.h new file mode 100644 index 0000000..e14b2f6 --- /dev/null +++ b/timer/RTE/_Reel/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'projetLEDD' + * Target: 'Reel' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/timer/RTE/_Simulation/RTE_Components.h b/timer/RTE/_Simulation/RTE_Components.h new file mode 100644 index 0000000..30d8459 --- /dev/null +++ b/timer/RTE/_Simulation/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'projetLEDD' + * Target: 'Simulation' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/timer/projetLEDD.uvoptx b/timer/projetLEDD.uvoptx new file mode 100644 index 0000000..942c0a0 --- /dev/null +++ b/timer/projetLEDD.uvoptx @@ -0,0 +1,450 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Reel + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + .\simu.ini + + + + + .\reel.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=638,234,1284,907,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1333,301,1754,706,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U066EFF323535474B43174430 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 -WK0-R0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Simulation + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + .\simu.ini + + + + + .\simu.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=638,234,1284,907,0)(110=1199,192,1419,652,0)(111=1025,230,1245,690,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=835,180,1256,607,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Application + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\Application\principal.c + principal.c + 0 + 0 + + + + + Services + 0 + 0 + 0 + 0 + + + + Drivers + 1 + 0 + 0 + 0 + + 3 + 2 + 5 + 0 + 0 + 0 + ..\Drivers\gpio.h + gpio.h + 0 + 0 + + + 3 + 3 + 1 + 0 + 0 + 0 + ..\Drivers\gpio.c + gpio.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/timer/reel.ini b/timer/reel.ini new file mode 100644 index 0000000..7442113 --- /dev/null +++ b/timer/reel.ini @@ -0,0 +1 @@ +OSC = 8000000 diff --git a/timer/simu.ini b/timer/simu.ini new file mode 100644 index 0000000..7442113 --- /dev/null +++ b/timer/simu.ini @@ -0,0 +1 @@ +OSC = 8000000 diff --git a/timer/timer.uvoptx b/timer/timer.uvoptx new file mode 100644 index 0000000..f0b5575 --- /dev/null +++ b/timer/timer.uvoptx @@ -0,0 +1,543 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Reel + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Simulation + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + .\simu.ini + + + + + + BIN\UL2CM3.DLL + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=582,194,958,751,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1596,725,2017,1152,0)(121=1520,456,1941,883,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=106,145,505,490,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=1307,165,1901,916,0)(131=1122,174,1716,925,0)(132=-1,-1,-1,-1,0)(133=990,195,1584,946,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=1299,217,1902,968,0)(151=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + 0 + 105 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Reel + 0x4 + ARM-ADS + 6230000::V6.23::ARMCLANG + 1 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.4.1 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + 4231 + $$Device:STM32F103RB$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Projet3FISA + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application + + + principal.c + 1 + .\Application\principal.c + + + + + Services + + + Drivers + + + gpio.c + 1 + ..\Drivers\gpio.c + + + MyTimer.c + 1 + ..\Drivers\MyTimer.c + + + adc.c + 1 + ..\Drivers\adc.c + + + adc.h + 5 + ..\Drivers\adc.h + + + + + ::CMSIS + + + ::Device + + + + + Simulation + 0x4 + ARM-ADS + 6230000::V6.23::ARMCLANG + 1 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.4.1 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + 4231 + $$Device:STM32F103RB$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + ProjetVide + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\Drivers;..\projetLEDD + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application + + + principal.c + 1 + .\Application\principal.c + + + + + Services + + + Drivers + + + gpio.c + 1 + ..\Drivers\gpio.c + + + MyTimer.c + 1 + ..\Drivers\MyTimer.c + + + adc.c + 1 + ..\Drivers\adc.c + + + adc.h + 5 + ..\Drivers\adc.h + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F103RB\RTE_Device.h + + + + + + + + + RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + + + + + + + RTE\Device\STM32F103RB\system_stm32f10x.c + + + + + + + + + + + + + + Projet3FISA + 1 + ProjetVide + + + + +