ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
+
+
+
+Function Pointers
+
+ - ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI9_5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text)
+
- TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_TRG_COM_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_UP_IRQHandler from mytimer.o(i.TIM1_UP_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM2_IRQHandler from mytimer.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM3_IRQHandler from mytimer.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM4_IRQHandler from mytimer.o(i.TIM4_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
+
- USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text)
+
- main from principal.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
+
+
+
+Global Symbols
+
+__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(.text)
+
+_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
+
+
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Calls]
+
+__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Called By]
+
+_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
+
+
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
+
+
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
+
+
__rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E))
+
+
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F))
+
+
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011))
+
+
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
+
NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+__aeabi_dadd (Thumb, 322 bytes, Stack size 48 bytes, dadd.o(.text))
+
[Stack]
- Max Depth = 88
- Call Chain = __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
+
+
[Calls]- >> __aeabi_lasr
+
- >> __aeabi_llsl
+
- >> _double_round
+
- >> _double_epilogue
+
+
[Called By]- >> __aeabi_dsub
+
- >> __aeabi_drsub
+
- >> bordage
+
+
+__aeabi_dsub (Thumb, 6 bytes, Stack size 0 bytes, dadd.o(.text), UNUSED)
+
[Calls]
+
+__aeabi_drsub (Thumb, 6 bytes, Stack size 0 bytes, dadd.o(.text))
+
[Stack]
- Max Depth = 88
- Call Chain = __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
+
+
[Calls]
+
[Called By]
+
+__aeabi_ddiv (Thumb, 222 bytes, Stack size 32 bytes, ddiv.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = __aeabi_ddiv ⇒ _double_round
+
+
[Calls]
+
[Called By]
+
+__aeabi_i2d (Thumb, 34 bytes, Stack size 16 bytes, dflti.o(.text))
+
[Stack]
- Max Depth = 56
- Call Chain = __aeabi_i2d ⇒ _double_epilogue ⇒ _double_round
+
+
[Calls]
+
[Called By]
+
+__aeabi_f2uiz (Thumb, 40 bytes, Stack size 0 bytes, ffixui.o(.text))
+
[Called By]
+
+__aeabi_f2d (Thumb, 38 bytes, Stack size 0 bytes, f2d.o(.text))
+
[Called By]
+
+__aeabi_d2f (Thumb, 56 bytes, Stack size 8 bytes, d2f.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = __aeabi_d2f
+
+
[Calls]
+
[Called By]
+
+__aeabi_llsl (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))
+
[Called By]
- >> _double_epilogue
+
- >> __aeabi_dadd
+
+
+_ll_shift_l (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
+
+
__aeabi_lasr (Thumb, 36 bytes, Stack size 0 bytes, llsshr.o(.text))
+
[Called By]
+
+_ll_sshift_r (Thumb, 0 bytes, Stack size 0 bytes, llsshr.o(.text), UNUSED)
+
+
__I$use$fp (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED)
+
+
_float_round (Thumb, 18 bytes, Stack size 0 bytes, fepilogue.o(.text))
+
[Called By]
+
+_float_epilogue (Thumb, 92 bytes, Stack size 4 bytes, fepilogue.o(.text), UNUSED)
+
+
_double_round (Thumb, 30 bytes, Stack size 8 bytes, depilogue.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = _double_round
+
+
[Called By]- >> _double_epilogue
+
- >> __aeabi_ddiv
+
- >> __aeabi_dadd
+
+
+_double_epilogue (Thumb, 156 bytes, Stack size 32 bytes, depilogue.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = _double_epilogue ⇒ _double_round
+
+
[Calls]- >> __aeabi_llsr
+
- >> __aeabi_llsl
+
- >> _double_round
+
+
[Called By]- >> __aeabi_i2d
+
- >> __aeabi_dadd
+
+
+__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
+
[Calls]
- >> __main_after_scatterload
+
+
[Called By]
+
+__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
+
+
__aeabi_llsr (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))
+
[Called By]
+
+_ll_ushift_r (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
+
+
MyGPIO_Activate (Thumb, 18 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Activate))
+
[Called By]
+
+MyGPIO_Init (Thumb, 166 bytes, Stack size 4 bytes, driver_gpio.o(i.MyGPIO_Init))
+
[Stack]
- Max Depth = 4
- Call Chain = MyGPIO_Init
+
+
[Calls]
+
[Called By]- >> bordage
+
- >> SPI_init_master
+
+
+MyGPIO_Reset (Thumb, 12 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Reset))
+
[Called By]
+
+MyGPIO_Set (Thumb, 8 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Set))
+
[Called By]
- >> lire
+
- >> SPI_init_master
+
- >> MyGPIO_Init
+
+
+MyTimer_Base_Init (Thumb, 106 bytes, Stack size 0 bytes, mytimer.o(i.MyTimer_Base_Init))
+
[Called By]
+
+MyTimer_PWM (Thumb, 120 bytes, Stack size 0 bytes, mytimer.o(i.MyTimer_PWM))
+
[Called By]
+
+Roulis_Handler (Thumb, 10 bytes, Stack size 8 bytes, bordage.o(i.Roulis_Handler))
+
[Stack]
- Max Depth = 152
- Call Chain = Roulis_Handler ⇒ bordage ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
+
+
[Calls]
+
[Called By]
+
+SPI_activate_clock (Thumb, 54 bytes, Stack size 0 bytes, driver_spi.o(i.SPI_activate_clock))
+
[Called By]
+
+SPI_init_master (Thumb, 182 bytes, Stack size 8 bytes, driver_spi.o(i.SPI_init_master))
+
[Stack]
- Max Depth = 12
- Call Chain = SPI_init_master ⇒ MyGPIO_Init
+
+
[Calls]- >> SPI_activate_clock
+
- >> MyGPIO_Set
+
- >> MyGPIO_Init
+
+
[Called By]
+
+SPI_rcv (Thumb, 36 bytes, Stack size 0 bytes, driver_spi.o(i.SPI_rcv))
+
[Called By]
+
+SPI_send (Thumb, 30 bytes, Stack size 0 bytes, driver_spi.o(i.SPI_send))
+
[Called By]
+
+Set_Duty_Cycle (Thumb, 76 bytes, Stack size 8 bytes, mytimer.o(i.Set_Duty_Cycle))
+
[Stack]
- Max Depth = 8
- Call Chain = Set_Duty_Cycle
+
+
[Called By]
+
+SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
+
[Stack]
- Max Depth = 28
- Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
+
+
[Calls]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(.text)
+
+TIM1_UP_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM1_UP_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM1_UP_IRQHandler
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+TIM2_IRQHandler (Thumb, 32 bytes, Stack size 8 bytes, mytimer.o(i.TIM2_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM2_IRQHandler
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+TIM3_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM3_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM3_IRQHandler
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+TIM4_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM4_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM4_IRQHandler
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
+
+
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
+
+
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
+
+
bordage (Thumb, 146 bytes, Stack size 56 bytes, bordage.o(i.bordage))
+
[Stack]
- Max Depth = 144
- Call Chain = bordage ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
+
+
[Calls]- >> __aeabi_i2d
+
- >> __aeabi_f2uiz
+
- >> __aeabi_f2d
+
- >> __aeabi_drsub
+
- >> __aeabi_ddiv
+
- >> __aeabi_dadd
+
- >> __aeabi_d2f
+
- >> Set_Duty_Cycle
+
- >> MyTimer_PWM
+
- >> MyTimer_Base_Init
+
- >> MyGPIO_Init
+
+
[Called By]
+
+chavirement_handler (Thumb, 44 bytes, Stack size 16 bytes, chavirement.o(i.chavirement_handler))
+
[Stack]
- Max Depth = 168
- Call Chain = chavirement_handler ⇒ Roulis_Handler ⇒ bordage ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
+
+
[Calls]- >> Roulis_Handler
+
- >> lire
+
+
[Called By]
+
+chavirement_init (Thumb, 20 bytes, Stack size 8 bytes, chavirement.o(i.chavirement_init))
+
[Stack]
- Max Depth = 24
- Call Chain = chavirement_init ⇒ lire
+
+
[Calls]- >> lire
+
- >> SPI_init_master
+
+
[Called By]
+
+lire (Thumb, 58 bytes, Stack size 16 bytes, chavirement.o(i.lire))
+
[Stack]
- Max Depth = 16
- Call Chain = lire
+
+
[Calls]- >> SPI_send
+
- >> SPI_rcv
+
- >> MyGPIO_Set
+
- >> MyGPIO_Reset
+
+
[Called By]- >> chavirement_init
+
- >> chavirement_handler
+
+
+main (Thumb, 30 bytes, Stack size 0 bytes, principal.o(i.main))
+
[Stack]
- Max Depth = 168
- Call Chain = main ⇒ chavirement_handler ⇒ Roulis_Handler ⇒ bordage ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
+
+
[Calls]- >> chavirement_init
+
- >> chavirement_handler
+
- >> MyGPIO_Activate
+
+
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
+
+
+Local Symbols
+
+SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
+
[Stack]
- Max Depth = 20
- Call Chain = SetSysClock ⇒ SetSysClockTo72
+
+
[Calls]
+
[Called By]
+
+SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
+
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
+
+
[Called By]
+
+
+Undefined Global Symbols
+
diff --git a/Keil_Commun/Objects/projet_chavirement.lnp b/Keil_Commun/Objects/projet_chavirement.lnp
new file mode 100644
index 0000000..4d2eb25
--- /dev/null
+++ b/Keil_Commun/Objects/projet_chavirement.lnp
@@ -0,0 +1,12 @@
+--cpu Cortex-M3
+".\objects\driver_gpio.o"
+".\objects\driver_spi.o"
+".\objects\mytimer.o"
+".\objects\principal.o"
+".\objects\chavirement.o"
+".\objects\bordage.o"
+".\objects\startup_stm32f10x_md.o"
+".\objects\system_stm32f10x.o"
+--library_type=microlib --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\Listings\projet_chavirement.map" -o .\Objects\projet_chavirement.axf
\ No newline at end of file
diff --git a/Keil_Commun/Objects/projet_chavirement_CarteSTM.dep b/Keil_Commun/Objects/projet_chavirement_CarteSTM.dep
new file mode 100644
index 0000000..349a7d4
--- /dev/null
+++ b/Keil_Commun/Objects/projet_chavirement_CarteSTM.dep
@@ -0,0 +1,85 @@
+Dependencies for Project 'projet_chavirement', Target 'CarteSTM': (DO NOT MODIFY !)
+CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
+F (..\Drivers\Driver_GPIO.c)(0x615B16FD)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_CarteSTM\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+F (..\Drivers\Driver_GPIO.h)(0x6155C0E0)()
+F (..\Drivers\Driver_SPI.c)(0x6189672A)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_spi.o --omf_browse .\objects\driver_spi.crf --depend .\objects\driver_spi.d)
+I (..\Drivers\Driver_SPI.h)(0x616FFEDD)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_CarteSTM\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+F (..\Drivers\Driver_SPI.h)(0x616FFEDD)()
+F (..\Drivers\MyTimer.c)(0x618531E2)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d)
+I (..\Drivers\MyTimer.h)(0x61852D2E)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_CarteSTM\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+F (..\Drivers\MyTimer.h)(0x61852D2E)()
+F (.\Local_Sources\principal.c)(0x61896043)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
+I (..\Sources\chavirement.h)(0x61853E09)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_CarteSTM\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+F (..\Sources\chavirement.c)(0x61896B2D)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\chavirement.o --omf_browse .\objects\chavirement.crf --depend .\objects\chavirement.d)
+I (..\Sources\chavirement.h)(0x61853E09)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_CarteSTM\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+I (..\Drivers\Driver_SPI.h)(0x616FFEDD)
+I (..\Sources\bordage.h)(0x618526E6)
+F (..\Sources\chavirement.h)(0x61853E09)()
+F (..\Sources\bordage.c)(0x61852EE4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\bordage.o --omf_browse .\objects\bordage.crf --depend .\objects\bordage.d)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_CarteSTM\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (..\Drivers\MyTimer.h)(0x61852D2E)
+I (..\Sources\bordage.h)(0x618526E6)
+F (..\Sources\bordage.h)(0x618526E6)()
+F (RTE\Device\STM32F103RB\RTE_Device.h)(0x61852267)()
+F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x6189683A)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 533" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
+F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x61852267)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_CarteSTM\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
diff --git a/Keil_Commun/Objects/projet_chavirement_Simulation.dep b/Keil_Commun/Objects/projet_chavirement_Simulation.dep
new file mode 100644
index 0000000..ac8fe15
--- /dev/null
+++ b/Keil_Commun/Objects/projet_chavirement_Simulation.dep
@@ -0,0 +1,84 @@
+Dependencies for Project 'projet_chavirement', Target 'Simulation': (DO NOT MODIFY !)
+CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
+F (..\Drivers\Driver_GPIO.c)(0x615B16FD)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simulation\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+F (..\Drivers\Driver_GPIO.h)(0x6155C0E0)()
+F (..\Drivers\Driver_SPI.c)(0x61852DD8)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_spi.o --omf_browse .\objects\driver_spi.crf --depend .\objects\driver_spi.d)
+I (..\Drivers\Driver_SPI.h)(0x616FFEDD)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simulation\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+F (..\Drivers\Driver_SPI.h)(0x616FFEDD)()
+F (..\Drivers\MyTimer.c)(0x618531E2)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d)
+I (..\Drivers\MyTimer.h)(0x61852D2E)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simulation\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+F (..\Drivers\MyTimer.h)(0x61852D2E)()
+F (.\Local_Sources\principal.c)(0x6185324D)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
+I (..\Sources\chavirement.h)(0x618518E6)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simulation\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+F (..\Sources\chavirement.c)(0x6185323C)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\chavirement.o --omf_browse .\objects\chavirement.crf --depend .\objects\chavirement.d)
+I (..\Sources\chavirement.h)(0x618518E6)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simulation\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+I (..\Drivers\Driver_SPI.h)(0x616FFEDD)
+I (..\Sources\bordage.h)(0x618526E6)
+F (..\Sources\chavirement.h)(0x618518E6)()
+F (..\Sources\bordage.c)(0x61852EE4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\bordage.o --omf_browse .\objects\bordage.crf --depend .\objects\bordage.d)
+I (..\Drivers\Driver_GPIO.h)(0x6155C0E0)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simulation\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (..\Drivers\MyTimer.h)(0x61852D2E)
+I (..\Sources\bordage.h)(0x618526E6)
+F (..\Sources\bordage.h)(0x618526E6)()
+F (RTE\Device\STM32F103RB\RTE_Device.h)(0x61852267)()
+F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x61852267)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 533" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
+F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x61852267)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\Includes -I ..\Sources -I ..\Drivers
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simulation\RTE_Components.h)(0x61852267)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
diff --git a/Keil_Commun/Objects/startup_stm32f10x_md.d b/Keil_Commun/Objects/startup_stm32f10x_md.d
new file mode 100644
index 0000000..96d5fcf
--- /dev/null
+++ b/Keil_Commun/Objects/startup_stm32f10x_md.d
@@ -0,0 +1 @@
+.\objects\startup_stm32f10x_md.o: RTE\Device\STM32F103RB\startup_stm32f10x_md.s
diff --git a/Keil_Commun/Objects/startup_stm32f10x_md.o b/Keil_Commun/Objects/startup_stm32f10x_md.o
new file mode 100644
index 0000000..83f2b87
Binary files /dev/null and b/Keil_Commun/Objects/startup_stm32f10x_md.o differ
diff --git a/Keil_Commun/Objects/system_stm32f10x.crf b/Keil_Commun/Objects/system_stm32f10x.crf
new file mode 100644
index 0000000..85a4e63
Binary files /dev/null and b/Keil_Commun/Objects/system_stm32f10x.crf differ
diff --git a/Keil_Commun/Objects/system_stm32f10x.d b/Keil_Commun/Objects/system_stm32f10x.d
new file mode 100644
index 0000000..b0d089a
--- /dev/null
+++ b/Keil_Commun/Objects/system_stm32f10x.d
@@ -0,0 +1,9 @@
+.\objects\system_stm32f10x.o: RTE\Device\STM32F103RB\system_stm32f10x.c
+.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
+.\objects\system_stm32f10x.o: .\RTE\_CarteSTM\RTE_Components.h
+.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/Keil_Commun/Objects/system_stm32f10x.o b/Keil_Commun/Objects/system_stm32f10x.o
new file mode 100644
index 0000000..3ee255d
Binary files /dev/null and b/Keil_Commun/Objects/system_stm32f10x.o differ
diff --git a/Keil_Commun/RTE/Device/STM32F103RB/RTE_Device.h b/Keil_Commun/RTE/Device/STM32F103RB/RTE_Device.h
new file mode 100644
index 0000000..22d1da2
--- /dev/null
+++ b/Keil_Commun/RTE/Device/STM32F103RB/RTE_Device.h
@@ -0,0 +1,1828 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2016 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software in
+ * a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date: 09. September 2016
+ * $Revision: V1.1.2
+ *
+ * Project: RTE Device Configuration for STMicroelectronics STM32F1xx
+ *
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+ (num == 1) ? GPIOB : \
+ (num == 2) ? GPIOC : \
+ (num == 3) ? GPIOD : \
+ (num == 4) ? GPIOE : \
+ (num == 5) ? GPIOF : \
+ (num == 6) ? GPIOG : \
+ NULL)
+
+
+// Clock Configuration
+// High-speed Internal Clock <1-999999999>
+#define RTE_HSI 8000000
+// High-speed External Clock <1-999999999>
+#define RTE_HSE 25000000
+// System Clock <1-999999999>
+#define RTE_SYSCLK 72000000
+// HCLK Clock <1-999999999>
+#define RTE_HCLK 72000000
+// APB1 Clock <1-999999999>
+#define RTE_PCLK1 36000000
+// APB2 Clock <1-999999999>
+#define RTE_PCLK2 72000000
+// ADC Clock <1-999999999>
+#define RTE_ADCCLK 36000000
+// USB Clock
+#define RTE_USBCLK 48000000
+//
+
+
+// USART1 (Universal synchronous asynchronous receiver transmitter)
+// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1 0
+
+// USART1_TX Pin <0=>Not Used <1=>PA9
+#define RTE_USART1_TX_PORT_ID_DEF 0
+#if (RTE_USART1_TX_PORT_ID_DEF == 0)
+#define RTE_USART1_TX_DEF 0
+#elif (RTE_USART1_TX_PORT_ID_DEF == 1)
+#define RTE_USART1_TX_DEF 1
+#define RTE_USART1_TX_PORT_DEF GPIOA
+#define RTE_USART1_TX_BIT_DEF 9
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+// USART1_RX Pin <0=>Not Used <1=>PA10
+#define RTE_USART1_RX_PORT_ID_DEF 0
+#if (RTE_USART1_RX_PORT_ID_DEF == 0)
+#define RTE_USART1_RX_DEF 0
+#elif (RTE_USART1_RX_PORT_ID_DEF == 1)
+#define RTE_USART1_RX_DEF 1
+#define RTE_USART1_RX_PORT_DEF GPIOA
+#define RTE_USART1_RX_BIT_DEF 10
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+// USART1_CK Pin <0=>Not Used <1=>PA8
+#define RTE_USART1_CK_PORT_ID_DEF 0
+#if (RTE_USART1_CK_PORT_ID_DEF == 0)
+#define RTE_USART1_CK 0
+#elif (RTE_USART1_CK_PORT_ID_DEF == 1)
+#define RTE_USART1_CK 1
+#define RTE_USART1_CK_PORT_DEF GPIOA
+#define RTE_USART1_CK_BIT_DEF 8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+// USART1_CTS Pin <0=>Not Used <1=>PA11
+#define RTE_USART1_CTS_PORT_ID_DEF 0
+#if (RTE_USART1_CTS_PORT_ID_DEF == 0)
+#define RTE_USART1_CTS 0
+#elif (RTE_USART1_CTS_PORT_ID_DEF == 1)
+#define RTE_USART1_CTS 1
+#define RTE_USART1_CTS_PORT_DEF GPIOA
+#define RTE_USART1_CTS_BIT_DEF 11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+
+// USART1_RTS Pin <0=>Not Used <1=>PA12
+#define RTE_USART1_RTS_PORT_ID_DEF 0
+#if (RTE_USART1_RTS_PORT_ID_DEF == 0)
+#define RTE_USART1_RTS 0
+#elif (RTE_USART1_RTS_PORT_ID_DEF == 1)
+#define RTE_USART1_RTS 1
+#define RTE_USART1_RTS_PORT_DEF GPIOA
+#define RTE_USART1_RTS_BIT_DEF 12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+// USART1 Pin Remap
+// Enable USART1 Pin Remapping
+#define RTE_USART1_REMAP_FULL 0
+
+// USART1_TX Pin <0=>Not Used <1=>PB6
+#define RTE_USART1_TX_PORT_ID_FULL 0
+#if (RTE_USART1_TX_PORT_ID_FULL == 0)
+#define RTE_USART1_TX_FULL 0
+#elif (RTE_USART1_TX_PORT_ID_FULL == 1)
+#define RTE_USART1_TX_FULL 1
+#define RTE_USART1_TX_PORT_FULL GPIOB
+#define RTE_USART1_TX_BIT_FULL 6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+// USART1_RX Pin <0=>Not Used <1=>PB7
+#define RTE_USART1_RX_PORT_ID_FULL 0
+#if (RTE_USART1_RX_PORT_ID_FULL == 0)
+#define RTE_USART1_RX_FULL 0
+#elif (RTE_USART1_RX_PORT_ID_FULL == 1)
+#define RTE_USART1_RX_FULL 1
+#define RTE_USART1_RX_PORT_FULL GPIOB
+#define RTE_USART1_RX_BIT_FULL 7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+//
+
+#if (RTE_USART1_REMAP_FULL)
+#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP
+#define RTE_USART1_TX RTE_USART1_TX_FULL
+#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL
+#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL
+#define RTE_USART1_RX RTE_USART1_RX_FULL
+#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL
+#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL
+#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
+#else
+#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP
+#define RTE_USART1_TX RTE_USART1_TX_DEF
+#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF
+#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF
+#define RTE_USART1_RX RTE_USART1_RX_DEF
+#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF
+#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF
+#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <5=>5
+// Selects DMA Channel (only Channel 5 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Set DMA Channel priority
+//
+#define RTE_USART1_RX_DMA 0
+#define RTE_USART1_RX_DMA_NUMBER 1
+#define RTE_USART1_RX_DMA_CHANNEL 5
+#define RTE_USART1_RX_DMA_PRIORITY 0
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <4=>4
+// Selects DMA Channel (only Channel 4 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Set DMA Channel priority
+//
+#define RTE_USART1_TX_DMA 0
+#define RTE_USART1_TX_DMA_NUMBER 1
+#define RTE_USART1_TX_DMA_CHANNEL 4
+#define RTE_USART1_TX_DMA_PRIORITY 0
+//
+
+
+// USART2 (Universal synchronous asynchronous receiver transmitter)
+// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_USART2 0
+
+// USART2_TX Pin <0=>Not Used <1=>PA2
+#define RTE_USART2_TX_PORT_ID_DEF 0
+#if (RTE_USART2_TX_PORT_ID_DEF == 0)
+#define RTE_USART2_TX_DEF 0
+#elif (RTE_USART2_TX_PORT_ID_DEF == 1)
+#define RTE_USART2_TX_DEF 1
+#define RTE_USART2_TX_PORT_DEF GPIOA
+#define RTE_USART2_TX_BIT_DEF 2
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+// USART2_RX Pin <0=>Not Used <1=>PA3
+#define RTE_USART2_RX_PORT_ID_DEF 0
+#if (RTE_USART2_RX_PORT_ID_DEF == 0)
+#define RTE_USART2_RX_DEF 0
+#elif (RTE_USART2_RX_PORT_ID_DEF == 1)
+#define RTE_USART2_RX_DEF 1
+#define RTE_USART2_RX_PORT_DEF GPIOA
+#define RTE_USART2_RX_BIT_DEF 3
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+// USART2_CK Pin <0=>Not Used <1=>PA4
+#define RTE_USART2_CK_PORT_ID_DEF 0
+#if (RTE_USART2_CK_PORT_ID_DEF == 0)
+#define RTE_USART2_CK_DEF 0
+#elif (RTE_USART2_CK_PORT_ID_DEF == 1)
+#define RTE_USART2_CK_DEF 1
+#define RTE_USART2_CK_PORT_DEF GPIOA
+#define RTE_USART2_CK_BIT_DEF 4
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+// USART2_CTS Pin <0=>Not Used <1=>PA0
+#define RTE_USART2_CTS_PORT_ID_DEF 0
+#if (RTE_USART2_CTS_PORT_ID_DEF == 0)
+#define RTE_USART2_CTS_DEF 0
+#elif (RTE_USART2_CTS_PORT_ID_DEF == 1)
+#define RTE_USART2_CTS_DEF 1
+#define RTE_USART2_CTS_PORT_DEF GPIOA
+#define RTE_USART2_CTS_BIT_DEF 0
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+// USART2_RTS Pin <0=>Not Used <1=>PA1
+#define RTE_USART2_RTS_PORT_ID_DEF 0
+#if (RTE_USART2_RTS_PORT_ID_DEF == 0)
+#define RTE_USART2_RTS_DEF 0
+#elif (RTE_USART2_RTS_PORT_ID_DEF == 1)
+#define RTE_USART2_RTS_DEF 1
+#define RTE_USART2_RTS_PORT_DEF GPIOA
+#define RTE_USART2_RTS_BIT_DEF 1
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+// USART2 Pin Remap
+// Enable USART2 Pin Remapping
+#define RTE_USART2_REMAP_FULL 0
+
+// USART2_TX Pin <0=>Not Used <1=>PD5
+#define RTE_USART2_TX_PORT_ID_FULL 0
+#if (RTE_USART2_TX_PORT_ID_FULL == 0)
+#define RTE_USART2_TX_FULL 0
+#elif (RTE_USART2_TX_PORT_ID_FULL == 1)
+#define RTE_USART2_TX_FULL 1
+#define RTE_USART2_TX_PORT_FULL GPIOD
+#define RTE_USART2_TX_BIT_FULL 5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+// USART2_RX Pin <0=>Not Used <1=>PD6
+#define RTE_USART2_RX_PORT_ID_FULL 0
+#if (RTE_USART2_RX_PORT_ID_FULL == 0)
+#define RTE_USART2_RX_FULL 0
+#elif (RTE_USART2_RX_PORT_ID_FULL == 1)
+#define RTE_USART2_RX_FULL 1
+#define RTE_USART2_RX_PORT_FULL GPIOD
+#define RTE_USART2_RX_BIT_FULL 6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+// USART2_CK Pin <0=>Not Used <1=>PD7
+#define RTE_USART2_CK_PORT_ID_FULL 0
+#if (RTE_USART2_CK_PORT_ID_FULL == 0)
+#define RTE_USART2_CK_FULL 0
+#elif (RTE_USART2_CK_PORT_ID_FULL == 1)
+#define RTE_USART2_CK_FULL 1
+#define RTE_USART2_CK_PORT_FULL GPIOD
+#define RTE_USART2_CK_BIT_FULL 7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+// USART2_CTS Pin <0=>Not Used <1=>PD3
+#define RTE_USART2_CTS_PORT_ID_FULL 0
+#if (RTE_USART2_CTS_PORT_ID_FULL == 0)
+#define RTE_USART2_CTS_FULL 0
+#elif (RTE_USART2_CTS_PORT_ID_FULL == 1)
+#define RTE_USART2_CTS_FULL 1
+#define RTE_USART2_CTS_PORT_FULL GPIOD
+#define RTE_USART2_CTS_BIT_FULL 3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+// USART2_RTS Pin <0=>Not Used <1=>PD4
+#define RTE_USART2_RTS_PORT_ID_FULL 0
+#if (RTE_USART2_RTS_PORT_ID_FULL == 0)
+#define RTE_USART2_RTS_FULL 0
+#elif (RTE_USART2_RTS_PORT_ID_FULL == 1)
+#define RTE_USART2_RTS_FULL 1
+#define RTE_USART2_RTS_PORT_FULL GPIOD
+#define RTE_USART2_RTS_BIT_FULL 4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+//
+
+#if (RTE_USART2_REMAP_FULL)
+#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP
+#define RTE_USART2_TX RTE_USART2_TX_FULL
+#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL
+#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL
+#define RTE_USART2_RX RTE_USART2_RX_FULL
+#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL
+#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL
+#define RTE_USART2_CK RTE_USART2_CK_FULL
+#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL
+#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL
+#define RTE_USART2_CTS RTE_USART2_CTS_FULL
+#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL
+#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL
+#define RTE_USART2_RTS RTE_USART2_RTS_FULL
+#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL
+#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL
+#else
+#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP
+#define RTE_USART2_TX RTE_USART2_TX_DEF
+#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF
+#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF
+#define RTE_USART2_RX RTE_USART2_RX_DEF
+#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF
+#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF
+#define RTE_USART2_CK RTE_USART2_CK_DEF
+#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF
+#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF
+#define RTE_USART2_CTS RTE_USART2_CTS_DEF
+#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF
+#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF
+#define RTE_USART2_RTS RTE_USART2_RTS_DEF
+#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF
+#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <6=>6
+// Selects DMA Channel (only Channel 6 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Set DMA Channel priority
+//
+#define RTE_USART2_RX_DMA 0
+#define RTE_USART2_RX_DMA_NUMBER 1
+#define RTE_USART2_RX_DMA_CHANNEL 6
+#define RTE_USART2_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <7=>7
+// Selects DMA Channel (only Channel 7 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Set DMA Channel priority
+//
+#define RTE_USART2_TX_DMA 0
+#define RTE_USART2_TX_DMA_NUMBER 1
+#define RTE_USART2_TX_DMA_CHANNEL 7
+#define RTE_USART2_TX_DMA_PRIORITY 0
+
+//
+
+
+// USART3 (Universal synchronous asynchronous receiver transmitter)
+// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_USART3 0
+
+// USART3_TX Pin <0=>Not Used <1=>PB10
+#define RTE_USART3_TX_PORT_ID_DEF 0
+#if (RTE_USART3_TX_PORT_ID_DEF == 0)
+#define RTE_USART3_TX_DEF 0
+#elif (RTE_USART3_TX_PORT_ID_DEF == 1)
+#define RTE_USART3_TX_DEF 1
+#define RTE_USART3_TX_PORT_DEF GPIOB
+#define RTE_USART3_TX_BIT_DEF 10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+// USART3_RX Pin <0=>Not Used <1=>PB11
+#define RTE_USART3_RX_PORT_ID_DEF 0
+#if (RTE_USART3_RX_PORT_ID_DEF == 0)
+#define RTE_USART3_RX_DEF 0
+#elif (RTE_USART3_RX_PORT_ID_DEF == 1)
+#define RTE_USART3_RX_DEF 1
+#define RTE_USART3_RX_PORT_DEF GPIOB
+#define RTE_USART3_RX_BIT_DEF 11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+// USART3_CK Pin <0=>Not Used <1=>PB12
+#define RTE_USART3_CK_PORT_ID_DEF 0
+#if (RTE_USART3_CK_PORT_ID_DEF == 0)
+#define RTE_USART3_CK_DEF 0
+#elif (RTE_USART3_CK_PORT_ID_DEF == 1)
+#define RTE_USART3_CK_DEF 1
+#define RTE_USART3_CK_PORT_DEF GPIOB
+#define RTE_USART3_CK_BIT_DEF 12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+// USART3_CTS Pin <0=>Not Used <1=>PB13
+#define RTE_USART3_CTS_PORT_ID_DEF 0
+#if (RTE_USART3_CTS_PORT_ID_DEF == 0)
+#define RTE_USART3_CTS_DEF 0
+#elif (RTE_USART3_CTS_PORT_ID_DEF == 1)
+#define RTE_USART3_CTS_DEF 1
+#define RTE_USART3_CTS_PORT_DEF GPIOB
+#define RTE_USART3_CTS_BIT_DEF 13
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+// USART3_RTS Pin <0=>Not Used <1=>PB14
+#define RTE_USART3_RTS_PORT_ID_DEF 0
+#if (RTE_USART3_RTS_PORT_ID_DEF == 0)
+#define RTE_USART3_RTS_DEF 0
+#elif (RTE_USART3_RTS_PORT_ID_DEF == 1)
+#define RTE_USART3_RTS_DEF 1
+#define RTE_USART3_RTS_PORT_DEF GPIOB
+#define RTE_USART3_RTS_BIT_DEF 14
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+// USART3 Partial Pin Remap
+// Enable USART3 Partial Pin Remapping
+#define RTE_USART3_REMAP_PARTIAL 0
+
+// USART3_TX Pin <0=>Not Used <1=>PC10
+#define RTE_USART3_TX_PORT_ID_PARTIAL 0
+#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_TX_PARTIAL 0
+#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_TX_PARTIAL 1
+#define RTE_USART3_TX_PORT_PARTIAL GPIOC
+#define RTE_USART3_TX_BIT_PARTIAL 10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+// USART3_RX Pin <0=>Not Used <1=>PC11
+#define RTE_USART3_RX_PORT_ID_PARTIAL 0
+#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_RX_PARTIAL 0
+#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_RX_PARTIAL 1
+#define RTE_USART3_RX_PORT_PARTIAL GPIOC
+#define RTE_USART3_RX_BIT_PARTIAL 11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+// USART3_CK Pin <0=>Not Used <1=>PC12
+#define RTE_USART3_CK_PORT_ID_PARTIAL 0
+#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_CK_PARTIAL 0
+#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_CK_PARTIAL 1
+#define RTE_USART3_CK_PORT_PARTIAL GPIOC
+#define RTE_USART3_CK_BIT_PARTIAL 12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+//
+
+// USART3 Full Pin Remap
+// Enable USART3 Full Pin Remapping
+#define RTE_USART3_REMAP_FULL 0
+
+// USART3_TX Pin <0=>Not Used <1=>PD8
+#define RTE_USART3_TX_PORT_ID_FULL 0
+#if (RTE_USART3_TX_PORT_ID_FULL == 0)
+#define RTE_USART3_TX_FULL 0
+#elif (RTE_USART3_TX_PORT_ID_FULL == 1)
+#define RTE_USART3_TX_FULL 1
+#define RTE_USART3_TX_PORT_FULL GPIOD
+#define RTE_USART3_TX_BIT_FULL 8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+// USART3_RX Pin <0=>Not Used <1=>PD9
+#define RTE_USART3_RX_PORT_ID_FULL 0
+#if (RTE_USART3_RX_PORT_ID_FULL == 0)
+#define RTE_USART3_RX_FULL 0
+#elif (RTE_USART3_RX_PORT_ID_FULL == 1)
+#define RTE_USART3_RX_FULL 1
+#define RTE_USART3_RX_PORT_FULL GPIOD
+#define RTE_USART3_RX_BIT_FULL 9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+// USART3_CK Pin <0=>Not Used <1=>PD10
+#define RTE_USART3_CK_PORT_ID_FULL 0
+#if (RTE_USART3_CK_PORT_ID_FULL == 0)
+#define RTE_USART3_CK_FULL 0
+#elif (RTE_USART3_CK_PORT_ID_FULL == 1)
+#define RTE_USART3_CK_FULL 1
+#define RTE_USART3_CK_PORT_FULL GPIOD
+#define RTE_USART3_CK_BIT_FULL 10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+// USART3_CTS Pin <0=>Not Used <1=>PD11
+#define RTE_USART3_CTS_PORT_ID_FULL 0
+#if (RTE_USART3_CTS_PORT_ID_FULL == 0)
+#define RTE_USART3_CTS_FULL 0
+#elif (RTE_USART3_CTS_PORT_ID_FULL == 1)
+#define RTE_USART3_CTS_FULL 1
+#define RTE_USART3_CTS_PORT_FULL GPIOD
+#define RTE_USART3_CTS_BIT_FULL 11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+// USART3_RTS Pin <0=>Not Used <1=>PD12
+#define RTE_USART3_RTS_PORT_ID_FULL 0
+#if (RTE_USART3_RTS_PORT_ID_FULL == 0)
+#define RTE_USART3_RTS_FULL 0
+#elif (RTE_USART3_RTS_PORT_ID_FULL == 1)
+#define RTE_USART3_RTS_FULL 1
+#define RTE_USART3_RTS_PORT_FULL GPIOD
+#define RTE_USART3_RTS_BIT_FULL 12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+//
+
+#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
+#error "Invalid USART3 Pin Remap Configuration!"
+#endif
+
+#if (RTE_USART3_REMAP_FULL)
+#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL
+#define RTE_USART3_TX RTE_USART3_TX_FULL
+#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL
+#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL
+#define RTE_USART3_RX RTE_USART3_RX_FULL
+#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL
+#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL
+#define RTE_USART3_CK RTE_USART3_CK_FULL
+#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL
+#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL
+#define RTE_USART3_CTS RTE_USART3_CTS_FULL
+#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL
+#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL
+#define RTE_USART3_RTS RTE_USART3_RTS_FULL
+#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL
+#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL
+#elif (RTE_USART3_REMAP_PARTIAL)
+#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL
+#define RTE_USART3_TX RTE_USART3_TX_PARTIAL
+#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL
+#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL
+#define RTE_USART3_RX RTE_USART3_RX_PARTIAL
+#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL
+#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL
+#define RTE_USART3_CK RTE_USART3_CK_PARTIAL
+#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL
+#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL
+#define RTE_USART3_CTS RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
+#else
+#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP
+#define RTE_USART3_TX RTE_USART3_TX_DEF
+#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF
+#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF
+#define RTE_USART3_RX RTE_USART3_RX_DEF
+#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF
+#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF
+#define RTE_USART3_CK RTE_USART3_CK_DEF
+#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF
+#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF
+#define RTE_USART3_CTS RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <3=>3
+// Selects DMA Channel (only Channel 3 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Sets DMA Channel priority
+//
+#define RTE_USART3_RX_DMA 0
+#define RTE_USART3_RX_DMA_NUMBER 1
+#define RTE_USART3_RX_DMA_CHANNEL 3
+#define RTE_USART3_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <2=>2
+// Selects DMA Channel (only Channel 2 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Sets DMA Channel priority
+//
+#define RTE_USART3_TX_DMA 0
+#define RTE_USART3_TX_DMA_NUMBER 1
+#define RTE_USART3_TX_DMA_CHANNEL 2
+#define RTE_USART3_TX_DMA_PRIORITY 0
+
+//
+
+
+// UART4 (Universal asynchronous receiver transmitter)
+// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
+#define RTE_UART4 0
+#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP
+
+// UART4_TX Pin <0=>Not Used <1=>PC10
+#define RTE_UART4_TX_ID 0
+#if (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX 0
+#elif (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX 1
+#define RTE_UART4_TX_PORT GPIOC
+#define RTE_UART4_TX_BIT 10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+// UART4_RX Pin <0=>Not Used <1=>PC11
+#define RTE_UART4_RX_ID 0
+#if (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX 0
+#elif (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX 1
+#define RTE_UART4_RX_PORT GPIOC
+#define RTE_UART4_RX_BIT 11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+
+// DMA Rx
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <3=>3
+// Selects DMA Channel (only Channel 3 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Sets DMA Channel priority
+//
+#define RTE_UART4_RX_DMA 0
+#define RTE_UART4_RX_DMA_NUMBER 2
+#define RTE_UART4_RX_DMA_CHANNEL 3
+#define RTE_UART4_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <5=>5
+// Selects DMA Channel (only Channel 5 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Sets DMA Channel priority
+//
+#define RTE_UART4_TX_DMA 0
+#define RTE_UART4_TX_DMA_NUMBER 2
+#define RTE_UART4_TX_DMA_CHANNEL 5
+#define RTE_UART4_TX_DMA_PRIORITY 0
+
+//
+
+
+// UART5 (Universal asynchronous receiver transmitter)
+// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
+#define RTE_UART5 0
+#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP
+
+// UART5_TX Pin <0=>Not Used <1=>PC12
+#define RTE_UART5_TX_ID 0
+#if (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX 0
+#elif (RTE_UART5_TX_ID == 1)
+#define RTE_UART5_TX 1
+#define RTE_UART5_TX_PORT GPIOC
+#define RTE_UART5_TX_BIT 12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+// UART5_RX Pin <0=>Not Used <1=>PD2
+#define RTE_UART5_RX_ID 0
+#if (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX 0
+#elif (RTE_UART5_RX_ID == 1)
+#define RTE_UART5_RX 1
+#define RTE_UART5_RX_PORT GPIOD
+#define RTE_UART5_RX_BIT 2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+//
+
+
+// I2C1 (Inter-integrated Circuit Interface 1)
+// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
+#define RTE_I2C1 0
+
+// I2C1_SCL Pin <0=>PB6
+#define RTE_I2C1_SCL_PORT_ID_DEF 0
+#if (RTE_I2C1_SCL_PORT_ID_DEF == 0)
+#define RTE_I2C1_SCL_PORT_DEF GPIOB
+#define RTE_I2C1_SCL_BIT_DEF 6
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+// I2C1_SDA Pin <0=>PB7
+#define RTE_I2C1_SDA_PORT_ID_DEF 0
+#if (RTE_I2C1_SDA_PORT_ID_DEF == 0)
+#define RTE_I2C1_SDA_PORT_DEF GPIOB
+#define RTE_I2C1_SDA_BIT_DEF 7
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+// I2C1 Pin Remap
+// Enable I2C1 Pin Remapping
+#define RTE_I2C1_REMAP_FULL 0
+
+// I2C1_SCL Pin <0=>PB8
+#define RTE_I2C1_SCL_PORT_ID_FULL 0
+#if (RTE_I2C1_SCL_PORT_ID_FULL == 0)
+#define RTE_I2C1_SCL_PORT_FULL GPIOB
+#define RTE_I2C1_SCL_BIT_FULL 8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+// I2C1_SDA Pin <0=>PB9
+#define RTE_I2C1_SDA_PORT_ID_FULL 0
+#if (RTE_I2C1_SDA_PORT_ID_FULL == 0)
+#define RTE_I2C1_SDA_PORT_FULL GPIOB
+#define RTE_I2C1_SDA_BIT_FULL 9
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//
+
+#if (RTE_I2C1_REMAP_FULL)
+#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP
+#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL
+#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL
+#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL
+#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL
+#else
+#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP
+#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF
+#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF
+#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF
+#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF
+#endif
+
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <7=>7
+// Selects DMA Channel (only Channel 7 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_I2C1_RX_DMA 0
+#define RTE_I2C1_RX_DMA_NUMBER 1
+#define RTE_I2C1_RX_DMA_CHANNEL 7
+#define RTE_I2C1_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <6=>6
+// Selects DMA Channel (only Channel 6 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_I2C1_TX_DMA 0
+#define RTE_I2C1_TX_DMA_NUMBER 1
+#define RTE_I2C1_TX_DMA_CHANNEL 6
+#define RTE_I2C1_TX_DMA_PRIORITY 0
+
+//
+
+
+// I2C2 (Inter-integrated Circuit Interface 2)
+// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
+#define RTE_I2C2 0
+#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP
+
+// I2C2_SCL Pin <0=>PB10
+#define RTE_I2C2_SCL_PORT_ID 0
+#if (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT GPIOB
+#define RTE_I2C2_SCL_BIT 10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+// I2C2_SDA Pin <0=>PB11
+#define RTE_I2C2_SDA_PORT_ID 0
+#if (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT GPIOB
+#define RTE_I2C2_SDA_BIT 11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <5=>5
+// Selects DMA Channel (only Channel 5 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_I2C2_RX_DMA 1
+#define RTE_I2C2_RX_DMA_NUMBER 1
+#define RTE_I2C2_RX_DMA_CHANNEL 5
+#define RTE_I2C2_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <4=>4
+// Selects DMA Channel (only Channel 4 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_I2C2_TX_DMA 1
+#define RTE_I2C2_TX_DMA_NUMBER 1
+#define RTE_I2C2_TX_DMA_CHANNEL 4
+#define RTE_I2C2_TX_DMA_PRIORITY 0
+
+//
+
+
+// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
+#define RTE_SPI1 0
+
+// SPI1_NSS Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..G, y = 0..15)
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SPI1_NSS_PIN 1
+#define RTE_SPI1_NSS_PORT GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT 4
+
+// SPI1_SCK Pin <0=>PA5
+#define RTE_SPI1_SCK_PORT_ID_DEF 0
+#if (RTE_SPI1_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI1_SCK_PORT_DEF GPIOA
+#define RTE_SPI1_SCK_BIT_DEF 5
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+// SPI1_MISO Pin <0=>Not Used <1=>PA6
+#define RTE_SPI1_MISO_PORT_ID_DEF 0
+#if (RTE_SPI1_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI1_MISO_DEF 0
+#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI1_MISO_DEF 1
+#define RTE_SPI1_MISO_PORT_DEF GPIOA
+#define RTE_SPI1_MISO_BIT_DEF 6
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+// SPI1_MOSI Pin <0=>Not Used <1=>PA7
+#define RTE_SPI1_MOSI_PORT_ID_DEF 0
+#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI1_MOSI_DEF 0
+#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI1_MOSI_DEF 1
+#define RTE_SPI1_MOSI_PORT_DEF GPIOA
+#define RTE_SPI1_MOSI_BIT_DEF 7
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+// SPI1 Pin Remap
+// Enable SPI1 Pin Remapping.
+#define RTE_SPI1_REMAP 0
+
+// SPI1_SCK Pin <0=>PB3
+#define RTE_SPI1_SCK_PORT_ID_FULL 0
+#if (RTE_SPI1_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI1_SCK_PORT_FULL GPIOB
+#define RTE_SPI1_SCK_BIT_FULL 3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+// SPI1_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID_FULL 0
+#if (RTE_SPI1_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI1_MISO_FULL 0
+#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI1_MISO_FULL 1
+#define RTE_SPI1_MISO_PORT_FULL GPIOB
+#define RTE_SPI1_MISO_BIT_FULL 4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+// SPI1_MOSI Pin <0=>Not Used <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID_FULL 0
+#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI1_MOSI_FULL 0
+#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI1_MOSI_FULL 1
+#define RTE_SPI1_MOSI_PORT_FULL GPIOB
+#define RTE_SPI1_MOSI_BIT_FULL 5
+#else
+#error "Invalid SPI1_MOSI Pin Configuration!"
+#endif
+
+//
+
+#if (RTE_SPI1_REMAP)
+#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP
+#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL
+#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL
+#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL
+#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL
+#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL
+#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL
+#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL
+#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL
+#else
+#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP
+#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF
+#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF
+#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF
+#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF
+#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF
+#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF
+#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF
+#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <2=>2
+// Selects DMA Channel (only Channel 2 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI1_RX_DMA 0
+#define RTE_SPI1_RX_DMA_NUMBER 1
+#define RTE_SPI1_RX_DMA_CHANNEL 2
+#define RTE_SPI1_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <3=>3
+// Selects DMA Channel (only Channel 3 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI1_TX_DMA 0
+#define RTE_SPI1_TX_DMA_NUMBER 1
+#define RTE_SPI1_TX_DMA_CHANNEL 3
+#define RTE_SPI1_TX_DMA_PRIORITY 0
+
+//
+
+
+// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
+#define RTE_SPI2 0
+
+// SPI2_NSS Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..G, y = 0..15)
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SPI2_NSS_PIN 1
+#define RTE_SPI2_NSS_PORT GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT 12
+
+// SPI2_SCK Pin <0=>PB13
+#define RTE_SPI2_SCK_PORT_ID 0
+#if (RTE_SPI2_SCK_PORT_ID == 0)
+#define RTE_SPI2_SCK_PORT GPIOB
+#define RTE_SPI2_SCK_BIT 13
+#define RTE_SPI2_SCK_REMAP 0
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+// SPI2_MISO Pin <0=>Not Used <1=>PB14
+#define RTE_SPI2_MISO_PORT_ID 0
+#if (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO 0
+#elif (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO 1
+#define RTE_SPI2_MISO_PORT GPIOB
+#define RTE_SPI2_MISO_BIT 14
+#define RTE_SPI2_MISO_REMAP 0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+// SPI2_MOSI Pin <0=>Not Used <1=>PB15
+#define RTE_SPI2_MOSI_PORT_ID 0
+#if (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI 0
+#elif (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI 1
+#define RTE_SPI2_MOSI_PORT GPIOB
+#define RTE_SPI2_MOSI_BIT 15
+#define RTE_SPI2_MOSI_REMAP 0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <4=>4
+// Selects DMA Channel (only Channel 4 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI2_RX_DMA 0
+#define RTE_SPI2_RX_DMA_NUMBER 1
+#define RTE_SPI2_RX_DMA_CHANNEL 4
+#define RTE_SPI2_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <5=>5
+// Selects DMA Channel (only Channel 5 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI2_TX_DMA 0
+#define RTE_SPI2_TX_DMA_NUMBER 1
+#define RTE_SPI2_TX_DMA_CHANNEL 5
+#define RTE_SPI2_TX_DMA_PRIORITY 0
+
+//
+
+
+// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
+#define RTE_SPI3 0
+
+// SPI3_NSS Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..G, y = 0..15)
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SPI3_NSS_PIN 1
+#define RTE_SPI3_NSS_PORT GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT 15
+
+// SPI3_SCK Pin <0=>PB3
+#define RTE_SPI3_SCK_PORT_ID_DEF 0
+#if (RTE_SPI3_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI3_SCK_PORT_DEF GPIOB
+#define RTE_SPI3_SCK_BIT_DEF 3
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+// SPI3_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI3_MISO_PORT_ID_DEF 0
+#if (RTE_SPI3_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI3_MISO_DEF 0
+#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI3_MISO_DEF 1
+#define RTE_SPI3_MISO_PORT_DEF GPIOB
+#define RTE_SPI3_MISO_BIT_DEF 4
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+// SPI3_MOSI <0=>Not Used Pin <1=>PB5
+#define RTE_SPI3_MOSI_PORT_ID_DEF 0
+#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI3_MOSI_DEF 0
+#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI3_MOSI_DEF 1
+#define RTE_SPI3_MOSI_PORT_DEF GPIOB
+#define RTE_SPI3_MOSI_BIT_DEF 5
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+// SPI3 Pin Remap
+// Enable SPI3 Pin Remapping.
+// SPI 3 Pin Remapping is available only in connectivity line devices!
+#define RTE_SPI3_REMAP 0
+
+// SPI3_SCK Pin <0=>PC10
+#define RTE_SPI3_SCK_PORT_ID_FULL 0
+#if (RTE_SPI3_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI3_SCK_PORT_FULL GPIOC
+#define RTE_SPI3_SCK_BIT_FULL 10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+// SPI3_MISO Pin <0=>Not Used <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID_FULL 0
+#if (RTE_SPI3_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI3_MISO_FULL 0
+#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI3_MISO_FULL 1
+#define RTE_SPI3_MISO_PORT_FULL GPIOC
+#define RTE_SPI3_MISO_BIT_FULL 11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+// SPI3_MOSI Pin <0=>Not Used <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID_FULL 0
+#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI3_MOSI_FULL 0
+#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI3_MOSI_FULL 1
+#define RTE_SPI3_MOSI_PORT_FULL GPIOC
+#define RTE_SPI3_MOSI_BIT_FULL 12
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+//
+
+#if (RTE_SPI3_REMAP)
+#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP
+#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL
+#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL
+#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL
+#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL
+#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL
+#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL
+#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL
+#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL
+#else
+#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP
+#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF
+#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF
+#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF
+#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF
+#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF
+#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF
+#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF
+#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <1=>1
+// Selects DMA Channel (only Channel 1 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI3_RX_DMA 0
+#define RTE_SPI3_RX_DMA_NUMBER 2
+#define RTE_SPI3_RX_DMA_CHANNEL 1
+#define RTE_SPI3_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <2=>2
+// Selects DMA Channel (only Channel 2 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI3_TX_DMA 0
+#define RTE_SPI3_TX_DMA_NUMBER 2
+#define RTE_SPI3_TX_DMA_CHANNEL 2
+#define RTE_SPI3_TX_DMA_PRIORITY 0
+
+//
+
+
+// SDIO (Secure Digital Input/Output) [Driver_MCI0]
+// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
+#define RTE_SDIO 0
+
+// SDIO Peripheral Bus
+// SDIO_CK Pin <0=>PC12
+#define RTE_SDIO_CK_PORT_ID 0
+#if (RTE_SDIO_CK_PORT_ID == 0)
+ #define RTE_SDIO_CK_PORT GPIOC
+ #define RTE_SDIO_CK_PIN 12
+#else
+ #error "Invalid SDIO_CLK Pin Configuration!"
+#endif
+// SDIO_CMD Pin <0=>PD2
+#define RTE_SDIO_CMD_PORT_ID 0
+#if (RTE_SDIO_CMD_PORT_ID == 0)
+ #define RTE_SDIO_CMD_PORT GPIOD
+ #define RTE_SDIO_CMD_PIN 2
+#else
+ #error "Invalid SDIO_CMD Pin Configuration!"
+#endif
+// SDIO_D0 Pin <0=>PC8
+#define RTE_SDIO_D0_PORT_ID 0
+#if (RTE_SDIO_D0_PORT_ID == 0)
+ #define RTE_SDIO_D0_PORT GPIOC
+ #define RTE_SDIO_D0_PIN 8
+#else
+ #error "Invalid SDIO_DAT0 Pin Configuration!"
+#endif
+// SDIO_D[1 .. 3]
+#define RTE_SDIO_BUS_WIDTH_4 1
+// SDIO_D1 Pin <0=>PC9
+#define RTE_SDIO_D1_PORT_ID 0
+#if (RTE_SDIO_D1_PORT_ID == 0)
+ #define RTE_SDIO_D1_PORT GPIOC
+ #define RTE_SDIO_D1_PIN 9
+#else
+ #error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+// SDIO_D2 Pin <0=>PC10
+#define RTE_SDIO_D2_PORT_ID 0
+#if (RTE_SDIO_D2_PORT_ID == 0)
+ #define RTE_SDIO_D2_PORT GPIOC
+ #define RTE_SDIO_D2_PIN 10
+#else
+ #error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+// SDIO_D3 Pin <0=>PC11
+#define RTE_SDIO_D3_PORT_ID 0
+#if (RTE_SDIO_D3_PORT_ID == 0)
+ #define RTE_SDIO_D3_PORT GPIOC
+ #define RTE_SDIO_D3_PIN 11
+#else
+ #error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+// SDIO_D[1 .. 3]
+// SDIO_D[4 .. 7]
+#define RTE_SDIO_BUS_WIDTH_8 0
+// SDIO_D4 Pin <0=>PB8
+#define RTE_SDIO_D4_PORT_ID 0
+#if (RTE_SDIO_D4_PORT_ID == 0)
+ #define RTE_SDIO_D4_PORT GPIOB
+ #define RTE_SDIO_D4_PIN 8
+#else
+ #error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+// SDIO_D5 Pin <0=>PB9
+#define RTE_SDIO_D5_PORT_ID 0
+#if (RTE_SDIO_D5_PORT_ID == 0)
+ #define RTE_SDIO_D5_PORT GPIOB
+ #define RTE_SDIO_D5_PIN 9
+#else
+ #error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+// SDIO_D6 Pin <0=>PC6
+#define RTE_SDIO_D6_PORT_ID 0
+#if (RTE_SDIO_D6_PORT_ID == 0)
+ #define RTE_SDIO_D6_PORT GPIOC
+ #define RTE_SDIO_D6_PIN 6
+#else
+ #error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+// SDIO_D7 Pin <0=>PC7
+#define RTE_SDIO_D7_PORT_ID 0
+#if (RTE_SDIO_D7_PORT_ID == 0)
+ #define RTE_SDIO_D7_PORT GPIOC
+ #define RTE_SDIO_D7_PIN 7
+#else
+ #error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+// SDIO_D[4 .. 7]
+// SDIO Peripheral Bus
+
+// Card Detect Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SDIO_CD_EN 1
+#define RTE_SDIO_CD_ACTIVE 0
+#define RTE_SDIO_CD_PORT GPIO_PORT(5)
+#define RTE_SDIO_CD_PIN 11
+
+// Write Protect Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SDIO_WP_EN 0
+#define RTE_SDIO_WP_ACTIVE 1
+#define RTE_SDIO_WP_PORT GPIO_PORT(0)
+#define RTE_SDIO_WP_PIN 10
+
+// DMA
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <4=>4
+// Selects DMA Channel (only Channel 4 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SDIO_DMA_NUMBER 2
+#define RTE_SDIO_DMA_CHANNEL 4
+#define RTE_SDIO_DMA_PRIORITY 0
+
+//
+
+
+// CAN1 (Controller Area Network 1) [Driver_CAN1]
+// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
+#define RTE_CAN1 0
+
+// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
+#define RTE_CAN1_RX_PORT_ID 0
+#if (RTE_CAN1_RX_PORT_ID == 0)
+#define RTE_CAN1_RX_PORT GPIOA
+#define RTE_CAN1_RX_BIT 11
+#elif (RTE_CAN1_RX_PORT_ID == 1)
+#define RTE_CAN1_RX_PORT GPIOB
+#define RTE_CAN1_RX_BIT 8
+#elif (RTE_CAN1_RX_PORT_ID == 2)
+#define RTE_CAN1_RX_PORT GPIOD
+#define RTE_CAN1_RX_BIT 0
+#else
+#error "Invalid CAN1_RX Pin Configuration!"
+#endif
+
+// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
+#define RTE_CAN1_TX_PORT_ID 0
+#if (RTE_CAN1_TX_PORT_ID == 0)
+#define RTE_CAN1_TX_PORT GPIOA
+#define RTE_CAN1_TX_BIT 12
+#elif (RTE_CAN1_TX_PORT_ID == 1)
+#define RTE_CAN1_TX_PORT GPIOB
+#define RTE_CAN1_TX_BIT 9
+#elif (RTE_CAN1_TX_PORT_ID == 2)
+#define RTE_CAN1_TX_PORT GPIOD
+#define RTE_CAN1_TX_BIT 1
+#else
+#error "Invalid CAN1_TX Pin Configuration!"
+#endif
+
+//
+
+
+// CAN2 (Controller Area Network 2) [Driver_CAN2]
+// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
+#define RTE_CAN2 0
+
+// CAN2_RX Pin <0=>PB5 <1=>PB12
+#define RTE_CAN2_RX_PORT_ID 0
+#if (RTE_CAN2_RX_PORT_ID == 0)
+#define RTE_CAN2_RX_PORT GPIOB
+#define RTE_CAN2_RX_BIT 5
+#elif (RTE_CAN2_RX_PORT_ID == 1)
+#define RTE_CAN2_RX_PORT GPIOB
+#define RTE_CAN2_RX_BIT 12
+#else
+#error "Invalid CAN2_RX Pin Configuration!"
+#endif
+
+// CAN2_TX Pin <0=>PB6 <1=>PB13
+#define RTE_CAN2_TX_PORT_ID 0
+#if (RTE_CAN2_TX_PORT_ID == 0)
+#define RTE_CAN2_TX_PORT GPIOB
+#define RTE_CAN2_TX_BIT 6
+#elif (RTE_CAN2_TX_PORT_ID == 1)
+#define RTE_CAN2_TX_PORT GPIOB
+#define RTE_CAN2_TX_BIT 13
+#else
+#error "Invalid CAN2_TX Pin Configuration!"
+#endif
+
+//
+
+
+// ETH (Ethernet Interface) [Driver_ETH_MAC0]
+// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
+#define RTE_ETH 0
+
+// MII (Media Independent Interface)
+// Enable Media Independent Interface pin configuration
+#define RTE_ETH_MII 0
+
+// ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID 0
+#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN 3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+// ETH_MII_TXD0 Pin <0=>PB12
+#define RTE_ETH_MII_TXD0_PORT_ID 0
+#if (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT GPIOB
+#define RTE_ETH_MII_TXD0_PIN 12
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+// ETH_MII_TXD1 Pin <0=>PB13
+#define RTE_ETH_MII_TXD1_PORT_ID 0
+#if (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT GPIOB
+#define RTE_ETH_MII_TXD1_PIN 13
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+// ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID 0
+#if (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT GPIOC
+#define RTE_ETH_MII_TXD2_PIN 2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+// ETH_MII_TXD3 Pin <0=>PB8
+#define RTE_ETH_MII_TXD3_PORT_ID 0
+#if (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT GPIOB
+#define RTE_ETH_MII_TXD3_PIN 8
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+// ETH_MII_TX_EN Pin <0=>PB11
+#define RTE_ETH_MII_TX_EN_PORT_ID 0
+#if (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT GPIOB
+#define RTE_ETH_MII_TX_EN_PIN 11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+// ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID 0
+#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN 1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+// ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_DEF 0
+
+// ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_DEF 0
+
+// ETH_MII_RXD2 Pin <0=>PB0
+#define RTE_ETH_MII_RXD2_DEF 0
+
+// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
+#define RTE_ETH_MII_RXD3_DEF 0
+
+// ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_DEF 0
+
+// ETH_MII_RX_ER Pin <0=>PB10
+#define RTE_ETH_MII_RX_ER_PORT_ID 0
+#if (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT GPIOB
+#define RTE_ETH_MII_RX_ER_PIN 10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+// ETH_MII_CRS Pin <0=>PA0
+#define RTE_ETH_MII_CRS_PORT_ID 0
+#if (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT GPIOA
+#define RTE_ETH_MII_CRS_PIN 0
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+// ETH_MII_COL Pin <0=>PA3
+#define RTE_ETH_MII_COL_PORT_ID 0
+#if (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT GPIOA
+#define RTE_ETH_MII_COL_PIN 3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+// Ethernet MAC I/O remapping
+// Remap Ethernet pins
+#define RTE_ETH_MII_REMAP 0
+
+// ETH_MII_RXD0 Pin <1=>PD9
+#define RTE_ETH_MII_RXD0_REMAP 1
+
+// ETH_MII_RXD1 Pin <1=>PD10
+#define RTE_ETH_MII_RXD1_REMAP 1
+
+// ETH_MII_RXD2 Pin <1=>PD11
+#define RTE_ETH_MII_RXD2_REMAP 1
+
+// ETH_MII_RXD3 Pin <1=>PD12
+#define RTE_ETH_MII_RXD3_REMAP 1
+
+// ETH_MII_RX_DV Pin <1=>PD8
+#define RTE_ETH_MII_RX_DV_REMAP 1
+//
+
+//
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
+#define RTE_ETH_MII_RXD0_PORT GPIOC
+#define RTE_ETH_MII_RXD0_PIN 4
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
+#define RTE_ETH_MII_RXD0_PORT GPIOD
+#define RTE_ETH_MII_RXD0_PIN 9
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
+#define RTE_ETH_MII_RXD1_PORT GPIOC
+#define RTE_ETH_MII_RXD1_PIN 5
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
+#define RTE_ETH_MII_RXD1_PORT GPIOD
+#define RTE_ETH_MII_RXD1_PIN 10
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
+#define RTE_ETH_MII_RXD2_PORT GPIOB
+#define RTE_ETH_MII_RXD2_PIN 0
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
+#define RTE_ETH_MII_RXD2_PORT GPIOD
+#define RTE_ETH_MII_RXD2_PIN 11
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
+#define RTE_ETH_MII_RXD3_PORT GPIOB
+#define RTE_ETH_MII_RXD3_PIN 1
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
+#define RTE_ETH_MII_RXD3_PORT GPIOD
+#define RTE_ETH_MII_RXD3_PIN 12
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
+#define RTE_ETH_MII_RX_DV_PORT GPIOA
+#define RTE_ETH_MII_RX_DV_PIN 7
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
+#define RTE_ETH_MII_RX_DV_PORT GPIOD
+#define RTE_ETH_MII_RX_DV_PIN 8
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+
+// RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII 0
+
+// ETH_RMII_TXD0 Pin <0=>PB12
+#define RTE_ETH_RMII_TXD0_PORT_ID 0
+#if (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT GPIOB
+#define RTE_ETH_RMII_TXD0_PIN 12
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+// ETH_RMII_TXD1 Pin <0=>PB13
+#define RTE_ETH_RMII_TXD1_PORT_ID 0
+#if (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT GPIOB
+#define RTE_ETH_RMII_TXD1_PIN 13
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+// ETH_RMII_TX_EN Pin <0=>PB11
+#define RTE_ETH_RMII_TX_EN_PORT_ID 0
+#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN 11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+// ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_DEF 0
+
+// ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_DEF 0
+
+// ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID 0
+#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN 1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+// ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_DEF 0
+
+// Ethernet MAC I/O remapping
+// Remap Ethernet pins
+#define RTE_ETH_RMII_REMAP 0
+// ETH_RMII_RXD0 Pin <1=>PD9
+#define RTE_ETH_RMII_RXD0_REMAP 1
+
+// ETH_RMII_RXD1 Pin <1=>PD10
+#define RTE_ETH_RMII_RXD1_REMAP 1
+
+// ETH_RMII_CRS_DV Pin <1=>PD8
+#define RTE_ETH_RMII_CRS_DV_REMAP 1
+//
+
+#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
+#define RTE_ETH_RMII_RXD0_PORT GPIOC
+#define RTE_ETH_RMII_RXD0_PIN 4
+#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
+#define RTE_ETH_RMII_RXD0_PORT GPIOD
+#define RTE_ETH_RMII_RXD0_PIN 9
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
+#define RTE_ETH_RMII_RXD1_PORT GPIOC
+#define RTE_ETH_RMII_RXD1_PIN 5
+#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
+#define RTE_ETH_RMII_RXD1_PORT GPIOD
+#define RTE_ETH_RMII_RXD1_PIN 10
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
+#define RTE_ETH_RMII_CRS_DV_PORT GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN 7
+#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
+#define RTE_ETH_RMII_CRS_DV_PORT GPIOD
+#define RTE_ETH_RMII_CRS_DV_PIN 8
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//
+
+// Management Data Interface
+// ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID 0
+#if (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT GPIOC
+#define RTE_ETH_MDI_MDC_PIN 1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+// ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID 0
+#if (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT GPIOA
+#define RTE_ETH_MDI_MDIO_PIN 2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//
+
+// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
+#define RTE_ETH_REF_CLOCK_ID 0
+#if (RTE_ETH_REF_CLOCK_ID == 0)
+#define RTE_ETH_REF_CLOCK 0
+#elif (RTE_ETH_REF_CLOCK_ID == 1)
+#define RTE_ETH_REF_CLOCK 1
+#else
+#error "Invalid MCO Ethernet Reference Clock Configuration!"
+#endif
+//
+
+
+// USB Device Full-speed
+// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_DEVICE 0
+
+// CON On/Off Pin
+// Configure Pin for driving D+ pull-up
+// GPIO Pxy (x = A..G, y = 0..15)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_USB_DEVICE_CON_PIN 1
+#define RTE_USB_DEVICE_CON_ACTIVE 0
+#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1)
+#define RTE_USB_DEVICE_CON_BIT 14
+
+//
+
+
+// USB OTG Full-speed
+#define RTE_USB_OTG_FS 0
+
+// Host [Driver_USBH0]
+// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST 0
+
+// VBUS Power On/Off Pin
+// Configure Pin for driving VBUS
+// GPIO Pxy (x = A..G, y = 0..15)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_OTG_FS_VBUS_PIN 1
+#define RTE_OTG_FS_VBUS_ACTIVE 0
+#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2)
+#define RTE_OTG_FS_VBUS_BIT 9
+
+// Overcurrent Detection Pin
+// Configure Pin for overcurrent detection
+// GPIO Pxy (x = A..G, y = 0..15)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_OTG_FS_OC_PIN 1
+#define RTE_OTG_FS_OC_ACTIVE 0
+#define RTE_OTG_FS_OC_PORT GPIO_PORT(4)
+#define RTE_OTG_FS_OC_BIT 1
+//
+
+//
+
+
+#endif /* __RTE_DEVICE_H */
diff --git a/Keil_Commun/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/Keil_Commun/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
new file mode 100644
index 0000000..74da96c
--- /dev/null
+++ b/Keil_Commun/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
@@ -0,0 +1,307 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_md.s
+;* Author : MCD Application Team
+;* Version : V3.5.0
+;* Date : 11-March-2011
+;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure the clock system
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1_2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/Keil_Commun/RTE/Device/STM32F103RB/system_stm32f10x.c b/Keil_Commun/RTE/Device/STM32F103RB/system_stm32f10x.c
new file mode 100644
index 0000000..71efc85
--- /dev/null
+++ b/Keil_Commun/RTE/Device/STM32F103RB/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f10x_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+ * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/** @addtogroup STM32F10x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f10x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your device's
+ maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to drive
+ the System clock.
+ If you are using different crystal you have to adapt those functions accordingly.
+ */
+
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz 24000000
+#else
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz 24000000 */
+/* #define SYSCLK_FREQ_36MHz 36000000 */
+/* #define SYSCLK_FREQ_48MHz 48000000 */
+/* #define SYSCLK_FREQ_56MHz 56000000 */
+#define SYSCLK_FREQ_72MHz 72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
+ STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+ uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+ static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+ static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+ static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+ static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+ static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+ static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+ SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+ SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+ SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+ SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+ SetSysClockTo72();
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ source (default after reset) */
+}
+
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x44444B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+ if (HSE_VALUE <= 24000000)
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+ }
+ else
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+ }
+#endif /* STM32F10X_CL */
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* Select HSE as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo24(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo36(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+#else
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo48(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo56(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL7);
+#else
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo72(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+#else
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Keil_Commun/RTE/_CarteSTM/RTE_Components.h b/Keil_Commun/RTE/_CarteSTM/RTE_Components.h
new file mode 100644
index 0000000..1b063fb
--- /dev/null
+++ b/Keil_Commun/RTE/_CarteSTM/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'projet_chavirement'
+ * Target: 'CarteSTM'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Keil_Commun/RTE/_Simulation/RTE_Components.h b/Keil_Commun/RTE/_Simulation/RTE_Components.h
new file mode 100644
index 0000000..0be29cc
--- /dev/null
+++ b/Keil_Commun/RTE/_Simulation/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'projet_chavirement'
+ * Target: 'Simulation'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Keil_Commun/RTE/_Target_1/RTE_Components.h b/Keil_Commun/RTE/_Target_1/RTE_Components.h
new file mode 100644
index 0000000..bba1c92
--- /dev/null
+++ b/Keil_Commun/RTE/_Target_1/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'projet_chavirement'
+ * Target: 'Target 1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Keil_Commun/projet_chavirement b/Keil_Commun/projet_chavirement
new file mode 100644
index 0000000..6c234be
--- /dev/null
+++ b/Keil_Commun/projet_chavirement
@@ -0,0 +1,289 @@
+/*------------------------------------------------------------------------------
+ * uVision/ARM development tools
+ * Copyright (C) 2015-2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: projet_chavirement
+ * Purpose: ROM Image generated from user specified files.
+ * Note: Generated by FCARM FILE CONVERTER V2.58, do not modify!
+ *----------------------------------------------------------------------------*/
+
+#include
+#include
+
+extern const uint32_t imageLastModified;
+extern uint32_t imageFileInfo (const char *name, const uint8_t **data);
+
+/* File information */
+typedef struct _imageFileItem {
+ uint32_t id; /* Name identifier (CRC32 value of file name) */
+ const uint8_t *data; /* Data start address in ROM */
+} imageFileItem;
+
+#define IMAGE_FILE_COUNT 1U
+
+/* Last-Modified: Fri, Nov 2021 13:00:57 GMT */
+const uint32_t imageLastModified = 1636117257U;
+
+static const uint8_t imageFileData[2671U] = {
+
+ /*-- File: ..\Drivers\MyTimer.h, 2671 bytes --*/
+ 0x23U,0x69U,0x66U,0x6EU,0x64U,0x65U,0x66U,0x20U,0x4DU,0x59U,0x54U,0x49U,0x4DU,
+ 0x45U,0x52U,0x5FU,0x48U,0x0DU,0x0AU,0x23U,0x64U,0x65U,0x66U,0x69U,0x6EU,0x65U,
+ 0x20U,0x4DU,0x59U,0x54U,0x49U,0x4DU,0x45U,0x52U,0x5FU,0x48U,0x0DU,0x0AU,0x23U,
+ 0x69U,0x6EU,0x63U,0x6CU,0x75U,0x64U,0x65U,0x20U,0x22U,0x73U,0x74U,0x6DU,0x33U,
+ 0x32U,0x66U,0x31U,0x30U,0x78U,0x2EU,0x68U,0x22U,0x0DU,0x0AU,0x0DU,0x0AU,0x74U,
+ 0x79U,0x70U,0x65U,0x64U,0x65U,0x66U,0x20U,0x73U,0x74U,0x72U,0x75U,0x63U,0x74U,
+ 0x0DU,0x0AU,0x7BU,0x0DU,0x0AU,0x54U,0x49U,0x4DU,0x5FU,0x54U,0x79U,0x70U,0x65U,
+ 0x44U,0x65U,0x66U,0x20U,0x2AU,0x20U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x20U,0x3BU,
+ 0x20U,0x2FU,0x2FU,0x20U,0x54U,0x49U,0x4DU,0x31U,0x20U,0xE0U,0x20U,0x54U,0x49U,
+ 0x4DU,0x34U,0x0DU,0x0AU,0x75U,0x6EU,0x73U,0x69U,0x67U,0x6EU,0x65U,0x64U,0x20U,
+ 0x73U,0x68U,0x6FU,0x72U,0x74U,0x20U,0x41U,0x52U,0x52U,0x20U,0x3BU,0x0DU,0x0AU,
+ 0x75U,0x6EU,0x73U,0x69U,0x67U,0x6EU,0x65U,0x64U,0x20U,0x73U,0x68U,0x6FU,0x72U,
+ 0x74U,0x20U,0x50U,0x53U,0x43U,0x20U,0x3BU,0x0DU,0x0AU,0x7DU,0x20U,0x4DU,0x79U,
+ 0x54U,0x69U,0x6DU,0x65U,0x72U,0x5FU,0x53U,0x74U,0x72U,0x75U,0x63U,0x74U,0x5FU,
+ 0x54U,0x79U,0x70U,0x65U,0x44U,0x65U,0x66U,0x20U,0x3BU,0x0DU,0x0AU,0x0DU,0x0AU,
+ 0x0DU,0x0AU,0x2FU,0x2AU,0x0DU,0x0AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x0DU,0x0AU,0x2AU,0x20U,0x40U,0x62U,0x72U,0x69U,0x65U,
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+ 0x3EU,0x20U,0x50U,0x61U,0x72U,0x61U,0x6DU,0xE8U,0x74U,0x72U,0x65U,0x20U,0x73U,
+ 0x6FU,0x75U,0x73U,0x20U,0x66U,0x6FU,0x72U,0x6DU,0x65U,0x20U,0x64U,0x92U,0x20U,
+ 0x75U,0x6EU,0x65U,0x20U,0x73U,0x74U,0x72U,0x75U,0x63U,0x74U,0x75U,0x72U,0x65U,
+ 0x20U,0x28U,0x20U,0x73U,0x6FU,0x6EU,0x20U,0x61U,0x64U,0x72U,0x65U,0x73U,0x73U,
+ 0x65U,0x20U,0x29U,0x20U,0x63U,0x6FU,0x6EU,0x74U,0x65U,0x6EU,0x61U,0x6EU,0x74U,
+ 0x20U,0x6CU,0x65U,0x73U,0x0DU,0x0AU,0x69U,0x6EU,0x66U,0x6FU,0x72U,0x6DU,0x61U,
+ 0x74U,0x69U,0x6FU,0x6EU,0x73U,0x20U,0x64U,0x65U,0x20U,0x62U,0x61U,0x73U,0x65U,
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+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
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+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x0DU,0x0AU,0x2AU,0x2FU,0x0DU,0x0AU,0x76U,
+ 0x6FU,0x69U,0x64U,0x20U,0x4DU,0x79U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x5FU,0x42U,
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+ 0x2AU,0x0DU,0x0AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x0DU,0x0AU,0x2AU,0x20U,0x40U,0x62U,0x72U,0x69U,0x65U,0x66U,0x0DU,0x0AU,
+ 0x2AU,0x20U,0x40U,0x70U,0x61U,0x72U,0x61U,0x6DU,0x20U,0x2DU,0x3EU,0x20U,0x2DU,
+ 0x20U,0x54U,0x49U,0x4DU,0x5FU,0x54U,0x79U,0x70U,0x65U,0x44U,0x65U,0x66U,0x20U,
+ 0x2AU,0x20U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x20U,0x3AU,0x20U,0x54U,0x69U,0x6DU,
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+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x0DU,0x0AU,0x2AU,0x2FU,0x0DU,0x0AU,0x76U,0x6FU,0x69U,0x64U,0x20U,0x53U,
+ 0x65U,0x74U,0x5FU,0x44U,0x75U,0x74U,0x79U,0x5FU,0x43U,0x79U,0x63U,0x6CU,0x65U,
+ 0x20U,0x28U,0x54U,0x49U,0x4DU,0x5FU,0x54U,0x79U,0x70U,0x65U,0x44U,0x65U,0x66U,
+ 0x20U,0x2AU,0x20U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x2CU,0x20U,0x63U,0x68U,0x61U,
+ 0x72U,0x20U,0x43U,0x68U,0x61U,0x6EU,0x6EU,0x65U,0x6CU,0x2CU,0x20U,0x63U,0x68U,
+ 0x61U,0x72U,0x20U,0x44U,0x75U,0x74U,0x79U,0x5FU,0x43U,0x79U,0x63U,0x6CU,0x65U,
+ 0x29U,0x20U,0x3BU,0x0DU,0x0AU,0x0DU,0x0AU,0x0DU,0x0AU,0x0DU,0x0AU,0x23U,0x64U,
+ 0x65U,0x66U,0x69U,0x6EU,0x65U,0x20U,0x4DU,0x79U,0x54U,0x69U,0x6DU,0x65U,0x72U,
+ 0x5FU,0x42U,0x61U,0x73U,0x65U,0x5FU,0x53U,0x74U,0x61U,0x72U,0x74U,0x28U,0x20U,
+ 0x54U,0x69U,0x6DU,0x65U,0x72U,0x20U,0x29U,0x20U,0x28U,0x20U,0x54U,0x69U,0x6DU,
+ 0x65U,0x72U,0x2DU,0x3EU,0x43U,0x52U,0x31U,0x20U,0x7CU,0x3DU,0x20U,0x28U,0x31U,
+ 0x20U,0x3CU,0x3CU,0x20U,0x30U,0x29U,0x20U,0x29U,0x0DU,0x0AU,0x23U,0x64U,0x65U,
+ 0x66U,0x69U,0x6EU,0x65U,0x20U,0x4DU,0x79U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x5FU,
+ 0x42U,0x61U,0x73U,0x65U,0x5FU,0x53U,0x74U,0x6FU,0x70U,0x28U,0x20U,0x54U,0x69U,
+ 0x6DU,0x65U,0x72U,0x20U,0x29U,0x20U,0x28U,0x20U,0x54U,0x69U,0x6DU,0x65U,0x72U,
+ 0x2DU,0x3EU,0x43U,0x52U,0x31U,0x20U,0x26U,0x3DU,0x20U,0x7EU,0x28U,0x31U,0x20U,
+ 0x3CU,0x3CU,0x20U,0x30U,0x29U,0x20U,0x29U,0x0DU,0x0AU,0x23U,0x65U,0x6EU,0x64U,
+ 0x69U,0x66U,0x0DU,0x0AU,0x0DU,0x0AU
+};
+
+static const imageFileItem imageFileTable[1U+1U] = {
+ { 0xFBF4E19AU, &imageFileData[0U] }, // "../Drivers/MyTimer.h"
+ { 0x00000000U, &imageFileData[2671U] }
+};
+
+/*
+ * Calculate 32-bit CRC (Polynom: 0x04C11DB7)
+ * Parameters:
+ * crc32: CRC initial value
+ * val: Input value
+ * Return value: Calculated CRC value
+ */
+static uint32_t crc32_8bit (uint32_t crc32, uint8_t val) {
+ uint32_t n;
+
+ crc32 ^= ((uint32_t)val) << 24U;
+ for (n = 8U; n; n--) {
+ if (crc32 & 0x80000000U) {
+ crc32 <<= 1U;
+ crc32 ^= 0x04C11DB7U;
+ } else {
+ crc32 <<= 1U;
+ }
+ }
+ return (crc32);
+}
+
+/*
+ * Get file information from ROM image
+ * Parameters:
+ * name: File name
+ * data: Pointer where file data pointer will be written
+ * Return value: File size
+ */
+uint32_t imageFileInfo (const char *name, const uint8_t **data) {
+ uint32_t id, n;
+
+ if ((name == NULL) || (data == NULL)) return 0U;
+
+ id = 0xFFFFFFFFU;
+ for (; *name; name++) {
+ id = crc32_8bit(id, *name);
+ }
+
+ for (n = 0U; n < IMAGE_FILE_COUNT; n++) {
+ if (imageFileTable[n].id == id) {
+ *data = imageFileTable[n].data;
+ return ((uint32_t)(imageFileTable[n+1].data - imageFileTable[n].data));
+ }
+ }
+ return 0U;
+}
diff --git a/Keil_Commun/projet_chavirement.axf b/Keil_Commun/projet_chavirement.axf
new file mode 100644
index 0000000..6730752
--- /dev/null
+++ b/Keil_Commun/projet_chavirement.axf
@@ -0,0 +1,289 @@
+/*------------------------------------------------------------------------------
+ * uVision/ARM development tools
+ * Copyright (C) 2015-2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: projet_chavirement.axf
+ * Purpose: ROM Image generated from user specified files.
+ * Note: Generated by FCARM FILE CONVERTER V2.58, do not modify!
+ *----------------------------------------------------------------------------*/
+
+#include
+#include
+
+extern const uint32_t imageLastModified;
+extern uint32_t imageFileInfo (const char *name, const uint8_t **data);
+
+/* File information */
+typedef struct _imageFileItem {
+ uint32_t id; /* Name identifier (CRC32 value of file name) */
+ const uint8_t *data; /* Data start address in ROM */
+} imageFileItem;
+
+#define IMAGE_FILE_COUNT 1U
+
+/* Last-Modified: Fri, Nov 2021 13:00:41 GMT */
+const uint32_t imageLastModified = 1636117241U;
+
+static const uint8_t imageFileData[2671U] = {
+
+ /*-- File: ..\Drivers\MyTimer.h, 2671 bytes --*/
+ 0x23U,0x69U,0x66U,0x6EU,0x64U,0x65U,0x66U,0x20U,0x4DU,0x59U,0x54U,0x49U,0x4DU,
+ 0x45U,0x52U,0x5FU,0x48U,0x0DU,0x0AU,0x23U,0x64U,0x65U,0x66U,0x69U,0x6EU,0x65U,
+ 0x20U,0x4DU,0x59U,0x54U,0x49U,0x4DU,0x45U,0x52U,0x5FU,0x48U,0x0DU,0x0AU,0x23U,
+ 0x69U,0x6EU,0x63U,0x6CU,0x75U,0x64U,0x65U,0x20U,0x22U,0x73U,0x74U,0x6DU,0x33U,
+ 0x32U,0x66U,0x31U,0x30U,0x78U,0x2EU,0x68U,0x22U,0x0DU,0x0AU,0x0DU,0x0AU,0x74U,
+ 0x79U,0x70U,0x65U,0x64U,0x65U,0x66U,0x20U,0x73U,0x74U,0x72U,0x75U,0x63U,0x74U,
+ 0x0DU,0x0AU,0x7BU,0x0DU,0x0AU,0x54U,0x49U,0x4DU,0x5FU,0x54U,0x79U,0x70U,0x65U,
+ 0x44U,0x65U,0x66U,0x20U,0x2AU,0x20U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x20U,0x3BU,
+ 0x20U,0x2FU,0x2FU,0x20U,0x54U,0x49U,0x4DU,0x31U,0x20U,0xE0U,0x20U,0x54U,0x49U,
+ 0x4DU,0x34U,0x0DU,0x0AU,0x75U,0x6EU,0x73U,0x69U,0x67U,0x6EU,0x65U,0x64U,0x20U,
+ 0x73U,0x68U,0x6FU,0x72U,0x74U,0x20U,0x41U,0x52U,0x52U,0x20U,0x3BU,0x0DU,0x0AU,
+ 0x75U,0x6EU,0x73U,0x69U,0x67U,0x6EU,0x65U,0x64U,0x20U,0x73U,0x68U,0x6FU,0x72U,
+ 0x74U,0x20U,0x50U,0x53U,0x43U,0x20U,0x3BU,0x0DU,0x0AU,0x7DU,0x20U,0x4DU,0x79U,
+ 0x54U,0x69U,0x6DU,0x65U,0x72U,0x5FU,0x53U,0x74U,0x72U,0x75U,0x63U,0x74U,0x5FU,
+ 0x54U,0x79U,0x70U,0x65U,0x44U,0x65U,0x66U,0x20U,0x3BU,0x0DU,0x0AU,0x0DU,0x0AU,
+ 0x0DU,0x0AU,0x2FU,0x2AU,0x0DU,0x0AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x0DU,0x0AU,0x2AU,0x20U,0x40U,0x62U,0x72U,0x69U,0x65U,
+ 0x66U,0x0DU,0x0AU,0x2AU,0x20U,0x40U,0x70U,0x61U,0x72U,0x61U,0x6DU,0x20U,0x2DU,
+ 0x3EU,0x20U,0x50U,0x61U,0x72U,0x61U,0x6DU,0xE8U,0x74U,0x72U,0x65U,0x20U,0x73U,
+ 0x6FU,0x75U,0x73U,0x20U,0x66U,0x6FU,0x72U,0x6DU,0x65U,0x20U,0x64U,0x92U,0x20U,
+ 0x75U,0x6EU,0x65U,0x20U,0x73U,0x74U,0x72U,0x75U,0x63U,0x74U,0x75U,0x72U,0x65U,
+ 0x20U,0x28U,0x20U,0x73U,0x6FU,0x6EU,0x20U,0x61U,0x64U,0x72U,0x65U,0x73U,0x73U,
+ 0x65U,0x20U,0x29U,0x20U,0x63U,0x6FU,0x6EU,0x74U,0x65U,0x6EU,0x61U,0x6EU,0x74U,
+ 0x20U,0x6CU,0x65U,0x73U,0x0DU,0x0AU,0x69U,0x6EU,0x66U,0x6FU,0x72U,0x6DU,0x61U,
+ 0x74U,0x69U,0x6FU,0x6EU,0x73U,0x20U,0x64U,0x65U,0x20U,0x62U,0x61U,0x73U,0x65U,
+ 0x0DU,0x0AU,0x2AU,0x20U,0x40U,0x4EU,0x6FU,0x74U,0x65U,0x20U,0x2DU,0x3EU,0x20U,
+ 0x46U,0x6FU,0x6EU,0x63U,0x74U,0x69U,0x6FU,0x6EU,0x20U,0xE0U,0x20U,0x6CU,0x61U,
+ 0x6EU,0x63U,0x65U,0x72U,0x20U,0x73U,0x79U,0x73U,0x74U,0xE9U,0x6DU,0x61U,0x74U,
+ 0x69U,0x71U,0x75U,0x65U,0x6DU,0x65U,0x6EU,0x74U,0x20U,0x61U,0x76U,0x61U,0x6EU,
+ 0x74U,0x20U,0x64U,0x92U,0x20U,0x61U,0x6CU,0x6CU,0x65U,0x72U,0x20U,0x70U,0x6CU,
+ 0x75U,0x73U,0x20U,0x65U,0x6EU,0x20U,0x64U,0xE9U,0x74U,0x61U,0x69U,0x6CU,0x20U,
+ 0x64U,0x61U,0x6EU,0x73U,0x20U,0x6CU,0x65U,0x73U,0x0DU,0x0AU,0x63U,0x6FU,0x6EU,
+ 0x66U,0x20U,0x70U,0x6CU,0x75U,0x73U,0x20U,0x66U,0x69U,0x6EU,0x65U,0x73U,0x20U,
+ 0x28U,0x50U,0x57U,0x4DU,0x2CU,0x20U,0x63U,0x6FU,0x64U,0x65U,0x75U,0x72U,0x20U,
+ 0x69U,0x6EU,0x63U,0x20U,0x2EU,0x20U,0x2EU,0x20U,0x2EU,0x20U,0x29U,0x0DU,0x0AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x0DU,0x0AU,0x2AU,0x2FU,0x0DU,0x0AU,0x76U,
+ 0x6FU,0x69U,0x64U,0x20U,0x4DU,0x79U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x5FU,0x42U,
+ 0x61U,0x73U,0x65U,0x5FU,0x49U,0x6EU,0x69U,0x74U,0x20U,0x28U,0x20U,0x4DU,0x79U,
+ 0x54U,0x69U,0x6DU,0x65U,0x72U,0x5FU,0x53U,0x74U,0x72U,0x75U,0x63U,0x74U,0x5FU,
+ 0x54U,0x79U,0x70U,0x65U,0x44U,0x65U,0x66U,0x20U,0x2AU,0x20U,0x54U,0x69U,0x6DU,
+ 0x65U,0x72U,0x20U,0x29U,0x20U,0x3BU,0x0DU,0x0AU,0x0DU,0x0AU,0x0DU,0x0AU,0x2FU,
+ 0x2AU,0x0DU,0x0AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x0DU,0x0AU,0x2AU,0x20U,0x40U,0x62U,0x72U,0x69U,0x65U,0x66U,0x0DU,0x0AU,
+ 0x2AU,0x20U,0x40U,0x70U,0x61U,0x72U,0x61U,0x6DU,0x20U,0x2DU,0x3EU,0x20U,0x2DU,
+ 0x20U,0x54U,0x49U,0x4DU,0x5FU,0x54U,0x79U,0x70U,0x65U,0x44U,0x65U,0x66U,0x20U,
+ 0x2AU,0x20U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x20U,0x3AU,0x20U,0x54U,0x69U,0x6DU,
+ 0x65U,0x72U,0x20U,0x63U,0x6FU,0x6EU,0x63U,0x65U,0x72U,0x6EU,0x65U,0x0DU,0x0AU,
+ 0x2AU,0x20U,0x40U,0x4EU,0x6FU,0x74U,0x65U,0x20U,0x2DU,0x3EU,0x20U,0x0DU,0x0AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x0DU,0x0AU,0x2AU,0x2FU,0x0DU,0x0AU,0x76U,
+ 0x6FU,0x69U,0x64U,0x20U,0x4DU,0x79U,0x54U,0x69U,0x6DU,0x65U,0x72U,0x5FU,0x45U,
+ 0x6EU,0x63U,0x6FU,0x64U,0x65U,0x72U,0x4DU,0x6FU,0x64U,0x65U,0x5FU,0x43U,0x6FU,
+ 0x6EU,0x66U,0x20U,0x28U,0x20U,0x54U,0x49U,0x4DU,0x5FU,0x54U,0x79U,0x70U,0x65U,
+ 0x44U,0x65U,0x66U,0x20U,0x2AU,0x54U,0x49U,0x4DU,0x20U,0x29U,0x20U,0x3BU,0x0DU,
+ 0x0AU,0x0DU,0x0AU,0x0DU,0x0AU,0x2FU,0x2AU,0x0DU,0x0AU,0x2AU,0x2AU,0x2AU,0x2AU,
+ 0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,0x2AU,
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+ 0x42U,0x61U,0x73U,0x65U,0x5FU,0x53U,0x74U,0x6FU,0x70U,0x28U,0x20U,0x54U,0x69U,
+ 0x6DU,0x65U,0x72U,0x20U,0x29U,0x20U,0x28U,0x20U,0x54U,0x69U,0x6DU,0x65U,0x72U,
+ 0x2DU,0x3EU,0x43U,0x52U,0x31U,0x20U,0x26U,0x3DU,0x20U,0x7EU,0x28U,0x31U,0x20U,
+ 0x3CU,0x3CU,0x20U,0x30U,0x29U,0x20U,0x29U,0x0DU,0x0AU,0x23U,0x65U,0x6EU,0x64U,
+ 0x69U,0x66U,0x0DU,0x0AU,0x0DU,0x0AU
+};
+
+static const imageFileItem imageFileTable[1U+1U] = {
+ { 0xFBF4E19AU, &imageFileData[0U] }, // "../Drivers/MyTimer.h"
+ { 0x00000000U, &imageFileData[2671U] }
+};
+
+/*
+ * Calculate 32-bit CRC (Polynom: 0x04C11DB7)
+ * Parameters:
+ * crc32: CRC initial value
+ * val: Input value
+ * Return value: Calculated CRC value
+ */
+static uint32_t crc32_8bit (uint32_t crc32, uint8_t val) {
+ uint32_t n;
+
+ crc32 ^= ((uint32_t)val) << 24U;
+ for (n = 8U; n; n--) {
+ if (crc32 & 0x80000000U) {
+ crc32 <<= 1U;
+ crc32 ^= 0x04C11DB7U;
+ } else {
+ crc32 <<= 1U;
+ }
+ }
+ return (crc32);
+}
+
+/*
+ * Get file information from ROM image
+ * Parameters:
+ * name: File name
+ * data: Pointer where file data pointer will be written
+ * Return value: File size
+ */
+uint32_t imageFileInfo (const char *name, const uint8_t **data) {
+ uint32_t id, n;
+
+ if ((name == NULL) || (data == NULL)) return 0U;
+
+ id = 0xFFFFFFFFU;
+ for (; *name; name++) {
+ id = crc32_8bit(id, *name);
+ }
+
+ for (n = 0U; n < IMAGE_FILE_COUNT; n++) {
+ if (imageFileTable[n].id == id) {
+ *data = imageFileTable[n].data;
+ return ((uint32_t)(imageFileTable[n+1].data - imageFileTable[n].data));
+ }
+ }
+ return 0U;
+}
diff --git a/Keil_Commun/projet_chavirement.uvguix.chauz b/Keil_Commun/projet_chavirement.uvguix.chauz
new file mode 100644
index 0000000..47528fc
--- /dev/null
+++ b/Keil_Commun/projet_chavirement.uvguix.chauz
@@ -0,0 +1,3727 @@
+
+
+
+ -6.1
+
+ ### uVision Project, (C) Keil Software
+
+
+ C:\Users\chauz\Documents_non_drive\INSA\4A\S7\projet_voilier\projet_voilier\Sources
+
+
+
+
+
+
+ 38003
+ Registers
+ 82 100
+
+
+ 346
+ Code Coverage
+ 770 560
+
+
+ 204
+ Performance Analyzer
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+
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+
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diff --git a/Keil_Commun/projet_chavirement.uvoptx b/Keil_Commun/projet_chavirement.uvoptx
new file mode 100644
index 0000000..b1bbff8
--- /dev/null
+++ b/Keil_Commun/projet_chavirement.uvoptx
@@ -0,0 +1,578 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
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diff --git a/Keil_Commun/projet_chavirement.uvprojx b/Keil_Commun/projet_chavirement.uvprojx
new file mode 100644
index 0000000..4dfdc8d
--- /dev/null
+++ b/Keil_Commun/projet_chavirement.uvprojx
@@ -0,0 +1,973 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Simulation
+ 0x4
+ ARM-ADS
+ 5060960::V5.06 update 7 (build 960)::.\ARMCC
+ 0
+
+
+ STM32F103RB
+ STMicroelectronics
+ Keil.STM32F1xx_DFP.2.3.0
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))
+ 0
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+ SARMCM3.DLL
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+
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+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+
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+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x5000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+ ..\Includes;..\Sources;..\Drivers
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Drivers
+
+
+ Driver_GPIO.c
+ 1
+ ..\Drivers\Driver_GPIO.c
+
+
+ Driver_GPIO.h
+ 5
+ ..\Drivers\Driver_GPIO.h
+
+
+ Driver_SPI.c
+ 1
+ ..\Drivers\Driver_SPI.c
+
+
+ Driver_SPI.h
+ 5
+ ..\Drivers\Driver_SPI.h
+
+
+ MyTimer.c
+ 1
+ ..\Drivers\MyTimer.c
+
+
+ MyTimer.h
+ 5
+ ..\Drivers\MyTimer.h
+
+
+
+
+ LocalSource
+
+
+ principal.c
+ 1
+ .\Local_Sources\principal.c
+
+
+
+
+ Source
+
+
+ chavirement.c
+ 1
+ ..\Sources\chavirement.c
+
+
+ chavirement.h
+ 5
+ ..\Sources\chavirement.h
+
+
+ bordage.c
+ 1
+ ..\Sources\bordage.c
+
+
+ bordage.h
+ 5
+ ..\Sources\bordage.h
+
+
+
+
+ ::CMSIS
+
+
+ ::Device
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ RTE\Device\STM32F103RB\RTE_Device.h
+
+
+
+
+
+
+
+
+ RTE\Device\STM32F103RB\startup_stm32f10x_md.s
+
+
+
+
+
+
+
+
+ RTE\Device\STM32F103RB\system_stm32f10x.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+ projet_chavirement
+ 1
+
+
+
+
+
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Listings/drivers_simule.map b/Keil_Elise_Yuwei/Local_Sources/bordage/Listings/drivers_simule.map
index 1e1c9d6..ec9882c 100644
--- a/Keil_Elise_Yuwei/Local_Sources/bordage/Listings/drivers_simule.map
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Listings/drivers_simule.map
@@ -4,9 +4,7 @@ Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]
Section Cross References
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init
principal.o(i.main) refers to bordage.o(i.Roulis_Handler) for Roulis_Handler
- principal.o(i.main) refers to principal.o(.data) for GPIO_Struct
driver_gpio.o(i.MyGPIO_Toggle) refers to driver_gpio.o(i.MyGPIO_Read) for MyGPIO_Read
driver_gpio.o(i.MyGPIO_Toggle) refers to driver_gpio.o(i.MyGPIO_Reset) for MyGPIO_Reset
driver_gpio.o(i.MyGPIO_Toggle) refers to driver_gpio.o(i.MyGPIO_Set) for MyGPIO_Set
@@ -22,6 +20,7 @@ Section Cross References
bordage.o(i.bordage) refers to f2d.o(.text) for __aeabi_f2d
bordage.o(i.bordage) refers to ddiv.o(.text) for __aeabi_ddiv
bordage.o(i.bordage) refers to mytimer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init
+ bordage.o(i.bordage) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init
bordage.o(i.bordage) refers to mytimer.o(i.MyTimer_PWM) for MyTimer_PWM
bordage.o(i.bordage) refers to ffixui.o(.text) for __aeabi_f2uiz
bordage.o(i.bordage) refers to mytimer.o(i.Set_Duty_Cycle) for Set_Duty_Cycle
@@ -112,24 +111,24 @@ Image Symbol Table
Symbol Name Value Ov Type Size Object(Section)
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
+ ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE
- ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE
../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE
+ ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE
../clib/microlib/stubs.s 0x00000000 Number 0 iusefp.o ABSOLUTE
../fplib/microlib/d2f.c 0x00000000 Number 0 d2f.o ABSOLUTE
../fplib/microlib/f2d.c 0x00000000 Number 0 f2d.o ABSOLUTE
@@ -176,8 +175,8 @@ Image Symbol Table
.text 0x080003c4 Section 0 d2f.o(.text)
.text 0x080003fc Section 0 llshl.o(.text)
.text 0x0800041a Section 0 llsshr.o(.text)
- .text 0x0800043e Section 0 iusefp.o(.text)
.text 0x0800043e Section 0 fepilogue.o(.text)
+ .text 0x0800043e Section 0 iusefp.o(.text)
.text 0x080004ac Section 0 depilogue.o(.text)
.text 0x08000568 Section 36 init.o(.text)
.text 0x0800058c Section 0 llushr.o(.text)
@@ -199,10 +198,9 @@ Image Symbol Table
i.__scatterload_null 0x080009aa Section 2 handlers.o(i.__scatterload_null)
i.__scatterload_zeroinit 0x080009ac Section 14 handlers.o(i.__scatterload_zeroinit)
i.bordage 0x080009bc Section 0 bordage.o(i.bordage)
- i.main 0x08000a44 Section 0 principal.o(i.main)
- .data 0x20000000 Section 8 principal.o(.data)
- .data 0x20000008 Section 4 mytimer.o(.data)
- STACK 0x20000010 Section 1024 startup_stm32f10x_md.o(STACK)
+ i.main 0x08000a64 Section 0 principal.o(i.main)
+ .data 0x20000000 Section 4 mytimer.o(.data)
+ STACK 0x20000008 Section 1024 startup_stm32f10x_md.o(STACK)
Global Symbols
@@ -312,13 +310,12 @@ Image Symbol Table
__scatterload_copy 0x0800099d Thumb Code 14 handlers.o(i.__scatterload_copy)
__scatterload_null 0x080009ab Thumb Code 2 handlers.o(i.__scatterload_null)
__scatterload_zeroinit 0x080009ad Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
- bordage 0x080009bd Thumb Code 120 bordage.o(i.bordage)
- main 0x08000a45 Thumb Code 28 principal.o(i.main)
- Region$$Table$$Base 0x08000a68 Number 0 anon$$obj.o(Region$$Table)
- Region$$Table$$Limit 0x08000a88 Number 0 anon$$obj.o(Region$$Table)
- GPIO_Struct 0x20000000 Data 8 principal.o(.data)
- PtrF 0x20000008 Data 4 mytimer.o(.data)
- __initial_sp 0x20000410 Data 0 startup_stm32f10x_md.o(STACK)
+ bordage 0x080009bd Thumb Code 146 bordage.o(i.bordage)
+ main 0x08000a65 Thumb Code 8 principal.o(i.main)
+ Region$$Table$$Base 0x08000a6c Number 0 anon$$obj.o(Region$$Table)
+ Region$$Table$$Limit 0x08000a8c Number 0 anon$$obj.o(Region$$Table)
+ PtrF 0x20000000 Data 4 mytimer.o(.data)
+ __initial_sp 0x20000408 Data 0 startup_stm32f10x_md.o(STACK)
@@ -328,74 +325,73 @@ Memory Map of the image
Image Entry point : 0x08000105
- Load Region LR_1 (Base: 0x08000000, Size: 0x00000a94, Max: 0xffffffff, ABSOLUTE)
+ Load Region LR_1 (Base: 0x08000000, Size: 0x00000a90, Max: 0xffffffff, ABSOLUTE)
- Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000a88, Max: 0xffffffff, ABSOLUTE)
+ Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000a8c, Max: 0xffffffff, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
- 0x08000000 0x08000000 0x000000ec Data RO 276 RESET startup_stm32f10x_md.o
- 0x080000ec 0x080000ec 0x00000000 Code RO 327 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
- 0x080000ec 0x080000ec 0x00000004 Code RO 342 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
- 0x080000f0 0x080000f0 0x00000004 Code RO 345 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
- 0x080000f4 0x080000f4 0x00000000 Code RO 347 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
- 0x080000f4 0x080000f4 0x00000000 Code RO 349 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
- 0x080000f4 0x080000f4 0x00000008 Code RO 350 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
- 0x080000fc 0x080000fc 0x00000004 Code RO 357 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o)
- 0x08000100 0x08000100 0x00000000 Code RO 352 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o)
- 0x08000100 0x08000100 0x00000000 Code RO 354 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o)
- 0x08000100 0x08000100 0x00000004 Code RO 343 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
- 0x08000104 0x08000104 0x00000024 Code RO 277 * .text startup_stm32f10x_md.o
- 0x08000128 0x08000128 0x0000014e Code RO 330 .text mf_w.l(dadd.o)
- 0x08000276 0x08000276 0x000000de Code RO 332 .text mf_w.l(ddiv.o)
- 0x08000354 0x08000354 0x00000022 Code RO 334 .text mf_w.l(dflti.o)
- 0x08000376 0x08000376 0x00000028 Code RO 336 .text mf_w.l(ffixui.o)
- 0x0800039e 0x0800039e 0x00000026 Code RO 338 .text mf_w.l(f2d.o)
- 0x080003c4 0x080003c4 0x00000038 Code RO 340 .text mf_w.l(d2f.o)
- 0x080003fc 0x080003fc 0x0000001e Code RO 358 .text mc_w.l(llshl.o)
- 0x0800041a 0x0800041a 0x00000024 Code RO 360 .text mc_w.l(llsshr.o)
- 0x0800043e 0x0800043e 0x00000000 Code RO 362 .text mc_w.l(iusefp.o)
- 0x0800043e 0x0800043e 0x0000006e Code RO 363 .text mf_w.l(fepilogue.o)
- 0x080004ac 0x080004ac 0x000000ba Code RO 365 .text mf_w.l(depilogue.o)
+ 0x08000000 0x08000000 0x000000ec Data RO 263 RESET startup_stm32f10x_md.o
+ 0x080000ec 0x080000ec 0x00000000 Code RO 314 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
+ 0x080000ec 0x080000ec 0x00000004 Code RO 329 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
+ 0x080000f0 0x080000f0 0x00000004 Code RO 332 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
+ 0x080000f4 0x080000f4 0x00000000 Code RO 334 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
+ 0x080000f4 0x080000f4 0x00000000 Code RO 336 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
+ 0x080000f4 0x080000f4 0x00000008 Code RO 337 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
+ 0x080000fc 0x080000fc 0x00000004 Code RO 344 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o)
+ 0x08000100 0x08000100 0x00000000 Code RO 339 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o)
+ 0x08000100 0x08000100 0x00000000 Code RO 341 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o)
+ 0x08000100 0x08000100 0x00000004 Code RO 330 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
+ 0x08000104 0x08000104 0x00000024 Code RO 264 * .text startup_stm32f10x_md.o
+ 0x08000128 0x08000128 0x0000014e Code RO 317 .text mf_w.l(dadd.o)
+ 0x08000276 0x08000276 0x000000de Code RO 319 .text mf_w.l(ddiv.o)
+ 0x08000354 0x08000354 0x00000022 Code RO 321 .text mf_w.l(dflti.o)
+ 0x08000376 0x08000376 0x00000028 Code RO 323 .text mf_w.l(ffixui.o)
+ 0x0800039e 0x0800039e 0x00000026 Code RO 325 .text mf_w.l(f2d.o)
+ 0x080003c4 0x080003c4 0x00000038 Code RO 327 .text mf_w.l(d2f.o)
+ 0x080003fc 0x080003fc 0x0000001e Code RO 345 .text mc_w.l(llshl.o)
+ 0x0800041a 0x0800041a 0x00000024 Code RO 347 .text mc_w.l(llsshr.o)
+ 0x0800043e 0x0800043e 0x00000000 Code RO 349 .text mc_w.l(iusefp.o)
+ 0x0800043e 0x0800043e 0x0000006e Code RO 350 .text mf_w.l(fepilogue.o)
+ 0x080004ac 0x080004ac 0x000000ba Code RO 352 .text mf_w.l(depilogue.o)
0x08000566 0x08000566 0x00000002 PAD
- 0x08000568 0x08000568 0x00000024 Code RO 367 .text mc_w.l(init.o)
- 0x0800058c 0x0800058c 0x00000020 Code RO 369 .text mc_w.l(llushr.o)
- 0x080005ac 0x080005ac 0x000000cc Code RO 72 i.MyGPIO_Init driver_gpio.o
- 0x08000678 0x08000678 0x0000007c Code RO 134 i.MyTimer_Base_Init mytimer.o
- 0x080006f4 0x080006f4 0x00000078 Code RO 136 i.MyTimer_PWM mytimer.o
- 0x0800076c 0x0800076c 0x0000000a Code RO 244 i.Roulis_Handler bordage.o
- 0x08000776 0x08000776 0x00000008 Code RO 284 i.SetSysClock system_stm32f10x.o
+ 0x08000568 0x08000568 0x00000024 Code RO 354 .text mc_w.l(init.o)
+ 0x0800058c 0x0800058c 0x00000020 Code RO 356 .text mc_w.l(llushr.o)
+ 0x080005ac 0x080005ac 0x000000cc Code RO 69 i.MyGPIO_Init driver_gpio.o
+ 0x08000678 0x08000678 0x0000007c Code RO 121 i.MyTimer_Base_Init mytimer.o
+ 0x080006f4 0x080006f4 0x00000078 Code RO 123 i.MyTimer_PWM mytimer.o
+ 0x0800076c 0x0800076c 0x0000000a Code RO 231 i.Roulis_Handler bordage.o
+ 0x08000776 0x08000776 0x00000008 Code RO 271 i.SetSysClock system_stm32f10x.o
0x0800077e 0x0800077e 0x00000002 PAD
- 0x08000780 0x08000780 0x000000e0 Code RO 285 i.SetSysClockTo72 system_stm32f10x.o
- 0x08000860 0x08000860 0x0000004c Code RO 137 i.Set_Duty_Cycle mytimer.o
- 0x080008ac 0x080008ac 0x00000060 Code RO 287 i.SystemInit system_stm32f10x.o
- 0x0800090c 0x0800090c 0x00000024 Code RO 138 i.TIM1_UP_IRQHandler mytimer.o
- 0x08000930 0x08000930 0x00000024 Code RO 139 i.TIM2_IRQHandler mytimer.o
- 0x08000954 0x08000954 0x00000024 Code RO 140 i.TIM3_IRQHandler mytimer.o
- 0x08000978 0x08000978 0x00000024 Code RO 141 i.TIM4_IRQHandler mytimer.o
- 0x0800099c 0x0800099c 0x0000000e Code RO 373 i.__scatterload_copy mc_w.l(handlers.o)
- 0x080009aa 0x080009aa 0x00000002 Code RO 374 i.__scatterload_null mc_w.l(handlers.o)
- 0x080009ac 0x080009ac 0x0000000e Code RO 375 i.__scatterload_zeroinit mc_w.l(handlers.o)
+ 0x08000780 0x08000780 0x000000e0 Code RO 272 i.SetSysClockTo72 system_stm32f10x.o
+ 0x08000860 0x08000860 0x0000004c Code RO 124 i.Set_Duty_Cycle mytimer.o
+ 0x080008ac 0x080008ac 0x00000060 Code RO 274 i.SystemInit system_stm32f10x.o
+ 0x0800090c 0x0800090c 0x00000024 Code RO 125 i.TIM1_UP_IRQHandler mytimer.o
+ 0x08000930 0x08000930 0x00000024 Code RO 126 i.TIM2_IRQHandler mytimer.o
+ 0x08000954 0x08000954 0x00000024 Code RO 127 i.TIM3_IRQHandler mytimer.o
+ 0x08000978 0x08000978 0x00000024 Code RO 128 i.TIM4_IRQHandler mytimer.o
+ 0x0800099c 0x0800099c 0x0000000e Code RO 360 i.__scatterload_copy mc_w.l(handlers.o)
+ 0x080009aa 0x080009aa 0x00000002 Code RO 361 i.__scatterload_null mc_w.l(handlers.o)
+ 0x080009ac 0x080009ac 0x0000000e Code RO 362 i.__scatterload_zeroinit mc_w.l(handlers.o)
0x080009ba 0x080009ba 0x00000002 PAD
- 0x080009bc 0x080009bc 0x00000088 Code RO 245 i.bordage bordage.o
- 0x08000a44 0x08000a44 0x00000024 Code RO 4 i.main principal.o
- 0x08000a68 0x08000a68 0x00000020 Data RO 371 Region$$Table anon$$obj.o
+ 0x080009bc 0x080009bc 0x000000a8 Code RO 232 i.bordage bordage.o
+ 0x08000a64 0x08000a64 0x00000008 Code RO 4 i.main principal.o
+ 0x08000a6c 0x08000a6c 0x00000020 Data RO 358 Region$$Table anon$$obj.o
- Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000a88, Size: 0x0000000c, Max: 0xffffffff, ABSOLUTE)
+ Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000a8c, Size: 0x00000004, Max: 0xffffffff, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
- 0x20000000 0x08000a88 0x00000008 Data RW 5 .data principal.o
- 0x20000008 0x08000a90 0x00000004 Data RW 142 .data mytimer.o
+ 0x20000000 0x08000a8c 0x00000004 Data RW 129 .data mytimer.o
- Execution Region ER_ZI (Exec base: 0x2000000c, Load base: 0x08000a94, Size: 0x00000404, Max: 0xffffffff, ABSOLUTE)
+ Execution Region ER_ZI (Exec base: 0x20000004, Load base: 0x08000a90, Size: 0x00000404, Max: 0xffffffff, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
- 0x2000000c 0x08000a94 0x00000004 PAD
- 0x20000010 - 0x00000400 Zero RW 274 STACK startup_stm32f10x_md.o
+ 0x20000004 0x08000a90 0x00000004 PAD
+ 0x20000008 - 0x00000400 Zero RW 261 STACK startup_stm32f10x_md.o
==============================================================================
@@ -405,15 +401,15 @@ Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
- 146 16 0 0 0 1091 bordage.o
- 204 20 0 0 0 203386 driver_gpio.o
- 464 46 0 4 0 4761 mytimer.o
- 36 8 0 8 0 207677 principal.o
- 36 8 236 0 1024 844 startup_stm32f10x_md.o
- 328 28 0 0 0 2109 system_stm32f10x.o
+ 178 22 0 0 0 1223 bordage.o
+ 204 20 0 0 0 1682 driver_gpio.o
+ 464 46 0 4 0 5101 mytimer.o
+ 8 0 0 0 0 206875 principal.o
+ 36 8 236 0 1024 876 startup_stm32f10x_md.o
+ 328 28 0 0 0 2253 system_stm32f10x.o
----------------------------------------------------------------------
- 1216 126 268 12 1028 419868 Object Totals
+ 1220 124 268 4 1028 218010 Object Totals
0 0 32 0 0 0 (incl. Generated)
2 0 0 0 4 0 (incl. Padding)
@@ -466,15 +462,15 @@ Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug
- 2428 142 268 12 1028 420040 Grand Totals
- 2428 142 268 12 1028 420040 ELF Image Totals
- 2428 142 268 12 0 0 ROM Totals
+ 2432 140 268 4 1028 218182 Grand Totals
+ 2432 140 268 4 1028 218182 ELF Image Totals
+ 2432 140 268 4 0 0 ROM Totals
==============================================================================
- Total RO Size (Code + RO Data) 2696 ( 2.63kB)
- Total RW Size (RW Data + ZI Data) 1040 ( 1.02kB)
- Total ROM Size (Code + RO Data + RW Data) 2708 ( 2.64kB)
+ Total RO Size (Code + RO Data) 2700 ( 2.64kB)
+ Total RW Size (RW Data + ZI Data) 1032 ( 1.01kB)
+ Total ROM Size (Code + RO Data + RW Data) 2704 ( 2.64kB)
==============================================================================
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Listings/startup_stm32f10x_md.lst b/Keil_Elise_Yuwei/Local_Sources/bordage/Listings/startup_stm32f10x_md.lst
index 8f160af..f365adf 100644
--- a/Keil_Elise_Yuwei/Local_Sources/bordage/Listings/startup_stm32f10x_md.lst
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Listings/startup_stm32f10x_md.lst
@@ -465,12 +465,13 @@ ARM Macro Assembler Page 8
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md.
-o -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\
-CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_D
-FP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB SET
-A 1" --predefine="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" --pred
-efine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --list=.\listings\startu
-p_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32f10x_md.s
+o -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Users\chauz\AppData\Local\Arm
+\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Users\chauz\AppData\Local\Arm\Pa
+cks\Keil\STM32F1xx_DFP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --prede
+fine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 533" --predefine="
+_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --li
+st=.\listings\startup_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32f10x
+_md.s
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.crf b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.crf
index 687aacf..468027e 100644
Binary files a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.crf and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.crf differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.d b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.d
index c7fb8d4..c7857bc 100644
--- a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.d
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.d
@@ -1,13 +1,13 @@
.\objects\bordage.o: Include\bordage.c
.\objects\bordage.o: Include\Driver_GPIO.h
-.\objects\bordage.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\bordage.o: .\RTE\_R_el\RTE_Components.h
-.\objects\bordage.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\bordage.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
+.\objects\bordage.o: .\RTE\_Simul_\RTE_Components.h
+.\objects\bordage.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
.\objects\bordage.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\bordage.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\bordage.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\bordage.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\bordage.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
+.\objects\bordage.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\bordage.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\bordage.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\bordage.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
.\objects\bordage.o: Include\MyTimer.h
.\objects\bordage.o: Include\MyADC.h
.\objects\bordage.o: Include\bordage.h
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.o b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.o
index 87ffb5f..1f241c3 100644
Binary files a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.o and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/bordage.o differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.crf b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.crf
index 1b109a2..cea34e8 100644
Binary files a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.crf and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.crf differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.d b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.d
index 05d8136..33264f2 100644
--- a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.d
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.d
@@ -1,10 +1,10 @@
.\objects\driver_gpio.o: Include\Driver_GPIO.c
.\objects\driver_gpio.o: Include\Driver_GPIO.h
-.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\driver_gpio.o: .\RTE\_R_el\RTE_Components.h
-.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
+.\objects\driver_gpio.o: .\RTE\_Simul_\RTE_Components.h
+.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
.\objects\driver_gpio.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
+.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.o b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.o
index 09a99b4..b899309 100644
Binary files a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.o and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/driver_gpio.o differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_Simulé.dep b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_Simulé.dep
index 06e7a3a..164dbc1 100644
--- a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_Simulé.dep
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_Simulé.dep
@@ -1,73 +1,73 @@
Dependencies for Project 'drivers', Target 'Simulé': (DO NOT MODIFY !)
CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
-F (.\Source\principal.c)(0x61851991)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
-I (.\Include\Driver_GPIO.h)(0x61487FC8)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x614494D8)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582)
+F (.\Source\principal.c)(0x618523FE)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
+I (.\Include\Driver_GPIO.h)(0x618523FE)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simul_\RTE_Components.h)(0x61852771)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\Include\MyTimer.h)(0x61701852)
-I (.\Include\MyADC.h)(0x615B16F8)
-I (.\Include\bordage.h)(0x618418F1)
-F (.\Include\Driver_GPIO.c)(0x61488964)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d)
-I (Include\Driver_GPIO.h)(0x61487FC8)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x614494D8)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (.\Include\MyTimer.h)(0x618523FE)
+I (.\Include\MyADC.h)(0x618523FE)
+I (.\Include\bordage.h)(0x618523FE)
+F (.\Include\Driver_GPIO.c)(0x618523FE)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d)
+I (Include\Driver_GPIO.h)(0x618523FE)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simul_\RTE_Components.h)(0x61852771)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-F (.\Include\Driver_GPIO.h)(0x61487FC8)()
-F (.\Include\MyTimer.c)(0x6170185B)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d)
-I (Include\MyTimer.h)(0x61701852)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x614494D8)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+F (.\Include\Driver_GPIO.h)(0x618523FE)()
+F (.\Include\MyTimer.c)(0x618523FE)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d)
+I (Include\MyTimer.h)(0x618523FE)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simul_\RTE_Components.h)(0x61852771)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-F (.\Include\MyTimer.h)(0x61701852)()
-F (.\Include\MyADC.c)(0x615B1F5C)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\myadc.o --omf_browse .\objects\myadc.crf --depend .\objects\myadc.d)
-I (Include\MyADC.h)(0x615B16F8)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x614494D8)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+F (.\Include\MyTimer.h)(0x618523FE)()
+F (.\Include\MyADC.c)(0x618523FE)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\myadc.o --omf_browse .\objects\myadc.crf --depend .\objects\myadc.d)
+I (Include\MyADC.h)(0x618523FE)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simul_\RTE_Components.h)(0x61852771)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-F (.\Include\MyADC.h)(0x615B16F8)()
-F (.\Include\bordage.h)(0x618418F1)()
-F (.\Include\bordage.c)(0x61851714)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\bordage.o --omf_browse .\objects\bordage.crf --depend .\objects\bordage.d)
-I (Include\Driver_GPIO.h)(0x61487FC8)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x614494D8)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+F (.\Include\MyADC.h)(0x618523FE)()
+F (.\Include\bordage.h)(0x618523FE)()
+F (.\Include\bordage.c)(0x618523FE)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\bordage.o --omf_browse .\objects\bordage.crf --depend .\objects\bordage.d)
+I (Include\Driver_GPIO.h)(0x618523FE)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simul_\RTE_Components.h)(0x61852771)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (Include\MyTimer.h)(0x61701852)
-I (Include\MyADC.h)(0x615B16F8)
-I (Include\bordage.h)(0x618418F1)
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59283406)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58258CCC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58258CCC)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x614494D8)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
+I (Include\MyTimer.h)(0x618523FE)
+I (Include\MyADC.h)(0x618523FE)
+I (Include\bordage.h)(0x618523FE)
+F (RTE\Device\STM32F103RB\RTE_Device.h)(0x618523FE)()
+F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x618523FE)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 533" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
+F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x618523FE)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Include
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simul_
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
+I (.\RTE\_Simul_\RTE_Components.h)(0x61852771)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
+I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.axf b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.axf
index 6a10fef..a9ef4c3 100644
Binary files a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.axf and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.axf differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.build_log.htm b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.build_log.htm
index 6c6ce22..a38b643 100644
--- a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.build_log.htm
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.build_log.htm
@@ -3,32 +3,39 @@
µVision Build Log
Tool Versions:
-IDE-Version: µVision V5.34.0.0
-Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: CSN CSN, INSA de Toulouse, LIC=----
+IDE-Version: µVision V5.33.0.0
+Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: Celia C, Insa, LIC=----
Tool Versions:
-Toolchain: MDK-Lite Version: 5.34.0.0
+Toolchain: MDK-Lite Version: 5.33.0.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 7 (build 960)
Assembler: Armasm.exe V5.06 update 7 (build 960)
Linker/Locator: ArmLink.exe V5.06 update 7 (build 960)
Library Manager: ArmAr.exe V5.06 update 7 (build 960)
Hex Converter: FromElf.exe V5.06 update 7 (build 960)
-CPU DLL: SARMCM3.DLL V5.34.0.0
+CPU DLL: SARMCM3.DLL V5.33.0.0
Dialog DLL: DARMSTM.DLL V1.68.0.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.8.0
Dialog DLL: TARMSTM.DLL V1.66.0.0
Project:
-U:\4IR\STM32\Projet_Voilier\projet_voilier\Keil_Elise_Yuwei\Local_Sources\bordage\drivers.uvprojx
-Project File Date: 11/04/2021
+C:\Users\chauz\Documents_non_drive\INSA\4A\S7\projet_voilier\projet_voilier\Keil_Elise_Yuwei\Local_Sources\bordage\drivers.uvprojx
+Project File Date: 11/05/2021
Output:
*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Build target 'Réel'
+Rebuild target 'Simulé'
+assembling startup_stm32f10x_md.s...
+compiling principal.c...
+compiling bordage.c...
+compiling MyTimer.c...
+compiling MyADC.c...
+compiling Driver_GPIO.c...
+compiling system_stm32f10x.c...
linking...
-Program Size: Code=2428 RO-data=268 RW-data=12 ZI-data=1028
+Program Size: Code=2432 RO-data=268 RW-data=4 ZI-data=1028
".\Objects\drivers_simule.axf" - 0 Error(s), 0 Warning(s).
Software Packages used:
@@ -47,19 +54,19 @@ Package Vendor: Keil
Collection of Component include folders:
.\RTE\Device\STM32F103RB
- .\RTE\_R_el
- C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
- C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
+ .\RTE\_Simul_
+ C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
+ C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
Collection of Component Files used:
* Component: ARM::CMSIS:CORE:5.4.0
* Component: Keil::Device:Startup:1.0.0
- Source file: Device\Source\ARM\STM32F1xx_OPT.s
- Include file: RTE_Driver\Config\RTE_Device.h
Source file: Device\Source\ARM\startup_stm32f10x_md.s
Source file: Device\Source\system_stm32f10x.c
+ Include file: RTE_Driver\Config\RTE_Device.h
+ Source file: Device\Source\ARM\STM32F1xx_OPT.s
Build Time Elapsed: 00:00:00