ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
+
+
+
+Function Pointers
+
+ - ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI9_5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text)
+
- TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_TRG_COM_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_UP_IRQHandler from mytimer.o(i.TIM1_UP_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM2_IRQHandler from mytimer.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM3_IRQHandler from mytimer.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM4_IRQHandler from mytimer.o(i.TIM4_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
+
- USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text)
+
- main from principal.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
+
+
+
+Global Symbols
+
+__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(.text)
+
+_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
+
+
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Calls]
+
+__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Called By]
+
+_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
+
+
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
+
+
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
+
+
__rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E))
+
+
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F))
+
+
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011))
+
+
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
+
NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
+
[Calls]
- >> __main_after_scatterload
+
+
[Called By]
+
+__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
+
+
MyADC_Init (Thumb, 66 bytes, Stack size 0 bytes, myadc.o(i.MyADC_Init))
+
[Called By]
+
+MyGPIO_Init (Thumb, 184 bytes, Stack size 12 bytes, driver_gpio.o(i.MyGPIO_Init))
+
[Stack]
- Max Depth = 12
- Call Chain = MyGPIO_Init
+
+
[Called By]
+
+MyTimer_Base_Init (Thumb, 106 bytes, Stack size 0 bytes, mytimer.o(i.MyTimer_Base_Init))
+
[Called By]
+
+MyTimer_PWM (Thumb, 120 bytes, Stack size 0 bytes, mytimer.o(i.MyTimer_PWM))
+
[Called By]
+
+Set_Duty_Cycle (Thumb, 76 bytes, Stack size 8 bytes, mytimer.o(i.Set_Duty_Cycle))
+
[Stack]
- Max Depth = 8
- Call Chain = Set_Duty_Cycle
+
+
[Called By]
+
+SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
+
[Stack]
- Max Depth = 28
- Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
+
+
[Calls]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(.text)
+
+TIM1_UP_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM1_UP_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM1_UP_IRQHandler
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+TIM2_IRQHandler (Thumb, 32 bytes, Stack size 8 bytes, mytimer.o(i.TIM2_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM2_IRQHandler
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+TIM3_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM3_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM3_IRQHandler
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+TIM4_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM4_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM4_IRQHandler
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
+
+
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
+
+
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
+
+
convert_single (Thumb, 52 bytes, Stack size 0 bytes, myadc.o(i.convert_single))
+
[Called By]
+
+main (Thumb, 124 bytes, Stack size 16 bytes, principal.o(i.main))
+
[Stack]
- Max Depth = 28
- Call Chain = main ⇒ MyGPIO_Init
+
+
[Calls]- >> convert_single
+
- >> Set_Duty_Cycle
+
- >> MyTimer_PWM
+
- >> MyTimer_Base_Init
+
- >> MyGPIO_Init
+
- >> MyADC_Init
+
+
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
+
+
+Local Symbols
+
+SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
+
[Stack]
- Max Depth = 20
- Call Chain = SetSysClock ⇒ SetSysClockTo72
+
+
[Calls]
+
[Called By]
+
+SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
+
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
+
+
[Called By]
+
+
+Undefined Global Symbols
+
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.lnp b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.lnp
new file mode 100644
index 0000000..ab3af48
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/drivers_simule.lnp
@@ -0,0 +1,11 @@
+--cpu Cortex-M3
+".\objects\principal.o"
+".\objects\bordage.o"
+".\objects\driver_gpio.o"
+".\objects\mytimer.o"
+".\objects\myadc.o"
+".\objects\startup_stm32f10x_md.o"
+".\objects\system_stm32f10x.o"
+--library_type=microlib --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\Listings\drivers_simule.map" -o .\Objects\drivers_simule.axf
\ No newline at end of file
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.crf b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.crf
new file mode 100644
index 0000000..09a8805
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.crf differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.d b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.d
new file mode 100644
index 0000000..5b2d3b4
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.d
@@ -0,0 +1,10 @@
+.\objects\myadc.o: Include\MyADC.c
+.\objects\myadc.o: Include\MyADC.h
+.\objects\myadc.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
+.\objects\myadc.o: .\RTE\_R_el\RTE_Components.h
+.\objects\myadc.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\myadc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\myadc.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\myadc.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\myadc.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\myadc.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.o b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.o
new file mode 100644
index 0000000..3872da2
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/myadc.o differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.crf b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.crf
new file mode 100644
index 0000000..8f2eea6
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.crf differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.d b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.d
new file mode 100644
index 0000000..c8fbd1a
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.d
@@ -0,0 +1,10 @@
+.\objects\mytimer.o: Include\MyTimer.c
+.\objects\mytimer.o: Include\MyTimer.h
+.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
+.\objects\mytimer.o: .\RTE\_R_el\RTE_Components.h
+.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\mytimer.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.o b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.o
new file mode 100644
index 0000000..7fe91c7
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/mytimer.o differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.crf b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.crf
new file mode 100644
index 0000000..3e7cd57
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.crf differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.d b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.d
new file mode 100644
index 0000000..b26a7e6
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.d
@@ -0,0 +1,12 @@
+.\objects\principal.o: Source\principal.c
+.\objects\principal.o: .\Include\Driver_GPIO.h
+.\objects\principal.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
+.\objects\principal.o: .\RTE\_R_el\RTE_Components.h
+.\objects\principal.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\principal.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\principal.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\principal.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\principal.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\principal.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
+.\objects\principal.o: .\Include\MyTimer.h
+.\objects\principal.o: .\Include\MyADC.h
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.o b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.o
new file mode 100644
index 0000000..fef6a73
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/principal.o differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/startup_stm32f10x_md.d b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/startup_stm32f10x_md.d
new file mode 100644
index 0000000..96d5fcf
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/startup_stm32f10x_md.d
@@ -0,0 +1 @@
+.\objects\startup_stm32f10x_md.o: RTE\Device\STM32F103RB\startup_stm32f10x_md.s
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/startup_stm32f10x_md.o b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/startup_stm32f10x_md.o
new file mode 100644
index 0000000..71745ea
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/startup_stm32f10x_md.o differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.crf b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.crf
new file mode 100644
index 0000000..784b70e
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.crf differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.d b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.d
new file mode 100644
index 0000000..ff9415b
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.d
@@ -0,0 +1,9 @@
+.\objects\system_stm32f10x.o: RTE\Device\STM32F103RB\system_stm32f10x.c
+.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
+.\objects\system_stm32f10x.o: .\RTE\_R_el\RTE_Components.h
+.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.o b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.o
new file mode 100644
index 0000000..dda16c2
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/system_stm32f10x.o differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/tests.crf b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/tests.crf
new file mode 100644
index 0000000..8a46d42
Binary files /dev/null and b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/tests.crf differ
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/tests.d b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/tests.d
new file mode 100644
index 0000000..6b73c60
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Objects/tests.d
@@ -0,0 +1,10 @@
+.\objects\tests.o: Source\tests.c
+.\objects\tests.o: .\Include\Driver_GPIO.h
+.\objects\tests.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
+.\objects\tests.o: .\RTE\_Simul_\RTE_Components.h
+.\objects\tests.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\tests.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\tests.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\tests.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\tests.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\tests.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/RTE_Device.h b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/RTE_Device.h
new file mode 100644
index 0000000..22d1da2
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/RTE_Device.h
@@ -0,0 +1,1828 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2016 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software in
+ * a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date: 09. September 2016
+ * $Revision: V1.1.2
+ *
+ * Project: RTE Device Configuration for STMicroelectronics STM32F1xx
+ *
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+ (num == 1) ? GPIOB : \
+ (num == 2) ? GPIOC : \
+ (num == 3) ? GPIOD : \
+ (num == 4) ? GPIOE : \
+ (num == 5) ? GPIOF : \
+ (num == 6) ? GPIOG : \
+ NULL)
+
+
+// Clock Configuration
+// High-speed Internal Clock <1-999999999>
+#define RTE_HSI 8000000
+// High-speed External Clock <1-999999999>
+#define RTE_HSE 25000000
+// System Clock <1-999999999>
+#define RTE_SYSCLK 72000000
+// HCLK Clock <1-999999999>
+#define RTE_HCLK 72000000
+// APB1 Clock <1-999999999>
+#define RTE_PCLK1 36000000
+// APB2 Clock <1-999999999>
+#define RTE_PCLK2 72000000
+// ADC Clock <1-999999999>
+#define RTE_ADCCLK 36000000
+// USB Clock
+#define RTE_USBCLK 48000000
+//
+
+
+// USART1 (Universal synchronous asynchronous receiver transmitter)
+// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1 0
+
+// USART1_TX Pin <0=>Not Used <1=>PA9
+#define RTE_USART1_TX_PORT_ID_DEF 0
+#if (RTE_USART1_TX_PORT_ID_DEF == 0)
+#define RTE_USART1_TX_DEF 0
+#elif (RTE_USART1_TX_PORT_ID_DEF == 1)
+#define RTE_USART1_TX_DEF 1
+#define RTE_USART1_TX_PORT_DEF GPIOA
+#define RTE_USART1_TX_BIT_DEF 9
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+// USART1_RX Pin <0=>Not Used <1=>PA10
+#define RTE_USART1_RX_PORT_ID_DEF 0
+#if (RTE_USART1_RX_PORT_ID_DEF == 0)
+#define RTE_USART1_RX_DEF 0
+#elif (RTE_USART1_RX_PORT_ID_DEF == 1)
+#define RTE_USART1_RX_DEF 1
+#define RTE_USART1_RX_PORT_DEF GPIOA
+#define RTE_USART1_RX_BIT_DEF 10
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+// USART1_CK Pin <0=>Not Used <1=>PA8
+#define RTE_USART1_CK_PORT_ID_DEF 0
+#if (RTE_USART1_CK_PORT_ID_DEF == 0)
+#define RTE_USART1_CK 0
+#elif (RTE_USART1_CK_PORT_ID_DEF == 1)
+#define RTE_USART1_CK 1
+#define RTE_USART1_CK_PORT_DEF GPIOA
+#define RTE_USART1_CK_BIT_DEF 8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+// USART1_CTS Pin <0=>Not Used <1=>PA11
+#define RTE_USART1_CTS_PORT_ID_DEF 0
+#if (RTE_USART1_CTS_PORT_ID_DEF == 0)
+#define RTE_USART1_CTS 0
+#elif (RTE_USART1_CTS_PORT_ID_DEF == 1)
+#define RTE_USART1_CTS 1
+#define RTE_USART1_CTS_PORT_DEF GPIOA
+#define RTE_USART1_CTS_BIT_DEF 11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+
+// USART1_RTS Pin <0=>Not Used <1=>PA12
+#define RTE_USART1_RTS_PORT_ID_DEF 0
+#if (RTE_USART1_RTS_PORT_ID_DEF == 0)
+#define RTE_USART1_RTS 0
+#elif (RTE_USART1_RTS_PORT_ID_DEF == 1)
+#define RTE_USART1_RTS 1
+#define RTE_USART1_RTS_PORT_DEF GPIOA
+#define RTE_USART1_RTS_BIT_DEF 12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+// USART1 Pin Remap
+// Enable USART1 Pin Remapping
+#define RTE_USART1_REMAP_FULL 0
+
+// USART1_TX Pin <0=>Not Used <1=>PB6
+#define RTE_USART1_TX_PORT_ID_FULL 0
+#if (RTE_USART1_TX_PORT_ID_FULL == 0)
+#define RTE_USART1_TX_FULL 0
+#elif (RTE_USART1_TX_PORT_ID_FULL == 1)
+#define RTE_USART1_TX_FULL 1
+#define RTE_USART1_TX_PORT_FULL GPIOB
+#define RTE_USART1_TX_BIT_FULL 6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+// USART1_RX Pin <0=>Not Used <1=>PB7
+#define RTE_USART1_RX_PORT_ID_FULL 0
+#if (RTE_USART1_RX_PORT_ID_FULL == 0)
+#define RTE_USART1_RX_FULL 0
+#elif (RTE_USART1_RX_PORT_ID_FULL == 1)
+#define RTE_USART1_RX_FULL 1
+#define RTE_USART1_RX_PORT_FULL GPIOB
+#define RTE_USART1_RX_BIT_FULL 7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+//
+
+#if (RTE_USART1_REMAP_FULL)
+#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP
+#define RTE_USART1_TX RTE_USART1_TX_FULL
+#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL
+#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL
+#define RTE_USART1_RX RTE_USART1_RX_FULL
+#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL
+#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL
+#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
+#else
+#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP
+#define RTE_USART1_TX RTE_USART1_TX_DEF
+#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF
+#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF
+#define RTE_USART1_RX RTE_USART1_RX_DEF
+#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF
+#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF
+#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <5=>5
+// Selects DMA Channel (only Channel 5 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Set DMA Channel priority
+//
+#define RTE_USART1_RX_DMA 0
+#define RTE_USART1_RX_DMA_NUMBER 1
+#define RTE_USART1_RX_DMA_CHANNEL 5
+#define RTE_USART1_RX_DMA_PRIORITY 0
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <4=>4
+// Selects DMA Channel (only Channel 4 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Set DMA Channel priority
+//
+#define RTE_USART1_TX_DMA 0
+#define RTE_USART1_TX_DMA_NUMBER 1
+#define RTE_USART1_TX_DMA_CHANNEL 4
+#define RTE_USART1_TX_DMA_PRIORITY 0
+//
+
+
+// USART2 (Universal synchronous asynchronous receiver transmitter)
+// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_USART2 0
+
+// USART2_TX Pin <0=>Not Used <1=>PA2
+#define RTE_USART2_TX_PORT_ID_DEF 0
+#if (RTE_USART2_TX_PORT_ID_DEF == 0)
+#define RTE_USART2_TX_DEF 0
+#elif (RTE_USART2_TX_PORT_ID_DEF == 1)
+#define RTE_USART2_TX_DEF 1
+#define RTE_USART2_TX_PORT_DEF GPIOA
+#define RTE_USART2_TX_BIT_DEF 2
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+// USART2_RX Pin <0=>Not Used <1=>PA3
+#define RTE_USART2_RX_PORT_ID_DEF 0
+#if (RTE_USART2_RX_PORT_ID_DEF == 0)
+#define RTE_USART2_RX_DEF 0
+#elif (RTE_USART2_RX_PORT_ID_DEF == 1)
+#define RTE_USART2_RX_DEF 1
+#define RTE_USART2_RX_PORT_DEF GPIOA
+#define RTE_USART2_RX_BIT_DEF 3
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+// USART2_CK Pin <0=>Not Used <1=>PA4
+#define RTE_USART2_CK_PORT_ID_DEF 0
+#if (RTE_USART2_CK_PORT_ID_DEF == 0)
+#define RTE_USART2_CK_DEF 0
+#elif (RTE_USART2_CK_PORT_ID_DEF == 1)
+#define RTE_USART2_CK_DEF 1
+#define RTE_USART2_CK_PORT_DEF GPIOA
+#define RTE_USART2_CK_BIT_DEF 4
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+// USART2_CTS Pin <0=>Not Used <1=>PA0
+#define RTE_USART2_CTS_PORT_ID_DEF 0
+#if (RTE_USART2_CTS_PORT_ID_DEF == 0)
+#define RTE_USART2_CTS_DEF 0
+#elif (RTE_USART2_CTS_PORT_ID_DEF == 1)
+#define RTE_USART2_CTS_DEF 1
+#define RTE_USART2_CTS_PORT_DEF GPIOA
+#define RTE_USART2_CTS_BIT_DEF 0
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+// USART2_RTS Pin <0=>Not Used <1=>PA1
+#define RTE_USART2_RTS_PORT_ID_DEF 0
+#if (RTE_USART2_RTS_PORT_ID_DEF == 0)
+#define RTE_USART2_RTS_DEF 0
+#elif (RTE_USART2_RTS_PORT_ID_DEF == 1)
+#define RTE_USART2_RTS_DEF 1
+#define RTE_USART2_RTS_PORT_DEF GPIOA
+#define RTE_USART2_RTS_BIT_DEF 1
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+// USART2 Pin Remap
+// Enable USART2 Pin Remapping
+#define RTE_USART2_REMAP_FULL 0
+
+// USART2_TX Pin <0=>Not Used <1=>PD5
+#define RTE_USART2_TX_PORT_ID_FULL 0
+#if (RTE_USART2_TX_PORT_ID_FULL == 0)
+#define RTE_USART2_TX_FULL 0
+#elif (RTE_USART2_TX_PORT_ID_FULL == 1)
+#define RTE_USART2_TX_FULL 1
+#define RTE_USART2_TX_PORT_FULL GPIOD
+#define RTE_USART2_TX_BIT_FULL 5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+// USART2_RX Pin <0=>Not Used <1=>PD6
+#define RTE_USART2_RX_PORT_ID_FULL 0
+#if (RTE_USART2_RX_PORT_ID_FULL == 0)
+#define RTE_USART2_RX_FULL 0
+#elif (RTE_USART2_RX_PORT_ID_FULL == 1)
+#define RTE_USART2_RX_FULL 1
+#define RTE_USART2_RX_PORT_FULL GPIOD
+#define RTE_USART2_RX_BIT_FULL 6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+// USART2_CK Pin <0=>Not Used <1=>PD7
+#define RTE_USART2_CK_PORT_ID_FULL 0
+#if (RTE_USART2_CK_PORT_ID_FULL == 0)
+#define RTE_USART2_CK_FULL 0
+#elif (RTE_USART2_CK_PORT_ID_FULL == 1)
+#define RTE_USART2_CK_FULL 1
+#define RTE_USART2_CK_PORT_FULL GPIOD
+#define RTE_USART2_CK_BIT_FULL 7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+// USART2_CTS Pin <0=>Not Used <1=>PD3
+#define RTE_USART2_CTS_PORT_ID_FULL 0
+#if (RTE_USART2_CTS_PORT_ID_FULL == 0)
+#define RTE_USART2_CTS_FULL 0
+#elif (RTE_USART2_CTS_PORT_ID_FULL == 1)
+#define RTE_USART2_CTS_FULL 1
+#define RTE_USART2_CTS_PORT_FULL GPIOD
+#define RTE_USART2_CTS_BIT_FULL 3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+// USART2_RTS Pin <0=>Not Used <1=>PD4
+#define RTE_USART2_RTS_PORT_ID_FULL 0
+#if (RTE_USART2_RTS_PORT_ID_FULL == 0)
+#define RTE_USART2_RTS_FULL 0
+#elif (RTE_USART2_RTS_PORT_ID_FULL == 1)
+#define RTE_USART2_RTS_FULL 1
+#define RTE_USART2_RTS_PORT_FULL GPIOD
+#define RTE_USART2_RTS_BIT_FULL 4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+//
+
+#if (RTE_USART2_REMAP_FULL)
+#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP
+#define RTE_USART2_TX RTE_USART2_TX_FULL
+#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL
+#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL
+#define RTE_USART2_RX RTE_USART2_RX_FULL
+#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL
+#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL
+#define RTE_USART2_CK RTE_USART2_CK_FULL
+#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL
+#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL
+#define RTE_USART2_CTS RTE_USART2_CTS_FULL
+#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL
+#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL
+#define RTE_USART2_RTS RTE_USART2_RTS_FULL
+#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL
+#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL
+#else
+#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP
+#define RTE_USART2_TX RTE_USART2_TX_DEF
+#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF
+#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF
+#define RTE_USART2_RX RTE_USART2_RX_DEF
+#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF
+#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF
+#define RTE_USART2_CK RTE_USART2_CK_DEF
+#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF
+#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF
+#define RTE_USART2_CTS RTE_USART2_CTS_DEF
+#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF
+#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF
+#define RTE_USART2_RTS RTE_USART2_RTS_DEF
+#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF
+#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <6=>6
+// Selects DMA Channel (only Channel 6 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Set DMA Channel priority
+//
+#define RTE_USART2_RX_DMA 0
+#define RTE_USART2_RX_DMA_NUMBER 1
+#define RTE_USART2_RX_DMA_CHANNEL 6
+#define RTE_USART2_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <7=>7
+// Selects DMA Channel (only Channel 7 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Set DMA Channel priority
+//
+#define RTE_USART2_TX_DMA 0
+#define RTE_USART2_TX_DMA_NUMBER 1
+#define RTE_USART2_TX_DMA_CHANNEL 7
+#define RTE_USART2_TX_DMA_PRIORITY 0
+
+//
+
+
+// USART3 (Universal synchronous asynchronous receiver transmitter)
+// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_USART3 0
+
+// USART3_TX Pin <0=>Not Used <1=>PB10
+#define RTE_USART3_TX_PORT_ID_DEF 0
+#if (RTE_USART3_TX_PORT_ID_DEF == 0)
+#define RTE_USART3_TX_DEF 0
+#elif (RTE_USART3_TX_PORT_ID_DEF == 1)
+#define RTE_USART3_TX_DEF 1
+#define RTE_USART3_TX_PORT_DEF GPIOB
+#define RTE_USART3_TX_BIT_DEF 10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+// USART3_RX Pin <0=>Not Used <1=>PB11
+#define RTE_USART3_RX_PORT_ID_DEF 0
+#if (RTE_USART3_RX_PORT_ID_DEF == 0)
+#define RTE_USART3_RX_DEF 0
+#elif (RTE_USART3_RX_PORT_ID_DEF == 1)
+#define RTE_USART3_RX_DEF 1
+#define RTE_USART3_RX_PORT_DEF GPIOB
+#define RTE_USART3_RX_BIT_DEF 11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+// USART3_CK Pin <0=>Not Used <1=>PB12
+#define RTE_USART3_CK_PORT_ID_DEF 0
+#if (RTE_USART3_CK_PORT_ID_DEF == 0)
+#define RTE_USART3_CK_DEF 0
+#elif (RTE_USART3_CK_PORT_ID_DEF == 1)
+#define RTE_USART3_CK_DEF 1
+#define RTE_USART3_CK_PORT_DEF GPIOB
+#define RTE_USART3_CK_BIT_DEF 12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+// USART3_CTS Pin <0=>Not Used <1=>PB13
+#define RTE_USART3_CTS_PORT_ID_DEF 0
+#if (RTE_USART3_CTS_PORT_ID_DEF == 0)
+#define RTE_USART3_CTS_DEF 0
+#elif (RTE_USART3_CTS_PORT_ID_DEF == 1)
+#define RTE_USART3_CTS_DEF 1
+#define RTE_USART3_CTS_PORT_DEF GPIOB
+#define RTE_USART3_CTS_BIT_DEF 13
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+// USART3_RTS Pin <0=>Not Used <1=>PB14
+#define RTE_USART3_RTS_PORT_ID_DEF 0
+#if (RTE_USART3_RTS_PORT_ID_DEF == 0)
+#define RTE_USART3_RTS_DEF 0
+#elif (RTE_USART3_RTS_PORT_ID_DEF == 1)
+#define RTE_USART3_RTS_DEF 1
+#define RTE_USART3_RTS_PORT_DEF GPIOB
+#define RTE_USART3_RTS_BIT_DEF 14
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+// USART3 Partial Pin Remap
+// Enable USART3 Partial Pin Remapping
+#define RTE_USART3_REMAP_PARTIAL 0
+
+// USART3_TX Pin <0=>Not Used <1=>PC10
+#define RTE_USART3_TX_PORT_ID_PARTIAL 0
+#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_TX_PARTIAL 0
+#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_TX_PARTIAL 1
+#define RTE_USART3_TX_PORT_PARTIAL GPIOC
+#define RTE_USART3_TX_BIT_PARTIAL 10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+// USART3_RX Pin <0=>Not Used <1=>PC11
+#define RTE_USART3_RX_PORT_ID_PARTIAL 0
+#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_RX_PARTIAL 0
+#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_RX_PARTIAL 1
+#define RTE_USART3_RX_PORT_PARTIAL GPIOC
+#define RTE_USART3_RX_BIT_PARTIAL 11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+// USART3_CK Pin <0=>Not Used <1=>PC12
+#define RTE_USART3_CK_PORT_ID_PARTIAL 0
+#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_CK_PARTIAL 0
+#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_CK_PARTIAL 1
+#define RTE_USART3_CK_PORT_PARTIAL GPIOC
+#define RTE_USART3_CK_BIT_PARTIAL 12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+//
+
+// USART3 Full Pin Remap
+// Enable USART3 Full Pin Remapping
+#define RTE_USART3_REMAP_FULL 0
+
+// USART3_TX Pin <0=>Not Used <1=>PD8
+#define RTE_USART3_TX_PORT_ID_FULL 0
+#if (RTE_USART3_TX_PORT_ID_FULL == 0)
+#define RTE_USART3_TX_FULL 0
+#elif (RTE_USART3_TX_PORT_ID_FULL == 1)
+#define RTE_USART3_TX_FULL 1
+#define RTE_USART3_TX_PORT_FULL GPIOD
+#define RTE_USART3_TX_BIT_FULL 8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+// USART3_RX Pin <0=>Not Used <1=>PD9
+#define RTE_USART3_RX_PORT_ID_FULL 0
+#if (RTE_USART3_RX_PORT_ID_FULL == 0)
+#define RTE_USART3_RX_FULL 0
+#elif (RTE_USART3_RX_PORT_ID_FULL == 1)
+#define RTE_USART3_RX_FULL 1
+#define RTE_USART3_RX_PORT_FULL GPIOD
+#define RTE_USART3_RX_BIT_FULL 9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+// USART3_CK Pin <0=>Not Used <1=>PD10
+#define RTE_USART3_CK_PORT_ID_FULL 0
+#if (RTE_USART3_CK_PORT_ID_FULL == 0)
+#define RTE_USART3_CK_FULL 0
+#elif (RTE_USART3_CK_PORT_ID_FULL == 1)
+#define RTE_USART3_CK_FULL 1
+#define RTE_USART3_CK_PORT_FULL GPIOD
+#define RTE_USART3_CK_BIT_FULL 10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+// USART3_CTS Pin <0=>Not Used <1=>PD11
+#define RTE_USART3_CTS_PORT_ID_FULL 0
+#if (RTE_USART3_CTS_PORT_ID_FULL == 0)
+#define RTE_USART3_CTS_FULL 0
+#elif (RTE_USART3_CTS_PORT_ID_FULL == 1)
+#define RTE_USART3_CTS_FULL 1
+#define RTE_USART3_CTS_PORT_FULL GPIOD
+#define RTE_USART3_CTS_BIT_FULL 11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+// USART3_RTS Pin <0=>Not Used <1=>PD12
+#define RTE_USART3_RTS_PORT_ID_FULL 0
+#if (RTE_USART3_RTS_PORT_ID_FULL == 0)
+#define RTE_USART3_RTS_FULL 0
+#elif (RTE_USART3_RTS_PORT_ID_FULL == 1)
+#define RTE_USART3_RTS_FULL 1
+#define RTE_USART3_RTS_PORT_FULL GPIOD
+#define RTE_USART3_RTS_BIT_FULL 12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+//
+
+#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
+#error "Invalid USART3 Pin Remap Configuration!"
+#endif
+
+#if (RTE_USART3_REMAP_FULL)
+#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL
+#define RTE_USART3_TX RTE_USART3_TX_FULL
+#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL
+#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL
+#define RTE_USART3_RX RTE_USART3_RX_FULL
+#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL
+#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL
+#define RTE_USART3_CK RTE_USART3_CK_FULL
+#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL
+#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL
+#define RTE_USART3_CTS RTE_USART3_CTS_FULL
+#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL
+#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL
+#define RTE_USART3_RTS RTE_USART3_RTS_FULL
+#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL
+#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL
+#elif (RTE_USART3_REMAP_PARTIAL)
+#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL
+#define RTE_USART3_TX RTE_USART3_TX_PARTIAL
+#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL
+#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL
+#define RTE_USART3_RX RTE_USART3_RX_PARTIAL
+#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL
+#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL
+#define RTE_USART3_CK RTE_USART3_CK_PARTIAL
+#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL
+#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL
+#define RTE_USART3_CTS RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
+#else
+#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP
+#define RTE_USART3_TX RTE_USART3_TX_DEF
+#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF
+#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF
+#define RTE_USART3_RX RTE_USART3_RX_DEF
+#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF
+#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF
+#define RTE_USART3_CK RTE_USART3_CK_DEF
+#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF
+#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF
+#define RTE_USART3_CTS RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <3=>3
+// Selects DMA Channel (only Channel 3 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Sets DMA Channel priority
+//
+#define RTE_USART3_RX_DMA 0
+#define RTE_USART3_RX_DMA_NUMBER 1
+#define RTE_USART3_RX_DMA_CHANNEL 3
+#define RTE_USART3_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <2=>2
+// Selects DMA Channel (only Channel 2 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Sets DMA Channel priority
+//
+#define RTE_USART3_TX_DMA 0
+#define RTE_USART3_TX_DMA_NUMBER 1
+#define RTE_USART3_TX_DMA_CHANNEL 2
+#define RTE_USART3_TX_DMA_PRIORITY 0
+
+//
+
+
+// UART4 (Universal asynchronous receiver transmitter)
+// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
+#define RTE_UART4 0
+#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP
+
+// UART4_TX Pin <0=>Not Used <1=>PC10
+#define RTE_UART4_TX_ID 0
+#if (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX 0
+#elif (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX 1
+#define RTE_UART4_TX_PORT GPIOC
+#define RTE_UART4_TX_BIT 10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+// UART4_RX Pin <0=>Not Used <1=>PC11
+#define RTE_UART4_RX_ID 0
+#if (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX 0
+#elif (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX 1
+#define RTE_UART4_RX_PORT GPIOC
+#define RTE_UART4_RX_BIT 11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+
+// DMA Rx
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <3=>3
+// Selects DMA Channel (only Channel 3 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Sets DMA Channel priority
+//
+#define RTE_UART4_RX_DMA 0
+#define RTE_UART4_RX_DMA_NUMBER 2
+#define RTE_UART4_RX_DMA_CHANNEL 3
+#define RTE_UART4_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <5=>5
+// Selects DMA Channel (only Channel 5 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+// Sets DMA Channel priority
+//
+#define RTE_UART4_TX_DMA 0
+#define RTE_UART4_TX_DMA_NUMBER 2
+#define RTE_UART4_TX_DMA_CHANNEL 5
+#define RTE_UART4_TX_DMA_PRIORITY 0
+
+//
+
+
+// UART5 (Universal asynchronous receiver transmitter)
+// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
+#define RTE_UART5 0
+#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP
+
+// UART5_TX Pin <0=>Not Used <1=>PC12
+#define RTE_UART5_TX_ID 0
+#if (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX 0
+#elif (RTE_UART5_TX_ID == 1)
+#define RTE_UART5_TX 1
+#define RTE_UART5_TX_PORT GPIOC
+#define RTE_UART5_TX_BIT 12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+// UART5_RX Pin <0=>Not Used <1=>PD2
+#define RTE_UART5_RX_ID 0
+#if (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX 0
+#elif (RTE_UART5_RX_ID == 1)
+#define RTE_UART5_RX 1
+#define RTE_UART5_RX_PORT GPIOD
+#define RTE_UART5_RX_BIT 2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+//
+
+
+// I2C1 (Inter-integrated Circuit Interface 1)
+// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
+#define RTE_I2C1 0
+
+// I2C1_SCL Pin <0=>PB6
+#define RTE_I2C1_SCL_PORT_ID_DEF 0
+#if (RTE_I2C1_SCL_PORT_ID_DEF == 0)
+#define RTE_I2C1_SCL_PORT_DEF GPIOB
+#define RTE_I2C1_SCL_BIT_DEF 6
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+// I2C1_SDA Pin <0=>PB7
+#define RTE_I2C1_SDA_PORT_ID_DEF 0
+#if (RTE_I2C1_SDA_PORT_ID_DEF == 0)
+#define RTE_I2C1_SDA_PORT_DEF GPIOB
+#define RTE_I2C1_SDA_BIT_DEF 7
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+// I2C1 Pin Remap
+// Enable I2C1 Pin Remapping
+#define RTE_I2C1_REMAP_FULL 0
+
+// I2C1_SCL Pin <0=>PB8
+#define RTE_I2C1_SCL_PORT_ID_FULL 0
+#if (RTE_I2C1_SCL_PORT_ID_FULL == 0)
+#define RTE_I2C1_SCL_PORT_FULL GPIOB
+#define RTE_I2C1_SCL_BIT_FULL 8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+// I2C1_SDA Pin <0=>PB9
+#define RTE_I2C1_SDA_PORT_ID_FULL 0
+#if (RTE_I2C1_SDA_PORT_ID_FULL == 0)
+#define RTE_I2C1_SDA_PORT_FULL GPIOB
+#define RTE_I2C1_SDA_BIT_FULL 9
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//
+
+#if (RTE_I2C1_REMAP_FULL)
+#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP
+#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL
+#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL
+#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL
+#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL
+#else
+#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP
+#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF
+#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF
+#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF
+#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF
+#endif
+
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <7=>7
+// Selects DMA Channel (only Channel 7 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_I2C1_RX_DMA 0
+#define RTE_I2C1_RX_DMA_NUMBER 1
+#define RTE_I2C1_RX_DMA_CHANNEL 7
+#define RTE_I2C1_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <6=>6
+// Selects DMA Channel (only Channel 6 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_I2C1_TX_DMA 0
+#define RTE_I2C1_TX_DMA_NUMBER 1
+#define RTE_I2C1_TX_DMA_CHANNEL 6
+#define RTE_I2C1_TX_DMA_PRIORITY 0
+
+//
+
+
+// I2C2 (Inter-integrated Circuit Interface 2)
+// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
+#define RTE_I2C2 0
+#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP
+
+// I2C2_SCL Pin <0=>PB10
+#define RTE_I2C2_SCL_PORT_ID 0
+#if (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT GPIOB
+#define RTE_I2C2_SCL_BIT 10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+// I2C2_SDA Pin <0=>PB11
+#define RTE_I2C2_SDA_PORT_ID 0
+#if (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT GPIOB
+#define RTE_I2C2_SDA_BIT 11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <5=>5
+// Selects DMA Channel (only Channel 5 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_I2C2_RX_DMA 1
+#define RTE_I2C2_RX_DMA_NUMBER 1
+#define RTE_I2C2_RX_DMA_CHANNEL 5
+#define RTE_I2C2_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <4=>4
+// Selects DMA Channel (only Channel 4 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_I2C2_TX_DMA 1
+#define RTE_I2C2_TX_DMA_NUMBER 1
+#define RTE_I2C2_TX_DMA_CHANNEL 4
+#define RTE_I2C2_TX_DMA_PRIORITY 0
+
+//
+
+
+// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
+#define RTE_SPI1 0
+
+// SPI1_NSS Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..G, y = 0..15)
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SPI1_NSS_PIN 1
+#define RTE_SPI1_NSS_PORT GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT 4
+
+// SPI1_SCK Pin <0=>PA5
+#define RTE_SPI1_SCK_PORT_ID_DEF 0
+#if (RTE_SPI1_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI1_SCK_PORT_DEF GPIOA
+#define RTE_SPI1_SCK_BIT_DEF 5
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+// SPI1_MISO Pin <0=>Not Used <1=>PA6
+#define RTE_SPI1_MISO_PORT_ID_DEF 0
+#if (RTE_SPI1_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI1_MISO_DEF 0
+#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI1_MISO_DEF 1
+#define RTE_SPI1_MISO_PORT_DEF GPIOA
+#define RTE_SPI1_MISO_BIT_DEF 6
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+// SPI1_MOSI Pin <0=>Not Used <1=>PA7
+#define RTE_SPI1_MOSI_PORT_ID_DEF 0
+#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI1_MOSI_DEF 0
+#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI1_MOSI_DEF 1
+#define RTE_SPI1_MOSI_PORT_DEF GPIOA
+#define RTE_SPI1_MOSI_BIT_DEF 7
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+// SPI1 Pin Remap
+// Enable SPI1 Pin Remapping.
+#define RTE_SPI1_REMAP 0
+
+// SPI1_SCK Pin <0=>PB3
+#define RTE_SPI1_SCK_PORT_ID_FULL 0
+#if (RTE_SPI1_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI1_SCK_PORT_FULL GPIOB
+#define RTE_SPI1_SCK_BIT_FULL 3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+// SPI1_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID_FULL 0
+#if (RTE_SPI1_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI1_MISO_FULL 0
+#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI1_MISO_FULL 1
+#define RTE_SPI1_MISO_PORT_FULL GPIOB
+#define RTE_SPI1_MISO_BIT_FULL 4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+// SPI1_MOSI Pin <0=>Not Used <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID_FULL 0
+#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI1_MOSI_FULL 0
+#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI1_MOSI_FULL 1
+#define RTE_SPI1_MOSI_PORT_FULL GPIOB
+#define RTE_SPI1_MOSI_BIT_FULL 5
+#else
+#error "Invalid SPI1_MOSI Pin Configuration!"
+#endif
+
+//
+
+#if (RTE_SPI1_REMAP)
+#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP
+#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL
+#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL
+#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL
+#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL
+#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL
+#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL
+#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL
+#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL
+#else
+#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP
+#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF
+#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF
+#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF
+#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF
+#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF
+#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF
+#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF
+#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <2=>2
+// Selects DMA Channel (only Channel 2 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI1_RX_DMA 0
+#define RTE_SPI1_RX_DMA_NUMBER 1
+#define RTE_SPI1_RX_DMA_CHANNEL 2
+#define RTE_SPI1_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <3=>3
+// Selects DMA Channel (only Channel 3 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI1_TX_DMA 0
+#define RTE_SPI1_TX_DMA_NUMBER 1
+#define RTE_SPI1_TX_DMA_CHANNEL 3
+#define RTE_SPI1_TX_DMA_PRIORITY 0
+
+//
+
+
+// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
+#define RTE_SPI2 0
+
+// SPI2_NSS Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..G, y = 0..15)
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SPI2_NSS_PIN 1
+#define RTE_SPI2_NSS_PORT GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT 12
+
+// SPI2_SCK Pin <0=>PB13
+#define RTE_SPI2_SCK_PORT_ID 0
+#if (RTE_SPI2_SCK_PORT_ID == 0)
+#define RTE_SPI2_SCK_PORT GPIOB
+#define RTE_SPI2_SCK_BIT 13
+#define RTE_SPI2_SCK_REMAP 0
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+// SPI2_MISO Pin <0=>Not Used <1=>PB14
+#define RTE_SPI2_MISO_PORT_ID 0
+#if (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO 0
+#elif (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO 1
+#define RTE_SPI2_MISO_PORT GPIOB
+#define RTE_SPI2_MISO_BIT 14
+#define RTE_SPI2_MISO_REMAP 0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+// SPI2_MOSI Pin <0=>Not Used <1=>PB15
+#define RTE_SPI2_MOSI_PORT_ID 0
+#if (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI 0
+#elif (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI 1
+#define RTE_SPI2_MOSI_PORT GPIOB
+#define RTE_SPI2_MOSI_BIT 15
+#define RTE_SPI2_MOSI_REMAP 0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+// DMA Rx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <4=>4
+// Selects DMA Channel (only Channel 4 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI2_RX_DMA 0
+#define RTE_SPI2_RX_DMA_NUMBER 1
+#define RTE_SPI2_RX_DMA_CHANNEL 4
+#define RTE_SPI2_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <1=>1
+// Selects DMA Number (only DMA1 can be used)
+// Channel <5=>5
+// Selects DMA Channel (only Channel 5 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI2_TX_DMA 0
+#define RTE_SPI2_TX_DMA_NUMBER 1
+#define RTE_SPI2_TX_DMA_CHANNEL 5
+#define RTE_SPI2_TX_DMA_PRIORITY 0
+
+//
+
+
+// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
+#define RTE_SPI3 0
+
+// SPI3_NSS Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..G, y = 0..15)
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SPI3_NSS_PIN 1
+#define RTE_SPI3_NSS_PORT GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT 15
+
+// SPI3_SCK Pin <0=>PB3
+#define RTE_SPI3_SCK_PORT_ID_DEF 0
+#if (RTE_SPI3_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI3_SCK_PORT_DEF GPIOB
+#define RTE_SPI3_SCK_BIT_DEF 3
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+// SPI3_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI3_MISO_PORT_ID_DEF 0
+#if (RTE_SPI3_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI3_MISO_DEF 0
+#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI3_MISO_DEF 1
+#define RTE_SPI3_MISO_PORT_DEF GPIOB
+#define RTE_SPI3_MISO_BIT_DEF 4
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+// SPI3_MOSI <0=>Not Used Pin <1=>PB5
+#define RTE_SPI3_MOSI_PORT_ID_DEF 0
+#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI3_MOSI_DEF 0
+#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI3_MOSI_DEF 1
+#define RTE_SPI3_MOSI_PORT_DEF GPIOB
+#define RTE_SPI3_MOSI_BIT_DEF 5
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+// SPI3 Pin Remap
+// Enable SPI3 Pin Remapping.
+// SPI 3 Pin Remapping is available only in connectivity line devices!
+#define RTE_SPI3_REMAP 0
+
+// SPI3_SCK Pin <0=>PC10
+#define RTE_SPI3_SCK_PORT_ID_FULL 0
+#if (RTE_SPI3_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI3_SCK_PORT_FULL GPIOC
+#define RTE_SPI3_SCK_BIT_FULL 10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+// SPI3_MISO Pin <0=>Not Used <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID_FULL 0
+#if (RTE_SPI3_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI3_MISO_FULL 0
+#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI3_MISO_FULL 1
+#define RTE_SPI3_MISO_PORT_FULL GPIOC
+#define RTE_SPI3_MISO_BIT_FULL 11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+// SPI3_MOSI Pin <0=>Not Used <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID_FULL 0
+#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI3_MOSI_FULL 0
+#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI3_MOSI_FULL 1
+#define RTE_SPI3_MOSI_PORT_FULL GPIOC
+#define RTE_SPI3_MOSI_BIT_FULL 12
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+//
+
+#if (RTE_SPI3_REMAP)
+#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP
+#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL
+#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL
+#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL
+#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL
+#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL
+#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL
+#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL
+#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL
+#else
+#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP
+#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF
+#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF
+#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF
+#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF
+#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF
+#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF
+#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF
+#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF
+#endif
+
+// DMA Rx
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <1=>1
+// Selects DMA Channel (only Channel 1 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI3_RX_DMA 0
+#define RTE_SPI3_RX_DMA_NUMBER 2
+#define RTE_SPI3_RX_DMA_CHANNEL 1
+#define RTE_SPI3_RX_DMA_PRIORITY 0
+
+// DMA Tx
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <2=>2
+// Selects DMA Channel (only Channel 2 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SPI3_TX_DMA 0
+#define RTE_SPI3_TX_DMA_NUMBER 2
+#define RTE_SPI3_TX_DMA_CHANNEL 2
+#define RTE_SPI3_TX_DMA_PRIORITY 0
+
+//
+
+
+// SDIO (Secure Digital Input/Output) [Driver_MCI0]
+// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
+#define RTE_SDIO 0
+
+// SDIO Peripheral Bus
+// SDIO_CK Pin <0=>PC12
+#define RTE_SDIO_CK_PORT_ID 0
+#if (RTE_SDIO_CK_PORT_ID == 0)
+ #define RTE_SDIO_CK_PORT GPIOC
+ #define RTE_SDIO_CK_PIN 12
+#else
+ #error "Invalid SDIO_CLK Pin Configuration!"
+#endif
+// SDIO_CMD Pin <0=>PD2
+#define RTE_SDIO_CMD_PORT_ID 0
+#if (RTE_SDIO_CMD_PORT_ID == 0)
+ #define RTE_SDIO_CMD_PORT GPIOD
+ #define RTE_SDIO_CMD_PIN 2
+#else
+ #error "Invalid SDIO_CMD Pin Configuration!"
+#endif
+// SDIO_D0 Pin <0=>PC8
+#define RTE_SDIO_D0_PORT_ID 0
+#if (RTE_SDIO_D0_PORT_ID == 0)
+ #define RTE_SDIO_D0_PORT GPIOC
+ #define RTE_SDIO_D0_PIN 8
+#else
+ #error "Invalid SDIO_DAT0 Pin Configuration!"
+#endif
+// SDIO_D[1 .. 3]
+#define RTE_SDIO_BUS_WIDTH_4 1
+// SDIO_D1 Pin <0=>PC9
+#define RTE_SDIO_D1_PORT_ID 0
+#if (RTE_SDIO_D1_PORT_ID == 0)
+ #define RTE_SDIO_D1_PORT GPIOC
+ #define RTE_SDIO_D1_PIN 9
+#else
+ #error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+// SDIO_D2 Pin <0=>PC10
+#define RTE_SDIO_D2_PORT_ID 0
+#if (RTE_SDIO_D2_PORT_ID == 0)
+ #define RTE_SDIO_D2_PORT GPIOC
+ #define RTE_SDIO_D2_PIN 10
+#else
+ #error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+// SDIO_D3 Pin <0=>PC11
+#define RTE_SDIO_D3_PORT_ID 0
+#if (RTE_SDIO_D3_PORT_ID == 0)
+ #define RTE_SDIO_D3_PORT GPIOC
+ #define RTE_SDIO_D3_PIN 11
+#else
+ #error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+// SDIO_D[1 .. 3]
+// SDIO_D[4 .. 7]
+#define RTE_SDIO_BUS_WIDTH_8 0
+// SDIO_D4 Pin <0=>PB8
+#define RTE_SDIO_D4_PORT_ID 0
+#if (RTE_SDIO_D4_PORT_ID == 0)
+ #define RTE_SDIO_D4_PORT GPIOB
+ #define RTE_SDIO_D4_PIN 8
+#else
+ #error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+// SDIO_D5 Pin <0=>PB9
+#define RTE_SDIO_D5_PORT_ID 0
+#if (RTE_SDIO_D5_PORT_ID == 0)
+ #define RTE_SDIO_D5_PORT GPIOB
+ #define RTE_SDIO_D5_PIN 9
+#else
+ #error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+// SDIO_D6 Pin <0=>PC6
+#define RTE_SDIO_D6_PORT_ID 0
+#if (RTE_SDIO_D6_PORT_ID == 0)
+ #define RTE_SDIO_D6_PORT GPIOC
+ #define RTE_SDIO_D6_PIN 6
+#else
+ #error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+// SDIO_D7 Pin <0=>PC7
+#define RTE_SDIO_D7_PORT_ID 0
+#if (RTE_SDIO_D7_PORT_ID == 0)
+ #define RTE_SDIO_D7_PORT GPIOC
+ #define RTE_SDIO_D7_PIN 7
+#else
+ #error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+// SDIO_D[4 .. 7]
+// SDIO Peripheral Bus
+
+// Card Detect Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SDIO_CD_EN 1
+#define RTE_SDIO_CD_ACTIVE 0
+#define RTE_SDIO_CD_PORT GPIO_PORT(5)
+#define RTE_SDIO_CD_PIN 11
+
+// Write Protect Pin
+// Configure Pin if exists
+// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_SDIO_WP_EN 0
+#define RTE_SDIO_WP_ACTIVE 1
+#define RTE_SDIO_WP_PORT GPIO_PORT(0)
+#define RTE_SDIO_WP_PIN 10
+
+// DMA
+// Number <2=>2
+// Selects DMA Number (only DMA2 can be used)
+// Channel <4=>4
+// Selects DMA Channel (only Channel 4 can be used)
+// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+// Selects DMA Priority
+//
+#define RTE_SDIO_DMA_NUMBER 2
+#define RTE_SDIO_DMA_CHANNEL 4
+#define RTE_SDIO_DMA_PRIORITY 0
+
+//
+
+
+// CAN1 (Controller Area Network 1) [Driver_CAN1]
+// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
+#define RTE_CAN1 0
+
+// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
+#define RTE_CAN1_RX_PORT_ID 0
+#if (RTE_CAN1_RX_PORT_ID == 0)
+#define RTE_CAN1_RX_PORT GPIOA
+#define RTE_CAN1_RX_BIT 11
+#elif (RTE_CAN1_RX_PORT_ID == 1)
+#define RTE_CAN1_RX_PORT GPIOB
+#define RTE_CAN1_RX_BIT 8
+#elif (RTE_CAN1_RX_PORT_ID == 2)
+#define RTE_CAN1_RX_PORT GPIOD
+#define RTE_CAN1_RX_BIT 0
+#else
+#error "Invalid CAN1_RX Pin Configuration!"
+#endif
+
+// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
+#define RTE_CAN1_TX_PORT_ID 0
+#if (RTE_CAN1_TX_PORT_ID == 0)
+#define RTE_CAN1_TX_PORT GPIOA
+#define RTE_CAN1_TX_BIT 12
+#elif (RTE_CAN1_TX_PORT_ID == 1)
+#define RTE_CAN1_TX_PORT GPIOB
+#define RTE_CAN1_TX_BIT 9
+#elif (RTE_CAN1_TX_PORT_ID == 2)
+#define RTE_CAN1_TX_PORT GPIOD
+#define RTE_CAN1_TX_BIT 1
+#else
+#error "Invalid CAN1_TX Pin Configuration!"
+#endif
+
+//
+
+
+// CAN2 (Controller Area Network 2) [Driver_CAN2]
+// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
+#define RTE_CAN2 0
+
+// CAN2_RX Pin <0=>PB5 <1=>PB12
+#define RTE_CAN2_RX_PORT_ID 0
+#if (RTE_CAN2_RX_PORT_ID == 0)
+#define RTE_CAN2_RX_PORT GPIOB
+#define RTE_CAN2_RX_BIT 5
+#elif (RTE_CAN2_RX_PORT_ID == 1)
+#define RTE_CAN2_RX_PORT GPIOB
+#define RTE_CAN2_RX_BIT 12
+#else
+#error "Invalid CAN2_RX Pin Configuration!"
+#endif
+
+// CAN2_TX Pin <0=>PB6 <1=>PB13
+#define RTE_CAN2_TX_PORT_ID 0
+#if (RTE_CAN2_TX_PORT_ID == 0)
+#define RTE_CAN2_TX_PORT GPIOB
+#define RTE_CAN2_TX_BIT 6
+#elif (RTE_CAN2_TX_PORT_ID == 1)
+#define RTE_CAN2_TX_PORT GPIOB
+#define RTE_CAN2_TX_BIT 13
+#else
+#error "Invalid CAN2_TX Pin Configuration!"
+#endif
+
+//
+
+
+// ETH (Ethernet Interface) [Driver_ETH_MAC0]
+// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
+#define RTE_ETH 0
+
+// MII (Media Independent Interface)
+// Enable Media Independent Interface pin configuration
+#define RTE_ETH_MII 0
+
+// ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID 0
+#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN 3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+// ETH_MII_TXD0 Pin <0=>PB12
+#define RTE_ETH_MII_TXD0_PORT_ID 0
+#if (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT GPIOB
+#define RTE_ETH_MII_TXD0_PIN 12
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+// ETH_MII_TXD1 Pin <0=>PB13
+#define RTE_ETH_MII_TXD1_PORT_ID 0
+#if (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT GPIOB
+#define RTE_ETH_MII_TXD1_PIN 13
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+// ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID 0
+#if (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT GPIOC
+#define RTE_ETH_MII_TXD2_PIN 2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+// ETH_MII_TXD3 Pin <0=>PB8
+#define RTE_ETH_MII_TXD3_PORT_ID 0
+#if (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT GPIOB
+#define RTE_ETH_MII_TXD3_PIN 8
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+// ETH_MII_TX_EN Pin <0=>PB11
+#define RTE_ETH_MII_TX_EN_PORT_ID 0
+#if (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT GPIOB
+#define RTE_ETH_MII_TX_EN_PIN 11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+// ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID 0
+#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN 1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+// ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_DEF 0
+
+// ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_DEF 0
+
+// ETH_MII_RXD2 Pin <0=>PB0
+#define RTE_ETH_MII_RXD2_DEF 0
+
+// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
+#define RTE_ETH_MII_RXD3_DEF 0
+
+// ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_DEF 0
+
+// ETH_MII_RX_ER Pin <0=>PB10
+#define RTE_ETH_MII_RX_ER_PORT_ID 0
+#if (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT GPIOB
+#define RTE_ETH_MII_RX_ER_PIN 10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+// ETH_MII_CRS Pin <0=>PA0
+#define RTE_ETH_MII_CRS_PORT_ID 0
+#if (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT GPIOA
+#define RTE_ETH_MII_CRS_PIN 0
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+// ETH_MII_COL Pin <0=>PA3
+#define RTE_ETH_MII_COL_PORT_ID 0
+#if (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT GPIOA
+#define RTE_ETH_MII_COL_PIN 3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+// Ethernet MAC I/O remapping
+// Remap Ethernet pins
+#define RTE_ETH_MII_REMAP 0
+
+// ETH_MII_RXD0 Pin <1=>PD9
+#define RTE_ETH_MII_RXD0_REMAP 1
+
+// ETH_MII_RXD1 Pin <1=>PD10
+#define RTE_ETH_MII_RXD1_REMAP 1
+
+// ETH_MII_RXD2 Pin <1=>PD11
+#define RTE_ETH_MII_RXD2_REMAP 1
+
+// ETH_MII_RXD3 Pin <1=>PD12
+#define RTE_ETH_MII_RXD3_REMAP 1
+
+// ETH_MII_RX_DV Pin <1=>PD8
+#define RTE_ETH_MII_RX_DV_REMAP 1
+//
+
+//
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
+#define RTE_ETH_MII_RXD0_PORT GPIOC
+#define RTE_ETH_MII_RXD0_PIN 4
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
+#define RTE_ETH_MII_RXD0_PORT GPIOD
+#define RTE_ETH_MII_RXD0_PIN 9
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
+#define RTE_ETH_MII_RXD1_PORT GPIOC
+#define RTE_ETH_MII_RXD1_PIN 5
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
+#define RTE_ETH_MII_RXD1_PORT GPIOD
+#define RTE_ETH_MII_RXD1_PIN 10
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
+#define RTE_ETH_MII_RXD2_PORT GPIOB
+#define RTE_ETH_MII_RXD2_PIN 0
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
+#define RTE_ETH_MII_RXD2_PORT GPIOD
+#define RTE_ETH_MII_RXD2_PIN 11
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
+#define RTE_ETH_MII_RXD3_PORT GPIOB
+#define RTE_ETH_MII_RXD3_PIN 1
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
+#define RTE_ETH_MII_RXD3_PORT GPIOD
+#define RTE_ETH_MII_RXD3_PIN 12
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
+#define RTE_ETH_MII_RX_DV_PORT GPIOA
+#define RTE_ETH_MII_RX_DV_PIN 7
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
+#define RTE_ETH_MII_RX_DV_PORT GPIOD
+#define RTE_ETH_MII_RX_DV_PIN 8
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+
+// RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII 0
+
+// ETH_RMII_TXD0 Pin <0=>PB12
+#define RTE_ETH_RMII_TXD0_PORT_ID 0
+#if (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT GPIOB
+#define RTE_ETH_RMII_TXD0_PIN 12
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+// ETH_RMII_TXD1 Pin <0=>PB13
+#define RTE_ETH_RMII_TXD1_PORT_ID 0
+#if (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT GPIOB
+#define RTE_ETH_RMII_TXD1_PIN 13
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+// ETH_RMII_TX_EN Pin <0=>PB11
+#define RTE_ETH_RMII_TX_EN_PORT_ID 0
+#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN 11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+// ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_DEF 0
+
+// ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_DEF 0
+
+// ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID 0
+#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN 1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+// ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_DEF 0
+
+// Ethernet MAC I/O remapping
+// Remap Ethernet pins
+#define RTE_ETH_RMII_REMAP 0
+// ETH_RMII_RXD0 Pin <1=>PD9
+#define RTE_ETH_RMII_RXD0_REMAP 1
+
+// ETH_RMII_RXD1 Pin <1=>PD10
+#define RTE_ETH_RMII_RXD1_REMAP 1
+
+// ETH_RMII_CRS_DV Pin <1=>PD8
+#define RTE_ETH_RMII_CRS_DV_REMAP 1
+//
+
+#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
+#define RTE_ETH_RMII_RXD0_PORT GPIOC
+#define RTE_ETH_RMII_RXD0_PIN 4
+#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
+#define RTE_ETH_RMII_RXD0_PORT GPIOD
+#define RTE_ETH_RMII_RXD0_PIN 9
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
+#define RTE_ETH_RMII_RXD1_PORT GPIOC
+#define RTE_ETH_RMII_RXD1_PIN 5
+#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
+#define RTE_ETH_RMII_RXD1_PORT GPIOD
+#define RTE_ETH_RMII_RXD1_PIN 10
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+
+#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
+#define RTE_ETH_RMII_CRS_DV_PORT GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN 7
+#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
+#define RTE_ETH_RMII_CRS_DV_PORT GPIOD
+#define RTE_ETH_RMII_CRS_DV_PIN 8
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//
+
+// Management Data Interface
+// ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID 0
+#if (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT GPIOC
+#define RTE_ETH_MDI_MDC_PIN 1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+// ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID 0
+#if (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT GPIOA
+#define RTE_ETH_MDI_MDIO_PIN 2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//
+
+// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
+#define RTE_ETH_REF_CLOCK_ID 0
+#if (RTE_ETH_REF_CLOCK_ID == 0)
+#define RTE_ETH_REF_CLOCK 0
+#elif (RTE_ETH_REF_CLOCK_ID == 1)
+#define RTE_ETH_REF_CLOCK 1
+#else
+#error "Invalid MCO Ethernet Reference Clock Configuration!"
+#endif
+//
+
+
+// USB Device Full-speed
+// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_DEVICE 0
+
+// CON On/Off Pin
+// Configure Pin for driving D+ pull-up
+// GPIO Pxy (x = A..G, y = 0..15)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_USB_DEVICE_CON_PIN 1
+#define RTE_USB_DEVICE_CON_ACTIVE 0
+#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1)
+#define RTE_USB_DEVICE_CON_BIT 14
+
+//
+
+
+// USB OTG Full-speed
+#define RTE_USB_OTG_FS 0
+
+// Host [Driver_USBH0]
+// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST 0
+
+// VBUS Power On/Off Pin
+// Configure Pin for driving VBUS
+// GPIO Pxy (x = A..G, y = 0..15)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_OTG_FS_VBUS_PIN 1
+#define RTE_OTG_FS_VBUS_ACTIVE 0
+#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2)
+#define RTE_OTG_FS_VBUS_BIT 9
+
+// Overcurrent Detection Pin
+// Configure Pin for overcurrent detection
+// GPIO Pxy (x = A..G, y = 0..15)
+// Active State <0=>Low <1=>High
+// Selects Active State Logical Level
+// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+// <4=>GPIOE <5=>GPIOF <6=>GPIOG
+// Selects Port Name
+// Bit <0-15>
+// Selects Port Bit
+//
+#define RTE_OTG_FS_OC_PIN 1
+#define RTE_OTG_FS_OC_ACTIVE 0
+#define RTE_OTG_FS_OC_PORT GPIO_PORT(4)
+#define RTE_OTG_FS_OC_BIT 1
+//
+
+//
+
+
+#endif /* __RTE_DEVICE_H */
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
new file mode 100644
index 0000000..74da96c
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
@@ -0,0 +1,307 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_md.s
+;* Author : MCD Application Team
+;* Version : V3.5.0
+;* Date : 11-March-2011
+;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure the clock system
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1_2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/system_stm32f10x.c b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/system_stm32f10x.c
new file mode 100644
index 0000000..71efc85
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/Device/STM32F103RB/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f10x_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+ * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/** @addtogroup STM32F10x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f10x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your device's
+ maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to drive
+ the System clock.
+ If you are using different crystal you have to adapt those functions accordingly.
+ */
+
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz 24000000
+#else
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz 24000000 */
+/* #define SYSCLK_FREQ_36MHz 36000000 */
+/* #define SYSCLK_FREQ_48MHz 48000000 */
+/* #define SYSCLK_FREQ_56MHz 56000000 */
+#define SYSCLK_FREQ_72MHz 72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
+ STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+ uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+ static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+ static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+ static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+ static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+ static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+ static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+ SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+ SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+ SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+ SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+ SetSysClockTo72();
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ source (default after reset) */
+}
+
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x44444B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+ if (HSE_VALUE <= 24000000)
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+ }
+ else
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+ }
+#endif /* STM32F10X_CL */
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* Select HSE as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo24(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo36(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+#else
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo48(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo56(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL7);
+#else
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo72(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+#else
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_R_el/RTE_Components.h b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_R_el/RTE_Components.h
new file mode 100644
index 0000000..97a4d81
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_R_el/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'drivers'
+ * Target: 'Réel'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_Simul_/RTE_Components.h b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_Simul_/RTE_Components.h
new file mode 100644
index 0000000..e5bd9b5
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_Simul_/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'drivers'
+ * Target: 'Simulé'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_Target_1/RTE_Components.h b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_Target_1/RTE_Components.h
new file mode 100644
index 0000000..b4122ad
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/RTE/_Target_1/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'drivers'
+ * Target: 'Target 1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Source/bordage.c b/Keil_Elise_Yuwei/Local_Sources/bordage/Source/bordage.c
new file mode 100644
index 0000000..4482053
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Source/bordage.c
@@ -0,0 +1,34 @@
+#include "Driver_GPIO.h"
+#include "MyTimer.h"
+#include "MyADC.h"
+#include "stm32f10x.h"
+
+#define TIMER_PWM (TIM3)
+#define CANAL_PWM (1)
+
+
+/*
+*****************************************************************************************
+* @brief
+* @param -> int angle : angle que l'on veut donner à la voile (entre 0 et 90°)
+* @Note ->
+*************************************************************************************************
+*/
+int bordage ( int angle ) {
+
+ float duty_cycle = ((float) angle)/18.0 + 5.0; // convertit l'angle en rapport cyclique pour la commande du servo moteur
+
+ // Configuration du timer avec une période de 20ms
+ MyTimer_Struct_TypeDef TIM;
+ TIM.Timer = TIMER_PWM;
+ TIM.ARR = 59999;
+ TIM.PSC = 23;
+ MyTimer_Base_Init(&TIM);
+
+ // PWM
+ MyTimer_PWM (TIMER_PWM, CANAL_PWM);
+ Set_Duty_Cycle(TIMER_PWM, CANAL_PWM, duty_cycle);
+
+
+ return 0;
+}
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/Source/principal.c b/Keil_Elise_Yuwei/Local_Sources/bordage/Source/principal.c
new file mode 100644
index 0000000..6de53fd
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/Source/principal.c
@@ -0,0 +1,52 @@
+#include "Driver_GPIO.h"
+#include "MyTimer.h"
+#include "MyADC.h"
+#include "stm32f10x.h"
+
+MyGPIO_Struct_TypeDef GPIO_Struct;
+
+void CallBack ( void )
+{
+ /* Le code à exécuter pendant l’interruption */
+ MyGPIO_Toggle (GPIO_Struct.GPIO, GPIO_Struct.GPIO_Pin) ;
+}
+
+
+int main ( void ) {
+
+ int res = 0;
+
+ // Configuration du timer
+ MyTimer_Struct_TypeDef TIM;
+ TIM.Timer = TIM3;
+ TIM.ARR = 719; //2000
+ TIM.PSC = 0; // 18000
+ MyTimer_Base_Init(&TIM);
+
+ // Configuration de la diode PA.6
+ GPIO_Struct.GPIO = GPIOA;
+ GPIO_Struct.GPIO_Pin = 6;
+ GPIO_Struct.GPIO_Conf = AltOut_Ppull;
+ MyGPIO_Init(&GPIO_Struct);
+
+ // PWM à 100kHz avec un rapport cyclique de 0% sur le Timer 3 et le canal 1.
+ MyTimer_PWM (TIM3, 1);
+ Set_Duty_Cycle(TIM3, 1, 0);
+
+ // Configuration de la broche PB.0
+ GPIO_Struct.GPIO = GPIOB;
+ GPIO_Struct.GPIO_Pin = 0;
+ GPIO_Struct.GPIO_Conf = In_Analog;
+ MyGPIO_Init(&GPIO_Struct);
+
+ MyADC_Init(8);
+
+
+
+
+while (1)
+{
+ res = convert_single(); // conversion
+ Set_Duty_Cycle(TIM3, 1, 100 * res / 0xFFF ); // mise à jour de l’intensité de la led
+}
+}
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvguix.lerouxde b/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvguix.lerouxde
new file mode 100644
index 0000000..fbaa77b
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvguix.lerouxde
@@ -0,0 +1,3695 @@
+
+
+
+ -6.1
+
+ ### uVision Project, (C) Keil Software
+
+
+ U:\4IR\STM32\Projet_Voilier\projet_voilier\Keil_Elise_Yuwei\Local_Sources\bordage\Source
+
+
+
+
+ System Viewer\GPIOA
+ 35902
+
+ 83
+
+
+ System Viewer\GPIOB
+ 35901
+
+ 83
+
+
+ System Viewer\TIM2
+ 35905
+
+ 85
+
+
+ System Viewer\TIM3
+ 35904
+
+ 83
+
+
+ System Viewer\TIM2
+ 35905
+
+ 85
+
+
+
+
+
+ 38003
+ Registers
+ 150 96
+
+
+ 346
+ Code Coverage
+ 1090 160
+
+
+ 204
+ Performance Analyzer
+ 1250
+
+
+
+
+
+ 35141
+ Event Statistics
+
+ 200 50 700
+
+
+ 1506
+ Symbols
+
+ 85 85 85
+
+
+ 1936
+ Watch 1
+
+ 200 133 133
+
+
+ 1937
+ Watch 2
+
+ 200 133 133
+
+
+ 1935
+ Call Stack + Locals
+
+ 200 133 133
+
+
+ 2506
+ Trace Data
+ FiltIdx=0;DescrEn=0;DescrHeight=4;FuncTrc=1;FindType=8;ColWidths=004B00870082005F004600E600C80096
+ 75 135 130 95 70 230 200 150
+
+
+ 466
+ Source Browser
+ 500
+ 300
+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 58
+ 10
+
+
+
+
+
+
+ 44
+ 2
+ 3
+
+ -1
+ -1
+
+
+ -1
+ -1
+
+
+ 208
+ 208
+ 1744
+ 1017
+
+
+
+ 0
+
+ 947
+ 01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000006000000020000000100000064553A5C3449525C53544D33325C50726F6A65745F566F696C6965725C70726F6A65745F766F696C6965725C4B65696C5F456C6973655F59757765695C4C6F63616C5F536F75726365735C626F72646167655C536F757263655C7072696E636970616C2E63000000000B7072696E636970616C2E6300000000C5D4F200FFFFFFFF63553A5C3449525C53544D33325C50726F6A65745F566F696C6965725C70726F6A65745F766F696C6965725C4B65696C5F456C6973655F59757765695C4C6F63616C5F536F75726365735C626F72646167655C496E636C7564655C4D7954696D65722E6800000000094D7954696D65722E6800000000F0A0A100FFFFFFFF63553A5C3449525C53544D33325C50726F6A65745F566F696C6965725C70726F6A65745F766F696C6965725C4B65696C5F456C6973655F59757765695C4C6F63616C5F536F75726365735C626F72646167655C496E636C7564655C4D7954696D65722E63000000000A4D7954696D65722E632A00000000BCA8E100FFFFFFFF67553A5C3449525C53544D33325C50726F6A65745F566F696C6965725C70726F6A65745F766F696C6965725C4B65696C5F456C6973655F59757765695C4C6F63616C5F536F75726365735C626F72646167655C496E636C7564655C4472697665725F4750494F2E68000000000D4472697665725F4750494F2E68000000009CC1B600FFFFFFFF67553A5C3449525C53544D33325C50726F6A65745F566F696C6965725C70726F6A65745F766F696C6965725C4B65696C5F456C6973655F59757765695C4C6F63616C5F536F75726365735C626F72646167655C496E636C7564655C4472697665725F4750494F2E63000000000D4472697665725F4750494F2E6300000000F7B88600FFFFFFFF62553A5C3449525C53544D33325C50726F6A65745F566F696C6965725C70726F6A65745F766F696C6965725C4B65696C5F456C6973655F59757765695C4C6F63616C5F536F75726365735C626F72646167655C536F757263655C626F72646167652E630000000009626F72646167652E6300000000B3A6BE00FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000040100006600000000080000C6020000
+
+
+
+ 0
+ Build
+
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 040100004F000000F0050000E9000000
+
+
+ 16
+ DC0100003E010000C8060000D8010000
+
+
+
+ 1005
+ 1005
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000096020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 109
+ 109
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000096020000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 1465
+ 1465
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1466
+ 1466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1467
+ 1467
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1468
+ 1468
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1506
+ 1506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 1913
+ 1913
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000ED050000D0000000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1935
+ 1935
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 1936
+ 1936
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 1937
+ 1937
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 1939
+ 1939
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1940
+ 1940
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1941
+ 1941
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1942
+ 1942
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 195
+ 195
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000096020000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 196
+ 196
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000096020000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 197
+ 197
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 03000000CA020000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 198
+ 198
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 0000000041020000F0050000EF020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 199
+ 199
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000CA020000FD07000034030000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 203
+ 203
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 8192
+ 0
+
+ 16
+ 0701000066000000ED050000D0000000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 204
+ 204
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000ED050000D0000000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 221
+ 221
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 00000000000000000000000000000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 2506
+ 2506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 2507
+ 2507
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 343
+ 343
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000ED050000D0000000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 346
+ 346
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000ED050000D0000000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 35141
+ 35141
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000ED050000D0000000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35824
+ 35824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000ED050000D0000000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 35885
+ 35885
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35886
+ 35886
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35887
+ 35887
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35888
+ 35888
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35889
+ 35889
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35890
+ 35890
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35891
+ 35891
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35892
+ 35892
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35893
+ 35893
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35894
+ 35894
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35895
+ 35895
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35896
+ 35896
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35897
+ 35897
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35898
+ 35898
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35899
+ 35899
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35900
+ 35900
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35901
+ 35901
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35902
+ 35902
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35903
+ 35903
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35904
+ 35904
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35905
+ 35905
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 38003
+ 38003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000077030000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 38007
+ 38007
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000CA020000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 436
+ 436
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000CA020000FD07000034030000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 437
+ 437
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 440
+ 440
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 463
+ 463
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000CA020000FD07000034030000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 466
+ 466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000CA020000FD07000034030000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 470
+ 470
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000ED050000D0000000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 50000
+ 50000
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50001
+ 50001
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50002
+ 50002
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50003
+ 50003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50004
+ 50004
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50005
+ 50005
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50006
+ 50006
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50007
+ 50007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50008
+ 50008
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50009
+ 50009
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50010
+ 50010
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50011
+ 50011
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50012
+ 50012
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50013
+ 50013
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50014
+ 50014
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50015
+ 50015
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50016
+ 50016
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50017
+ 50017
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50018
+ 50018
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50019
+ 50019
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F304000066000000ED05000038020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 59392
+ 59392
+ 1
+ 0
+ 0
+ 0
+ 966
+ 0
+ 8192
+ 0
+
+ 16
+ 0000000000000000D10300001C000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59393
+ 0
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 000000002E0400000008000041040000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59399
+ 59399
+ 1
+ 0
+ 0
+ 0
+ 476
+ 0
+ 8192
+ 1
+
+ 16
+ 000000001C000000E701000038000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59400
+ 59400
+ 0
+ 0
+ 0
+ 0
+ 612
+ 0
+ 8192
+ 2
+
+ 16
+ 00000000380000006F02000054000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 824
+ 824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000058020000ED050000D6020000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 3312
+ 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFF04010000E9000000F0050000ED000000000000000100000004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000000000000DC0100003E010000C8060000D8010000040100004F000000F0050000E90000000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFFEC0400004F000000F004000051020000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000C80500003E010000C806000040030000F00400004F000000F00500005102000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFF000100004F00000004010000AF020000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C40000007394000001800010000001000000D80000003E010000D80100007F040000000000004F00000000010000AF0200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF000000003D020000F00500004102000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800080000000000000D800000030030000C8060000DE0300000000000041020000F0050000EF02000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFFF802000041020000FC020000EF02000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF00000000AF02000000080000B302000001000000010000100400000001000000C4FCFFFF98000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000001000000D800000083040000D80800001D05000000000000B3020000000800002E0400000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572010000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000
+
+
+ 59392
+ File
+
+ 2537
+ 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000002000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000096000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000
+
+
+
+ 59399
+ Build
+
+ 979
+ 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000000000000100000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050010000000452E9656C960000000000000002000653696D756CE90452E9656C00000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000
+
+
+
+ 59400
+ Debug
+
+ 2373
+ 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000
+
+
+
+ 0
+ 2048
+ 1152
+
+
+
+ 1
+ Debug
+
+ -1
+ -1
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 040100004F000000FC06000062010000
+
+
+ 16
+ 0401000066000000FC06000079010000
+
+
+
+ 1005
+ 1005
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 109
+ 109
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000063030000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 1465
+ 1465
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1466
+ 1466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1467
+ 1467
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1468
+ 1468
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1506
+ 1506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 1913
+ 1913
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000F906000049010000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1935
+ 1935
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 1936
+ 1936
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 1937
+ 1937
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 1939
+ 1939
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1940
+ 1940
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1941
+ 1941
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 1942
+ 1942
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 195
+ 195
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000063030000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 196
+ 196
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000063030000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 197
+ 197
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 030000006C020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 198
+ 198
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 0000000080030000000400002E040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 199
+ 199
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006C020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 203
+ 203
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 8192
+ 0
+
+ 16
+ 0701000066000000F906000049010000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 204
+ 204
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000F906000049010000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 221
+ 221
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 00000000000000000000000000000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 2506
+ 2506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 2507
+ 2507
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 343
+ 343
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000F906000049010000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 346
+ 346
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000F906000049010000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 35141
+ 35141
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000F906000049010000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35824
+ 35824
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000F906000049010000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 35885
+ 35885
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35886
+ 35886
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35887
+ 35887
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35888
+ 35888
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35889
+ 35889
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35890
+ 35890
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35891
+ 35891
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35892
+ 35892
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35893
+ 35893
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35894
+ 35894
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35895
+ 35895
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35896
+ 35896
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35897
+ 35897
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35898
+ 35898
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35899
+ 35899
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35900
+ 35900
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35901
+ 35901
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35902
+ 35902
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35903
+ 35903
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35904
+ 35904
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 35905
+ 35905
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0007000063000000000800007C030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 38003
+ 38003
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000FD00000063030000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 38007
+ 38007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006C020000ED050000D6020000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 436
+ 436
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006C020000ED050000D6020000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 437
+ 437
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 440
+ 440
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 463
+ 463
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006C020000ED050000D6020000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 466
+ 466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006C020000ED050000D6020000
+
+
+ 16
+ 0C010000230100003C0200008B030000
+
+
+
+ 470
+ 470
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0701000066000000F906000049010000
+
+
+ 16
+ 0C0100002301000004040000BD010000
+
+
+
+ 50000
+ 50000
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50001
+ 50001
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50002
+ 50002
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50003
+ 50003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50004
+ 50004
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50005
+ 50005
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50006
+ 50006
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50007
+ 50007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50008
+ 50008
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50009
+ 50009
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50010
+ 50010
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50011
+ 50011
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50012
+ 50012
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50013
+ 50013
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50014
+ 50014
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50015
+ 50015
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50016
+ 50016
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50017
+ 50017
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50018
+ 50018
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 50019
+ 50019
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 0307000066000000FD07000063030000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 59392
+ 59392
+ 1
+ 0
+ 0
+ 0
+ 966
+ 0
+ 8192
+ 0
+
+ 16
+ 0000000000000000D10300001C000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59393
+ 0
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 000000002E0400000008000041040000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59399
+ 59399
+ 0
+ 0
+ 0
+ 0
+ 476
+ 0
+ 8192
+ 1
+
+ 16
+ 000000001C000000E701000038000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59400
+ 59400
+ 1
+ 0
+ 0
+ 0
+ 612
+ 0
+ 8192
+ 2
+
+ 16
+ 000000001C0000006F02000038000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 824
+ 824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0704000097030000FD07000015040000
+
+
+ 16
+ 0C010000230100000C020000FC010000
+
+
+
+ 3333
+ 000000000B000000000000000020000001000000FFFFFFFFFFFFFFFF0401000062010000FC060000660100000100000001000010040000000100000068FFFFFFBA020000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E6500200000010000000401000066000000FC06000079010000040100004F000000FC060000620100000000000040280056080000000B446973617373656D626C7901000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657201000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFF03000000000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000001000000FFFFFFFFFFFFFFFFFC0600004F000000000700007C030000010000000200001004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C300000180004000000100000000070000660000000008000093030000000700004F000000000800007C03000000000000404100562B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF054750494F42000000003D8C000001000000FFFFFFFFFFFFFFFF054750494F41000000003E8C000001000000FFFFFFFFFFFFFFFF0441444331000000003F8C000001000000FFFFFFFFFFFFFFFF0454494D3300000000408C000001000000FFFFFFFFFFFFFFFF0454494D3201000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFF16000000000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFF000100004F000000040100007C030000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C4000000739400000180001000000100000000000000660000000001000093030000000000004F000000000100007C0300000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73000000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7300000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657300000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273010000007394000001000000FFFFFFFFFFFFFFFF04000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000001000000FFFFFFFFFFFFFFFF000000007C030000000800008003000001000000010000100400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800080000001000000040400009703000000080000450400000404000080030000000800002E04000000000000404100560F0000001343616C6C20537461636B202B204C6F63616C73010000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203101000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFF000000000000000001000000000000000100000001000000FFFFFFFF0004000080030000040400002E04000001000000020000100400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000000000000FFFFFFFFFFFFFFFF0000000051020000F005000055020000000000000100000004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000000000000000000006C020000F0050000060300000000000055020000F0050000EF0200000000000040820046060000000C4275696C64204F757470757400000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0642726F777365000000007794000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000
+
+
+ 59392
+ File
+
+ 2537
+ 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000096000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000300150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000
+
+
+
+ 59399
+ Build
+
+ 955
+ 00200000000000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0000000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000000002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050FFFFFFFF00960000000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000000240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000
+
+
+
+ 59400
+ Debug
+
+ 2362
+ 00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020001002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720000000000000000010000000000000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000002000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7200000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720000000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720000000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730000000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72000000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000
+
+
+
+ 0
+ 2048
+ 1152
+
+
+
+
+
+ 1
+ 0
+
+ 100
+ 2
+
+ .\Source\principal.c
+ 1
+ 5
+ 52
+ 1
+
+ 0
+
+
+ .\Include\MyTimer.h
+ 40
+ 1
+ 19
+ 0
+
+ 0
+
+
+ .\Include\MyTimer.c
+ 51
+ 81
+ 111
+ 0
+
+ 0
+
+
+ .\Include\Driver_GPIO.h
+ 15
+ 1
+ 15
+ 1
+
+ 0
+
+
+ .\Include\Driver_GPIO.c
+ 0
+ 1
+ 14
+ 1
+
+ 0
+
+
+ .\Source\bordage.c
+ 2
+ 1
+ 32
+ 0
+
+ 0
+
+
+
+
+
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvoptx b/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvoptx
new file mode 100644
index 0000000..2c6d6a9
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvoptx
@@ -0,0 +1,548 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc; *.md
+ *.plm
+ *.cpp; *.cc; *.cxx
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ Simulé
+ 0x4
+ ARM-ADS
+
+ 8000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\Listings\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 0
+
+ 18
+
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 6
+
+
+
+
+
+
+
+
+
+
+ STLink\ST-LINKIII-KEIL_SWO.dll
+
+
+
+ 0
+ DLGDARM
+ (1010=988,106,1364,663,0)(1007=-1,-1,-1,-1,0)(1008=90,121,466,357,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1175,390,1596,817,1)(121=540,360,961,787,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=120,153,405,449,0)(130=-1,-1,-1,-1,0)(131=770,0,1364,751,0)(132=150,186,744,937,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=1176,373,1779,1124,0)(151=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMRTXEVENTFLAGS
+ -L70 -Z18 -C0 -M0 -T1
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+ -T0
+
+
+ 0
+ DLGUARM
+ (105=-1,-1,-1,-1,0)
+
+
+ 0
+ ST-LINKIII-KEIL_SWO
+ -U0672FF524951775087241345 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+ 0
+ ((porta & 0x00000040) >> 6 & 0x40) >> 6
+ 00800000000000000000000000000000E0FFEF400100000000000000000000000000000028706F7274612026203078303030303030343029203E3E2036000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F0A0000000000000000000000000000000000000050050008
+
+
+
+
+ System Viewer\GPIOA
+ 35902
+
+
+ System Viewer\GPIOB
+ 35901
+
+
+ System Viewer\TIM2
+ 35905
+
+
+ System Viewer\TIM3
+ 35904
+
+
+
+ 1
+ 0
+ 0
+ 2
+ 10000000
+
+
+
+
+
+ Réel
+ 0x4
+ ARM-ADS
+
+ 8000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\Listings\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 18
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 6
+
+
+
+
+
+
+
+
+
+
+ STLink\ST-LINKIII-KEIL_SWO.dll
+
+
+
+ 0
+ ARMRTXEVENTFLAGS
+ -L70 -Z18 -C0 -M0 -T1
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=105,137,292,412,0)(1008=393,252,769,488,0)(1009=-1,-1,-1,-1,0)(100=692,179,1338,852,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1049,222,1470,627,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=105,137,504,482,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=655,170,1249,864,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=240,283,843,917,0)(151=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+ (105=-1,-1,-1,-1,0)
+
+
+ 0
+ ST-LINKIII-KEIL_SWO
+ -U0672FF524951775087241345 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+ System Viewer\TIM2
+ 35905
+
+
+
+ 1
+ 0
+ 0
+ 2
+ 10000000
+
+
+
+
+
+ MesSources
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+ .\Source\principal.c
+ principal.c
+ 0
+ 0
+
+
+ 1
+ 2
+ 1
+ 0
+ 0
+ 0
+ .\Source\bordage.c
+ bordage.c
+ 0
+ 0
+
+
+
+
+ MesDrivers
+ 1
+ 0
+ 0
+ 0
+
+ 2
+ 3
+ 1
+ 0
+ 0
+ 0
+ .\Include\Driver_GPIO.c
+ Driver_GPIO.c
+ 0
+ 0
+
+
+ 2
+ 4
+ 5
+ 0
+ 0
+ 0
+ .\Include\Driver_GPIO.h
+ Driver_GPIO.h
+ 0
+ 0
+
+
+ 2
+ 5
+ 1
+ 0
+ 0
+ 0
+ .\Include\MyTimer.c
+ MyTimer.c
+ 0
+ 0
+
+
+ 2
+ 6
+ 5
+ 0
+ 0
+ 0
+ .\Include\MyTimer.h
+ MyTimer.h
+ 0
+ 0
+
+
+ 2
+ 7
+ 1
+ 0
+ 0
+ 0
+ .\Include\MyADC.c
+ MyADC.c
+ 0
+ 0
+
+
+ 2
+ 8
+ 5
+ 0
+ 0
+ 0
+ .\Include\MyADC.h
+ MyADC.h
+ 0
+ 0
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
+ ::Device
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvprojx b/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvprojx
new file mode 100644
index 0000000..c57690d
--- /dev/null
+++ b/Keil_Elise_Yuwei/Local_Sources/bordage/drivers.uvprojx
@@ -0,0 +1,933 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Simulé
+ 0x4
+ ARM-ADS
+ 5060960::V5.06 update 7 (build 960)::.\ARMCC
+ 0
+
+
+ STM32F103RB
+ STMicroelectronics
+ Keil.STM32F1xx_DFP.2.3.0
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))
+ 4231
+ $$Device:STM32F103RB$Device\Include\stm32f10x.h
+
+
+
+
+
+
+
+
+
+ $$Device:STM32F103RB$SVD\STM32F103xx.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Objects\
+ drivers_simule
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\Listings\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DARMSTM.DLL
+ -pSTM32F103RB
+ SARMCM3.DLL
+
+ TARMSTM.DLL
+ -pSTM32F103RB
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ -1
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 8
+ 1
+ 0
+ 0
+ 0
+ 3
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x5000
+
+
+ 1
+ 0x8000000
+ 0x20000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x8000000
+ 0x20000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x5000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+ .\Include
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ MesSources
+
+
+ principal.c
+ 1
+ .\Source\principal.c
+
+
+ bordage.c
+ 1
+ .\Source\bordage.c
+
+
+
+
+ MesDrivers
+
+
+ Driver_GPIO.c
+ 1
+ .\Include\Driver_GPIO.c
+
+
+ Driver_GPIO.h
+ 5
+ .\Include\Driver_GPIO.h
+
+
+ MyTimer.c
+ 1
+ .\Include\MyTimer.c
+
+
+ MyTimer.h
+ 5
+ .\Include\MyTimer.h
+
+
+ MyADC.c
+ 1
+ .\Include\MyADC.c
+
+
+ MyADC.h
+ 5
+ .\Include\MyADC.h
+
+
+
+
+ ::CMSIS
+
+
+ ::Device
+
+
+
+
+ Réel
+ 0x4
+ ARM-ADS
+ 5060960::V5.06 update 7 (build 960)::.\ARMCC
+ 0
+
+
+ STM32F103RB
+ STMicroelectronics
+ Keil.STM32F1xx_DFP.2.3.0
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))
+ 4231
+ $$Device:STM32F103RB$Device\Include\stm32f10x.h
+
+
+
+
+
+
+
+
+
+ $$Device:STM32F103RB$SVD\STM32F103xx.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Objects\
+ drivers_simule
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\Listings\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DARMSTM.DLL
+ -pSTM32F103RB
+ SARMCM3.DLL
+
+ TARMSTM.DLL
+ -pSTM32F103RB
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ -1
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 8
+ 1
+ 0
+ 0
+ 0
+ 3
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x5000
+
+
+ 1
+ 0x8000000
+ 0x20000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x8000000
+ 0x20000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x5000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+ .\Include
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ MesSources
+
+
+ principal.c
+ 1
+ .\Source\principal.c
+
+
+ bordage.c
+ 1
+ .\Source\bordage.c
+
+
+
+
+ MesDrivers
+
+
+ Driver_GPIO.c
+ 1
+ .\Include\Driver_GPIO.c
+
+
+ Driver_GPIO.h
+ 5
+ .\Include\Driver_GPIO.h
+
+
+ MyTimer.c
+ 1
+ .\Include\MyTimer.c
+
+
+ MyTimer.h
+ 5
+ .\Include\MyTimer.h
+
+
+ MyADC.c
+ 1
+ .\Include\MyADC.c
+
+
+ MyADC.h
+ 5
+ .\Include\MyADC.h
+
+
+
+
+ ::CMSIS
+
+
+ ::Device
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ RTE\Device\STM32F103RB\RTE_Device.h
+
+
+
+
+
+
+
+
+ RTE\Device\STM32F103RB\startup_stm32f10x_md.s
+
+
+
+
+
+
+
+
+ RTE\Device\STM32F103RB\system_stm32f10x.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+ drivers
+ 1
+
+
+
+
+