diff --git a/bateau-microcontrolleur/Listings/hello_world.map b/bateau-microcontrolleur/Listings/hello_world.map
deleted file mode 100644
index ad33d7a..0000000
--- a/bateau-microcontrolleur/Listings/hello_world.map
+++ /dev/null
@@ -1,306 +0,0 @@
-Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]
-
-==============================================================================
-
-Section Cross References
-
- startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler
- startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
- startup_stm32f10x_md.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
- system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72
- system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock
- system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000F) for __rt_final_cpp
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$00000011) for __rt_final_exit
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry12b.o(.ARM.Collect$$$$0000000E) for __rt_lib_shutdown_fini
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
- entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
- entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
- entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
- entry9a.o(.ARM.Collect$$$$0000000B) refers to principal.o(i.main) for main
- entry9b.o(.ARM.Collect$$$$0000000C) refers to principal.o(i.main) for main
- init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
-
-
-==============================================================================
-
-Removing Unused input sections from the image.
-
- Removing principal.o(.rev16_text), (4 bytes).
- Removing principal.o(.revsh_text), (4 bytes).
- Removing principal.o(.rrx_text), (6 bytes).
- Removing startup_stm32f10x_md.o(HEAP), (512 bytes).
- Removing system_stm32f10x.o(.rev16_text), (4 bytes).
- Removing system_stm32f10x.o(.revsh_text), (4 bytes).
- Removing system_stm32f10x.o(.rrx_text), (6 bytes).
- Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes).
- Removing system_stm32f10x.o(.data), (20 bytes).
-
-9 unused section(s) (total 724 bytes) removed from the image.
-
-==============================================================================
-
-Image Symbol Table
-
- Local Symbols
-
- Symbol Name Value Ov Type Size Object(Section)
-
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE
- RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE
- RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE
- RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE
- Source\\principal.c 0x00000000 Number 0 principal.o ABSOLUTE
- Source\principal.c 0x00000000 Number 0 principal.o ABSOLUTE
- dc.s 0x00000000 Number 0 dc.o ABSOLUTE
- handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE
- init.s 0x00000000 Number 0 init.o ABSOLUTE
- RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET)
- .ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000)
- .ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001)
- .ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004)
- .ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008)
- .ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A)
- .ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B)
- .ARM.Collect$$$$0000000E 0x080000fc Section 4 entry12b.o(.ARM.Collect$$$$0000000E)
- .ARM.Collect$$$$0000000F 0x08000100 Section 0 entry10a.o(.ARM.Collect$$$$0000000F)
- .ARM.Collect$$$$00000011 0x08000100 Section 0 entry11a.o(.ARM.Collect$$$$00000011)
- .ARM.Collect$$$$00002712 0x08000100 Section 4 entry2.o(.ARM.Collect$$$$00002712)
- __lit__00000000 0x08000100 Data 4 entry2.o(.ARM.Collect$$$$00002712)
- .text 0x08000104 Section 36 startup_stm32f10x_md.o(.text)
- .text 0x08000128 Section 36 init.o(.text)
- i.SetSysClock 0x0800014c Section 0 system_stm32f10x.o(i.SetSysClock)
- SetSysClock 0x0800014d Thumb Code 8 system_stm32f10x.o(i.SetSysClock)
- i.SetSysClockTo72 0x08000154 Section 0 system_stm32f10x.o(i.SetSysClockTo72)
- SetSysClockTo72 0x08000155 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72)
- i.SystemInit 0x08000234 Section 0 system_stm32f10x.o(i.SystemInit)
- i.__scatterload_copy 0x08000294 Section 14 handlers.o(i.__scatterload_copy)
- i.__scatterload_null 0x080002a2 Section 2 handlers.o(i.__scatterload_null)
- i.__scatterload_zeroinit 0x080002a4 Section 14 handlers.o(i.__scatterload_zeroinit)
- i.main 0x080002b4 Section 0 principal.o(i.main)
- STACK 0x20000000 Section 1024 startup_stm32f10x_md.o(STACK)
-
- Global Symbols
-
- Symbol Name Value Ov Type Size Object(Section)
-
- BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
- __ARM_use_no_argv 0x00000000 Number 0 principal.o ABSOLUTE
- __arm_fini_ - Undefined Weak Reference
- __cpp_initialize__aeabi_ - Undefined Weak Reference
- __cxa_finalize - Undefined Weak Reference
- __decompress - Undefined Weak Reference
- _clock_init - Undefined Weak Reference
- _microlib_exit - Undefined Weak Reference
- __Vectors_Size 0x000000ec Number 0 startup_stm32f10x_md.o ABSOLUTE
- __Vectors 0x08000000 Data 4 startup_stm32f10x_md.o(RESET)
- __Vectors_End 0x080000ec Data 0 startup_stm32f10x_md.o(RESET)
- __main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000)
- _main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001)
- _main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
- __main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
- _main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008)
- _main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A)
- _main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B)
- __rt_lib_shutdown_fini 0x080000fd Thumb Code 0 entry12b.o(.ARM.Collect$$$$0000000E)
- __rt_final_cpp 0x08000101 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000F)
- __rt_final_exit 0x08000101 Thumb Code 0 entry11a.o(.ARM.Collect$$$$00000011)
- Reset_Handler 0x08000105 Thumb Code 8 startup_stm32f10x_md.o(.text)
- NMI_Handler 0x0800010d Thumb Code 2 startup_stm32f10x_md.o(.text)
- HardFault_Handler 0x0800010f Thumb Code 2 startup_stm32f10x_md.o(.text)
- MemManage_Handler 0x08000111 Thumb Code 2 startup_stm32f10x_md.o(.text)
- BusFault_Handler 0x08000113 Thumb Code 2 startup_stm32f10x_md.o(.text)
- UsageFault_Handler 0x08000115 Thumb Code 2 startup_stm32f10x_md.o(.text)
- SVC_Handler 0x08000117 Thumb Code 2 startup_stm32f10x_md.o(.text)
- DebugMon_Handler 0x08000119 Thumb Code 2 startup_stm32f10x_md.o(.text)
- PendSV_Handler 0x0800011b Thumb Code 2 startup_stm32f10x_md.o(.text)
- SysTick_Handler 0x0800011d Thumb Code 2 startup_stm32f10x_md.o(.text)
- ADC1_2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- CAN1_RX1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- CAN1_SCE_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel6_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel7_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI15_10_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI9_5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- FLASH_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C1_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C1_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C2_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C2_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- PVD_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RCC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RTCAlarm_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RTC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- SPI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- SPI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TAMPER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_BRK_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_CC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_TRG_COM_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_UP_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USBWakeUp_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USB_HP_CAN1_TX_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USB_LP_CAN1_RX0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- WWDG_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- __scatterload 0x08000129 Thumb Code 28 init.o(.text)
- __scatterload_rt2 0x08000129 Thumb Code 0 init.o(.text)
- SystemInit 0x08000235 Thumb Code 78 system_stm32f10x.o(i.SystemInit)
- __scatterload_copy 0x08000295 Thumb Code 14 handlers.o(i.__scatterload_copy)
- __scatterload_null 0x080002a3 Thumb Code 2 handlers.o(i.__scatterload_null)
- __scatterload_zeroinit 0x080002a5 Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
- main 0x080002b5 Thumb Code 82 principal.o(i.main)
- Region$$Table$$Base 0x08000314 Number 0 anon$$obj.o(Region$$Table)
- Region$$Table$$Limit 0x08000324 Number 0 anon$$obj.o(Region$$Table)
- __initial_sp 0x20000400 Data 0 startup_stm32f10x_md.o(STACK)
-
-
-
-==============================================================================
-
-Memory Map of the image
-
- Image Entry point : 0x08000105
-
- Load Region LR_1 (Base: 0x08000000, Size: 0x00000324, Max: 0xffffffff, ABSOLUTE)
-
- Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000324, Max: 0xffffffff, ABSOLUTE)
-
- Exec Addr Load Addr Size Type Attr Idx E Section Name Object
-
- 0x08000000 0x08000000 0x000000ec Data RO 56 RESET startup_stm32f10x_md.o
- 0x080000ec 0x080000ec 0x00000000 Code RO 107 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
- 0x080000ec 0x080000ec 0x00000004 Code RO 110 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
- 0x080000f0 0x080000f0 0x00000004 Code RO 113 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
- 0x080000f4 0x080000f4 0x00000000 Code RO 115 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
- 0x080000f4 0x080000f4 0x00000000 Code RO 117 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
- 0x080000f4 0x080000f4 0x00000008 Code RO 118 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
- 0x080000fc 0x080000fc 0x00000004 Code RO 125 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o)
- 0x08000100 0x08000100 0x00000000 Code RO 120 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o)
- 0x08000100 0x08000100 0x00000000 Code RO 122 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o)
- 0x08000100 0x08000100 0x00000004 Code RO 111 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
- 0x08000104 0x08000104 0x00000024 Code RO 57 * .text startup_stm32f10x_md.o
- 0x08000128 0x08000128 0x00000024 Code RO 126 .text mc_w.l(init.o)
- 0x0800014c 0x0800014c 0x00000008 Code RO 64 i.SetSysClock system_stm32f10x.o
- 0x08000154 0x08000154 0x000000e0 Code RO 65 i.SetSysClockTo72 system_stm32f10x.o
- 0x08000234 0x08000234 0x00000060 Code RO 67 i.SystemInit system_stm32f10x.o
- 0x08000294 0x08000294 0x0000000e Code RO 130 i.__scatterload_copy mc_w.l(handlers.o)
- 0x080002a2 0x080002a2 0x00000002 Code RO 131 i.__scatterload_null mc_w.l(handlers.o)
- 0x080002a4 0x080002a4 0x0000000e Code RO 132 i.__scatterload_zeroinit mc_w.l(handlers.o)
- 0x080002b2 0x080002b2 0x00000002 PAD
- 0x080002b4 0x080002b4 0x00000060 Code RO 4 i.main principal.o
- 0x08000314 0x08000314 0x00000010 Data RO 128 Region$$Table anon$$obj.o
-
-
- Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000324, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE)
-
- **** No section assigned to this execution region ****
-
-
- Execution Region ER_ZI (Exec base: 0x20000000, Load base: 0x08000324, Size: 0x00000400, Max: 0xffffffff, ABSOLUTE)
-
- Exec Addr Load Addr Size Type Attr Idx E Section Name Object
-
- 0x20000000 - 0x00000400 Zero RW 54 STACK startup_stm32f10x_md.o
-
-
-==============================================================================
-
-Image component sizes
-
-
- Code (inc. data) RO Data RW Data ZI Data Debug Object Name
-
- 96 14 0 0 0 5039 principal.o
- 36 8 236 0 1024 872 startup_stm32f10x_md.o
- 328 28 0 0 0 2229 system_stm32f10x.o
-
- ----------------------------------------------------------------------
- 460 50 252 0 1024 8140 Object Totals
- 0 0 16 0 0 0 (incl. Generated)
- 0 0 0 0 0 0 (incl. Padding)
-
- ----------------------------------------------------------------------
-
- Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
-
- 0 0 0 0 0 0 entry.o
- 0 0 0 0 0 0 entry10a.o
- 0 0 0 0 0 0 entry11a.o
- 4 0 0 0 0 0 entry12b.o
- 8 4 0 0 0 0 entry2.o
- 4 0 0 0 0 0 entry5.o
- 0 0 0 0 0 0 entry7b.o
- 0 0 0 0 0 0 entry8b.o
- 8 4 0 0 0 0 entry9a.o
- 30 0 0 0 0 0 handlers.o
- 36 8 0 0 0 68 init.o
-
- ----------------------------------------------------------------------
- 92 16 0 0 0 68 Library Totals
- 2 0 0 0 0 0 (incl. Padding)
-
- ----------------------------------------------------------------------
-
- Code (inc. data) RO Data RW Data ZI Data Debug Library Name
-
- 90 16 0 0 0 68 mc_w.l
-
- ----------------------------------------------------------------------
- 92 16 0 0 0 68 Library Totals
-
- ----------------------------------------------------------------------
-
-==============================================================================
-
-
- Code (inc. data) RO Data RW Data ZI Data Debug
-
- 552 66 252 0 1024 8256 Grand Totals
- 552 66 252 0 1024 8256 ELF Image Totals
- 552 66 252 0 0 0 ROM Totals
-
-==============================================================================
-
- Total RO Size (Code + RO Data) 804 ( 0.79kB)
- Total RW Size (RW Data + ZI Data) 1024 ( 1.00kB)
- Total ROM Size (Code + RO Data + RW Data) 804 ( 0.79kB)
-
-==============================================================================
-
diff --git a/bateau-microcontrolleur/Listings/startup_stm32f10x_md.lst b/bateau-microcontrolleur/Listings/startup_stm32f10x_md.lst
deleted file mode 100644
index 9bfae77..0000000
--- a/bateau-microcontrolleur/Listings/startup_stm32f10x_md.lst
+++ /dev/null
@@ -1,1181 +0,0 @@
-
-
-
-ARM Macro Assembler Page 1
-
-
- 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron
- ics ********************
- 2 00000000 ;* File Name : startup_stm32f10x_md.s
- 3 00000000 ;* Author : MCD Application Team
- 4 00000000 ;* Version : V3.5.0
- 5 00000000 ;* Date : 11-March-2011
- 6 00000000 ;* Description : STM32F10x Medium Density Devices
- vector table for MDK-ARM
- 7 00000000 ;* toolchain.
- 8 00000000 ;* This module performs:
- 9 00000000 ;* - Set the initial SP
- 10 00000000 ;* - Set the initial PC == Reset_Ha
- ndler
- 11 00000000 ;* - Set the vector table entries w
- ith the exceptions ISR address
- 12 00000000 ;* - Configure the clock system
- 13 00000000 ;* - Branches to __main in the C li
- brary (which eventually
- 14 00000000 ;* calls main()).
- 15 00000000 ;* After Reset the CortexM3 process
- or is in Thread mode,
- 16 00000000 ;* priority is Privileged, and the
- Stack is set to Main.
- 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
- 18 00000000 ;*******************************************************
- ************************
- 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A
- T PROVIDING CUSTOMERS
- 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR
- DER FOR THEM TO SAVE TIME.
- 21 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB
- LE FOR ANY DIRECT,
- 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
- CLAIMS ARISING FROM THE
- 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM
- ERS OF THE CODING
- 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR
- PRODUCTS.
- 25 00000000 ;*******************************************************
- ************************
- 26 00000000
- 27 00000000 ; Amount of memory (in bytes) allocated for Stack
- 28 00000000 ; Tailor this value to your application needs
- 29 00000000 ; Stack Configuration
- 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
- 31 00000000 ;
- 32 00000000
- 33 00000000 00000400
- Stack_Size
- EQU 0x00000400
- 34 00000000
- 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
-=3
- 36 00000000 Stack_Mem
- SPACE Stack_Size
- 37 00000400 __initial_sp
- 38 00000400
- 39 00000400
- 40 00000400 ; Heap Configuration
-
-
-
-ARM Macro Assembler Page 2
-
-
- 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
- 42 00000400 ;
- 43 00000400
- 44 00000400 00000200
- Heap_Size
- EQU 0x00000200
- 45 00000400
- 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
-3
- 47 00000000 __heap_base
- 48 00000000 Heap_Mem
- SPACE Heap_Size
- 49 00000200 __heap_limit
- 50 00000200
- 51 00000200 PRESERVE8
- 52 00000200 THUMB
- 53 00000200
- 54 00000200
- 55 00000200 ; Vector Table Mapped to Address 0 at Reset
- 56 00000200 AREA RESET, DATA, READONLY
- 57 00000000 EXPORT __Vectors
- 58 00000000 EXPORT __Vectors_End
- 59 00000000 EXPORT __Vectors_Size
- 60 00000000
- 61 00000000 00000000
- __Vectors
- DCD __initial_sp ; Top of Stack
- 62 00000004 00000000 DCD Reset_Handler ; Reset Handler
- 63 00000008 00000000 DCD NMI_Handler ; NMI Handler
- 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
- Handler
- 65 00000010 00000000 DCD MemManage_Handler
- ; MPU Fault Handler
-
- 66 00000014 00000000 DCD BusFault_Handler
- ; Bus Fault Handler
-
- 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul
- t Handler
- 68 0000001C 00000000 DCD 0 ; Reserved
- 69 00000020 00000000 DCD 0 ; Reserved
- 70 00000024 00000000 DCD 0 ; Reserved
- 71 00000028 00000000 DCD 0 ; Reserved
- 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
- 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito
- r Handler
- 74 00000034 00000000 DCD 0 ; Reserved
- 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
-
- 76 0000003C 00000000 DCD SysTick_Handler
- ; SysTick Handler
- 77 00000040
- 78 00000040 ; External Interrupts
- 79 00000040 00000000 DCD WWDG_IRQHandler
- ; Window Watchdog
- 80 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX
- TI Line detect
- 81 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper
- 82 0000004C 00000000 DCD RTC_IRQHandler ; RTC
-
-
-
-ARM Macro Assembler Page 3
-
-
- 83 00000050 00000000 DCD FLASH_IRQHandler ; Flash
- 84 00000054 00000000 DCD RCC_IRQHandler ; RCC
- 85 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0
- 86 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1
- 87 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2
- 88 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3
- 89 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4
- 90 0000006C 00000000 DCD DMA1_Channel1_IRQHandler
- ; DMA1 Channel 1
- 91 00000070 00000000 DCD DMA1_Channel2_IRQHandler
- ; DMA1 Channel 2
- 92 00000074 00000000 DCD DMA1_Channel3_IRQHandler
- ; DMA1 Channel 3
- 93 00000078 00000000 DCD DMA1_Channel4_IRQHandler
- ; DMA1 Channel 4
- 94 0000007C 00000000 DCD DMA1_Channel5_IRQHandler
- ; DMA1 Channel 5
- 95 00000080 00000000 DCD DMA1_Channel6_IRQHandler
- ; DMA1 Channel 6
- 96 00000084 00000000 DCD DMA1_Channel7_IRQHandler
- ; DMA1 Channel 7
- 97 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1_2
- 98 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB
- High Priority or C
- AN1 TX
- 99 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US
- B Low Priority or
- CAN1 RX0
- 100 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- 101 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- 102 0000009C 00000000 DCD EXTI9_5_IRQHandler
- ; EXTI Line 9..5
- 103 000000A0 00000000 DCD TIM1_BRK_IRQHandler
- ; TIM1 Break
- 104 000000A4 00000000 DCD TIM1_UP_IRQHandler
- ; TIM1 Update
- 105 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1
- Trigger and Commuta
- tion
- 106 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
- re Compare
- 107 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2
- 108 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3
- 109 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4
- 110 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event
-
- 111 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error
-
- 112 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event
-
- 113 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error
-
- 114 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1
- 115 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2
- 116 000000D4 00000000 DCD USART1_IRQHandler ; USART1
- 117 000000D8 00000000 DCD USART2_IRQHandler ; USART2
- 118 000000DC 00000000 DCD USART3_IRQHandler ; USART3
- 119 000000E0 00000000 DCD EXTI15_10_IRQHandler
- ; EXTI Line 15..10
-
-
-
-ARM Macro Assembler Page 4
-
-
- 120 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm
- through EXTI Line
- 121 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake
- up from suspend
- 122 000000EC __Vectors_End
- 123 000000EC
- 124 000000EC 000000EC
- __Vectors_Size
- EQU __Vectors_End - __Vectors
- 125 000000EC
- 126 000000EC AREA |.text|, CODE, READONLY
- 127 00000000
- 128 00000000 ; Reset handler
- 129 00000000 Reset_Handler
- PROC
- 130 00000000 EXPORT Reset_Handler [WEAK
-]
- 131 00000000 IMPORT __main
- 132 00000000 IMPORT SystemInit
- 133 00000000 4806 LDR R0, =SystemInit
- 134 00000002 4780 BLX R0
- 135 00000004 4806 LDR R0, =__main
- 136 00000006 4700 BX R0
- 137 00000008 ENDP
- 138 00000008
- 139 00000008 ; Dummy Exception Handlers (infinite loops which can be
- modified)
- 140 00000008
- 141 00000008 NMI_Handler
- PROC
- 142 00000008 EXPORT NMI_Handler [WEA
-K]
- 143 00000008 E7FE B .
- 144 0000000A ENDP
- 146 0000000A HardFault_Handler
- PROC
- 147 0000000A EXPORT HardFault_Handler [WEA
-K]
- 148 0000000A E7FE B .
- 149 0000000C ENDP
- 151 0000000C MemManage_Handler
- PROC
- 152 0000000C EXPORT MemManage_Handler [WEA
-K]
- 153 0000000C E7FE B .
- 154 0000000E ENDP
- 156 0000000E BusFault_Handler
- PROC
- 157 0000000E EXPORT BusFault_Handler [WEA
-K]
- 158 0000000E E7FE B .
- 159 00000010 ENDP
- 161 00000010 UsageFault_Handler
- PROC
- 162 00000010 EXPORT UsageFault_Handler [WEA
-K]
- 163 00000010 E7FE B .
- 164 00000012 ENDP
- 165 00000012 SVC_Handler
-
-
-
-ARM Macro Assembler Page 5
-
-
- PROC
- 166 00000012 EXPORT SVC_Handler [WEA
-K]
- 167 00000012 E7FE B .
- 168 00000014 ENDP
- 170 00000014 DebugMon_Handler
- PROC
- 171 00000014 EXPORT DebugMon_Handler [WEA
-K]
- 172 00000014 E7FE B .
- 173 00000016 ENDP
- 174 00000016 PendSV_Handler
- PROC
- 175 00000016 EXPORT PendSV_Handler [WEA
-K]
- 176 00000016 E7FE B .
- 177 00000018 ENDP
- 178 00000018 SysTick_Handler
- PROC
- 179 00000018 EXPORT SysTick_Handler [WEA
-K]
- 180 00000018 E7FE B .
- 181 0000001A ENDP
- 182 0000001A
- 183 0000001A Default_Handler
- PROC
- 184 0000001A
- 185 0000001A EXPORT WWDG_IRQHandler [WEA
-K]
- 186 0000001A EXPORT PVD_IRQHandler [WEA
-K]
- 187 0000001A EXPORT TAMPER_IRQHandler [WEA
-K]
- 188 0000001A EXPORT RTC_IRQHandler [WEA
-K]
- 189 0000001A EXPORT FLASH_IRQHandler [WEA
-K]
- 190 0000001A EXPORT RCC_IRQHandler [WEA
-K]
- 191 0000001A EXPORT EXTI0_IRQHandler [WEA
-K]
- 192 0000001A EXPORT EXTI1_IRQHandler [WEA
-K]
- 193 0000001A EXPORT EXTI2_IRQHandler [WEA
-K]
- 194 0000001A EXPORT EXTI3_IRQHandler [WEA
-K]
- 195 0000001A EXPORT EXTI4_IRQHandler [WEA
-K]
- 196 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA
-K]
- 197 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA
-K]
- 198 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA
-K]
- 199 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA
-K]
- 200 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA
-K]
-
-
-
-ARM Macro Assembler Page 6
-
-
- 201 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA
-K]
- 202 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA
-K]
- 203 0000001A EXPORT ADC1_2_IRQHandler [WEA
-K]
- 204 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA
-K]
- 205 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA
-K]
- 206 0000001A EXPORT CAN1_RX1_IRQHandler [WEA
-K]
- 207 0000001A EXPORT CAN1_SCE_IRQHandler [WEA
-K]
- 208 0000001A EXPORT EXTI9_5_IRQHandler [WEA
-K]
- 209 0000001A EXPORT TIM1_BRK_IRQHandler [WEA
-K]
- 210 0000001A EXPORT TIM1_UP_IRQHandler [WEA
-K]
- 211 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA
-K]
- 212 0000001A EXPORT TIM1_CC_IRQHandler [WEA
-K]
- 213 0000001A EXPORT TIM2_IRQHandler [WEA
-K]
- 214 0000001A EXPORT TIM3_IRQHandler [WEA
-K]
- 215 0000001A EXPORT TIM4_IRQHandler [WEA
-K]
- 216 0000001A EXPORT I2C1_EV_IRQHandler [WEA
-K]
- 217 0000001A EXPORT I2C1_ER_IRQHandler [WEA
-K]
- 218 0000001A EXPORT I2C2_EV_IRQHandler [WEA
-K]
- 219 0000001A EXPORT I2C2_ER_IRQHandler [WEA
-K]
- 220 0000001A EXPORT SPI1_IRQHandler [WEA
-K]
- 221 0000001A EXPORT SPI2_IRQHandler [WEA
-K]
- 222 0000001A EXPORT USART1_IRQHandler [WEA
-K]
- 223 0000001A EXPORT USART2_IRQHandler [WEA
-K]
- 224 0000001A EXPORT USART3_IRQHandler [WEA
-K]
- 225 0000001A EXPORT EXTI15_10_IRQHandler [WEA
-K]
- 226 0000001A EXPORT RTCAlarm_IRQHandler [WEA
-K]
- 227 0000001A EXPORT USBWakeUp_IRQHandler [WEA
-K]
- 228 0000001A
- 229 0000001A WWDG_IRQHandler
- 230 0000001A PVD_IRQHandler
- 231 0000001A TAMPER_IRQHandler
- 232 0000001A RTC_IRQHandler
-
-
-
-ARM Macro Assembler Page 7
-
-
- 233 0000001A FLASH_IRQHandler
- 234 0000001A RCC_IRQHandler
- 235 0000001A EXTI0_IRQHandler
- 236 0000001A EXTI1_IRQHandler
- 237 0000001A EXTI2_IRQHandler
- 238 0000001A EXTI3_IRQHandler
- 239 0000001A EXTI4_IRQHandler
- 240 0000001A DMA1_Channel1_IRQHandler
- 241 0000001A DMA1_Channel2_IRQHandler
- 242 0000001A DMA1_Channel3_IRQHandler
- 243 0000001A DMA1_Channel4_IRQHandler
- 244 0000001A DMA1_Channel5_IRQHandler
- 245 0000001A DMA1_Channel6_IRQHandler
- 246 0000001A DMA1_Channel7_IRQHandler
- 247 0000001A ADC1_2_IRQHandler
- 248 0000001A USB_HP_CAN1_TX_IRQHandler
- 249 0000001A USB_LP_CAN1_RX0_IRQHandler
- 250 0000001A CAN1_RX1_IRQHandler
- 251 0000001A CAN1_SCE_IRQHandler
- 252 0000001A EXTI9_5_IRQHandler
- 253 0000001A TIM1_BRK_IRQHandler
- 254 0000001A TIM1_UP_IRQHandler
- 255 0000001A TIM1_TRG_COM_IRQHandler
- 256 0000001A TIM1_CC_IRQHandler
- 257 0000001A TIM2_IRQHandler
- 258 0000001A TIM3_IRQHandler
- 259 0000001A TIM4_IRQHandler
- 260 0000001A I2C1_EV_IRQHandler
- 261 0000001A I2C1_ER_IRQHandler
- 262 0000001A I2C2_EV_IRQHandler
- 263 0000001A I2C2_ER_IRQHandler
- 264 0000001A SPI1_IRQHandler
- 265 0000001A SPI2_IRQHandler
- 266 0000001A USART1_IRQHandler
- 267 0000001A USART2_IRQHandler
- 268 0000001A USART3_IRQHandler
- 269 0000001A EXTI15_10_IRQHandler
- 270 0000001A RTCAlarm_IRQHandler
- 271 0000001A USBWakeUp_IRQHandler
- 272 0000001A
- 273 0000001A E7FE B .
- 274 0000001C
- 275 0000001C ENDP
- 276 0000001C
- 277 0000001C ALIGN
- 278 0000001C
- 279 0000001C ;*******************************************************
- ************************
- 280 0000001C ; User Stack and Heap initialization
- 281 0000001C ;*******************************************************
- ************************
- 282 0000001C IF :DEF:__MICROLIB
- 283 0000001C
- 284 0000001C EXPORT __initial_sp
- 285 0000001C EXPORT __heap_base
- 286 0000001C EXPORT __heap_limit
- 287 0000001C
- 288 0000001C ELSE
- 303 ENDIF
-
-
-
-ARM Macro Assembler Page 8
-
-
- 304 0000001C
- 305 0000001C END
- 00000000
- 00000000
-Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
-ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md.
-o -I.\RTE\Device\STM32F103RB -I.\RTE\_CarteSTM -IC:\Users\chauz\AppData\Local\A
-rm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Users\chauz\AppData\Local\Arm\
-Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --pre
-define="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 533" --predefine
-="_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --
-list=.\listings\startup_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32f1
-0x_md.s
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-STACK 00000000
-
-Symbol: STACK
- Definitions
- At line 35 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: STACK unused
-Stack_Mem 00000000
-
-Symbol: Stack_Mem
- Definitions
- At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Stack_Mem unused
-__initial_sp 00000400
-
-Symbol: __initial_sp
- Definitions
- At line 37 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 284 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-HEAP 00000000
-
-Symbol: HEAP
- Definitions
- At line 46 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: HEAP unused
-Heap_Mem 00000000
-
-Symbol: Heap_Mem
- Definitions
- At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Heap_Mem unused
-__heap_base 00000000
-
-Symbol: __heap_base
- Definitions
- At line 47 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 285 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __heap_base used once
-__heap_limit 00000200
-
-Symbol: __heap_limit
- Definitions
- At line 49 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 286 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __heap_limit used once
-4 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-RESET 00000000
-
-Symbol: RESET
- Definitions
- At line 56 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: RESET unused
-__Vectors 00000000
-
-Symbol: __Vectors
- Definitions
- At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 57 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-__Vectors_End 000000EC
-
-Symbol: __Vectors_End
- Definitions
- At line 122 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 58 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-.text 00000000
-
-Symbol: .text
- Definitions
- At line 126 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: .text unused
-ADC1_2_IRQHandler 0000001A
-
-Symbol: ADC1_2_IRQHandler
- Definitions
- At line 247 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 97 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 203 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-BusFault_Handler 0000000E
-
-Symbol: BusFault_Handler
- Definitions
- At line 156 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 66 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 157 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-CAN1_RX1_IRQHandler 0000001A
-
-Symbol: CAN1_RX1_IRQHandler
- Definitions
- At line 250 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 100 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 206 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-CAN1_SCE_IRQHandler 0000001A
-
-Symbol: CAN1_SCE_IRQHandler
- Definitions
- At line 251 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 101 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 207 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel1_IRQHandler 0000001A
-
-Symbol: DMA1_Channel1_IRQHandler
- Definitions
- At line 240 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 90 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 196 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel2_IRQHandler 0000001A
-
-Symbol: DMA1_Channel2_IRQHandler
- Definitions
- At line 241 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
-
-
-
-ARM Macro Assembler Page 2 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 91 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 197 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel3_IRQHandler 0000001A
-
-Symbol: DMA1_Channel3_IRQHandler
- Definitions
- At line 242 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 92 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 198 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel4_IRQHandler 0000001A
-
-Symbol: DMA1_Channel4_IRQHandler
- Definitions
- At line 243 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 93 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 199 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel5_IRQHandler 0000001A
-
-Symbol: DMA1_Channel5_IRQHandler
- Definitions
- At line 244 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 94 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 200 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel6_IRQHandler 0000001A
-
-Symbol: DMA1_Channel6_IRQHandler
- Definitions
- At line 245 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 95 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 201 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel7_IRQHandler 0000001A
-
-Symbol: DMA1_Channel7_IRQHandler
- Definitions
- At line 246 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 96 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 202 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DebugMon_Handler 00000014
-
-Symbol: DebugMon_Handler
- Definitions
- At line 170 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 73 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 171 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-Default_Handler 0000001A
-
-
-
-
-ARM Macro Assembler Page 3 Alphabetic symbol ordering
-Relocatable symbols
-
-Symbol: Default_Handler
- Definitions
- At line 183 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Default_Handler unused
-EXTI0_IRQHandler 0000001A
-
-Symbol: EXTI0_IRQHandler
- Definitions
- At line 235 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 85 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 191 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI15_10_IRQHandler 0000001A
-
-Symbol: EXTI15_10_IRQHandler
- Definitions
- At line 269 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 119 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 225 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI1_IRQHandler 0000001A
-
-Symbol: EXTI1_IRQHandler
- Definitions
- At line 236 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 86 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 192 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI2_IRQHandler 0000001A
-
-Symbol: EXTI2_IRQHandler
- Definitions
- At line 237 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 87 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 193 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI3_IRQHandler 0000001A
-
-Symbol: EXTI3_IRQHandler
- Definitions
- At line 238 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 88 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 194 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI4_IRQHandler 0000001A
-
-Symbol: EXTI4_IRQHandler
- Definitions
- At line 239 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 89 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 195 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler Page 4 Alphabetic symbol ordering
-Relocatable symbols
-
-
-EXTI9_5_IRQHandler 0000001A
-
-Symbol: EXTI9_5_IRQHandler
- Definitions
- At line 252 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 102 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 208 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-FLASH_IRQHandler 0000001A
-
-Symbol: FLASH_IRQHandler
- Definitions
- At line 233 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 83 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 189 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-HardFault_Handler 0000000A
-
-Symbol: HardFault_Handler
- Definitions
- At line 146 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 64 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 147 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C1_ER_IRQHandler 0000001A
-
-Symbol: I2C1_ER_IRQHandler
- Definitions
- At line 261 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 111 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 217 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C1_EV_IRQHandler 0000001A
-
-Symbol: I2C1_EV_IRQHandler
- Definitions
- At line 260 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 110 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 216 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C2_ER_IRQHandler 0000001A
-
-Symbol: I2C2_ER_IRQHandler
- Definitions
- At line 263 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 113 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 219 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C2_EV_IRQHandler 0000001A
-
-Symbol: I2C2_EV_IRQHandler
- Definitions
-
-
-
-ARM Macro Assembler Page 5 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 262 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 112 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 218 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-MemManage_Handler 0000000C
-
-Symbol: MemManage_Handler
- Definitions
- At line 151 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 65 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 152 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-NMI_Handler 00000008
-
-Symbol: NMI_Handler
- Definitions
- At line 141 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 63 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 142 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-PVD_IRQHandler 0000001A
-
-Symbol: PVD_IRQHandler
- Definitions
- At line 230 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 80 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 186 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-PendSV_Handler 00000016
-
-Symbol: PendSV_Handler
- Definitions
- At line 174 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 75 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 175 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-RCC_IRQHandler 0000001A
-
-Symbol: RCC_IRQHandler
- Definitions
- At line 234 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 84 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 190 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-RTCAlarm_IRQHandler 0000001A
-
-Symbol: RTCAlarm_IRQHandler
- Definitions
- At line 270 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 120 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 226 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-
-ARM Macro Assembler Page 6 Alphabetic symbol ordering
-Relocatable symbols
-
-RTC_IRQHandler 0000001A
-
-Symbol: RTC_IRQHandler
- Definitions
- At line 232 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 82 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 188 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-Reset_Handler 00000000
-
-Symbol: Reset_Handler
- Definitions
- At line 129 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 62 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 130 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SPI1_IRQHandler 0000001A
-
-Symbol: SPI1_IRQHandler
- Definitions
- At line 264 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 114 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 220 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SPI2_IRQHandler 0000001A
-
-Symbol: SPI2_IRQHandler
- Definitions
- At line 265 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 115 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 221 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SVC_Handler 00000012
-
-Symbol: SVC_Handler
- Definitions
- At line 165 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 72 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 166 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SysTick_Handler 00000018
-
-Symbol: SysTick_Handler
- Definitions
- At line 178 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 76 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 179 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TAMPER_IRQHandler 0000001A
-
-Symbol: TAMPER_IRQHandler
- Definitions
- At line 231 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler Page 7 Alphabetic symbol ordering
-Relocatable symbols
-
- Uses
- At line 81 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 187 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_BRK_IRQHandler 0000001A
-
-Symbol: TIM1_BRK_IRQHandler
- Definitions
- At line 253 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 103 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 209 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_CC_IRQHandler 0000001A
-
-Symbol: TIM1_CC_IRQHandler
- Definitions
- At line 256 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 106 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 212 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_TRG_COM_IRQHandler 0000001A
-
-Symbol: TIM1_TRG_COM_IRQHandler
- Definitions
- At line 255 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 105 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 211 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_UP_IRQHandler 0000001A
-
-Symbol: TIM1_UP_IRQHandler
- Definitions
- At line 254 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 104 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 210 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM2_IRQHandler 0000001A
-
-Symbol: TIM2_IRQHandler
- Definitions
- At line 257 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 107 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 213 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM3_IRQHandler 0000001A
-
-Symbol: TIM3_IRQHandler
- Definitions
- At line 258 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 108 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 214 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM4_IRQHandler 0000001A
-
-
-
-ARM Macro Assembler Page 8 Alphabetic symbol ordering
-Relocatable symbols
-
-
-Symbol: TIM4_IRQHandler
- Definitions
- At line 259 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 109 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 215 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART1_IRQHandler 0000001A
-
-Symbol: USART1_IRQHandler
- Definitions
- At line 266 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 116 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 222 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART2_IRQHandler 0000001A
-
-Symbol: USART2_IRQHandler
- Definitions
- At line 267 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 117 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 223 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART3_IRQHandler 0000001A
-
-Symbol: USART3_IRQHandler
- Definitions
- At line 268 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 118 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 224 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USBWakeUp_IRQHandler 0000001A
-
-Symbol: USBWakeUp_IRQHandler
- Definitions
- At line 271 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 121 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 227 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USB_HP_CAN1_TX_IRQHandler 0000001A
-
-Symbol: USB_HP_CAN1_TX_IRQHandler
- Definitions
- At line 248 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 98 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 204 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USB_LP_CAN1_RX0_IRQHandler 0000001A
-
-Symbol: USB_LP_CAN1_RX0_IRQHandler
- Definitions
- At line 249 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
-
-
-
-ARM Macro Assembler Page 9 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 99 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 205 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-UsageFault_Handler 00000010
-
-Symbol: UsageFault_Handler
- Definitions
- At line 161 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 67 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 162 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-WWDG_IRQHandler 0000001A
-
-Symbol: WWDG_IRQHandler
- Definitions
- At line 229 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 79 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 185 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-55 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Absolute symbols
-
-Heap_Size 00000200
-
-Symbol: Heap_Size
- Definitions
- At line 44 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: Heap_Size used once
-Stack_Size 00000400
-
-Symbol: Stack_Size
- Definitions
- At line 33 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: Stack_Size used once
-__Vectors_Size 000000EC
-
-Symbol: __Vectors_Size
- Definitions
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 59 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __Vectors_Size used once
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-External symbols
-
-SystemInit 00000000
-
-Symbol: SystemInit
- Definitions
- At line 132 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 133 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: SystemInit used once
-__main 00000000
-
-Symbol: __main
- Definitions
- At line 131 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 135 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __main used once
-2 symbols
-407 symbols in table
diff --git a/bateau-microcontrolleur/Objects/ExtDll.iex b/bateau-microcontrolleur/Objects/ExtDll.iex
deleted file mode 100644
index 6c0896e..0000000
--- a/bateau-microcontrolleur/Objects/ExtDll.iex
+++ /dev/null
@@ -1,2 +0,0 @@
-[EXTDLL]
-Count=0
diff --git a/bateau-microcontrolleur/Objects/hello_world.axf b/bateau-microcontrolleur/Objects/hello_world.axf
deleted file mode 100644
index 55a2bb3..0000000
Binary files a/bateau-microcontrolleur/Objects/hello_world.axf and /dev/null differ
diff --git a/bateau-microcontrolleur/Objects/hello_world.build_log.htm b/bateau-microcontrolleur/Objects/hello_world.build_log.htm
deleted file mode 100644
index 2a5490c..0000000
--- a/bateau-microcontrolleur/Objects/hello_world.build_log.htm
+++ /dev/null
@@ -1,72 +0,0 @@
-
-
-
-µVision Build Log
-Tool Versions:
-IDE-Version: µVision V5.33.0.0
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: Celia C, Insa, LIC=----
-
-Tool Versions:
-Toolchain: MDK-Lite Version: 5.33.0.0
-Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler: Armcc.exe V5.06 update 7 (build 960)
-Assembler: Armasm.exe V5.06 update 7 (build 960)
-Linker/Locator: ArmLink.exe V5.06 update 7 (build 960)
-Library Manager: ArmAr.exe V5.06 update 7 (build 960)
-Hex Converter: FromElf.exe V5.06 update 7 (build 960)
-CPU DLL: SARMCM3.DLL V5.33.0.0
-Dialog DLL: DARMSTM.DLL V1.68.0.0
-Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.8.0
-Dialog DLL: TARMSTM.DLL V1.66.0.0
-
-Project:
-C:\Users\chauz\Documents_non_drive\INSA\4A\S7\Microcontroleur\bateau-microcontrolleur\bateau-microcontrolleur\hello_world.uvprojx
-Project File Date: 09/13/2021
-
-Output:
-*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Rebuild target 'CarteSTM'
-assembling startup_stm32f10x_md.s...
-compiling principal.c...
-Source\principal.c(35): warning: #1-D: last line of file ends without a newline
- }
-Source\principal.c: 1 warning, 0 errors
-compiling system_stm32f10x.c...
-linking...
-Program Size: Code=552 RO-data=252 RW-data=0 ZI-data=1024
-".\Objects\hello_world.axf" - 0 Error(s), 1 Warning(s).
-
-Software Packages used:
-
-Package Vendor: ARM
- http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
- ARM.CMSIS.5.7.0
- CMSIS (Cortex Microcontroller Software Interface Standard)
- * Component: CORE Version: 5.4.0
-
-Package Vendor: Keil
- http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
- Keil.STM32F1xx_DFP.2.3.0
- STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
- * Component: Startup Version: 1.0.0
-
-Collection of Component include folders:
- .\RTE\Device\STM32F103RB
- .\RTE\_CarteSTM
- C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
- C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-
-Collection of Component Files used:
-
- * Component: ARM::CMSIS:CORE:5.4.0
-
- * Component: Keil::Device:Startup:1.0.0
- Source file: Device\Source\ARM\startup_stm32f10x_md.s
- Source file: Device\Source\system_stm32f10x.c
- Source file: Device\Source\ARM\STM32F1xx_OPT.s
- Include file: RTE_Driver\Config\RTE_Device.h
-Build Time Elapsed: 00:00:01
-
-
-
diff --git a/bateau-microcontrolleur/Objects/hello_world.htm b/bateau-microcontrolleur/Objects/hello_world.htm
deleted file mode 100644
index 605643e..0000000
--- a/bateau-microcontrolleur/Objects/hello_world.htm
+++ /dev/null
@@ -1,356 +0,0 @@
-
-
-Static Call Graph - [.\Objects\hello_world.axf]
-
-Static Call Graph for image .\Objects\hello_world.axf
-
#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Sun Sep 19 19:02:34 2021
-
-
Maximum Stack Usage = 28 bytes + Unknown(Cycles, Untraceable Function Pointers)
-Call chain for Maximum Stack Depth:
-SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
-
-
-Mutually Recursive functions
-
NMI_Handler ⇒ NMI_Handler
- HardFault_Handler ⇒ HardFault_Handler
- MemManage_Handler ⇒ MemManage_Handler
- BusFault_Handler ⇒ BusFault_Handler
- UsageFault_Handler ⇒ UsageFault_Handler
- SVC_Handler ⇒ SVC_Handler
- DebugMon_Handler ⇒ DebugMon_Handler
- PendSV_Handler ⇒ PendSV_Handler
- SysTick_Handler ⇒ SysTick_Handler
- ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
-
-
-
-Function Pointers
-
- - ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI9_5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text)
-
- TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_TRG_COM_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_UP_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text)
-
- main from principal.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-
-Global Symbols
-
-__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(.text)
-
-_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Calls]
-
-__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Called By]
-
-_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-
__rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E))
-
-
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F))
-
-
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011))
-
-
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
-
NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-
[Calls]
- >> __main_after_scatterload
-
-
[Called By]
-
-__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-
SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
-
[Stack]
- Max Depth = 28
- Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(.text)
-
-__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-
main (Thumb, 82 bytes, Stack size 0 bytes, principal.o(i.main))
-
[Address Reference Count : 1]
- entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-Local Symbols
-
-SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
-
[Stack]
- Max Depth = 20
- Call Chain = SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Called By]
-
-SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
-
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
-
-
[Called By]
-
-
-Undefined Global Symbols
-
diff --git a/bateau-microcontrolleur/Objects/hello_world.lnp b/bateau-microcontrolleur/Objects/hello_world.lnp
deleted file mode 100644
index 4140e56..0000000
--- a/bateau-microcontrolleur/Objects/hello_world.lnp
+++ /dev/null
@@ -1,7 +0,0 @@
---cpu Cortex-M3
-".\objects\principal.o"
-".\objects\startup_stm32f10x_md.o"
-".\objects\system_stm32f10x.o"
---library_type=microlib --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\hello_world.map" -o .\Objects\hello_world.axf
\ No newline at end of file
diff --git a/bateau-microcontrolleur/Objects/hello_world_CarteSTM.dep b/bateau-microcontrolleur/Objects/hello_world_CarteSTM.dep
deleted file mode 100644
index 7c4af73..0000000
--- a/bateau-microcontrolleur/Objects/hello_world_CarteSTM.dep
+++ /dev/null
@@ -1,22 +0,0 @@
-Dependencies for Project 'hello_world', Target 'CarteSTM': (DO NOT MODIFY !)
-CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
-F (.\Source\principal.c)(0x6145B463)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_CarteSTM\RTE_Components.h)(0x61447A6A)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59283406)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58258CCC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 533" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58258CCC)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_CarteSTM\RTE_Components.h)(0x61447A6A)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
diff --git a/bateau-microcontrolleur/Objects/hello_world_Simulation.dep b/bateau-microcontrolleur/Objects/hello_world_Simulation.dep
deleted file mode 100644
index 11bb6d5..0000000
--- a/bateau-microcontrolleur/Objects/hello_world_Simulation.dep
+++ /dev/null
@@ -1,14 +0,0 @@
-Dependencies for Project 'hello_world', Target 'Simulation': (DO NOT MODIFY !)
-CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
-F (.\Source\principal.c)(0x613F35FE)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59283406)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58258CCC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58258CCC)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simulation\RTE_Components.h)(0x613F3406)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
diff --git a/bateau-microcontrolleur/Objects/hello_world_Target 1.dep b/bateau-microcontrolleur/Objects/hello_world_Target 1.dep
deleted file mode 100644
index eea001b..0000000
--- a/bateau-microcontrolleur/Objects/hello_world_Target 1.dep
+++ /dev/null
@@ -1,15 +0,0 @@
-Dependencies for Project 'hello_world', Target 'Target 1': (DO NOT MODIFY !)
-CompilerVersion: 6160000::V6.16::ARMCLANG
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59283406)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58258CCC)(--target=arm-arm-none-eabi -mcpu=cortex-m3 -masm=auto -c
-gdwarf-3 -Wa,armasm,--pd,"__EVAL SETA 1"
-I./RTE/Device/STM32F103RB
-I./RTE/_Target_1
-IC:/Programdata/Keil/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include
-IC:/Programdata/Keil/Arm/Packs/Keil/STM32F1xx_DFP/2.3.0/Device/Include
-Wa,armasm,--pd,"__UVISION_VERSION SETA 534" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"STM32F10X_MD SETA 1" -Wa,armasm,--pd,"_RTE_ SETA 1"
-o ./objects/startup_stm32f10x_md.o)
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58258CCC)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c
-fno-rtti -funsigned-char -fshort-enums -fshort-wchar
-D__EVAL -gdwarf-3 -O1 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality
-I./RTE/Device/STM32F103RB
-I./RTE/_Target_1
-IC:/Programdata/Keil/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include
-IC:/Programdata/Keil/Arm/Packs/Keil/STM32F1xx_DFP/2.3.0/Device/Include
-D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o ./objects/system_stm32f10x.o -MD)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (RTE\_Target_1\RTE_Components.h)(0x613F3339)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582)
-I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035F908)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22)
-I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armclang.h)(0x5E8F2582)
-I (C:\Keil_v5\ARM\ARMCLANG\include\arm_compat.h)(0x5EE189B2)
-I (C:\Keil_v5\ARM\ARMCLANG\include\arm_acle.h)(0x6035F904)
-I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
diff --git a/bateau-microcontrolleur/Objects/principal.crf b/bateau-microcontrolleur/Objects/principal.crf
deleted file mode 100644
index 94ce089..0000000
Binary files a/bateau-microcontrolleur/Objects/principal.crf and /dev/null differ
diff --git a/bateau-microcontrolleur/Objects/principal.d b/bateau-microcontrolleur/Objects/principal.d
deleted file mode 100644
index 9619a82..0000000
--- a/bateau-microcontrolleur/Objects/principal.d
+++ /dev/null
@@ -1,9 +0,0 @@
-.\objects\principal.o: Source\principal.c
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\principal.o: .\RTE\_CarteSTM\RTE_Components.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\principal.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/bateau-microcontrolleur/Objects/principal.o b/bateau-microcontrolleur/Objects/principal.o
deleted file mode 100644
index a7031ee..0000000
Binary files a/bateau-microcontrolleur/Objects/principal.o and /dev/null differ
diff --git a/bateau-microcontrolleur/Objects/startup_stm32f10x_md.d b/bateau-microcontrolleur/Objects/startup_stm32f10x_md.d
deleted file mode 100644
index 96d5fcf..0000000
--- a/bateau-microcontrolleur/Objects/startup_stm32f10x_md.d
+++ /dev/null
@@ -1 +0,0 @@
-.\objects\startup_stm32f10x_md.o: RTE\Device\STM32F103RB\startup_stm32f10x_md.s
diff --git a/bateau-microcontrolleur/Objects/startup_stm32f10x_md.o b/bateau-microcontrolleur/Objects/startup_stm32f10x_md.o
deleted file mode 100644
index a2941f8..0000000
Binary files a/bateau-microcontrolleur/Objects/startup_stm32f10x_md.o and /dev/null differ
diff --git a/bateau-microcontrolleur/Objects/system_stm32f10x.crf b/bateau-microcontrolleur/Objects/system_stm32f10x.crf
deleted file mode 100644
index 5d5784b..0000000
Binary files a/bateau-microcontrolleur/Objects/system_stm32f10x.crf and /dev/null differ
diff --git a/bateau-microcontrolleur/Objects/system_stm32f10x.d b/bateau-microcontrolleur/Objects/system_stm32f10x.d
deleted file mode 100644
index b0d089a..0000000
--- a/bateau-microcontrolleur/Objects/system_stm32f10x.d
+++ /dev/null
@@ -1,9 +0,0 @@
-.\objects\system_stm32f10x.o: RTE\Device\STM32F103RB\system_stm32f10x.c
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\system_stm32f10x.o: .\RTE\_CarteSTM\RTE_Components.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/bateau-microcontrolleur/Objects/system_stm32f10x.o b/bateau-microcontrolleur/Objects/system_stm32f10x.o
deleted file mode 100644
index dc46f1b..0000000
Binary files a/bateau-microcontrolleur/Objects/system_stm32f10x.o and /dev/null differ
diff --git a/bateau-microcontrolleur/RTE/Device/STM32F103RB/RTE_Device.h b/bateau-microcontrolleur/RTE/Device/STM32F103RB/RTE_Device.h
deleted file mode 100644
index 22d1da2..0000000
--- a/bateau-microcontrolleur/RTE/Device/STM32F103RB/RTE_Device.h
+++ /dev/null
@@ -1,1828 +0,0 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2016 ARM Ltd.
- *
- * This software is provided 'as-is', without any express or implied warranty.
- * In no event will the authors be held liable for any damages arising from
- * the use of this software. Permission is granted to anyone to use this
- * software for any purpose, including commercial applications, and to alter
- * it and redistribute it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software. If you use this software in
- * a product, an acknowledgment in the product documentation would be
- * appreciated but is not required.
- *
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.
- *
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * $Date: 09. September 2016
- * $Revision: V1.1.2
- *
- * Project: RTE Device Configuration for STMicroelectronics STM32F1xx
- *
- * -------------------------------------------------------------------------- */
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-#ifndef __RTE_DEVICE_H
-#define __RTE_DEVICE_H
-
-
-#define GPIO_PORT(num) \
- ((num == 0) ? GPIOA : \
- (num == 1) ? GPIOB : \
- (num == 2) ? GPIOC : \
- (num == 3) ? GPIOD : \
- (num == 4) ? GPIOE : \
- (num == 5) ? GPIOF : \
- (num == 6) ? GPIOG : \
- NULL)
-
-
-// Clock Configuration
-// High-speed Internal Clock <1-999999999>
-#define RTE_HSI 8000000
-// High-speed External Clock <1-999999999>
-#define RTE_HSE 25000000
-// System Clock <1-999999999>
-#define RTE_SYSCLK 72000000
-// HCLK Clock <1-999999999>
-#define RTE_HCLK 72000000
-// APB1 Clock <1-999999999>
-#define RTE_PCLK1 36000000
-// APB2 Clock <1-999999999>
-#define RTE_PCLK2 72000000
-// ADC Clock <1-999999999>
-#define RTE_ADCCLK 36000000
-// USB Clock
-#define RTE_USBCLK 48000000
-//
-
-
-// USART1 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
-#define RTE_USART1 0
-
-// USART1_TX Pin <0=>Not Used <1=>PA9
-#define RTE_USART1_TX_PORT_ID_DEF 0
-#if (RTE_USART1_TX_PORT_ID_DEF == 0)
-#define RTE_USART1_TX_DEF 0
-#elif (RTE_USART1_TX_PORT_ID_DEF == 1)
-#define RTE_USART1_TX_DEF 1
-#define RTE_USART1_TX_PORT_DEF GPIOA
-#define RTE_USART1_TX_BIT_DEF 9
-#else
-#error "Invalid USART1_TX Pin Configuration!"
-#endif
-
-// USART1_RX Pin <0=>Not Used <1=>PA10
-#define RTE_USART1_RX_PORT_ID_DEF 0
-#if (RTE_USART1_RX_PORT_ID_DEF == 0)
-#define RTE_USART1_RX_DEF 0
-#elif (RTE_USART1_RX_PORT_ID_DEF == 1)
-#define RTE_USART1_RX_DEF 1
-#define RTE_USART1_RX_PORT_DEF GPIOA
-#define RTE_USART1_RX_BIT_DEF 10
-#else
-#error "Invalid USART1_RX Pin Configuration!"
-#endif
-
-// USART1_CK Pin <0=>Not Used <1=>PA8
-#define RTE_USART1_CK_PORT_ID_DEF 0
-#if (RTE_USART1_CK_PORT_ID_DEF == 0)
-#define RTE_USART1_CK 0
-#elif (RTE_USART1_CK_PORT_ID_DEF == 1)
-#define RTE_USART1_CK 1
-#define RTE_USART1_CK_PORT_DEF GPIOA
-#define RTE_USART1_CK_BIT_DEF 8
-#else
-#error "Invalid USART1_CK Pin Configuration!"
-#endif
-
-// USART1_CTS Pin <0=>Not Used <1=>PA11
-#define RTE_USART1_CTS_PORT_ID_DEF 0
-#if (RTE_USART1_CTS_PORT_ID_DEF == 0)
-#define RTE_USART1_CTS 0
-#elif (RTE_USART1_CTS_PORT_ID_DEF == 1)
-#define RTE_USART1_CTS 1
-#define RTE_USART1_CTS_PORT_DEF GPIOA
-#define RTE_USART1_CTS_BIT_DEF 11
-#else
-#error "Invalid USART1_CTS Pin Configuration!"
-#endif
-
-// USART1_RTS Pin <0=>Not Used <1=>PA12
-#define RTE_USART1_RTS_PORT_ID_DEF 0
-#if (RTE_USART1_RTS_PORT_ID_DEF == 0)
-#define RTE_USART1_RTS 0
-#elif (RTE_USART1_RTS_PORT_ID_DEF == 1)
-#define RTE_USART1_RTS 1
-#define RTE_USART1_RTS_PORT_DEF GPIOA
-#define RTE_USART1_RTS_BIT_DEF 12
-#else
-#error "Invalid USART1_RTS Pin Configuration!"
-#endif
-
-// USART1 Pin Remap
-// Enable USART1 Pin Remapping
-#define RTE_USART1_REMAP_FULL 0
-
-// USART1_TX Pin <0=>Not Used <1=>PB6
-#define RTE_USART1_TX_PORT_ID_FULL 0
-#if (RTE_USART1_TX_PORT_ID_FULL == 0)
-#define RTE_USART1_TX_FULL 0
-#elif (RTE_USART1_TX_PORT_ID_FULL == 1)
-#define RTE_USART1_TX_FULL 1
-#define RTE_USART1_TX_PORT_FULL GPIOB
-#define RTE_USART1_TX_BIT_FULL 6
-#else
-#error "Invalid USART1_TX Pin Configuration!"
-#endif
-
-// USART1_RX Pin <0=>Not Used <1=>PB7
-#define RTE_USART1_RX_PORT_ID_FULL 0
-#if (RTE_USART1_RX_PORT_ID_FULL == 0)
-#define RTE_USART1_RX_FULL 0
-#elif (RTE_USART1_RX_PORT_ID_FULL == 1)
-#define RTE_USART1_RX_FULL 1
-#define RTE_USART1_RX_PORT_FULL GPIOB
-#define RTE_USART1_RX_BIT_FULL 7
-#else
-#error "Invalid USART1_RX Pin Configuration!"
-#endif
-//
-
-#if (RTE_USART1_REMAP_FULL)
-#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP
-#define RTE_USART1_TX RTE_USART1_TX_FULL
-#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL
-#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL
-#define RTE_USART1_RX RTE_USART1_RX_FULL
-#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL
-#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL
-#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
-#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
-#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
-#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
-#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
-#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
-#else
-#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP
-#define RTE_USART1_TX RTE_USART1_TX_DEF
-#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF
-#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF
-#define RTE_USART1_RX RTE_USART1_RX_DEF
-#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF
-#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF
-#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
-#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
-#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
-#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
-#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
-#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART1_RX_DMA 0
-#define RTE_USART1_RX_DMA_NUMBER 1
-#define RTE_USART1_RX_DMA_CHANNEL 5
-#define RTE_USART1_RX_DMA_PRIORITY 0
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART1_TX_DMA 0
-#define RTE_USART1_TX_DMA_NUMBER 1
-#define RTE_USART1_TX_DMA_CHANNEL 4
-#define RTE_USART1_TX_DMA_PRIORITY 0
-//
-
-
-// USART2 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
-#define RTE_USART2 0
-
-// USART2_TX Pin <0=>Not Used <1=>PA2
-#define RTE_USART2_TX_PORT_ID_DEF 0
-#if (RTE_USART2_TX_PORT_ID_DEF == 0)
-#define RTE_USART2_TX_DEF 0
-#elif (RTE_USART2_TX_PORT_ID_DEF == 1)
-#define RTE_USART2_TX_DEF 1
-#define RTE_USART2_TX_PORT_DEF GPIOA
-#define RTE_USART2_TX_BIT_DEF 2
-#else
-#error "Invalid USART2_TX Pin Configuration!"
-#endif
-
-// USART2_RX Pin <0=>Not Used <1=>PA3
-#define RTE_USART2_RX_PORT_ID_DEF 0
-#if (RTE_USART2_RX_PORT_ID_DEF == 0)
-#define RTE_USART2_RX_DEF 0
-#elif (RTE_USART2_RX_PORT_ID_DEF == 1)
-#define RTE_USART2_RX_DEF 1
-#define RTE_USART2_RX_PORT_DEF GPIOA
-#define RTE_USART2_RX_BIT_DEF 3
-#else
-#error "Invalid USART2_RX Pin Configuration!"
-#endif
-
-// USART2_CK Pin <0=>Not Used <1=>PA4
-#define RTE_USART2_CK_PORT_ID_DEF 0
-#if (RTE_USART2_CK_PORT_ID_DEF == 0)
-#define RTE_USART2_CK_DEF 0
-#elif (RTE_USART2_CK_PORT_ID_DEF == 1)
-#define RTE_USART2_CK_DEF 1
-#define RTE_USART2_CK_PORT_DEF GPIOA
-#define RTE_USART2_CK_BIT_DEF 4
-#else
-#error "Invalid USART2_CK Pin Configuration!"
-#endif
-
-// USART2_CTS Pin <0=>Not Used <1=>PA0
-#define RTE_USART2_CTS_PORT_ID_DEF 0
-#if (RTE_USART2_CTS_PORT_ID_DEF == 0)
-#define RTE_USART2_CTS_DEF 0
-#elif (RTE_USART2_CTS_PORT_ID_DEF == 1)
-#define RTE_USART2_CTS_DEF 1
-#define RTE_USART2_CTS_PORT_DEF GPIOA
-#define RTE_USART2_CTS_BIT_DEF 0
-#else
-#error "Invalid USART2_CTS Pin Configuration!"
-#endif
-
-// USART2_RTS Pin <0=>Not Used <1=>PA1
-#define RTE_USART2_RTS_PORT_ID_DEF 0
-#if (RTE_USART2_RTS_PORT_ID_DEF == 0)
-#define RTE_USART2_RTS_DEF 0
-#elif (RTE_USART2_RTS_PORT_ID_DEF == 1)
-#define RTE_USART2_RTS_DEF 1
-#define RTE_USART2_RTS_PORT_DEF GPIOA
-#define RTE_USART2_RTS_BIT_DEF 1
-#else
-#error "Invalid USART2_RTS Pin Configuration!"
-#endif
-
-// USART2 Pin Remap
-// Enable USART2 Pin Remapping
-#define RTE_USART2_REMAP_FULL 0
-
-// USART2_TX Pin <0=>Not Used <1=>PD5
-#define RTE_USART2_TX_PORT_ID_FULL 0
-#if (RTE_USART2_TX_PORT_ID_FULL == 0)
-#define RTE_USART2_TX_FULL 0
-#elif (RTE_USART2_TX_PORT_ID_FULL == 1)
-#define RTE_USART2_TX_FULL 1
-#define RTE_USART2_TX_PORT_FULL GPIOD
-#define RTE_USART2_TX_BIT_FULL 5
-#else
-#error "Invalid USART2_TX Pin Configuration!"
-#endif
-
-// USART2_RX Pin <0=>Not Used <1=>PD6
-#define RTE_USART2_RX_PORT_ID_FULL 0
-#if (RTE_USART2_RX_PORT_ID_FULL == 0)
-#define RTE_USART2_RX_FULL 0
-#elif (RTE_USART2_RX_PORT_ID_FULL == 1)
-#define RTE_USART2_RX_FULL 1
-#define RTE_USART2_RX_PORT_FULL GPIOD
-#define RTE_USART2_RX_BIT_FULL 6
-#else
-#error "Invalid USART2_RX Pin Configuration!"
-#endif
-
-// USART2_CK Pin <0=>Not Used <1=>PD7
-#define RTE_USART2_CK_PORT_ID_FULL 0
-#if (RTE_USART2_CK_PORT_ID_FULL == 0)
-#define RTE_USART2_CK_FULL 0
-#elif (RTE_USART2_CK_PORT_ID_FULL == 1)
-#define RTE_USART2_CK_FULL 1
-#define RTE_USART2_CK_PORT_FULL GPIOD
-#define RTE_USART2_CK_BIT_FULL 7
-#else
-#error "Invalid USART2_CK Pin Configuration!"
-#endif
-
-// USART2_CTS Pin <0=>Not Used <1=>PD3
-#define RTE_USART2_CTS_PORT_ID_FULL 0
-#if (RTE_USART2_CTS_PORT_ID_FULL == 0)
-#define RTE_USART2_CTS_FULL 0
-#elif (RTE_USART2_CTS_PORT_ID_FULL == 1)
-#define RTE_USART2_CTS_FULL 1
-#define RTE_USART2_CTS_PORT_FULL GPIOD
-#define RTE_USART2_CTS_BIT_FULL 3
-#else
-#error "Invalid USART2_CTS Pin Configuration!"
-#endif
-
-// USART2_RTS Pin <0=>Not Used <1=>PD4
-#define RTE_USART2_RTS_PORT_ID_FULL 0
-#if (RTE_USART2_RTS_PORT_ID_FULL == 0)
-#define RTE_USART2_RTS_FULL 0
-#elif (RTE_USART2_RTS_PORT_ID_FULL == 1)
-#define RTE_USART2_RTS_FULL 1
-#define RTE_USART2_RTS_PORT_FULL GPIOD
-#define RTE_USART2_RTS_BIT_FULL 4
-#else
-#error "Invalid USART2_RTS Pin Configuration!"
-#endif
-//
-
-#if (RTE_USART2_REMAP_FULL)
-#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP
-#define RTE_USART2_TX RTE_USART2_TX_FULL
-#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL
-#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL
-#define RTE_USART2_RX RTE_USART2_RX_FULL
-#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL
-#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL
-#define RTE_USART2_CK RTE_USART2_CK_FULL
-#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL
-#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL
-#define RTE_USART2_CTS RTE_USART2_CTS_FULL
-#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL
-#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL
-#define RTE_USART2_RTS RTE_USART2_RTS_FULL
-#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL
-#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL
-#else
-#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP
-#define RTE_USART2_TX RTE_USART2_TX_DEF
-#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF
-#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF
-#define RTE_USART2_RX RTE_USART2_RX_DEF
-#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF
-#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF
-#define RTE_USART2_CK RTE_USART2_CK_DEF
-#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF
-#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF
-#define RTE_USART2_CTS RTE_USART2_CTS_DEF
-#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF
-#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF
-#define RTE_USART2_RTS RTE_USART2_RTS_DEF
-#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF
-#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <6=>6
-// Selects DMA Channel (only Channel 6 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART2_RX_DMA 0
-#define RTE_USART2_RX_DMA_NUMBER 1
-#define RTE_USART2_RX_DMA_CHANNEL 6
-#define RTE_USART2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <7=>7
-// Selects DMA Channel (only Channel 7 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART2_TX_DMA 0
-#define RTE_USART2_TX_DMA_NUMBER 1
-#define RTE_USART2_TX_DMA_CHANNEL 7
-#define RTE_USART2_TX_DMA_PRIORITY 0
-
-//
-
-
-// USART3 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
-#define RTE_USART3 0
-
-// USART3_TX Pin <0=>Not Used <1=>PB10
-#define RTE_USART3_TX_PORT_ID_DEF 0
-#if (RTE_USART3_TX_PORT_ID_DEF == 0)
-#define RTE_USART3_TX_DEF 0
-#elif (RTE_USART3_TX_PORT_ID_DEF == 1)
-#define RTE_USART3_TX_DEF 1
-#define RTE_USART3_TX_PORT_DEF GPIOB
-#define RTE_USART3_TX_BIT_DEF 10
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PB11
-#define RTE_USART3_RX_PORT_ID_DEF 0
-#if (RTE_USART3_RX_PORT_ID_DEF == 0)
-#define RTE_USART3_RX_DEF 0
-#elif (RTE_USART3_RX_PORT_ID_DEF == 1)
-#define RTE_USART3_RX_DEF 1
-#define RTE_USART3_RX_PORT_DEF GPIOB
-#define RTE_USART3_RX_BIT_DEF 11
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PB12
-#define RTE_USART3_CK_PORT_ID_DEF 0
-#if (RTE_USART3_CK_PORT_ID_DEF == 0)
-#define RTE_USART3_CK_DEF 0
-#elif (RTE_USART3_CK_PORT_ID_DEF == 1)
-#define RTE_USART3_CK_DEF 1
-#define RTE_USART3_CK_PORT_DEF GPIOB
-#define RTE_USART3_CK_BIT_DEF 12
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-
-// USART3_CTS Pin <0=>Not Used <1=>PB13
-#define RTE_USART3_CTS_PORT_ID_DEF 0
-#if (RTE_USART3_CTS_PORT_ID_DEF == 0)
-#define RTE_USART3_CTS_DEF 0
-#elif (RTE_USART3_CTS_PORT_ID_DEF == 1)
-#define RTE_USART3_CTS_DEF 1
-#define RTE_USART3_CTS_PORT_DEF GPIOB
-#define RTE_USART3_CTS_BIT_DEF 13
-#else
-#error "Invalid USART3_CTS Pin Configuration!"
-#endif
-
-// USART3_RTS Pin <0=>Not Used <1=>PB14
-#define RTE_USART3_RTS_PORT_ID_DEF 0
-#if (RTE_USART3_RTS_PORT_ID_DEF == 0)
-#define RTE_USART3_RTS_DEF 0
-#elif (RTE_USART3_RTS_PORT_ID_DEF == 1)
-#define RTE_USART3_RTS_DEF 1
-#define RTE_USART3_RTS_PORT_DEF GPIOB
-#define RTE_USART3_RTS_BIT_DEF 14
-#else
-#error "Invalid USART3_RTS Pin Configuration!"
-#endif
-
-// USART3 Partial Pin Remap
-// Enable USART3 Partial Pin Remapping
-#define RTE_USART3_REMAP_PARTIAL 0
-
-// USART3_TX Pin <0=>Not Used <1=>PC10
-#define RTE_USART3_TX_PORT_ID_PARTIAL 0
-#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_TX_PARTIAL 0
-#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_TX_PARTIAL 1
-#define RTE_USART3_TX_PORT_PARTIAL GPIOC
-#define RTE_USART3_TX_BIT_PARTIAL 10
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PC11
-#define RTE_USART3_RX_PORT_ID_PARTIAL 0
-#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_RX_PARTIAL 0
-#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_RX_PARTIAL 1
-#define RTE_USART3_RX_PORT_PARTIAL GPIOC
-#define RTE_USART3_RX_BIT_PARTIAL 11
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PC12
-#define RTE_USART3_CK_PORT_ID_PARTIAL 0
-#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_CK_PARTIAL 0
-#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_CK_PARTIAL 1
-#define RTE_USART3_CK_PORT_PARTIAL GPIOC
-#define RTE_USART3_CK_BIT_PARTIAL 12
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-//
-
-// USART3 Full Pin Remap
-// Enable USART3 Full Pin Remapping
-#define RTE_USART3_REMAP_FULL 0
-
-// USART3_TX Pin <0=>Not Used <1=>PD8
-#define RTE_USART3_TX_PORT_ID_FULL 0
-#if (RTE_USART3_TX_PORT_ID_FULL == 0)
-#define RTE_USART3_TX_FULL 0
-#elif (RTE_USART3_TX_PORT_ID_FULL == 1)
-#define RTE_USART3_TX_FULL 1
-#define RTE_USART3_TX_PORT_FULL GPIOD
-#define RTE_USART3_TX_BIT_FULL 8
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PD9
-#define RTE_USART3_RX_PORT_ID_FULL 0
-#if (RTE_USART3_RX_PORT_ID_FULL == 0)
-#define RTE_USART3_RX_FULL 0
-#elif (RTE_USART3_RX_PORT_ID_FULL == 1)
-#define RTE_USART3_RX_FULL 1
-#define RTE_USART3_RX_PORT_FULL GPIOD
-#define RTE_USART3_RX_BIT_FULL 9
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PD10
-#define RTE_USART3_CK_PORT_ID_FULL 0
-#if (RTE_USART3_CK_PORT_ID_FULL == 0)
-#define RTE_USART3_CK_FULL 0
-#elif (RTE_USART3_CK_PORT_ID_FULL == 1)
-#define RTE_USART3_CK_FULL 1
-#define RTE_USART3_CK_PORT_FULL GPIOD
-#define RTE_USART3_CK_BIT_FULL 10
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-
-// USART3_CTS Pin <0=>Not Used <1=>PD11
-#define RTE_USART3_CTS_PORT_ID_FULL 0
-#if (RTE_USART3_CTS_PORT_ID_FULL == 0)
-#define RTE_USART3_CTS_FULL 0
-#elif (RTE_USART3_CTS_PORT_ID_FULL == 1)
-#define RTE_USART3_CTS_FULL 1
-#define RTE_USART3_CTS_PORT_FULL GPIOD
-#define RTE_USART3_CTS_BIT_FULL 11
-#else
-#error "Invalid USART3_CTS Pin Configuration!"
-#endif
-
-// USART3_RTS Pin <0=>Not Used <1=>PD12
-#define RTE_USART3_RTS_PORT_ID_FULL 0
-#if (RTE_USART3_RTS_PORT_ID_FULL == 0)
-#define RTE_USART3_RTS_FULL 0
-#elif (RTE_USART3_RTS_PORT_ID_FULL == 1)
-#define RTE_USART3_RTS_FULL 1
-#define RTE_USART3_RTS_PORT_FULL GPIOD
-#define RTE_USART3_RTS_BIT_FULL 12
-#else
-#error "Invalid USART3_RTS Pin Configuration!"
-#endif
-//
-
-#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
-#error "Invalid USART3 Pin Remap Configuration!"
-#endif
-
-#if (RTE_USART3_REMAP_FULL)
-#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL
-#define RTE_USART3_TX RTE_USART3_TX_FULL
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL
-#define RTE_USART3_RX RTE_USART3_RX_FULL
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL
-#define RTE_USART3_CK RTE_USART3_CK_FULL
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL
-#define RTE_USART3_CTS RTE_USART3_CTS_FULL
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL
-#define RTE_USART3_RTS RTE_USART3_RTS_FULL
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL
-#elif (RTE_USART3_REMAP_PARTIAL)
-#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL
-#define RTE_USART3_TX RTE_USART3_TX_PARTIAL
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL
-#define RTE_USART3_RX RTE_USART3_RX_PARTIAL
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL
-#define RTE_USART3_CK RTE_USART3_CK_PARTIAL
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL
-#define RTE_USART3_CTS RTE_USART3_CTS_DEF
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
-#define RTE_USART3_RTS RTE_USART3_RTS_DEF
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
-#else
-#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP
-#define RTE_USART3_TX RTE_USART3_TX_DEF
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF
-#define RTE_USART3_RX RTE_USART3_RX_DEF
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF
-#define RTE_USART3_CK RTE_USART3_CK_DEF
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF
-#define RTE_USART3_CTS RTE_USART3_CTS_DEF
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
-#define RTE_USART3_RTS RTE_USART3_RTS_DEF
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_USART3_RX_DMA 0
-#define RTE_USART3_RX_DMA_NUMBER 1
-#define RTE_USART3_RX_DMA_CHANNEL 3
-#define RTE_USART3_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_USART3_TX_DMA 0
-#define RTE_USART3_TX_DMA_NUMBER 1
-#define RTE_USART3_TX_DMA_CHANNEL 2
-#define RTE_USART3_TX_DMA_PRIORITY 0
-
-//
-
-
-// UART4 (Universal asynchronous receiver transmitter)
-// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
-#define RTE_UART4 0
-#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// UART4_TX Pin <0=>Not Used <1=>PC10
-#define RTE_UART4_TX_ID 0
-#if (RTE_UART4_TX_ID == 0)
-#define RTE_UART4_TX 0
-#elif (RTE_UART4_TX_ID == 1)
-#define RTE_UART4_TX 1
-#define RTE_UART4_TX_PORT GPIOC
-#define RTE_UART4_TX_BIT 10
-#else
-#error "Invalid UART4_TX Pin Configuration!"
-#endif
-
-// UART4_RX Pin <0=>Not Used <1=>PC11
-#define RTE_UART4_RX_ID 0
-#if (RTE_UART4_RX_ID == 0)
-#define RTE_UART4_RX 0
-#elif (RTE_UART4_RX_ID == 1)
-#define RTE_UART4_RX 1
-#define RTE_UART4_RX_PORT GPIOC
-#define RTE_UART4_RX_BIT 11
-#else
-#error "Invalid UART4_RX Pin Configuration!"
-#endif
-
-
-// DMA Rx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_UART4_RX_DMA 0
-#define RTE_UART4_RX_DMA_NUMBER 2
-#define RTE_UART4_RX_DMA_CHANNEL 3
-#define RTE_UART4_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_UART4_TX_DMA 0
-#define RTE_UART4_TX_DMA_NUMBER 2
-#define RTE_UART4_TX_DMA_CHANNEL 5
-#define RTE_UART4_TX_DMA_PRIORITY 0
-
-//
-
-
-// UART5 (Universal asynchronous receiver transmitter)
-// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
-#define RTE_UART5 0
-#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// UART5_TX Pin <0=>Not Used <1=>PC12
-#define RTE_UART5_TX_ID 0
-#if (RTE_UART5_TX_ID == 0)
-#define RTE_UART5_TX 0
-#elif (RTE_UART5_TX_ID == 1)
-#define RTE_UART5_TX 1
-#define RTE_UART5_TX_PORT GPIOC
-#define RTE_UART5_TX_BIT 12
-#else
-#error "Invalid UART5_TX Pin Configuration!"
-#endif
-
-// UART5_RX Pin <0=>Not Used <1=>PD2
-#define RTE_UART5_RX_ID 0
-#if (RTE_UART5_RX_ID == 0)
-#define RTE_UART5_RX 0
-#elif (RTE_UART5_RX_ID == 1)
-#define RTE_UART5_RX 1
-#define RTE_UART5_RX_PORT GPIOD
-#define RTE_UART5_RX_BIT 2
-#else
-#error "Invalid UART5_RX Pin Configuration!"
-#endif
-//
-
-
-// I2C1 (Inter-integrated Circuit Interface 1)
-// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
-#define RTE_I2C1 0
-
-// I2C1_SCL Pin <0=>PB6
-#define RTE_I2C1_SCL_PORT_ID_DEF 0
-#if (RTE_I2C1_SCL_PORT_ID_DEF == 0)
-#define RTE_I2C1_SCL_PORT_DEF GPIOB
-#define RTE_I2C1_SCL_BIT_DEF 6
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1_SDA Pin <0=>PB7
-#define RTE_I2C1_SDA_PORT_ID_DEF 0
-#if (RTE_I2C1_SDA_PORT_ID_DEF == 0)
-#define RTE_I2C1_SDA_PORT_DEF GPIOB
-#define RTE_I2C1_SDA_BIT_DEF 7
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1 Pin Remap
-// Enable I2C1 Pin Remapping
-#define RTE_I2C1_REMAP_FULL 0
-
-// I2C1_SCL Pin <0=>PB8
-#define RTE_I2C1_SCL_PORT_ID_FULL 0
-#if (RTE_I2C1_SCL_PORT_ID_FULL == 0)
-#define RTE_I2C1_SCL_PORT_FULL GPIOB
-#define RTE_I2C1_SCL_BIT_FULL 8
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1_SDA Pin <0=>PB9
-#define RTE_I2C1_SDA_PORT_ID_FULL 0
-#if (RTE_I2C1_SDA_PORT_ID_FULL == 0)
-#define RTE_I2C1_SDA_PORT_FULL GPIOB
-#define RTE_I2C1_SDA_BIT_FULL 9
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_I2C1_REMAP_FULL)
-#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP
-#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL
-#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL
-#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL
-#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL
-#else
-#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP
-#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF
-#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF
-#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF
-#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF
-#endif
-
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <7=>7
-// Selects DMA Channel (only Channel 7 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C1_RX_DMA 0
-#define RTE_I2C1_RX_DMA_NUMBER 1
-#define RTE_I2C1_RX_DMA_CHANNEL 7
-#define RTE_I2C1_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <6=>6
-// Selects DMA Channel (only Channel 6 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C1_TX_DMA 0
-#define RTE_I2C1_TX_DMA_NUMBER 1
-#define RTE_I2C1_TX_DMA_CHANNEL 6
-#define RTE_I2C1_TX_DMA_PRIORITY 0
-
-//
-
-
-// I2C2 (Inter-integrated Circuit Interface 2)
-// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
-#define RTE_I2C2 0
-#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// I2C2_SCL Pin <0=>PB10
-#define RTE_I2C2_SCL_PORT_ID 0
-#if (RTE_I2C2_SCL_PORT_ID == 0)
-#define RTE_I2C2_SCL_PORT GPIOB
-#define RTE_I2C2_SCL_BIT 10
-#else
-#error "Invalid I2C2_SCL Pin Configuration!"
-#endif
-
-// I2C2_SDA Pin <0=>PB11
-#define RTE_I2C2_SDA_PORT_ID 0
-#if (RTE_I2C2_SDA_PORT_ID == 0)
-#define RTE_I2C2_SDA_PORT GPIOB
-#define RTE_I2C2_SDA_BIT 11
-#else
-#error "Invalid I2C2_SCL Pin Configuration!"
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C2_RX_DMA 1
-#define RTE_I2C2_RX_DMA_NUMBER 1
-#define RTE_I2C2_RX_DMA_CHANNEL 5
-#define RTE_I2C2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C2_TX_DMA 1
-#define RTE_I2C2_TX_DMA_NUMBER 1
-#define RTE_I2C2_TX_DMA_CHANNEL 4
-#define RTE_I2C2_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
-// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
-#define RTE_SPI1 0
-
-// SPI1_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI1_NSS_PIN 1
-#define RTE_SPI1_NSS_PORT GPIO_PORT(0)
-#define RTE_SPI1_NSS_BIT 4
-
-// SPI1_SCK Pin <0=>PA5
-#define RTE_SPI1_SCK_PORT_ID_DEF 0
-#if (RTE_SPI1_SCK_PORT_ID_DEF == 0)
-#define RTE_SPI1_SCK_PORT_DEF GPIOA
-#define RTE_SPI1_SCK_BIT_DEF 5
-#else
-#error "Invalid SPI1_SCK Pin Configuration!"
-#endif
-
-// SPI1_MISO Pin <0=>Not Used <1=>PA6
-#define RTE_SPI1_MISO_PORT_ID_DEF 0
-#if (RTE_SPI1_MISO_PORT_ID_DEF == 0)
-#define RTE_SPI1_MISO_DEF 0
-#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1)
-#define RTE_SPI1_MISO_DEF 1
-#define RTE_SPI1_MISO_PORT_DEF GPIOA
-#define RTE_SPI1_MISO_BIT_DEF 6
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-
-// SPI1_MOSI Pin <0=>Not Used <1=>PA7
-#define RTE_SPI1_MOSI_PORT_ID_DEF 0
-#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
-#define RTE_SPI1_MOSI_DEF 0
-#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
-#define RTE_SPI1_MOSI_DEF 1
-#define RTE_SPI1_MOSI_PORT_DEF GPIOA
-#define RTE_SPI1_MOSI_BIT_DEF 7
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-
-// SPI1 Pin Remap
-// Enable SPI1 Pin Remapping.
-#define RTE_SPI1_REMAP 0
-
-// SPI1_SCK Pin <0=>PB3
-#define RTE_SPI1_SCK_PORT_ID_FULL 0
-#if (RTE_SPI1_SCK_PORT_ID_FULL == 0)
-#define RTE_SPI1_SCK_PORT_FULL GPIOB
-#define RTE_SPI1_SCK_BIT_FULL 3
-#else
-#error "Invalid SPI1_SCK Pin Configuration!"
-#endif
-
-// SPI1_MISO Pin <0=>Not Used <1=>PB4
-#define RTE_SPI1_MISO_PORT_ID_FULL 0
-#if (RTE_SPI1_MISO_PORT_ID_FULL == 0)
-#define RTE_SPI1_MISO_FULL 0
-#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1)
-#define RTE_SPI1_MISO_FULL 1
-#define RTE_SPI1_MISO_PORT_FULL GPIOB
-#define RTE_SPI1_MISO_BIT_FULL 4
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-// SPI1_MOSI Pin <0=>Not Used <1=>PB5
-#define RTE_SPI1_MOSI_PORT_ID_FULL 0
-#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
-#define RTE_SPI1_MOSI_FULL 0
-#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
-#define RTE_SPI1_MOSI_FULL 1
-#define RTE_SPI1_MOSI_PORT_FULL GPIOB
-#define RTE_SPI1_MOSI_BIT_FULL 5
-#else
-#error "Invalid SPI1_MOSI Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_SPI1_REMAP)
-#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP
-#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL
-#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL
-#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL
-#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL
-#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL
-#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL
-#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL
-#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL
-#else
-#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP
-#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF
-#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF
-#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF
-#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF
-#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF
-#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF
-#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF
-#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI1_RX_DMA 0
-#define RTE_SPI1_RX_DMA_NUMBER 1
-#define RTE_SPI1_RX_DMA_CHANNEL 2
-#define RTE_SPI1_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI1_TX_DMA 0
-#define RTE_SPI1_TX_DMA_NUMBER 1
-#define RTE_SPI1_TX_DMA_CHANNEL 3
-#define RTE_SPI1_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
-// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
-#define RTE_SPI2 0
-
-// SPI2_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI2_NSS_PIN 1
-#define RTE_SPI2_NSS_PORT GPIO_PORT(1)
-#define RTE_SPI2_NSS_BIT 12
-
-// SPI2_SCK Pin <0=>PB13
-#define RTE_SPI2_SCK_PORT_ID 0
-#if (RTE_SPI2_SCK_PORT_ID == 0)
-#define RTE_SPI2_SCK_PORT GPIOB
-#define RTE_SPI2_SCK_BIT 13
-#define RTE_SPI2_SCK_REMAP 0
-#else
-#error "Invalid SPI2_SCK Pin Configuration!"
-#endif
-
-// SPI2_MISO Pin <0=>Not Used <1=>PB14
-#define RTE_SPI2_MISO_PORT_ID 0
-#if (RTE_SPI2_MISO_PORT_ID == 0)
-#define RTE_SPI2_MISO 0
-#elif (RTE_SPI2_MISO_PORT_ID == 1)
-#define RTE_SPI2_MISO 1
-#define RTE_SPI2_MISO_PORT GPIOB
-#define RTE_SPI2_MISO_BIT 14
-#define RTE_SPI2_MISO_REMAP 0
-#else
-#error "Invalid SPI2_MISO Pin Configuration!"
-#endif
-
-// SPI2_MOSI Pin <0=>Not Used <1=>PB15
-#define RTE_SPI2_MOSI_PORT_ID 0
-#if (RTE_SPI2_MOSI_PORT_ID == 0)
-#define RTE_SPI2_MOSI 0
-#elif (RTE_SPI2_MOSI_PORT_ID == 1)
-#define RTE_SPI2_MOSI 1
-#define RTE_SPI2_MOSI_PORT GPIOB
-#define RTE_SPI2_MOSI_BIT 15
-#define RTE_SPI2_MOSI_REMAP 0
-#else
-#error "Invalid SPI2_MISO Pin Configuration!"
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI2_RX_DMA 0
-#define RTE_SPI2_RX_DMA_NUMBER 1
-#define RTE_SPI2_RX_DMA_CHANNEL 4
-#define RTE_SPI2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI2_TX_DMA 0
-#define RTE_SPI2_TX_DMA_NUMBER 1
-#define RTE_SPI2_TX_DMA_CHANNEL 5
-#define RTE_SPI2_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
-// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
-#define RTE_SPI3 0
-
-// SPI3_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI3_NSS_PIN 1
-#define RTE_SPI3_NSS_PORT GPIO_PORT(0)
-#define RTE_SPI3_NSS_BIT 15
-
-// SPI3_SCK Pin <0=>PB3
-#define RTE_SPI3_SCK_PORT_ID_DEF 0
-#if (RTE_SPI3_SCK_PORT_ID_DEF == 0)
-#define RTE_SPI3_SCK_PORT_DEF GPIOB
-#define RTE_SPI3_SCK_BIT_DEF 3
-#else
-#error "Invalid SPI3_SCK Pin Configuration!"
-#endif
-
-// SPI3_MISO Pin <0=>Not Used <1=>PB4
-#define RTE_SPI3_MISO_PORT_ID_DEF 0
-#if (RTE_SPI3_MISO_PORT_ID_DEF == 0)
-#define RTE_SPI3_MISO_DEF 0
-#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1)
-#define RTE_SPI3_MISO_DEF 1
-#define RTE_SPI3_MISO_PORT_DEF GPIOB
-#define RTE_SPI3_MISO_BIT_DEF 4
-#else
-#error "Invalid SPI3_MISO Pin Configuration!"
-#endif
-
-// SPI3_MOSI <0=>Not Used Pin <1=>PB5
-#define RTE_SPI3_MOSI_PORT_ID_DEF 0
-#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
-#define RTE_SPI3_MOSI_DEF 0
-#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
-#define RTE_SPI3_MOSI_DEF 1
-#define RTE_SPI3_MOSI_PORT_DEF GPIOB
-#define RTE_SPI3_MOSI_BIT_DEF 5
-#else
-#error "Invalid SPI3_MOSI Pin Configuration!"
-#endif
-
-// SPI3 Pin Remap
-// Enable SPI3 Pin Remapping.
-// SPI 3 Pin Remapping is available only in connectivity line devices!
-#define RTE_SPI3_REMAP 0
-
-// SPI3_SCK Pin <0=>PC10
-#define RTE_SPI3_SCK_PORT_ID_FULL 0
-#if (RTE_SPI3_SCK_PORT_ID_FULL == 0)
-#define RTE_SPI3_SCK_PORT_FULL GPIOC
-#define RTE_SPI3_SCK_BIT_FULL 10
-#else
-#error "Invalid SPI3_SCK Pin Configuration!"
-#endif
-
-// SPI3_MISO Pin <0=>Not Used <1=>PC11
-#define RTE_SPI3_MISO_PORT_ID_FULL 0
-#if (RTE_SPI3_MISO_PORT_ID_FULL == 0)
-#define RTE_SPI3_MISO_FULL 0
-#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1)
-#define RTE_SPI3_MISO_FULL 1
-#define RTE_SPI3_MISO_PORT_FULL GPIOC
-#define RTE_SPI3_MISO_BIT_FULL 11
-#else
-#error "Invalid SPI3_MISO Pin Configuration!"
-#endif
-// SPI3_MOSI Pin <0=>Not Used <1=>PC12
-#define RTE_SPI3_MOSI_PORT_ID_FULL 0
-#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
-#define RTE_SPI3_MOSI_FULL 0
-#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
-#define RTE_SPI3_MOSI_FULL 1
-#define RTE_SPI3_MOSI_PORT_FULL GPIOC
-#define RTE_SPI3_MOSI_BIT_FULL 12
-#else
-#error "Invalid SPI3_MOSI Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_SPI3_REMAP)
-#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP
-#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL
-#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL
-#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL
-#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL
-#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL
-#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL
-#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL
-#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL
-#else
-#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP
-#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF
-#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF
-#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF
-#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF
-#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF
-#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF
-#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF
-#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <1=>1
-// Selects DMA Channel (only Channel 1 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI3_RX_DMA 0
-#define RTE_SPI3_RX_DMA_NUMBER 2
-#define RTE_SPI3_RX_DMA_CHANNEL 1
-#define RTE_SPI3_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI3_TX_DMA 0
-#define RTE_SPI3_TX_DMA_NUMBER 2
-#define RTE_SPI3_TX_DMA_CHANNEL 2
-#define RTE_SPI3_TX_DMA_PRIORITY 0
-
-//
-
-
-// SDIO (Secure Digital Input/Output) [Driver_MCI0]
-// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
-#define RTE_SDIO 0
-
-// SDIO Peripheral Bus
-// SDIO_CK Pin <0=>PC12
-#define RTE_SDIO_CK_PORT_ID 0
-#if (RTE_SDIO_CK_PORT_ID == 0)
- #define RTE_SDIO_CK_PORT GPIOC
- #define RTE_SDIO_CK_PIN 12
-#else
- #error "Invalid SDIO_CLK Pin Configuration!"
-#endif
-// SDIO_CMD Pin <0=>PD2
-#define RTE_SDIO_CMD_PORT_ID 0
-#if (RTE_SDIO_CMD_PORT_ID == 0)
- #define RTE_SDIO_CMD_PORT GPIOD
- #define RTE_SDIO_CMD_PIN 2
-#else
- #error "Invalid SDIO_CMD Pin Configuration!"
-#endif
-// SDIO_D0 Pin <0=>PC8
-#define RTE_SDIO_D0_PORT_ID 0
-#if (RTE_SDIO_D0_PORT_ID == 0)
- #define RTE_SDIO_D0_PORT GPIOC
- #define RTE_SDIO_D0_PIN 8
-#else
- #error "Invalid SDIO_DAT0 Pin Configuration!"
-#endif
-// SDIO_D[1 .. 3]
-#define RTE_SDIO_BUS_WIDTH_4 1
-// SDIO_D1 Pin <0=>PC9
-#define RTE_SDIO_D1_PORT_ID 0
-#if (RTE_SDIO_D1_PORT_ID == 0)
- #define RTE_SDIO_D1_PORT GPIOC
- #define RTE_SDIO_D1_PIN 9
-#else
- #error "Invalid SDIO_D1 Pin Configuration!"
-#endif
-// SDIO_D2 Pin <0=>PC10
-#define RTE_SDIO_D2_PORT_ID 0
-#if (RTE_SDIO_D2_PORT_ID == 0)
- #define RTE_SDIO_D2_PORT GPIOC
- #define RTE_SDIO_D2_PIN 10
-#else
- #error "Invalid SDIO_D2 Pin Configuration!"
-#endif
-// SDIO_D3 Pin <0=>PC11
-#define RTE_SDIO_D3_PORT_ID 0
-#if (RTE_SDIO_D3_PORT_ID == 0)
- #define RTE_SDIO_D3_PORT GPIOC
- #define RTE_SDIO_D3_PIN 11
-#else
- #error "Invalid SDIO_D3 Pin Configuration!"
-#endif
-// SDIO_D[1 .. 3]
-// SDIO_D[4 .. 7]
-#define RTE_SDIO_BUS_WIDTH_8 0
-// SDIO_D4 Pin <0=>PB8
-#define RTE_SDIO_D4_PORT_ID 0
-#if (RTE_SDIO_D4_PORT_ID == 0)
- #define RTE_SDIO_D4_PORT GPIOB
- #define RTE_SDIO_D4_PIN 8
-#else
- #error "Invalid SDIO_D4 Pin Configuration!"
-#endif
-// SDIO_D5 Pin <0=>PB9
-#define RTE_SDIO_D5_PORT_ID 0
-#if (RTE_SDIO_D5_PORT_ID == 0)
- #define RTE_SDIO_D5_PORT GPIOB
- #define RTE_SDIO_D5_PIN 9
-#else
- #error "Invalid SDIO_D5 Pin Configuration!"
-#endif
-// SDIO_D6 Pin <0=>PC6
-#define RTE_SDIO_D6_PORT_ID 0
-#if (RTE_SDIO_D6_PORT_ID == 0)
- #define RTE_SDIO_D6_PORT GPIOC
- #define RTE_SDIO_D6_PIN 6
-#else
- #error "Invalid SDIO_D6 Pin Configuration!"
-#endif
-// SDIO_D7 Pin <0=>PC7
-#define RTE_SDIO_D7_PORT_ID 0
-#if (RTE_SDIO_D7_PORT_ID == 0)
- #define RTE_SDIO_D7_PORT GPIOC
- #define RTE_SDIO_D7_PIN 7
-#else
- #error "Invalid SDIO_D7 Pin Configuration!"
-#endif
-// SDIO_D[4 .. 7]
-// SDIO Peripheral Bus
-
-// Card Detect Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SDIO_CD_EN 1
-#define RTE_SDIO_CD_ACTIVE 0
-#define RTE_SDIO_CD_PORT GPIO_PORT(5)
-#define RTE_SDIO_CD_PIN 11
-
-// Write Protect Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SDIO_WP_EN 0
-#define RTE_SDIO_WP_ACTIVE 1
-#define RTE_SDIO_WP_PORT GPIO_PORT(0)
-#define RTE_SDIO_WP_PIN 10
-
-// DMA
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SDIO_DMA_NUMBER 2
-#define RTE_SDIO_DMA_CHANNEL 4
-#define RTE_SDIO_DMA_PRIORITY 0
-
-//
-
-
-// CAN1 (Controller Area Network 1) [Driver_CAN1]
-// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
-#define RTE_CAN1 0
-
-// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
-#define RTE_CAN1_RX_PORT_ID 0
-#if (RTE_CAN1_RX_PORT_ID == 0)
-#define RTE_CAN1_RX_PORT GPIOA
-#define RTE_CAN1_RX_BIT 11
-#elif (RTE_CAN1_RX_PORT_ID == 1)
-#define RTE_CAN1_RX_PORT GPIOB
-#define RTE_CAN1_RX_BIT 8
-#elif (RTE_CAN1_RX_PORT_ID == 2)
-#define RTE_CAN1_RX_PORT GPIOD
-#define RTE_CAN1_RX_BIT 0
-#else
-#error "Invalid CAN1_RX Pin Configuration!"
-#endif
-
-// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
-#define RTE_CAN1_TX_PORT_ID 0
-#if (RTE_CAN1_TX_PORT_ID == 0)
-#define RTE_CAN1_TX_PORT GPIOA
-#define RTE_CAN1_TX_BIT 12
-#elif (RTE_CAN1_TX_PORT_ID == 1)
-#define RTE_CAN1_TX_PORT GPIOB
-#define RTE_CAN1_TX_BIT 9
-#elif (RTE_CAN1_TX_PORT_ID == 2)
-#define RTE_CAN1_TX_PORT GPIOD
-#define RTE_CAN1_TX_BIT 1
-#else
-#error "Invalid CAN1_TX Pin Configuration!"
-#endif
-
-//
-
-
-// CAN2 (Controller Area Network 2) [Driver_CAN2]
-// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
-#define RTE_CAN2 0
-
-// CAN2_RX Pin <0=>PB5 <1=>PB12
-#define RTE_CAN2_RX_PORT_ID 0
-#if (RTE_CAN2_RX_PORT_ID == 0)
-#define RTE_CAN2_RX_PORT GPIOB
-#define RTE_CAN2_RX_BIT 5
-#elif (RTE_CAN2_RX_PORT_ID == 1)
-#define RTE_CAN2_RX_PORT GPIOB
-#define RTE_CAN2_RX_BIT 12
-#else
-#error "Invalid CAN2_RX Pin Configuration!"
-#endif
-
-// CAN2_TX Pin <0=>PB6 <1=>PB13
-#define RTE_CAN2_TX_PORT_ID 0
-#if (RTE_CAN2_TX_PORT_ID == 0)
-#define RTE_CAN2_TX_PORT GPIOB
-#define RTE_CAN2_TX_BIT 6
-#elif (RTE_CAN2_TX_PORT_ID == 1)
-#define RTE_CAN2_TX_PORT GPIOB
-#define RTE_CAN2_TX_BIT 13
-#else
-#error "Invalid CAN2_TX Pin Configuration!"
-#endif
-
-//
-
-
-// ETH (Ethernet Interface) [Driver_ETH_MAC0]
-// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
-#define RTE_ETH 0
-
-// MII (Media Independent Interface)
-// Enable Media Independent Interface pin configuration
-#define RTE_ETH_MII 0
-
-// ETH_MII_TX_CLK Pin <0=>PC3
-#define RTE_ETH_MII_TX_CLK_PORT_ID 0
-#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
-#define RTE_ETH_MII_TX_CLK_PORT GPIOC
-#define RTE_ETH_MII_TX_CLK_PIN 3
-#else
-#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
-#endif
-// ETH_MII_TXD0 Pin <0=>PB12
-#define RTE_ETH_MII_TXD0_PORT_ID 0
-#if (RTE_ETH_MII_TXD0_PORT_ID == 0)
-#define RTE_ETH_MII_TXD0_PORT GPIOB
-#define RTE_ETH_MII_TXD0_PIN 12
-#else
-#error "Invalid ETH_MII_TXD0 Pin Configuration!"
-#endif
-// ETH_MII_TXD1 Pin <0=>PB13
-#define RTE_ETH_MII_TXD1_PORT_ID 0
-#if (RTE_ETH_MII_TXD1_PORT_ID == 0)
-#define RTE_ETH_MII_TXD1_PORT GPIOB
-#define RTE_ETH_MII_TXD1_PIN 13
-#else
-#error "Invalid ETH_MII_TXD1 Pin Configuration!"
-#endif
-// ETH_MII_TXD2 Pin <0=>PC2
-#define RTE_ETH_MII_TXD2_PORT_ID 0
-#if (RTE_ETH_MII_TXD2_PORT_ID == 0)
-#define RTE_ETH_MII_TXD2_PORT GPIOC
-#define RTE_ETH_MII_TXD2_PIN 2
-#else
-#error "Invalid ETH_MII_TXD2 Pin Configuration!"
-#endif
-// ETH_MII_TXD3 Pin <0=>PB8
-#define RTE_ETH_MII_TXD3_PORT_ID 0
-#if (RTE_ETH_MII_TXD3_PORT_ID == 0)
-#define RTE_ETH_MII_TXD3_PORT GPIOB
-#define RTE_ETH_MII_TXD3_PIN 8
-#else
-#error "Invalid ETH_MII_TXD3 Pin Configuration!"
-#endif
-// ETH_MII_TX_EN Pin <0=>PB11
-#define RTE_ETH_MII_TX_EN_PORT_ID 0
-#if (RTE_ETH_MII_TX_EN_PORT_ID == 0)
-#define RTE_ETH_MII_TX_EN_PORT GPIOB
-#define RTE_ETH_MII_TX_EN_PIN 11
-#else
-#error "Invalid ETH_MII_TX_EN Pin Configuration!"
-#endif
-// ETH_MII_RX_CLK Pin <0=>PA1
-#define RTE_ETH_MII_RX_CLK_PORT_ID 0
-#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
-#define RTE_ETH_MII_RX_CLK_PORT GPIOA
-#define RTE_ETH_MII_RX_CLK_PIN 1
-#else
-#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
-#endif
-// ETH_MII_RXD0 Pin <0=>PC4
-#define RTE_ETH_MII_RXD0_DEF 0
-
-// ETH_MII_RXD1 Pin <0=>PC5
-#define RTE_ETH_MII_RXD1_DEF 0
-
-// ETH_MII_RXD2 Pin <0=>PB0
-#define RTE_ETH_MII_RXD2_DEF 0
-
-// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
-#define RTE_ETH_MII_RXD3_DEF 0
-
-// ETH_MII_RX_DV Pin <0=>PA7
-#define RTE_ETH_MII_RX_DV_DEF 0
-
-// ETH_MII_RX_ER Pin <0=>PB10
-#define RTE_ETH_MII_RX_ER_PORT_ID 0
-#if (RTE_ETH_MII_RX_ER_PORT_ID == 0)
-#define RTE_ETH_MII_RX_ER_PORT GPIOB
-#define RTE_ETH_MII_RX_ER_PIN 10
-#else
-#error "Invalid ETH_MII_RX_ER Pin Configuration!"
-#endif
-// ETH_MII_CRS Pin <0=>PA0
-#define RTE_ETH_MII_CRS_PORT_ID 0
-#if (RTE_ETH_MII_CRS_PORT_ID == 0)
-#define RTE_ETH_MII_CRS_PORT GPIOA
-#define RTE_ETH_MII_CRS_PIN 0
-#else
-#error "Invalid ETH_MII_CRS Pin Configuration!"
-#endif
-// ETH_MII_COL Pin <0=>PA3
-#define RTE_ETH_MII_COL_PORT_ID 0
-#if (RTE_ETH_MII_COL_PORT_ID == 0)
-#define RTE_ETH_MII_COL_PORT GPIOA
-#define RTE_ETH_MII_COL_PIN 3
-#else
-#error "Invalid ETH_MII_COL Pin Configuration!"
-#endif
-
-// Ethernet MAC I/O remapping
-// Remap Ethernet pins
-#define RTE_ETH_MII_REMAP 0
-
-// ETH_MII_RXD0 Pin <1=>PD9
-#define RTE_ETH_MII_RXD0_REMAP 1
-
-// ETH_MII_RXD1 Pin <1=>PD10
-#define RTE_ETH_MII_RXD1_REMAP 1
-
-// ETH_MII_RXD2 Pin <1=>PD11
-#define RTE_ETH_MII_RXD2_REMAP 1
-
-// ETH_MII_RXD3 Pin <1=>PD12
-#define RTE_ETH_MII_RXD3_REMAP 1
-
-// ETH_MII_RX_DV Pin <1=>PD8
-#define RTE_ETH_MII_RX_DV_REMAP 1
-//
-
-//
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
-#define RTE_ETH_MII_RXD0_PORT GPIOC
-#define RTE_ETH_MII_RXD0_PIN 4
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
-#define RTE_ETH_MII_RXD0_PORT GPIOD
-#define RTE_ETH_MII_RXD0_PIN 9
-#else
-#error "Invalid ETH_MII_RXD0 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
-#define RTE_ETH_MII_RXD1_PORT GPIOC
-#define RTE_ETH_MII_RXD1_PIN 5
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
-#define RTE_ETH_MII_RXD1_PORT GPIOD
-#define RTE_ETH_MII_RXD1_PIN 10
-#else
-#error "Invalid ETH_MII_RXD1 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
-#define RTE_ETH_MII_RXD2_PORT GPIOB
-#define RTE_ETH_MII_RXD2_PIN 0
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
-#define RTE_ETH_MII_RXD2_PORT GPIOD
-#define RTE_ETH_MII_RXD2_PIN 11
-#else
-#error "Invalid ETH_MII_RXD2 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
-#define RTE_ETH_MII_RXD3_PORT GPIOB
-#define RTE_ETH_MII_RXD3_PIN 1
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
-#define RTE_ETH_MII_RXD3_PORT GPIOD
-#define RTE_ETH_MII_RXD3_PIN 12
-#else
-#error "Invalid ETH_MII_RXD3 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
-#define RTE_ETH_MII_RX_DV_PORT GPIOA
-#define RTE_ETH_MII_RX_DV_PIN 7
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
-#define RTE_ETH_MII_RX_DV_PORT GPIOD
-#define RTE_ETH_MII_RX_DV_PIN 8
-#else
-#error "Invalid ETH_MII_RX_DV Pin Configuration!"
-#endif
-
-// RMII (Reduced Media Independent Interface)
-#define RTE_ETH_RMII 0
-
-// ETH_RMII_TXD0 Pin <0=>PB12
-#define RTE_ETH_RMII_TXD0_PORT_ID 0
-#if (RTE_ETH_RMII_TXD0_PORT_ID == 0)
-#define RTE_ETH_RMII_TXD0_PORT GPIOB
-#define RTE_ETH_RMII_TXD0_PIN 12
-#else
-#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
-#endif
-// ETH_RMII_TXD1 Pin <0=>PB13
-#define RTE_ETH_RMII_TXD1_PORT_ID 0
-#if (RTE_ETH_RMII_TXD1_PORT_ID == 0)
-#define RTE_ETH_RMII_TXD1_PORT GPIOB
-#define RTE_ETH_RMII_TXD1_PIN 13
-#else
-#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
-#endif
-// ETH_RMII_TX_EN Pin <0=>PB11
-#define RTE_ETH_RMII_TX_EN_PORT_ID 0
-#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
-#define RTE_ETH_RMII_TX_EN_PORT GPIOB
-#define RTE_ETH_RMII_TX_EN_PIN 11
-#else
-#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
-#endif
-// ETH_RMII_RXD0 Pin <0=>PC4
-#define RTE_ETH_RMII_RXD0_DEF 0
-
-// ETH_RMII_RXD1 Pin <0=>PC5
-#define RTE_ETH_RMII_RXD1_DEF 0
-
-// ETH_RMII_REF_CLK Pin <0=>PA1
-#define RTE_ETH_RMII_REF_CLK_PORT_ID 0
-#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
-#define RTE_ETH_RMII_REF_CLK_PORT GPIOA
-#define RTE_ETH_RMII_REF_CLK_PIN 1
-#else
-#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
-#endif
-// ETH_RMII_CRS_DV Pin <0=>PA7
-#define RTE_ETH_RMII_CRS_DV_DEF 0
-
-// Ethernet MAC I/O remapping
-// Remap Ethernet pins
-#define RTE_ETH_RMII_REMAP 0
-// ETH_RMII_RXD0 Pin <1=>PD9
-#define RTE_ETH_RMII_RXD0_REMAP 1
-
-// ETH_RMII_RXD1 Pin <1=>PD10
-#define RTE_ETH_RMII_RXD1_REMAP 1
-
-// ETH_RMII_CRS_DV Pin <1=>PD8
-#define RTE_ETH_RMII_CRS_DV_REMAP 1
-//
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
-#define RTE_ETH_RMII_RXD0_PORT GPIOC
-#define RTE_ETH_RMII_RXD0_PIN 4
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
-#define RTE_ETH_RMII_RXD0_PORT GPIOD
-#define RTE_ETH_RMII_RXD0_PIN 9
-#else
-#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
-#define RTE_ETH_RMII_RXD1_PORT GPIOC
-#define RTE_ETH_RMII_RXD1_PIN 5
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
-#define RTE_ETH_RMII_RXD1_PORT GPIOD
-#define RTE_ETH_RMII_RXD1_PIN 10
-#else
-#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
-#define RTE_ETH_RMII_CRS_DV_PORT GPIOA
-#define RTE_ETH_RMII_CRS_DV_PIN 7
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
-#define RTE_ETH_RMII_CRS_DV_PORT GPIOD
-#define RTE_ETH_RMII_CRS_DV_PIN 8
-#else
-#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
-#endif
-
-//
-
-// Management Data Interface
-// ETH_MDC Pin <0=>PC1
-#define RTE_ETH_MDI_MDC_PORT_ID 0
-#if (RTE_ETH_MDI_MDC_PORT_ID == 0)
-#define RTE_ETH_MDI_MDC_PORT GPIOC
-#define RTE_ETH_MDI_MDC_PIN 1
-#else
-#error "Invalid ETH_MDC Pin Configuration!"
-#endif
-// ETH_MDIO Pin <0=>PA2
-#define RTE_ETH_MDI_MDIO_PORT_ID 0
-#if (RTE_ETH_MDI_MDIO_PORT_ID == 0)
-#define RTE_ETH_MDI_MDIO_PORT GPIOA
-#define RTE_ETH_MDI_MDIO_PIN 2
-#else
-#error "Invalid ETH_MDIO Pin Configuration!"
-#endif
-//
-
-// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
-#define RTE_ETH_REF_CLOCK_ID 0
-#if (RTE_ETH_REF_CLOCK_ID == 0)
-#define RTE_ETH_REF_CLOCK 0
-#elif (RTE_ETH_REF_CLOCK_ID == 1)
-#define RTE_ETH_REF_CLOCK 1
-#else
-#error "Invalid MCO Ethernet Reference Clock Configuration!"
-#endif
-//
-
-
-// USB Device Full-speed
-// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
-#define RTE_USB_DEVICE 0
-
-// CON On/Off Pin
-// Configure Pin for driving D+ pull-up
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_USB_DEVICE_CON_PIN 1
-#define RTE_USB_DEVICE_CON_ACTIVE 0
-#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1)
-#define RTE_USB_DEVICE_CON_BIT 14
-
-//
-
-
-// USB OTG Full-speed
-#define RTE_USB_OTG_FS 0
-
-// Host [Driver_USBH0]
-// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
-
-#define RTE_USB_OTG_FS_HOST 0
-
-// VBUS Power On/Off Pin
-// Configure Pin for driving VBUS
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_OTG_FS_VBUS_PIN 1
-#define RTE_OTG_FS_VBUS_ACTIVE 0
-#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2)
-#define RTE_OTG_FS_VBUS_BIT 9
-
-// Overcurrent Detection Pin
-// Configure Pin for overcurrent detection
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_OTG_FS_OC_PIN 1
-#define RTE_OTG_FS_OC_ACTIVE 0
-#define RTE_OTG_FS_OC_PORT GPIO_PORT(4)
-#define RTE_OTG_FS_OC_BIT 1
-//
-
-//
-
-
-#endif /* __RTE_DEVICE_H */
diff --git a/bateau-microcontrolleur/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/bateau-microcontrolleur/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
deleted file mode 100644
index 74da96c..0000000
--- a/bateau-microcontrolleur/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
+++ /dev/null
@@ -1,307 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name : startup_stm32f10x_md.s
-;* Author : MCD Application Team
-;* Version : V3.5.0
-;* Date : 11-March-2011
-;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
-;* toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the clock system
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1_2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
- DCD TIM1_BRK_IRQHandler ; TIM1 Break
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_IRQHandler [WEAK]
- EXPORT TIM1_UP_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bateau-microcontrolleur/RTE/Device/STM32F103RB/system_stm32f10x.c b/bateau-microcontrolleur/RTE/Device/STM32F103RB/system_stm32f10x.c
deleted file mode 100644
index 71efc85..0000000
--- a/bateau-microcontrolleur/RTE/Device/STM32F103RB/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f10x.c
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * factors, AHB/APBx prescalers and Flash settings).
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f10x_xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
- * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
- * When HSE is used as system clock source, directly or through PLL, and you
- * are using different crystal you have to adapt the HSE value to your own
- * configuration.
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * © COPYRIGHT 2011 STMicroelectronics
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f10x_system
- * @{
- */
-
-/** @addtogroup STM32F10x_System_Private_Includes
- * @{
- */
-
-#include "stm32f10x.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
- frequency (after reset the HSI is used as SYSCLK source)
-
- IMPORTANT NOTE:
- ==============
- 1. After each device reset the HSI is used as System clock source.
-
- 2. Please make sure that the selected System clock doesn't exceed your device's
- maximum frequency.
-
- 3. If none of the define below is enabled, the HSI is used as System clock
- source.
-
- 4. The System clock configuration functions provided within this file assume that:
- - For Low, Medium and High density Value line devices an external 8MHz
- crystal is used to drive the System clock.
- - For Low, Medium and High density devices an external 8MHz crystal is
- used to drive the System clock.
- - For Connectivity line devices an external 25MHz crystal is used to drive
- the System clock.
- If you are using different crystal you have to adapt those functions accordingly.
- */
-
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
- #define SYSCLK_FREQ_24MHz 24000000
-#else
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz 24000000 */
-/* #define SYSCLK_FREQ_36MHz 36000000 */
-/* #define SYSCLK_FREQ_48MHz 48000000 */
-/* #define SYSCLK_FREQ_56MHz 56000000 */
-#define SYSCLK_FREQ_72MHz 72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
- STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Variables
- * @{
- */
-
-/*******************************************************************************
-* Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
- uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
- uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
- static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
- static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
- static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
- static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
- static void SetSysClockTo56(void);
-#elif defined SYSCLK_FREQ_72MHz
- static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
- RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
- RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
- /* Reset PLL2ON and PLL3ON bits */
- RCC->CR &= (uint32_t)0xEBFFFFFF;
-
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x00FF0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#else
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
- #ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
- #endif /* DATA_IN_ExtSRAM */
-#endif
-
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
- /* Configure the Flash Latency cycles and enable prefetch buffer */
- SetSysClock();
-
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
- * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
- * that HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef STM32F10X_CL
- uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
-
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-#ifndef STM32F10X_CL
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- #else
- /* HSE selected as PLL clock entry */
- if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
- {/* HSE oscillator clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
- }
- else
- {
- SystemCoreClock = HSE_VALUE * pllmull;
- }
- #endif
- }
-#else
- pllmull = pllmull >> 18;
-
- if (pllmull != 0x0D)
- {
- pllmull += 2;
- }
- else
- { /* PLL multiplication factor = PLL input clock * 6.5 */
- pllmull = 13 / 2;
- }
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {/* PREDIV1 selected as PLL clock entry */
-
- /* Get PREDIV1 clock source and division factor */
- prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-
- if (prediv1source == 0)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- else
- {/* PLL2 clock selected as PREDIV1 clock entry */
-
- /* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
- SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
- }
- }
-#endif /* STM32F10X_CL */
- break;
-
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
-
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
- SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
- SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
- SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
- SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
- SetSysClockTo56();
-#elif defined SYSCLK_FREQ_72MHz
- SetSysClockTo72();
-#endif
-
- /* If none of the define above is enabled, the HSI is used as System clock
- source (default after reset) */
-}
-
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f10x.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f10x_xx.s/.c before jump to main.
- * This function configures the external SRAM mounted on STM3210E-EVAL
- * board (STM32 High density devices). This SRAM will be used as program
- * data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
- required, then adjust the Register Addresses */
-
- /* Enable FSMC clock */
- RCC->AHBENR = 0x00000114;
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- RCC->APB2ENR = 0x000001E0;
-
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
-/*---------------- SRAM Address lines configuration -------------------------*/
-/*---------------- NOE and NWE configuration --------------------------------*/
-/*---------------- NE3 configuration ----------------------------------------*/
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- GPIOD->CRL = 0x44BB44BB;
- GPIOD->CRH = 0xBBBBBBBB;
-
- GPIOE->CRL = 0xB44444BB;
- GPIOE->CRH = 0xBBBBBBBB;
-
- GPIOF->CRL = 0x44BBBBBB;
- GPIOF->CRH = 0xBBBB4444;
-
- GPIOG->CRL = 0x44BBBBBB;
- GPIOG->CRH = 0x44444B44;
-
-/*---------------- FSMC Configuration ---------------------------------------*/
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
-
- FSMC_Bank1->BTCR[4] = 0x00001011;
- FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSE(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
- if (HSE_VALUE <= 24000000)
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
- }
- else
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
- }
-#endif /* STM32F10X_CL */
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo24(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo36(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-
- /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-#else
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo56(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL7);
-#else
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-#else
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
- RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bateau-microcontrolleur/RTE/_CarteSTM/RTE_Components.h b/bateau-microcontrolleur/RTE/_CarteSTM/RTE_Components.h
deleted file mode 100644
index 173899d..0000000
--- a/bateau-microcontrolleur/RTE/_CarteSTM/RTE_Components.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'hello_world'
- * Target: 'CarteSTM'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "stm32f10x.h"
-
-
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/bateau-microcontrolleur/RTE/_Simulation/RTE_Components.h b/bateau-microcontrolleur/RTE/_Simulation/RTE_Components.h
deleted file mode 100644
index 79ef10f..0000000
--- a/bateau-microcontrolleur/RTE/_Simulation/RTE_Components.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'hello_world'
- * Target: 'Simulation'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "stm32f10x.h"
-
-
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/bateau-microcontrolleur/RTE/_Target_1/RTE_Components.h b/bateau-microcontrolleur/RTE/_Target_1/RTE_Components.h
deleted file mode 100644
index 0f377a5..0000000
--- a/bateau-microcontrolleur/RTE/_Target_1/RTE_Components.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'hello_world'
- * Target: 'Target 1'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "stm32f10x.h"
-
-
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/driver_premier_test/Listings/driver_premier_test.map b/driver_premier_test/Listings/driver_premier_test.map
deleted file mode 100644
index a734071..0000000
--- a/driver_premier_test/Listings/driver_premier_test.map
+++ /dev/null
@@ -1,336 +0,0 @@
-Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]
-
-==============================================================================
-
-Section Cross References
-
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Activate) for MyGPIO_Activate
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Read) for MyGPIO_Read
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Reset) for MyGPIO_Reset
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Set) for MyGPIO_Set
- driver_gpio.o(i.MyGPIO_Init) refers to driver_gpio.o(i.MyGPIO_Set) for MyGPIO_Set
- driver_gpio.o(i.MyGPIO_Toggle) refers to driver_gpio.o(i.MyGPIO_Reset) for MyGPIO_Reset
- driver_gpio.o(i.MyGPIO_Toggle) refers to driver_gpio.o(i.MyGPIO_Set) for MyGPIO_Set
- startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler
- startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
- startup_stm32f10x_md.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
- system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72
- system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock
- system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000F) for __rt_final_cpp
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$00000011) for __rt_final_exit
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry12b.o(.ARM.Collect$$$$0000000E) for __rt_lib_shutdown_fini
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
- entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
- entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
- entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
- entry9a.o(.ARM.Collect$$$$0000000B) refers to principal.o(i.main) for main
- entry9b.o(.ARM.Collect$$$$0000000C) refers to principal.o(i.main) for main
- init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
-
-
-==============================================================================
-
-Removing Unused input sections from the image.
-
- Removing principal.o(.rev16_text), (4 bytes).
- Removing principal.o(.revsh_text), (4 bytes).
- Removing principal.o(.rrx_text), (6 bytes).
- Removing driver_gpio.o(.rev16_text), (4 bytes).
- Removing driver_gpio.o(.revsh_text), (4 bytes).
- Removing driver_gpio.o(.rrx_text), (6 bytes).
- Removing driver_gpio.o(i.MyGPIO_Toggle), (36 bytes).
- Removing startup_stm32f10x_md.o(HEAP), (512 bytes).
- Removing system_stm32f10x.o(.rev16_text), (4 bytes).
- Removing system_stm32f10x.o(.revsh_text), (4 bytes).
- Removing system_stm32f10x.o(.rrx_text), (6 bytes).
- Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes).
- Removing system_stm32f10x.o(.data), (20 bytes).
-
-13 unused section(s) (total 774 bytes) removed from the image.
-
-==============================================================================
-
-Image Symbol Table
-
- Local Symbols
-
- Symbol Name Value Ov Type Size Object(Section)
-
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
- Includes\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE
- Includes\\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE
- RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE
- RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE
- RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE
- Source\\principal.c 0x00000000 Number 0 principal.o ABSOLUTE
- Source\principal.c 0x00000000 Number 0 principal.o ABSOLUTE
- dc.s 0x00000000 Number 0 dc.o ABSOLUTE
- handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE
- init.s 0x00000000 Number 0 init.o ABSOLUTE
- RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET)
- .ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000)
- .ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001)
- .ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004)
- .ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008)
- .ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A)
- .ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B)
- .ARM.Collect$$$$0000000E 0x080000fc Section 4 entry12b.o(.ARM.Collect$$$$0000000E)
- .ARM.Collect$$$$0000000F 0x08000100 Section 0 entry10a.o(.ARM.Collect$$$$0000000F)
- .ARM.Collect$$$$00000011 0x08000100 Section 0 entry11a.o(.ARM.Collect$$$$00000011)
- .ARM.Collect$$$$00002712 0x08000100 Section 4 entry2.o(.ARM.Collect$$$$00002712)
- __lit__00000000 0x08000100 Data 4 entry2.o(.ARM.Collect$$$$00002712)
- .text 0x08000104 Section 36 startup_stm32f10x_md.o(.text)
- .text 0x08000128 Section 36 init.o(.text)
- i.MyGPIO_Activate 0x0800014c Section 0 driver_gpio.o(i.MyGPIO_Activate)
- i.MyGPIO_Init 0x08000164 Section 0 driver_gpio.o(i.MyGPIO_Init)
- i.MyGPIO_Read 0x08000250 Section 0 driver_gpio.o(i.MyGPIO_Read)
- i.MyGPIO_Reset 0x0800025c Section 0 driver_gpio.o(i.MyGPIO_Reset)
- i.MyGPIO_Set 0x08000268 Section 0 driver_gpio.o(i.MyGPIO_Set)
- i.SetSysClock 0x08000270 Section 0 system_stm32f10x.o(i.SetSysClock)
- SetSysClock 0x08000271 Thumb Code 8 system_stm32f10x.o(i.SetSysClock)
- i.SetSysClockTo72 0x08000278 Section 0 system_stm32f10x.o(i.SetSysClockTo72)
- SetSysClockTo72 0x08000279 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72)
- i.SystemInit 0x08000358 Section 0 system_stm32f10x.o(i.SystemInit)
- i.__scatterload_copy 0x080003b8 Section 14 handlers.o(i.__scatterload_copy)
- i.__scatterload_null 0x080003c6 Section 2 handlers.o(i.__scatterload_null)
- i.__scatterload_zeroinit 0x080003c8 Section 14 handlers.o(i.__scatterload_zeroinit)
- i.main 0x080003d8 Section 0 principal.o(i.main)
- STACK 0x20000000 Section 1024 startup_stm32f10x_md.o(STACK)
-
- Global Symbols
-
- Symbol Name Value Ov Type Size Object(Section)
-
- BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
- __ARM_use_no_argv 0x00000000 Number 0 principal.o ABSOLUTE
- __arm_fini_ - Undefined Weak Reference
- __cpp_initialize__aeabi_ - Undefined Weak Reference
- __cxa_finalize - Undefined Weak Reference
- __decompress - Undefined Weak Reference
- _clock_init - Undefined Weak Reference
- _microlib_exit - Undefined Weak Reference
- __Vectors_Size 0x000000ec Number 0 startup_stm32f10x_md.o ABSOLUTE
- __Vectors 0x08000000 Data 4 startup_stm32f10x_md.o(RESET)
- __Vectors_End 0x080000ec Data 0 startup_stm32f10x_md.o(RESET)
- __main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000)
- _main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001)
- _main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
- __main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
- _main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008)
- _main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A)
- _main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B)
- __rt_lib_shutdown_fini 0x080000fd Thumb Code 0 entry12b.o(.ARM.Collect$$$$0000000E)
- __rt_final_cpp 0x08000101 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000F)
- __rt_final_exit 0x08000101 Thumb Code 0 entry11a.o(.ARM.Collect$$$$00000011)
- Reset_Handler 0x08000105 Thumb Code 8 startup_stm32f10x_md.o(.text)
- NMI_Handler 0x0800010d Thumb Code 2 startup_stm32f10x_md.o(.text)
- HardFault_Handler 0x0800010f Thumb Code 2 startup_stm32f10x_md.o(.text)
- MemManage_Handler 0x08000111 Thumb Code 2 startup_stm32f10x_md.o(.text)
- BusFault_Handler 0x08000113 Thumb Code 2 startup_stm32f10x_md.o(.text)
- UsageFault_Handler 0x08000115 Thumb Code 2 startup_stm32f10x_md.o(.text)
- SVC_Handler 0x08000117 Thumb Code 2 startup_stm32f10x_md.o(.text)
- DebugMon_Handler 0x08000119 Thumb Code 2 startup_stm32f10x_md.o(.text)
- PendSV_Handler 0x0800011b Thumb Code 2 startup_stm32f10x_md.o(.text)
- SysTick_Handler 0x0800011d Thumb Code 2 startup_stm32f10x_md.o(.text)
- ADC1_2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- CAN1_RX1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- CAN1_SCE_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel6_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel7_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI15_10_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI9_5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- FLASH_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C1_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C1_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C2_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C2_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- PVD_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RCC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RTCAlarm_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RTC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- SPI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- SPI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TAMPER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_BRK_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_CC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_TRG_COM_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_UP_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USBWakeUp_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USB_HP_CAN1_TX_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USB_LP_CAN1_RX0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- WWDG_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- __scatterload 0x08000129 Thumb Code 28 init.o(.text)
- __scatterload_rt2 0x08000129 Thumb Code 0 init.o(.text)
- MyGPIO_Activate 0x0800014d Thumb Code 18 driver_gpio.o(i.MyGPIO_Activate)
- MyGPIO_Init 0x08000165 Thumb Code 236 driver_gpio.o(i.MyGPIO_Init)
- MyGPIO_Read 0x08000251 Thumb Code 12 driver_gpio.o(i.MyGPIO_Read)
- MyGPIO_Reset 0x0800025d Thumb Code 12 driver_gpio.o(i.MyGPIO_Reset)
- MyGPIO_Set 0x08000269 Thumb Code 8 driver_gpio.o(i.MyGPIO_Set)
- SystemInit 0x08000359 Thumb Code 78 system_stm32f10x.o(i.SystemInit)
- __scatterload_copy 0x080003b9 Thumb Code 14 handlers.o(i.__scatterload_copy)
- __scatterload_null 0x080003c7 Thumb Code 2 handlers.o(i.__scatterload_null)
- __scatterload_zeroinit 0x080003c9 Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
- main 0x080003d9 Thumb Code 96 principal.o(i.main)
- Region$$Table$$Base 0x08000440 Number 0 anon$$obj.o(Region$$Table)
- Region$$Table$$Limit 0x08000450 Number 0 anon$$obj.o(Region$$Table)
- __initial_sp 0x20000400 Data 0 startup_stm32f10x_md.o(STACK)
-
-
-
-==============================================================================
-
-Memory Map of the image
-
- Image Entry point : 0x08000105
-
- Load Region LR_1 (Base: 0x08000000, Size: 0x00000450, Max: 0xffffffff, ABSOLUTE)
-
- Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000450, Max: 0xffffffff, ABSOLUTE)
-
- Exec Addr Load Addr Size Type Attr Idx E Section Name Object
-
- 0x08000000 0x08000000 0x000000ec Data RO 119 RESET startup_stm32f10x_md.o
- 0x080000ec 0x080000ec 0x00000000 Code RO 170 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
- 0x080000ec 0x080000ec 0x00000004 Code RO 173 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
- 0x080000f0 0x080000f0 0x00000004 Code RO 176 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
- 0x080000f4 0x080000f4 0x00000000 Code RO 178 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
- 0x080000f4 0x080000f4 0x00000000 Code RO 180 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
- 0x080000f4 0x080000f4 0x00000008 Code RO 181 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
- 0x080000fc 0x080000fc 0x00000004 Code RO 188 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o)
- 0x08000100 0x08000100 0x00000000 Code RO 183 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o)
- 0x08000100 0x08000100 0x00000000 Code RO 185 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o)
- 0x08000100 0x08000100 0x00000004 Code RO 174 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
- 0x08000104 0x08000104 0x00000024 Code RO 120 * .text startup_stm32f10x_md.o
- 0x08000128 0x08000128 0x00000024 Code RO 189 .text mc_w.l(init.o)
- 0x0800014c 0x0800014c 0x00000018 Code RO 60 i.MyGPIO_Activate driver_gpio.o
- 0x08000164 0x08000164 0x000000ec Code RO 61 i.MyGPIO_Init driver_gpio.o
- 0x08000250 0x08000250 0x0000000c Code RO 62 i.MyGPIO_Read driver_gpio.o
- 0x0800025c 0x0800025c 0x0000000c Code RO 63 i.MyGPIO_Reset driver_gpio.o
- 0x08000268 0x08000268 0x00000008 Code RO 64 i.MyGPIO_Set driver_gpio.o
- 0x08000270 0x08000270 0x00000008 Code RO 127 i.SetSysClock system_stm32f10x.o
- 0x08000278 0x08000278 0x000000e0 Code RO 128 i.SetSysClockTo72 system_stm32f10x.o
- 0x08000358 0x08000358 0x00000060 Code RO 130 i.SystemInit system_stm32f10x.o
- 0x080003b8 0x080003b8 0x0000000e Code RO 193 i.__scatterload_copy mc_w.l(handlers.o)
- 0x080003c6 0x080003c6 0x00000002 Code RO 194 i.__scatterload_null mc_w.l(handlers.o)
- 0x080003c8 0x080003c8 0x0000000e Code RO 195 i.__scatterload_zeroinit mc_w.l(handlers.o)
- 0x080003d6 0x080003d6 0x00000002 PAD
- 0x080003d8 0x080003d8 0x00000068 Code RO 4 i.main principal.o
- 0x08000440 0x08000440 0x00000010 Data RO 191 Region$$Table anon$$obj.o
-
-
- Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000450, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE)
-
- **** No section assigned to this execution region ****
-
-
- Execution Region ER_ZI (Exec base: 0x20000000, Load base: 0x08000450, Size: 0x00000400, Max: 0xffffffff, ABSOLUTE)
-
- Exec Addr Load Addr Size Type Attr Idx E Section Name Object
-
- 0x20000000 - 0x00000400 Zero RW 117 STACK startup_stm32f10x_md.o
-
-
-==============================================================================
-
-Image component sizes
-
-
- Code (inc. data) RO Data RW Data ZI Data Debug Object Name
-
- 292 6 0 0 0 3798 driver_gpio.o
- 104 8 0 0 0 207571 principal.o
- 36 8 236 0 1024 868 startup_stm32f10x_md.o
- 328 28 0 0 0 2213 system_stm32f10x.o
-
- ----------------------------------------------------------------------
- 760 50 252 0 1024 214450 Object Totals
- 0 0 16 0 0 0 (incl. Generated)
- 0 0 0 0 0 0 (incl. Padding)
-
- ----------------------------------------------------------------------
-
- Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
-
- 0 0 0 0 0 0 entry.o
- 0 0 0 0 0 0 entry10a.o
- 0 0 0 0 0 0 entry11a.o
- 4 0 0 0 0 0 entry12b.o
- 8 4 0 0 0 0 entry2.o
- 4 0 0 0 0 0 entry5.o
- 0 0 0 0 0 0 entry7b.o
- 0 0 0 0 0 0 entry8b.o
- 8 4 0 0 0 0 entry9a.o
- 30 0 0 0 0 0 handlers.o
- 36 8 0 0 0 68 init.o
-
- ----------------------------------------------------------------------
- 92 16 0 0 0 68 Library Totals
- 2 0 0 0 0 0 (incl. Padding)
-
- ----------------------------------------------------------------------
-
- Code (inc. data) RO Data RW Data ZI Data Debug Library Name
-
- 90 16 0 0 0 68 mc_w.l
-
- ----------------------------------------------------------------------
- 92 16 0 0 0 68 Library Totals
-
- ----------------------------------------------------------------------
-
-==============================================================================
-
-
- Code (inc. data) RO Data RW Data ZI Data Debug
-
- 852 66 252 0 1024 214306 Grand Totals
- 852 66 252 0 1024 214306 ELF Image Totals
- 852 66 252 0 0 0 ROM Totals
-
-==============================================================================
-
- Total RO Size (Code + RO Data) 1104 ( 1.08kB)
- Total RW Size (RW Data + ZI Data) 1024 ( 1.00kB)
- Total ROM Size (Code + RO Data + RW Data) 1104 ( 1.08kB)
-
-==============================================================================
-
diff --git a/driver_premier_test/Listings/startup_stm32f10x_md.lst b/driver_premier_test/Listings/startup_stm32f10x_md.lst
deleted file mode 100644
index d0deafd..0000000
--- a/driver_premier_test/Listings/startup_stm32f10x_md.lst
+++ /dev/null
@@ -1,1181 +0,0 @@
-
-
-
-ARM Macro Assembler Page 1
-
-
- 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron
- ics ********************
- 2 00000000 ;* File Name : startup_stm32f10x_md.s
- 3 00000000 ;* Author : MCD Application Team
- 4 00000000 ;* Version : V3.5.0
- 5 00000000 ;* Date : 11-March-2011
- 6 00000000 ;* Description : STM32F10x Medium Density Devices
- vector table for MDK-ARM
- 7 00000000 ;* toolchain.
- 8 00000000 ;* This module performs:
- 9 00000000 ;* - Set the initial SP
- 10 00000000 ;* - Set the initial PC == Reset_Ha
- ndler
- 11 00000000 ;* - Set the vector table entries w
- ith the exceptions ISR address
- 12 00000000 ;* - Configure the clock system
- 13 00000000 ;* - Branches to __main in the C li
- brary (which eventually
- 14 00000000 ;* calls main()).
- 15 00000000 ;* After Reset the CortexM3 process
- or is in Thread mode,
- 16 00000000 ;* priority is Privileged, and the
- Stack is set to Main.
- 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
- 18 00000000 ;*******************************************************
- ************************
- 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A
- T PROVIDING CUSTOMERS
- 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR
- DER FOR THEM TO SAVE TIME.
- 21 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB
- LE FOR ANY DIRECT,
- 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
- CLAIMS ARISING FROM THE
- 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM
- ERS OF THE CODING
- 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR
- PRODUCTS.
- 25 00000000 ;*******************************************************
- ************************
- 26 00000000
- 27 00000000 ; Amount of memory (in bytes) allocated for Stack
- 28 00000000 ; Tailor this value to your application needs
- 29 00000000 ; Stack Configuration
- 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
- 31 00000000 ;
- 32 00000000
- 33 00000000 00000400
- Stack_Size
- EQU 0x00000400
- 34 00000000
- 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
-=3
- 36 00000000 Stack_Mem
- SPACE Stack_Size
- 37 00000400 __initial_sp
- 38 00000400
- 39 00000400
- 40 00000400 ; Heap Configuration
-
-
-
-ARM Macro Assembler Page 2
-
-
- 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
- 42 00000400 ;
- 43 00000400
- 44 00000400 00000200
- Heap_Size
- EQU 0x00000200
- 45 00000400
- 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
-3
- 47 00000000 __heap_base
- 48 00000000 Heap_Mem
- SPACE Heap_Size
- 49 00000200 __heap_limit
- 50 00000200
- 51 00000200 PRESERVE8
- 52 00000200 THUMB
- 53 00000200
- 54 00000200
- 55 00000200 ; Vector Table Mapped to Address 0 at Reset
- 56 00000200 AREA RESET, DATA, READONLY
- 57 00000000 EXPORT __Vectors
- 58 00000000 EXPORT __Vectors_End
- 59 00000000 EXPORT __Vectors_Size
- 60 00000000
- 61 00000000 00000000
- __Vectors
- DCD __initial_sp ; Top of Stack
- 62 00000004 00000000 DCD Reset_Handler ; Reset Handler
- 63 00000008 00000000 DCD NMI_Handler ; NMI Handler
- 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
- Handler
- 65 00000010 00000000 DCD MemManage_Handler
- ; MPU Fault Handler
-
- 66 00000014 00000000 DCD BusFault_Handler
- ; Bus Fault Handler
-
- 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul
- t Handler
- 68 0000001C 00000000 DCD 0 ; Reserved
- 69 00000020 00000000 DCD 0 ; Reserved
- 70 00000024 00000000 DCD 0 ; Reserved
- 71 00000028 00000000 DCD 0 ; Reserved
- 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
- 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito
- r Handler
- 74 00000034 00000000 DCD 0 ; Reserved
- 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
-
- 76 0000003C 00000000 DCD SysTick_Handler
- ; SysTick Handler
- 77 00000040
- 78 00000040 ; External Interrupts
- 79 00000040 00000000 DCD WWDG_IRQHandler
- ; Window Watchdog
- 80 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX
- TI Line detect
- 81 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper
- 82 0000004C 00000000 DCD RTC_IRQHandler ; RTC
-
-
-
-ARM Macro Assembler Page 3
-
-
- 83 00000050 00000000 DCD FLASH_IRQHandler ; Flash
- 84 00000054 00000000 DCD RCC_IRQHandler ; RCC
- 85 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0
- 86 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1
- 87 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2
- 88 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3
- 89 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4
- 90 0000006C 00000000 DCD DMA1_Channel1_IRQHandler
- ; DMA1 Channel 1
- 91 00000070 00000000 DCD DMA1_Channel2_IRQHandler
- ; DMA1 Channel 2
- 92 00000074 00000000 DCD DMA1_Channel3_IRQHandler
- ; DMA1 Channel 3
- 93 00000078 00000000 DCD DMA1_Channel4_IRQHandler
- ; DMA1 Channel 4
- 94 0000007C 00000000 DCD DMA1_Channel5_IRQHandler
- ; DMA1 Channel 5
- 95 00000080 00000000 DCD DMA1_Channel6_IRQHandler
- ; DMA1 Channel 6
- 96 00000084 00000000 DCD DMA1_Channel7_IRQHandler
- ; DMA1 Channel 7
- 97 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1_2
- 98 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB
- High Priority or C
- AN1 TX
- 99 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US
- B Low Priority or
- CAN1 RX0
- 100 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- 101 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- 102 0000009C 00000000 DCD EXTI9_5_IRQHandler
- ; EXTI Line 9..5
- 103 000000A0 00000000 DCD TIM1_BRK_IRQHandler
- ; TIM1 Break
- 104 000000A4 00000000 DCD TIM1_UP_IRQHandler
- ; TIM1 Update
- 105 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1
- Trigger and Commuta
- tion
- 106 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
- re Compare
- 107 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2
- 108 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3
- 109 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4
- 110 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event
-
- 111 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error
-
- 112 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event
-
- 113 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error
-
- 114 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1
- 115 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2
- 116 000000D4 00000000 DCD USART1_IRQHandler ; USART1
- 117 000000D8 00000000 DCD USART2_IRQHandler ; USART2
- 118 000000DC 00000000 DCD USART3_IRQHandler ; USART3
- 119 000000E0 00000000 DCD EXTI15_10_IRQHandler
- ; EXTI Line 15..10
-
-
-
-ARM Macro Assembler Page 4
-
-
- 120 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm
- through EXTI Line
- 121 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake
- up from suspend
- 122 000000EC __Vectors_End
- 123 000000EC
- 124 000000EC 000000EC
- __Vectors_Size
- EQU __Vectors_End - __Vectors
- 125 000000EC
- 126 000000EC AREA |.text|, CODE, READONLY
- 127 00000000
- 128 00000000 ; Reset handler
- 129 00000000 Reset_Handler
- PROC
- 130 00000000 EXPORT Reset_Handler [WEAK
-]
- 131 00000000 IMPORT __main
- 132 00000000 IMPORT SystemInit
- 133 00000000 4806 LDR R0, =SystemInit
- 134 00000002 4780 BLX R0
- 135 00000004 4806 LDR R0, =__main
- 136 00000006 4700 BX R0
- 137 00000008 ENDP
- 138 00000008
- 139 00000008 ; Dummy Exception Handlers (infinite loops which can be
- modified)
- 140 00000008
- 141 00000008 NMI_Handler
- PROC
- 142 00000008 EXPORT NMI_Handler [WEA
-K]
- 143 00000008 E7FE B .
- 144 0000000A ENDP
- 146 0000000A HardFault_Handler
- PROC
- 147 0000000A EXPORT HardFault_Handler [WEA
-K]
- 148 0000000A E7FE B .
- 149 0000000C ENDP
- 151 0000000C MemManage_Handler
- PROC
- 152 0000000C EXPORT MemManage_Handler [WEA
-K]
- 153 0000000C E7FE B .
- 154 0000000E ENDP
- 156 0000000E BusFault_Handler
- PROC
- 157 0000000E EXPORT BusFault_Handler [WEA
-K]
- 158 0000000E E7FE B .
- 159 00000010 ENDP
- 161 00000010 UsageFault_Handler
- PROC
- 162 00000010 EXPORT UsageFault_Handler [WEA
-K]
- 163 00000010 E7FE B .
- 164 00000012 ENDP
- 165 00000012 SVC_Handler
-
-
-
-ARM Macro Assembler Page 5
-
-
- PROC
- 166 00000012 EXPORT SVC_Handler [WEA
-K]
- 167 00000012 E7FE B .
- 168 00000014 ENDP
- 170 00000014 DebugMon_Handler
- PROC
- 171 00000014 EXPORT DebugMon_Handler [WEA
-K]
- 172 00000014 E7FE B .
- 173 00000016 ENDP
- 174 00000016 PendSV_Handler
- PROC
- 175 00000016 EXPORT PendSV_Handler [WEA
-K]
- 176 00000016 E7FE B .
- 177 00000018 ENDP
- 178 00000018 SysTick_Handler
- PROC
- 179 00000018 EXPORT SysTick_Handler [WEA
-K]
- 180 00000018 E7FE B .
- 181 0000001A ENDP
- 182 0000001A
- 183 0000001A Default_Handler
- PROC
- 184 0000001A
- 185 0000001A EXPORT WWDG_IRQHandler [WEA
-K]
- 186 0000001A EXPORT PVD_IRQHandler [WEA
-K]
- 187 0000001A EXPORT TAMPER_IRQHandler [WEA
-K]
- 188 0000001A EXPORT RTC_IRQHandler [WEA
-K]
- 189 0000001A EXPORT FLASH_IRQHandler [WEA
-K]
- 190 0000001A EXPORT RCC_IRQHandler [WEA
-K]
- 191 0000001A EXPORT EXTI0_IRQHandler [WEA
-K]
- 192 0000001A EXPORT EXTI1_IRQHandler [WEA
-K]
- 193 0000001A EXPORT EXTI2_IRQHandler [WEA
-K]
- 194 0000001A EXPORT EXTI3_IRQHandler [WEA
-K]
- 195 0000001A EXPORT EXTI4_IRQHandler [WEA
-K]
- 196 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA
-K]
- 197 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA
-K]
- 198 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA
-K]
- 199 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA
-K]
- 200 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA
-K]
-
-
-
-ARM Macro Assembler Page 6
-
-
- 201 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA
-K]
- 202 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA
-K]
- 203 0000001A EXPORT ADC1_2_IRQHandler [WEA
-K]
- 204 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA
-K]
- 205 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA
-K]
- 206 0000001A EXPORT CAN1_RX1_IRQHandler [WEA
-K]
- 207 0000001A EXPORT CAN1_SCE_IRQHandler [WEA
-K]
- 208 0000001A EXPORT EXTI9_5_IRQHandler [WEA
-K]
- 209 0000001A EXPORT TIM1_BRK_IRQHandler [WEA
-K]
- 210 0000001A EXPORT TIM1_UP_IRQHandler [WEA
-K]
- 211 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA
-K]
- 212 0000001A EXPORT TIM1_CC_IRQHandler [WEA
-K]
- 213 0000001A EXPORT TIM2_IRQHandler [WEA
-K]
- 214 0000001A EXPORT TIM3_IRQHandler [WEA
-K]
- 215 0000001A EXPORT TIM4_IRQHandler [WEA
-K]
- 216 0000001A EXPORT I2C1_EV_IRQHandler [WEA
-K]
- 217 0000001A EXPORT I2C1_ER_IRQHandler [WEA
-K]
- 218 0000001A EXPORT I2C2_EV_IRQHandler [WEA
-K]
- 219 0000001A EXPORT I2C2_ER_IRQHandler [WEA
-K]
- 220 0000001A EXPORT SPI1_IRQHandler [WEA
-K]
- 221 0000001A EXPORT SPI2_IRQHandler [WEA
-K]
- 222 0000001A EXPORT USART1_IRQHandler [WEA
-K]
- 223 0000001A EXPORT USART2_IRQHandler [WEA
-K]
- 224 0000001A EXPORT USART3_IRQHandler [WEA
-K]
- 225 0000001A EXPORT EXTI15_10_IRQHandler [WEA
-K]
- 226 0000001A EXPORT RTCAlarm_IRQHandler [WEA
-K]
- 227 0000001A EXPORT USBWakeUp_IRQHandler [WEA
-K]
- 228 0000001A
- 229 0000001A WWDG_IRQHandler
- 230 0000001A PVD_IRQHandler
- 231 0000001A TAMPER_IRQHandler
- 232 0000001A RTC_IRQHandler
-
-
-
-ARM Macro Assembler Page 7
-
-
- 233 0000001A FLASH_IRQHandler
- 234 0000001A RCC_IRQHandler
- 235 0000001A EXTI0_IRQHandler
- 236 0000001A EXTI1_IRQHandler
- 237 0000001A EXTI2_IRQHandler
- 238 0000001A EXTI3_IRQHandler
- 239 0000001A EXTI4_IRQHandler
- 240 0000001A DMA1_Channel1_IRQHandler
- 241 0000001A DMA1_Channel2_IRQHandler
- 242 0000001A DMA1_Channel3_IRQHandler
- 243 0000001A DMA1_Channel4_IRQHandler
- 244 0000001A DMA1_Channel5_IRQHandler
- 245 0000001A DMA1_Channel6_IRQHandler
- 246 0000001A DMA1_Channel7_IRQHandler
- 247 0000001A ADC1_2_IRQHandler
- 248 0000001A USB_HP_CAN1_TX_IRQHandler
- 249 0000001A USB_LP_CAN1_RX0_IRQHandler
- 250 0000001A CAN1_RX1_IRQHandler
- 251 0000001A CAN1_SCE_IRQHandler
- 252 0000001A EXTI9_5_IRQHandler
- 253 0000001A TIM1_BRK_IRQHandler
- 254 0000001A TIM1_UP_IRQHandler
- 255 0000001A TIM1_TRG_COM_IRQHandler
- 256 0000001A TIM1_CC_IRQHandler
- 257 0000001A TIM2_IRQHandler
- 258 0000001A TIM3_IRQHandler
- 259 0000001A TIM4_IRQHandler
- 260 0000001A I2C1_EV_IRQHandler
- 261 0000001A I2C1_ER_IRQHandler
- 262 0000001A I2C2_EV_IRQHandler
- 263 0000001A I2C2_ER_IRQHandler
- 264 0000001A SPI1_IRQHandler
- 265 0000001A SPI2_IRQHandler
- 266 0000001A USART1_IRQHandler
- 267 0000001A USART2_IRQHandler
- 268 0000001A USART3_IRQHandler
- 269 0000001A EXTI15_10_IRQHandler
- 270 0000001A RTCAlarm_IRQHandler
- 271 0000001A USBWakeUp_IRQHandler
- 272 0000001A
- 273 0000001A E7FE B .
- 274 0000001C
- 275 0000001C ENDP
- 276 0000001C
- 277 0000001C ALIGN
- 278 0000001C
- 279 0000001C ;*******************************************************
- ************************
- 280 0000001C ; User Stack and Heap initialization
- 281 0000001C ;*******************************************************
- ************************
- 282 0000001C IF :DEF:__MICROLIB
- 283 0000001C
- 284 0000001C EXPORT __initial_sp
- 285 0000001C EXPORT __heap_base
- 286 0000001C EXPORT __heap_limit
- 287 0000001C
- 288 0000001C ELSE
- 303 ENDIF
-
-
-
-ARM Macro Assembler Page 8
-
-
- 304 0000001C
- 305 0000001C END
- 00000000
- 00000000
-Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
-ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md.
-o -I.\RTE\Device\STM32F103RB -I.\RTE\_CarteSTM32 -IC:\Users\chauz\AppData\Local
-\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Users\chauz\AppData\Local\Ar
-m\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --p
-redefine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 533" --predefi
-ne="_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1"
---list=.\listings\startup_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32
-f10x_md.s
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-STACK 00000000
-
-Symbol: STACK
- Definitions
- At line 35 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: STACK unused
-Stack_Mem 00000000
-
-Symbol: Stack_Mem
- Definitions
- At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Stack_Mem unused
-__initial_sp 00000400
-
-Symbol: __initial_sp
- Definitions
- At line 37 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 284 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-HEAP 00000000
-
-Symbol: HEAP
- Definitions
- At line 46 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: HEAP unused
-Heap_Mem 00000000
-
-Symbol: Heap_Mem
- Definitions
- At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Heap_Mem unused
-__heap_base 00000000
-
-Symbol: __heap_base
- Definitions
- At line 47 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 285 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __heap_base used once
-__heap_limit 00000200
-
-Symbol: __heap_limit
- Definitions
- At line 49 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 286 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __heap_limit used once
-4 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-RESET 00000000
-
-Symbol: RESET
- Definitions
- At line 56 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: RESET unused
-__Vectors 00000000
-
-Symbol: __Vectors
- Definitions
- At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 57 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-__Vectors_End 000000EC
-
-Symbol: __Vectors_End
- Definitions
- At line 122 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 58 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-.text 00000000
-
-Symbol: .text
- Definitions
- At line 126 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: .text unused
-ADC1_2_IRQHandler 0000001A
-
-Symbol: ADC1_2_IRQHandler
- Definitions
- At line 247 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 97 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 203 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-BusFault_Handler 0000000E
-
-Symbol: BusFault_Handler
- Definitions
- At line 156 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 66 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 157 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-CAN1_RX1_IRQHandler 0000001A
-
-Symbol: CAN1_RX1_IRQHandler
- Definitions
- At line 250 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 100 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 206 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-CAN1_SCE_IRQHandler 0000001A
-
-Symbol: CAN1_SCE_IRQHandler
- Definitions
- At line 251 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 101 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 207 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel1_IRQHandler 0000001A
-
-Symbol: DMA1_Channel1_IRQHandler
- Definitions
- At line 240 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 90 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 196 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel2_IRQHandler 0000001A
-
-Symbol: DMA1_Channel2_IRQHandler
- Definitions
- At line 241 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
-
-
-
-ARM Macro Assembler Page 2 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 91 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 197 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel3_IRQHandler 0000001A
-
-Symbol: DMA1_Channel3_IRQHandler
- Definitions
- At line 242 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 92 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 198 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel4_IRQHandler 0000001A
-
-Symbol: DMA1_Channel4_IRQHandler
- Definitions
- At line 243 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 93 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 199 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel5_IRQHandler 0000001A
-
-Symbol: DMA1_Channel5_IRQHandler
- Definitions
- At line 244 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 94 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 200 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel6_IRQHandler 0000001A
-
-Symbol: DMA1_Channel6_IRQHandler
- Definitions
- At line 245 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 95 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 201 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel7_IRQHandler 0000001A
-
-Symbol: DMA1_Channel7_IRQHandler
- Definitions
- At line 246 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 96 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 202 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DebugMon_Handler 00000014
-
-Symbol: DebugMon_Handler
- Definitions
- At line 170 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 73 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 171 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-Default_Handler 0000001A
-
-
-
-
-ARM Macro Assembler Page 3 Alphabetic symbol ordering
-Relocatable symbols
-
-Symbol: Default_Handler
- Definitions
- At line 183 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Default_Handler unused
-EXTI0_IRQHandler 0000001A
-
-Symbol: EXTI0_IRQHandler
- Definitions
- At line 235 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 85 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 191 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI15_10_IRQHandler 0000001A
-
-Symbol: EXTI15_10_IRQHandler
- Definitions
- At line 269 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 119 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 225 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI1_IRQHandler 0000001A
-
-Symbol: EXTI1_IRQHandler
- Definitions
- At line 236 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 86 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 192 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI2_IRQHandler 0000001A
-
-Symbol: EXTI2_IRQHandler
- Definitions
- At line 237 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 87 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 193 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI3_IRQHandler 0000001A
-
-Symbol: EXTI3_IRQHandler
- Definitions
- At line 238 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 88 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 194 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI4_IRQHandler 0000001A
-
-Symbol: EXTI4_IRQHandler
- Definitions
- At line 239 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 89 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 195 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler Page 4 Alphabetic symbol ordering
-Relocatable symbols
-
-
-EXTI9_5_IRQHandler 0000001A
-
-Symbol: EXTI9_5_IRQHandler
- Definitions
- At line 252 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 102 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 208 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-FLASH_IRQHandler 0000001A
-
-Symbol: FLASH_IRQHandler
- Definitions
- At line 233 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 83 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 189 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-HardFault_Handler 0000000A
-
-Symbol: HardFault_Handler
- Definitions
- At line 146 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 64 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 147 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C1_ER_IRQHandler 0000001A
-
-Symbol: I2C1_ER_IRQHandler
- Definitions
- At line 261 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 111 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 217 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C1_EV_IRQHandler 0000001A
-
-Symbol: I2C1_EV_IRQHandler
- Definitions
- At line 260 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 110 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 216 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C2_ER_IRQHandler 0000001A
-
-Symbol: I2C2_ER_IRQHandler
- Definitions
- At line 263 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 113 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 219 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C2_EV_IRQHandler 0000001A
-
-Symbol: I2C2_EV_IRQHandler
- Definitions
-
-
-
-ARM Macro Assembler Page 5 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 262 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 112 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 218 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-MemManage_Handler 0000000C
-
-Symbol: MemManage_Handler
- Definitions
- At line 151 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 65 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 152 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-NMI_Handler 00000008
-
-Symbol: NMI_Handler
- Definitions
- At line 141 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 63 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 142 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-PVD_IRQHandler 0000001A
-
-Symbol: PVD_IRQHandler
- Definitions
- At line 230 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 80 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 186 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-PendSV_Handler 00000016
-
-Symbol: PendSV_Handler
- Definitions
- At line 174 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 75 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 175 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-RCC_IRQHandler 0000001A
-
-Symbol: RCC_IRQHandler
- Definitions
- At line 234 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 84 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 190 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-RTCAlarm_IRQHandler 0000001A
-
-Symbol: RTCAlarm_IRQHandler
- Definitions
- At line 270 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 120 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 226 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-
-ARM Macro Assembler Page 6 Alphabetic symbol ordering
-Relocatable symbols
-
-RTC_IRQHandler 0000001A
-
-Symbol: RTC_IRQHandler
- Definitions
- At line 232 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 82 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 188 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-Reset_Handler 00000000
-
-Symbol: Reset_Handler
- Definitions
- At line 129 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 62 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 130 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SPI1_IRQHandler 0000001A
-
-Symbol: SPI1_IRQHandler
- Definitions
- At line 264 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 114 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 220 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SPI2_IRQHandler 0000001A
-
-Symbol: SPI2_IRQHandler
- Definitions
- At line 265 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 115 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 221 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SVC_Handler 00000012
-
-Symbol: SVC_Handler
- Definitions
- At line 165 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 72 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 166 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SysTick_Handler 00000018
-
-Symbol: SysTick_Handler
- Definitions
- At line 178 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 76 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 179 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TAMPER_IRQHandler 0000001A
-
-Symbol: TAMPER_IRQHandler
- Definitions
- At line 231 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler Page 7 Alphabetic symbol ordering
-Relocatable symbols
-
- Uses
- At line 81 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 187 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_BRK_IRQHandler 0000001A
-
-Symbol: TIM1_BRK_IRQHandler
- Definitions
- At line 253 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 103 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 209 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_CC_IRQHandler 0000001A
-
-Symbol: TIM1_CC_IRQHandler
- Definitions
- At line 256 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 106 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 212 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_TRG_COM_IRQHandler 0000001A
-
-Symbol: TIM1_TRG_COM_IRQHandler
- Definitions
- At line 255 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 105 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 211 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_UP_IRQHandler 0000001A
-
-Symbol: TIM1_UP_IRQHandler
- Definitions
- At line 254 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 104 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 210 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM2_IRQHandler 0000001A
-
-Symbol: TIM2_IRQHandler
- Definitions
- At line 257 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 107 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 213 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM3_IRQHandler 0000001A
-
-Symbol: TIM3_IRQHandler
- Definitions
- At line 258 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 108 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 214 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM4_IRQHandler 0000001A
-
-
-
-ARM Macro Assembler Page 8 Alphabetic symbol ordering
-Relocatable symbols
-
-
-Symbol: TIM4_IRQHandler
- Definitions
- At line 259 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 109 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 215 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART1_IRQHandler 0000001A
-
-Symbol: USART1_IRQHandler
- Definitions
- At line 266 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 116 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 222 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART2_IRQHandler 0000001A
-
-Symbol: USART2_IRQHandler
- Definitions
- At line 267 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 117 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 223 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART3_IRQHandler 0000001A
-
-Symbol: USART3_IRQHandler
- Definitions
- At line 268 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 118 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 224 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USBWakeUp_IRQHandler 0000001A
-
-Symbol: USBWakeUp_IRQHandler
- Definitions
- At line 271 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 121 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 227 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USB_HP_CAN1_TX_IRQHandler 0000001A
-
-Symbol: USB_HP_CAN1_TX_IRQHandler
- Definitions
- At line 248 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 98 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 204 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USB_LP_CAN1_RX0_IRQHandler 0000001A
-
-Symbol: USB_LP_CAN1_RX0_IRQHandler
- Definitions
- At line 249 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
-
-
-
-ARM Macro Assembler Page 9 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 99 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 205 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-UsageFault_Handler 00000010
-
-Symbol: UsageFault_Handler
- Definitions
- At line 161 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 67 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 162 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-WWDG_IRQHandler 0000001A
-
-Symbol: WWDG_IRQHandler
- Definitions
- At line 229 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 79 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 185 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-55 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Absolute symbols
-
-Heap_Size 00000200
-
-Symbol: Heap_Size
- Definitions
- At line 44 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: Heap_Size used once
-Stack_Size 00000400
-
-Symbol: Stack_Size
- Definitions
- At line 33 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: Stack_Size used once
-__Vectors_Size 000000EC
-
-Symbol: __Vectors_Size
- Definitions
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 59 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __Vectors_Size used once
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-External symbols
-
-SystemInit 00000000
-
-Symbol: SystemInit
- Definitions
- At line 132 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 133 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: SystemInit used once
-__main 00000000
-
-Symbol: __main
- Definitions
- At line 131 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 135 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __main used once
-2 symbols
-407 symbols in table
diff --git a/driver_premier_test/Objects/ExtDll.iex b/driver_premier_test/Objects/ExtDll.iex
deleted file mode 100644
index 6c0896e..0000000
--- a/driver_premier_test/Objects/ExtDll.iex
+++ /dev/null
@@ -1,2 +0,0 @@
-[EXTDLL]
-Count=0
diff --git a/driver_premier_test/Objects/driver_gpio.crf b/driver_premier_test/Objects/driver_gpio.crf
deleted file mode 100644
index 0bcf94f..0000000
Binary files a/driver_premier_test/Objects/driver_gpio.crf and /dev/null differ
diff --git a/driver_premier_test/Objects/driver_gpio.d b/driver_premier_test/Objects/driver_gpio.d
deleted file mode 100644
index 777ebfb..0000000
--- a/driver_premier_test/Objects/driver_gpio.d
+++ /dev/null
@@ -1,10 +0,0 @@
-.\objects\driver_gpio.o: Includes\Driver_GPIO.c
-.\objects\driver_gpio.o: Includes\Driver_GPIO.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\driver_gpio.o: .\RTE\_CarteSTM32\RTE_Components.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\driver_gpio.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/driver_premier_test/Objects/driver_gpio.o b/driver_premier_test/Objects/driver_gpio.o
deleted file mode 100644
index 5c4b612..0000000
Binary files a/driver_premier_test/Objects/driver_gpio.o and /dev/null differ
diff --git a/driver_premier_test/Objects/driver_premier_test.axf b/driver_premier_test/Objects/driver_premier_test.axf
deleted file mode 100644
index 207f234..0000000
Binary files a/driver_premier_test/Objects/driver_premier_test.axf and /dev/null differ
diff --git a/driver_premier_test/Objects/driver_premier_test.build_log.htm b/driver_premier_test/Objects/driver_premier_test.build_log.htm
deleted file mode 100644
index ff3ab06..0000000
--- a/driver_premier_test/Objects/driver_premier_test.build_log.htm
+++ /dev/null
@@ -1,67 +0,0 @@
-
-
-
-µVision Build Log
-Tool Versions:
-IDE-Version: µVision V5.33.0.0
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: Celia C, Insa, LIC=----
-
-Tool Versions:
-Toolchain: MDK-Lite Version: 5.33.0.0
-Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler: Armcc.exe V5.06 update 7 (build 960)
-Assembler: Armasm.exe V5.06 update 7 (build 960)
-Linker/Locator: ArmLink.exe V5.06 update 7 (build 960)
-Library Manager: ArmAr.exe V5.06 update 7 (build 960)
-Hex Converter: FromElf.exe V5.06 update 7 (build 960)
-CPU DLL: SARMCM3.DLL V5.33.0.0
-Dialog DLL: DARMSTM.DLL V1.68.0.0
-Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.8.0
-Dialog DLL: TARMSTM.DLL V1.66.0.0
-
-Project:
-C:\Users\chauz\Documents_non_drive\INSA\4A\S7\TP_microcontroleur\driver_premier_test\driver_premier_test.uvprojx
-Project File Date: 09/19/2021
-
-Output:
-*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Build target 'CarteSTM32'
-compiling principal.c...
-linking...
-Program Size: Code=852 RO-data=252 RW-data=0 ZI-data=1024
-".\Objects\driver_premier_test.axf" - 0 Error(s), 0 Warning(s).
-
-Software Packages used:
-
-Package Vendor: ARM
- http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
- ARM.CMSIS.5.7.0
- CMSIS (Cortex Microcontroller Software Interface Standard)
- * Component: CORE Version: 5.4.0
-
-Package Vendor: Keil
- http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
- Keil.STM32F1xx_DFP.2.3.0
- STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
- * Component: Startup Version: 1.0.0
-
-Collection of Component include folders:
- .\RTE\Device\STM32F103RB
- .\RTE\_CarteSTM32
- C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
- C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-
-Collection of Component Files used:
-
- * Component: ARM::CMSIS:CORE:5.4.0
-
- * Component: Keil::Device:Startup:1.0.0
- Include file: RTE_Driver\Config\RTE_Device.h
- Source file: Device\Source\system_stm32f10x.c
- Source file: Device\Source\ARM\startup_stm32f10x_md.s
- Source file: Device\Source\ARM\STM32F1xx_OPT.s
-Build Time Elapsed: 00:00:01
-
-
-
diff --git a/driver_premier_test/Objects/driver_premier_test.htm b/driver_premier_test/Objects/driver_premier_test.htm
deleted file mode 100644
index fcaba60..0000000
--- a/driver_premier_test/Objects/driver_premier_test.htm
+++ /dev/null
@@ -1,389 +0,0 @@
-
-
-Static Call Graph - [.\Objects\driver_premier_test.axf]
-
-Static Call Graph for image .\Objects\driver_premier_test.axf
-
#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Fri Sep 24 15:45:55 2021
-
-
Maximum Stack Usage = 28 bytes + Unknown(Cycles, Untraceable Function Pointers)
-Call chain for Maximum Stack Depth:
-SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
-
-
-Mutually Recursive functions
-
NMI_Handler ⇒ NMI_Handler
- HardFault_Handler ⇒ HardFault_Handler
- MemManage_Handler ⇒ MemManage_Handler
- BusFault_Handler ⇒ BusFault_Handler
- UsageFault_Handler ⇒ UsageFault_Handler
- SVC_Handler ⇒ SVC_Handler
- DebugMon_Handler ⇒ DebugMon_Handler
- PendSV_Handler ⇒ PendSV_Handler
- SysTick_Handler ⇒ SysTick_Handler
- ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
-
-
-
-Function Pointers
-
- - ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI9_5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text)
-
- TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_TRG_COM_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_UP_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text)
-
- main from principal.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-
-Global Symbols
-
-__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(.text)
-
-_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Calls]
-
-__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Called By]
-
-_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-
__rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E))
-
-
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F))
-
-
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011))
-
-
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
-
NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-
[Calls]
- >> __main_after_scatterload
-
-
[Called By]
-
-__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-
MyGPIO_Activate (Thumb, 18 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Activate))
-
[Called By]
-
-MyGPIO_Init (Thumb, 236 bytes, Stack size 4 bytes, driver_gpio.o(i.MyGPIO_Init))
-
[Stack]
- Max Depth = 4
- Call Chain = MyGPIO_Init
-
-
[Calls]
-
[Called By]
-
-MyGPIO_Read (Thumb, 12 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Read))
-
[Called By]
-
-MyGPIO_Reset (Thumb, 12 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Reset))
-
[Called By]
-
-MyGPIO_Set (Thumb, 8 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Set))
-
[Called By]
- >> MyGPIO_Init
-
- >> main
-
-
-SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
-
[Stack]
- Max Depth = 28
- Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(.text)
-
-__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-
main (Thumb, 96 bytes, Stack size 24 bytes, principal.o(i.main))
-
[Stack]
- Max Depth = 28
- Call Chain = main ⇒ MyGPIO_Init
-
-
[Calls]- >> MyGPIO_Set
-
- >> MyGPIO_Reset
-
- >> MyGPIO_Read
-
- >> MyGPIO_Init
-
- >> MyGPIO_Activate
-
-
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-Local Symbols
-
-SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
-
[Stack]
- Max Depth = 20
- Call Chain = SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Called By]
-
-SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
-
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
-
-
[Called By]
-
-
-Undefined Global Symbols
-
diff --git a/driver_premier_test/Objects/driver_premier_test.lnp b/driver_premier_test/Objects/driver_premier_test.lnp
deleted file mode 100644
index 476f117..0000000
--- a/driver_premier_test/Objects/driver_premier_test.lnp
+++ /dev/null
@@ -1,8 +0,0 @@
---cpu Cortex-M3
-".\objects\principal.o"
-".\objects\driver_gpio.o"
-".\objects\startup_stm32f10x_md.o"
-".\objects\system_stm32f10x.o"
---library_type=microlib --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\driver_premier_test.map" -o .\Objects\driver_premier_test.axf
\ No newline at end of file
diff --git a/driver_premier_test/Objects/driver_premier_test_CarteSTM32.dep b/driver_premier_test/Objects/driver_premier_test_CarteSTM32.dep
deleted file mode 100644
index 62da13b..0000000
--- a/driver_premier_test/Objects/driver_premier_test_CarteSTM32.dep
+++ /dev/null
@@ -1,34 +0,0 @@
-Dependencies for Project 'driver_premier_test', Target 'CarteSTM32': (DO NOT MODIFY !)
-CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
-F (.\Source\principal.c)(0x614DD68F)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM32
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_CarteSTM32\RTE_Components.h)(0x61476EF1)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-I (.\Includes\Driver_GPIO.h)(0x61476D7E)
-F (.\Includes\Driver_GPIO.c)(0x61477817)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM32
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d)
-I (Includes\Driver_GPIO.h)(0x61476D7E)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_CarteSTM32\RTE_Components.h)(0x61476EF1)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-F (.\Includes\Driver_GPIO.h)(0x61476D7E)()
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59284216)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58259ADC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM32
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 533" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58259ADC)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_CarteSTM32
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_CarteSTM32\RTE_Components.h)(0x61476EF1)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
diff --git a/driver_premier_test/Objects/principal.crf b/driver_premier_test/Objects/principal.crf
deleted file mode 100644
index 59622fe..0000000
Binary files a/driver_premier_test/Objects/principal.crf and /dev/null differ
diff --git a/driver_premier_test/Objects/principal.d b/driver_premier_test/Objects/principal.d
deleted file mode 100644
index 983c26e..0000000
--- a/driver_premier_test/Objects/principal.d
+++ /dev/null
@@ -1,10 +0,0 @@
-.\objects\principal.o: Source\principal.c
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\principal.o: .\RTE\_CarteSTM32\RTE_Components.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\principal.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
-.\objects\principal.o: .\Includes\Driver_GPIO.h
diff --git a/driver_premier_test/Objects/principal.o b/driver_premier_test/Objects/principal.o
deleted file mode 100644
index abd721e..0000000
Binary files a/driver_premier_test/Objects/principal.o and /dev/null differ
diff --git a/driver_premier_test/Objects/startup_stm32f10x_md.d b/driver_premier_test/Objects/startup_stm32f10x_md.d
deleted file mode 100644
index 96d5fcf..0000000
--- a/driver_premier_test/Objects/startup_stm32f10x_md.d
+++ /dev/null
@@ -1 +0,0 @@
-.\objects\startup_stm32f10x_md.o: RTE\Device\STM32F103RB\startup_stm32f10x_md.s
diff --git a/driver_premier_test/Objects/startup_stm32f10x_md.o b/driver_premier_test/Objects/startup_stm32f10x_md.o
deleted file mode 100644
index baa8453..0000000
Binary files a/driver_premier_test/Objects/startup_stm32f10x_md.o and /dev/null differ
diff --git a/driver_premier_test/Objects/system_stm32f10x.crf b/driver_premier_test/Objects/system_stm32f10x.crf
deleted file mode 100644
index 54b7c0c..0000000
Binary files a/driver_premier_test/Objects/system_stm32f10x.crf and /dev/null differ
diff --git a/driver_premier_test/Objects/system_stm32f10x.d b/driver_premier_test/Objects/system_stm32f10x.d
deleted file mode 100644
index dc463e8..0000000
--- a/driver_premier_test/Objects/system_stm32f10x.d
+++ /dev/null
@@ -1,9 +0,0 @@
-.\objects\system_stm32f10x.o: RTE\Device\STM32F103RB\system_stm32f10x.c
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\system_stm32f10x.o: .\RTE\_CarteSTM32\RTE_Components.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/driver_premier_test/Objects/system_stm32f10x.o b/driver_premier_test/Objects/system_stm32f10x.o
deleted file mode 100644
index a686a27..0000000
Binary files a/driver_premier_test/Objects/system_stm32f10x.o and /dev/null differ
diff --git a/driver_premier_test/RTE/Device/STM32F103RB/RTE_Device.h b/driver_premier_test/RTE/Device/STM32F103RB/RTE_Device.h
deleted file mode 100644
index 22d1da2..0000000
--- a/driver_premier_test/RTE/Device/STM32F103RB/RTE_Device.h
+++ /dev/null
@@ -1,1828 +0,0 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2016 ARM Ltd.
- *
- * This software is provided 'as-is', without any express or implied warranty.
- * In no event will the authors be held liable for any damages arising from
- * the use of this software. Permission is granted to anyone to use this
- * software for any purpose, including commercial applications, and to alter
- * it and redistribute it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software. If you use this software in
- * a product, an acknowledgment in the product documentation would be
- * appreciated but is not required.
- *
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.
- *
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * $Date: 09. September 2016
- * $Revision: V1.1.2
- *
- * Project: RTE Device Configuration for STMicroelectronics STM32F1xx
- *
- * -------------------------------------------------------------------------- */
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-#ifndef __RTE_DEVICE_H
-#define __RTE_DEVICE_H
-
-
-#define GPIO_PORT(num) \
- ((num == 0) ? GPIOA : \
- (num == 1) ? GPIOB : \
- (num == 2) ? GPIOC : \
- (num == 3) ? GPIOD : \
- (num == 4) ? GPIOE : \
- (num == 5) ? GPIOF : \
- (num == 6) ? GPIOG : \
- NULL)
-
-
-// Clock Configuration
-// High-speed Internal Clock <1-999999999>
-#define RTE_HSI 8000000
-// High-speed External Clock <1-999999999>
-#define RTE_HSE 25000000
-// System Clock <1-999999999>
-#define RTE_SYSCLK 72000000
-// HCLK Clock <1-999999999>
-#define RTE_HCLK 72000000
-// APB1 Clock <1-999999999>
-#define RTE_PCLK1 36000000
-// APB2 Clock <1-999999999>
-#define RTE_PCLK2 72000000
-// ADC Clock <1-999999999>
-#define RTE_ADCCLK 36000000
-// USB Clock
-#define RTE_USBCLK 48000000
-//
-
-
-// USART1 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
-#define RTE_USART1 0
-
-// USART1_TX Pin <0=>Not Used <1=>PA9
-#define RTE_USART1_TX_PORT_ID_DEF 0
-#if (RTE_USART1_TX_PORT_ID_DEF == 0)
-#define RTE_USART1_TX_DEF 0
-#elif (RTE_USART1_TX_PORT_ID_DEF == 1)
-#define RTE_USART1_TX_DEF 1
-#define RTE_USART1_TX_PORT_DEF GPIOA
-#define RTE_USART1_TX_BIT_DEF 9
-#else
-#error "Invalid USART1_TX Pin Configuration!"
-#endif
-
-// USART1_RX Pin <0=>Not Used <1=>PA10
-#define RTE_USART1_RX_PORT_ID_DEF 0
-#if (RTE_USART1_RX_PORT_ID_DEF == 0)
-#define RTE_USART1_RX_DEF 0
-#elif (RTE_USART1_RX_PORT_ID_DEF == 1)
-#define RTE_USART1_RX_DEF 1
-#define RTE_USART1_RX_PORT_DEF GPIOA
-#define RTE_USART1_RX_BIT_DEF 10
-#else
-#error "Invalid USART1_RX Pin Configuration!"
-#endif
-
-// USART1_CK Pin <0=>Not Used <1=>PA8
-#define RTE_USART1_CK_PORT_ID_DEF 0
-#if (RTE_USART1_CK_PORT_ID_DEF == 0)
-#define RTE_USART1_CK 0
-#elif (RTE_USART1_CK_PORT_ID_DEF == 1)
-#define RTE_USART1_CK 1
-#define RTE_USART1_CK_PORT_DEF GPIOA
-#define RTE_USART1_CK_BIT_DEF 8
-#else
-#error "Invalid USART1_CK Pin Configuration!"
-#endif
-
-// USART1_CTS Pin <0=>Not Used <1=>PA11
-#define RTE_USART1_CTS_PORT_ID_DEF 0
-#if (RTE_USART1_CTS_PORT_ID_DEF == 0)
-#define RTE_USART1_CTS 0
-#elif (RTE_USART1_CTS_PORT_ID_DEF == 1)
-#define RTE_USART1_CTS 1
-#define RTE_USART1_CTS_PORT_DEF GPIOA
-#define RTE_USART1_CTS_BIT_DEF 11
-#else
-#error "Invalid USART1_CTS Pin Configuration!"
-#endif
-
-// USART1_RTS Pin <0=>Not Used <1=>PA12
-#define RTE_USART1_RTS_PORT_ID_DEF 0
-#if (RTE_USART1_RTS_PORT_ID_DEF == 0)
-#define RTE_USART1_RTS 0
-#elif (RTE_USART1_RTS_PORT_ID_DEF == 1)
-#define RTE_USART1_RTS 1
-#define RTE_USART1_RTS_PORT_DEF GPIOA
-#define RTE_USART1_RTS_BIT_DEF 12
-#else
-#error "Invalid USART1_RTS Pin Configuration!"
-#endif
-
-// USART1 Pin Remap
-// Enable USART1 Pin Remapping
-#define RTE_USART1_REMAP_FULL 0
-
-// USART1_TX Pin <0=>Not Used <1=>PB6
-#define RTE_USART1_TX_PORT_ID_FULL 0
-#if (RTE_USART1_TX_PORT_ID_FULL == 0)
-#define RTE_USART1_TX_FULL 0
-#elif (RTE_USART1_TX_PORT_ID_FULL == 1)
-#define RTE_USART1_TX_FULL 1
-#define RTE_USART1_TX_PORT_FULL GPIOB
-#define RTE_USART1_TX_BIT_FULL 6
-#else
-#error "Invalid USART1_TX Pin Configuration!"
-#endif
-
-// USART1_RX Pin <0=>Not Used <1=>PB7
-#define RTE_USART1_RX_PORT_ID_FULL 0
-#if (RTE_USART1_RX_PORT_ID_FULL == 0)
-#define RTE_USART1_RX_FULL 0
-#elif (RTE_USART1_RX_PORT_ID_FULL == 1)
-#define RTE_USART1_RX_FULL 1
-#define RTE_USART1_RX_PORT_FULL GPIOB
-#define RTE_USART1_RX_BIT_FULL 7
-#else
-#error "Invalid USART1_RX Pin Configuration!"
-#endif
-//
-
-#if (RTE_USART1_REMAP_FULL)
-#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP
-#define RTE_USART1_TX RTE_USART1_TX_FULL
-#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL
-#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL
-#define RTE_USART1_RX RTE_USART1_RX_FULL
-#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL
-#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL
-#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
-#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
-#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
-#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
-#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
-#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
-#else
-#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP
-#define RTE_USART1_TX RTE_USART1_TX_DEF
-#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF
-#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF
-#define RTE_USART1_RX RTE_USART1_RX_DEF
-#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF
-#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF
-#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
-#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
-#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
-#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
-#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
-#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART1_RX_DMA 0
-#define RTE_USART1_RX_DMA_NUMBER 1
-#define RTE_USART1_RX_DMA_CHANNEL 5
-#define RTE_USART1_RX_DMA_PRIORITY 0
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART1_TX_DMA 0
-#define RTE_USART1_TX_DMA_NUMBER 1
-#define RTE_USART1_TX_DMA_CHANNEL 4
-#define RTE_USART1_TX_DMA_PRIORITY 0
-//
-
-
-// USART2 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
-#define RTE_USART2 0
-
-// USART2_TX Pin <0=>Not Used <1=>PA2
-#define RTE_USART2_TX_PORT_ID_DEF 0
-#if (RTE_USART2_TX_PORT_ID_DEF == 0)
-#define RTE_USART2_TX_DEF 0
-#elif (RTE_USART2_TX_PORT_ID_DEF == 1)
-#define RTE_USART2_TX_DEF 1
-#define RTE_USART2_TX_PORT_DEF GPIOA
-#define RTE_USART2_TX_BIT_DEF 2
-#else
-#error "Invalid USART2_TX Pin Configuration!"
-#endif
-
-// USART2_RX Pin <0=>Not Used <1=>PA3
-#define RTE_USART2_RX_PORT_ID_DEF 0
-#if (RTE_USART2_RX_PORT_ID_DEF == 0)
-#define RTE_USART2_RX_DEF 0
-#elif (RTE_USART2_RX_PORT_ID_DEF == 1)
-#define RTE_USART2_RX_DEF 1
-#define RTE_USART2_RX_PORT_DEF GPIOA
-#define RTE_USART2_RX_BIT_DEF 3
-#else
-#error "Invalid USART2_RX Pin Configuration!"
-#endif
-
-// USART2_CK Pin <0=>Not Used <1=>PA4
-#define RTE_USART2_CK_PORT_ID_DEF 0
-#if (RTE_USART2_CK_PORT_ID_DEF == 0)
-#define RTE_USART2_CK_DEF 0
-#elif (RTE_USART2_CK_PORT_ID_DEF == 1)
-#define RTE_USART2_CK_DEF 1
-#define RTE_USART2_CK_PORT_DEF GPIOA
-#define RTE_USART2_CK_BIT_DEF 4
-#else
-#error "Invalid USART2_CK Pin Configuration!"
-#endif
-
-// USART2_CTS Pin <0=>Not Used <1=>PA0
-#define RTE_USART2_CTS_PORT_ID_DEF 0
-#if (RTE_USART2_CTS_PORT_ID_DEF == 0)
-#define RTE_USART2_CTS_DEF 0
-#elif (RTE_USART2_CTS_PORT_ID_DEF == 1)
-#define RTE_USART2_CTS_DEF 1
-#define RTE_USART2_CTS_PORT_DEF GPIOA
-#define RTE_USART2_CTS_BIT_DEF 0
-#else
-#error "Invalid USART2_CTS Pin Configuration!"
-#endif
-
-// USART2_RTS Pin <0=>Not Used <1=>PA1
-#define RTE_USART2_RTS_PORT_ID_DEF 0
-#if (RTE_USART2_RTS_PORT_ID_DEF == 0)
-#define RTE_USART2_RTS_DEF 0
-#elif (RTE_USART2_RTS_PORT_ID_DEF == 1)
-#define RTE_USART2_RTS_DEF 1
-#define RTE_USART2_RTS_PORT_DEF GPIOA
-#define RTE_USART2_RTS_BIT_DEF 1
-#else
-#error "Invalid USART2_RTS Pin Configuration!"
-#endif
-
-// USART2 Pin Remap
-// Enable USART2 Pin Remapping
-#define RTE_USART2_REMAP_FULL 0
-
-// USART2_TX Pin <0=>Not Used <1=>PD5
-#define RTE_USART2_TX_PORT_ID_FULL 0
-#if (RTE_USART2_TX_PORT_ID_FULL == 0)
-#define RTE_USART2_TX_FULL 0
-#elif (RTE_USART2_TX_PORT_ID_FULL == 1)
-#define RTE_USART2_TX_FULL 1
-#define RTE_USART2_TX_PORT_FULL GPIOD
-#define RTE_USART2_TX_BIT_FULL 5
-#else
-#error "Invalid USART2_TX Pin Configuration!"
-#endif
-
-// USART2_RX Pin <0=>Not Used <1=>PD6
-#define RTE_USART2_RX_PORT_ID_FULL 0
-#if (RTE_USART2_RX_PORT_ID_FULL == 0)
-#define RTE_USART2_RX_FULL 0
-#elif (RTE_USART2_RX_PORT_ID_FULL == 1)
-#define RTE_USART2_RX_FULL 1
-#define RTE_USART2_RX_PORT_FULL GPIOD
-#define RTE_USART2_RX_BIT_FULL 6
-#else
-#error "Invalid USART2_RX Pin Configuration!"
-#endif
-
-// USART2_CK Pin <0=>Not Used <1=>PD7
-#define RTE_USART2_CK_PORT_ID_FULL 0
-#if (RTE_USART2_CK_PORT_ID_FULL == 0)
-#define RTE_USART2_CK_FULL 0
-#elif (RTE_USART2_CK_PORT_ID_FULL == 1)
-#define RTE_USART2_CK_FULL 1
-#define RTE_USART2_CK_PORT_FULL GPIOD
-#define RTE_USART2_CK_BIT_FULL 7
-#else
-#error "Invalid USART2_CK Pin Configuration!"
-#endif
-
-// USART2_CTS Pin <0=>Not Used <1=>PD3
-#define RTE_USART2_CTS_PORT_ID_FULL 0
-#if (RTE_USART2_CTS_PORT_ID_FULL == 0)
-#define RTE_USART2_CTS_FULL 0
-#elif (RTE_USART2_CTS_PORT_ID_FULL == 1)
-#define RTE_USART2_CTS_FULL 1
-#define RTE_USART2_CTS_PORT_FULL GPIOD
-#define RTE_USART2_CTS_BIT_FULL 3
-#else
-#error "Invalid USART2_CTS Pin Configuration!"
-#endif
-
-// USART2_RTS Pin <0=>Not Used <1=>PD4
-#define RTE_USART2_RTS_PORT_ID_FULL 0
-#if (RTE_USART2_RTS_PORT_ID_FULL == 0)
-#define RTE_USART2_RTS_FULL 0
-#elif (RTE_USART2_RTS_PORT_ID_FULL == 1)
-#define RTE_USART2_RTS_FULL 1
-#define RTE_USART2_RTS_PORT_FULL GPIOD
-#define RTE_USART2_RTS_BIT_FULL 4
-#else
-#error "Invalid USART2_RTS Pin Configuration!"
-#endif
-//
-
-#if (RTE_USART2_REMAP_FULL)
-#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP
-#define RTE_USART2_TX RTE_USART2_TX_FULL
-#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL
-#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL
-#define RTE_USART2_RX RTE_USART2_RX_FULL
-#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL
-#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL
-#define RTE_USART2_CK RTE_USART2_CK_FULL
-#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL
-#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL
-#define RTE_USART2_CTS RTE_USART2_CTS_FULL
-#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL
-#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL
-#define RTE_USART2_RTS RTE_USART2_RTS_FULL
-#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL
-#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL
-#else
-#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP
-#define RTE_USART2_TX RTE_USART2_TX_DEF
-#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF
-#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF
-#define RTE_USART2_RX RTE_USART2_RX_DEF
-#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF
-#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF
-#define RTE_USART2_CK RTE_USART2_CK_DEF
-#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF
-#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF
-#define RTE_USART2_CTS RTE_USART2_CTS_DEF
-#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF
-#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF
-#define RTE_USART2_RTS RTE_USART2_RTS_DEF
-#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF
-#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <6=>6
-// Selects DMA Channel (only Channel 6 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART2_RX_DMA 0
-#define RTE_USART2_RX_DMA_NUMBER 1
-#define RTE_USART2_RX_DMA_CHANNEL 6
-#define RTE_USART2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <7=>7
-// Selects DMA Channel (only Channel 7 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART2_TX_DMA 0
-#define RTE_USART2_TX_DMA_NUMBER 1
-#define RTE_USART2_TX_DMA_CHANNEL 7
-#define RTE_USART2_TX_DMA_PRIORITY 0
-
-//
-
-
-// USART3 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
-#define RTE_USART3 0
-
-// USART3_TX Pin <0=>Not Used <1=>PB10
-#define RTE_USART3_TX_PORT_ID_DEF 0
-#if (RTE_USART3_TX_PORT_ID_DEF == 0)
-#define RTE_USART3_TX_DEF 0
-#elif (RTE_USART3_TX_PORT_ID_DEF == 1)
-#define RTE_USART3_TX_DEF 1
-#define RTE_USART3_TX_PORT_DEF GPIOB
-#define RTE_USART3_TX_BIT_DEF 10
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PB11
-#define RTE_USART3_RX_PORT_ID_DEF 0
-#if (RTE_USART3_RX_PORT_ID_DEF == 0)
-#define RTE_USART3_RX_DEF 0
-#elif (RTE_USART3_RX_PORT_ID_DEF == 1)
-#define RTE_USART3_RX_DEF 1
-#define RTE_USART3_RX_PORT_DEF GPIOB
-#define RTE_USART3_RX_BIT_DEF 11
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PB12
-#define RTE_USART3_CK_PORT_ID_DEF 0
-#if (RTE_USART3_CK_PORT_ID_DEF == 0)
-#define RTE_USART3_CK_DEF 0
-#elif (RTE_USART3_CK_PORT_ID_DEF == 1)
-#define RTE_USART3_CK_DEF 1
-#define RTE_USART3_CK_PORT_DEF GPIOB
-#define RTE_USART3_CK_BIT_DEF 12
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-
-// USART3_CTS Pin <0=>Not Used <1=>PB13
-#define RTE_USART3_CTS_PORT_ID_DEF 0
-#if (RTE_USART3_CTS_PORT_ID_DEF == 0)
-#define RTE_USART3_CTS_DEF 0
-#elif (RTE_USART3_CTS_PORT_ID_DEF == 1)
-#define RTE_USART3_CTS_DEF 1
-#define RTE_USART3_CTS_PORT_DEF GPIOB
-#define RTE_USART3_CTS_BIT_DEF 13
-#else
-#error "Invalid USART3_CTS Pin Configuration!"
-#endif
-
-// USART3_RTS Pin <0=>Not Used <1=>PB14
-#define RTE_USART3_RTS_PORT_ID_DEF 0
-#if (RTE_USART3_RTS_PORT_ID_DEF == 0)
-#define RTE_USART3_RTS_DEF 0
-#elif (RTE_USART3_RTS_PORT_ID_DEF == 1)
-#define RTE_USART3_RTS_DEF 1
-#define RTE_USART3_RTS_PORT_DEF GPIOB
-#define RTE_USART3_RTS_BIT_DEF 14
-#else
-#error "Invalid USART3_RTS Pin Configuration!"
-#endif
-
-// USART3 Partial Pin Remap
-// Enable USART3 Partial Pin Remapping
-#define RTE_USART3_REMAP_PARTIAL 0
-
-// USART3_TX Pin <0=>Not Used <1=>PC10
-#define RTE_USART3_TX_PORT_ID_PARTIAL 0
-#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_TX_PARTIAL 0
-#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_TX_PARTIAL 1
-#define RTE_USART3_TX_PORT_PARTIAL GPIOC
-#define RTE_USART3_TX_BIT_PARTIAL 10
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PC11
-#define RTE_USART3_RX_PORT_ID_PARTIAL 0
-#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_RX_PARTIAL 0
-#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_RX_PARTIAL 1
-#define RTE_USART3_RX_PORT_PARTIAL GPIOC
-#define RTE_USART3_RX_BIT_PARTIAL 11
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PC12
-#define RTE_USART3_CK_PORT_ID_PARTIAL 0
-#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_CK_PARTIAL 0
-#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_CK_PARTIAL 1
-#define RTE_USART3_CK_PORT_PARTIAL GPIOC
-#define RTE_USART3_CK_BIT_PARTIAL 12
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-//
-
-// USART3 Full Pin Remap
-// Enable USART3 Full Pin Remapping
-#define RTE_USART3_REMAP_FULL 0
-
-// USART3_TX Pin <0=>Not Used <1=>PD8
-#define RTE_USART3_TX_PORT_ID_FULL 0
-#if (RTE_USART3_TX_PORT_ID_FULL == 0)
-#define RTE_USART3_TX_FULL 0
-#elif (RTE_USART3_TX_PORT_ID_FULL == 1)
-#define RTE_USART3_TX_FULL 1
-#define RTE_USART3_TX_PORT_FULL GPIOD
-#define RTE_USART3_TX_BIT_FULL 8
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PD9
-#define RTE_USART3_RX_PORT_ID_FULL 0
-#if (RTE_USART3_RX_PORT_ID_FULL == 0)
-#define RTE_USART3_RX_FULL 0
-#elif (RTE_USART3_RX_PORT_ID_FULL == 1)
-#define RTE_USART3_RX_FULL 1
-#define RTE_USART3_RX_PORT_FULL GPIOD
-#define RTE_USART3_RX_BIT_FULL 9
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PD10
-#define RTE_USART3_CK_PORT_ID_FULL 0
-#if (RTE_USART3_CK_PORT_ID_FULL == 0)
-#define RTE_USART3_CK_FULL 0
-#elif (RTE_USART3_CK_PORT_ID_FULL == 1)
-#define RTE_USART3_CK_FULL 1
-#define RTE_USART3_CK_PORT_FULL GPIOD
-#define RTE_USART3_CK_BIT_FULL 10
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-
-// USART3_CTS Pin <0=>Not Used <1=>PD11
-#define RTE_USART3_CTS_PORT_ID_FULL 0
-#if (RTE_USART3_CTS_PORT_ID_FULL == 0)
-#define RTE_USART3_CTS_FULL 0
-#elif (RTE_USART3_CTS_PORT_ID_FULL == 1)
-#define RTE_USART3_CTS_FULL 1
-#define RTE_USART3_CTS_PORT_FULL GPIOD
-#define RTE_USART3_CTS_BIT_FULL 11
-#else
-#error "Invalid USART3_CTS Pin Configuration!"
-#endif
-
-// USART3_RTS Pin <0=>Not Used <1=>PD12
-#define RTE_USART3_RTS_PORT_ID_FULL 0
-#if (RTE_USART3_RTS_PORT_ID_FULL == 0)
-#define RTE_USART3_RTS_FULL 0
-#elif (RTE_USART3_RTS_PORT_ID_FULL == 1)
-#define RTE_USART3_RTS_FULL 1
-#define RTE_USART3_RTS_PORT_FULL GPIOD
-#define RTE_USART3_RTS_BIT_FULL 12
-#else
-#error "Invalid USART3_RTS Pin Configuration!"
-#endif
-//
-
-#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
-#error "Invalid USART3 Pin Remap Configuration!"
-#endif
-
-#if (RTE_USART3_REMAP_FULL)
-#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL
-#define RTE_USART3_TX RTE_USART3_TX_FULL
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL
-#define RTE_USART3_RX RTE_USART3_RX_FULL
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL
-#define RTE_USART3_CK RTE_USART3_CK_FULL
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL
-#define RTE_USART3_CTS RTE_USART3_CTS_FULL
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL
-#define RTE_USART3_RTS RTE_USART3_RTS_FULL
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL
-#elif (RTE_USART3_REMAP_PARTIAL)
-#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL
-#define RTE_USART3_TX RTE_USART3_TX_PARTIAL
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL
-#define RTE_USART3_RX RTE_USART3_RX_PARTIAL
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL
-#define RTE_USART3_CK RTE_USART3_CK_PARTIAL
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL
-#define RTE_USART3_CTS RTE_USART3_CTS_DEF
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
-#define RTE_USART3_RTS RTE_USART3_RTS_DEF
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
-#else
-#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP
-#define RTE_USART3_TX RTE_USART3_TX_DEF
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF
-#define RTE_USART3_RX RTE_USART3_RX_DEF
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF
-#define RTE_USART3_CK RTE_USART3_CK_DEF
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF
-#define RTE_USART3_CTS RTE_USART3_CTS_DEF
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
-#define RTE_USART3_RTS RTE_USART3_RTS_DEF
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_USART3_RX_DMA 0
-#define RTE_USART3_RX_DMA_NUMBER 1
-#define RTE_USART3_RX_DMA_CHANNEL 3
-#define RTE_USART3_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_USART3_TX_DMA 0
-#define RTE_USART3_TX_DMA_NUMBER 1
-#define RTE_USART3_TX_DMA_CHANNEL 2
-#define RTE_USART3_TX_DMA_PRIORITY 0
-
-//
-
-
-// UART4 (Universal asynchronous receiver transmitter)
-// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
-#define RTE_UART4 0
-#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// UART4_TX Pin <0=>Not Used <1=>PC10
-#define RTE_UART4_TX_ID 0
-#if (RTE_UART4_TX_ID == 0)
-#define RTE_UART4_TX 0
-#elif (RTE_UART4_TX_ID == 1)
-#define RTE_UART4_TX 1
-#define RTE_UART4_TX_PORT GPIOC
-#define RTE_UART4_TX_BIT 10
-#else
-#error "Invalid UART4_TX Pin Configuration!"
-#endif
-
-// UART4_RX Pin <0=>Not Used <1=>PC11
-#define RTE_UART4_RX_ID 0
-#if (RTE_UART4_RX_ID == 0)
-#define RTE_UART4_RX 0
-#elif (RTE_UART4_RX_ID == 1)
-#define RTE_UART4_RX 1
-#define RTE_UART4_RX_PORT GPIOC
-#define RTE_UART4_RX_BIT 11
-#else
-#error "Invalid UART4_RX Pin Configuration!"
-#endif
-
-
-// DMA Rx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_UART4_RX_DMA 0
-#define RTE_UART4_RX_DMA_NUMBER 2
-#define RTE_UART4_RX_DMA_CHANNEL 3
-#define RTE_UART4_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_UART4_TX_DMA 0
-#define RTE_UART4_TX_DMA_NUMBER 2
-#define RTE_UART4_TX_DMA_CHANNEL 5
-#define RTE_UART4_TX_DMA_PRIORITY 0
-
-//
-
-
-// UART5 (Universal asynchronous receiver transmitter)
-// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
-#define RTE_UART5 0
-#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// UART5_TX Pin <0=>Not Used <1=>PC12
-#define RTE_UART5_TX_ID 0
-#if (RTE_UART5_TX_ID == 0)
-#define RTE_UART5_TX 0
-#elif (RTE_UART5_TX_ID == 1)
-#define RTE_UART5_TX 1
-#define RTE_UART5_TX_PORT GPIOC
-#define RTE_UART5_TX_BIT 12
-#else
-#error "Invalid UART5_TX Pin Configuration!"
-#endif
-
-// UART5_RX Pin <0=>Not Used <1=>PD2
-#define RTE_UART5_RX_ID 0
-#if (RTE_UART5_RX_ID == 0)
-#define RTE_UART5_RX 0
-#elif (RTE_UART5_RX_ID == 1)
-#define RTE_UART5_RX 1
-#define RTE_UART5_RX_PORT GPIOD
-#define RTE_UART5_RX_BIT 2
-#else
-#error "Invalid UART5_RX Pin Configuration!"
-#endif
-//
-
-
-// I2C1 (Inter-integrated Circuit Interface 1)
-// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
-#define RTE_I2C1 0
-
-// I2C1_SCL Pin <0=>PB6
-#define RTE_I2C1_SCL_PORT_ID_DEF 0
-#if (RTE_I2C1_SCL_PORT_ID_DEF == 0)
-#define RTE_I2C1_SCL_PORT_DEF GPIOB
-#define RTE_I2C1_SCL_BIT_DEF 6
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1_SDA Pin <0=>PB7
-#define RTE_I2C1_SDA_PORT_ID_DEF 0
-#if (RTE_I2C1_SDA_PORT_ID_DEF == 0)
-#define RTE_I2C1_SDA_PORT_DEF GPIOB
-#define RTE_I2C1_SDA_BIT_DEF 7
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1 Pin Remap
-// Enable I2C1 Pin Remapping
-#define RTE_I2C1_REMAP_FULL 0
-
-// I2C1_SCL Pin <0=>PB8
-#define RTE_I2C1_SCL_PORT_ID_FULL 0
-#if (RTE_I2C1_SCL_PORT_ID_FULL == 0)
-#define RTE_I2C1_SCL_PORT_FULL GPIOB
-#define RTE_I2C1_SCL_BIT_FULL 8
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1_SDA Pin <0=>PB9
-#define RTE_I2C1_SDA_PORT_ID_FULL 0
-#if (RTE_I2C1_SDA_PORT_ID_FULL == 0)
-#define RTE_I2C1_SDA_PORT_FULL GPIOB
-#define RTE_I2C1_SDA_BIT_FULL 9
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_I2C1_REMAP_FULL)
-#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP
-#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL
-#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL
-#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL
-#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL
-#else
-#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP
-#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF
-#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF
-#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF
-#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF
-#endif
-
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <7=>7
-// Selects DMA Channel (only Channel 7 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C1_RX_DMA 0
-#define RTE_I2C1_RX_DMA_NUMBER 1
-#define RTE_I2C1_RX_DMA_CHANNEL 7
-#define RTE_I2C1_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <6=>6
-// Selects DMA Channel (only Channel 6 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C1_TX_DMA 0
-#define RTE_I2C1_TX_DMA_NUMBER 1
-#define RTE_I2C1_TX_DMA_CHANNEL 6
-#define RTE_I2C1_TX_DMA_PRIORITY 0
-
-//
-
-
-// I2C2 (Inter-integrated Circuit Interface 2)
-// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
-#define RTE_I2C2 0
-#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// I2C2_SCL Pin <0=>PB10
-#define RTE_I2C2_SCL_PORT_ID 0
-#if (RTE_I2C2_SCL_PORT_ID == 0)
-#define RTE_I2C2_SCL_PORT GPIOB
-#define RTE_I2C2_SCL_BIT 10
-#else
-#error "Invalid I2C2_SCL Pin Configuration!"
-#endif
-
-// I2C2_SDA Pin <0=>PB11
-#define RTE_I2C2_SDA_PORT_ID 0
-#if (RTE_I2C2_SDA_PORT_ID == 0)
-#define RTE_I2C2_SDA_PORT GPIOB
-#define RTE_I2C2_SDA_BIT 11
-#else
-#error "Invalid I2C2_SCL Pin Configuration!"
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C2_RX_DMA 1
-#define RTE_I2C2_RX_DMA_NUMBER 1
-#define RTE_I2C2_RX_DMA_CHANNEL 5
-#define RTE_I2C2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C2_TX_DMA 1
-#define RTE_I2C2_TX_DMA_NUMBER 1
-#define RTE_I2C2_TX_DMA_CHANNEL 4
-#define RTE_I2C2_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
-// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
-#define RTE_SPI1 0
-
-// SPI1_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI1_NSS_PIN 1
-#define RTE_SPI1_NSS_PORT GPIO_PORT(0)
-#define RTE_SPI1_NSS_BIT 4
-
-// SPI1_SCK Pin <0=>PA5
-#define RTE_SPI1_SCK_PORT_ID_DEF 0
-#if (RTE_SPI1_SCK_PORT_ID_DEF == 0)
-#define RTE_SPI1_SCK_PORT_DEF GPIOA
-#define RTE_SPI1_SCK_BIT_DEF 5
-#else
-#error "Invalid SPI1_SCK Pin Configuration!"
-#endif
-
-// SPI1_MISO Pin <0=>Not Used <1=>PA6
-#define RTE_SPI1_MISO_PORT_ID_DEF 0
-#if (RTE_SPI1_MISO_PORT_ID_DEF == 0)
-#define RTE_SPI1_MISO_DEF 0
-#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1)
-#define RTE_SPI1_MISO_DEF 1
-#define RTE_SPI1_MISO_PORT_DEF GPIOA
-#define RTE_SPI1_MISO_BIT_DEF 6
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-
-// SPI1_MOSI Pin <0=>Not Used <1=>PA7
-#define RTE_SPI1_MOSI_PORT_ID_DEF 0
-#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
-#define RTE_SPI1_MOSI_DEF 0
-#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
-#define RTE_SPI1_MOSI_DEF 1
-#define RTE_SPI1_MOSI_PORT_DEF GPIOA
-#define RTE_SPI1_MOSI_BIT_DEF 7
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-
-// SPI1 Pin Remap
-// Enable SPI1 Pin Remapping.
-#define RTE_SPI1_REMAP 0
-
-// SPI1_SCK Pin <0=>PB3
-#define RTE_SPI1_SCK_PORT_ID_FULL 0
-#if (RTE_SPI1_SCK_PORT_ID_FULL == 0)
-#define RTE_SPI1_SCK_PORT_FULL GPIOB
-#define RTE_SPI1_SCK_BIT_FULL 3
-#else
-#error "Invalid SPI1_SCK Pin Configuration!"
-#endif
-
-// SPI1_MISO Pin <0=>Not Used <1=>PB4
-#define RTE_SPI1_MISO_PORT_ID_FULL 0
-#if (RTE_SPI1_MISO_PORT_ID_FULL == 0)
-#define RTE_SPI1_MISO_FULL 0
-#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1)
-#define RTE_SPI1_MISO_FULL 1
-#define RTE_SPI1_MISO_PORT_FULL GPIOB
-#define RTE_SPI1_MISO_BIT_FULL 4
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-// SPI1_MOSI Pin <0=>Not Used <1=>PB5
-#define RTE_SPI1_MOSI_PORT_ID_FULL 0
-#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
-#define RTE_SPI1_MOSI_FULL 0
-#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
-#define RTE_SPI1_MOSI_FULL 1
-#define RTE_SPI1_MOSI_PORT_FULL GPIOB
-#define RTE_SPI1_MOSI_BIT_FULL 5
-#else
-#error "Invalid SPI1_MOSI Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_SPI1_REMAP)
-#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP
-#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL
-#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL
-#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL
-#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL
-#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL
-#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL
-#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL
-#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL
-#else
-#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP
-#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF
-#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF
-#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF
-#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF
-#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF
-#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF
-#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF
-#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI1_RX_DMA 0
-#define RTE_SPI1_RX_DMA_NUMBER 1
-#define RTE_SPI1_RX_DMA_CHANNEL 2
-#define RTE_SPI1_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI1_TX_DMA 0
-#define RTE_SPI1_TX_DMA_NUMBER 1
-#define RTE_SPI1_TX_DMA_CHANNEL 3
-#define RTE_SPI1_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
-// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
-#define RTE_SPI2 0
-
-// SPI2_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI2_NSS_PIN 1
-#define RTE_SPI2_NSS_PORT GPIO_PORT(1)
-#define RTE_SPI2_NSS_BIT 12
-
-// SPI2_SCK Pin <0=>PB13
-#define RTE_SPI2_SCK_PORT_ID 0
-#if (RTE_SPI2_SCK_PORT_ID == 0)
-#define RTE_SPI2_SCK_PORT GPIOB
-#define RTE_SPI2_SCK_BIT 13
-#define RTE_SPI2_SCK_REMAP 0
-#else
-#error "Invalid SPI2_SCK Pin Configuration!"
-#endif
-
-// SPI2_MISO Pin <0=>Not Used <1=>PB14
-#define RTE_SPI2_MISO_PORT_ID 0
-#if (RTE_SPI2_MISO_PORT_ID == 0)
-#define RTE_SPI2_MISO 0
-#elif (RTE_SPI2_MISO_PORT_ID == 1)
-#define RTE_SPI2_MISO 1
-#define RTE_SPI2_MISO_PORT GPIOB
-#define RTE_SPI2_MISO_BIT 14
-#define RTE_SPI2_MISO_REMAP 0
-#else
-#error "Invalid SPI2_MISO Pin Configuration!"
-#endif
-
-// SPI2_MOSI Pin <0=>Not Used <1=>PB15
-#define RTE_SPI2_MOSI_PORT_ID 0
-#if (RTE_SPI2_MOSI_PORT_ID == 0)
-#define RTE_SPI2_MOSI 0
-#elif (RTE_SPI2_MOSI_PORT_ID == 1)
-#define RTE_SPI2_MOSI 1
-#define RTE_SPI2_MOSI_PORT GPIOB
-#define RTE_SPI2_MOSI_BIT 15
-#define RTE_SPI2_MOSI_REMAP 0
-#else
-#error "Invalid SPI2_MISO Pin Configuration!"
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI2_RX_DMA 0
-#define RTE_SPI2_RX_DMA_NUMBER 1
-#define RTE_SPI2_RX_DMA_CHANNEL 4
-#define RTE_SPI2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI2_TX_DMA 0
-#define RTE_SPI2_TX_DMA_NUMBER 1
-#define RTE_SPI2_TX_DMA_CHANNEL 5
-#define RTE_SPI2_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
-// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
-#define RTE_SPI3 0
-
-// SPI3_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI3_NSS_PIN 1
-#define RTE_SPI3_NSS_PORT GPIO_PORT(0)
-#define RTE_SPI3_NSS_BIT 15
-
-// SPI3_SCK Pin <0=>PB3
-#define RTE_SPI3_SCK_PORT_ID_DEF 0
-#if (RTE_SPI3_SCK_PORT_ID_DEF == 0)
-#define RTE_SPI3_SCK_PORT_DEF GPIOB
-#define RTE_SPI3_SCK_BIT_DEF 3
-#else
-#error "Invalid SPI3_SCK Pin Configuration!"
-#endif
-
-// SPI3_MISO Pin <0=>Not Used <1=>PB4
-#define RTE_SPI3_MISO_PORT_ID_DEF 0
-#if (RTE_SPI3_MISO_PORT_ID_DEF == 0)
-#define RTE_SPI3_MISO_DEF 0
-#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1)
-#define RTE_SPI3_MISO_DEF 1
-#define RTE_SPI3_MISO_PORT_DEF GPIOB
-#define RTE_SPI3_MISO_BIT_DEF 4
-#else
-#error "Invalid SPI3_MISO Pin Configuration!"
-#endif
-
-// SPI3_MOSI <0=>Not Used Pin <1=>PB5
-#define RTE_SPI3_MOSI_PORT_ID_DEF 0
-#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
-#define RTE_SPI3_MOSI_DEF 0
-#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
-#define RTE_SPI3_MOSI_DEF 1
-#define RTE_SPI3_MOSI_PORT_DEF GPIOB
-#define RTE_SPI3_MOSI_BIT_DEF 5
-#else
-#error "Invalid SPI3_MOSI Pin Configuration!"
-#endif
-
-// SPI3 Pin Remap
-// Enable SPI3 Pin Remapping.
-// SPI 3 Pin Remapping is available only in connectivity line devices!
-#define RTE_SPI3_REMAP 0
-
-// SPI3_SCK Pin <0=>PC10
-#define RTE_SPI3_SCK_PORT_ID_FULL 0
-#if (RTE_SPI3_SCK_PORT_ID_FULL == 0)
-#define RTE_SPI3_SCK_PORT_FULL GPIOC
-#define RTE_SPI3_SCK_BIT_FULL 10
-#else
-#error "Invalid SPI3_SCK Pin Configuration!"
-#endif
-
-// SPI3_MISO Pin <0=>Not Used <1=>PC11
-#define RTE_SPI3_MISO_PORT_ID_FULL 0
-#if (RTE_SPI3_MISO_PORT_ID_FULL == 0)
-#define RTE_SPI3_MISO_FULL 0
-#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1)
-#define RTE_SPI3_MISO_FULL 1
-#define RTE_SPI3_MISO_PORT_FULL GPIOC
-#define RTE_SPI3_MISO_BIT_FULL 11
-#else
-#error "Invalid SPI3_MISO Pin Configuration!"
-#endif
-// SPI3_MOSI Pin <0=>Not Used <1=>PC12
-#define RTE_SPI3_MOSI_PORT_ID_FULL 0
-#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
-#define RTE_SPI3_MOSI_FULL 0
-#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
-#define RTE_SPI3_MOSI_FULL 1
-#define RTE_SPI3_MOSI_PORT_FULL GPIOC
-#define RTE_SPI3_MOSI_BIT_FULL 12
-#else
-#error "Invalid SPI3_MOSI Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_SPI3_REMAP)
-#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP
-#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL
-#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL
-#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL
-#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL
-#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL
-#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL
-#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL
-#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL
-#else
-#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP
-#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF
-#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF
-#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF
-#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF
-#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF
-#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF
-#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF
-#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <1=>1
-// Selects DMA Channel (only Channel 1 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI3_RX_DMA 0
-#define RTE_SPI3_RX_DMA_NUMBER 2
-#define RTE_SPI3_RX_DMA_CHANNEL 1
-#define RTE_SPI3_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI3_TX_DMA 0
-#define RTE_SPI3_TX_DMA_NUMBER 2
-#define RTE_SPI3_TX_DMA_CHANNEL 2
-#define RTE_SPI3_TX_DMA_PRIORITY 0
-
-//
-
-
-// SDIO (Secure Digital Input/Output) [Driver_MCI0]
-// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
-#define RTE_SDIO 0
-
-// SDIO Peripheral Bus
-// SDIO_CK Pin <0=>PC12
-#define RTE_SDIO_CK_PORT_ID 0
-#if (RTE_SDIO_CK_PORT_ID == 0)
- #define RTE_SDIO_CK_PORT GPIOC
- #define RTE_SDIO_CK_PIN 12
-#else
- #error "Invalid SDIO_CLK Pin Configuration!"
-#endif
-// SDIO_CMD Pin <0=>PD2
-#define RTE_SDIO_CMD_PORT_ID 0
-#if (RTE_SDIO_CMD_PORT_ID == 0)
- #define RTE_SDIO_CMD_PORT GPIOD
- #define RTE_SDIO_CMD_PIN 2
-#else
- #error "Invalid SDIO_CMD Pin Configuration!"
-#endif
-// SDIO_D0 Pin <0=>PC8
-#define RTE_SDIO_D0_PORT_ID 0
-#if (RTE_SDIO_D0_PORT_ID == 0)
- #define RTE_SDIO_D0_PORT GPIOC
- #define RTE_SDIO_D0_PIN 8
-#else
- #error "Invalid SDIO_DAT0 Pin Configuration!"
-#endif
-// SDIO_D[1 .. 3]
-#define RTE_SDIO_BUS_WIDTH_4 1
-// SDIO_D1 Pin <0=>PC9
-#define RTE_SDIO_D1_PORT_ID 0
-#if (RTE_SDIO_D1_PORT_ID == 0)
- #define RTE_SDIO_D1_PORT GPIOC
- #define RTE_SDIO_D1_PIN 9
-#else
- #error "Invalid SDIO_D1 Pin Configuration!"
-#endif
-// SDIO_D2 Pin <0=>PC10
-#define RTE_SDIO_D2_PORT_ID 0
-#if (RTE_SDIO_D2_PORT_ID == 0)
- #define RTE_SDIO_D2_PORT GPIOC
- #define RTE_SDIO_D2_PIN 10
-#else
- #error "Invalid SDIO_D2 Pin Configuration!"
-#endif
-// SDIO_D3 Pin <0=>PC11
-#define RTE_SDIO_D3_PORT_ID 0
-#if (RTE_SDIO_D3_PORT_ID == 0)
- #define RTE_SDIO_D3_PORT GPIOC
- #define RTE_SDIO_D3_PIN 11
-#else
- #error "Invalid SDIO_D3 Pin Configuration!"
-#endif
-// SDIO_D[1 .. 3]
-// SDIO_D[4 .. 7]
-#define RTE_SDIO_BUS_WIDTH_8 0
-// SDIO_D4 Pin <0=>PB8
-#define RTE_SDIO_D4_PORT_ID 0
-#if (RTE_SDIO_D4_PORT_ID == 0)
- #define RTE_SDIO_D4_PORT GPIOB
- #define RTE_SDIO_D4_PIN 8
-#else
- #error "Invalid SDIO_D4 Pin Configuration!"
-#endif
-// SDIO_D5 Pin <0=>PB9
-#define RTE_SDIO_D5_PORT_ID 0
-#if (RTE_SDIO_D5_PORT_ID == 0)
- #define RTE_SDIO_D5_PORT GPIOB
- #define RTE_SDIO_D5_PIN 9
-#else
- #error "Invalid SDIO_D5 Pin Configuration!"
-#endif
-// SDIO_D6 Pin <0=>PC6
-#define RTE_SDIO_D6_PORT_ID 0
-#if (RTE_SDIO_D6_PORT_ID == 0)
- #define RTE_SDIO_D6_PORT GPIOC
- #define RTE_SDIO_D6_PIN 6
-#else
- #error "Invalid SDIO_D6 Pin Configuration!"
-#endif
-// SDIO_D7 Pin <0=>PC7
-#define RTE_SDIO_D7_PORT_ID 0
-#if (RTE_SDIO_D7_PORT_ID == 0)
- #define RTE_SDIO_D7_PORT GPIOC
- #define RTE_SDIO_D7_PIN 7
-#else
- #error "Invalid SDIO_D7 Pin Configuration!"
-#endif
-// SDIO_D[4 .. 7]
-// SDIO Peripheral Bus
-
-// Card Detect Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SDIO_CD_EN 1
-#define RTE_SDIO_CD_ACTIVE 0
-#define RTE_SDIO_CD_PORT GPIO_PORT(5)
-#define RTE_SDIO_CD_PIN 11
-
-// Write Protect Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SDIO_WP_EN 0
-#define RTE_SDIO_WP_ACTIVE 1
-#define RTE_SDIO_WP_PORT GPIO_PORT(0)
-#define RTE_SDIO_WP_PIN 10
-
-// DMA
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SDIO_DMA_NUMBER 2
-#define RTE_SDIO_DMA_CHANNEL 4
-#define RTE_SDIO_DMA_PRIORITY 0
-
-//
-
-
-// CAN1 (Controller Area Network 1) [Driver_CAN1]
-// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
-#define RTE_CAN1 0
-
-// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
-#define RTE_CAN1_RX_PORT_ID 0
-#if (RTE_CAN1_RX_PORT_ID == 0)
-#define RTE_CAN1_RX_PORT GPIOA
-#define RTE_CAN1_RX_BIT 11
-#elif (RTE_CAN1_RX_PORT_ID == 1)
-#define RTE_CAN1_RX_PORT GPIOB
-#define RTE_CAN1_RX_BIT 8
-#elif (RTE_CAN1_RX_PORT_ID == 2)
-#define RTE_CAN1_RX_PORT GPIOD
-#define RTE_CAN1_RX_BIT 0
-#else
-#error "Invalid CAN1_RX Pin Configuration!"
-#endif
-
-// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
-#define RTE_CAN1_TX_PORT_ID 0
-#if (RTE_CAN1_TX_PORT_ID == 0)
-#define RTE_CAN1_TX_PORT GPIOA
-#define RTE_CAN1_TX_BIT 12
-#elif (RTE_CAN1_TX_PORT_ID == 1)
-#define RTE_CAN1_TX_PORT GPIOB
-#define RTE_CAN1_TX_BIT 9
-#elif (RTE_CAN1_TX_PORT_ID == 2)
-#define RTE_CAN1_TX_PORT GPIOD
-#define RTE_CAN1_TX_BIT 1
-#else
-#error "Invalid CAN1_TX Pin Configuration!"
-#endif
-
-//
-
-
-// CAN2 (Controller Area Network 2) [Driver_CAN2]
-// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
-#define RTE_CAN2 0
-
-// CAN2_RX Pin <0=>PB5 <1=>PB12
-#define RTE_CAN2_RX_PORT_ID 0
-#if (RTE_CAN2_RX_PORT_ID == 0)
-#define RTE_CAN2_RX_PORT GPIOB
-#define RTE_CAN2_RX_BIT 5
-#elif (RTE_CAN2_RX_PORT_ID == 1)
-#define RTE_CAN2_RX_PORT GPIOB
-#define RTE_CAN2_RX_BIT 12
-#else
-#error "Invalid CAN2_RX Pin Configuration!"
-#endif
-
-// CAN2_TX Pin <0=>PB6 <1=>PB13
-#define RTE_CAN2_TX_PORT_ID 0
-#if (RTE_CAN2_TX_PORT_ID == 0)
-#define RTE_CAN2_TX_PORT GPIOB
-#define RTE_CAN2_TX_BIT 6
-#elif (RTE_CAN2_TX_PORT_ID == 1)
-#define RTE_CAN2_TX_PORT GPIOB
-#define RTE_CAN2_TX_BIT 13
-#else
-#error "Invalid CAN2_TX Pin Configuration!"
-#endif
-
-//
-
-
-// ETH (Ethernet Interface) [Driver_ETH_MAC0]
-// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
-#define RTE_ETH 0
-
-// MII (Media Independent Interface)
-// Enable Media Independent Interface pin configuration
-#define RTE_ETH_MII 0
-
-// ETH_MII_TX_CLK Pin <0=>PC3
-#define RTE_ETH_MII_TX_CLK_PORT_ID 0
-#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
-#define RTE_ETH_MII_TX_CLK_PORT GPIOC
-#define RTE_ETH_MII_TX_CLK_PIN 3
-#else
-#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
-#endif
-// ETH_MII_TXD0 Pin <0=>PB12
-#define RTE_ETH_MII_TXD0_PORT_ID 0
-#if (RTE_ETH_MII_TXD0_PORT_ID == 0)
-#define RTE_ETH_MII_TXD0_PORT GPIOB
-#define RTE_ETH_MII_TXD0_PIN 12
-#else
-#error "Invalid ETH_MII_TXD0 Pin Configuration!"
-#endif
-// ETH_MII_TXD1 Pin <0=>PB13
-#define RTE_ETH_MII_TXD1_PORT_ID 0
-#if (RTE_ETH_MII_TXD1_PORT_ID == 0)
-#define RTE_ETH_MII_TXD1_PORT GPIOB
-#define RTE_ETH_MII_TXD1_PIN 13
-#else
-#error "Invalid ETH_MII_TXD1 Pin Configuration!"
-#endif
-// ETH_MII_TXD2 Pin <0=>PC2
-#define RTE_ETH_MII_TXD2_PORT_ID 0
-#if (RTE_ETH_MII_TXD2_PORT_ID == 0)
-#define RTE_ETH_MII_TXD2_PORT GPIOC
-#define RTE_ETH_MII_TXD2_PIN 2
-#else
-#error "Invalid ETH_MII_TXD2 Pin Configuration!"
-#endif
-// ETH_MII_TXD3 Pin <0=>PB8
-#define RTE_ETH_MII_TXD3_PORT_ID 0
-#if (RTE_ETH_MII_TXD3_PORT_ID == 0)
-#define RTE_ETH_MII_TXD3_PORT GPIOB
-#define RTE_ETH_MII_TXD3_PIN 8
-#else
-#error "Invalid ETH_MII_TXD3 Pin Configuration!"
-#endif
-// ETH_MII_TX_EN Pin <0=>PB11
-#define RTE_ETH_MII_TX_EN_PORT_ID 0
-#if (RTE_ETH_MII_TX_EN_PORT_ID == 0)
-#define RTE_ETH_MII_TX_EN_PORT GPIOB
-#define RTE_ETH_MII_TX_EN_PIN 11
-#else
-#error "Invalid ETH_MII_TX_EN Pin Configuration!"
-#endif
-// ETH_MII_RX_CLK Pin <0=>PA1
-#define RTE_ETH_MII_RX_CLK_PORT_ID 0
-#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
-#define RTE_ETH_MII_RX_CLK_PORT GPIOA
-#define RTE_ETH_MII_RX_CLK_PIN 1
-#else
-#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
-#endif
-// ETH_MII_RXD0 Pin <0=>PC4
-#define RTE_ETH_MII_RXD0_DEF 0
-
-// ETH_MII_RXD1 Pin <0=>PC5
-#define RTE_ETH_MII_RXD1_DEF 0
-
-// ETH_MII_RXD2 Pin <0=>PB0
-#define RTE_ETH_MII_RXD2_DEF 0
-
-// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
-#define RTE_ETH_MII_RXD3_DEF 0
-
-// ETH_MII_RX_DV Pin <0=>PA7
-#define RTE_ETH_MII_RX_DV_DEF 0
-
-// ETH_MII_RX_ER Pin <0=>PB10
-#define RTE_ETH_MII_RX_ER_PORT_ID 0
-#if (RTE_ETH_MII_RX_ER_PORT_ID == 0)
-#define RTE_ETH_MII_RX_ER_PORT GPIOB
-#define RTE_ETH_MII_RX_ER_PIN 10
-#else
-#error "Invalid ETH_MII_RX_ER Pin Configuration!"
-#endif
-// ETH_MII_CRS Pin <0=>PA0
-#define RTE_ETH_MII_CRS_PORT_ID 0
-#if (RTE_ETH_MII_CRS_PORT_ID == 0)
-#define RTE_ETH_MII_CRS_PORT GPIOA
-#define RTE_ETH_MII_CRS_PIN 0
-#else
-#error "Invalid ETH_MII_CRS Pin Configuration!"
-#endif
-// ETH_MII_COL Pin <0=>PA3
-#define RTE_ETH_MII_COL_PORT_ID 0
-#if (RTE_ETH_MII_COL_PORT_ID == 0)
-#define RTE_ETH_MII_COL_PORT GPIOA
-#define RTE_ETH_MII_COL_PIN 3
-#else
-#error "Invalid ETH_MII_COL Pin Configuration!"
-#endif
-
-// Ethernet MAC I/O remapping
-// Remap Ethernet pins
-#define RTE_ETH_MII_REMAP 0
-
-// ETH_MII_RXD0 Pin <1=>PD9
-#define RTE_ETH_MII_RXD0_REMAP 1
-
-// ETH_MII_RXD1 Pin <1=>PD10
-#define RTE_ETH_MII_RXD1_REMAP 1
-
-// ETH_MII_RXD2 Pin <1=>PD11
-#define RTE_ETH_MII_RXD2_REMAP 1
-
-// ETH_MII_RXD3 Pin <1=>PD12
-#define RTE_ETH_MII_RXD3_REMAP 1
-
-// ETH_MII_RX_DV Pin <1=>PD8
-#define RTE_ETH_MII_RX_DV_REMAP 1
-//
-
-//
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
-#define RTE_ETH_MII_RXD0_PORT GPIOC
-#define RTE_ETH_MII_RXD0_PIN 4
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
-#define RTE_ETH_MII_RXD0_PORT GPIOD
-#define RTE_ETH_MII_RXD0_PIN 9
-#else
-#error "Invalid ETH_MII_RXD0 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
-#define RTE_ETH_MII_RXD1_PORT GPIOC
-#define RTE_ETH_MII_RXD1_PIN 5
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
-#define RTE_ETH_MII_RXD1_PORT GPIOD
-#define RTE_ETH_MII_RXD1_PIN 10
-#else
-#error "Invalid ETH_MII_RXD1 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
-#define RTE_ETH_MII_RXD2_PORT GPIOB
-#define RTE_ETH_MII_RXD2_PIN 0
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
-#define RTE_ETH_MII_RXD2_PORT GPIOD
-#define RTE_ETH_MII_RXD2_PIN 11
-#else
-#error "Invalid ETH_MII_RXD2 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
-#define RTE_ETH_MII_RXD3_PORT GPIOB
-#define RTE_ETH_MII_RXD3_PIN 1
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
-#define RTE_ETH_MII_RXD3_PORT GPIOD
-#define RTE_ETH_MII_RXD3_PIN 12
-#else
-#error "Invalid ETH_MII_RXD3 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
-#define RTE_ETH_MII_RX_DV_PORT GPIOA
-#define RTE_ETH_MII_RX_DV_PIN 7
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
-#define RTE_ETH_MII_RX_DV_PORT GPIOD
-#define RTE_ETH_MII_RX_DV_PIN 8
-#else
-#error "Invalid ETH_MII_RX_DV Pin Configuration!"
-#endif
-
-// RMII (Reduced Media Independent Interface)
-#define RTE_ETH_RMII 0
-
-// ETH_RMII_TXD0 Pin <0=>PB12
-#define RTE_ETH_RMII_TXD0_PORT_ID 0
-#if (RTE_ETH_RMII_TXD0_PORT_ID == 0)
-#define RTE_ETH_RMII_TXD0_PORT GPIOB
-#define RTE_ETH_RMII_TXD0_PIN 12
-#else
-#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
-#endif
-// ETH_RMII_TXD1 Pin <0=>PB13
-#define RTE_ETH_RMII_TXD1_PORT_ID 0
-#if (RTE_ETH_RMII_TXD1_PORT_ID == 0)
-#define RTE_ETH_RMII_TXD1_PORT GPIOB
-#define RTE_ETH_RMII_TXD1_PIN 13
-#else
-#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
-#endif
-// ETH_RMII_TX_EN Pin <0=>PB11
-#define RTE_ETH_RMII_TX_EN_PORT_ID 0
-#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
-#define RTE_ETH_RMII_TX_EN_PORT GPIOB
-#define RTE_ETH_RMII_TX_EN_PIN 11
-#else
-#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
-#endif
-// ETH_RMII_RXD0 Pin <0=>PC4
-#define RTE_ETH_RMII_RXD0_DEF 0
-
-// ETH_RMII_RXD1 Pin <0=>PC5
-#define RTE_ETH_RMII_RXD1_DEF 0
-
-// ETH_RMII_REF_CLK Pin <0=>PA1
-#define RTE_ETH_RMII_REF_CLK_PORT_ID 0
-#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
-#define RTE_ETH_RMII_REF_CLK_PORT GPIOA
-#define RTE_ETH_RMII_REF_CLK_PIN 1
-#else
-#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
-#endif
-// ETH_RMII_CRS_DV Pin <0=>PA7
-#define RTE_ETH_RMII_CRS_DV_DEF 0
-
-// Ethernet MAC I/O remapping
-// Remap Ethernet pins
-#define RTE_ETH_RMII_REMAP 0
-// ETH_RMII_RXD0 Pin <1=>PD9
-#define RTE_ETH_RMII_RXD0_REMAP 1
-
-// ETH_RMII_RXD1 Pin <1=>PD10
-#define RTE_ETH_RMII_RXD1_REMAP 1
-
-// ETH_RMII_CRS_DV Pin <1=>PD8
-#define RTE_ETH_RMII_CRS_DV_REMAP 1
-//
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
-#define RTE_ETH_RMII_RXD0_PORT GPIOC
-#define RTE_ETH_RMII_RXD0_PIN 4
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
-#define RTE_ETH_RMII_RXD0_PORT GPIOD
-#define RTE_ETH_RMII_RXD0_PIN 9
-#else
-#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
-#define RTE_ETH_RMII_RXD1_PORT GPIOC
-#define RTE_ETH_RMII_RXD1_PIN 5
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
-#define RTE_ETH_RMII_RXD1_PORT GPIOD
-#define RTE_ETH_RMII_RXD1_PIN 10
-#else
-#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
-#define RTE_ETH_RMII_CRS_DV_PORT GPIOA
-#define RTE_ETH_RMII_CRS_DV_PIN 7
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
-#define RTE_ETH_RMII_CRS_DV_PORT GPIOD
-#define RTE_ETH_RMII_CRS_DV_PIN 8
-#else
-#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
-#endif
-
-//
-
-// Management Data Interface
-// ETH_MDC Pin <0=>PC1
-#define RTE_ETH_MDI_MDC_PORT_ID 0
-#if (RTE_ETH_MDI_MDC_PORT_ID == 0)
-#define RTE_ETH_MDI_MDC_PORT GPIOC
-#define RTE_ETH_MDI_MDC_PIN 1
-#else
-#error "Invalid ETH_MDC Pin Configuration!"
-#endif
-// ETH_MDIO Pin <0=>PA2
-#define RTE_ETH_MDI_MDIO_PORT_ID 0
-#if (RTE_ETH_MDI_MDIO_PORT_ID == 0)
-#define RTE_ETH_MDI_MDIO_PORT GPIOA
-#define RTE_ETH_MDI_MDIO_PIN 2
-#else
-#error "Invalid ETH_MDIO Pin Configuration!"
-#endif
-//
-
-// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
-#define RTE_ETH_REF_CLOCK_ID 0
-#if (RTE_ETH_REF_CLOCK_ID == 0)
-#define RTE_ETH_REF_CLOCK 0
-#elif (RTE_ETH_REF_CLOCK_ID == 1)
-#define RTE_ETH_REF_CLOCK 1
-#else
-#error "Invalid MCO Ethernet Reference Clock Configuration!"
-#endif
-//
-
-
-// USB Device Full-speed
-// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
-#define RTE_USB_DEVICE 0
-
-// CON On/Off Pin
-// Configure Pin for driving D+ pull-up
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_USB_DEVICE_CON_PIN 1
-#define RTE_USB_DEVICE_CON_ACTIVE 0
-#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1)
-#define RTE_USB_DEVICE_CON_BIT 14
-
-//
-
-
-// USB OTG Full-speed
-#define RTE_USB_OTG_FS 0
-
-// Host [Driver_USBH0]
-// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
-
-#define RTE_USB_OTG_FS_HOST 0
-
-// VBUS Power On/Off Pin
-// Configure Pin for driving VBUS
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_OTG_FS_VBUS_PIN 1
-#define RTE_OTG_FS_VBUS_ACTIVE 0
-#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2)
-#define RTE_OTG_FS_VBUS_BIT 9
-
-// Overcurrent Detection Pin
-// Configure Pin for overcurrent detection
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_OTG_FS_OC_PIN 1
-#define RTE_OTG_FS_OC_ACTIVE 0
-#define RTE_OTG_FS_OC_PORT GPIO_PORT(4)
-#define RTE_OTG_FS_OC_BIT 1
-//
-
-//
-
-
-#endif /* __RTE_DEVICE_H */
diff --git a/driver_premier_test/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/driver_premier_test/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
deleted file mode 100644
index 74da96c..0000000
--- a/driver_premier_test/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
+++ /dev/null
@@ -1,307 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name : startup_stm32f10x_md.s
-;* Author : MCD Application Team
-;* Version : V3.5.0
-;* Date : 11-March-2011
-;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
-;* toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the clock system
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1_2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
- DCD TIM1_BRK_IRQHandler ; TIM1 Break
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_IRQHandler [WEAK]
- EXPORT TIM1_UP_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/driver_premier_test/RTE/Device/STM32F103RB/system_stm32f10x.c b/driver_premier_test/RTE/Device/STM32F103RB/system_stm32f10x.c
deleted file mode 100644
index 71efc85..0000000
--- a/driver_premier_test/RTE/Device/STM32F103RB/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f10x.c
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * factors, AHB/APBx prescalers and Flash settings).
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f10x_xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
- * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
- * When HSE is used as system clock source, directly or through PLL, and you
- * are using different crystal you have to adapt the HSE value to your own
- * configuration.
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * © COPYRIGHT 2011 STMicroelectronics
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f10x_system
- * @{
- */
-
-/** @addtogroup STM32F10x_System_Private_Includes
- * @{
- */
-
-#include "stm32f10x.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
- frequency (after reset the HSI is used as SYSCLK source)
-
- IMPORTANT NOTE:
- ==============
- 1. After each device reset the HSI is used as System clock source.
-
- 2. Please make sure that the selected System clock doesn't exceed your device's
- maximum frequency.
-
- 3. If none of the define below is enabled, the HSI is used as System clock
- source.
-
- 4. The System clock configuration functions provided within this file assume that:
- - For Low, Medium and High density Value line devices an external 8MHz
- crystal is used to drive the System clock.
- - For Low, Medium and High density devices an external 8MHz crystal is
- used to drive the System clock.
- - For Connectivity line devices an external 25MHz crystal is used to drive
- the System clock.
- If you are using different crystal you have to adapt those functions accordingly.
- */
-
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
- #define SYSCLK_FREQ_24MHz 24000000
-#else
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz 24000000 */
-/* #define SYSCLK_FREQ_36MHz 36000000 */
-/* #define SYSCLK_FREQ_48MHz 48000000 */
-/* #define SYSCLK_FREQ_56MHz 56000000 */
-#define SYSCLK_FREQ_72MHz 72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
- STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Variables
- * @{
- */
-
-/*******************************************************************************
-* Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
- uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
- uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
- static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
- static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
- static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
- static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
- static void SetSysClockTo56(void);
-#elif defined SYSCLK_FREQ_72MHz
- static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
- RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
- RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
- /* Reset PLL2ON and PLL3ON bits */
- RCC->CR &= (uint32_t)0xEBFFFFFF;
-
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x00FF0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#else
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
- #ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
- #endif /* DATA_IN_ExtSRAM */
-#endif
-
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
- /* Configure the Flash Latency cycles and enable prefetch buffer */
- SetSysClock();
-
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
- * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
- * that HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef STM32F10X_CL
- uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
-
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-#ifndef STM32F10X_CL
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- #else
- /* HSE selected as PLL clock entry */
- if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
- {/* HSE oscillator clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
- }
- else
- {
- SystemCoreClock = HSE_VALUE * pllmull;
- }
- #endif
- }
-#else
- pllmull = pllmull >> 18;
-
- if (pllmull != 0x0D)
- {
- pllmull += 2;
- }
- else
- { /* PLL multiplication factor = PLL input clock * 6.5 */
- pllmull = 13 / 2;
- }
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {/* PREDIV1 selected as PLL clock entry */
-
- /* Get PREDIV1 clock source and division factor */
- prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-
- if (prediv1source == 0)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- else
- {/* PLL2 clock selected as PREDIV1 clock entry */
-
- /* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
- SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
- }
- }
-#endif /* STM32F10X_CL */
- break;
-
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
-
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
- SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
- SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
- SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
- SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
- SetSysClockTo56();
-#elif defined SYSCLK_FREQ_72MHz
- SetSysClockTo72();
-#endif
-
- /* If none of the define above is enabled, the HSI is used as System clock
- source (default after reset) */
-}
-
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f10x.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f10x_xx.s/.c before jump to main.
- * This function configures the external SRAM mounted on STM3210E-EVAL
- * board (STM32 High density devices). This SRAM will be used as program
- * data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
- required, then adjust the Register Addresses */
-
- /* Enable FSMC clock */
- RCC->AHBENR = 0x00000114;
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- RCC->APB2ENR = 0x000001E0;
-
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
-/*---------------- SRAM Address lines configuration -------------------------*/
-/*---------------- NOE and NWE configuration --------------------------------*/
-/*---------------- NE3 configuration ----------------------------------------*/
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- GPIOD->CRL = 0x44BB44BB;
- GPIOD->CRH = 0xBBBBBBBB;
-
- GPIOE->CRL = 0xB44444BB;
- GPIOE->CRH = 0xBBBBBBBB;
-
- GPIOF->CRL = 0x44BBBBBB;
- GPIOF->CRH = 0xBBBB4444;
-
- GPIOG->CRL = 0x44BBBBBB;
- GPIOG->CRH = 0x44444B44;
-
-/*---------------- FSMC Configuration ---------------------------------------*/
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
-
- FSMC_Bank1->BTCR[4] = 0x00001011;
- FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSE(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
- if (HSE_VALUE <= 24000000)
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
- }
- else
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
- }
-#endif /* STM32F10X_CL */
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo24(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo36(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-
- /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-#else
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo56(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL7);
-#else
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-#else
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
- RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/driver_premier_test/RTE/_CarteSTM32/RTE_Components.h b/driver_premier_test/RTE/_CarteSTM32/RTE_Components.h
deleted file mode 100644
index 1dbbd10..0000000
--- a/driver_premier_test/RTE/_CarteSTM32/RTE_Components.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'driver_premier_test'
- * Target: 'CarteSTM32'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "stm32f10x.h"
-
-
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/driver_premier_test/RTE/_Target_1/RTE_Components.h b/driver_premier_test/RTE/_Target_1/RTE_Components.h
deleted file mode 100644
index 78979f2..0000000
--- a/driver_premier_test/RTE/_Target_1/RTE_Components.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'driver_premier_test'
- * Target: 'Target 1'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "stm32f10x.h"
-
-
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/timer_act2/Listings/startup_stm32f10x_md.lst b/timer_act2/Listings/startup_stm32f10x_md.lst
deleted file mode 100644
index e0cfc58..0000000
--- a/timer_act2/Listings/startup_stm32f10x_md.lst
+++ /dev/null
@@ -1,1181 +0,0 @@
-
-
-
-ARM Macro Assembler Page 1
-
-
- 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron
- ics ********************
- 2 00000000 ;* File Name : startup_stm32f10x_md.s
- 3 00000000 ;* Author : MCD Application Team
- 4 00000000 ;* Version : V3.5.0
- 5 00000000 ;* Date : 11-March-2011
- 6 00000000 ;* Description : STM32F10x Medium Density Devices
- vector table for MDK-ARM
- 7 00000000 ;* toolchain.
- 8 00000000 ;* This module performs:
- 9 00000000 ;* - Set the initial SP
- 10 00000000 ;* - Set the initial PC == Reset_Ha
- ndler
- 11 00000000 ;* - Set the vector table entries w
- ith the exceptions ISR address
- 12 00000000 ;* - Configure the clock system
- 13 00000000 ;* - Branches to __main in the C li
- brary (which eventually
- 14 00000000 ;* calls main()).
- 15 00000000 ;* After Reset the CortexM3 process
- or is in Thread mode,
- 16 00000000 ;* priority is Privileged, and the
- Stack is set to Main.
- 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
- 18 00000000 ;*******************************************************
- ************************
- 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A
- T PROVIDING CUSTOMERS
- 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR
- DER FOR THEM TO SAVE TIME.
- 21 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB
- LE FOR ANY DIRECT,
- 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
- CLAIMS ARISING FROM THE
- 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM
- ERS OF THE CODING
- 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR
- PRODUCTS.
- 25 00000000 ;*******************************************************
- ************************
- 26 00000000
- 27 00000000 ; Amount of memory (in bytes) allocated for Stack
- 28 00000000 ; Tailor this value to your application needs
- 29 00000000 ; Stack Configuration
- 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
- 31 00000000 ;
- 32 00000000
- 33 00000000 00000400
- Stack_Size
- EQU 0x00000400
- 34 00000000
- 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
-=3
- 36 00000000 Stack_Mem
- SPACE Stack_Size
- 37 00000400 __initial_sp
- 38 00000400
- 39 00000400
- 40 00000400 ; Heap Configuration
-
-
-
-ARM Macro Assembler Page 2
-
-
- 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
- 42 00000400 ;
- 43 00000400
- 44 00000400 00000200
- Heap_Size
- EQU 0x00000200
- 45 00000400
- 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
-3
- 47 00000000 __heap_base
- 48 00000000 Heap_Mem
- SPACE Heap_Size
- 49 00000200 __heap_limit
- 50 00000200
- 51 00000200 PRESERVE8
- 52 00000200 THUMB
- 53 00000200
- 54 00000200
- 55 00000200 ; Vector Table Mapped to Address 0 at Reset
- 56 00000200 AREA RESET, DATA, READONLY
- 57 00000000 EXPORT __Vectors
- 58 00000000 EXPORT __Vectors_End
- 59 00000000 EXPORT __Vectors_Size
- 60 00000000
- 61 00000000 00000000
- __Vectors
- DCD __initial_sp ; Top of Stack
- 62 00000004 00000000 DCD Reset_Handler ; Reset Handler
- 63 00000008 00000000 DCD NMI_Handler ; NMI Handler
- 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
- Handler
- 65 00000010 00000000 DCD MemManage_Handler
- ; MPU Fault Handler
-
- 66 00000014 00000000 DCD BusFault_Handler
- ; Bus Fault Handler
-
- 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul
- t Handler
- 68 0000001C 00000000 DCD 0 ; Reserved
- 69 00000020 00000000 DCD 0 ; Reserved
- 70 00000024 00000000 DCD 0 ; Reserved
- 71 00000028 00000000 DCD 0 ; Reserved
- 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
- 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito
- r Handler
- 74 00000034 00000000 DCD 0 ; Reserved
- 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
-
- 76 0000003C 00000000 DCD SysTick_Handler
- ; SysTick Handler
- 77 00000040
- 78 00000040 ; External Interrupts
- 79 00000040 00000000 DCD WWDG_IRQHandler
- ; Window Watchdog
- 80 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX
- TI Line detect
- 81 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper
- 82 0000004C 00000000 DCD RTC_IRQHandler ; RTC
-
-
-
-ARM Macro Assembler Page 3
-
-
- 83 00000050 00000000 DCD FLASH_IRQHandler ; Flash
- 84 00000054 00000000 DCD RCC_IRQHandler ; RCC
- 85 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0
- 86 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1
- 87 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2
- 88 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3
- 89 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4
- 90 0000006C 00000000 DCD DMA1_Channel1_IRQHandler
- ; DMA1 Channel 1
- 91 00000070 00000000 DCD DMA1_Channel2_IRQHandler
- ; DMA1 Channel 2
- 92 00000074 00000000 DCD DMA1_Channel3_IRQHandler
- ; DMA1 Channel 3
- 93 00000078 00000000 DCD DMA1_Channel4_IRQHandler
- ; DMA1 Channel 4
- 94 0000007C 00000000 DCD DMA1_Channel5_IRQHandler
- ; DMA1 Channel 5
- 95 00000080 00000000 DCD DMA1_Channel6_IRQHandler
- ; DMA1 Channel 6
- 96 00000084 00000000 DCD DMA1_Channel7_IRQHandler
- ; DMA1 Channel 7
- 97 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1_2
- 98 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB
- High Priority or C
- AN1 TX
- 99 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US
- B Low Priority or
- CAN1 RX0
- 100 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- 101 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- 102 0000009C 00000000 DCD EXTI9_5_IRQHandler
- ; EXTI Line 9..5
- 103 000000A0 00000000 DCD TIM1_BRK_IRQHandler
- ; TIM1 Break
- 104 000000A4 00000000 DCD TIM1_UP_IRQHandler
- ; TIM1 Update
- 105 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1
- Trigger and Commuta
- tion
- 106 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
- re Compare
- 107 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2
- 108 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3
- 109 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4
- 110 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event
-
- 111 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error
-
- 112 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event
-
- 113 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error
-
- 114 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1
- 115 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2
- 116 000000D4 00000000 DCD USART1_IRQHandler ; USART1
- 117 000000D8 00000000 DCD USART2_IRQHandler ; USART2
- 118 000000DC 00000000 DCD USART3_IRQHandler ; USART3
- 119 000000E0 00000000 DCD EXTI15_10_IRQHandler
- ; EXTI Line 15..10
-
-
-
-ARM Macro Assembler Page 4
-
-
- 120 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm
- through EXTI Line
- 121 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake
- up from suspend
- 122 000000EC __Vectors_End
- 123 000000EC
- 124 000000EC 000000EC
- __Vectors_Size
- EQU __Vectors_End - __Vectors
- 125 000000EC
- 126 000000EC AREA |.text|, CODE, READONLY
- 127 00000000
- 128 00000000 ; Reset handler
- 129 00000000 Reset_Handler
- PROC
- 130 00000000 EXPORT Reset_Handler [WEAK
-]
- 131 00000000 IMPORT __main
- 132 00000000 IMPORT SystemInit
- 133 00000000 4806 LDR R0, =SystemInit
- 134 00000002 4780 BLX R0
- 135 00000004 4806 LDR R0, =__main
- 136 00000006 4700 BX R0
- 137 00000008 ENDP
- 138 00000008
- 139 00000008 ; Dummy Exception Handlers (infinite loops which can be
- modified)
- 140 00000008
- 141 00000008 NMI_Handler
- PROC
- 142 00000008 EXPORT NMI_Handler [WEA
-K]
- 143 00000008 E7FE B .
- 144 0000000A ENDP
- 146 0000000A HardFault_Handler
- PROC
- 147 0000000A EXPORT HardFault_Handler [WEA
-K]
- 148 0000000A E7FE B .
- 149 0000000C ENDP
- 151 0000000C MemManage_Handler
- PROC
- 152 0000000C EXPORT MemManage_Handler [WEA
-K]
- 153 0000000C E7FE B .
- 154 0000000E ENDP
- 156 0000000E BusFault_Handler
- PROC
- 157 0000000E EXPORT BusFault_Handler [WEA
-K]
- 158 0000000E E7FE B .
- 159 00000010 ENDP
- 161 00000010 UsageFault_Handler
- PROC
- 162 00000010 EXPORT UsageFault_Handler [WEA
-K]
- 163 00000010 E7FE B .
- 164 00000012 ENDP
- 165 00000012 SVC_Handler
-
-
-
-ARM Macro Assembler Page 5
-
-
- PROC
- 166 00000012 EXPORT SVC_Handler [WEA
-K]
- 167 00000012 E7FE B .
- 168 00000014 ENDP
- 170 00000014 DebugMon_Handler
- PROC
- 171 00000014 EXPORT DebugMon_Handler [WEA
-K]
- 172 00000014 E7FE B .
- 173 00000016 ENDP
- 174 00000016 PendSV_Handler
- PROC
- 175 00000016 EXPORT PendSV_Handler [WEA
-K]
- 176 00000016 E7FE B .
- 177 00000018 ENDP
- 178 00000018 SysTick_Handler
- PROC
- 179 00000018 EXPORT SysTick_Handler [WEA
-K]
- 180 00000018 E7FE B .
- 181 0000001A ENDP
- 182 0000001A
- 183 0000001A Default_Handler
- PROC
- 184 0000001A
- 185 0000001A EXPORT WWDG_IRQHandler [WEA
-K]
- 186 0000001A EXPORT PVD_IRQHandler [WEA
-K]
- 187 0000001A EXPORT TAMPER_IRQHandler [WEA
-K]
- 188 0000001A EXPORT RTC_IRQHandler [WEA
-K]
- 189 0000001A EXPORT FLASH_IRQHandler [WEA
-K]
- 190 0000001A EXPORT RCC_IRQHandler [WEA
-K]
- 191 0000001A EXPORT EXTI0_IRQHandler [WEA
-K]
- 192 0000001A EXPORT EXTI1_IRQHandler [WEA
-K]
- 193 0000001A EXPORT EXTI2_IRQHandler [WEA
-K]
- 194 0000001A EXPORT EXTI3_IRQHandler [WEA
-K]
- 195 0000001A EXPORT EXTI4_IRQHandler [WEA
-K]
- 196 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA
-K]
- 197 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA
-K]
- 198 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA
-K]
- 199 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA
-K]
- 200 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA
-K]
-
-
-
-ARM Macro Assembler Page 6
-
-
- 201 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA
-K]
- 202 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA
-K]
- 203 0000001A EXPORT ADC1_2_IRQHandler [WEA
-K]
- 204 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA
-K]
- 205 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA
-K]
- 206 0000001A EXPORT CAN1_RX1_IRQHandler [WEA
-K]
- 207 0000001A EXPORT CAN1_SCE_IRQHandler [WEA
-K]
- 208 0000001A EXPORT EXTI9_5_IRQHandler [WEA
-K]
- 209 0000001A EXPORT TIM1_BRK_IRQHandler [WEA
-K]
- 210 0000001A EXPORT TIM1_UP_IRQHandler [WEA
-K]
- 211 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA
-K]
- 212 0000001A EXPORT TIM1_CC_IRQHandler [WEA
-K]
- 213 0000001A EXPORT TIM2_IRQHandler [WEA
-K]
- 214 0000001A EXPORT TIM3_IRQHandler [WEA
-K]
- 215 0000001A EXPORT TIM4_IRQHandler [WEA
-K]
- 216 0000001A EXPORT I2C1_EV_IRQHandler [WEA
-K]
- 217 0000001A EXPORT I2C1_ER_IRQHandler [WEA
-K]
- 218 0000001A EXPORT I2C2_EV_IRQHandler [WEA
-K]
- 219 0000001A EXPORT I2C2_ER_IRQHandler [WEA
-K]
- 220 0000001A EXPORT SPI1_IRQHandler [WEA
-K]
- 221 0000001A EXPORT SPI2_IRQHandler [WEA
-K]
- 222 0000001A EXPORT USART1_IRQHandler [WEA
-K]
- 223 0000001A EXPORT USART2_IRQHandler [WEA
-K]
- 224 0000001A EXPORT USART3_IRQHandler [WEA
-K]
- 225 0000001A EXPORT EXTI15_10_IRQHandler [WEA
-K]
- 226 0000001A EXPORT RTCAlarm_IRQHandler [WEA
-K]
- 227 0000001A EXPORT USBWakeUp_IRQHandler [WEA
-K]
- 228 0000001A
- 229 0000001A WWDG_IRQHandler
- 230 0000001A PVD_IRQHandler
- 231 0000001A TAMPER_IRQHandler
- 232 0000001A RTC_IRQHandler
-
-
-
-ARM Macro Assembler Page 7
-
-
- 233 0000001A FLASH_IRQHandler
- 234 0000001A RCC_IRQHandler
- 235 0000001A EXTI0_IRQHandler
- 236 0000001A EXTI1_IRQHandler
- 237 0000001A EXTI2_IRQHandler
- 238 0000001A EXTI3_IRQHandler
- 239 0000001A EXTI4_IRQHandler
- 240 0000001A DMA1_Channel1_IRQHandler
- 241 0000001A DMA1_Channel2_IRQHandler
- 242 0000001A DMA1_Channel3_IRQHandler
- 243 0000001A DMA1_Channel4_IRQHandler
- 244 0000001A DMA1_Channel5_IRQHandler
- 245 0000001A DMA1_Channel6_IRQHandler
- 246 0000001A DMA1_Channel7_IRQHandler
- 247 0000001A ADC1_2_IRQHandler
- 248 0000001A USB_HP_CAN1_TX_IRQHandler
- 249 0000001A USB_LP_CAN1_RX0_IRQHandler
- 250 0000001A CAN1_RX1_IRQHandler
- 251 0000001A CAN1_SCE_IRQHandler
- 252 0000001A EXTI9_5_IRQHandler
- 253 0000001A TIM1_BRK_IRQHandler
- 254 0000001A TIM1_UP_IRQHandler
- 255 0000001A TIM1_TRG_COM_IRQHandler
- 256 0000001A TIM1_CC_IRQHandler
- 257 0000001A TIM2_IRQHandler
- 258 0000001A TIM3_IRQHandler
- 259 0000001A TIM4_IRQHandler
- 260 0000001A I2C1_EV_IRQHandler
- 261 0000001A I2C1_ER_IRQHandler
- 262 0000001A I2C2_EV_IRQHandler
- 263 0000001A I2C2_ER_IRQHandler
- 264 0000001A SPI1_IRQHandler
- 265 0000001A SPI2_IRQHandler
- 266 0000001A USART1_IRQHandler
- 267 0000001A USART2_IRQHandler
- 268 0000001A USART3_IRQHandler
- 269 0000001A EXTI15_10_IRQHandler
- 270 0000001A RTCAlarm_IRQHandler
- 271 0000001A USBWakeUp_IRQHandler
- 272 0000001A
- 273 0000001A E7FE B .
- 274 0000001C
- 275 0000001C ENDP
- 276 0000001C
- 277 0000001C ALIGN
- 278 0000001C
- 279 0000001C ;*******************************************************
- ************************
- 280 0000001C ; User Stack and Heap initialization
- 281 0000001C ;*******************************************************
- ************************
- 282 0000001C IF :DEF:__MICROLIB
- 283 0000001C
- 284 0000001C EXPORT __initial_sp
- 285 0000001C EXPORT __heap_base
- 286 0000001C EXPORT __heap_limit
- 287 0000001C
- 288 0000001C ELSE
- 303 ENDIF
-
-
-
-ARM Macro Assembler Page 8
-
-
- 304 0000001C
- 305 0000001C END
- 00000000
- 00000000
-Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
-ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md.
-o -I.\RTE\Device\STM32F103RB -I.\RTE\_carteSTM -IC:\Users\chauz\AppData\Local\A
-rm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Users\chauz\AppData\Local\Arm\
-Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --pre
-define="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 533" --predefine
-="_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --
-list=.\listings\startup_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32f1
-0x_md.s
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-STACK 00000000
-
-Symbol: STACK
- Definitions
- At line 35 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: STACK unused
-Stack_Mem 00000000
-
-Symbol: Stack_Mem
- Definitions
- At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Stack_Mem unused
-__initial_sp 00000400
-
-Symbol: __initial_sp
- Definitions
- At line 37 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 284 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-HEAP 00000000
-
-Symbol: HEAP
- Definitions
- At line 46 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: HEAP unused
-Heap_Mem 00000000
-
-Symbol: Heap_Mem
- Definitions
- At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Heap_Mem unused
-__heap_base 00000000
-
-Symbol: __heap_base
- Definitions
- At line 47 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 285 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __heap_base used once
-__heap_limit 00000200
-
-Symbol: __heap_limit
- Definitions
- At line 49 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 286 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __heap_limit used once
-4 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-RESET 00000000
-
-Symbol: RESET
- Definitions
- At line 56 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: RESET unused
-__Vectors 00000000
-
-Symbol: __Vectors
- Definitions
- At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 57 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-__Vectors_End 000000EC
-
-Symbol: __Vectors_End
- Definitions
- At line 122 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 58 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-.text 00000000
-
-Symbol: .text
- Definitions
- At line 126 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: .text unused
-ADC1_2_IRQHandler 0000001A
-
-Symbol: ADC1_2_IRQHandler
- Definitions
- At line 247 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 97 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 203 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-BusFault_Handler 0000000E
-
-Symbol: BusFault_Handler
- Definitions
- At line 156 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 66 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 157 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-CAN1_RX1_IRQHandler 0000001A
-
-Symbol: CAN1_RX1_IRQHandler
- Definitions
- At line 250 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 100 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 206 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-CAN1_SCE_IRQHandler 0000001A
-
-Symbol: CAN1_SCE_IRQHandler
- Definitions
- At line 251 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 101 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 207 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel1_IRQHandler 0000001A
-
-Symbol: DMA1_Channel1_IRQHandler
- Definitions
- At line 240 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 90 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 196 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel2_IRQHandler 0000001A
-
-Symbol: DMA1_Channel2_IRQHandler
- Definitions
- At line 241 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
-
-
-
-ARM Macro Assembler Page 2 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 91 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 197 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel3_IRQHandler 0000001A
-
-Symbol: DMA1_Channel3_IRQHandler
- Definitions
- At line 242 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 92 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 198 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel4_IRQHandler 0000001A
-
-Symbol: DMA1_Channel4_IRQHandler
- Definitions
- At line 243 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 93 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 199 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel5_IRQHandler 0000001A
-
-Symbol: DMA1_Channel5_IRQHandler
- Definitions
- At line 244 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 94 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 200 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel6_IRQHandler 0000001A
-
-Symbol: DMA1_Channel6_IRQHandler
- Definitions
- At line 245 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 95 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 201 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel7_IRQHandler 0000001A
-
-Symbol: DMA1_Channel7_IRQHandler
- Definitions
- At line 246 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 96 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 202 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DebugMon_Handler 00000014
-
-Symbol: DebugMon_Handler
- Definitions
- At line 170 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 73 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 171 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-Default_Handler 0000001A
-
-
-
-
-ARM Macro Assembler Page 3 Alphabetic symbol ordering
-Relocatable symbols
-
-Symbol: Default_Handler
- Definitions
- At line 183 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- None
-Comment: Default_Handler unused
-EXTI0_IRQHandler 0000001A
-
-Symbol: EXTI0_IRQHandler
- Definitions
- At line 235 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 85 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 191 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI15_10_IRQHandler 0000001A
-
-Symbol: EXTI15_10_IRQHandler
- Definitions
- At line 269 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 119 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 225 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI1_IRQHandler 0000001A
-
-Symbol: EXTI1_IRQHandler
- Definitions
- At line 236 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 86 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 192 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI2_IRQHandler 0000001A
-
-Symbol: EXTI2_IRQHandler
- Definitions
- At line 237 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 87 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 193 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI3_IRQHandler 0000001A
-
-Symbol: EXTI3_IRQHandler
- Definitions
- At line 238 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 88 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 194 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI4_IRQHandler 0000001A
-
-Symbol: EXTI4_IRQHandler
- Definitions
- At line 239 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 89 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 195 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler Page 4 Alphabetic symbol ordering
-Relocatable symbols
-
-
-EXTI9_5_IRQHandler 0000001A
-
-Symbol: EXTI9_5_IRQHandler
- Definitions
- At line 252 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 102 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 208 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-FLASH_IRQHandler 0000001A
-
-Symbol: FLASH_IRQHandler
- Definitions
- At line 233 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 83 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 189 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-HardFault_Handler 0000000A
-
-Symbol: HardFault_Handler
- Definitions
- At line 146 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 64 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 147 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C1_ER_IRQHandler 0000001A
-
-Symbol: I2C1_ER_IRQHandler
- Definitions
- At line 261 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 111 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 217 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C1_EV_IRQHandler 0000001A
-
-Symbol: I2C1_EV_IRQHandler
- Definitions
- At line 260 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 110 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 216 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C2_ER_IRQHandler 0000001A
-
-Symbol: I2C2_ER_IRQHandler
- Definitions
- At line 263 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 113 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 219 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C2_EV_IRQHandler 0000001A
-
-Symbol: I2C2_EV_IRQHandler
- Definitions
-
-
-
-ARM Macro Assembler Page 5 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 262 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 112 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 218 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-MemManage_Handler 0000000C
-
-Symbol: MemManage_Handler
- Definitions
- At line 151 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 65 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 152 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-NMI_Handler 00000008
-
-Symbol: NMI_Handler
- Definitions
- At line 141 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 63 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 142 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-PVD_IRQHandler 0000001A
-
-Symbol: PVD_IRQHandler
- Definitions
- At line 230 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 80 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 186 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-PendSV_Handler 00000016
-
-Symbol: PendSV_Handler
- Definitions
- At line 174 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 75 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 175 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-RCC_IRQHandler 0000001A
-
-Symbol: RCC_IRQHandler
- Definitions
- At line 234 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 84 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 190 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-RTCAlarm_IRQHandler 0000001A
-
-Symbol: RTCAlarm_IRQHandler
- Definitions
- At line 270 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 120 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 226 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-
-ARM Macro Assembler Page 6 Alphabetic symbol ordering
-Relocatable symbols
-
-RTC_IRQHandler 0000001A
-
-Symbol: RTC_IRQHandler
- Definitions
- At line 232 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 82 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 188 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-Reset_Handler 00000000
-
-Symbol: Reset_Handler
- Definitions
- At line 129 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 62 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 130 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SPI1_IRQHandler 0000001A
-
-Symbol: SPI1_IRQHandler
- Definitions
- At line 264 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 114 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 220 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SPI2_IRQHandler 0000001A
-
-Symbol: SPI2_IRQHandler
- Definitions
- At line 265 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 115 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 221 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SVC_Handler 00000012
-
-Symbol: SVC_Handler
- Definitions
- At line 165 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 72 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 166 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SysTick_Handler 00000018
-
-Symbol: SysTick_Handler
- Definitions
- At line 178 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 76 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 179 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TAMPER_IRQHandler 0000001A
-
-Symbol: TAMPER_IRQHandler
- Definitions
- At line 231 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler Page 7 Alphabetic symbol ordering
-Relocatable symbols
-
- Uses
- At line 81 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 187 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_BRK_IRQHandler 0000001A
-
-Symbol: TIM1_BRK_IRQHandler
- Definitions
- At line 253 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 103 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 209 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_CC_IRQHandler 0000001A
-
-Symbol: TIM1_CC_IRQHandler
- Definitions
- At line 256 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 106 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 212 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_TRG_COM_IRQHandler 0000001A
-
-Symbol: TIM1_TRG_COM_IRQHandler
- Definitions
- At line 255 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 105 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 211 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_UP_IRQHandler 0000001A
-
-Symbol: TIM1_UP_IRQHandler
- Definitions
- At line 254 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 104 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 210 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM2_IRQHandler 0000001A
-
-Symbol: TIM2_IRQHandler
- Definitions
- At line 257 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 107 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 213 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM3_IRQHandler 0000001A
-
-Symbol: TIM3_IRQHandler
- Definitions
- At line 258 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 108 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 214 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM4_IRQHandler 0000001A
-
-
-
-ARM Macro Assembler Page 8 Alphabetic symbol ordering
-Relocatable symbols
-
-
-Symbol: TIM4_IRQHandler
- Definitions
- At line 259 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 109 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 215 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART1_IRQHandler 0000001A
-
-Symbol: USART1_IRQHandler
- Definitions
- At line 266 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 116 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 222 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART2_IRQHandler 0000001A
-
-Symbol: USART2_IRQHandler
- Definitions
- At line 267 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 117 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 223 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART3_IRQHandler 0000001A
-
-Symbol: USART3_IRQHandler
- Definitions
- At line 268 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 118 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 224 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USBWakeUp_IRQHandler 0000001A
-
-Symbol: USBWakeUp_IRQHandler
- Definitions
- At line 271 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 121 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 227 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USB_HP_CAN1_TX_IRQHandler 0000001A
-
-Symbol: USB_HP_CAN1_TX_IRQHandler
- Definitions
- At line 248 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 98 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 204 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USB_LP_CAN1_RX0_IRQHandler 0000001A
-
-Symbol: USB_LP_CAN1_RX0_IRQHandler
- Definitions
- At line 249 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
-
-
-
-ARM Macro Assembler Page 9 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 99 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 205 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-UsageFault_Handler 00000010
-
-Symbol: UsageFault_Handler
- Definitions
- At line 161 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 67 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 162 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-WWDG_IRQHandler 0000001A
-
-Symbol: WWDG_IRQHandler
- Definitions
- At line 229 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 79 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- At line 185 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-55 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Absolute symbols
-
-Heap_Size 00000200
-
-Symbol: Heap_Size
- Definitions
- At line 44 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: Heap_Size used once
-Stack_Size 00000400
-
-Symbol: Stack_Size
- Definitions
- At line 33 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: Stack_Size used once
-__Vectors_Size 000000EC
-
-Symbol: __Vectors_Size
- Definitions
- At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 59 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __Vectors_Size used once
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-External symbols
-
-SystemInit 00000000
-
-Symbol: SystemInit
- Definitions
- At line 132 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 133 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: SystemInit used once
-__main 00000000
-
-Symbol: __main
- Definitions
- At line 131 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
- Uses
- At line 135 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __main used once
-2 symbols
-407 symbols in table
diff --git a/timer_act2/Listings/timer_act2.map b/timer_act2/Listings/timer_act2.map
deleted file mode 100644
index 625512b..0000000
--- a/timer_act2/Listings/timer_act2.map
+++ /dev/null
@@ -1,397 +0,0 @@
-Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]
-
-==============================================================================
-
-Section Cross References
-
- principal.o(i.handle_TIM2) refers to driver_gpio.o(i.MyGPIO_Toggle) for MyGPIO_Toggle
- principal.o(i.handle_TIM2) refers to principal.o(.data) for greenLed
- principal.o(i.main) refers to driver_timer.o(i.Activate_TIM) for Activate_TIM
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Activate) for MyGPIO_Activate
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init
- principal.o(i.main) refers to driver_timer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init
- principal.o(i.main) refers to driver_gpio.o(i.MyGPIO_Set) for MyGPIO_Set
- principal.o(i.main) refers to driver_timer.o(i.MyTimer_Active_IT) for MyTimer_Active_IT
- principal.o(i.main) refers to principal.o(.data) for greenLed
- principal.o(i.main) refers to principal.o(i.handle_TIM2) for handle_TIM2
- driver_gpio.o(i.MyGPIO_Init) refers to driver_gpio.o(i.MyGPIO_Set) for MyGPIO_Set
- driver_gpio.o(i.MyGPIO_Toggle) refers to driver_gpio.o(i.MyGPIO_Reset) for MyGPIO_Reset
- driver_gpio.o(i.MyGPIO_Toggle) refers to driver_gpio.o(i.MyGPIO_Set) for MyGPIO_Set
- driver_timer.o(i.MyTimer_Active_IT) refers to driver_timer.o(i.__NVIC_EnableIRQ) for __NVIC_EnableIRQ
- driver_timer.o(i.MyTimer_Active_IT) refers to driver_timer.o(i.__NVIC_SetPriority) for __NVIC_SetPriority
- driver_timer.o(i.MyTimer_Active_IT) refers to driver_timer.o(.data) for IT_function_TIM1
- driver_timer.o(i.TIM1_TRG_COM_IRQHandler) refers to driver_timer.o(.data) for IT_function_TIM1
- driver_timer.o(i.TIM2_IRQHandler) refers to driver_timer.o(.data) for IT_function_TIM2
- driver_timer.o(i.TIM3_IRQHandler) refers to driver_timer.o(.data) for IT_function_TIM3
- driver_timer.o(i.TIM4_IRQHandler) refers to driver_timer.o(.data) for IT_function_TIM4
- startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler
- startup_stm32f10x_md.o(RESET) refers to driver_timer.o(i.TIM1_TRG_COM_IRQHandler) for TIM1_TRG_COM_IRQHandler
- startup_stm32f10x_md.o(RESET) refers to driver_timer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler
- startup_stm32f10x_md.o(RESET) refers to driver_timer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler
- startup_stm32f10x_md.o(RESET) refers to driver_timer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler
- startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
- startup_stm32f10x_md.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
- system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72
- system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock
- system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000F) for __rt_final_cpp
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$00000011) for __rt_final_exit
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry12b.o(.ARM.Collect$$$$0000000E) for __rt_lib_shutdown_fini
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
- entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
- entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
- entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
- entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
- entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
- entry9a.o(.ARM.Collect$$$$0000000B) refers to principal.o(i.main) for main
- entry9b.o(.ARM.Collect$$$$0000000C) refers to principal.o(i.main) for main
- init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
-
-
-==============================================================================
-
-Removing Unused input sections from the image.
-
- Removing principal.o(.rev16_text), (4 bytes).
- Removing principal.o(.revsh_text), (4 bytes).
- Removing principal.o(.rrx_text), (6 bytes).
- Removing driver_gpio.o(.rev16_text), (4 bytes).
- Removing driver_gpio.o(.revsh_text), (4 bytes).
- Removing driver_gpio.o(.rrx_text), (6 bytes).
- Removing driver_gpio.o(i.MyGPIO_Read), (12 bytes).
- Removing driver_timer.o(.rev16_text), (4 bytes).
- Removing driver_timer.o(.revsh_text), (4 bytes).
- Removing driver_timer.o(.rrx_text), (6 bytes).
- Removing startup_stm32f10x_md.o(HEAP), (512 bytes).
- Removing system_stm32f10x.o(.rev16_text), (4 bytes).
- Removing system_stm32f10x.o(.revsh_text), (4 bytes).
- Removing system_stm32f10x.o(.rrx_text), (6 bytes).
- Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes).
- Removing system_stm32f10x.o(.data), (20 bytes).
-
-16 unused section(s) (total 764 bytes) removed from the image.
-
-==============================================================================
-
-Image Symbol Table
-
- Local Symbols
-
- Symbol Name Value Ov Type Size Object(Section)
-
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
- ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
- Includes\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE
- Includes\Driver_TIMER.c 0x00000000 Number 0 driver_timer.o ABSOLUTE
- Includes\\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE
- Includes\\Driver_TIMER.c 0x00000000 Number 0 driver_timer.o ABSOLUTE
- RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE
- RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE
- RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE
- Source\\principal.c 0x00000000 Number 0 principal.o ABSOLUTE
- Source\principal.c 0x00000000 Number 0 principal.o ABSOLUTE
- dc.s 0x00000000 Number 0 dc.o ABSOLUTE
- handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE
- init.s 0x00000000 Number 0 init.o ABSOLUTE
- RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET)
- .ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000)
- .ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001)
- .ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004)
- .ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008)
- .ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A)
- .ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B)
- .ARM.Collect$$$$0000000E 0x080000fc Section 4 entry12b.o(.ARM.Collect$$$$0000000E)
- .ARM.Collect$$$$0000000F 0x08000100 Section 0 entry10a.o(.ARM.Collect$$$$0000000F)
- .ARM.Collect$$$$00000011 0x08000100 Section 0 entry11a.o(.ARM.Collect$$$$00000011)
- .ARM.Collect$$$$00002712 0x08000100 Section 4 entry2.o(.ARM.Collect$$$$00002712)
- __lit__00000000 0x08000100 Data 4 entry2.o(.ARM.Collect$$$$00002712)
- .text 0x08000104 Section 36 startup_stm32f10x_md.o(.text)
- .text 0x08000128 Section 36 init.o(.text)
- i.Activate_TIM 0x0800014c Section 0 driver_timer.o(i.Activate_TIM)
- i.MyGPIO_Activate 0x08000174 Section 0 driver_gpio.o(i.MyGPIO_Activate)
- i.MyGPIO_Init 0x0800018c Section 0 driver_gpio.o(i.MyGPIO_Init)
- i.MyGPIO_Reset 0x08000278 Section 0 driver_gpio.o(i.MyGPIO_Reset)
- i.MyGPIO_Set 0x08000284 Section 0 driver_gpio.o(i.MyGPIO_Set)
- i.MyGPIO_Toggle 0x0800028c Section 0 driver_gpio.o(i.MyGPIO_Toggle)
- i.MyTimer_Active_IT 0x080002b0 Section 0 driver_timer.o(i.MyTimer_Active_IT)
- i.MyTimer_Base_Init 0x08000344 Section 0 driver_timer.o(i.MyTimer_Base_Init)
- i.SetSysClock 0x08000356 Section 0 system_stm32f10x.o(i.SetSysClock)
- SetSysClock 0x08000357 Thumb Code 8 system_stm32f10x.o(i.SetSysClock)
- i.SetSysClockTo72 0x08000360 Section 0 system_stm32f10x.o(i.SetSysClockTo72)
- SetSysClockTo72 0x08000361 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72)
- i.SystemInit 0x08000440 Section 0 system_stm32f10x.o(i.SystemInit)
- i.TIM1_TRG_COM_IRQHandler 0x080004a0 Section 0 driver_timer.o(i.TIM1_TRG_COM_IRQHandler)
- i.TIM2_IRQHandler 0x080004c4 Section 0 driver_timer.o(i.TIM2_IRQHandler)
- i.TIM3_IRQHandler 0x080004e8 Section 0 driver_timer.o(i.TIM3_IRQHandler)
- i.TIM4_IRQHandler 0x0800050c Section 0 driver_timer.o(i.TIM4_IRQHandler)
- i.__NVIC_EnableIRQ 0x08000530 Section 0 driver_timer.o(i.__NVIC_EnableIRQ)
- __NVIC_EnableIRQ 0x08000531 Thumb Code 34 driver_timer.o(i.__NVIC_EnableIRQ)
- i.__NVIC_SetPriority 0x08000554 Section 0 driver_timer.o(i.__NVIC_SetPriority)
- __NVIC_SetPriority 0x08000555 Thumb Code 32 driver_timer.o(i.__NVIC_SetPriority)
- i.__scatterload_copy 0x0800057c Section 14 handlers.o(i.__scatterload_copy)
- i.__scatterload_null 0x0800058a Section 2 handlers.o(i.__scatterload_null)
- i.__scatterload_zeroinit 0x0800058c Section 14 handlers.o(i.__scatterload_zeroinit)
- i.handle_TIM2 0x0800059c Section 0 principal.o(i.handle_TIM2)
- i.main 0x080005b0 Section 0 principal.o(i.main)
- .data 0x20000000 Section 16 principal.o(.data)
- .data 0x20000010 Section 16 driver_timer.o(.data)
- STACK 0x20000020 Section 1024 startup_stm32f10x_md.o(STACK)
-
- Global Symbols
-
- Symbol Name Value Ov Type Size Object(Section)
-
- BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
- __ARM_use_no_argv 0x00000000 Number 0 principal.o ABSOLUTE
- __arm_fini_ - Undefined Weak Reference
- __cpp_initialize__aeabi_ - Undefined Weak Reference
- __cxa_finalize - Undefined Weak Reference
- __decompress - Undefined Weak Reference
- _clock_init - Undefined Weak Reference
- _microlib_exit - Undefined Weak Reference
- __Vectors_Size 0x000000ec Number 0 startup_stm32f10x_md.o ABSOLUTE
- __Vectors 0x08000000 Data 4 startup_stm32f10x_md.o(RESET)
- __Vectors_End 0x080000ec Data 0 startup_stm32f10x_md.o(RESET)
- __main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000)
- _main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001)
- _main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
- __main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
- _main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008)
- _main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A)
- _main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B)
- __rt_lib_shutdown_fini 0x080000fd Thumb Code 0 entry12b.o(.ARM.Collect$$$$0000000E)
- __rt_final_cpp 0x08000101 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000F)
- __rt_final_exit 0x08000101 Thumb Code 0 entry11a.o(.ARM.Collect$$$$00000011)
- Reset_Handler 0x08000105 Thumb Code 8 startup_stm32f10x_md.o(.text)
- NMI_Handler 0x0800010d Thumb Code 2 startup_stm32f10x_md.o(.text)
- HardFault_Handler 0x0800010f Thumb Code 2 startup_stm32f10x_md.o(.text)
- MemManage_Handler 0x08000111 Thumb Code 2 startup_stm32f10x_md.o(.text)
- BusFault_Handler 0x08000113 Thumb Code 2 startup_stm32f10x_md.o(.text)
- UsageFault_Handler 0x08000115 Thumb Code 2 startup_stm32f10x_md.o(.text)
- SVC_Handler 0x08000117 Thumb Code 2 startup_stm32f10x_md.o(.text)
- DebugMon_Handler 0x08000119 Thumb Code 2 startup_stm32f10x_md.o(.text)
- PendSV_Handler 0x0800011b Thumb Code 2 startup_stm32f10x_md.o(.text)
- SysTick_Handler 0x0800011d Thumb Code 2 startup_stm32f10x_md.o(.text)
- ADC1_2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- CAN1_RX1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- CAN1_SCE_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel6_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- DMA1_Channel7_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI15_10_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- EXTI9_5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- FLASH_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C1_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C1_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C2_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- I2C2_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- PVD_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RCC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RTCAlarm_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- RTC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- SPI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- SPI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TAMPER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_BRK_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_CC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- TIM1_UP_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USART3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USBWakeUp_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USB_HP_CAN1_TX_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- USB_LP_CAN1_RX0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- WWDG_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text)
- __scatterload 0x08000129 Thumb Code 28 init.o(.text)
- __scatterload_rt2 0x08000129 Thumb Code 0 init.o(.text)
- Activate_TIM 0x0800014d Thumb Code 36 driver_timer.o(i.Activate_TIM)
- MyGPIO_Activate 0x08000175 Thumb Code 18 driver_gpio.o(i.MyGPIO_Activate)
- MyGPIO_Init 0x0800018d Thumb Code 236 driver_gpio.o(i.MyGPIO_Init)
- MyGPIO_Reset 0x08000279 Thumb Code 12 driver_gpio.o(i.MyGPIO_Reset)
- MyGPIO_Set 0x08000285 Thumb Code 8 driver_gpio.o(i.MyGPIO_Set)
- MyGPIO_Toggle 0x0800028d Thumb Code 36 driver_gpio.o(i.MyGPIO_Toggle)
- MyTimer_Active_IT 0x080002b1 Thumb Code 120 driver_timer.o(i.MyTimer_Active_IT)
- MyTimer_Base_Init 0x08000345 Thumb Code 18 driver_timer.o(i.MyTimer_Base_Init)
- SystemInit 0x08000441 Thumb Code 78 system_stm32f10x.o(i.SystemInit)
- TIM1_TRG_COM_IRQHandler 0x080004a1 Thumb Code 28 driver_timer.o(i.TIM1_TRG_COM_IRQHandler)
- TIM2_IRQHandler 0x080004c5 Thumb Code 32 driver_timer.o(i.TIM2_IRQHandler)
- TIM3_IRQHandler 0x080004e9 Thumb Code 28 driver_timer.o(i.TIM3_IRQHandler)
- TIM4_IRQHandler 0x0800050d Thumb Code 28 driver_timer.o(i.TIM4_IRQHandler)
- __scatterload_copy 0x0800057d Thumb Code 14 handlers.o(i.__scatterload_copy)
- __scatterload_null 0x0800058b Thumb Code 2 handlers.o(i.__scatterload_null)
- __scatterload_zeroinit 0x0800058d Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
- handle_TIM2 0x0800059d Thumb Code 14 principal.o(i.handle_TIM2)
- main 0x080005b1 Thumb Code 98 principal.o(i.main)
- Region$$Table$$Base 0x08000624 Number 0 anon$$obj.o(Region$$Table)
- Region$$Table$$Limit 0x08000644 Number 0 anon$$obj.o(Region$$Table)
- MonTimer 0x20000000 Data 8 principal.o(.data)
- greenLed 0x20000008 Data 8 principal.o(.data)
- IT_function_TIM1 0x20000010 Data 4 driver_timer.o(.data)
- IT_function_TIM2 0x20000014 Data 4 driver_timer.o(.data)
- IT_function_TIM3 0x20000018 Data 4 driver_timer.o(.data)
- IT_function_TIM4 0x2000001c Data 4 driver_timer.o(.data)
- __initial_sp 0x20000420 Data 0 startup_stm32f10x_md.o(STACK)
-
-
-
-==============================================================================
-
-Memory Map of the image
-
- Image Entry point : 0x08000105
-
- Load Region LR_1 (Base: 0x08000000, Size: 0x00000664, Max: 0xffffffff, ABSOLUTE)
-
- Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000644, Max: 0xffffffff, ABSOLUTE)
-
- Exec Addr Load Addr Size Type Attr Idx E Section Name Object
-
- 0x08000000 0x08000000 0x000000ec Data RO 208 RESET startup_stm32f10x_md.o
- 0x080000ec 0x080000ec 0x00000000 Code RO 259 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
- 0x080000ec 0x080000ec 0x00000004 Code RO 262 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
- 0x080000f0 0x080000f0 0x00000004 Code RO 265 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
- 0x080000f4 0x080000f4 0x00000000 Code RO 267 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
- 0x080000f4 0x080000f4 0x00000000 Code RO 269 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
- 0x080000f4 0x080000f4 0x00000008 Code RO 270 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
- 0x080000fc 0x080000fc 0x00000004 Code RO 277 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o)
- 0x08000100 0x08000100 0x00000000 Code RO 272 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o)
- 0x08000100 0x08000100 0x00000000 Code RO 274 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o)
- 0x08000100 0x08000100 0x00000004 Code RO 263 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
- 0x08000104 0x08000104 0x00000024 Code RO 209 * .text startup_stm32f10x_md.o
- 0x08000128 0x08000128 0x00000024 Code RO 278 .text mc_w.l(init.o)
- 0x0800014c 0x0800014c 0x00000028 Code RO 129 i.Activate_TIM driver_timer.o
- 0x08000174 0x08000174 0x00000018 Code RO 72 i.MyGPIO_Activate driver_gpio.o
- 0x0800018c 0x0800018c 0x000000ec Code RO 73 i.MyGPIO_Init driver_gpio.o
- 0x08000278 0x08000278 0x0000000c Code RO 75 i.MyGPIO_Reset driver_gpio.o
- 0x08000284 0x08000284 0x00000008 Code RO 76 i.MyGPIO_Set driver_gpio.o
- 0x0800028c 0x0800028c 0x00000024 Code RO 77 i.MyGPIO_Toggle driver_gpio.o
- 0x080002b0 0x080002b0 0x00000094 Code RO 130 i.MyTimer_Active_IT driver_timer.o
- 0x08000344 0x08000344 0x00000012 Code RO 131 i.MyTimer_Base_Init driver_timer.o
- 0x08000356 0x08000356 0x00000008 Code RO 216 i.SetSysClock system_stm32f10x.o
- 0x0800035e 0x0800035e 0x00000002 PAD
- 0x08000360 0x08000360 0x000000e0 Code RO 217 i.SetSysClockTo72 system_stm32f10x.o
- 0x08000440 0x08000440 0x00000060 Code RO 219 i.SystemInit system_stm32f10x.o
- 0x080004a0 0x080004a0 0x00000024 Code RO 132 i.TIM1_TRG_COM_IRQHandler driver_timer.o
- 0x080004c4 0x080004c4 0x00000024 Code RO 133 i.TIM2_IRQHandler driver_timer.o
- 0x080004e8 0x080004e8 0x00000024 Code RO 134 i.TIM3_IRQHandler driver_timer.o
- 0x0800050c 0x0800050c 0x00000024 Code RO 135 i.TIM4_IRQHandler driver_timer.o
- 0x08000530 0x08000530 0x00000022 Code RO 136 i.__NVIC_EnableIRQ driver_timer.o
- 0x08000552 0x08000552 0x00000002 PAD
- 0x08000554 0x08000554 0x00000028 Code RO 137 i.__NVIC_SetPriority driver_timer.o
- 0x0800057c 0x0800057c 0x0000000e Code RO 282 i.__scatterload_copy mc_w.l(handlers.o)
- 0x0800058a 0x0800058a 0x00000002 Code RO 283 i.__scatterload_null mc_w.l(handlers.o)
- 0x0800058c 0x0800058c 0x0000000e Code RO 284 i.__scatterload_zeroinit mc_w.l(handlers.o)
- 0x0800059a 0x0800059a 0x00000002 PAD
- 0x0800059c 0x0800059c 0x00000014 Code RO 4 i.handle_TIM2 principal.o
- 0x080005b0 0x080005b0 0x00000074 Code RO 5 i.main principal.o
- 0x08000624 0x08000624 0x00000020 Data RO 280 Region$$Table anon$$obj.o
-
-
- Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000644, Size: 0x00000020, Max: 0xffffffff, ABSOLUTE)
-
- Exec Addr Load Addr Size Type Attr Idx E Section Name Object
-
- 0x20000000 0x08000644 0x00000010 Data RW 6 .data principal.o
- 0x20000010 0x08000654 0x00000010 Data RW 138 .data driver_timer.o
-
-
- Execution Region ER_ZI (Exec base: 0x20000020, Load base: 0x08000664, Size: 0x00000400, Max: 0xffffffff, ABSOLUTE)
-
- Exec Addr Load Addr Size Type Attr Idx E Section Name Object
-
- 0x20000020 - 0x00000400 Zero RW 206 STACK startup_stm32f10x_md.o
-
-
-==============================================================================
-
-Image component sizes
-
-
- Code (inc. data) RO Data RW Data ZI Data Debug Object Name
-
- 316 6 0 0 0 3616 driver_gpio.o
- 424 68 0 16 0 6033 driver_timer.o
- 136 24 0 16 0 208769 principal.o
- 36 8 236 0 1024 840 startup_stm32f10x_md.o
- 328 28 0 0 0 2101 system_stm32f10x.o
-
- ----------------------------------------------------------------------
- 1244 134 268 32 1024 221359 Object Totals
- 0 0 32 0 0 0 (incl. Generated)
- 4 0 0 0 0 0 (incl. Padding)
-
- ----------------------------------------------------------------------
-
- Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
-
- 0 0 0 0 0 0 entry.o
- 0 0 0 0 0 0 entry10a.o
- 0 0 0 0 0 0 entry11a.o
- 4 0 0 0 0 0 entry12b.o
- 8 4 0 0 0 0 entry2.o
- 4 0 0 0 0 0 entry5.o
- 0 0 0 0 0 0 entry7b.o
- 0 0 0 0 0 0 entry8b.o
- 8 4 0 0 0 0 entry9a.o
- 30 0 0 0 0 0 handlers.o
- 36 8 0 0 0 68 init.o
-
- ----------------------------------------------------------------------
- 92 16 0 0 0 68 Library Totals
- 2 0 0 0 0 0 (incl. Padding)
-
- ----------------------------------------------------------------------
-
- Code (inc. data) RO Data RW Data ZI Data Debug Library Name
-
- 90 16 0 0 0 68 mc_w.l
-
- ----------------------------------------------------------------------
- 92 16 0 0 0 68 Library Totals
-
- ----------------------------------------------------------------------
-
-==============================================================================
-
-
- Code (inc. data) RO Data RW Data ZI Data Debug
-
- 1336 150 268 32 1024 220695 Grand Totals
- 1336 150 268 32 1024 220695 ELF Image Totals
- 1336 150 268 32 0 0 ROM Totals
-
-==============================================================================
-
- Total RO Size (Code + RO Data) 1604 ( 1.57kB)
- Total RW Size (RW Data + ZI Data) 1056 ( 1.03kB)
- Total ROM Size (Code + RO Data + RW Data) 1636 ( 1.60kB)
-
-==============================================================================
-
diff --git a/timer_act2/Objects/ExtDll.iex b/timer_act2/Objects/ExtDll.iex
deleted file mode 100644
index 6c0896e..0000000
--- a/timer_act2/Objects/ExtDll.iex
+++ /dev/null
@@ -1,2 +0,0 @@
-[EXTDLL]
-Count=0
diff --git a/timer_act2/Objects/driver_gpio.crf b/timer_act2/Objects/driver_gpio.crf
deleted file mode 100644
index 3ac33b6..0000000
Binary files a/timer_act2/Objects/driver_gpio.crf and /dev/null differ
diff --git a/timer_act2/Objects/driver_gpio.d b/timer_act2/Objects/driver_gpio.d
deleted file mode 100644
index 6b958f3..0000000
--- a/timer_act2/Objects/driver_gpio.d
+++ /dev/null
@@ -1,10 +0,0 @@
-.\objects\driver_gpio.o: Includes\Driver_GPIO.c
-.\objects\driver_gpio.o: Includes\Driver_GPIO.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\driver_gpio.o: .\RTE\_carteSTM\RTE_Components.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\driver_gpio.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\driver_gpio.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/timer_act2/Objects/driver_gpio.o b/timer_act2/Objects/driver_gpio.o
deleted file mode 100644
index ee32b87..0000000
Binary files a/timer_act2/Objects/driver_gpio.o and /dev/null differ
diff --git a/timer_act2/Objects/driver_timer.crf b/timer_act2/Objects/driver_timer.crf
deleted file mode 100644
index 2a9e3cd..0000000
Binary files a/timer_act2/Objects/driver_timer.crf and /dev/null differ
diff --git a/timer_act2/Objects/driver_timer.d b/timer_act2/Objects/driver_timer.d
deleted file mode 100644
index d563af9..0000000
--- a/timer_act2/Objects/driver_timer.d
+++ /dev/null
@@ -1,10 +0,0 @@
-.\objects\driver_timer.o: Includes\Driver_TIMER.c
-.\objects\driver_timer.o: Includes\Driver_TIMER.h
-.\objects\driver_timer.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\driver_timer.o: .\RTE\_carteSTM\RTE_Components.h
-.\objects\driver_timer.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\driver_timer.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\driver_timer.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\driver_timer.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\driver_timer.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\driver_timer.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/timer_act2/Objects/driver_timer.o b/timer_act2/Objects/driver_timer.o
deleted file mode 100644
index 2dce5fe..0000000
Binary files a/timer_act2/Objects/driver_timer.o and /dev/null differ
diff --git a/timer_act2/Objects/principal.crf b/timer_act2/Objects/principal.crf
deleted file mode 100644
index 2200ed7..0000000
Binary files a/timer_act2/Objects/principal.crf and /dev/null differ
diff --git a/timer_act2/Objects/principal.d b/timer_act2/Objects/principal.d
deleted file mode 100644
index 002908d..0000000
--- a/timer_act2/Objects/principal.d
+++ /dev/null
@@ -1,11 +0,0 @@
-.\objects\principal.o: Source\principal.c
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\principal.o: .\RTE\_carteSTM\RTE_Components.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\principal.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\principal.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
-.\objects\principal.o: .\Includes\Driver_GPIO.h
-.\objects\principal.o: .\Includes\Driver_TIMER.h
diff --git a/timer_act2/Objects/principal.o b/timer_act2/Objects/principal.o
deleted file mode 100644
index ac560dc..0000000
Binary files a/timer_act2/Objects/principal.o and /dev/null differ
diff --git a/timer_act2/Objects/startup_stm32f10x_md.d b/timer_act2/Objects/startup_stm32f10x_md.d
deleted file mode 100644
index 96d5fcf..0000000
--- a/timer_act2/Objects/startup_stm32f10x_md.d
+++ /dev/null
@@ -1 +0,0 @@
-.\objects\startup_stm32f10x_md.o: RTE\Device\STM32F103RB\startup_stm32f10x_md.s
diff --git a/timer_act2/Objects/startup_stm32f10x_md.o b/timer_act2/Objects/startup_stm32f10x_md.o
deleted file mode 100644
index 85b7e0f..0000000
Binary files a/timer_act2/Objects/startup_stm32f10x_md.o and /dev/null differ
diff --git a/timer_act2/Objects/system_stm32f10x.crf b/timer_act2/Objects/system_stm32f10x.crf
deleted file mode 100644
index 94130bd..0000000
Binary files a/timer_act2/Objects/system_stm32f10x.crf and /dev/null differ
diff --git a/timer_act2/Objects/system_stm32f10x.d b/timer_act2/Objects/system_stm32f10x.d
deleted file mode 100644
index 8528c7f..0000000
--- a/timer_act2/Objects/system_stm32f10x.d
+++ /dev/null
@@ -1,9 +0,0 @@
-.\objects\system_stm32f10x.o: RTE\Device\STM32F103RB\system_stm32f10x.c
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h
-.\objects\system_stm32f10x.o: .\RTE\_carteSTM\RTE_Components.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
-.\objects\system_stm32f10x.o: C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h
diff --git a/timer_act2/Objects/system_stm32f10x.o b/timer_act2/Objects/system_stm32f10x.o
deleted file mode 100644
index 284aeae..0000000
Binary files a/timer_act2/Objects/system_stm32f10x.o and /dev/null differ
diff --git a/timer_act2/Objects/timer_act2.axf b/timer_act2/Objects/timer_act2.axf
deleted file mode 100644
index 9014802..0000000
Binary files a/timer_act2/Objects/timer_act2.axf and /dev/null differ
diff --git a/timer_act2/Objects/timer_act2.build_log.htm b/timer_act2/Objects/timer_act2.build_log.htm
deleted file mode 100644
index 9342f98..0000000
--- a/timer_act2/Objects/timer_act2.build_log.htm
+++ /dev/null
@@ -1,74 +0,0 @@
-
-
-
-µVision Build Log
-Tool Versions:
-IDE-Version: µVision V5.33.0.0
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: Celia C, Insa, LIC=----
-
-Tool Versions:
-Toolchain: MDK-Lite Version: 5.33.0.0
-Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler: Armcc.exe V5.06 update 7 (build 960)
-Assembler: Armasm.exe V5.06 update 7 (build 960)
-Linker/Locator: ArmLink.exe V5.06 update 7 (build 960)
-Library Manager: ArmAr.exe V5.06 update 7 (build 960)
-Hex Converter: FromElf.exe V5.06 update 7 (build 960)
-CPU DLL: SARMCM3.DLL V5.33.0.0
-Dialog DLL: DARMSTM.DLL V1.68.0.0
-Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.8.0
-Dialog DLL: TARMSTM.DLL V1.66.0.0
-
-Project:
-C:\Users\chauz\Documents_non_drive\INSA\4A\S7\TP_microcontroleur\timer_act2\timer_act2.uvprojx
-Project File Date: 09/20/2021
-
-Output:
-*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Rebuild target 'carteSTM'
-assembling startup_stm32f10x_md.s...
-compiling principal.c...
-Source\principal.c(40): warning: #111-D: statement is unreachable
- return 0;
-Source\principal.c: 1 warning, 0 errors
-compiling Driver_GPIO.c...
-compiling Driver_TIMER.c...
-compiling system_stm32f10x.c...
-linking...
-Program Size: Code=1336 RO-data=268 RW-data=32 ZI-data=1024
-".\Objects\timer_act2.axf" - 0 Error(s), 1 Warning(s).
-
-Software Packages used:
-
-Package Vendor: ARM
- http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
- ARM.CMSIS.5.7.0
- CMSIS (Cortex Microcontroller Software Interface Standard)
- * Component: CORE Version: 5.4.0
-
-Package Vendor: Keil
- http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
- Keil.STM32F1xx_DFP.2.3.0
- STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
- * Component: Startup Version: 1.0.0
-
-Collection of Component include folders:
- .\RTE\Device\STM32F103RB
- .\RTE\_carteSTM
- C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
- C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-
-Collection of Component Files used:
-
- * Component: ARM::CMSIS:CORE:5.4.0
-
- * Component: Keil::Device:Startup:1.0.0
- Source file: Device\Source\ARM\startup_stm32f10x_md.s
- Source file: Device\Source\system_stm32f10x.c
- Include file: RTE_Driver\Config\RTE_Device.h
- Source file: Device\Source\ARM\STM32F1xx_OPT.s
-Build Time Elapsed: 00:00:00
-
-
-
diff --git a/timer_act2/Objects/timer_act2.htm b/timer_act2/Objects/timer_act2.htm
deleted file mode 100644
index dba448f..0000000
--- a/timer_act2/Objects/timer_act2.htm
+++ /dev/null
@@ -1,439 +0,0 @@
-
-
-Static Call Graph - [.\Objects\timer_act2.axf]
-
-Static Call Graph for image .\Objects\timer_act2.axf
-
#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Fri Sep 24 18:37:27 2021
-
-
Maximum Stack Usage = 28 bytes + Unknown(Cycles, Untraceable Function Pointers)
-Call chain for Maximum Stack Depth:
-SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
-
-
-Mutually Recursive functions
-
NMI_Handler ⇒ NMI_Handler
- HardFault_Handler ⇒ HardFault_Handler
- MemManage_Handler ⇒ MemManage_Handler
- BusFault_Handler ⇒ BusFault_Handler
- UsageFault_Handler ⇒ UsageFault_Handler
- SVC_Handler ⇒ SVC_Handler
- DebugMon_Handler ⇒ DebugMon_Handler
- PendSV_Handler ⇒ PendSV_Handler
- SysTick_Handler ⇒ SysTick_Handler
- ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
-
-
-
-Function Pointers
-
- - ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- EXTI9_5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text)
-
- TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_TRG_COM_IRQHandler from driver_timer.o(i.TIM1_TRG_COM_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM1_UP_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM2_IRQHandler from driver_timer.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM3_IRQHandler from driver_timer.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
-
- TIM4_IRQHandler from driver_timer.o(i.TIM4_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
-
- USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
-
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text)
-
- handle_TIM2 from principal.o(i.handle_TIM2) referenced from principal.o(i.main)
-
- main from principal.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-
-Global Symbols
-
-__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(.text)
-
-_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Calls]
-
-__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Called By]
-
-_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-
__rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E))
-
-
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F))
-
-
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011))
-
-
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
-
NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
-
-__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-
[Calls]
- >> __main_after_scatterload
-
-
[Called By]
-
-__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-
Activate_TIM (Thumb, 36 bytes, Stack size 0 bytes, driver_timer.o(i.Activate_TIM))
-
[Called By]
-
-MyGPIO_Activate (Thumb, 18 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Activate))
-
[Called By]
-
-MyGPIO_Init (Thumb, 236 bytes, Stack size 4 bytes, driver_gpio.o(i.MyGPIO_Init))
-
[Stack]
- Max Depth = 4
- Call Chain = MyGPIO_Init
-
-
[Calls]
-
[Called By]
-
-MyGPIO_Reset (Thumb, 12 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Reset))
-
[Called By]
-
-MyGPIO_Set (Thumb, 8 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Set))
-
[Called By]
- >> MyGPIO_Toggle
-
- >> MyGPIO_Init
-
- >> main
-
-
-MyGPIO_Toggle (Thumb, 36 bytes, Stack size 12 bytes, driver_gpio.o(i.MyGPIO_Toggle))
-
[Stack]
- Max Depth = 12
- Call Chain = MyGPIO_Toggle
-
-
[Calls]- >> MyGPIO_Reset
-
- >> MyGPIO_Set
-
-
[Called By]
-
-MyTimer_Active_IT (Thumb, 120 bytes, Stack size 16 bytes, driver_timer.o(i.MyTimer_Active_IT))
-
[Stack]
- Max Depth = 24
- Call Chain = MyTimer_Active_IT ⇒ __NVIC_SetPriority
-
-
[Calls]- >> __NVIC_SetPriority
-
- >> __NVIC_EnableIRQ
-
-
[Called By]
-
-MyTimer_Base_Init (Thumb, 18 bytes, Stack size 0 bytes, driver_timer.o(i.MyTimer_Base_Init))
-
[Called By]
-
-SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
-
[Stack]
- Max Depth = 28
- Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(.text)
-
-TIM1_TRG_COM_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, driver_timer.o(i.TIM1_TRG_COM_IRQHandler))
-
[Stack]
- Max Depth = 8
- Call Chain = TIM1_TRG_COM_IRQHandler
-
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-TIM2_IRQHandler (Thumb, 32 bytes, Stack size 8 bytes, driver_timer.o(i.TIM2_IRQHandler))
-
[Stack]
- Max Depth = 8
- Call Chain = TIM2_IRQHandler
-
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-TIM3_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, driver_timer.o(i.TIM3_IRQHandler))
-
[Stack]
- Max Depth = 8
- Call Chain = TIM3_IRQHandler
-
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-TIM4_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, driver_timer.o(i.TIM4_IRQHandler))
-
[Stack]
- Max Depth = 8
- Call Chain = TIM4_IRQHandler
-
-
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
-
-__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-
handle_TIM2 (Thumb, 14 bytes, Stack size 8 bytes, principal.o(i.handle_TIM2))
-
[Stack]
- Max Depth = 20
- Call Chain = handle_TIM2 ⇒ MyGPIO_Toggle
-
-
[Calls]
-
[Address Reference Count : 1]
-main (Thumb, 98 bytes, Stack size 0 bytes, principal.o(i.main))
-
[Stack]
- Max Depth = 24
- Call Chain = main ⇒ MyTimer_Active_IT ⇒ __NVIC_SetPriority
-
-
[Calls]- >> MyTimer_Base_Init
-
- >> MyTimer_Active_IT
-
- >> MyGPIO_Set
-
- >> MyGPIO_Init
-
- >> MyGPIO_Activate
-
- >> Activate_TIM
-
-
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-Local Symbols
-
-__NVIC_EnableIRQ (Thumb, 34 bytes, Stack size 0 bytes, driver_timer.o(i.__NVIC_EnableIRQ))
-
[Called By]
-
-__NVIC_SetPriority (Thumb, 32 bytes, Stack size 8 bytes, driver_timer.o(i.__NVIC_SetPriority))
-
[Stack]
- Max Depth = 8
- Call Chain = __NVIC_SetPriority
-
-
[Called By]
-
-SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
-
[Stack]
- Max Depth = 20
- Call Chain = SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Called By]
-
-SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
-
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
-
-
[Called By]
-
-
-Undefined Global Symbols
-
diff --git a/timer_act2/Objects/timer_act2.lnp b/timer_act2/Objects/timer_act2.lnp
deleted file mode 100644
index a196eef..0000000
--- a/timer_act2/Objects/timer_act2.lnp
+++ /dev/null
@@ -1,9 +0,0 @@
---cpu Cortex-M3
-".\objects\principal.o"
-".\objects\driver_gpio.o"
-".\objects\driver_timer.o"
-".\objects\startup_stm32f10x_md.o"
-".\objects\system_stm32f10x.o"
---library_type=microlib --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\timer_act2.map" -o .\Objects\timer_act2.axf
\ No newline at end of file
diff --git a/timer_act2/Objects/timer_act2_Simulation.dep b/timer_act2/Objects/timer_act2_Simulation.dep
deleted file mode 100644
index e875b00..0000000
--- a/timer_act2/Objects/timer_act2_Simulation.dep
+++ /dev/null
@@ -1,46 +0,0 @@
-Dependencies for Project 'timer_act2', Target 'Simulation': (DO NOT MODIFY !)
-CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
-F (.\Source\principal.c)(0x614DFD86)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_Simulation\RTE_Components.h)(0x61487B1E)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-I (.\Includes\Driver_GPIO.h)(0x61476D7E)
-I (.\Includes\Driver_TIMER.h)(0x614DED89)
-F (.\Includes\Driver_GPIO.c)(0x614DFC28)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d)
-I (Includes\Driver_GPIO.h)(0x61476D7E)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_Simulation\RTE_Components.h)(0x61487B1E)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-F (.\Includes\Driver_GPIO.h)(0x61476D7E)()
-F (.\Includes\Driver_TIMER.c)(0x614DFDB4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_timer.o --omf_browse .\objects\driver_timer.crf --depend .\objects\driver_timer.d)
-I (Includes\Driver_TIMER.h)(0x614DED89)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_Simulation\RTE_Components.h)(0x61487B1E)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-F (.\Includes\Driver_TIMER.h)(0x614DED89)()
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59284216)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58259ADC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 533" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58259ADC)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_Simulation
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_Simulation\RTE_Components.h)(0x61487B1E)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
diff --git a/timer_act2/Objects/timer_act2_carteSTM.dep b/timer_act2/Objects/timer_act2_carteSTM.dep
deleted file mode 100644
index bb0b885..0000000
--- a/timer_act2/Objects/timer_act2_carteSTM.dep
+++ /dev/null
@@ -1,46 +0,0 @@
-Dependencies for Project 'timer_act2', Target 'carteSTM': (DO NOT MODIFY !)
-CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
-F (.\Source\principal.c)(0x614DFEC0)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_carteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\principal.o --omf_browse .\objects\principal.crf --depend .\objects\principal.d)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_carteSTM\RTE_Components.h)(0x61487C22)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-I (.\Includes\Driver_GPIO.h)(0x61476D7E)
-I (.\Includes\Driver_TIMER.h)(0x614DED89)
-F (.\Includes\Driver_GPIO.c)(0x614DFC28)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_carteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d)
-I (Includes\Driver_GPIO.h)(0x61476D7E)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_carteSTM\RTE_Components.h)(0x61487C22)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-F (.\Includes\Driver_GPIO.h)(0x61476D7E)()
-F (.\Includes\Driver_TIMER.c)(0x614DFDB4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_carteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\driver_timer.o --omf_browse .\objects\driver_timer.crf --depend .\objects\driver_timer.d)
-I (Includes\Driver_TIMER.h)(0x614DED89)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_carteSTM\RTE_Components.h)(0x61487C22)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
-F (.\Includes\Driver_TIMER.h)(0x614DED89)()
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59284216)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58259ADC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\Device\STM32F103RB
-I.\RTE\_carteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
--pd "__UVISION_VERSION SETA 533" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58259ADC)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Includes
-I.\RTE\Device\STM32F103RB
-I.\RTE\_carteSTM
-IC:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-D__UVISION_VERSION="533" -D_RTE_ -DSTM32F10X_MD -D_RTE_
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58259ADC)
-I (.\RTE\_carteSTM\RTE_Components.h)(0x61487C22)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F3392)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E836932)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F3392)
-I (C:\Users\chauz\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58259ADC)
diff --git a/timer_act2/RTE/Device/STM32F103RB/RTE_Device.h b/timer_act2/RTE/Device/STM32F103RB/RTE_Device.h
deleted file mode 100644
index 22d1da2..0000000
--- a/timer_act2/RTE/Device/STM32F103RB/RTE_Device.h
+++ /dev/null
@@ -1,1828 +0,0 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2016 ARM Ltd.
- *
- * This software is provided 'as-is', without any express or implied warranty.
- * In no event will the authors be held liable for any damages arising from
- * the use of this software. Permission is granted to anyone to use this
- * software for any purpose, including commercial applications, and to alter
- * it and redistribute it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software. If you use this software in
- * a product, an acknowledgment in the product documentation would be
- * appreciated but is not required.
- *
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.
- *
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * $Date: 09. September 2016
- * $Revision: V1.1.2
- *
- * Project: RTE Device Configuration for STMicroelectronics STM32F1xx
- *
- * -------------------------------------------------------------------------- */
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-#ifndef __RTE_DEVICE_H
-#define __RTE_DEVICE_H
-
-
-#define GPIO_PORT(num) \
- ((num == 0) ? GPIOA : \
- (num == 1) ? GPIOB : \
- (num == 2) ? GPIOC : \
- (num == 3) ? GPIOD : \
- (num == 4) ? GPIOE : \
- (num == 5) ? GPIOF : \
- (num == 6) ? GPIOG : \
- NULL)
-
-
-// Clock Configuration
-// High-speed Internal Clock <1-999999999>
-#define RTE_HSI 8000000
-// High-speed External Clock <1-999999999>
-#define RTE_HSE 25000000
-// System Clock <1-999999999>
-#define RTE_SYSCLK 72000000
-// HCLK Clock <1-999999999>
-#define RTE_HCLK 72000000
-// APB1 Clock <1-999999999>
-#define RTE_PCLK1 36000000
-// APB2 Clock <1-999999999>
-#define RTE_PCLK2 72000000
-// ADC Clock <1-999999999>
-#define RTE_ADCCLK 36000000
-// USB Clock
-#define RTE_USBCLK 48000000
-//
-
-
-// USART1 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
-#define RTE_USART1 0
-
-// USART1_TX Pin <0=>Not Used <1=>PA9
-#define RTE_USART1_TX_PORT_ID_DEF 0
-#if (RTE_USART1_TX_PORT_ID_DEF == 0)
-#define RTE_USART1_TX_DEF 0
-#elif (RTE_USART1_TX_PORT_ID_DEF == 1)
-#define RTE_USART1_TX_DEF 1
-#define RTE_USART1_TX_PORT_DEF GPIOA
-#define RTE_USART1_TX_BIT_DEF 9
-#else
-#error "Invalid USART1_TX Pin Configuration!"
-#endif
-
-// USART1_RX Pin <0=>Not Used <1=>PA10
-#define RTE_USART1_RX_PORT_ID_DEF 0
-#if (RTE_USART1_RX_PORT_ID_DEF == 0)
-#define RTE_USART1_RX_DEF 0
-#elif (RTE_USART1_RX_PORT_ID_DEF == 1)
-#define RTE_USART1_RX_DEF 1
-#define RTE_USART1_RX_PORT_DEF GPIOA
-#define RTE_USART1_RX_BIT_DEF 10
-#else
-#error "Invalid USART1_RX Pin Configuration!"
-#endif
-
-// USART1_CK Pin <0=>Not Used <1=>PA8
-#define RTE_USART1_CK_PORT_ID_DEF 0
-#if (RTE_USART1_CK_PORT_ID_DEF == 0)
-#define RTE_USART1_CK 0
-#elif (RTE_USART1_CK_PORT_ID_DEF == 1)
-#define RTE_USART1_CK 1
-#define RTE_USART1_CK_PORT_DEF GPIOA
-#define RTE_USART1_CK_BIT_DEF 8
-#else
-#error "Invalid USART1_CK Pin Configuration!"
-#endif
-
-// USART1_CTS Pin <0=>Not Used <1=>PA11
-#define RTE_USART1_CTS_PORT_ID_DEF 0
-#if (RTE_USART1_CTS_PORT_ID_DEF == 0)
-#define RTE_USART1_CTS 0
-#elif (RTE_USART1_CTS_PORT_ID_DEF == 1)
-#define RTE_USART1_CTS 1
-#define RTE_USART1_CTS_PORT_DEF GPIOA
-#define RTE_USART1_CTS_BIT_DEF 11
-#else
-#error "Invalid USART1_CTS Pin Configuration!"
-#endif
-
-// USART1_RTS Pin <0=>Not Used <1=>PA12
-#define RTE_USART1_RTS_PORT_ID_DEF 0
-#if (RTE_USART1_RTS_PORT_ID_DEF == 0)
-#define RTE_USART1_RTS 0
-#elif (RTE_USART1_RTS_PORT_ID_DEF == 1)
-#define RTE_USART1_RTS 1
-#define RTE_USART1_RTS_PORT_DEF GPIOA
-#define RTE_USART1_RTS_BIT_DEF 12
-#else
-#error "Invalid USART1_RTS Pin Configuration!"
-#endif
-
-// USART1 Pin Remap
-// Enable USART1 Pin Remapping
-#define RTE_USART1_REMAP_FULL 0
-
-// USART1_TX Pin <0=>Not Used <1=>PB6
-#define RTE_USART1_TX_PORT_ID_FULL 0
-#if (RTE_USART1_TX_PORT_ID_FULL == 0)
-#define RTE_USART1_TX_FULL 0
-#elif (RTE_USART1_TX_PORT_ID_FULL == 1)
-#define RTE_USART1_TX_FULL 1
-#define RTE_USART1_TX_PORT_FULL GPIOB
-#define RTE_USART1_TX_BIT_FULL 6
-#else
-#error "Invalid USART1_TX Pin Configuration!"
-#endif
-
-// USART1_RX Pin <0=>Not Used <1=>PB7
-#define RTE_USART1_RX_PORT_ID_FULL 0
-#if (RTE_USART1_RX_PORT_ID_FULL == 0)
-#define RTE_USART1_RX_FULL 0
-#elif (RTE_USART1_RX_PORT_ID_FULL == 1)
-#define RTE_USART1_RX_FULL 1
-#define RTE_USART1_RX_PORT_FULL GPIOB
-#define RTE_USART1_RX_BIT_FULL 7
-#else
-#error "Invalid USART1_RX Pin Configuration!"
-#endif
-//
-
-#if (RTE_USART1_REMAP_FULL)
-#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP
-#define RTE_USART1_TX RTE_USART1_TX_FULL
-#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL
-#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL
-#define RTE_USART1_RX RTE_USART1_RX_FULL
-#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL
-#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL
-#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
-#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
-#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
-#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
-#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
-#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
-#else
-#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP
-#define RTE_USART1_TX RTE_USART1_TX_DEF
-#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF
-#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF
-#define RTE_USART1_RX RTE_USART1_RX_DEF
-#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF
-#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF
-#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
-#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
-#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
-#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
-#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
-#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART1_RX_DMA 0
-#define RTE_USART1_RX_DMA_NUMBER 1
-#define RTE_USART1_RX_DMA_CHANNEL 5
-#define RTE_USART1_RX_DMA_PRIORITY 0
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART1_TX_DMA 0
-#define RTE_USART1_TX_DMA_NUMBER 1
-#define RTE_USART1_TX_DMA_CHANNEL 4
-#define RTE_USART1_TX_DMA_PRIORITY 0
-//
-
-
-// USART2 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
-#define RTE_USART2 0
-
-// USART2_TX Pin <0=>Not Used <1=>PA2
-#define RTE_USART2_TX_PORT_ID_DEF 0
-#if (RTE_USART2_TX_PORT_ID_DEF == 0)
-#define RTE_USART2_TX_DEF 0
-#elif (RTE_USART2_TX_PORT_ID_DEF == 1)
-#define RTE_USART2_TX_DEF 1
-#define RTE_USART2_TX_PORT_DEF GPIOA
-#define RTE_USART2_TX_BIT_DEF 2
-#else
-#error "Invalid USART2_TX Pin Configuration!"
-#endif
-
-// USART2_RX Pin <0=>Not Used <1=>PA3
-#define RTE_USART2_RX_PORT_ID_DEF 0
-#if (RTE_USART2_RX_PORT_ID_DEF == 0)
-#define RTE_USART2_RX_DEF 0
-#elif (RTE_USART2_RX_PORT_ID_DEF == 1)
-#define RTE_USART2_RX_DEF 1
-#define RTE_USART2_RX_PORT_DEF GPIOA
-#define RTE_USART2_RX_BIT_DEF 3
-#else
-#error "Invalid USART2_RX Pin Configuration!"
-#endif
-
-// USART2_CK Pin <0=>Not Used <1=>PA4
-#define RTE_USART2_CK_PORT_ID_DEF 0
-#if (RTE_USART2_CK_PORT_ID_DEF == 0)
-#define RTE_USART2_CK_DEF 0
-#elif (RTE_USART2_CK_PORT_ID_DEF == 1)
-#define RTE_USART2_CK_DEF 1
-#define RTE_USART2_CK_PORT_DEF GPIOA
-#define RTE_USART2_CK_BIT_DEF 4
-#else
-#error "Invalid USART2_CK Pin Configuration!"
-#endif
-
-// USART2_CTS Pin <0=>Not Used <1=>PA0
-#define RTE_USART2_CTS_PORT_ID_DEF 0
-#if (RTE_USART2_CTS_PORT_ID_DEF == 0)
-#define RTE_USART2_CTS_DEF 0
-#elif (RTE_USART2_CTS_PORT_ID_DEF == 1)
-#define RTE_USART2_CTS_DEF 1
-#define RTE_USART2_CTS_PORT_DEF GPIOA
-#define RTE_USART2_CTS_BIT_DEF 0
-#else
-#error "Invalid USART2_CTS Pin Configuration!"
-#endif
-
-// USART2_RTS Pin <0=>Not Used <1=>PA1
-#define RTE_USART2_RTS_PORT_ID_DEF 0
-#if (RTE_USART2_RTS_PORT_ID_DEF == 0)
-#define RTE_USART2_RTS_DEF 0
-#elif (RTE_USART2_RTS_PORT_ID_DEF == 1)
-#define RTE_USART2_RTS_DEF 1
-#define RTE_USART2_RTS_PORT_DEF GPIOA
-#define RTE_USART2_RTS_BIT_DEF 1
-#else
-#error "Invalid USART2_RTS Pin Configuration!"
-#endif
-
-// USART2 Pin Remap
-// Enable USART2 Pin Remapping
-#define RTE_USART2_REMAP_FULL 0
-
-// USART2_TX Pin <0=>Not Used <1=>PD5
-#define RTE_USART2_TX_PORT_ID_FULL 0
-#if (RTE_USART2_TX_PORT_ID_FULL == 0)
-#define RTE_USART2_TX_FULL 0
-#elif (RTE_USART2_TX_PORT_ID_FULL == 1)
-#define RTE_USART2_TX_FULL 1
-#define RTE_USART2_TX_PORT_FULL GPIOD
-#define RTE_USART2_TX_BIT_FULL 5
-#else
-#error "Invalid USART2_TX Pin Configuration!"
-#endif
-
-// USART2_RX Pin <0=>Not Used <1=>PD6
-#define RTE_USART2_RX_PORT_ID_FULL 0
-#if (RTE_USART2_RX_PORT_ID_FULL == 0)
-#define RTE_USART2_RX_FULL 0
-#elif (RTE_USART2_RX_PORT_ID_FULL == 1)
-#define RTE_USART2_RX_FULL 1
-#define RTE_USART2_RX_PORT_FULL GPIOD
-#define RTE_USART2_RX_BIT_FULL 6
-#else
-#error "Invalid USART2_RX Pin Configuration!"
-#endif
-
-// USART2_CK Pin <0=>Not Used <1=>PD7
-#define RTE_USART2_CK_PORT_ID_FULL 0
-#if (RTE_USART2_CK_PORT_ID_FULL == 0)
-#define RTE_USART2_CK_FULL 0
-#elif (RTE_USART2_CK_PORT_ID_FULL == 1)
-#define RTE_USART2_CK_FULL 1
-#define RTE_USART2_CK_PORT_FULL GPIOD
-#define RTE_USART2_CK_BIT_FULL 7
-#else
-#error "Invalid USART2_CK Pin Configuration!"
-#endif
-
-// USART2_CTS Pin <0=>Not Used <1=>PD3
-#define RTE_USART2_CTS_PORT_ID_FULL 0
-#if (RTE_USART2_CTS_PORT_ID_FULL == 0)
-#define RTE_USART2_CTS_FULL 0
-#elif (RTE_USART2_CTS_PORT_ID_FULL == 1)
-#define RTE_USART2_CTS_FULL 1
-#define RTE_USART2_CTS_PORT_FULL GPIOD
-#define RTE_USART2_CTS_BIT_FULL 3
-#else
-#error "Invalid USART2_CTS Pin Configuration!"
-#endif
-
-// USART2_RTS Pin <0=>Not Used <1=>PD4
-#define RTE_USART2_RTS_PORT_ID_FULL 0
-#if (RTE_USART2_RTS_PORT_ID_FULL == 0)
-#define RTE_USART2_RTS_FULL 0
-#elif (RTE_USART2_RTS_PORT_ID_FULL == 1)
-#define RTE_USART2_RTS_FULL 1
-#define RTE_USART2_RTS_PORT_FULL GPIOD
-#define RTE_USART2_RTS_BIT_FULL 4
-#else
-#error "Invalid USART2_RTS Pin Configuration!"
-#endif
-//
-
-#if (RTE_USART2_REMAP_FULL)
-#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP
-#define RTE_USART2_TX RTE_USART2_TX_FULL
-#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL
-#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL
-#define RTE_USART2_RX RTE_USART2_RX_FULL
-#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL
-#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL
-#define RTE_USART2_CK RTE_USART2_CK_FULL
-#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL
-#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL
-#define RTE_USART2_CTS RTE_USART2_CTS_FULL
-#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL
-#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL
-#define RTE_USART2_RTS RTE_USART2_RTS_FULL
-#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL
-#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL
-#else
-#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP
-#define RTE_USART2_TX RTE_USART2_TX_DEF
-#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF
-#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF
-#define RTE_USART2_RX RTE_USART2_RX_DEF
-#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF
-#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF
-#define RTE_USART2_CK RTE_USART2_CK_DEF
-#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF
-#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF
-#define RTE_USART2_CTS RTE_USART2_CTS_DEF
-#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF
-#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF
-#define RTE_USART2_RTS RTE_USART2_RTS_DEF
-#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF
-#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <6=>6
-// Selects DMA Channel (only Channel 6 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART2_RX_DMA 0
-#define RTE_USART2_RX_DMA_NUMBER 1
-#define RTE_USART2_RX_DMA_CHANNEL 6
-#define RTE_USART2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <7=>7
-// Selects DMA Channel (only Channel 7 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Set DMA Channel priority
-//
-#define RTE_USART2_TX_DMA 0
-#define RTE_USART2_TX_DMA_NUMBER 1
-#define RTE_USART2_TX_DMA_CHANNEL 7
-#define RTE_USART2_TX_DMA_PRIORITY 0
-
-//
-
-
-// USART3 (Universal synchronous asynchronous receiver transmitter)
-// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
-#define RTE_USART3 0
-
-// USART3_TX Pin <0=>Not Used <1=>PB10
-#define RTE_USART3_TX_PORT_ID_DEF 0
-#if (RTE_USART3_TX_PORT_ID_DEF == 0)
-#define RTE_USART3_TX_DEF 0
-#elif (RTE_USART3_TX_PORT_ID_DEF == 1)
-#define RTE_USART3_TX_DEF 1
-#define RTE_USART3_TX_PORT_DEF GPIOB
-#define RTE_USART3_TX_BIT_DEF 10
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PB11
-#define RTE_USART3_RX_PORT_ID_DEF 0
-#if (RTE_USART3_RX_PORT_ID_DEF == 0)
-#define RTE_USART3_RX_DEF 0
-#elif (RTE_USART3_RX_PORT_ID_DEF == 1)
-#define RTE_USART3_RX_DEF 1
-#define RTE_USART3_RX_PORT_DEF GPIOB
-#define RTE_USART3_RX_BIT_DEF 11
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PB12
-#define RTE_USART3_CK_PORT_ID_DEF 0
-#if (RTE_USART3_CK_PORT_ID_DEF == 0)
-#define RTE_USART3_CK_DEF 0
-#elif (RTE_USART3_CK_PORT_ID_DEF == 1)
-#define RTE_USART3_CK_DEF 1
-#define RTE_USART3_CK_PORT_DEF GPIOB
-#define RTE_USART3_CK_BIT_DEF 12
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-
-// USART3_CTS Pin <0=>Not Used <1=>PB13
-#define RTE_USART3_CTS_PORT_ID_DEF 0
-#if (RTE_USART3_CTS_PORT_ID_DEF == 0)
-#define RTE_USART3_CTS_DEF 0
-#elif (RTE_USART3_CTS_PORT_ID_DEF == 1)
-#define RTE_USART3_CTS_DEF 1
-#define RTE_USART3_CTS_PORT_DEF GPIOB
-#define RTE_USART3_CTS_BIT_DEF 13
-#else
-#error "Invalid USART3_CTS Pin Configuration!"
-#endif
-
-// USART3_RTS Pin <0=>Not Used <1=>PB14
-#define RTE_USART3_RTS_PORT_ID_DEF 0
-#if (RTE_USART3_RTS_PORT_ID_DEF == 0)
-#define RTE_USART3_RTS_DEF 0
-#elif (RTE_USART3_RTS_PORT_ID_DEF == 1)
-#define RTE_USART3_RTS_DEF 1
-#define RTE_USART3_RTS_PORT_DEF GPIOB
-#define RTE_USART3_RTS_BIT_DEF 14
-#else
-#error "Invalid USART3_RTS Pin Configuration!"
-#endif
-
-// USART3 Partial Pin Remap
-// Enable USART3 Partial Pin Remapping
-#define RTE_USART3_REMAP_PARTIAL 0
-
-// USART3_TX Pin <0=>Not Used <1=>PC10
-#define RTE_USART3_TX_PORT_ID_PARTIAL 0
-#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_TX_PARTIAL 0
-#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_TX_PARTIAL 1
-#define RTE_USART3_TX_PORT_PARTIAL GPIOC
-#define RTE_USART3_TX_BIT_PARTIAL 10
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PC11
-#define RTE_USART3_RX_PORT_ID_PARTIAL 0
-#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_RX_PARTIAL 0
-#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_RX_PARTIAL 1
-#define RTE_USART3_RX_PORT_PARTIAL GPIOC
-#define RTE_USART3_RX_BIT_PARTIAL 11
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PC12
-#define RTE_USART3_CK_PORT_ID_PARTIAL 0
-#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_CK_PARTIAL 0
-#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_CK_PARTIAL 1
-#define RTE_USART3_CK_PORT_PARTIAL GPIOC
-#define RTE_USART3_CK_BIT_PARTIAL 12
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-//
-
-// USART3 Full Pin Remap
-// Enable USART3 Full Pin Remapping
-#define RTE_USART3_REMAP_FULL 0
-
-// USART3_TX Pin <0=>Not Used <1=>PD8
-#define RTE_USART3_TX_PORT_ID_FULL 0
-#if (RTE_USART3_TX_PORT_ID_FULL == 0)
-#define RTE_USART3_TX_FULL 0
-#elif (RTE_USART3_TX_PORT_ID_FULL == 1)
-#define RTE_USART3_TX_FULL 1
-#define RTE_USART3_TX_PORT_FULL GPIOD
-#define RTE_USART3_TX_BIT_FULL 8
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-// USART3_RX Pin <0=>Not Used <1=>PD9
-#define RTE_USART3_RX_PORT_ID_FULL 0
-#if (RTE_USART3_RX_PORT_ID_FULL == 0)
-#define RTE_USART3_RX_FULL 0
-#elif (RTE_USART3_RX_PORT_ID_FULL == 1)
-#define RTE_USART3_RX_FULL 1
-#define RTE_USART3_RX_PORT_FULL GPIOD
-#define RTE_USART3_RX_BIT_FULL 9
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-// USART3_CK Pin <0=>Not Used <1=>PD10
-#define RTE_USART3_CK_PORT_ID_FULL 0
-#if (RTE_USART3_CK_PORT_ID_FULL == 0)
-#define RTE_USART3_CK_FULL 0
-#elif (RTE_USART3_CK_PORT_ID_FULL == 1)
-#define RTE_USART3_CK_FULL 1
-#define RTE_USART3_CK_PORT_FULL GPIOD
-#define RTE_USART3_CK_BIT_FULL 10
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-
-// USART3_CTS Pin <0=>Not Used <1=>PD11
-#define RTE_USART3_CTS_PORT_ID_FULL 0
-#if (RTE_USART3_CTS_PORT_ID_FULL == 0)
-#define RTE_USART3_CTS_FULL 0
-#elif (RTE_USART3_CTS_PORT_ID_FULL == 1)
-#define RTE_USART3_CTS_FULL 1
-#define RTE_USART3_CTS_PORT_FULL GPIOD
-#define RTE_USART3_CTS_BIT_FULL 11
-#else
-#error "Invalid USART3_CTS Pin Configuration!"
-#endif
-
-// USART3_RTS Pin <0=>Not Used <1=>PD12
-#define RTE_USART3_RTS_PORT_ID_FULL 0
-#if (RTE_USART3_RTS_PORT_ID_FULL == 0)
-#define RTE_USART3_RTS_FULL 0
-#elif (RTE_USART3_RTS_PORT_ID_FULL == 1)
-#define RTE_USART3_RTS_FULL 1
-#define RTE_USART3_RTS_PORT_FULL GPIOD
-#define RTE_USART3_RTS_BIT_FULL 12
-#else
-#error "Invalid USART3_RTS Pin Configuration!"
-#endif
-//
-
-#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
-#error "Invalid USART3 Pin Remap Configuration!"
-#endif
-
-#if (RTE_USART3_REMAP_FULL)
-#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL
-#define RTE_USART3_TX RTE_USART3_TX_FULL
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL
-#define RTE_USART3_RX RTE_USART3_RX_FULL
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL
-#define RTE_USART3_CK RTE_USART3_CK_FULL
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL
-#define RTE_USART3_CTS RTE_USART3_CTS_FULL
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL
-#define RTE_USART3_RTS RTE_USART3_RTS_FULL
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL
-#elif (RTE_USART3_REMAP_PARTIAL)
-#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL
-#define RTE_USART3_TX RTE_USART3_TX_PARTIAL
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL
-#define RTE_USART3_RX RTE_USART3_RX_PARTIAL
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL
-#define RTE_USART3_CK RTE_USART3_CK_PARTIAL
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL
-#define RTE_USART3_CTS RTE_USART3_CTS_DEF
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
-#define RTE_USART3_RTS RTE_USART3_RTS_DEF
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
-#else
-#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP
-#define RTE_USART3_TX RTE_USART3_TX_DEF
-#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF
-#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF
-#define RTE_USART3_RX RTE_USART3_RX_DEF
-#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF
-#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF
-#define RTE_USART3_CK RTE_USART3_CK_DEF
-#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF
-#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF
-#define RTE_USART3_CTS RTE_USART3_CTS_DEF
-#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
-#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
-#define RTE_USART3_RTS RTE_USART3_RTS_DEF
-#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
-#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_USART3_RX_DMA 0
-#define RTE_USART3_RX_DMA_NUMBER 1
-#define RTE_USART3_RX_DMA_CHANNEL 3
-#define RTE_USART3_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_USART3_TX_DMA 0
-#define RTE_USART3_TX_DMA_NUMBER 1
-#define RTE_USART3_TX_DMA_CHANNEL 2
-#define RTE_USART3_TX_DMA_PRIORITY 0
-
-//
-
-
-// UART4 (Universal asynchronous receiver transmitter)
-// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
-#define RTE_UART4 0
-#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// UART4_TX Pin <0=>Not Used <1=>PC10
-#define RTE_UART4_TX_ID 0
-#if (RTE_UART4_TX_ID == 0)
-#define RTE_UART4_TX 0
-#elif (RTE_UART4_TX_ID == 1)
-#define RTE_UART4_TX 1
-#define RTE_UART4_TX_PORT GPIOC
-#define RTE_UART4_TX_BIT 10
-#else
-#error "Invalid UART4_TX Pin Configuration!"
-#endif
-
-// UART4_RX Pin <0=>Not Used <1=>PC11
-#define RTE_UART4_RX_ID 0
-#if (RTE_UART4_RX_ID == 0)
-#define RTE_UART4_RX 0
-#elif (RTE_UART4_RX_ID == 1)
-#define RTE_UART4_RX 1
-#define RTE_UART4_RX_PORT GPIOC
-#define RTE_UART4_RX_BIT 11
-#else
-#error "Invalid UART4_RX Pin Configuration!"
-#endif
-
-
-// DMA Rx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_UART4_RX_DMA 0
-#define RTE_UART4_RX_DMA_NUMBER 2
-#define RTE_UART4_RX_DMA_CHANNEL 3
-#define RTE_UART4_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-// Sets DMA Channel priority
-//
-#define RTE_UART4_TX_DMA 0
-#define RTE_UART4_TX_DMA_NUMBER 2
-#define RTE_UART4_TX_DMA_CHANNEL 5
-#define RTE_UART4_TX_DMA_PRIORITY 0
-
-//
-
-
-// UART5 (Universal asynchronous receiver transmitter)
-// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
-#define RTE_UART5 0
-#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// UART5_TX Pin <0=>Not Used <1=>PC12
-#define RTE_UART5_TX_ID 0
-#if (RTE_UART5_TX_ID == 0)
-#define RTE_UART5_TX 0
-#elif (RTE_UART5_TX_ID == 1)
-#define RTE_UART5_TX 1
-#define RTE_UART5_TX_PORT GPIOC
-#define RTE_UART5_TX_BIT 12
-#else
-#error "Invalid UART5_TX Pin Configuration!"
-#endif
-
-// UART5_RX Pin <0=>Not Used <1=>PD2
-#define RTE_UART5_RX_ID 0
-#if (RTE_UART5_RX_ID == 0)
-#define RTE_UART5_RX 0
-#elif (RTE_UART5_RX_ID == 1)
-#define RTE_UART5_RX 1
-#define RTE_UART5_RX_PORT GPIOD
-#define RTE_UART5_RX_BIT 2
-#else
-#error "Invalid UART5_RX Pin Configuration!"
-#endif
-//
-
-
-// I2C1 (Inter-integrated Circuit Interface 1)
-// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
-#define RTE_I2C1 0
-
-// I2C1_SCL Pin <0=>PB6
-#define RTE_I2C1_SCL_PORT_ID_DEF 0
-#if (RTE_I2C1_SCL_PORT_ID_DEF == 0)
-#define RTE_I2C1_SCL_PORT_DEF GPIOB
-#define RTE_I2C1_SCL_BIT_DEF 6
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1_SDA Pin <0=>PB7
-#define RTE_I2C1_SDA_PORT_ID_DEF 0
-#if (RTE_I2C1_SDA_PORT_ID_DEF == 0)
-#define RTE_I2C1_SDA_PORT_DEF GPIOB
-#define RTE_I2C1_SDA_BIT_DEF 7
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1 Pin Remap
-// Enable I2C1 Pin Remapping
-#define RTE_I2C1_REMAP_FULL 0
-
-// I2C1_SCL Pin <0=>PB8
-#define RTE_I2C1_SCL_PORT_ID_FULL 0
-#if (RTE_I2C1_SCL_PORT_ID_FULL == 0)
-#define RTE_I2C1_SCL_PORT_FULL GPIOB
-#define RTE_I2C1_SCL_BIT_FULL 8
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-// I2C1_SDA Pin <0=>PB9
-#define RTE_I2C1_SDA_PORT_ID_FULL 0
-#if (RTE_I2C1_SDA_PORT_ID_FULL == 0)
-#define RTE_I2C1_SDA_PORT_FULL GPIOB
-#define RTE_I2C1_SDA_BIT_FULL 9
-#else
-#error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_I2C1_REMAP_FULL)
-#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP
-#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL
-#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL
-#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL
-#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL
-#else
-#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP
-#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF
-#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF
-#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF
-#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF
-#endif
-
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <7=>7
-// Selects DMA Channel (only Channel 7 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C1_RX_DMA 0
-#define RTE_I2C1_RX_DMA_NUMBER 1
-#define RTE_I2C1_RX_DMA_CHANNEL 7
-#define RTE_I2C1_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <6=>6
-// Selects DMA Channel (only Channel 6 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C1_TX_DMA 0
-#define RTE_I2C1_TX_DMA_NUMBER 1
-#define RTE_I2C1_TX_DMA_CHANNEL 6
-#define RTE_I2C1_TX_DMA_PRIORITY 0
-
-//
-
-
-// I2C2 (Inter-integrated Circuit Interface 2)
-// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
-#define RTE_I2C2 0
-#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP
-
-// I2C2_SCL Pin <0=>PB10
-#define RTE_I2C2_SCL_PORT_ID 0
-#if (RTE_I2C2_SCL_PORT_ID == 0)
-#define RTE_I2C2_SCL_PORT GPIOB
-#define RTE_I2C2_SCL_BIT 10
-#else
-#error "Invalid I2C2_SCL Pin Configuration!"
-#endif
-
-// I2C2_SDA Pin <0=>PB11
-#define RTE_I2C2_SDA_PORT_ID 0
-#if (RTE_I2C2_SDA_PORT_ID == 0)
-#define RTE_I2C2_SDA_PORT GPIOB
-#define RTE_I2C2_SDA_BIT 11
-#else
-#error "Invalid I2C2_SCL Pin Configuration!"
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C2_RX_DMA 1
-#define RTE_I2C2_RX_DMA_NUMBER 1
-#define RTE_I2C2_RX_DMA_CHANNEL 5
-#define RTE_I2C2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_I2C2_TX_DMA 1
-#define RTE_I2C2_TX_DMA_NUMBER 1
-#define RTE_I2C2_TX_DMA_CHANNEL 4
-#define RTE_I2C2_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
-// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
-#define RTE_SPI1 0
-
-// SPI1_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI1_NSS_PIN 1
-#define RTE_SPI1_NSS_PORT GPIO_PORT(0)
-#define RTE_SPI1_NSS_BIT 4
-
-// SPI1_SCK Pin <0=>PA5
-#define RTE_SPI1_SCK_PORT_ID_DEF 0
-#if (RTE_SPI1_SCK_PORT_ID_DEF == 0)
-#define RTE_SPI1_SCK_PORT_DEF GPIOA
-#define RTE_SPI1_SCK_BIT_DEF 5
-#else
-#error "Invalid SPI1_SCK Pin Configuration!"
-#endif
-
-// SPI1_MISO Pin <0=>Not Used <1=>PA6
-#define RTE_SPI1_MISO_PORT_ID_DEF 0
-#if (RTE_SPI1_MISO_PORT_ID_DEF == 0)
-#define RTE_SPI1_MISO_DEF 0
-#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1)
-#define RTE_SPI1_MISO_DEF 1
-#define RTE_SPI1_MISO_PORT_DEF GPIOA
-#define RTE_SPI1_MISO_BIT_DEF 6
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-
-// SPI1_MOSI Pin <0=>Not Used <1=>PA7
-#define RTE_SPI1_MOSI_PORT_ID_DEF 0
-#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
-#define RTE_SPI1_MOSI_DEF 0
-#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
-#define RTE_SPI1_MOSI_DEF 1
-#define RTE_SPI1_MOSI_PORT_DEF GPIOA
-#define RTE_SPI1_MOSI_BIT_DEF 7
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-
-// SPI1 Pin Remap
-// Enable SPI1 Pin Remapping.
-#define RTE_SPI1_REMAP 0
-
-// SPI1_SCK Pin <0=>PB3
-#define RTE_SPI1_SCK_PORT_ID_FULL 0
-#if (RTE_SPI1_SCK_PORT_ID_FULL == 0)
-#define RTE_SPI1_SCK_PORT_FULL GPIOB
-#define RTE_SPI1_SCK_BIT_FULL 3
-#else
-#error "Invalid SPI1_SCK Pin Configuration!"
-#endif
-
-// SPI1_MISO Pin <0=>Not Used <1=>PB4
-#define RTE_SPI1_MISO_PORT_ID_FULL 0
-#if (RTE_SPI1_MISO_PORT_ID_FULL == 0)
-#define RTE_SPI1_MISO_FULL 0
-#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1)
-#define RTE_SPI1_MISO_FULL 1
-#define RTE_SPI1_MISO_PORT_FULL GPIOB
-#define RTE_SPI1_MISO_BIT_FULL 4
-#else
-#error "Invalid SPI1_MISO Pin Configuration!"
-#endif
-// SPI1_MOSI Pin <0=>Not Used <1=>PB5
-#define RTE_SPI1_MOSI_PORT_ID_FULL 0
-#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
-#define RTE_SPI1_MOSI_FULL 0
-#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
-#define RTE_SPI1_MOSI_FULL 1
-#define RTE_SPI1_MOSI_PORT_FULL GPIOB
-#define RTE_SPI1_MOSI_BIT_FULL 5
-#else
-#error "Invalid SPI1_MOSI Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_SPI1_REMAP)
-#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP
-#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL
-#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL
-#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL
-#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL
-#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL
-#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL
-#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL
-#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL
-#else
-#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP
-#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF
-#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF
-#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF
-#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF
-#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF
-#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF
-#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF
-#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI1_RX_DMA 0
-#define RTE_SPI1_RX_DMA_NUMBER 1
-#define RTE_SPI1_RX_DMA_CHANNEL 2
-#define RTE_SPI1_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <3=>3
-// Selects DMA Channel (only Channel 3 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI1_TX_DMA 0
-#define RTE_SPI1_TX_DMA_NUMBER 1
-#define RTE_SPI1_TX_DMA_CHANNEL 3
-#define RTE_SPI1_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
-// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
-#define RTE_SPI2 0
-
-// SPI2_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI2_NSS_PIN 1
-#define RTE_SPI2_NSS_PORT GPIO_PORT(1)
-#define RTE_SPI2_NSS_BIT 12
-
-// SPI2_SCK Pin <0=>PB13
-#define RTE_SPI2_SCK_PORT_ID 0
-#if (RTE_SPI2_SCK_PORT_ID == 0)
-#define RTE_SPI2_SCK_PORT GPIOB
-#define RTE_SPI2_SCK_BIT 13
-#define RTE_SPI2_SCK_REMAP 0
-#else
-#error "Invalid SPI2_SCK Pin Configuration!"
-#endif
-
-// SPI2_MISO Pin <0=>Not Used <1=>PB14
-#define RTE_SPI2_MISO_PORT_ID 0
-#if (RTE_SPI2_MISO_PORT_ID == 0)
-#define RTE_SPI2_MISO 0
-#elif (RTE_SPI2_MISO_PORT_ID == 1)
-#define RTE_SPI2_MISO 1
-#define RTE_SPI2_MISO_PORT GPIOB
-#define RTE_SPI2_MISO_BIT 14
-#define RTE_SPI2_MISO_REMAP 0
-#else
-#error "Invalid SPI2_MISO Pin Configuration!"
-#endif
-
-// SPI2_MOSI Pin <0=>Not Used <1=>PB15
-#define RTE_SPI2_MOSI_PORT_ID 0
-#if (RTE_SPI2_MOSI_PORT_ID == 0)
-#define RTE_SPI2_MOSI 0
-#elif (RTE_SPI2_MOSI_PORT_ID == 1)
-#define RTE_SPI2_MOSI 1
-#define RTE_SPI2_MOSI_PORT GPIOB
-#define RTE_SPI2_MOSI_BIT 15
-#define RTE_SPI2_MOSI_REMAP 0
-#else
-#error "Invalid SPI2_MISO Pin Configuration!"
-#endif
-
-// DMA Rx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI2_RX_DMA 0
-#define RTE_SPI2_RX_DMA_NUMBER 1
-#define RTE_SPI2_RX_DMA_CHANNEL 4
-#define RTE_SPI2_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <1=>1
-// Selects DMA Number (only DMA1 can be used)
-// Channel <5=>5
-// Selects DMA Channel (only Channel 5 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI2_TX_DMA 0
-#define RTE_SPI2_TX_DMA_NUMBER 1
-#define RTE_SPI2_TX_DMA_CHANNEL 5
-#define RTE_SPI2_TX_DMA_PRIORITY 0
-
-//
-
-
-// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
-// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
-#define RTE_SPI3 0
-
-// SPI3_NSS Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..G, y = 0..15)
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SPI3_NSS_PIN 1
-#define RTE_SPI3_NSS_PORT GPIO_PORT(0)
-#define RTE_SPI3_NSS_BIT 15
-
-// SPI3_SCK Pin <0=>PB3
-#define RTE_SPI3_SCK_PORT_ID_DEF 0
-#if (RTE_SPI3_SCK_PORT_ID_DEF == 0)
-#define RTE_SPI3_SCK_PORT_DEF GPIOB
-#define RTE_SPI3_SCK_BIT_DEF 3
-#else
-#error "Invalid SPI3_SCK Pin Configuration!"
-#endif
-
-// SPI3_MISO Pin <0=>Not Used <1=>PB4
-#define RTE_SPI3_MISO_PORT_ID_DEF 0
-#if (RTE_SPI3_MISO_PORT_ID_DEF == 0)
-#define RTE_SPI3_MISO_DEF 0
-#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1)
-#define RTE_SPI3_MISO_DEF 1
-#define RTE_SPI3_MISO_PORT_DEF GPIOB
-#define RTE_SPI3_MISO_BIT_DEF 4
-#else
-#error "Invalid SPI3_MISO Pin Configuration!"
-#endif
-
-// SPI3_MOSI <0=>Not Used Pin <1=>PB5
-#define RTE_SPI3_MOSI_PORT_ID_DEF 0
-#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
-#define RTE_SPI3_MOSI_DEF 0
-#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
-#define RTE_SPI3_MOSI_DEF 1
-#define RTE_SPI3_MOSI_PORT_DEF GPIOB
-#define RTE_SPI3_MOSI_BIT_DEF 5
-#else
-#error "Invalid SPI3_MOSI Pin Configuration!"
-#endif
-
-// SPI3 Pin Remap
-// Enable SPI3 Pin Remapping.
-// SPI 3 Pin Remapping is available only in connectivity line devices!
-#define RTE_SPI3_REMAP 0
-
-// SPI3_SCK Pin <0=>PC10
-#define RTE_SPI3_SCK_PORT_ID_FULL 0
-#if (RTE_SPI3_SCK_PORT_ID_FULL == 0)
-#define RTE_SPI3_SCK_PORT_FULL GPIOC
-#define RTE_SPI3_SCK_BIT_FULL 10
-#else
-#error "Invalid SPI3_SCK Pin Configuration!"
-#endif
-
-// SPI3_MISO Pin <0=>Not Used <1=>PC11
-#define RTE_SPI3_MISO_PORT_ID_FULL 0
-#if (RTE_SPI3_MISO_PORT_ID_FULL == 0)
-#define RTE_SPI3_MISO_FULL 0
-#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1)
-#define RTE_SPI3_MISO_FULL 1
-#define RTE_SPI3_MISO_PORT_FULL GPIOC
-#define RTE_SPI3_MISO_BIT_FULL 11
-#else
-#error "Invalid SPI3_MISO Pin Configuration!"
-#endif
-// SPI3_MOSI Pin <0=>Not Used <1=>PC12
-#define RTE_SPI3_MOSI_PORT_ID_FULL 0
-#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
-#define RTE_SPI3_MOSI_FULL 0
-#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
-#define RTE_SPI3_MOSI_FULL 1
-#define RTE_SPI3_MOSI_PORT_FULL GPIOC
-#define RTE_SPI3_MOSI_BIT_FULL 12
-#else
-#error "Invalid SPI3_MOSI Pin Configuration!"
-#endif
-
-//
-
-#if (RTE_SPI3_REMAP)
-#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP
-#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL
-#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL
-#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL
-#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL
-#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL
-#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL
-#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL
-#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL
-#else
-#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP
-#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF
-#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF
-#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF
-#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF
-#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF
-#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF
-#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF
-#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF
-#endif
-
-// DMA Rx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <1=>1
-// Selects DMA Channel (only Channel 1 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI3_RX_DMA 0
-#define RTE_SPI3_RX_DMA_NUMBER 2
-#define RTE_SPI3_RX_DMA_CHANNEL 1
-#define RTE_SPI3_RX_DMA_PRIORITY 0
-
-// DMA Tx
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <2=>2
-// Selects DMA Channel (only Channel 2 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SPI3_TX_DMA 0
-#define RTE_SPI3_TX_DMA_NUMBER 2
-#define RTE_SPI3_TX_DMA_CHANNEL 2
-#define RTE_SPI3_TX_DMA_PRIORITY 0
-
-//
-
-
-// SDIO (Secure Digital Input/Output) [Driver_MCI0]
-// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
-#define RTE_SDIO 0
-
-// SDIO Peripheral Bus
-// SDIO_CK Pin <0=>PC12
-#define RTE_SDIO_CK_PORT_ID 0
-#if (RTE_SDIO_CK_PORT_ID == 0)
- #define RTE_SDIO_CK_PORT GPIOC
- #define RTE_SDIO_CK_PIN 12
-#else
- #error "Invalid SDIO_CLK Pin Configuration!"
-#endif
-// SDIO_CMD Pin <0=>PD2
-#define RTE_SDIO_CMD_PORT_ID 0
-#if (RTE_SDIO_CMD_PORT_ID == 0)
- #define RTE_SDIO_CMD_PORT GPIOD
- #define RTE_SDIO_CMD_PIN 2
-#else
- #error "Invalid SDIO_CMD Pin Configuration!"
-#endif
-// SDIO_D0 Pin <0=>PC8
-#define RTE_SDIO_D0_PORT_ID 0
-#if (RTE_SDIO_D0_PORT_ID == 0)
- #define RTE_SDIO_D0_PORT GPIOC
- #define RTE_SDIO_D0_PIN 8
-#else
- #error "Invalid SDIO_DAT0 Pin Configuration!"
-#endif
-// SDIO_D[1 .. 3]
-#define RTE_SDIO_BUS_WIDTH_4 1
-// SDIO_D1 Pin <0=>PC9
-#define RTE_SDIO_D1_PORT_ID 0
-#if (RTE_SDIO_D1_PORT_ID == 0)
- #define RTE_SDIO_D1_PORT GPIOC
- #define RTE_SDIO_D1_PIN 9
-#else
- #error "Invalid SDIO_D1 Pin Configuration!"
-#endif
-// SDIO_D2 Pin <0=>PC10
-#define RTE_SDIO_D2_PORT_ID 0
-#if (RTE_SDIO_D2_PORT_ID == 0)
- #define RTE_SDIO_D2_PORT GPIOC
- #define RTE_SDIO_D2_PIN 10
-#else
- #error "Invalid SDIO_D2 Pin Configuration!"
-#endif
-// SDIO_D3 Pin <0=>PC11
-#define RTE_SDIO_D3_PORT_ID 0
-#if (RTE_SDIO_D3_PORT_ID == 0)
- #define RTE_SDIO_D3_PORT GPIOC
- #define RTE_SDIO_D3_PIN 11
-#else
- #error "Invalid SDIO_D3 Pin Configuration!"
-#endif
-// SDIO_D[1 .. 3]
-// SDIO_D[4 .. 7]
-#define RTE_SDIO_BUS_WIDTH_8 0
-// SDIO_D4 Pin <0=>PB8
-#define RTE_SDIO_D4_PORT_ID 0
-#if (RTE_SDIO_D4_PORT_ID == 0)
- #define RTE_SDIO_D4_PORT GPIOB
- #define RTE_SDIO_D4_PIN 8
-#else
- #error "Invalid SDIO_D4 Pin Configuration!"
-#endif
-// SDIO_D5 Pin <0=>PB9
-#define RTE_SDIO_D5_PORT_ID 0
-#if (RTE_SDIO_D5_PORT_ID == 0)
- #define RTE_SDIO_D5_PORT GPIOB
- #define RTE_SDIO_D5_PIN 9
-#else
- #error "Invalid SDIO_D5 Pin Configuration!"
-#endif
-// SDIO_D6 Pin <0=>PC6
-#define RTE_SDIO_D6_PORT_ID 0
-#if (RTE_SDIO_D6_PORT_ID == 0)
- #define RTE_SDIO_D6_PORT GPIOC
- #define RTE_SDIO_D6_PIN 6
-#else
- #error "Invalid SDIO_D6 Pin Configuration!"
-#endif
-// SDIO_D7 Pin <0=>PC7
-#define RTE_SDIO_D7_PORT_ID 0
-#if (RTE_SDIO_D7_PORT_ID == 0)
- #define RTE_SDIO_D7_PORT GPIOC
- #define RTE_SDIO_D7_PIN 7
-#else
- #error "Invalid SDIO_D7 Pin Configuration!"
-#endif
-// SDIO_D[4 .. 7]
-// SDIO Peripheral Bus
-
-// Card Detect Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SDIO_CD_EN 1
-#define RTE_SDIO_CD_ACTIVE 0
-#define RTE_SDIO_CD_PORT GPIO_PORT(5)
-#define RTE_SDIO_CD_PIN 11
-
-// Write Protect Pin
-// Configure Pin if exists
-// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_SDIO_WP_EN 0
-#define RTE_SDIO_WP_ACTIVE 1
-#define RTE_SDIO_WP_PORT GPIO_PORT(0)
-#define RTE_SDIO_WP_PIN 10
-
-// DMA
-// Number <2=>2
-// Selects DMA Number (only DMA2 can be used)
-// Channel <4=>4
-// Selects DMA Channel (only Channel 4 can be used)
-// Priority <0=>Low <1=>Medium <2=>High <3=>Very High
-// Selects DMA Priority
-//
-#define RTE_SDIO_DMA_NUMBER 2
-#define RTE_SDIO_DMA_CHANNEL 4
-#define RTE_SDIO_DMA_PRIORITY 0
-
-//
-
-
-// CAN1 (Controller Area Network 1) [Driver_CAN1]
-// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
-#define RTE_CAN1 0
-
-// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
-#define RTE_CAN1_RX_PORT_ID 0
-#if (RTE_CAN1_RX_PORT_ID == 0)
-#define RTE_CAN1_RX_PORT GPIOA
-#define RTE_CAN1_RX_BIT 11
-#elif (RTE_CAN1_RX_PORT_ID == 1)
-#define RTE_CAN1_RX_PORT GPIOB
-#define RTE_CAN1_RX_BIT 8
-#elif (RTE_CAN1_RX_PORT_ID == 2)
-#define RTE_CAN1_RX_PORT GPIOD
-#define RTE_CAN1_RX_BIT 0
-#else
-#error "Invalid CAN1_RX Pin Configuration!"
-#endif
-
-// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
-#define RTE_CAN1_TX_PORT_ID 0
-#if (RTE_CAN1_TX_PORT_ID == 0)
-#define RTE_CAN1_TX_PORT GPIOA
-#define RTE_CAN1_TX_BIT 12
-#elif (RTE_CAN1_TX_PORT_ID == 1)
-#define RTE_CAN1_TX_PORT GPIOB
-#define RTE_CAN1_TX_BIT 9
-#elif (RTE_CAN1_TX_PORT_ID == 2)
-#define RTE_CAN1_TX_PORT GPIOD
-#define RTE_CAN1_TX_BIT 1
-#else
-#error "Invalid CAN1_TX Pin Configuration!"
-#endif
-
-//
-
-
-// CAN2 (Controller Area Network 2) [Driver_CAN2]
-// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
-#define RTE_CAN2 0
-
-// CAN2_RX Pin <0=>PB5 <1=>PB12
-#define RTE_CAN2_RX_PORT_ID 0
-#if (RTE_CAN2_RX_PORT_ID == 0)
-#define RTE_CAN2_RX_PORT GPIOB
-#define RTE_CAN2_RX_BIT 5
-#elif (RTE_CAN2_RX_PORT_ID == 1)
-#define RTE_CAN2_RX_PORT GPIOB
-#define RTE_CAN2_RX_BIT 12
-#else
-#error "Invalid CAN2_RX Pin Configuration!"
-#endif
-
-// CAN2_TX Pin <0=>PB6 <1=>PB13
-#define RTE_CAN2_TX_PORT_ID 0
-#if (RTE_CAN2_TX_PORT_ID == 0)
-#define RTE_CAN2_TX_PORT GPIOB
-#define RTE_CAN2_TX_BIT 6
-#elif (RTE_CAN2_TX_PORT_ID == 1)
-#define RTE_CAN2_TX_PORT GPIOB
-#define RTE_CAN2_TX_BIT 13
-#else
-#error "Invalid CAN2_TX Pin Configuration!"
-#endif
-
-//
-
-
-// ETH (Ethernet Interface) [Driver_ETH_MAC0]
-// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
-#define RTE_ETH 0
-
-// MII (Media Independent Interface)
-// Enable Media Independent Interface pin configuration
-#define RTE_ETH_MII 0
-
-// ETH_MII_TX_CLK Pin <0=>PC3
-#define RTE_ETH_MII_TX_CLK_PORT_ID 0
-#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
-#define RTE_ETH_MII_TX_CLK_PORT GPIOC
-#define RTE_ETH_MII_TX_CLK_PIN 3
-#else
-#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
-#endif
-// ETH_MII_TXD0 Pin <0=>PB12
-#define RTE_ETH_MII_TXD0_PORT_ID 0
-#if (RTE_ETH_MII_TXD0_PORT_ID == 0)
-#define RTE_ETH_MII_TXD0_PORT GPIOB
-#define RTE_ETH_MII_TXD0_PIN 12
-#else
-#error "Invalid ETH_MII_TXD0 Pin Configuration!"
-#endif
-// ETH_MII_TXD1 Pin <0=>PB13
-#define RTE_ETH_MII_TXD1_PORT_ID 0
-#if (RTE_ETH_MII_TXD1_PORT_ID == 0)
-#define RTE_ETH_MII_TXD1_PORT GPIOB
-#define RTE_ETH_MII_TXD1_PIN 13
-#else
-#error "Invalid ETH_MII_TXD1 Pin Configuration!"
-#endif
-// ETH_MII_TXD2 Pin <0=>PC2
-#define RTE_ETH_MII_TXD2_PORT_ID 0
-#if (RTE_ETH_MII_TXD2_PORT_ID == 0)
-#define RTE_ETH_MII_TXD2_PORT GPIOC
-#define RTE_ETH_MII_TXD2_PIN 2
-#else
-#error "Invalid ETH_MII_TXD2 Pin Configuration!"
-#endif
-// ETH_MII_TXD3 Pin <0=>PB8
-#define RTE_ETH_MII_TXD3_PORT_ID 0
-#if (RTE_ETH_MII_TXD3_PORT_ID == 0)
-#define RTE_ETH_MII_TXD3_PORT GPIOB
-#define RTE_ETH_MII_TXD3_PIN 8
-#else
-#error "Invalid ETH_MII_TXD3 Pin Configuration!"
-#endif
-// ETH_MII_TX_EN Pin <0=>PB11
-#define RTE_ETH_MII_TX_EN_PORT_ID 0
-#if (RTE_ETH_MII_TX_EN_PORT_ID == 0)
-#define RTE_ETH_MII_TX_EN_PORT GPIOB
-#define RTE_ETH_MII_TX_EN_PIN 11
-#else
-#error "Invalid ETH_MII_TX_EN Pin Configuration!"
-#endif
-// ETH_MII_RX_CLK Pin <0=>PA1
-#define RTE_ETH_MII_RX_CLK_PORT_ID 0
-#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
-#define RTE_ETH_MII_RX_CLK_PORT GPIOA
-#define RTE_ETH_MII_RX_CLK_PIN 1
-#else
-#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
-#endif
-// ETH_MII_RXD0 Pin <0=>PC4
-#define RTE_ETH_MII_RXD0_DEF 0
-
-// ETH_MII_RXD1 Pin <0=>PC5
-#define RTE_ETH_MII_RXD1_DEF 0
-
-// ETH_MII_RXD2 Pin <0=>PB0
-#define RTE_ETH_MII_RXD2_DEF 0
-
-// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
-#define RTE_ETH_MII_RXD3_DEF 0
-
-// ETH_MII_RX_DV Pin <0=>PA7
-#define RTE_ETH_MII_RX_DV_DEF 0
-
-// ETH_MII_RX_ER Pin <0=>PB10
-#define RTE_ETH_MII_RX_ER_PORT_ID 0
-#if (RTE_ETH_MII_RX_ER_PORT_ID == 0)
-#define RTE_ETH_MII_RX_ER_PORT GPIOB
-#define RTE_ETH_MII_RX_ER_PIN 10
-#else
-#error "Invalid ETH_MII_RX_ER Pin Configuration!"
-#endif
-// ETH_MII_CRS Pin <0=>PA0
-#define RTE_ETH_MII_CRS_PORT_ID 0
-#if (RTE_ETH_MII_CRS_PORT_ID == 0)
-#define RTE_ETH_MII_CRS_PORT GPIOA
-#define RTE_ETH_MII_CRS_PIN 0
-#else
-#error "Invalid ETH_MII_CRS Pin Configuration!"
-#endif
-// ETH_MII_COL Pin <0=>PA3
-#define RTE_ETH_MII_COL_PORT_ID 0
-#if (RTE_ETH_MII_COL_PORT_ID == 0)
-#define RTE_ETH_MII_COL_PORT GPIOA
-#define RTE_ETH_MII_COL_PIN 3
-#else
-#error "Invalid ETH_MII_COL Pin Configuration!"
-#endif
-
-// Ethernet MAC I/O remapping
-// Remap Ethernet pins
-#define RTE_ETH_MII_REMAP 0
-
-// ETH_MII_RXD0 Pin <1=>PD9
-#define RTE_ETH_MII_RXD0_REMAP 1
-
-// ETH_MII_RXD1 Pin <1=>PD10
-#define RTE_ETH_MII_RXD1_REMAP 1
-
-// ETH_MII_RXD2 Pin <1=>PD11
-#define RTE_ETH_MII_RXD2_REMAP 1
-
-// ETH_MII_RXD3 Pin <1=>PD12
-#define RTE_ETH_MII_RXD3_REMAP 1
-
-// ETH_MII_RX_DV Pin <1=>PD8
-#define RTE_ETH_MII_RX_DV_REMAP 1
-//
-
-//
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
-#define RTE_ETH_MII_RXD0_PORT GPIOC
-#define RTE_ETH_MII_RXD0_PIN 4
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
-#define RTE_ETH_MII_RXD0_PORT GPIOD
-#define RTE_ETH_MII_RXD0_PIN 9
-#else
-#error "Invalid ETH_MII_RXD0 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
-#define RTE_ETH_MII_RXD1_PORT GPIOC
-#define RTE_ETH_MII_RXD1_PIN 5
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
-#define RTE_ETH_MII_RXD1_PORT GPIOD
-#define RTE_ETH_MII_RXD1_PIN 10
-#else
-#error "Invalid ETH_MII_RXD1 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
-#define RTE_ETH_MII_RXD2_PORT GPIOB
-#define RTE_ETH_MII_RXD2_PIN 0
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
-#define RTE_ETH_MII_RXD2_PORT GPIOD
-#define RTE_ETH_MII_RXD2_PIN 11
-#else
-#error "Invalid ETH_MII_RXD2 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
-#define RTE_ETH_MII_RXD3_PORT GPIOB
-#define RTE_ETH_MII_RXD3_PIN 1
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
-#define RTE_ETH_MII_RXD3_PORT GPIOD
-#define RTE_ETH_MII_RXD3_PIN 12
-#else
-#error "Invalid ETH_MII_RXD3 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
-#define RTE_ETH_MII_RX_DV_PORT GPIOA
-#define RTE_ETH_MII_RX_DV_PIN 7
-#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
-#define RTE_ETH_MII_RX_DV_PORT GPIOD
-#define RTE_ETH_MII_RX_DV_PIN 8
-#else
-#error "Invalid ETH_MII_RX_DV Pin Configuration!"
-#endif
-
-// RMII (Reduced Media Independent Interface)
-#define RTE_ETH_RMII 0
-
-// ETH_RMII_TXD0 Pin <0=>PB12
-#define RTE_ETH_RMII_TXD0_PORT_ID 0
-#if (RTE_ETH_RMII_TXD0_PORT_ID == 0)
-#define RTE_ETH_RMII_TXD0_PORT GPIOB
-#define RTE_ETH_RMII_TXD0_PIN 12
-#else
-#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
-#endif
-// ETH_RMII_TXD1 Pin <0=>PB13
-#define RTE_ETH_RMII_TXD1_PORT_ID 0
-#if (RTE_ETH_RMII_TXD1_PORT_ID == 0)
-#define RTE_ETH_RMII_TXD1_PORT GPIOB
-#define RTE_ETH_RMII_TXD1_PIN 13
-#else
-#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
-#endif
-// ETH_RMII_TX_EN Pin <0=>PB11
-#define RTE_ETH_RMII_TX_EN_PORT_ID 0
-#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
-#define RTE_ETH_RMII_TX_EN_PORT GPIOB
-#define RTE_ETH_RMII_TX_EN_PIN 11
-#else
-#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
-#endif
-// ETH_RMII_RXD0 Pin <0=>PC4
-#define RTE_ETH_RMII_RXD0_DEF 0
-
-// ETH_RMII_RXD1 Pin <0=>PC5
-#define RTE_ETH_RMII_RXD1_DEF 0
-
-// ETH_RMII_REF_CLK Pin <0=>PA1
-#define RTE_ETH_RMII_REF_CLK_PORT_ID 0
-#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
-#define RTE_ETH_RMII_REF_CLK_PORT GPIOA
-#define RTE_ETH_RMII_REF_CLK_PIN 1
-#else
-#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
-#endif
-// ETH_RMII_CRS_DV Pin <0=>PA7
-#define RTE_ETH_RMII_CRS_DV_DEF 0
-
-// Ethernet MAC I/O remapping
-// Remap Ethernet pins
-#define RTE_ETH_RMII_REMAP 0
-// ETH_RMII_RXD0 Pin <1=>PD9
-#define RTE_ETH_RMII_RXD0_REMAP 1
-
-// ETH_RMII_RXD1 Pin <1=>PD10
-#define RTE_ETH_RMII_RXD1_REMAP 1
-
-// ETH_RMII_CRS_DV Pin <1=>PD8
-#define RTE_ETH_RMII_CRS_DV_REMAP 1
-//
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
-#define RTE_ETH_RMII_RXD0_PORT GPIOC
-#define RTE_ETH_RMII_RXD0_PIN 4
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
-#define RTE_ETH_RMII_RXD0_PORT GPIOD
-#define RTE_ETH_RMII_RXD0_PIN 9
-#else
-#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
-#define RTE_ETH_RMII_RXD1_PORT GPIOC
-#define RTE_ETH_RMII_RXD1_PIN 5
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
-#define RTE_ETH_RMII_RXD1_PORT GPIOD
-#define RTE_ETH_RMII_RXD1_PIN 10
-#else
-#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
-#endif
-
-#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
-#define RTE_ETH_RMII_CRS_DV_PORT GPIOA
-#define RTE_ETH_RMII_CRS_DV_PIN 7
-#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
-#define RTE_ETH_RMII_CRS_DV_PORT GPIOD
-#define RTE_ETH_RMII_CRS_DV_PIN 8
-#else
-#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
-#endif
-
-//
-
-// Management Data Interface
-// ETH_MDC Pin <0=>PC1
-#define RTE_ETH_MDI_MDC_PORT_ID 0
-#if (RTE_ETH_MDI_MDC_PORT_ID == 0)
-#define RTE_ETH_MDI_MDC_PORT GPIOC
-#define RTE_ETH_MDI_MDC_PIN 1
-#else
-#error "Invalid ETH_MDC Pin Configuration!"
-#endif
-// ETH_MDIO Pin <0=>PA2
-#define RTE_ETH_MDI_MDIO_PORT_ID 0
-#if (RTE_ETH_MDI_MDIO_PORT_ID == 0)
-#define RTE_ETH_MDI_MDIO_PORT GPIOA
-#define RTE_ETH_MDI_MDIO_PIN 2
-#else
-#error "Invalid ETH_MDIO Pin Configuration!"
-#endif
-//
-
-// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
-#define RTE_ETH_REF_CLOCK_ID 0
-#if (RTE_ETH_REF_CLOCK_ID == 0)
-#define RTE_ETH_REF_CLOCK 0
-#elif (RTE_ETH_REF_CLOCK_ID == 1)
-#define RTE_ETH_REF_CLOCK 1
-#else
-#error "Invalid MCO Ethernet Reference Clock Configuration!"
-#endif
-//
-
-
-// USB Device Full-speed
-// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
-#define RTE_USB_DEVICE 0
-
-// CON On/Off Pin
-// Configure Pin for driving D+ pull-up
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_USB_DEVICE_CON_PIN 1
-#define RTE_USB_DEVICE_CON_ACTIVE 0
-#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1)
-#define RTE_USB_DEVICE_CON_BIT 14
-
-//
-
-
-// USB OTG Full-speed
-#define RTE_USB_OTG_FS 0
-
-// Host [Driver_USBH0]
-// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
-
-#define RTE_USB_OTG_FS_HOST 0
-
-// VBUS Power On/Off Pin
-// Configure Pin for driving VBUS
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_OTG_FS_VBUS_PIN 1
-#define RTE_OTG_FS_VBUS_ACTIVE 0
-#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2)
-#define RTE_OTG_FS_VBUS_BIT 9
-
-// Overcurrent Detection Pin
-// Configure Pin for overcurrent detection
-// GPIO Pxy (x = A..G, y = 0..15)
-// Active State <0=>Low <1=>High
-// Selects Active State Logical Level
-// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
-// <4=>GPIOE <5=>GPIOF <6=>GPIOG
-// Selects Port Name
-// Bit <0-15>
-// Selects Port Bit
-//
-#define RTE_OTG_FS_OC_PIN 1
-#define RTE_OTG_FS_OC_ACTIVE 0
-#define RTE_OTG_FS_OC_PORT GPIO_PORT(4)
-#define RTE_OTG_FS_OC_BIT 1
-//
-
-//
-
-
-#endif /* __RTE_DEVICE_H */
diff --git a/timer_act2/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/timer_act2/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
deleted file mode 100644
index 74da96c..0000000
--- a/timer_act2/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
+++ /dev/null
@@ -1,307 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name : startup_stm32f10x_md.s
-;* Author : MCD Application Team
-;* Version : V3.5.0
-;* Date : 11-March-2011
-;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
-;* toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the clock system
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1_2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
- DCD TIM1_BRK_IRQHandler ; TIM1 Break
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_IRQHandler [WEAK]
- EXPORT TIM1_UP_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/timer_act2/RTE/Device/STM32F103RB/system_stm32f10x.c b/timer_act2/RTE/Device/STM32F103RB/system_stm32f10x.c
deleted file mode 100644
index 71efc85..0000000
--- a/timer_act2/RTE/Device/STM32F103RB/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f10x.c
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * factors, AHB/APBx prescalers and Flash settings).
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f10x_xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
- * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
- * When HSE is used as system clock source, directly or through PLL, and you
- * are using different crystal you have to adapt the HSE value to your own
- * configuration.
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * © COPYRIGHT 2011 STMicroelectronics
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f10x_system
- * @{
- */
-
-/** @addtogroup STM32F10x_System_Private_Includes
- * @{
- */
-
-#include "stm32f10x.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
- frequency (after reset the HSI is used as SYSCLK source)
-
- IMPORTANT NOTE:
- ==============
- 1. After each device reset the HSI is used as System clock source.
-
- 2. Please make sure that the selected System clock doesn't exceed your device's
- maximum frequency.
-
- 3. If none of the define below is enabled, the HSI is used as System clock
- source.
-
- 4. The System clock configuration functions provided within this file assume that:
- - For Low, Medium and High density Value line devices an external 8MHz
- crystal is used to drive the System clock.
- - For Low, Medium and High density devices an external 8MHz crystal is
- used to drive the System clock.
- - For Connectivity line devices an external 25MHz crystal is used to drive
- the System clock.
- If you are using different crystal you have to adapt those functions accordingly.
- */
-
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
- #define SYSCLK_FREQ_24MHz 24000000
-#else
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz 24000000 */
-/* #define SYSCLK_FREQ_36MHz 36000000 */
-/* #define SYSCLK_FREQ_48MHz 48000000 */
-/* #define SYSCLK_FREQ_56MHz 56000000 */
-#define SYSCLK_FREQ_72MHz 72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
- STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Variables
- * @{
- */
-
-/*******************************************************************************
-* Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
- uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
- uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
- static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
- static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
- static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
- static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
- static void SetSysClockTo56(void);
-#elif defined SYSCLK_FREQ_72MHz
- static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
- RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
- RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
- /* Reset PLL2ON and PLL3ON bits */
- RCC->CR &= (uint32_t)0xEBFFFFFF;
-
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x00FF0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#else
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
- #ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
- #endif /* DATA_IN_ExtSRAM */
-#endif
-
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
- /* Configure the Flash Latency cycles and enable prefetch buffer */
- SetSysClock();
-
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
- * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
- * that HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef STM32F10X_CL
- uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
-
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-#ifndef STM32F10X_CL
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- #else
- /* HSE selected as PLL clock entry */
- if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
- {/* HSE oscillator clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
- }
- else
- {
- SystemCoreClock = HSE_VALUE * pllmull;
- }
- #endif
- }
-#else
- pllmull = pllmull >> 18;
-
- if (pllmull != 0x0D)
- {
- pllmull += 2;
- }
- else
- { /* PLL multiplication factor = PLL input clock * 6.5 */
- pllmull = 13 / 2;
- }
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {/* PREDIV1 selected as PLL clock entry */
-
- /* Get PREDIV1 clock source and division factor */
- prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-
- if (prediv1source == 0)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- else
- {/* PLL2 clock selected as PREDIV1 clock entry */
-
- /* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
- SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
- }
- }
-#endif /* STM32F10X_CL */
- break;
-
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
-
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
- SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
- SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
- SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
- SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
- SetSysClockTo56();
-#elif defined SYSCLK_FREQ_72MHz
- SetSysClockTo72();
-#endif
-
- /* If none of the define above is enabled, the HSI is used as System clock
- source (default after reset) */
-}
-
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f10x.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f10x_xx.s/.c before jump to main.
- * This function configures the external SRAM mounted on STM3210E-EVAL
- * board (STM32 High density devices). This SRAM will be used as program
- * data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
- required, then adjust the Register Addresses */
-
- /* Enable FSMC clock */
- RCC->AHBENR = 0x00000114;
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- RCC->APB2ENR = 0x000001E0;
-
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
-/*---------------- SRAM Address lines configuration -------------------------*/
-/*---------------- NOE and NWE configuration --------------------------------*/
-/*---------------- NE3 configuration ----------------------------------------*/
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- GPIOD->CRL = 0x44BB44BB;
- GPIOD->CRH = 0xBBBBBBBB;
-
- GPIOE->CRL = 0xB44444BB;
- GPIOE->CRH = 0xBBBBBBBB;
-
- GPIOF->CRL = 0x44BBBBBB;
- GPIOF->CRH = 0xBBBB4444;
-
- GPIOG->CRL = 0x44BBBBBB;
- GPIOG->CRH = 0x44444B44;
-
-/*---------------- FSMC Configuration ---------------------------------------*/
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
-
- FSMC_Bank1->BTCR[4] = 0x00001011;
- FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSE(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
- if (HSE_VALUE <= 24000000)
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
- }
- else
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
- }
-#endif /* STM32F10X_CL */
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo24(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo36(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-
- /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-#else
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo56(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL7);
-#else
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-#else
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
- RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/timer_act2/RTE/_Simulation/RTE_Components.h b/timer_act2/RTE/_Simulation/RTE_Components.h
deleted file mode 100644
index 0d97072..0000000
--- a/timer_act2/RTE/_Simulation/RTE_Components.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'timer_act2'
- * Target: 'Simulation'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "stm32f10x.h"
-
-
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/timer_act2/RTE/_Target_1/RTE_Components.h b/timer_act2/RTE/_Target_1/RTE_Components.h
deleted file mode 100644
index 6d88aff..0000000
--- a/timer_act2/RTE/_Target_1/RTE_Components.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'timer_act2'
- * Target: 'Target 1'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "stm32f10x.h"
-
-
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/timer_act2/RTE/_carteSTM/RTE_Components.h b/timer_act2/RTE/_carteSTM/RTE_Components.h
deleted file mode 100644
index ed964dc..0000000
--- a/timer_act2/RTE/_carteSTM/RTE_Components.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'timer_act2'
- * Target: 'carteSTM'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "stm32f10x.h"
-
-
-
-#endif /* RTE_COMPONENTS_H */