2479 lines
85 KiB
Text
2479 lines
85 KiB
Text
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RealOne.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00000d1c 08000188 08000188 00010188 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000000 08000ea4 08000ea4 0002000c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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3 .ARM.extab 00000000 08000ea4 08000ea4 0002000c 2**0
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CONTENTS
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4 .ARM 00000000 08000ea4 08000ea4 0002000c 2**0
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CONTENTS
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5 .preinit_array 00000000 08000ea4 08000ea4 0002000c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08000ea4 08000ea4 00010ea4 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08000ea8 08000ea8 00010ea8 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 0000000c 20000000 08000eac 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000024 2000000c 08000eb8 0002000c 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000030 08000eb8 00020030 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
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CONTENTS, READONLY
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12 .debug_info 00004bd6 00000000 00000000 0002003c 2**0
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CONTENTS, READONLY, DEBUGGING
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13 .debug_abbrev 00000d51 00000000 00000000 00024c12 2**0
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CONTENTS, READONLY, DEBUGGING
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14 .debug_aranges 000005b8 00000000 00000000 00025968 2**3
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CONTENTS, READONLY, DEBUGGING
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15 .debug_ranges 00000540 00000000 00000000 00025f20 2**3
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CONTENTS, READONLY, DEBUGGING
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16 .debug_macro 00026337 00000000 00000000 00026460 2**0
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CONTENTS, READONLY, DEBUGGING
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17 .debug_line 000040fa 00000000 00000000 0004c797 2**0
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CONTENTS, READONLY, DEBUGGING
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18 .debug_str 000ee8c5 00000000 00000000 00050891 2**0
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CONTENTS, READONLY, DEBUGGING
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19 .comment 0000007b 00000000 00000000 0013f156 2**0
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CONTENTS, READONLY
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20 .debug_frame 000015c0 00000000 00000000 0013f1d4 2**2
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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08000188 <__do_global_dtors_aux>:
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8000188: b510 push {r4, lr}
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800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
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800018c: 7823 ldrb r3, [r4, #0]
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800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
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8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
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8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
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8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
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8000196: f3af 8000 nop.w
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800019a: 2301 movs r3, #1
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800019c: 7023 strb r3, [r4, #0]
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800019e: bd10 pop {r4, pc}
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80001a0: 2000000c .word 0x2000000c
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80001a4: 00000000 .word 0x00000000
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80001a8: 08000e8c .word 0x08000e8c
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080001ac <frame_dummy>:
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80001ac: b508 push {r3, lr}
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80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
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80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
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80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
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80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
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80001b6: f3af 8000 nop.w
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80001ba: bd08 pop {r3, pc}
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80001bc: 00000000 .word 0x00000000
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80001c0: 20000010 .word 0x20000010
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80001c4: 08000e8c .word 0x08000e8c
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080001c8 <LL_AHB2_GRP1_EnableClock>:
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
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{
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80001c8: b480 push {r7}
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80001ca: b085 sub sp, #20
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80001cc: af00 add r7, sp, #0
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80001ce: 6078 str r0, [r7, #4]
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHB2ENR, Periphs);
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80001d0: 4b08 ldr r3, [pc, #32] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
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80001d2: 6cda ldr r2, [r3, #76] ; 0x4c
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80001d4: 4907 ldr r1, [pc, #28] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
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80001d6: 687b ldr r3, [r7, #4]
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80001d8: 4313 orrs r3, r2
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80001da: 64cb str r3, [r1, #76] ; 0x4c
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
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80001dc: 4b05 ldr r3, [pc, #20] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
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80001de: 6cda ldr r2, [r3, #76] ; 0x4c
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80001e0: 687b ldr r3, [r7, #4]
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80001e2: 4013 ands r3, r2
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80001e4: 60fb str r3, [r7, #12]
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(void)tmpreg;
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80001e6: 68fb ldr r3, [r7, #12]
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}
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80001e8: bf00 nop
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80001ea: 3714 adds r7, #20
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80001ec: 46bd mov sp, r7
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80001ee: f85d 7b04 ldr.w r7, [sp], #4
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80001f2: 4770 bx lr
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80001f4: 40021000 .word 0x40021000
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080001f8 <LL_GPIO_SetPinMode>:
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* @arg @ref LL_GPIO_MODE_ALTERNATE
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* @arg @ref LL_GPIO_MODE_ANALOG
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
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{
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80001f8: b480 push {r7}
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80001fa: b08b sub sp, #44 ; 0x2c
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80001fc: af00 add r7, sp, #0
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80001fe: 60f8 str r0, [r7, #12]
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8000200: 60b9 str r1, [r7, #8]
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8000202: 607a str r2, [r7, #4]
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MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
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8000204: 68fb ldr r3, [r7, #12]
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8000206: 681a ldr r2, [r3, #0]
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8000208: 68bb ldr r3, [r7, #8]
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800020a: 617b str r3, [r7, #20]
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uint32_t result;
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
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__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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800020c: 697b ldr r3, [r7, #20]
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800020e: fa93 f3a3 rbit r3, r3
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8000212: 613b str r3, [r7, #16]
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result |= value & 1U;
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s--;
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}
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result <<= s; /* shift when v's highest bits are zero */
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#endif
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return result;
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8000214: 693b ldr r3, [r7, #16]
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8000216: 61bb str r3, [r7, #24]
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optimisations using the logic "value was passed to __builtin_clz, so it
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is non-zero".
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ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
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single CLZ instruction.
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*/
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if (value == 0U)
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8000218: 69bb ldr r3, [r7, #24]
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800021a: 2b00 cmp r3, #0
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800021c: d101 bne.n 8000222 <LL_GPIO_SetPinMode+0x2a>
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{
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return 32U;
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800021e: 2320 movs r3, #32
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8000220: e003 b.n 800022a <LL_GPIO_SetPinMode+0x32>
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}
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return __builtin_clz(value);
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8000222: 69bb ldr r3, [r7, #24]
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8000224: fab3 f383 clz r3, r3
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8000228: b2db uxtb r3, r3
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800022a: 005b lsls r3, r3, #1
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800022c: 2103 movs r1, #3
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800022e: fa01 f303 lsl.w r3, r1, r3
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8000232: 43db mvns r3, r3
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8000234: 401a ands r2, r3
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8000236: 68bb ldr r3, [r7, #8]
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8000238: 623b str r3, [r7, #32]
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__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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800023a: 6a3b ldr r3, [r7, #32]
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800023c: fa93 f3a3 rbit r3, r3
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8000240: 61fb str r3, [r7, #28]
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return result;
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8000242: 69fb ldr r3, [r7, #28]
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8000244: 627b str r3, [r7, #36] ; 0x24
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if (value == 0U)
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8000246: 6a7b ldr r3, [r7, #36] ; 0x24
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8000248: 2b00 cmp r3, #0
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800024a: d101 bne.n 8000250 <LL_GPIO_SetPinMode+0x58>
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return 32U;
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800024c: 2320 movs r3, #32
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800024e: e003 b.n 8000258 <LL_GPIO_SetPinMode+0x60>
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return __builtin_clz(value);
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8000250: 6a7b ldr r3, [r7, #36] ; 0x24
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8000252: fab3 f383 clz r3, r3
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8000256: b2db uxtb r3, r3
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8000258: 005b lsls r3, r3, #1
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800025a: 6879 ldr r1, [r7, #4]
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800025c: fa01 f303 lsl.w r3, r1, r3
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8000260: 431a orrs r2, r3
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8000262: 68fb ldr r3, [r7, #12]
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8000264: 601a str r2, [r3, #0]
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}
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8000266: bf00 nop
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8000268: 372c adds r7, #44 ; 0x2c
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800026a: 46bd mov sp, r7
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800026c: f85d 7b04 ldr.w r7, [sp], #4
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8000270: 4770 bx lr
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08000272 <LL_GPIO_SetPinOutputType>:
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* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
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* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
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{
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8000272: b480 push {r7}
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8000274: b085 sub sp, #20
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8000276: af00 add r7, sp, #0
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8000278: 60f8 str r0, [r7, #12]
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800027a: 60b9 str r1, [r7, #8]
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800027c: 607a str r2, [r7, #4]
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MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
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800027e: 68fb ldr r3, [r7, #12]
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8000280: 685a ldr r2, [r3, #4]
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8000282: 68bb ldr r3, [r7, #8]
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8000284: 43db mvns r3, r3
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8000286: 401a ands r2, r3
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8000288: 68bb ldr r3, [r7, #8]
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800028a: 6879 ldr r1, [r7, #4]
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800028c: fb01 f303 mul.w r3, r1, r3
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8000290: 431a orrs r2, r3
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8000292: 68fb ldr r3, [r7, #12]
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8000294: 605a str r2, [r3, #4]
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}
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8000296: bf00 nop
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8000298: 3714 adds r7, #20
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800029a: 46bd mov sp, r7
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800029c: f85d 7b04 ldr.w r7, [sp], #4
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80002a0: 4770 bx lr
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080002a2 <LL_GPIO_IsInputPinSet>:
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* @arg @ref LL_GPIO_PIN_15
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* @arg @ref LL_GPIO_PIN_ALL
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
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{
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80002a2: b480 push {r7}
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80002a4: b083 sub sp, #12
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80002a6: af00 add r7, sp, #0
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80002a8: 6078 str r0, [r7, #4]
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80002aa: 6039 str r1, [r7, #0]
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return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
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80002ac: 687b ldr r3, [r7, #4]
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80002ae: 691a ldr r2, [r3, #16]
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80002b0: 683b ldr r3, [r7, #0]
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80002b2: 4013 ands r3, r2
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80002b4: 683a ldr r2, [r7, #0]
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80002b6: 429a cmp r2, r3
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80002b8: d101 bne.n 80002be <LL_GPIO_IsInputPinSet+0x1c>
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80002ba: 2301 movs r3, #1
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80002bc: e000 b.n 80002c0 <LL_GPIO_IsInputPinSet+0x1e>
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80002be: 2300 movs r3, #0
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}
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80002c0: 4618 mov r0, r3
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80002c2: 370c adds r7, #12
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80002c4: 46bd mov sp, r7
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80002c6: f85d 7b04 ldr.w r7, [sp], #4
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80002ca: 4770 bx lr
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080002cc <LL_GPIO_SetOutputPin>:
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* @arg @ref LL_GPIO_PIN_15
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* @arg @ref LL_GPIO_PIN_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
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{
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80002cc: b480 push {r7}
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80002ce: b083 sub sp, #12
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80002d0: af00 add r7, sp, #0
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80002d2: 6078 str r0, [r7, #4]
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80002d4: 6039 str r1, [r7, #0]
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WRITE_REG(GPIOx->BSRR, PinMask);
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80002d6: 687b ldr r3, [r7, #4]
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80002d8: 683a ldr r2, [r7, #0]
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80002da: 619a str r2, [r3, #24]
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}
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80002dc: bf00 nop
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80002de: 370c adds r7, #12
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80002e0: 46bd mov sp, r7
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80002e2: f85d 7b04 ldr.w r7, [sp], #4
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80002e6: 4770 bx lr
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080002e8 <LL_GPIO_ResetOutputPin>:
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* @arg @ref LL_GPIO_PIN_15
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* @arg @ref LL_GPIO_PIN_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
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{
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80002e8: b480 push {r7}
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80002ea: b083 sub sp, #12
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80002ec: af00 add r7, sp, #0
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80002ee: 6078 str r0, [r7, #4]
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80002f0: 6039 str r1, [r7, #0]
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WRITE_REG(GPIOx->BRR, PinMask);
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80002f2: 687b ldr r3, [r7, #4]
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80002f4: 683a ldr r2, [r7, #0]
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80002f6: 629a str r2, [r3, #40] ; 0x28
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}
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80002f8: bf00 nop
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80002fa: 370c adds r7, #12
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80002fc: 46bd mov sp, r7
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80002fe: f85d 7b04 ldr.w r7, [sp], #4
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8000302: 4770 bx lr
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08000304 <LL_GPIO_TogglePin>:
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* @arg @ref LL_GPIO_PIN_15
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* @arg @ref LL_GPIO_PIN_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
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{
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8000304: b480 push {r7}
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8000306: b085 sub sp, #20
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8000308: af00 add r7, sp, #0
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800030a: 6078 str r0, [r7, #4]
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800030c: 6039 str r1, [r7, #0]
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uint32_t odr = READ_REG(GPIOx->ODR);
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800030e: 687b ldr r3, [r7, #4]
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8000310: 695b ldr r3, [r3, #20]
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8000312: 60fb str r3, [r7, #12]
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WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
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8000314: 68fa ldr r2, [r7, #12]
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8000316: 683b ldr r3, [r7, #0]
|
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8000318: 4013 ands r3, r2
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800031a: 041a lsls r2, r3, #16
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800031c: 68fb ldr r3, [r7, #12]
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800031e: 43d9 mvns r1, r3
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8000320: 683b ldr r3, [r7, #0]
|
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8000322: 400b ands r3, r1
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|
8000324: 431a orrs r2, r3
|
|
8000326: 687b ldr r3, [r7, #4]
|
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8000328: 619a str r2, [r3, #24]
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}
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800032a: bf00 nop
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800032c: 3714 adds r7, #20
|
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800032e: 46bd mov sp, r7
|
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8000330: f85d 7b04 ldr.w r7, [sp], #4
|
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8000334: 4770 bx lr
|
|
...
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08000338 <GPIO_init>:
|
|
#define BUT_PORT GPIOC
|
|
#define BUT_PIN LL_GPIO_PIN_13
|
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#define CLK_PIN LL_GPIO_PIN_10
|
|
|
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void GPIO_init(void)
|
|
{
|
|
8000338: b580 push {r7, lr}
|
|
800033a: af00 add r7, sp, #0
|
|
// PORT A
|
|
LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA );
|
|
800033c: 2001 movs r0, #1
|
|
800033e: f7ff ff43 bl 80001c8 <LL_AHB2_GRP1_EnableClock>
|
|
// Green LED (user LED) - PA5
|
|
LL_GPIO_SetPinMode( LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT );
|
|
8000342: 2201 movs r2, #1
|
|
8000344: 2120 movs r1, #32
|
|
8000346: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
800034a: f7ff ff55 bl 80001f8 <LL_GPIO_SetPinMode>
|
|
LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL );
|
|
800034e: 2200 movs r2, #0
|
|
8000350: 2120 movs r1, #32
|
|
8000352: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
8000356: f7ff ff8c bl 8000272 <LL_GPIO_SetPinOutputType>
|
|
|
|
// PORT C
|
|
LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC );
|
|
800035a: 2004 movs r0, #4
|
|
800035c: f7ff ff34 bl 80001c8 <LL_AHB2_GRP1_EnableClock>
|
|
// Blue button - PC13
|
|
LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT );
|
|
8000360: 2200 movs r2, #0
|
|
8000362: f44f 5100 mov.w r1, #8192 ; 0x2000
|
|
8000366: 4805 ldr r0, [pc, #20] ; (800037c <GPIO_init+0x44>)
|
|
8000368: f7ff ff46 bl 80001f8 <LL_GPIO_SetPinMode>
|
|
LL_GPIO_SetPinMode( BUT_PORT, CLK_PIN, LL_GPIO_MODE_OUTPUT );
|
|
800036c: 2201 movs r2, #1
|
|
800036e: f44f 6180 mov.w r1, #1024 ; 0x400
|
|
8000372: 4802 ldr r0, [pc, #8] ; (800037c <GPIO_init+0x44>)
|
|
8000374: f7ff ff40 bl 80001f8 <LL_GPIO_SetPinMode>
|
|
}
|
|
8000378: bf00 nop
|
|
800037a: bd80 pop {r7, pc}
|
|
800037c: 48000800 .word 0x48000800
|
|
|
|
08000380 <CLK_TOGGLE>:
|
|
|
|
void CLK_TOGGLE(){
|
|
8000380: b580 push {r7, lr}
|
|
8000382: af00 add r7, sp, #0
|
|
LL_GPIO_TogglePin(BUT_PORT, CLK_PIN);
|
|
8000384: f44f 6180 mov.w r1, #1024 ; 0x400
|
|
8000388: 4802 ldr r0, [pc, #8] ; (8000394 <CLK_TOGGLE+0x14>)
|
|
800038a: f7ff ffbb bl 8000304 <LL_GPIO_TogglePin>
|
|
}
|
|
800038e: bf00 nop
|
|
8000390: bd80 pop {r7, pc}
|
|
8000392: bf00 nop
|
|
8000394: 48000800 .word 0x48000800
|
|
|
|
08000398 <LED_GREEN>:
|
|
|
|
void LED_GREEN( int val )
|
|
{
|
|
8000398: b580 push {r7, lr}
|
|
800039a: b082 sub sp, #8
|
|
800039c: af00 add r7, sp, #0
|
|
800039e: 6078 str r0, [r7, #4]
|
|
if ( val )
|
|
80003a0: 687b ldr r3, [r7, #4]
|
|
80003a2: 2b00 cmp r3, #0
|
|
80003a4: d005 beq.n 80003b2 <LED_GREEN+0x1a>
|
|
LL_GPIO_SetOutputPin( LED_PORT, LED_PIN );
|
|
80003a6: 2120 movs r1, #32
|
|
80003a8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80003ac: f7ff ff8e bl 80002cc <LL_GPIO_SetOutputPin>
|
|
else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
|
|
}
|
|
80003b0: e004 b.n 80003bc <LED_GREEN+0x24>
|
|
else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
|
|
80003b2: 2120 movs r1, #32
|
|
80003b4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80003b8: f7ff ff96 bl 80002e8 <LL_GPIO_ResetOutputPin>
|
|
}
|
|
80003bc: bf00 nop
|
|
80003be: 3708 adds r7, #8
|
|
80003c0: 46bd mov sp, r7
|
|
80003c2: bd80 pop {r7, pc}
|
|
|
|
080003c4 <BLUE_BUTTON>:
|
|
|
|
int BLUE_BUTTON()
|
|
{
|
|
80003c4: b580 push {r7, lr}
|
|
80003c6: af00 add r7, sp, #0
|
|
return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) );
|
|
80003c8: f44f 5100 mov.w r1, #8192 ; 0x2000
|
|
80003cc: 4805 ldr r0, [pc, #20] ; (80003e4 <BLUE_BUTTON+0x20>)
|
|
80003ce: f7ff ff68 bl 80002a2 <LL_GPIO_IsInputPinSet>
|
|
80003d2: 4603 mov r3, r0
|
|
80003d4: 2b00 cmp r3, #0
|
|
80003d6: bf0c ite eq
|
|
80003d8: 2301 moveq r3, #1
|
|
80003da: 2300 movne r3, #0
|
|
80003dc: b2db uxtb r3, r3
|
|
}
|
|
80003de: 4618 mov r0, r3
|
|
80003e0: bd80 pop {r7, pc}
|
|
80003e2: bf00 nop
|
|
80003e4: 48000800 .word 0x48000800
|
|
|
|
080003e8 <LL_RCC_LSE_Enable>:
|
|
* @brief Enable Low Speed External (LSE) crystal.
|
|
* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
|
|
{
|
|
80003e8: b480 push {r7}
|
|
80003ea: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
80003ec: 4b06 ldr r3, [pc, #24] ; (8000408 <LL_RCC_LSE_Enable+0x20>)
|
|
80003ee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
80003f2: 4a05 ldr r2, [pc, #20] ; (8000408 <LL_RCC_LSE_Enable+0x20>)
|
|
80003f4: f043 0301 orr.w r3, r3, #1
|
|
80003f8: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
}
|
|
80003fc: bf00 nop
|
|
80003fe: 46bd mov sp, r7
|
|
8000400: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000404: 4770 bx lr
|
|
8000406: bf00 nop
|
|
8000408: 40021000 .word 0x40021000
|
|
|
|
0800040c <LL_RCC_LSE_SetDriveCapability>:
|
|
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
|
|
* @arg @ref LL_RCC_LSEDRIVE_HIGH
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
|
|
{
|
|
800040c: b480 push {r7}
|
|
800040e: b083 sub sp, #12
|
|
8000410: af00 add r7, sp, #0
|
|
8000412: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
|
|
8000414: 4b07 ldr r3, [pc, #28] ; (8000434 <LL_RCC_LSE_SetDriveCapability+0x28>)
|
|
8000416: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800041a: f023 0218 bic.w r2, r3, #24
|
|
800041e: 4905 ldr r1, [pc, #20] ; (8000434 <LL_RCC_LSE_SetDriveCapability+0x28>)
|
|
8000420: 687b ldr r3, [r7, #4]
|
|
8000422: 4313 orrs r3, r2
|
|
8000424: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
8000428: bf00 nop
|
|
800042a: 370c adds r7, #12
|
|
800042c: 46bd mov sp, r7
|
|
800042e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000432: 4770 bx lr
|
|
8000434: 40021000 .word 0x40021000
|
|
|
|
08000438 <LL_RCC_LSE_IsReady>:
|
|
* @brief Check if LSE oscillator Ready
|
|
* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
|
|
{
|
|
8000438: b480 push {r7}
|
|
800043a: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
|
|
800043c: 4b07 ldr r3, [pc, #28] ; (800045c <LL_RCC_LSE_IsReady+0x24>)
|
|
800043e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8000442: f003 0302 and.w r3, r3, #2
|
|
8000446: 2b02 cmp r3, #2
|
|
8000448: d101 bne.n 800044e <LL_RCC_LSE_IsReady+0x16>
|
|
800044a: 2301 movs r3, #1
|
|
800044c: e000 b.n 8000450 <LL_RCC_LSE_IsReady+0x18>
|
|
800044e: 2300 movs r3, #0
|
|
}
|
|
8000450: 4618 mov r0, r3
|
|
8000452: 46bd mov sp, r7
|
|
8000454: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000458: 4770 bx lr
|
|
800045a: bf00 nop
|
|
800045c: 40021000 .word 0x40021000
|
|
|
|
08000460 <LL_RCC_MSI_Enable>:
|
|
* @brief Enable MSI oscillator
|
|
* @rmtoll CR MSION LL_RCC_MSI_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
|
|
{
|
|
8000460: b480 push {r7}
|
|
8000462: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSION);
|
|
8000464: 4b05 ldr r3, [pc, #20] ; (800047c <LL_RCC_MSI_Enable+0x1c>)
|
|
8000466: 681b ldr r3, [r3, #0]
|
|
8000468: 4a04 ldr r2, [pc, #16] ; (800047c <LL_RCC_MSI_Enable+0x1c>)
|
|
800046a: f043 0301 orr.w r3, r3, #1
|
|
800046e: 6013 str r3, [r2, #0]
|
|
}
|
|
8000470: bf00 nop
|
|
8000472: 46bd mov sp, r7
|
|
8000474: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000478: 4770 bx lr
|
|
800047a: bf00 nop
|
|
800047c: 40021000 .word 0x40021000
|
|
|
|
08000480 <LL_RCC_MSI_IsReady>:
|
|
* @brief Check if MSI oscillator Ready
|
|
* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
|
|
{
|
|
8000480: b480 push {r7}
|
|
8000482: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
|
|
8000484: 4b06 ldr r3, [pc, #24] ; (80004a0 <LL_RCC_MSI_IsReady+0x20>)
|
|
8000486: 681b ldr r3, [r3, #0]
|
|
8000488: f003 0302 and.w r3, r3, #2
|
|
800048c: 2b02 cmp r3, #2
|
|
800048e: d101 bne.n 8000494 <LL_RCC_MSI_IsReady+0x14>
|
|
8000490: 2301 movs r3, #1
|
|
8000492: e000 b.n 8000496 <LL_RCC_MSI_IsReady+0x16>
|
|
8000494: 2300 movs r3, #0
|
|
}
|
|
8000496: 4618 mov r0, r3
|
|
8000498: 46bd mov sp, r7
|
|
800049a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800049e: 4770 bx lr
|
|
80004a0: 40021000 .word 0x40021000
|
|
|
|
080004a4 <LL_RCC_MSI_EnablePLLMode>:
|
|
* ready
|
|
* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
|
|
{
|
|
80004a4: b480 push {r7}
|
|
80004a6: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
|
|
80004a8: 4b05 ldr r3, [pc, #20] ; (80004c0 <LL_RCC_MSI_EnablePLLMode+0x1c>)
|
|
80004aa: 681b ldr r3, [r3, #0]
|
|
80004ac: 4a04 ldr r2, [pc, #16] ; (80004c0 <LL_RCC_MSI_EnablePLLMode+0x1c>)
|
|
80004ae: f043 0304 orr.w r3, r3, #4
|
|
80004b2: 6013 str r3, [r2, #0]
|
|
}
|
|
80004b4: bf00 nop
|
|
80004b6: 46bd mov sp, r7
|
|
80004b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80004bc: 4770 bx lr
|
|
80004be: bf00 nop
|
|
80004c0: 40021000 .word 0x40021000
|
|
|
|
080004c4 <LL_RCC_MSI_EnableRangeSelection>:
|
|
* MSISRANGE
|
|
* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
|
|
{
|
|
80004c4: b480 push {r7}
|
|
80004c6: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
|
|
80004c8: 4b05 ldr r3, [pc, #20] ; (80004e0 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
|
|
80004ca: 681b ldr r3, [r3, #0]
|
|
80004cc: 4a04 ldr r2, [pc, #16] ; (80004e0 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
|
|
80004ce: f043 0308 orr.w r3, r3, #8
|
|
80004d2: 6013 str r3, [r2, #0]
|
|
}
|
|
80004d4: bf00 nop
|
|
80004d6: 46bd mov sp, r7
|
|
80004d8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80004dc: 4770 bx lr
|
|
80004de: bf00 nop
|
|
80004e0: 40021000 .word 0x40021000
|
|
|
|
080004e4 <LL_RCC_MSI_SetRange>:
|
|
* @arg @ref LL_RCC_MSIRANGE_10
|
|
* @arg @ref LL_RCC_MSIRANGE_11
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
|
|
{
|
|
80004e4: b480 push {r7}
|
|
80004e6: b083 sub sp, #12
|
|
80004e8: af00 add r7, sp, #0
|
|
80004ea: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
|
|
80004ec: 4b06 ldr r3, [pc, #24] ; (8000508 <LL_RCC_MSI_SetRange+0x24>)
|
|
80004ee: 681b ldr r3, [r3, #0]
|
|
80004f0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
80004f4: 4904 ldr r1, [pc, #16] ; (8000508 <LL_RCC_MSI_SetRange+0x24>)
|
|
80004f6: 687b ldr r3, [r7, #4]
|
|
80004f8: 4313 orrs r3, r2
|
|
80004fa: 600b str r3, [r1, #0]
|
|
}
|
|
80004fc: bf00 nop
|
|
80004fe: 370c adds r7, #12
|
|
8000500: 46bd mov sp, r7
|
|
8000502: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000506: 4770 bx lr
|
|
8000508: 40021000 .word 0x40021000
|
|
|
|
0800050c <LL_RCC_MSI_SetCalibTrimming>:
|
|
* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
|
|
* @param Value Between Min_Data = 0 and Max_Data = 255
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
|
|
{
|
|
800050c: b480 push {r7}
|
|
800050e: b083 sub sp, #12
|
|
8000510: af00 add r7, sp, #0
|
|
8000512: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
|
|
8000514: 4b07 ldr r3, [pc, #28] ; (8000534 <LL_RCC_MSI_SetCalibTrimming+0x28>)
|
|
8000516: 685b ldr r3, [r3, #4]
|
|
8000518: f423 427f bic.w r2, r3, #65280 ; 0xff00
|
|
800051c: 687b ldr r3, [r7, #4]
|
|
800051e: 021b lsls r3, r3, #8
|
|
8000520: 4904 ldr r1, [pc, #16] ; (8000534 <LL_RCC_MSI_SetCalibTrimming+0x28>)
|
|
8000522: 4313 orrs r3, r2
|
|
8000524: 604b str r3, [r1, #4]
|
|
}
|
|
8000526: bf00 nop
|
|
8000528: 370c adds r7, #12
|
|
800052a: 46bd mov sp, r7
|
|
800052c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000530: 4770 bx lr
|
|
8000532: bf00 nop
|
|
8000534: 40021000 .word 0x40021000
|
|
|
|
08000538 <LL_RCC_SetSysClkSource>:
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
|
|
{
|
|
8000538: b480 push {r7}
|
|
800053a: b083 sub sp, #12
|
|
800053c: af00 add r7, sp, #0
|
|
800053e: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
|
|
8000540: 4b06 ldr r3, [pc, #24] ; (800055c <LL_RCC_SetSysClkSource+0x24>)
|
|
8000542: 689b ldr r3, [r3, #8]
|
|
8000544: f023 0203 bic.w r2, r3, #3
|
|
8000548: 4904 ldr r1, [pc, #16] ; (800055c <LL_RCC_SetSysClkSource+0x24>)
|
|
800054a: 687b ldr r3, [r7, #4]
|
|
800054c: 4313 orrs r3, r2
|
|
800054e: 608b str r3, [r1, #8]
|
|
}
|
|
8000550: bf00 nop
|
|
8000552: 370c adds r7, #12
|
|
8000554: 46bd mov sp, r7
|
|
8000556: f85d 7b04 ldr.w r7, [sp], #4
|
|
800055a: 4770 bx lr
|
|
800055c: 40021000 .word 0x40021000
|
|
|
|
08000560 <LL_RCC_GetSysClkSource>:
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
|
|
{
|
|
8000560: b480 push {r7}
|
|
8000562: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
|
|
8000564: 4b04 ldr r3, [pc, #16] ; (8000578 <LL_RCC_GetSysClkSource+0x18>)
|
|
8000566: 689b ldr r3, [r3, #8]
|
|
8000568: f003 030c and.w r3, r3, #12
|
|
}
|
|
800056c: 4618 mov r0, r3
|
|
800056e: 46bd mov sp, r7
|
|
8000570: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000574: 4770 bx lr
|
|
8000576: bf00 nop
|
|
8000578: 40021000 .word 0x40021000
|
|
|
|
0800057c <LL_RCC_SetAHBPrescaler>:
|
|
* @arg @ref LL_RCC_SYSCLK_DIV_256
|
|
* @arg @ref LL_RCC_SYSCLK_DIV_512
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
|
|
{
|
|
800057c: b480 push {r7}
|
|
800057e: b083 sub sp, #12
|
|
8000580: af00 add r7, sp, #0
|
|
8000582: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
|
|
8000584: 4b06 ldr r3, [pc, #24] ; (80005a0 <LL_RCC_SetAHBPrescaler+0x24>)
|
|
8000586: 689b ldr r3, [r3, #8]
|
|
8000588: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
800058c: 4904 ldr r1, [pc, #16] ; (80005a0 <LL_RCC_SetAHBPrescaler+0x24>)
|
|
800058e: 687b ldr r3, [r7, #4]
|
|
8000590: 4313 orrs r3, r2
|
|
8000592: 608b str r3, [r1, #8]
|
|
}
|
|
8000594: bf00 nop
|
|
8000596: 370c adds r7, #12
|
|
8000598: 46bd mov sp, r7
|
|
800059a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800059e: 4770 bx lr
|
|
80005a0: 40021000 .word 0x40021000
|
|
|
|
080005a4 <LL_RCC_SetAPB1Prescaler>:
|
|
* @arg @ref LL_RCC_APB1_DIV_8
|
|
* @arg @ref LL_RCC_APB1_DIV_16
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
|
|
{
|
|
80005a4: b480 push {r7}
|
|
80005a6: b083 sub sp, #12
|
|
80005a8: af00 add r7, sp, #0
|
|
80005aa: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
|
|
80005ac: 4b06 ldr r3, [pc, #24] ; (80005c8 <LL_RCC_SetAPB1Prescaler+0x24>)
|
|
80005ae: 689b ldr r3, [r3, #8]
|
|
80005b0: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
80005b4: 4904 ldr r1, [pc, #16] ; (80005c8 <LL_RCC_SetAPB1Prescaler+0x24>)
|
|
80005b6: 687b ldr r3, [r7, #4]
|
|
80005b8: 4313 orrs r3, r2
|
|
80005ba: 608b str r3, [r1, #8]
|
|
}
|
|
80005bc: bf00 nop
|
|
80005be: 370c adds r7, #12
|
|
80005c0: 46bd mov sp, r7
|
|
80005c2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80005c6: 4770 bx lr
|
|
80005c8: 40021000 .word 0x40021000
|
|
|
|
080005cc <LL_RCC_SetAPB2Prescaler>:
|
|
* @arg @ref LL_RCC_APB2_DIV_8
|
|
* @arg @ref LL_RCC_APB2_DIV_16
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
|
|
{
|
|
80005cc: b480 push {r7}
|
|
80005ce: b083 sub sp, #12
|
|
80005d0: af00 add r7, sp, #0
|
|
80005d2: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
|
|
80005d4: 4b06 ldr r3, [pc, #24] ; (80005f0 <LL_RCC_SetAPB2Prescaler+0x24>)
|
|
80005d6: 689b ldr r3, [r3, #8]
|
|
80005d8: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
80005dc: 4904 ldr r1, [pc, #16] ; (80005f0 <LL_RCC_SetAPB2Prescaler+0x24>)
|
|
80005de: 687b ldr r3, [r7, #4]
|
|
80005e0: 4313 orrs r3, r2
|
|
80005e2: 608b str r3, [r1, #8]
|
|
}
|
|
80005e4: bf00 nop
|
|
80005e6: 370c adds r7, #12
|
|
80005e8: 46bd mov sp, r7
|
|
80005ea: f85d 7b04 ldr.w r7, [sp], #4
|
|
80005ee: 4770 bx lr
|
|
80005f0: 40021000 .word 0x40021000
|
|
|
|
080005f4 <LL_RCC_SetRTCClockSource>:
|
|
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
|
|
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
|
|
{
|
|
80005f4: b480 push {r7}
|
|
80005f6: b083 sub sp, #12
|
|
80005f8: af00 add r7, sp, #0
|
|
80005fa: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
|
|
80005fc: 4b07 ldr r3, [pc, #28] ; (800061c <LL_RCC_SetRTCClockSource+0x28>)
|
|
80005fe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8000602: f423 7240 bic.w r2, r3, #768 ; 0x300
|
|
8000606: 4905 ldr r1, [pc, #20] ; (800061c <LL_RCC_SetRTCClockSource+0x28>)
|
|
8000608: 687b ldr r3, [r7, #4]
|
|
800060a: 4313 orrs r3, r2
|
|
800060c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
8000610: bf00 nop
|
|
8000612: 370c adds r7, #12
|
|
8000614: 46bd mov sp, r7
|
|
8000616: f85d 7b04 ldr.w r7, [sp], #4
|
|
800061a: 4770 bx lr
|
|
800061c: 40021000 .word 0x40021000
|
|
|
|
08000620 <LL_RCC_EnableRTC>:
|
|
* @brief Enable RTC
|
|
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_EnableRTC(void)
|
|
{
|
|
8000620: b480 push {r7}
|
|
8000622: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
|
|
8000624: 4b06 ldr r3, [pc, #24] ; (8000640 <LL_RCC_EnableRTC+0x20>)
|
|
8000626: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800062a: 4a05 ldr r2, [pc, #20] ; (8000640 <LL_RCC_EnableRTC+0x20>)
|
|
800062c: f443 4300 orr.w r3, r3, #32768 ; 0x8000
|
|
8000630: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
}
|
|
8000634: bf00 nop
|
|
8000636: 46bd mov sp, r7
|
|
8000638: f85d 7b04 ldr.w r7, [sp], #4
|
|
800063c: 4770 bx lr
|
|
800063e: bf00 nop
|
|
8000640: 40021000 .word 0x40021000
|
|
|
|
08000644 <LL_RCC_ReleaseBackupDomainReset>:
|
|
* @brief Release the Backup domain reset
|
|
* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
|
|
{
|
|
8000644: b480 push {r7}
|
|
8000646: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
|
|
8000648: 4b06 ldr r3, [pc, #24] ; (8000664 <LL_RCC_ReleaseBackupDomainReset+0x20>)
|
|
800064a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800064e: 4a05 ldr r2, [pc, #20] ; (8000664 <LL_RCC_ReleaseBackupDomainReset+0x20>)
|
|
8000650: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8000654: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
}
|
|
8000658: bf00 nop
|
|
800065a: 46bd mov sp, r7
|
|
800065c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000660: 4770 bx lr
|
|
8000662: bf00 nop
|
|
8000664: 40021000 .word 0x40021000
|
|
|
|
08000668 <LL_RCC_PLL_Enable>:
|
|
* @brief Enable PLL
|
|
* @rmtoll CR PLLON LL_RCC_PLL_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
|
|
{
|
|
8000668: b480 push {r7}
|
|
800066a: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_PLLON);
|
|
800066c: 4b05 ldr r3, [pc, #20] ; (8000684 <LL_RCC_PLL_Enable+0x1c>)
|
|
800066e: 681b ldr r3, [r3, #0]
|
|
8000670: 4a04 ldr r2, [pc, #16] ; (8000684 <LL_RCC_PLL_Enable+0x1c>)
|
|
8000672: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
8000676: 6013 str r3, [r2, #0]
|
|
}
|
|
8000678: bf00 nop
|
|
800067a: 46bd mov sp, r7
|
|
800067c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000680: 4770 bx lr
|
|
8000682: bf00 nop
|
|
8000684: 40021000 .word 0x40021000
|
|
|
|
08000688 <LL_RCC_PLL_IsReady>:
|
|
* @brief Check if PLL Ready
|
|
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
|
|
{
|
|
8000688: b480 push {r7}
|
|
800068a: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
|
|
800068c: 4b07 ldr r3, [pc, #28] ; (80006ac <LL_RCC_PLL_IsReady+0x24>)
|
|
800068e: 681b ldr r3, [r3, #0]
|
|
8000690: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8000694: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
|
|
8000698: d101 bne.n 800069e <LL_RCC_PLL_IsReady+0x16>
|
|
800069a: 2301 movs r3, #1
|
|
800069c: e000 b.n 80006a0 <LL_RCC_PLL_IsReady+0x18>
|
|
800069e: 2300 movs r3, #0
|
|
}
|
|
80006a0: 4618 mov r0, r3
|
|
80006a2: 46bd mov sp, r7
|
|
80006a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80006a8: 4770 bx lr
|
|
80006aa: bf00 nop
|
|
80006ac: 40021000 .word 0x40021000
|
|
|
|
080006b0 <LL_RCC_PLL_ConfigDomain_SYS>:
|
|
* @arg @ref LL_RCC_PLLR_DIV_6
|
|
* @arg @ref LL_RCC_PLLR_DIV_8
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
|
|
{
|
|
80006b0: b480 push {r7}
|
|
80006b2: b085 sub sp, #20
|
|
80006b4: af00 add r7, sp, #0
|
|
80006b6: 60f8 str r0, [r7, #12]
|
|
80006b8: 60b9 str r1, [r7, #8]
|
|
80006ba: 607a str r2, [r7, #4]
|
|
80006bc: 603b str r3, [r7, #0]
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
|
|
80006be: 4b0a ldr r3, [pc, #40] ; (80006e8 <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
|
|
80006c0: 68da ldr r2, [r3, #12]
|
|
80006c2: 4b0a ldr r3, [pc, #40] ; (80006ec <LL_RCC_PLL_ConfigDomain_SYS+0x3c>)
|
|
80006c4: 4013 ands r3, r2
|
|
80006c6: 68f9 ldr r1, [r7, #12]
|
|
80006c8: 68ba ldr r2, [r7, #8]
|
|
80006ca: 4311 orrs r1, r2
|
|
80006cc: 687a ldr r2, [r7, #4]
|
|
80006ce: 0212 lsls r2, r2, #8
|
|
80006d0: 4311 orrs r1, r2
|
|
80006d2: 683a ldr r2, [r7, #0]
|
|
80006d4: 430a orrs r2, r1
|
|
80006d6: 4904 ldr r1, [pc, #16] ; (80006e8 <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
|
|
80006d8: 4313 orrs r3, r2
|
|
80006da: 60cb str r3, [r1, #12]
|
|
Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
|
|
}
|
|
80006dc: bf00 nop
|
|
80006de: 3714 adds r7, #20
|
|
80006e0: 46bd mov sp, r7
|
|
80006e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80006e6: 4770 bx lr
|
|
80006e8: 40021000 .word 0x40021000
|
|
80006ec: f9ff808c .word 0xf9ff808c
|
|
|
|
080006f0 <LL_RCC_PLL_EnableDomain_SYS>:
|
|
* @brief Enable PLL output mapped on SYSCLK domain
|
|
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
|
|
{
|
|
80006f0: b480 push {r7}
|
|
80006f2: af00 add r7, sp, #0
|
|
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
|
|
80006f4: 4b05 ldr r3, [pc, #20] ; (800070c <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
|
|
80006f6: 68db ldr r3, [r3, #12]
|
|
80006f8: 4a04 ldr r2, [pc, #16] ; (800070c <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
|
|
80006fa: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
80006fe: 60d3 str r3, [r2, #12]
|
|
}
|
|
8000700: bf00 nop
|
|
8000702: 46bd mov sp, r7
|
|
8000704: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000708: 4770 bx lr
|
|
800070a: bf00 nop
|
|
800070c: 40021000 .word 0x40021000
|
|
|
|
08000710 <LL_APB1_GRP1_EnableClock>:
|
|
*
|
|
* (*) value not defined in all devices.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
8000710: b480 push {r7}
|
|
8000712: b085 sub sp, #20
|
|
8000714: af00 add r7, sp, #0
|
|
8000716: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APB1ENR1, Periphs);
|
|
8000718: 4b08 ldr r3, [pc, #32] ; (800073c <LL_APB1_GRP1_EnableClock+0x2c>)
|
|
800071a: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
800071c: 4907 ldr r1, [pc, #28] ; (800073c <LL_APB1_GRP1_EnableClock+0x2c>)
|
|
800071e: 687b ldr r3, [r7, #4]
|
|
8000720: 4313 orrs r3, r2
|
|
8000722: 658b str r3, [r1, #88] ; 0x58
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
|
|
8000724: 4b05 ldr r3, [pc, #20] ; (800073c <LL_APB1_GRP1_EnableClock+0x2c>)
|
|
8000726: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8000728: 687b ldr r3, [r7, #4]
|
|
800072a: 4013 ands r3, r2
|
|
800072c: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
800072e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000730: bf00 nop
|
|
8000732: 3714 adds r7, #20
|
|
8000734: 46bd mov sp, r7
|
|
8000736: f85d 7b04 ldr.w r7, [sp], #4
|
|
800073a: 4770 bx lr
|
|
800073c: 40021000 .word 0x40021000
|
|
|
|
08000740 <LL_FLASH_SetLatency>:
|
|
*
|
|
* (*) value not defined in all devices.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
|
|
{
|
|
8000740: b480 push {r7}
|
|
8000742: b083 sub sp, #12
|
|
8000744: af00 add r7, sp, #0
|
|
8000746: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
|
|
8000748: 4b06 ldr r3, [pc, #24] ; (8000764 <LL_FLASH_SetLatency+0x24>)
|
|
800074a: 681b ldr r3, [r3, #0]
|
|
800074c: f023 0207 bic.w r2, r3, #7
|
|
8000750: 4904 ldr r1, [pc, #16] ; (8000764 <LL_FLASH_SetLatency+0x24>)
|
|
8000752: 687b ldr r3, [r7, #4]
|
|
8000754: 4313 orrs r3, r2
|
|
8000756: 600b str r3, [r1, #0]
|
|
}
|
|
8000758: bf00 nop
|
|
800075a: 370c adds r7, #12
|
|
800075c: 46bd mov sp, r7
|
|
800075e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000762: 4770 bx lr
|
|
8000764: 40022000 .word 0x40022000
|
|
|
|
08000768 <LL_FLASH_GetLatency>:
|
|
* @arg @ref LL_FLASH_LATENCY_15 (*)
|
|
*
|
|
* (*) value not defined in all devices.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
|
|
{
|
|
8000768: b480 push {r7}
|
|
800076a: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
|
|
800076c: 4b04 ldr r3, [pc, #16] ; (8000780 <LL_FLASH_GetLatency+0x18>)
|
|
800076e: 681b ldr r3, [r3, #0]
|
|
8000770: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8000774: 4618 mov r0, r3
|
|
8000776: 46bd mov sp, r7
|
|
8000778: f85d 7b04 ldr.w r7, [sp], #4
|
|
800077c: 4770 bx lr
|
|
800077e: bf00 nop
|
|
8000780: 40022000 .word 0x40022000
|
|
|
|
08000784 <LL_SYSTICK_EnableIT>:
|
|
* @brief Enable SysTick exception request
|
|
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
|
|
{
|
|
8000784: b480 push {r7}
|
|
8000786: af00 add r7, sp, #0
|
|
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
|
8000788: 4b05 ldr r3, [pc, #20] ; (80007a0 <LL_SYSTICK_EnableIT+0x1c>)
|
|
800078a: 681b ldr r3, [r3, #0]
|
|
800078c: 4a04 ldr r2, [pc, #16] ; (80007a0 <LL_SYSTICK_EnableIT+0x1c>)
|
|
800078e: f043 0302 orr.w r3, r3, #2
|
|
8000792: 6013 str r3, [r2, #0]
|
|
}
|
|
8000794: bf00 nop
|
|
8000796: 46bd mov sp, r7
|
|
8000798: f85d 7b04 ldr.w r7, [sp], #4
|
|
800079c: 4770 bx lr
|
|
800079e: bf00 nop
|
|
80007a0: e000e010 .word 0xe000e010
|
|
|
|
080007a4 <LL_LPM_EnableSleep>:
|
|
* @brief Processor uses sleep as its low power mode
|
|
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_LPM_EnableSleep(void)
|
|
{
|
|
80007a4: b480 push {r7}
|
|
80007a6: af00 add r7, sp, #0
|
|
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
80007a8: 4b05 ldr r3, [pc, #20] ; (80007c0 <LL_LPM_EnableSleep+0x1c>)
|
|
80007aa: 691b ldr r3, [r3, #16]
|
|
80007ac: 4a04 ldr r2, [pc, #16] ; (80007c0 <LL_LPM_EnableSleep+0x1c>)
|
|
80007ae: f023 0304 bic.w r3, r3, #4
|
|
80007b2: 6113 str r3, [r2, #16]
|
|
}
|
|
80007b4: bf00 nop
|
|
80007b6: 46bd mov sp, r7
|
|
80007b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80007bc: 4770 bx lr
|
|
80007be: bf00 nop
|
|
80007c0: e000ed00 .word 0xe000ed00
|
|
|
|
080007c4 <LL_PWR_SetRegulVoltageScaling>:
|
|
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
|
|
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
80007c4: b480 push {r7}
|
|
80007c6: b083 sub sp, #12
|
|
80007c8: af00 add r7, sp, #0
|
|
80007ca: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
|
|
80007cc: 4b06 ldr r3, [pc, #24] ; (80007e8 <LL_PWR_SetRegulVoltageScaling+0x24>)
|
|
80007ce: 681b ldr r3, [r3, #0]
|
|
80007d0: f423 62c0 bic.w r2, r3, #1536 ; 0x600
|
|
80007d4: 4904 ldr r1, [pc, #16] ; (80007e8 <LL_PWR_SetRegulVoltageScaling+0x24>)
|
|
80007d6: 687b ldr r3, [r7, #4]
|
|
80007d8: 4313 orrs r3, r2
|
|
80007da: 600b str r3, [r1, #0]
|
|
}
|
|
80007dc: bf00 nop
|
|
80007de: 370c adds r7, #12
|
|
80007e0: 46bd mov sp, r7
|
|
80007e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80007e6: 4770 bx lr
|
|
80007e8: 40007000 .word 0x40007000
|
|
|
|
080007ec <LL_PWR_EnableBkUpAccess>:
|
|
* @brief Enable access to the backup domain
|
|
* @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
|
|
{
|
|
80007ec: b480 push {r7}
|
|
80007ee: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80007f0: 4b05 ldr r3, [pc, #20] ; (8000808 <LL_PWR_EnableBkUpAccess+0x1c>)
|
|
80007f2: 681b ldr r3, [r3, #0]
|
|
80007f4: 4a04 ldr r2, [pc, #16] ; (8000808 <LL_PWR_EnableBkUpAccess+0x1c>)
|
|
80007f6: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
80007fa: 6013 str r3, [r2, #0]
|
|
}
|
|
80007fc: bf00 nop
|
|
80007fe: 46bd mov sp, r7
|
|
8000800: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000804: 4770 bx lr
|
|
8000806: bf00 nop
|
|
8000808: 40007000 .word 0x40007000
|
|
|
|
0800080c <LL_PWR_DisableBkUpAccess>:
|
|
* @brief Disable access to the backup domain
|
|
* @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
|
|
{
|
|
800080c: b480 push {r7}
|
|
800080e: af00 add r7, sp, #0
|
|
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8000810: 4b05 ldr r3, [pc, #20] ; (8000828 <LL_PWR_DisableBkUpAccess+0x1c>)
|
|
8000812: 681b ldr r3, [r3, #0]
|
|
8000814: 4a04 ldr r2, [pc, #16] ; (8000828 <LL_PWR_DisableBkUpAccess+0x1c>)
|
|
8000816: f423 7380 bic.w r3, r3, #256 ; 0x100
|
|
800081a: 6013 str r3, [r2, #0]
|
|
}
|
|
800081c: bf00 nop
|
|
800081e: 46bd mov sp, r7
|
|
8000820: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000824: 4770 bx lr
|
|
8000826: bf00 nop
|
|
8000828: 40007000 .word 0x40007000
|
|
|
|
0800082c <SysTick_Handler>:
|
|
volatile uint32_t msTicks = 0;
|
|
volatile uint8_t expe = 0;
|
|
volatile uint8_t blue_mode = 0;
|
|
|
|
void SysTick_Handler()
|
|
{
|
|
800082c: b580 push {r7, lr}
|
|
800082e: af00 add r7, sp, #0
|
|
if ( BLUE_BUTTON() ){
|
|
8000830: f7ff fdc8 bl 80003c4 <BLUE_BUTTON>
|
|
8000834: 4603 mov r3, r0
|
|
8000836: 2b00 cmp r3, #0
|
|
8000838: d002 beq.n 8000840 <SysTick_Handler+0x14>
|
|
blue_mode = 1 ;
|
|
800083a: 4b15 ldr r3, [pc, #84] ; (8000890 <SysTick_Handler+0x64>)
|
|
800083c: 2201 movs r2, #1
|
|
800083e: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
|
|
8000840: 4b14 ldr r3, [pc, #80] ; (8000894 <SysTick_Handler+0x68>)
|
|
8000842: 681b ldr r3, [r3, #0]
|
|
8000844: 3301 adds r3, #1
|
|
8000846: 4a13 ldr r2, [pc, #76] ; (8000894 <SysTick_Handler+0x68>)
|
|
8000848: 6013 str r3, [r2, #0]
|
|
if (msTicks == 5 * expe){
|
|
800084a: 4b13 ldr r3, [pc, #76] ; (8000898 <SysTick_Handler+0x6c>)
|
|
800084c: 781b ldrb r3, [r3, #0]
|
|
800084e: b2db uxtb r3, r3
|
|
8000850: 461a mov r2, r3
|
|
8000852: 4613 mov r3, r2
|
|
8000854: 009b lsls r3, r3, #2
|
|
8000856: 4413 add r3, r2
|
|
8000858: 461a mov r2, r3
|
|
800085a: 4b0e ldr r3, [pc, #56] ; (8000894 <SysTick_Handler+0x68>)
|
|
800085c: 681b ldr r3, [r3, #0]
|
|
800085e: 429a cmp r2, r3
|
|
8000860: d103 bne.n 800086a <SysTick_Handler+0x3e>
|
|
LED_GREEN(0);
|
|
8000862: 2000 movs r0, #0
|
|
8000864: f7ff fd98 bl 8000398 <LED_GREEN>
|
|
8000868: e009 b.n 800087e <SysTick_Handler+0x52>
|
|
}else if(msTicks >= 200){
|
|
800086a: 4b0a ldr r3, [pc, #40] ; (8000894 <SysTick_Handler+0x68>)
|
|
800086c: 681b ldr r3, [r3, #0]
|
|
800086e: 2bc7 cmp r3, #199 ; 0xc7
|
|
8000870: d905 bls.n 800087e <SysTick_Handler+0x52>
|
|
msTicks = 0;
|
|
8000872: 4b08 ldr r3, [pc, #32] ; (8000894 <SysTick_Handler+0x68>)
|
|
8000874: 2200 movs r2, #0
|
|
8000876: 601a str r2, [r3, #0]
|
|
LED_GREEN(1);
|
|
8000878: 2001 movs r0, #1
|
|
800087a: f7ff fd8d bl 8000398 <LED_GREEN>
|
|
}
|
|
if(expe == 2){
|
|
800087e: 4b06 ldr r3, [pc, #24] ; (8000898 <SysTick_Handler+0x6c>)
|
|
8000880: 781b ldrb r3, [r3, #0]
|
|
8000882: b2db uxtb r3, r3
|
|
8000884: 2b02 cmp r3, #2
|
|
8000886: d101 bne.n 800088c <SysTick_Handler+0x60>
|
|
CLK_TOGGLE();
|
|
8000888: f7ff fd7a bl 8000380 <CLK_TOGGLE>
|
|
}
|
|
}
|
|
800088c: bf00 nop
|
|
800088e: bd80 pop {r7, pc}
|
|
8000890: 2000002d .word 0x2000002d
|
|
8000894: 20000028 .word 0x20000028
|
|
8000898: 2000002c .word 0x2000002c
|
|
|
|
0800089c <main>:
|
|
|
|
|
|
|
|
|
|
int main(void)
|
|
{
|
|
800089c: b580 push {r7, lr}
|
|
800089e: af00 add r7, sp, #0
|
|
|
|
|
|
// config GPIO
|
|
GPIO_init();
|
|
80008a0: f7ff fd4a bl 8000338 <GPIO_init>
|
|
|
|
// if (RCC->BDCR & RCC_BDCR_LSEON) {
|
|
LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
|
|
80008a4: f04f 5080 mov.w r0, #268435456 ; 0x10000000
|
|
80008a8: f7ff ff32 bl 8000710 <LL_APB1_GRP1_EnableClock>
|
|
LL_PWR_EnableBkUpAccess();
|
|
80008ac: f7ff ff9e bl 80007ec <LL_PWR_EnableBkUpAccess>
|
|
|
|
//expe = register RTC
|
|
expe = RTC->BKP0R;
|
|
80008b0: 4b2f ldr r3, [pc, #188] ; (8000970 <main+0xd4>)
|
|
80008b2: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
80008b4: b2da uxtb r2, r3
|
|
80008b6: 4b2f ldr r3, [pc, #188] ; (8000974 <main+0xd8>)
|
|
80008b8: 701a strb r2, [r3, #0]
|
|
if (expe == 0) {
|
|
80008ba: 4b2e ldr r3, [pc, #184] ; (8000974 <main+0xd8>)
|
|
80008bc: 781b ldrb r3, [r3, #0]
|
|
80008be: b2db uxtb r3, r3
|
|
80008c0: 2b00 cmp r3, #0
|
|
80008c2: d10f bne.n 80008e4 <main+0x48>
|
|
SystemClock_Config_24M_LSE();
|
|
80008c4: f000 f85c bl 8000980 <SystemClock_Config_24M_LSE>
|
|
expe = 1;
|
|
80008c8: 4b2a ldr r3, [pc, #168] ; (8000974 <main+0xd8>)
|
|
80008ca: 2201 movs r2, #1
|
|
80008cc: 701a strb r2, [r3, #0]
|
|
LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
|
|
80008ce: f04f 5080 mov.w r0, #268435456 ; 0x10000000
|
|
80008d2: f7ff ff1d bl 8000710 <LL_APB1_GRP1_EnableClock>
|
|
LL_PWR_EnableBkUpAccess();
|
|
80008d6: f7ff ff89 bl 80007ec <LL_PWR_EnableBkUpAccess>
|
|
RTC->BKP0R = expe;
|
|
80008da: 4b26 ldr r3, [pc, #152] ; (8000974 <main+0xd8>)
|
|
80008dc: 781b ldrb r3, [r3, #0]
|
|
80008de: b2da uxtb r2, r3
|
|
80008e0: 4b23 ldr r3, [pc, #140] ; (8000970 <main+0xd4>)
|
|
80008e2: 651a str r2, [r3, #80] ; 0x50
|
|
}
|
|
|
|
if (BLUE_BUTTON()){
|
|
80008e4: f7ff fd6e bl 80003c4 <BLUE_BUTTON>
|
|
80008e8: 4603 mov r3, r0
|
|
80008ea: 2b00 cmp r3, #0
|
|
80008ec: d013 beq.n 8000916 <main+0x7a>
|
|
|
|
expe ++;
|
|
80008ee: 4b21 ldr r3, [pc, #132] ; (8000974 <main+0xd8>)
|
|
80008f0: 781b ldrb r3, [r3, #0]
|
|
80008f2: b2db uxtb r3, r3
|
|
80008f4: 3301 adds r3, #1
|
|
80008f6: b2da uxtb r2, r3
|
|
80008f8: 4b1e ldr r3, [pc, #120] ; (8000974 <main+0xd8>)
|
|
80008fa: 701a strb r2, [r3, #0]
|
|
|
|
if (expe > 2) expe = 1;
|
|
80008fc: 4b1d ldr r3, [pc, #116] ; (8000974 <main+0xd8>)
|
|
80008fe: 781b ldrb r3, [r3, #0]
|
|
8000900: b2db uxtb r3, r3
|
|
8000902: 2b02 cmp r3, #2
|
|
8000904: d902 bls.n 800090c <main+0x70>
|
|
8000906: 4b1b ldr r3, [pc, #108] ; (8000974 <main+0xd8>)
|
|
8000908: 2201 movs r2, #1
|
|
800090a: 701a strb r2, [r3, #0]
|
|
RTC->BKP0R = expe;
|
|
800090c: 4b19 ldr r3, [pc, #100] ; (8000974 <main+0xd8>)
|
|
800090e: 781b ldrb r3, [r3, #0]
|
|
8000910: b2da uxtb r2, r3
|
|
8000912: 4b17 ldr r3, [pc, #92] ; (8000970 <main+0xd4>)
|
|
8000914: 651a str r2, [r3, #80] ; 0x50
|
|
}
|
|
// }else{
|
|
|
|
// }
|
|
LL_PWR_DisableBkUpAccess();
|
|
8000916: f7ff ff79 bl 800080c <LL_PWR_DisableBkUpAccess>
|
|
switch(expe){
|
|
800091a: 4b16 ldr r3, [pc, #88] ; (8000974 <main+0xd8>)
|
|
800091c: 781b ldrb r3, [r3, #0]
|
|
800091e: b2db uxtb r3, r3
|
|
8000920: 2b01 cmp r3, #1
|
|
8000922: d002 beq.n 800092a <main+0x8e>
|
|
8000924: 2b02 cmp r3, #2
|
|
8000926: d003 beq.n 8000930 <main+0x94>
|
|
8000928: e005 b.n 8000936 <main+0x9a>
|
|
case 1:
|
|
/* Configure the system clock */
|
|
SystemClock_Config_80M();
|
|
800092a: f000 f88f bl 8000a4c <SystemClock_Config_80M>
|
|
break;
|
|
800092e: e002 b.n 8000936 <main+0x9a>
|
|
case 2:
|
|
/* Configure the system clock */
|
|
SystemClock_Config_24M_LSE();
|
|
8000930: f000 f826 bl 8000980 <SystemClock_Config_24M_LSE>
|
|
break;
|
|
8000934: bf00 nop
|
|
}
|
|
|
|
|
|
// init systick timer (tick period at 1 ms)
|
|
LL_Init1msTick( SystemCoreClock );
|
|
8000936: 4b10 ldr r3, [pc, #64] ; (8000978 <main+0xdc>)
|
|
8000938: 681b ldr r3, [r3, #0]
|
|
800093a: 4618 mov r0, r3
|
|
800093c: f000 fa66 bl 8000e0c <LL_Init1msTick>
|
|
LL_SYSTICK_EnableIT();
|
|
8000940: f7ff ff20 bl 8000784 <LL_SYSTICK_EnableIT>
|
|
|
|
//Setup Sleep mode
|
|
LL_LPM_EnableSleep();
|
|
8000944: f7ff ff2e bl 80007a4 <LL_LPM_EnableSleep>
|
|
//LL_LPM_EnableSleepOnExit();
|
|
|
|
while (1) {
|
|
if (blue_mode){
|
|
8000948: 4b0c ldr r3, [pc, #48] ; (800097c <main+0xe0>)
|
|
800094a: 781b ldrb r3, [r3, #0]
|
|
800094c: b2db uxtb r3, r3
|
|
800094e: 2b00 cmp r3, #0
|
|
8000950: d0fa beq.n 8000948 <main+0xac>
|
|
switch(expe){
|
|
8000952: 4b08 ldr r3, [pc, #32] ; (8000974 <main+0xd8>)
|
|
8000954: 781b ldrb r3, [r3, #0]
|
|
8000956: b2db uxtb r3, r3
|
|
8000958: 2b01 cmp r3, #1
|
|
800095a: d002 beq.n 8000962 <main+0xc6>
|
|
800095c: 2b02 cmp r3, #2
|
|
800095e: d002 beq.n 8000966 <main+0xca>
|
|
8000960: e004 b.n 800096c <main+0xd0>
|
|
case 1:
|
|
__WFI();
|
|
8000962: bf30 wfi
|
|
break;
|
|
8000964: e002 b.n 800096c <main+0xd0>
|
|
case 2:
|
|
LL_RCC_MSI_EnablePLLMode();
|
|
8000966: f7ff fd9d bl 80004a4 <LL_RCC_MSI_EnablePLLMode>
|
|
break;
|
|
800096a: bf00 nop
|
|
if (blue_mode){
|
|
800096c: e7ec b.n 8000948 <main+0xac>
|
|
800096e: bf00 nop
|
|
8000970: 40002800 .word 0x40002800
|
|
8000974: 2000002c .word 0x2000002c
|
|
8000978: 20000000 .word 0x20000000
|
|
800097c: 2000002d .word 0x2000002d
|
|
|
|
08000980 <SystemClock_Config_24M_LSE>:
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
* 24Mhz + RTC + LSE
|
|
*/
|
|
void SystemClock_Config_24M_LSE(void)
|
|
{
|
|
8000980: b580 push {r7, lr}
|
|
8000982: af00 add r7, sp, #0
|
|
LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
|
|
8000984: f04f 5080 mov.w r0, #268435456 ; 0x10000000
|
|
8000988: f7ff fec2 bl 8000710 <LL_APB1_GRP1_EnableClock>
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
|
|
800098c: 2001 movs r0, #1
|
|
800098e: f7ff fed7 bl 8000740 <LL_FLASH_SetLatency>
|
|
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_1)
|
|
8000992: bf00 nop
|
|
8000994: f7ff fee8 bl 8000768 <LL_FLASH_GetLatency>
|
|
8000998: 4603 mov r3, r0
|
|
800099a: 2b01 cmp r3, #1
|
|
800099c: d1fa bne.n 8000994 <SystemClock_Config_24M_LSE+0x14>
|
|
{
|
|
}
|
|
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
|
|
800099e: f44f 7000 mov.w r0, #512 ; 0x200
|
|
80009a2: f7ff ff0f bl 80007c4 <LL_PWR_SetRegulVoltageScaling>
|
|
LL_RCC_MSI_Enable();
|
|
80009a6: f7ff fd5b bl 8000460 <LL_RCC_MSI_Enable>
|
|
|
|
/* Wait till MSI is ready */
|
|
while(LL_RCC_MSI_IsReady() != 1)
|
|
80009aa: bf00 nop
|
|
80009ac: f7ff fd68 bl 8000480 <LL_RCC_MSI_IsReady>
|
|
80009b0: 4603 mov r3, r0
|
|
80009b2: 2b01 cmp r3, #1
|
|
80009b4: d1fa bne.n 80009ac <SystemClock_Config_24M_LSE+0x2c>
|
|
{
|
|
|
|
}
|
|
|
|
LL_PWR_EnableBkUpAccess();
|
|
80009b6: f7ff ff19 bl 80007ec <LL_PWR_EnableBkUpAccess>
|
|
// LL_RCC_ForceBackupDomainReset();
|
|
LL_RCC_ReleaseBackupDomainReset();
|
|
80009ba: f7ff fe43 bl 8000644 <LL_RCC_ReleaseBackupDomainReset>
|
|
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW);
|
|
80009be: 2000 movs r0, #0
|
|
80009c0: f7ff fd24 bl 800040c <LL_RCC_LSE_SetDriveCapability>
|
|
|
|
LL_RCC_MSI_EnableRangeSelection();
|
|
80009c4: f7ff fd7e bl 80004c4 <LL_RCC_MSI_EnableRangeSelection>
|
|
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
|
|
80009c8: 2060 movs r0, #96 ; 0x60
|
|
80009ca: f7ff fd8b bl 80004e4 <LL_RCC_MSI_SetRange>
|
|
LL_RCC_MSI_SetCalibTrimming(0);
|
|
80009ce: 2000 movs r0, #0
|
|
80009d0: f7ff fd9c bl 800050c <LL_RCC_MSI_SetCalibTrimming>
|
|
// LL_RCC_MSI_EnablePLLMode();
|
|
|
|
LL_RCC_LSE_Enable();
|
|
80009d4: f7ff fd08 bl 80003e8 <LL_RCC_LSE_Enable>
|
|
|
|
/* Wait till LSE is ready */
|
|
while(LL_RCC_LSE_IsReady() != 1)
|
|
80009d8: bf00 nop
|
|
80009da: f7ff fd2d bl 8000438 <LL_RCC_LSE_IsReady>
|
|
80009de: 4603 mov r3, r0
|
|
80009e0: 2b01 cmp r3, #1
|
|
80009e2: d1fa bne.n 80009da <SystemClock_Config_24M_LSE+0x5a>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
|
|
80009e4: f44f 7080 mov.w r0, #256 ; 0x100
|
|
80009e8: f7ff fe04 bl 80005f4 <LL_RCC_SetRTCClockSource>
|
|
LL_RCC_EnableRTC();
|
|
80009ec: f7ff fe18 bl 8000620 <LL_RCC_EnableRTC>
|
|
|
|
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 24, LL_RCC_PLLR_DIV_4);
|
|
80009f0: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
80009f4: 2218 movs r2, #24
|
|
80009f6: 2100 movs r1, #0
|
|
80009f8: 2001 movs r0, #1
|
|
80009fa: f7ff fe59 bl 80006b0 <LL_RCC_PLL_ConfigDomain_SYS>
|
|
LL_RCC_PLL_EnableDomain_SYS();
|
|
80009fe: f7ff fe77 bl 80006f0 <LL_RCC_PLL_EnableDomain_SYS>
|
|
LL_RCC_PLL_Enable();
|
|
8000a02: f7ff fe31 bl 8000668 <LL_RCC_PLL_Enable>
|
|
|
|
/* Wait till PLL is ready */
|
|
while(LL_RCC_PLL_IsReady() != 1)
|
|
8000a06: bf00 nop
|
|
8000a08: f7ff fe3e bl 8000688 <LL_RCC_PLL_IsReady>
|
|
8000a0c: 4603 mov r3, r0
|
|
8000a0e: 2b01 cmp r3, #1
|
|
8000a10: d1fa bne.n 8000a08 <SystemClock_Config_24M_LSE+0x88>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
8000a12: 2003 movs r0, #3
|
|
8000a14: f7ff fd90 bl 8000538 <LL_RCC_SetSysClkSource>
|
|
|
|
/* Wait till System clock is ready */
|
|
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
|
8000a18: bf00 nop
|
|
8000a1a: f7ff fda1 bl 8000560 <LL_RCC_GetSysClkSource>
|
|
8000a1e: 4603 mov r3, r0
|
|
8000a20: 2b0c cmp r3, #12
|
|
8000a22: d1fa bne.n 8000a1a <SystemClock_Config_24M_LSE+0x9a>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
8000a24: 2000 movs r0, #0
|
|
8000a26: f7ff fda9 bl 800057c <LL_RCC_SetAHBPrescaler>
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
|
|
8000a2a: 2000 movs r0, #0
|
|
8000a2c: f7ff fdba bl 80005a4 <LL_RCC_SetAPB1Prescaler>
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
|
8000a30: 2000 movs r0, #0
|
|
8000a32: f7ff fdcb bl 80005cc <LL_RCC_SetAPB2Prescaler>
|
|
LL_SetSystemCoreClock(24000000);
|
|
8000a36: 4804 ldr r0, [pc, #16] ; (8000a48 <SystemClock_Config_24M_LSE+0xc8>)
|
|
8000a38: f000 f9f4 bl 8000e24 <LL_SetSystemCoreClock>
|
|
|
|
/* Update the time base */
|
|
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
|
|
8000a3c: 2000 movs r0, #0
|
|
8000a3e: f000 f8d9 bl 8000bf4 <HAL_InitTick>
|
|
{
|
|
// Error_Handler();
|
|
}
|
|
}
|
|
8000a42: bf00 nop
|
|
8000a44: bd80 pop {r7, pc}
|
|
8000a46: bf00 nop
|
|
8000a48: 016e3600 .word 0x016e3600
|
|
|
|
08000a4c <SystemClock_Config_80M>:
|
|
|
|
|
|
void SystemClock_Config_80M(void)
|
|
{
|
|
8000a4c: b580 push {r7, lr}
|
|
8000a4e: af00 add r7, sp, #0
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
|
|
8000a50: 2004 movs r0, #4
|
|
8000a52: f7ff fe75 bl 8000740 <LL_FLASH_SetLatency>
|
|
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4)
|
|
8000a56: bf00 nop
|
|
8000a58: f7ff fe86 bl 8000768 <LL_FLASH_GetLatency>
|
|
8000a5c: 4603 mov r3, r0
|
|
8000a5e: 2b04 cmp r3, #4
|
|
8000a60: d1fa bne.n 8000a58 <SystemClock_Config_80M+0xc>
|
|
{
|
|
}
|
|
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
|
|
8000a62: f44f 7000 mov.w r0, #512 ; 0x200
|
|
8000a66: f7ff fead bl 80007c4 <LL_PWR_SetRegulVoltageScaling>
|
|
LL_RCC_MSI_Enable();
|
|
8000a6a: f7ff fcf9 bl 8000460 <LL_RCC_MSI_Enable>
|
|
|
|
/* Wait till MSI is ready */
|
|
while(LL_RCC_MSI_IsReady() != 1)
|
|
8000a6e: bf00 nop
|
|
8000a70: f7ff fd06 bl 8000480 <LL_RCC_MSI_IsReady>
|
|
8000a74: 4603 mov r3, r0
|
|
8000a76: 2b01 cmp r3, #1
|
|
8000a78: d1fa bne.n 8000a70 <SystemClock_Config_80M+0x24>
|
|
{
|
|
|
|
}
|
|
LL_RCC_MSI_EnableRangeSelection();
|
|
8000a7a: f7ff fd23 bl 80004c4 <LL_RCC_MSI_EnableRangeSelection>
|
|
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
|
|
8000a7e: 2060 movs r0, #96 ; 0x60
|
|
8000a80: f7ff fd30 bl 80004e4 <LL_RCC_MSI_SetRange>
|
|
LL_RCC_MSI_SetCalibTrimming(0);
|
|
8000a84: 2000 movs r0, #0
|
|
8000a86: f7ff fd41 bl 800050c <LL_RCC_MSI_SetCalibTrimming>
|
|
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);
|
|
8000a8a: 2300 movs r3, #0
|
|
8000a8c: 2228 movs r2, #40 ; 0x28
|
|
8000a8e: 2100 movs r1, #0
|
|
8000a90: 2001 movs r0, #1
|
|
8000a92: f7ff fe0d bl 80006b0 <LL_RCC_PLL_ConfigDomain_SYS>
|
|
LL_RCC_PLL_EnableDomain_SYS();
|
|
8000a96: f7ff fe2b bl 80006f0 <LL_RCC_PLL_EnableDomain_SYS>
|
|
LL_RCC_PLL_Enable();
|
|
8000a9a: f7ff fde5 bl 8000668 <LL_RCC_PLL_Enable>
|
|
|
|
/* Wait till PLL is ready */
|
|
while(LL_RCC_PLL_IsReady() != 1)
|
|
8000a9e: bf00 nop
|
|
8000aa0: f7ff fdf2 bl 8000688 <LL_RCC_PLL_IsReady>
|
|
8000aa4: 4603 mov r3, r0
|
|
8000aa6: 2b01 cmp r3, #1
|
|
8000aa8: d1fa bne.n 8000aa0 <SystemClock_Config_80M+0x54>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
8000aaa: 2003 movs r0, #3
|
|
8000aac: f7ff fd44 bl 8000538 <LL_RCC_SetSysClkSource>
|
|
|
|
/* Wait till System clock is ready */
|
|
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
|
8000ab0: bf00 nop
|
|
8000ab2: f7ff fd55 bl 8000560 <LL_RCC_GetSysClkSource>
|
|
8000ab6: 4603 mov r3, r0
|
|
8000ab8: 2b0c cmp r3, #12
|
|
8000aba: d1fa bne.n 8000ab2 <SystemClock_Config_80M+0x66>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
8000abc: 2000 movs r0, #0
|
|
8000abe: f7ff fd5d bl 800057c <LL_RCC_SetAHBPrescaler>
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
|
|
8000ac2: 2000 movs r0, #0
|
|
8000ac4: f7ff fd6e bl 80005a4 <LL_RCC_SetAPB1Prescaler>
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
|
8000ac8: 2000 movs r0, #0
|
|
8000aca: f7ff fd7f bl 80005cc <LL_RCC_SetAPB2Prescaler>
|
|
LL_SetSystemCoreClock(80000000);
|
|
8000ace: 4804 ldr r0, [pc, #16] ; (8000ae0 <SystemClock_Config_80M+0x94>)
|
|
8000ad0: f000 f9a8 bl 8000e24 <LL_SetSystemCoreClock>
|
|
|
|
/* Update the time base */
|
|
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
|
|
8000ad4: 2000 movs r0, #0
|
|
8000ad6: f000 f88d bl 8000bf4 <HAL_InitTick>
|
|
{
|
|
// Error_Handler();
|
|
}
|
|
}
|
|
8000ada: bf00 nop
|
|
8000adc: bd80 pop {r7, pc}
|
|
8000ade: bf00 nop
|
|
8000ae0: 04c4b400 .word 0x04c4b400
|
|
|
|
08000ae4 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000ae4: b480 push {r7}
|
|
8000ae6: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 1 */
|
|
}
|
|
8000ae8: bf00 nop
|
|
8000aea: 46bd mov sp, r7
|
|
8000aec: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000af0: 4770 bx lr
|
|
|
|
08000af2 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8000af2: b480 push {r7}
|
|
8000af4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8000af6: e7fe b.n 8000af6 <HardFault_Handler+0x4>
|
|
|
|
08000af8 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8000af8: b480 push {r7}
|
|
8000afa: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8000afc: e7fe b.n 8000afc <MemManage_Handler+0x4>
|
|
|
|
08000afe <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8000afe: b480 push {r7}
|
|
8000b00: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8000b02: e7fe b.n 8000b02 <BusFault_Handler+0x4>
|
|
|
|
08000b04 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000b04: b480 push {r7}
|
|
8000b06: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000b08: e7fe b.n 8000b08 <UsageFault_Handler+0x4>
|
|
|
|
08000b0a <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8000b0a: b480 push {r7}
|
|
8000b0c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8000b0e: bf00 nop
|
|
8000b10: 46bd mov sp, r7
|
|
8000b12: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b16: 4770 bx lr
|
|
|
|
08000b18 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000b18: b480 push {r7}
|
|
8000b1a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8000b1c: bf00 nop
|
|
8000b1e: 46bd mov sp, r7
|
|
8000b20: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b24: 4770 bx lr
|
|
|
|
08000b26 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000b26: b480 push {r7}
|
|
8000b28: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8000b2a: bf00 nop
|
|
8000b2c: 46bd mov sp, r7
|
|
8000b2e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b32: 4770 bx lr
|
|
|
|
08000b34 <SystemInit>:
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
8000b34: b480 push {r7}
|
|
8000b36: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
8000b38: 4b17 ldr r3, [pc, #92] ; (8000b98 <SystemInit+0x64>)
|
|
8000b3a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8000b3e: 4a16 ldr r2, [pc, #88] ; (8000b98 <SystemInit+0x64>)
|
|
8000b40: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
|
8000b44: f8c2 3088 str.w r3, [r2, #136] ; 0x88
|
|
#endif
|
|
|
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
|
/* Set MSION bit */
|
|
RCC->CR |= RCC_CR_MSION;
|
|
8000b48: 4b14 ldr r3, [pc, #80] ; (8000b9c <SystemInit+0x68>)
|
|
8000b4a: 681b ldr r3, [r3, #0]
|
|
8000b4c: 4a13 ldr r2, [pc, #76] ; (8000b9c <SystemInit+0x68>)
|
|
8000b4e: f043 0301 orr.w r3, r3, #1
|
|
8000b52: 6013 str r3, [r2, #0]
|
|
|
|
/* Reset CFGR register */
|
|
RCC->CFGR = 0x00000000U;
|
|
8000b54: 4b11 ldr r3, [pc, #68] ; (8000b9c <SystemInit+0x68>)
|
|
8000b56: 2200 movs r2, #0
|
|
8000b58: 609a str r2, [r3, #8]
|
|
|
|
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
|
RCC->CR &= 0xEAF6FFFFU;
|
|
8000b5a: 4b10 ldr r3, [pc, #64] ; (8000b9c <SystemInit+0x68>)
|
|
8000b5c: 681b ldr r3, [r3, #0]
|
|
8000b5e: 4a0f ldr r2, [pc, #60] ; (8000b9c <SystemInit+0x68>)
|
|
8000b60: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
|
|
8000b64: f423 2310 bic.w r3, r3, #589824 ; 0x90000
|
|
8000b68: 6013 str r3, [r2, #0]
|
|
|
|
/* Reset PLLCFGR register */
|
|
RCC->PLLCFGR = 0x00001000U;
|
|
8000b6a: 4b0c ldr r3, [pc, #48] ; (8000b9c <SystemInit+0x68>)
|
|
8000b6c: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
8000b70: 60da str r2, [r3, #12]
|
|
|
|
/* Reset HSEBYP bit */
|
|
RCC->CR &= 0xFFFBFFFFU;
|
|
8000b72: 4b0a ldr r3, [pc, #40] ; (8000b9c <SystemInit+0x68>)
|
|
8000b74: 681b ldr r3, [r3, #0]
|
|
8000b76: 4a09 ldr r2, [pc, #36] ; (8000b9c <SystemInit+0x68>)
|
|
8000b78: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8000b7c: 6013 str r3, [r2, #0]
|
|
|
|
/* Disable all interrupts */
|
|
RCC->CIER = 0x00000000U;
|
|
8000b7e: 4b07 ldr r3, [pc, #28] ; (8000b9c <SystemInit+0x68>)
|
|
8000b80: 2200 movs r2, #0
|
|
8000b82: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
|
#ifdef VECT_TAB_SRAM
|
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#else
|
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
|
8000b84: 4b04 ldr r3, [pc, #16] ; (8000b98 <SystemInit+0x64>)
|
|
8000b86: f04f 6200 mov.w r2, #134217728 ; 0x8000000
|
|
8000b8a: 609a str r2, [r3, #8]
|
|
#endif
|
|
}
|
|
8000b8c: bf00 nop
|
|
8000b8e: 46bd mov sp, r7
|
|
8000b90: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b94: 4770 bx lr
|
|
8000b96: bf00 nop
|
|
8000b98: e000ed00 .word 0xe000ed00
|
|
8000b9c: 40021000 .word 0x40021000
|
|
|
|
08000ba0 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8000ba0: f8df d034 ldr.w sp, [pc, #52] ; 8000bd8 <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8000ba4: f7ff ffc6 bl 8000b34 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
movs r1, #0
|
|
8000ba8: 2100 movs r1, #0
|
|
b LoopCopyDataInit
|
|
8000baa: e003 b.n 8000bb4 <LoopCopyDataInit>
|
|
|
|
08000bac <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r3, =_sidata
|
|
8000bac: 4b0b ldr r3, [pc, #44] ; (8000bdc <LoopForever+0x6>)
|
|
ldr r3, [r3, r1]
|
|
8000bae: 585b ldr r3, [r3, r1]
|
|
str r3, [r0, r1]
|
|
8000bb0: 5043 str r3, [r0, r1]
|
|
adds r1, r1, #4
|
|
8000bb2: 3104 adds r1, #4
|
|
|
|
08000bb4 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
ldr r0, =_sdata
|
|
8000bb4: 480a ldr r0, [pc, #40] ; (8000be0 <LoopForever+0xa>)
|
|
ldr r3, =_edata
|
|
8000bb6: 4b0b ldr r3, [pc, #44] ; (8000be4 <LoopForever+0xe>)
|
|
adds r2, r0, r1
|
|
8000bb8: 1842 adds r2, r0, r1
|
|
cmp r2, r3
|
|
8000bba: 429a cmp r2, r3
|
|
bcc CopyDataInit
|
|
8000bbc: d3f6 bcc.n 8000bac <CopyDataInit>
|
|
ldr r2, =_sbss
|
|
8000bbe: 4a0a ldr r2, [pc, #40] ; (8000be8 <LoopForever+0x12>)
|
|
b LoopFillZerobss
|
|
8000bc0: e002 b.n 8000bc8 <LoopFillZerobss>
|
|
|
|
08000bc2 <FillZerobss>:
|
|
/* Zero fill the bss segment. */
|
|
FillZerobss:
|
|
movs r3, #0
|
|
8000bc2: 2300 movs r3, #0
|
|
str r3, [r2], #4
|
|
8000bc4: f842 3b04 str.w r3, [r2], #4
|
|
|
|
08000bc8 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
ldr r3, = _ebss
|
|
8000bc8: 4b08 ldr r3, [pc, #32] ; (8000bec <LoopForever+0x16>)
|
|
cmp r2, r3
|
|
8000bca: 429a cmp r2, r3
|
|
bcc FillZerobss
|
|
8000bcc: d3f9 bcc.n 8000bc2 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8000bce: f000 f939 bl 8000e44 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8000bd2: f7ff fe63 bl 800089c <main>
|
|
|
|
08000bd6 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
8000bd6: e7fe b.n 8000bd6 <LoopForever>
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8000bd8: 20018000 .word 0x20018000
|
|
ldr r3, =_sidata
|
|
8000bdc: 08000eac .word 0x08000eac
|
|
ldr r0, =_sdata
|
|
8000be0: 20000000 .word 0x20000000
|
|
ldr r3, =_edata
|
|
8000be4: 2000000c .word 0x2000000c
|
|
ldr r2, =_sbss
|
|
8000be8: 2000000c .word 0x2000000c
|
|
ldr r3, = _ebss
|
|
8000bec: 20000030 .word 0x20000030
|
|
|
|
08000bf0 <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8000bf0: e7fe b.n 8000bf0 <ADC1_2_IRQHandler>
|
|
...
|
|
|
|
08000bf4 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8000bf4: b580 push {r7, lr}
|
|
8000bf6: b084 sub sp, #16
|
|
8000bf8: af00 add r7, sp, #0
|
|
8000bfa: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8000bfc: 2300 movs r3, #0
|
|
8000bfe: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
8000c00: 4b17 ldr r3, [pc, #92] ; (8000c60 <HAL_InitTick+0x6c>)
|
|
8000c02: 781b ldrb r3, [r3, #0]
|
|
8000c04: 2b00 cmp r3, #0
|
|
8000c06: d023 beq.n 8000c50 <HAL_InitTick+0x5c>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
|
|
8000c08: 4b16 ldr r3, [pc, #88] ; (8000c64 <HAL_InitTick+0x70>)
|
|
8000c0a: 681a ldr r2, [r3, #0]
|
|
8000c0c: 4b14 ldr r3, [pc, #80] ; (8000c60 <HAL_InitTick+0x6c>)
|
|
8000c0e: 781b ldrb r3, [r3, #0]
|
|
8000c10: 4619 mov r1, r3
|
|
8000c12: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
8000c16: fbb3 f3f1 udiv r3, r3, r1
|
|
8000c1a: fbb2 f3f3 udiv r3, r2, r3
|
|
8000c1e: 4618 mov r0, r3
|
|
8000c20: f000 f8ce bl 8000dc0 <HAL_SYSTICK_Config>
|
|
8000c24: 4603 mov r3, r0
|
|
8000c26: 2b00 cmp r3, #0
|
|
8000c28: d10f bne.n 8000c4a <HAL_InitTick+0x56>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8000c2a: 687b ldr r3, [r7, #4]
|
|
8000c2c: 2b0f cmp r3, #15
|
|
8000c2e: d809 bhi.n 8000c44 <HAL_InitTick+0x50>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8000c30: 2200 movs r2, #0
|
|
8000c32: 6879 ldr r1, [r7, #4]
|
|
8000c34: f04f 30ff mov.w r0, #4294967295
|
|
8000c38: f000 f8a6 bl 8000d88 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8000c3c: 4a0a ldr r2, [pc, #40] ; (8000c68 <HAL_InitTick+0x74>)
|
|
8000c3e: 687b ldr r3, [r7, #4]
|
|
8000c40: 6013 str r3, [r2, #0]
|
|
8000c42: e007 b.n 8000c54 <HAL_InitTick+0x60>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000c44: 2301 movs r3, #1
|
|
8000c46: 73fb strb r3, [r7, #15]
|
|
8000c48: e004 b.n 8000c54 <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000c4a: 2301 movs r3, #1
|
|
8000c4c: 73fb strb r3, [r7, #15]
|
|
8000c4e: e001 b.n 8000c54 <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000c50: 2301 movs r3, #1
|
|
8000c52: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8000c54: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8000c56: 4618 mov r0, r3
|
|
8000c58: 3710 adds r7, #16
|
|
8000c5a: 46bd mov sp, r7
|
|
8000c5c: bd80 pop {r7, pc}
|
|
8000c5e: bf00 nop
|
|
8000c60: 20000008 .word 0x20000008
|
|
8000c64: 20000000 .word 0x20000000
|
|
8000c68: 20000004 .word 0x20000004
|
|
|
|
08000c6c <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8000c6c: b480 push {r7}
|
|
8000c6e: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8000c70: 4b04 ldr r3, [pc, #16] ; (8000c84 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8000c72: 68db ldr r3, [r3, #12]
|
|
8000c74: 0a1b lsrs r3, r3, #8
|
|
8000c76: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8000c7a: 4618 mov r0, r3
|
|
8000c7c: 46bd mov sp, r7
|
|
8000c7e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000c82: 4770 bx lr
|
|
8000c84: e000ed00 .word 0xe000ed00
|
|
|
|
08000c88 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8000c88: b480 push {r7}
|
|
8000c8a: b083 sub sp, #12
|
|
8000c8c: af00 add r7, sp, #0
|
|
8000c8e: 4603 mov r3, r0
|
|
8000c90: 6039 str r1, [r7, #0]
|
|
8000c92: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8000c94: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000c98: 2b00 cmp r3, #0
|
|
8000c9a: db0a blt.n 8000cb2 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8000c9c: 683b ldr r3, [r7, #0]
|
|
8000c9e: b2da uxtb r2, r3
|
|
8000ca0: 490c ldr r1, [pc, #48] ; (8000cd4 <__NVIC_SetPriority+0x4c>)
|
|
8000ca2: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000ca6: 0112 lsls r2, r2, #4
|
|
8000ca8: b2d2 uxtb r2, r2
|
|
8000caa: 440b add r3, r1
|
|
8000cac: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8000cb0: e00a b.n 8000cc8 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8000cb2: 683b ldr r3, [r7, #0]
|
|
8000cb4: b2da uxtb r2, r3
|
|
8000cb6: 4908 ldr r1, [pc, #32] ; (8000cd8 <__NVIC_SetPriority+0x50>)
|
|
8000cb8: 79fb ldrb r3, [r7, #7]
|
|
8000cba: f003 030f and.w r3, r3, #15
|
|
8000cbe: 3b04 subs r3, #4
|
|
8000cc0: 0112 lsls r2, r2, #4
|
|
8000cc2: b2d2 uxtb r2, r2
|
|
8000cc4: 440b add r3, r1
|
|
8000cc6: 761a strb r2, [r3, #24]
|
|
}
|
|
8000cc8: bf00 nop
|
|
8000cca: 370c adds r7, #12
|
|
8000ccc: 46bd mov sp, r7
|
|
8000cce: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000cd2: 4770 bx lr
|
|
8000cd4: e000e100 .word 0xe000e100
|
|
8000cd8: e000ed00 .word 0xe000ed00
|
|
|
|
08000cdc <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000cdc: b480 push {r7}
|
|
8000cde: b089 sub sp, #36 ; 0x24
|
|
8000ce0: af00 add r7, sp, #0
|
|
8000ce2: 60f8 str r0, [r7, #12]
|
|
8000ce4: 60b9 str r1, [r7, #8]
|
|
8000ce6: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000ce8: 68fb ldr r3, [r7, #12]
|
|
8000cea: f003 0307 and.w r3, r3, #7
|
|
8000cee: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8000cf0: 69fb ldr r3, [r7, #28]
|
|
8000cf2: f1c3 0307 rsb r3, r3, #7
|
|
8000cf6: 2b04 cmp r3, #4
|
|
8000cf8: bf28 it cs
|
|
8000cfa: 2304 movcs r3, #4
|
|
8000cfc: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8000cfe: 69fb ldr r3, [r7, #28]
|
|
8000d00: 3304 adds r3, #4
|
|
8000d02: 2b06 cmp r3, #6
|
|
8000d04: d902 bls.n 8000d0c <NVIC_EncodePriority+0x30>
|
|
8000d06: 69fb ldr r3, [r7, #28]
|
|
8000d08: 3b03 subs r3, #3
|
|
8000d0a: e000 b.n 8000d0e <NVIC_EncodePriority+0x32>
|
|
8000d0c: 2300 movs r3, #0
|
|
8000d0e: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8000d10: f04f 32ff mov.w r2, #4294967295
|
|
8000d14: 69bb ldr r3, [r7, #24]
|
|
8000d16: fa02 f303 lsl.w r3, r2, r3
|
|
8000d1a: 43da mvns r2, r3
|
|
8000d1c: 68bb ldr r3, [r7, #8]
|
|
8000d1e: 401a ands r2, r3
|
|
8000d20: 697b ldr r3, [r7, #20]
|
|
8000d22: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8000d24: f04f 31ff mov.w r1, #4294967295
|
|
8000d28: 697b ldr r3, [r7, #20]
|
|
8000d2a: fa01 f303 lsl.w r3, r1, r3
|
|
8000d2e: 43d9 mvns r1, r3
|
|
8000d30: 687b ldr r3, [r7, #4]
|
|
8000d32: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8000d34: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8000d36: 4618 mov r0, r3
|
|
8000d38: 3724 adds r7, #36 ; 0x24
|
|
8000d3a: 46bd mov sp, r7
|
|
8000d3c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000d40: 4770 bx lr
|
|
...
|
|
|
|
08000d44 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8000d44: b580 push {r7, lr}
|
|
8000d46: b082 sub sp, #8
|
|
8000d48: af00 add r7, sp, #0
|
|
8000d4a: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8000d4c: 687b ldr r3, [r7, #4]
|
|
8000d4e: 3b01 subs r3, #1
|
|
8000d50: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
8000d54: d301 bcc.n 8000d5a <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8000d56: 2301 movs r3, #1
|
|
8000d58: e00f b.n 8000d7a <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8000d5a: 4a0a ldr r2, [pc, #40] ; (8000d84 <SysTick_Config+0x40>)
|
|
8000d5c: 687b ldr r3, [r7, #4]
|
|
8000d5e: 3b01 subs r3, #1
|
|
8000d60: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8000d62: 210f movs r1, #15
|
|
8000d64: f04f 30ff mov.w r0, #4294967295
|
|
8000d68: f7ff ff8e bl 8000c88 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8000d6c: 4b05 ldr r3, [pc, #20] ; (8000d84 <SysTick_Config+0x40>)
|
|
8000d6e: 2200 movs r2, #0
|
|
8000d70: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8000d72: 4b04 ldr r3, [pc, #16] ; (8000d84 <SysTick_Config+0x40>)
|
|
8000d74: 2207 movs r2, #7
|
|
8000d76: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8000d78: 2300 movs r3, #0
|
|
}
|
|
8000d7a: 4618 mov r0, r3
|
|
8000d7c: 3708 adds r7, #8
|
|
8000d7e: 46bd mov sp, r7
|
|
8000d80: bd80 pop {r7, pc}
|
|
8000d82: bf00 nop
|
|
8000d84: e000e010 .word 0xe000e010
|
|
|
|
08000d88 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000d88: b580 push {r7, lr}
|
|
8000d8a: b086 sub sp, #24
|
|
8000d8c: af00 add r7, sp, #0
|
|
8000d8e: 4603 mov r3, r0
|
|
8000d90: 60b9 str r1, [r7, #8]
|
|
8000d92: 607a str r2, [r7, #4]
|
|
8000d94: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8000d96: 2300 movs r3, #0
|
|
8000d98: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8000d9a: f7ff ff67 bl 8000c6c <__NVIC_GetPriorityGrouping>
|
|
8000d9e: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8000da0: 687a ldr r2, [r7, #4]
|
|
8000da2: 68b9 ldr r1, [r7, #8]
|
|
8000da4: 6978 ldr r0, [r7, #20]
|
|
8000da6: f7ff ff99 bl 8000cdc <NVIC_EncodePriority>
|
|
8000daa: 4602 mov r2, r0
|
|
8000dac: f997 300f ldrsb.w r3, [r7, #15]
|
|
8000db0: 4611 mov r1, r2
|
|
8000db2: 4618 mov r0, r3
|
|
8000db4: f7ff ff68 bl 8000c88 <__NVIC_SetPriority>
|
|
}
|
|
8000db8: bf00 nop
|
|
8000dba: 3718 adds r7, #24
|
|
8000dbc: 46bd mov sp, r7
|
|
8000dbe: bd80 pop {r7, pc}
|
|
|
|
08000dc0 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8000dc0: b580 push {r7, lr}
|
|
8000dc2: b082 sub sp, #8
|
|
8000dc4: af00 add r7, sp, #0
|
|
8000dc6: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8000dc8: 6878 ldr r0, [r7, #4]
|
|
8000dca: f7ff ffbb bl 8000d44 <SysTick_Config>
|
|
8000dce: 4603 mov r3, r0
|
|
}
|
|
8000dd0: 4618 mov r0, r3
|
|
8000dd2: 3708 adds r7, #8
|
|
8000dd4: 46bd mov sp, r7
|
|
8000dd6: bd80 pop {r7, pc}
|
|
|
|
08000dd8 <LL_InitTick>:
|
|
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
|
* @param Ticks Number of ticks
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
|
{
|
|
8000dd8: b480 push {r7}
|
|
8000dda: b083 sub sp, #12
|
|
8000ddc: af00 add r7, sp, #0
|
|
8000dde: 6078 str r0, [r7, #4]
|
|
8000de0: 6039 str r1, [r7, #0]
|
|
/* Configure the SysTick to have interrupt in 1ms time base */
|
|
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
|
8000de2: 687a ldr r2, [r7, #4]
|
|
8000de4: 683b ldr r3, [r7, #0]
|
|
8000de6: fbb2 f3f3 udiv r3, r2, r3
|
|
8000dea: 4a07 ldr r2, [pc, #28] ; (8000e08 <LL_InitTick+0x30>)
|
|
8000dec: 3b01 subs r3, #1
|
|
8000dee: 6053 str r3, [r2, #4]
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8000df0: 4b05 ldr r3, [pc, #20] ; (8000e08 <LL_InitTick+0x30>)
|
|
8000df2: 2200 movs r2, #0
|
|
8000df4: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8000df6: 4b04 ldr r3, [pc, #16] ; (8000e08 <LL_InitTick+0x30>)
|
|
8000df8: 2205 movs r2, #5
|
|
8000dfa: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
|
}
|
|
8000dfc: bf00 nop
|
|
8000dfe: 370c adds r7, #12
|
|
8000e00: 46bd mov sp, r7
|
|
8000e02: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000e06: 4770 bx lr
|
|
8000e08: e000e010 .word 0xe000e010
|
|
|
|
08000e0c <LL_Init1msTick>:
|
|
* @param HCLKFrequency HCLK frequency in Hz
|
|
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
|
|
* @retval None
|
|
*/
|
|
void LL_Init1msTick(uint32_t HCLKFrequency)
|
|
{
|
|
8000e0c: b580 push {r7, lr}
|
|
8000e0e: b082 sub sp, #8
|
|
8000e10: af00 add r7, sp, #0
|
|
8000e12: 6078 str r0, [r7, #4]
|
|
/* Use frequency provided in argument */
|
|
LL_InitTick(HCLKFrequency, 100U);
|
|
8000e14: 2164 movs r1, #100 ; 0x64
|
|
8000e16: 6878 ldr r0, [r7, #4]
|
|
8000e18: f7ff ffde bl 8000dd8 <LL_InitTick>
|
|
}
|
|
8000e1c: bf00 nop
|
|
8000e1e: 3708 adds r7, #8
|
|
8000e20: 46bd mov sp, r7
|
|
8000e22: bd80 pop {r7, pc}
|
|
|
|
08000e24 <LL_SetSystemCoreClock>:
|
|
* @note Variable can be calculated also through SystemCoreClockUpdate function.
|
|
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
|
* @retval None
|
|
*/
|
|
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
|
|
{
|
|
8000e24: b480 push {r7}
|
|
8000e26: b083 sub sp, #12
|
|
8000e28: af00 add r7, sp, #0
|
|
8000e2a: 6078 str r0, [r7, #4]
|
|
/* HCLK clock frequency */
|
|
SystemCoreClock = HCLKFrequency;
|
|
8000e2c: 4a04 ldr r2, [pc, #16] ; (8000e40 <LL_SetSystemCoreClock+0x1c>)
|
|
8000e2e: 687b ldr r3, [r7, #4]
|
|
8000e30: 6013 str r3, [r2, #0]
|
|
}
|
|
8000e32: bf00 nop
|
|
8000e34: 370c adds r7, #12
|
|
8000e36: 46bd mov sp, r7
|
|
8000e38: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000e3c: 4770 bx lr
|
|
8000e3e: bf00 nop
|
|
8000e40: 20000000 .word 0x20000000
|
|
|
|
08000e44 <__libc_init_array>:
|
|
8000e44: b570 push {r4, r5, r6, lr}
|
|
8000e46: 4e0d ldr r6, [pc, #52] ; (8000e7c <__libc_init_array+0x38>)
|
|
8000e48: 4c0d ldr r4, [pc, #52] ; (8000e80 <__libc_init_array+0x3c>)
|
|
8000e4a: 1ba4 subs r4, r4, r6
|
|
8000e4c: 10a4 asrs r4, r4, #2
|
|
8000e4e: 2500 movs r5, #0
|
|
8000e50: 42a5 cmp r5, r4
|
|
8000e52: d109 bne.n 8000e68 <__libc_init_array+0x24>
|
|
8000e54: 4e0b ldr r6, [pc, #44] ; (8000e84 <__libc_init_array+0x40>)
|
|
8000e56: 4c0c ldr r4, [pc, #48] ; (8000e88 <__libc_init_array+0x44>)
|
|
8000e58: f000 f818 bl 8000e8c <_init>
|
|
8000e5c: 1ba4 subs r4, r4, r6
|
|
8000e5e: 10a4 asrs r4, r4, #2
|
|
8000e60: 2500 movs r5, #0
|
|
8000e62: 42a5 cmp r5, r4
|
|
8000e64: d105 bne.n 8000e72 <__libc_init_array+0x2e>
|
|
8000e66: bd70 pop {r4, r5, r6, pc}
|
|
8000e68: f856 3025 ldr.w r3, [r6, r5, lsl #2]
|
|
8000e6c: 4798 blx r3
|
|
8000e6e: 3501 adds r5, #1
|
|
8000e70: e7ee b.n 8000e50 <__libc_init_array+0xc>
|
|
8000e72: f856 3025 ldr.w r3, [r6, r5, lsl #2]
|
|
8000e76: 4798 blx r3
|
|
8000e78: 3501 adds r5, #1
|
|
8000e7a: e7f2 b.n 8000e62 <__libc_init_array+0x1e>
|
|
8000e7c: 08000ea4 .word 0x08000ea4
|
|
8000e80: 08000ea4 .word 0x08000ea4
|
|
8000e84: 08000ea4 .word 0x08000ea4
|
|
8000e88: 08000ea8 .word 0x08000ea8
|
|
|
|
08000e8c <_init>:
|
|
8000e8c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8000e8e: bf00 nop
|
|
8000e90: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8000e92: bc08 pop {r3}
|
|
8000e94: 469e mov lr, r3
|
|
8000e96: 4770 bx lr
|
|
|
|
08000e98 <_fini>:
|
|
8000e98: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8000e9a: bf00 nop
|
|
8000e9c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8000e9e: bc08 pop {r3}
|
|
8000ea0: 469e mov lr, r3
|
|
8000ea2: 4770 bx lr
|