1555 lines
53 KiB
Text
1555 lines
53 KiB
Text
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L476_ats_blink-master.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00000804 08000188 08000188 00010188 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000040 0800098c 0800098c 0001098c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 080009cc 080009cc 00020004 2**0
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CONTENTS
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4 .ARM 00000000 080009cc 080009cc 00020004 2**0
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CONTENTS
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5 .preinit_array 00000000 080009cc 080009cc 00020004 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 080009cc 080009cc 000109cc 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 080009d0 080009d0 000109d0 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 00000004 20000000 080009d4 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000024 20000004 080009d8 00020004 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000028 080009d8 00020028 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 00020004 2**0
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CONTENTS, READONLY
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12 .debug_info 00002106 00000000 00000000 00020034 2**0
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CONTENTS, READONLY, DEBUGGING
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13 .debug_abbrev 00000771 00000000 00000000 0002213a 2**0
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CONTENTS, READONLY, DEBUGGING
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14 .debug_aranges 000002d8 00000000 00000000 000228b0 2**3
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CONTENTS, READONLY, DEBUGGING
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15 .debug_ranges 00000280 00000000 00000000 00022b88 2**3
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CONTENTS, READONLY, DEBUGGING
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16 .debug_macro 0001e120 00000000 00000000 00022e08 2**0
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CONTENTS, READONLY, DEBUGGING
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17 .debug_line 0000201e 00000000 00000000 00040f28 2**0
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CONTENTS, READONLY, DEBUGGING
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18 .debug_str 000a94ae 00000000 00000000 00042f46 2**0
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CONTENTS, READONLY, DEBUGGING
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19 .comment 0000007b 00000000 00000000 000ec3f4 2**0
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CONTENTS, READONLY
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20 .debug_frame 00000a00 00000000 00000000 000ec470 2**2
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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08000188 <__do_global_dtors_aux>:
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8000188: b510 push {r4, lr}
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800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
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800018c: 7823 ldrb r3, [r4, #0]
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800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
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8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
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8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
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8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
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8000196: f3af 8000 nop.w
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800019a: 2301 movs r3, #1
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800019c: 7023 strb r3, [r4, #0]
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800019e: bd10 pop {r4, pc}
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80001a0: 20000004 .word 0x20000004
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80001a4: 00000000 .word 0x00000000
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80001a8: 08000974 .word 0x08000974
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080001ac <frame_dummy>:
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80001ac: b508 push {r3, lr}
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80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
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80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
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80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
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80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
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80001b6: f3af 8000 nop.w
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80001ba: bd08 pop {r3, pc}
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80001bc: 00000000 .word 0x00000000
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80001c0: 20000008 .word 0x20000008
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80001c4: 08000974 .word 0x08000974
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080001c8 <LL_AHB2_GRP1_EnableClock>:
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
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{
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80001c8: b480 push {r7}
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80001ca: b085 sub sp, #20
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80001cc: af00 add r7, sp, #0
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80001ce: 6078 str r0, [r7, #4]
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHB2ENR, Periphs);
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80001d0: 4b08 ldr r3, [pc, #32] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
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80001d2: 6cda ldr r2, [r3, #76] ; 0x4c
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80001d4: 4907 ldr r1, [pc, #28] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
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80001d6: 687b ldr r3, [r7, #4]
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80001d8: 4313 orrs r3, r2
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80001da: 64cb str r3, [r1, #76] ; 0x4c
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
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80001dc: 4b05 ldr r3, [pc, #20] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
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80001de: 6cda ldr r2, [r3, #76] ; 0x4c
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80001e0: 687b ldr r3, [r7, #4]
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80001e2: 4013 ands r3, r2
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80001e4: 60fb str r3, [r7, #12]
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(void)tmpreg;
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80001e6: 68fb ldr r3, [r7, #12]
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}
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80001e8: bf00 nop
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80001ea: 3714 adds r7, #20
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80001ec: 46bd mov sp, r7
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80001ee: f85d 7b04 ldr.w r7, [sp], #4
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80001f2: 4770 bx lr
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80001f4: 40021000 .word 0x40021000
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080001f8 <LL_GPIO_SetPinMode>:
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* @arg @ref LL_GPIO_MODE_ALTERNATE
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* @arg @ref LL_GPIO_MODE_ANALOG
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
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{
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80001f8: b480 push {r7}
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80001fa: b08b sub sp, #44 ; 0x2c
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80001fc: af00 add r7, sp, #0
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80001fe: 60f8 str r0, [r7, #12]
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8000200: 60b9 str r1, [r7, #8]
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8000202: 607a str r2, [r7, #4]
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MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
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8000204: 68fb ldr r3, [r7, #12]
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8000206: 681a ldr r2, [r3, #0]
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8000208: 68bb ldr r3, [r7, #8]
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800020a: 617b str r3, [r7, #20]
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uint32_t result;
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
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__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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800020c: 697b ldr r3, [r7, #20]
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800020e: fa93 f3a3 rbit r3, r3
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8000212: 613b str r3, [r7, #16]
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result |= value & 1U;
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s--;
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}
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result <<= s; /* shift when v's highest bits are zero */
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#endif
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return result;
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8000214: 693b ldr r3, [r7, #16]
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8000216: 61bb str r3, [r7, #24]
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optimisations using the logic "value was passed to __builtin_clz, so it
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is non-zero".
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ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
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single CLZ instruction.
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*/
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if (value == 0U)
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8000218: 69bb ldr r3, [r7, #24]
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800021a: 2b00 cmp r3, #0
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800021c: d101 bne.n 8000222 <LL_GPIO_SetPinMode+0x2a>
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{
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return 32U;
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800021e: 2320 movs r3, #32
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8000220: e003 b.n 800022a <LL_GPIO_SetPinMode+0x32>
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}
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return __builtin_clz(value);
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8000222: 69bb ldr r3, [r7, #24]
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8000224: fab3 f383 clz r3, r3
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8000228: b2db uxtb r3, r3
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800022a: 005b lsls r3, r3, #1
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800022c: 2103 movs r1, #3
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800022e: fa01 f303 lsl.w r3, r1, r3
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8000232: 43db mvns r3, r3
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8000234: 401a ands r2, r3
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8000236: 68bb ldr r3, [r7, #8]
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8000238: 623b str r3, [r7, #32]
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__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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800023a: 6a3b ldr r3, [r7, #32]
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800023c: fa93 f3a3 rbit r3, r3
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8000240: 61fb str r3, [r7, #28]
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return result;
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8000242: 69fb ldr r3, [r7, #28]
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8000244: 627b str r3, [r7, #36] ; 0x24
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if (value == 0U)
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8000246: 6a7b ldr r3, [r7, #36] ; 0x24
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8000248: 2b00 cmp r3, #0
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800024a: d101 bne.n 8000250 <LL_GPIO_SetPinMode+0x58>
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return 32U;
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800024c: 2320 movs r3, #32
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800024e: e003 b.n 8000258 <LL_GPIO_SetPinMode+0x60>
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return __builtin_clz(value);
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8000250: 6a7b ldr r3, [r7, #36] ; 0x24
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8000252: fab3 f383 clz r3, r3
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8000256: b2db uxtb r3, r3
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8000258: 005b lsls r3, r3, #1
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800025a: 6879 ldr r1, [r7, #4]
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800025c: fa01 f303 lsl.w r3, r1, r3
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8000260: 431a orrs r2, r3
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8000262: 68fb ldr r3, [r7, #12]
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8000264: 601a str r2, [r3, #0]
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}
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8000266: bf00 nop
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8000268: 372c adds r7, #44 ; 0x2c
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800026a: 46bd mov sp, r7
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800026c: f85d 7b04 ldr.w r7, [sp], #4
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8000270: 4770 bx lr
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08000272 <LL_GPIO_SetPinOutputType>:
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* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
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* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
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{
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8000272: b480 push {r7}
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8000274: b085 sub sp, #20
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8000276: af00 add r7, sp, #0
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8000278: 60f8 str r0, [r7, #12]
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800027a: 60b9 str r1, [r7, #8]
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800027c: 607a str r2, [r7, #4]
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MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
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800027e: 68fb ldr r3, [r7, #12]
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8000280: 685a ldr r2, [r3, #4]
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8000282: 68bb ldr r3, [r7, #8]
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8000284: 43db mvns r3, r3
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8000286: 401a ands r2, r3
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8000288: 68bb ldr r3, [r7, #8]
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800028a: 6879 ldr r1, [r7, #4]
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800028c: fb01 f303 mul.w r3, r1, r3
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8000290: 431a orrs r2, r3
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8000292: 68fb ldr r3, [r7, #12]
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8000294: 605a str r2, [r3, #4]
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}
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8000296: bf00 nop
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8000298: 3714 adds r7, #20
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800029a: 46bd mov sp, r7
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800029c: f85d 7b04 ldr.w r7, [sp], #4
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80002a0: 4770 bx lr
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080002a2 <LL_GPIO_IsInputPinSet>:
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* @arg @ref LL_GPIO_PIN_15
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* @arg @ref LL_GPIO_PIN_ALL
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
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{
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80002a2: b480 push {r7}
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80002a4: b083 sub sp, #12
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80002a6: af00 add r7, sp, #0
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80002a8: 6078 str r0, [r7, #4]
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80002aa: 6039 str r1, [r7, #0]
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return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
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80002ac: 687b ldr r3, [r7, #4]
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80002ae: 691a ldr r2, [r3, #16]
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80002b0: 683b ldr r3, [r7, #0]
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80002b2: 4013 ands r3, r2
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80002b4: 683a ldr r2, [r7, #0]
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80002b6: 429a cmp r2, r3
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80002b8: d101 bne.n 80002be <LL_GPIO_IsInputPinSet+0x1c>
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80002ba: 2301 movs r3, #1
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80002bc: e000 b.n 80002c0 <LL_GPIO_IsInputPinSet+0x1e>
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80002be: 2300 movs r3, #0
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}
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80002c0: 4618 mov r0, r3
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80002c2: 370c adds r7, #12
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80002c4: 46bd mov sp, r7
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80002c6: f85d 7b04 ldr.w r7, [sp], #4
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80002ca: 4770 bx lr
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080002cc <LL_GPIO_SetOutputPin>:
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* @arg @ref LL_GPIO_PIN_15
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* @arg @ref LL_GPIO_PIN_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
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{
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80002cc: b480 push {r7}
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80002ce: b083 sub sp, #12
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80002d0: af00 add r7, sp, #0
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80002d2: 6078 str r0, [r7, #4]
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80002d4: 6039 str r1, [r7, #0]
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WRITE_REG(GPIOx->BSRR, PinMask);
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80002d6: 687b ldr r3, [r7, #4]
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80002d8: 683a ldr r2, [r7, #0]
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80002da: 619a str r2, [r3, #24]
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}
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80002dc: bf00 nop
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80002de: 370c adds r7, #12
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80002e0: 46bd mov sp, r7
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80002e2: f85d 7b04 ldr.w r7, [sp], #4
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80002e6: 4770 bx lr
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080002e8 <LL_GPIO_ResetOutputPin>:
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* @arg @ref LL_GPIO_PIN_15
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* @arg @ref LL_GPIO_PIN_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
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{
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80002e8: b480 push {r7}
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80002ea: b083 sub sp, #12
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80002ec: af00 add r7, sp, #0
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80002ee: 6078 str r0, [r7, #4]
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80002f0: 6039 str r1, [r7, #0]
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WRITE_REG(GPIOx->BRR, PinMask);
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80002f2: 687b ldr r3, [r7, #4]
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80002f4: 683a ldr r2, [r7, #0]
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80002f6: 629a str r2, [r3, #40] ; 0x28
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}
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80002f8: bf00 nop
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80002fa: 370c adds r7, #12
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80002fc: 46bd mov sp, r7
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80002fe: f85d 7b04 ldr.w r7, [sp], #4
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8000302: 4770 bx lr
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08000304 <GPIO_init>:
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#define LED_PIN LL_GPIO_PIN_5
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#define BUT_PORT GPIOC
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#define BUT_PIN LL_GPIO_PIN_13
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void GPIO_init(void)
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{
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8000304: b580 push {r7, lr}
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8000306: af00 add r7, sp, #0
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// PORT A
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LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA );
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8000308: 2001 movs r0, #1
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800030a: f7ff ff5d bl 80001c8 <LL_AHB2_GRP1_EnableClock>
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// Green LED (user LED) - PA5
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LL_GPIO_SetPinMode( LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT );
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800030e: 2201 movs r2, #1
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8000310: 2120 movs r1, #32
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8000312: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
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8000316: f7ff ff6f bl 80001f8 <LL_GPIO_SetPinMode>
|
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LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL );
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800031a: 2200 movs r2, #0
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800031c: 2120 movs r1, #32
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800031e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
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8000322: f7ff ffa6 bl 8000272 <LL_GPIO_SetPinOutputType>
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|
|
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// PORT C
|
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LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC );
|
|
8000326: 2004 movs r0, #4
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|
8000328: f7ff ff4e bl 80001c8 <LL_AHB2_GRP1_EnableClock>
|
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// Blue button - PC13
|
|
LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT );
|
|
800032c: 2200 movs r2, #0
|
|
800032e: f44f 5100 mov.w r1, #8192 ; 0x2000
|
|
8000332: 4802 ldr r0, [pc, #8] ; (800033c <GPIO_init+0x38>)
|
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8000334: f7ff ff60 bl 80001f8 <LL_GPIO_SetPinMode>
|
|
}
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|
8000338: bf00 nop
|
|
800033a: bd80 pop {r7, pc}
|
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800033c: 48000800 .word 0x48000800
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08000340 <LED_GREEN>:
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void LED_GREEN( int val )
|
|
{
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|
8000340: b580 push {r7, lr}
|
|
8000342: b082 sub sp, #8
|
|
8000344: af00 add r7, sp, #0
|
|
8000346: 6078 str r0, [r7, #4]
|
|
if ( val )
|
|
8000348: 687b ldr r3, [r7, #4]
|
|
800034a: 2b00 cmp r3, #0
|
|
800034c: d005 beq.n 800035a <LED_GREEN+0x1a>
|
|
LL_GPIO_SetOutputPin( LED_PORT, LED_PIN );
|
|
800034e: 2120 movs r1, #32
|
|
8000350: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
8000354: f7ff ffba bl 80002cc <LL_GPIO_SetOutputPin>
|
|
else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
|
|
}
|
|
8000358: e004 b.n 8000364 <LED_GREEN+0x24>
|
|
else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
|
|
800035a: 2120 movs r1, #32
|
|
800035c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
8000360: f7ff ffc2 bl 80002e8 <LL_GPIO_ResetOutputPin>
|
|
}
|
|
8000364: bf00 nop
|
|
8000366: 3708 adds r7, #8
|
|
8000368: 46bd mov sp, r7
|
|
800036a: bd80 pop {r7, pc}
|
|
|
|
0800036c <BLUE_BUTTON>:
|
|
|
|
int BLUE_BUTTON()
|
|
{
|
|
800036c: b580 push {r7, lr}
|
|
800036e: af00 add r7, sp, #0
|
|
return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) );
|
|
8000370: f44f 5100 mov.w r1, #8192 ; 0x2000
|
|
8000374: 4805 ldr r0, [pc, #20] ; (800038c <BLUE_BUTTON+0x20>)
|
|
8000376: f7ff ff94 bl 80002a2 <LL_GPIO_IsInputPinSet>
|
|
800037a: 4603 mov r3, r0
|
|
800037c: 2b00 cmp r3, #0
|
|
800037e: bf0c ite eq
|
|
8000380: 2301 moveq r3, #1
|
|
8000382: 2300 movne r3, #0
|
|
8000384: b2db uxtb r3, r3
|
|
}
|
|
8000386: 4618 mov r0, r3
|
|
8000388: bd80 pop {r7, pc}
|
|
800038a: bf00 nop
|
|
800038c: 48000800 .word 0x48000800
|
|
|
|
08000390 <LL_RCC_MSI_Enable>:
|
|
* @brief Enable MSI oscillator
|
|
* @rmtoll CR MSION LL_RCC_MSI_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
|
|
{
|
|
8000390: b480 push {r7}
|
|
8000392: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSION);
|
|
8000394: 4b05 ldr r3, [pc, #20] ; (80003ac <LL_RCC_MSI_Enable+0x1c>)
|
|
8000396: 681b ldr r3, [r3, #0]
|
|
8000398: 4a04 ldr r2, [pc, #16] ; (80003ac <LL_RCC_MSI_Enable+0x1c>)
|
|
800039a: f043 0301 orr.w r3, r3, #1
|
|
800039e: 6013 str r3, [r2, #0]
|
|
}
|
|
80003a0: bf00 nop
|
|
80003a2: 46bd mov sp, r7
|
|
80003a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80003a8: 4770 bx lr
|
|
80003aa: bf00 nop
|
|
80003ac: 40021000 .word 0x40021000
|
|
|
|
080003b0 <LL_RCC_MSI_IsReady>:
|
|
* @brief Check if MSI oscillator Ready
|
|
* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
|
|
{
|
|
80003b0: b480 push {r7}
|
|
80003b2: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
|
|
80003b4: 4b06 ldr r3, [pc, #24] ; (80003d0 <LL_RCC_MSI_IsReady+0x20>)
|
|
80003b6: 681b ldr r3, [r3, #0]
|
|
80003b8: f003 0302 and.w r3, r3, #2
|
|
80003bc: 2b02 cmp r3, #2
|
|
80003be: d101 bne.n 80003c4 <LL_RCC_MSI_IsReady+0x14>
|
|
80003c0: 2301 movs r3, #1
|
|
80003c2: e000 b.n 80003c6 <LL_RCC_MSI_IsReady+0x16>
|
|
80003c4: 2300 movs r3, #0
|
|
}
|
|
80003c6: 4618 mov r0, r3
|
|
80003c8: 46bd mov sp, r7
|
|
80003ca: f85d 7b04 ldr.w r7, [sp], #4
|
|
80003ce: 4770 bx lr
|
|
80003d0: 40021000 .word 0x40021000
|
|
|
|
080003d4 <LL_RCC_SetSysClkSource>:
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
|
|
{
|
|
80003d4: b480 push {r7}
|
|
80003d6: b083 sub sp, #12
|
|
80003d8: af00 add r7, sp, #0
|
|
80003da: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
|
|
80003dc: 4b06 ldr r3, [pc, #24] ; (80003f8 <LL_RCC_SetSysClkSource+0x24>)
|
|
80003de: 689b ldr r3, [r3, #8]
|
|
80003e0: f023 0203 bic.w r2, r3, #3
|
|
80003e4: 4904 ldr r1, [pc, #16] ; (80003f8 <LL_RCC_SetSysClkSource+0x24>)
|
|
80003e6: 687b ldr r3, [r7, #4]
|
|
80003e8: 4313 orrs r3, r2
|
|
80003ea: 608b str r3, [r1, #8]
|
|
}
|
|
80003ec: bf00 nop
|
|
80003ee: 370c adds r7, #12
|
|
80003f0: 46bd mov sp, r7
|
|
80003f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80003f6: 4770 bx lr
|
|
80003f8: 40021000 .word 0x40021000
|
|
|
|
080003fc <LL_RCC_GetSysClkSource>:
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
|
|
{
|
|
80003fc: b480 push {r7}
|
|
80003fe: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
|
|
8000400: 4b04 ldr r3, [pc, #16] ; (8000414 <LL_RCC_GetSysClkSource+0x18>)
|
|
8000402: 689b ldr r3, [r3, #8]
|
|
8000404: f003 030c and.w r3, r3, #12
|
|
}
|
|
8000408: 4618 mov r0, r3
|
|
800040a: 46bd mov sp, r7
|
|
800040c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000410: 4770 bx lr
|
|
8000412: bf00 nop
|
|
8000414: 40021000 .word 0x40021000
|
|
|
|
08000418 <LL_RCC_SetAHBPrescaler>:
|
|
* @arg @ref LL_RCC_SYSCLK_DIV_256
|
|
* @arg @ref LL_RCC_SYSCLK_DIV_512
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
|
|
{
|
|
8000418: b480 push {r7}
|
|
800041a: b083 sub sp, #12
|
|
800041c: af00 add r7, sp, #0
|
|
800041e: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
|
|
8000420: 4b06 ldr r3, [pc, #24] ; (800043c <LL_RCC_SetAHBPrescaler+0x24>)
|
|
8000422: 689b ldr r3, [r3, #8]
|
|
8000424: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
8000428: 4904 ldr r1, [pc, #16] ; (800043c <LL_RCC_SetAHBPrescaler+0x24>)
|
|
800042a: 687b ldr r3, [r7, #4]
|
|
800042c: 4313 orrs r3, r2
|
|
800042e: 608b str r3, [r1, #8]
|
|
}
|
|
8000430: bf00 nop
|
|
8000432: 370c adds r7, #12
|
|
8000434: 46bd mov sp, r7
|
|
8000436: f85d 7b04 ldr.w r7, [sp], #4
|
|
800043a: 4770 bx lr
|
|
800043c: 40021000 .word 0x40021000
|
|
|
|
08000440 <LL_RCC_SetAPB1Prescaler>:
|
|
* @arg @ref LL_RCC_APB1_DIV_8
|
|
* @arg @ref LL_RCC_APB1_DIV_16
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
|
|
{
|
|
8000440: b480 push {r7}
|
|
8000442: b083 sub sp, #12
|
|
8000444: af00 add r7, sp, #0
|
|
8000446: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
|
|
8000448: 4b06 ldr r3, [pc, #24] ; (8000464 <LL_RCC_SetAPB1Prescaler+0x24>)
|
|
800044a: 689b ldr r3, [r3, #8]
|
|
800044c: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
8000450: 4904 ldr r1, [pc, #16] ; (8000464 <LL_RCC_SetAPB1Prescaler+0x24>)
|
|
8000452: 687b ldr r3, [r7, #4]
|
|
8000454: 4313 orrs r3, r2
|
|
8000456: 608b str r3, [r1, #8]
|
|
}
|
|
8000458: bf00 nop
|
|
800045a: 370c adds r7, #12
|
|
800045c: 46bd mov sp, r7
|
|
800045e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000462: 4770 bx lr
|
|
8000464: 40021000 .word 0x40021000
|
|
|
|
08000468 <LL_RCC_SetAPB2Prescaler>:
|
|
* @arg @ref LL_RCC_APB2_DIV_8
|
|
* @arg @ref LL_RCC_APB2_DIV_16
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
|
|
{
|
|
8000468: b480 push {r7}
|
|
800046a: b083 sub sp, #12
|
|
800046c: af00 add r7, sp, #0
|
|
800046e: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
|
|
8000470: 4b06 ldr r3, [pc, #24] ; (800048c <LL_RCC_SetAPB2Prescaler+0x24>)
|
|
8000472: 689b ldr r3, [r3, #8]
|
|
8000474: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
8000478: 4904 ldr r1, [pc, #16] ; (800048c <LL_RCC_SetAPB2Prescaler+0x24>)
|
|
800047a: 687b ldr r3, [r7, #4]
|
|
800047c: 4313 orrs r3, r2
|
|
800047e: 608b str r3, [r1, #8]
|
|
}
|
|
8000480: bf00 nop
|
|
8000482: 370c adds r7, #12
|
|
8000484: 46bd mov sp, r7
|
|
8000486: f85d 7b04 ldr.w r7, [sp], #4
|
|
800048a: 4770 bx lr
|
|
800048c: 40021000 .word 0x40021000
|
|
|
|
08000490 <LL_RCC_PLL_Enable>:
|
|
* @brief Enable PLL
|
|
* @rmtoll CR PLLON LL_RCC_PLL_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
|
|
{
|
|
8000490: b480 push {r7}
|
|
8000492: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_PLLON);
|
|
8000494: 4b05 ldr r3, [pc, #20] ; (80004ac <LL_RCC_PLL_Enable+0x1c>)
|
|
8000496: 681b ldr r3, [r3, #0]
|
|
8000498: 4a04 ldr r2, [pc, #16] ; (80004ac <LL_RCC_PLL_Enable+0x1c>)
|
|
800049a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
800049e: 6013 str r3, [r2, #0]
|
|
}
|
|
80004a0: bf00 nop
|
|
80004a2: 46bd mov sp, r7
|
|
80004a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80004a8: 4770 bx lr
|
|
80004aa: bf00 nop
|
|
80004ac: 40021000 .word 0x40021000
|
|
|
|
080004b0 <LL_RCC_PLL_IsReady>:
|
|
* @brief Check if PLL Ready
|
|
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
|
|
{
|
|
80004b0: b480 push {r7}
|
|
80004b2: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
|
|
80004b4: 4b07 ldr r3, [pc, #28] ; (80004d4 <LL_RCC_PLL_IsReady+0x24>)
|
|
80004b6: 681b ldr r3, [r3, #0]
|
|
80004b8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80004bc: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
|
|
80004c0: d101 bne.n 80004c6 <LL_RCC_PLL_IsReady+0x16>
|
|
80004c2: 2301 movs r3, #1
|
|
80004c4: e000 b.n 80004c8 <LL_RCC_PLL_IsReady+0x18>
|
|
80004c6: 2300 movs r3, #0
|
|
}
|
|
80004c8: 4618 mov r0, r3
|
|
80004ca: 46bd mov sp, r7
|
|
80004cc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80004d0: 4770 bx lr
|
|
80004d2: bf00 nop
|
|
80004d4: 40021000 .word 0x40021000
|
|
|
|
080004d8 <LL_RCC_PLL_ConfigDomain_SYS>:
|
|
* @arg @ref LL_RCC_PLLR_DIV_6
|
|
* @arg @ref LL_RCC_PLLR_DIV_8
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
|
|
{
|
|
80004d8: b480 push {r7}
|
|
80004da: b085 sub sp, #20
|
|
80004dc: af00 add r7, sp, #0
|
|
80004de: 60f8 str r0, [r7, #12]
|
|
80004e0: 60b9 str r1, [r7, #8]
|
|
80004e2: 607a str r2, [r7, #4]
|
|
80004e4: 603b str r3, [r7, #0]
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
|
|
80004e6: 4b0a ldr r3, [pc, #40] ; (8000510 <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
|
|
80004e8: 68da ldr r2, [r3, #12]
|
|
80004ea: 4b0a ldr r3, [pc, #40] ; (8000514 <LL_RCC_PLL_ConfigDomain_SYS+0x3c>)
|
|
80004ec: 4013 ands r3, r2
|
|
80004ee: 68f9 ldr r1, [r7, #12]
|
|
80004f0: 68ba ldr r2, [r7, #8]
|
|
80004f2: 4311 orrs r1, r2
|
|
80004f4: 687a ldr r2, [r7, #4]
|
|
80004f6: 0212 lsls r2, r2, #8
|
|
80004f8: 4311 orrs r1, r2
|
|
80004fa: 683a ldr r2, [r7, #0]
|
|
80004fc: 430a orrs r2, r1
|
|
80004fe: 4904 ldr r1, [pc, #16] ; (8000510 <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
|
|
8000500: 4313 orrs r3, r2
|
|
8000502: 60cb str r3, [r1, #12]
|
|
Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
|
|
}
|
|
8000504: bf00 nop
|
|
8000506: 3714 adds r7, #20
|
|
8000508: 46bd mov sp, r7
|
|
800050a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800050e: 4770 bx lr
|
|
8000510: 40021000 .word 0x40021000
|
|
8000514: f9ff808c .word 0xf9ff808c
|
|
|
|
08000518 <LL_RCC_PLL_EnableDomain_SYS>:
|
|
* @brief Enable PLL output mapped on SYSCLK domain
|
|
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
|
|
{
|
|
8000518: b480 push {r7}
|
|
800051a: af00 add r7, sp, #0
|
|
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
|
|
800051c: 4b05 ldr r3, [pc, #20] ; (8000534 <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
|
|
800051e: 68db ldr r3, [r3, #12]
|
|
8000520: 4a04 ldr r2, [pc, #16] ; (8000534 <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
|
|
8000522: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
8000526: 60d3 str r3, [r2, #12]
|
|
}
|
|
8000528: bf00 nop
|
|
800052a: 46bd mov sp, r7
|
|
800052c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000530: 4770 bx lr
|
|
8000532: bf00 nop
|
|
8000534: 40021000 .word 0x40021000
|
|
|
|
08000538 <LL_FLASH_SetLatency>:
|
|
*
|
|
* (*) value not defined in all devices.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
|
|
{
|
|
8000538: b480 push {r7}
|
|
800053a: b083 sub sp, #12
|
|
800053c: af00 add r7, sp, #0
|
|
800053e: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
|
|
8000540: 4b06 ldr r3, [pc, #24] ; (800055c <LL_FLASH_SetLatency+0x24>)
|
|
8000542: 681b ldr r3, [r3, #0]
|
|
8000544: f023 0207 bic.w r2, r3, #7
|
|
8000548: 4904 ldr r1, [pc, #16] ; (800055c <LL_FLASH_SetLatency+0x24>)
|
|
800054a: 687b ldr r3, [r7, #4]
|
|
800054c: 4313 orrs r3, r2
|
|
800054e: 600b str r3, [r1, #0]
|
|
}
|
|
8000550: bf00 nop
|
|
8000552: 370c adds r7, #12
|
|
8000554: 46bd mov sp, r7
|
|
8000556: f85d 7b04 ldr.w r7, [sp], #4
|
|
800055a: 4770 bx lr
|
|
800055c: 40022000 .word 0x40022000
|
|
|
|
08000560 <LL_SYSTICK_EnableIT>:
|
|
* @brief Enable SysTick exception request
|
|
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
|
|
{
|
|
8000560: b480 push {r7}
|
|
8000562: af00 add r7, sp, #0
|
|
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
|
8000564: 4b05 ldr r3, [pc, #20] ; (800057c <LL_SYSTICK_EnableIT+0x1c>)
|
|
8000566: 681b ldr r3, [r3, #0]
|
|
8000568: 4a04 ldr r2, [pc, #16] ; (800057c <LL_SYSTICK_EnableIT+0x1c>)
|
|
800056a: f043 0302 orr.w r3, r3, #2
|
|
800056e: 6013 str r3, [r2, #0]
|
|
}
|
|
8000570: bf00 nop
|
|
8000572: 46bd mov sp, r7
|
|
8000574: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000578: 4770 bx lr
|
|
800057a: bf00 nop
|
|
800057c: e000e010 .word 0xe000e010
|
|
|
|
08000580 <SysTick_Handler>:
|
|
volatile uint32_t msTicks = 0;
|
|
volatile uint8_t expe = 0;
|
|
volatile uint8_t blue_mode = 0;
|
|
|
|
void SysTick_Handler()
|
|
{
|
|
8000580: b580 push {r7, lr}
|
|
8000582: af00 add r7, sp, #0
|
|
|
|
msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
|
|
8000584: 4b0c ldr r3, [pc, #48] ; (80005b8 <SysTick_Handler+0x38>)
|
|
8000586: 681b ldr r3, [r3, #0]
|
|
8000588: 3301 adds r3, #1
|
|
800058a: 4a0b ldr r2, [pc, #44] ; (80005b8 <SysTick_Handler+0x38>)
|
|
800058c: 6013 str r3, [r2, #0]
|
|
if (msTicks == 50){
|
|
800058e: 4b0a ldr r3, [pc, #40] ; (80005b8 <SysTick_Handler+0x38>)
|
|
8000590: 681b ldr r3, [r3, #0]
|
|
8000592: 2b32 cmp r3, #50 ; 0x32
|
|
8000594: d103 bne.n 800059e <SysTick_Handler+0x1e>
|
|
LED_GREEN(0);
|
|
8000596: 2000 movs r0, #0
|
|
8000598: f7ff fed2 bl 8000340 <LED_GREEN>
|
|
}else if(msTicks >= 1000){
|
|
msTicks = 0;
|
|
LED_GREEN(1);
|
|
}
|
|
}
|
|
800059c: e00a b.n 80005b4 <SysTick_Handler+0x34>
|
|
}else if(msTicks >= 1000){
|
|
800059e: 4b06 ldr r3, [pc, #24] ; (80005b8 <SysTick_Handler+0x38>)
|
|
80005a0: 681b ldr r3, [r3, #0]
|
|
80005a2: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
80005a6: d305 bcc.n 80005b4 <SysTick_Handler+0x34>
|
|
msTicks = 0;
|
|
80005a8: 4b03 ldr r3, [pc, #12] ; (80005b8 <SysTick_Handler+0x38>)
|
|
80005aa: 2200 movs r2, #0
|
|
80005ac: 601a str r2, [r3, #0]
|
|
LED_GREEN(1);
|
|
80005ae: 2001 movs r0, #1
|
|
80005b0: f7ff fec6 bl 8000340 <LED_GREEN>
|
|
}
|
|
80005b4: bf00 nop
|
|
80005b6: bd80 pop {r7, pc}
|
|
80005b8: 20000020 .word 0x20000020
|
|
|
|
080005bc <main>:
|
|
|
|
void SystemClock_Config(void);
|
|
|
|
int main(void)
|
|
{
|
|
80005bc: b580 push {r7, lr}
|
|
80005be: af00 add r7, sp, #0
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
80005c0: f000 f816 bl 80005f0 <SystemClock_Config>
|
|
|
|
// config GPIO
|
|
GPIO_init();
|
|
80005c4: f7ff fe9e bl 8000304 <GPIO_init>
|
|
|
|
// init systick timer (tick period at 1 ms)
|
|
LL_Init1msTick( SystemCoreClock );
|
|
80005c8: 4b07 ldr r3, [pc, #28] ; (80005e8 <main+0x2c>)
|
|
80005ca: 681b ldr r3, [r3, #0]
|
|
80005cc: 4618 mov r0, r3
|
|
80005ce: f000 f99f bl 8000910 <LL_Init1msTick>
|
|
LL_SYSTICK_EnableIT();
|
|
80005d2: f7ff ffc5 bl 8000560 <LL_SYSTICK_EnableIT>
|
|
|
|
|
|
while (1) {
|
|
if ( BLUE_BUTTON() ){
|
|
80005d6: f7ff fec9 bl 800036c <BLUE_BUTTON>
|
|
80005da: 4603 mov r3, r0
|
|
80005dc: 2b00 cmp r3, #0
|
|
80005de: d0fa beq.n 80005d6 <main+0x1a>
|
|
blue_mode = 1;
|
|
80005e0: 4b02 ldr r3, [pc, #8] ; (80005ec <main+0x30>)
|
|
80005e2: 2201 movs r2, #1
|
|
80005e4: 701a strb r2, [r3, #0]
|
|
if ( BLUE_BUTTON() ){
|
|
80005e6: e7f6 b.n 80005d6 <main+0x1a>
|
|
80005e8: 20000000 .word 0x20000000
|
|
80005ec: 20000024 .word 0x20000024
|
|
|
|
080005f0 <SystemClock_Config>:
|
|
* PLL_R = 2
|
|
* Flash Latency(WS) = 4
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void) {
|
|
80005f0: b580 push {r7, lr}
|
|
80005f2: af00 add r7, sp, #0
|
|
/* MSI configuration and activation */
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
|
|
80005f4: 2004 movs r0, #4
|
|
80005f6: f7ff ff9f bl 8000538 <LL_FLASH_SetLatency>
|
|
LL_RCC_MSI_Enable();
|
|
80005fa: f7ff fec9 bl 8000390 <LL_RCC_MSI_Enable>
|
|
while (LL_RCC_MSI_IsReady() != 1)
|
|
80005fe: bf00 nop
|
|
8000600: f7ff fed6 bl 80003b0 <LL_RCC_MSI_IsReady>
|
|
8000604: 4603 mov r3, r0
|
|
8000606: 2b01 cmp r3, #1
|
|
8000608: d1fa bne.n 8000600 <SystemClock_Config+0x10>
|
|
{ };
|
|
|
|
/* Main PLL configuration and activation */
|
|
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);
|
|
800060a: 2300 movs r3, #0
|
|
800060c: 2228 movs r2, #40 ; 0x28
|
|
800060e: 2100 movs r1, #0
|
|
8000610: 2001 movs r0, #1
|
|
8000612: f7ff ff61 bl 80004d8 <LL_RCC_PLL_ConfigDomain_SYS>
|
|
LL_RCC_PLL_Enable();
|
|
8000616: f7ff ff3b bl 8000490 <LL_RCC_PLL_Enable>
|
|
LL_RCC_PLL_EnableDomain_SYS();
|
|
800061a: f7ff ff7d bl 8000518 <LL_RCC_PLL_EnableDomain_SYS>
|
|
while(LL_RCC_PLL_IsReady() != 1)
|
|
800061e: bf00 nop
|
|
8000620: f7ff ff46 bl 80004b0 <LL_RCC_PLL_IsReady>
|
|
8000624: 4603 mov r3, r0
|
|
8000626: 2b01 cmp r3, #1
|
|
8000628: d1fa bne.n 8000620 <SystemClock_Config+0x30>
|
|
{ };
|
|
|
|
/* Sysclk activation on the main PLL */
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
800062a: 2000 movs r0, #0
|
|
800062c: f7ff fef4 bl 8000418 <LL_RCC_SetAHBPrescaler>
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
8000630: 2003 movs r0, #3
|
|
8000632: f7ff fecf bl 80003d4 <LL_RCC_SetSysClkSource>
|
|
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
|
8000636: bf00 nop
|
|
8000638: f7ff fee0 bl 80003fc <LL_RCC_GetSysClkSource>
|
|
800063c: 4603 mov r3, r0
|
|
800063e: 2b0c cmp r3, #12
|
|
8000640: d1fa bne.n 8000638 <SystemClock_Config+0x48>
|
|
{ };
|
|
|
|
/* Set APB1 & APB2 prescaler*/
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
|
|
8000642: 2000 movs r0, #0
|
|
8000644: f7ff fefc bl 8000440 <LL_RCC_SetAPB1Prescaler>
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
|
8000648: 2000 movs r0, #0
|
|
800064a: f7ff ff0d bl 8000468 <LL_RCC_SetAPB2Prescaler>
|
|
|
|
/* Update the global variable called SystemCoreClock */
|
|
SystemCoreClockUpdate();
|
|
800064e: f000 f861 bl 8000714 <SystemCoreClockUpdate>
|
|
}
|
|
8000652: bf00 nop
|
|
8000654: bd80 pop {r7, pc}
|
|
|
|
08000656 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000656: b480 push {r7}
|
|
8000658: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 1 */
|
|
}
|
|
800065a: bf00 nop
|
|
800065c: 46bd mov sp, r7
|
|
800065e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000662: 4770 bx lr
|
|
|
|
08000664 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8000664: b480 push {r7}
|
|
8000666: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8000668: e7fe b.n 8000668 <HardFault_Handler+0x4>
|
|
|
|
0800066a <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
800066a: b480 push {r7}
|
|
800066c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
800066e: e7fe b.n 800066e <MemManage_Handler+0x4>
|
|
|
|
08000670 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8000670: b480 push {r7}
|
|
8000672: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8000674: e7fe b.n 8000674 <BusFault_Handler+0x4>
|
|
|
|
08000676 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000676: b480 push {r7}
|
|
8000678: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
800067a: e7fe b.n 800067a <UsageFault_Handler+0x4>
|
|
|
|
0800067c <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
800067c: b480 push {r7}
|
|
800067e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8000680: bf00 nop
|
|
8000682: 46bd mov sp, r7
|
|
8000684: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000688: 4770 bx lr
|
|
|
|
0800068a <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
800068a: b480 push {r7}
|
|
800068c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800068e: bf00 nop
|
|
8000690: 46bd mov sp, r7
|
|
8000692: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000696: 4770 bx lr
|
|
|
|
08000698 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000698: b480 push {r7}
|
|
800069a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
800069c: bf00 nop
|
|
800069e: 46bd mov sp, r7
|
|
80006a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80006a4: 4770 bx lr
|
|
...
|
|
|
|
080006a8 <SystemInit>:
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
80006a8: b480 push {r7}
|
|
80006aa: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
80006ac: 4b17 ldr r3, [pc, #92] ; (800070c <SystemInit+0x64>)
|
|
80006ae: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
80006b2: 4a16 ldr r2, [pc, #88] ; (800070c <SystemInit+0x64>)
|
|
80006b4: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
|
80006b8: f8c2 3088 str.w r3, [r2, #136] ; 0x88
|
|
#endif
|
|
|
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
|
/* Set MSION bit */
|
|
RCC->CR |= RCC_CR_MSION;
|
|
80006bc: 4b14 ldr r3, [pc, #80] ; (8000710 <SystemInit+0x68>)
|
|
80006be: 681b ldr r3, [r3, #0]
|
|
80006c0: 4a13 ldr r2, [pc, #76] ; (8000710 <SystemInit+0x68>)
|
|
80006c2: f043 0301 orr.w r3, r3, #1
|
|
80006c6: 6013 str r3, [r2, #0]
|
|
|
|
/* Reset CFGR register */
|
|
RCC->CFGR = 0x00000000U;
|
|
80006c8: 4b11 ldr r3, [pc, #68] ; (8000710 <SystemInit+0x68>)
|
|
80006ca: 2200 movs r2, #0
|
|
80006cc: 609a str r2, [r3, #8]
|
|
|
|
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
|
RCC->CR &= 0xEAF6FFFFU;
|
|
80006ce: 4b10 ldr r3, [pc, #64] ; (8000710 <SystemInit+0x68>)
|
|
80006d0: 681b ldr r3, [r3, #0]
|
|
80006d2: 4a0f ldr r2, [pc, #60] ; (8000710 <SystemInit+0x68>)
|
|
80006d4: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
|
|
80006d8: f423 2310 bic.w r3, r3, #589824 ; 0x90000
|
|
80006dc: 6013 str r3, [r2, #0]
|
|
|
|
/* Reset PLLCFGR register */
|
|
RCC->PLLCFGR = 0x00001000U;
|
|
80006de: 4b0c ldr r3, [pc, #48] ; (8000710 <SystemInit+0x68>)
|
|
80006e0: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
80006e4: 60da str r2, [r3, #12]
|
|
|
|
/* Reset HSEBYP bit */
|
|
RCC->CR &= 0xFFFBFFFFU;
|
|
80006e6: 4b0a ldr r3, [pc, #40] ; (8000710 <SystemInit+0x68>)
|
|
80006e8: 681b ldr r3, [r3, #0]
|
|
80006ea: 4a09 ldr r2, [pc, #36] ; (8000710 <SystemInit+0x68>)
|
|
80006ec: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
80006f0: 6013 str r3, [r2, #0]
|
|
|
|
/* Disable all interrupts */
|
|
RCC->CIER = 0x00000000U;
|
|
80006f2: 4b07 ldr r3, [pc, #28] ; (8000710 <SystemInit+0x68>)
|
|
80006f4: 2200 movs r2, #0
|
|
80006f6: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
|
#ifdef VECT_TAB_SRAM
|
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#else
|
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
|
80006f8: 4b04 ldr r3, [pc, #16] ; (800070c <SystemInit+0x64>)
|
|
80006fa: f04f 6200 mov.w r2, #134217728 ; 0x8000000
|
|
80006fe: 609a str r2, [r3, #8]
|
|
#endif
|
|
}
|
|
8000700: bf00 nop
|
|
8000702: 46bd mov sp, r7
|
|
8000704: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000708: 4770 bx lr
|
|
800070a: bf00 nop
|
|
800070c: e000ed00 .word 0xe000ed00
|
|
8000710: 40021000 .word 0x40021000
|
|
|
|
08000714 <SystemCoreClockUpdate>:
|
|
*
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemCoreClockUpdate(void)
|
|
{
|
|
8000714: b480 push {r7}
|
|
8000716: b087 sub sp, #28
|
|
8000718: af00 add r7, sp, #0
|
|
uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
|
|
800071a: 2300 movs r3, #0
|
|
800071c: 60fb str r3, [r7, #12]
|
|
800071e: 2300 movs r3, #0
|
|
8000720: 617b str r3, [r7, #20]
|
|
8000722: 2300 movs r3, #0
|
|
8000724: 613b str r3, [r7, #16]
|
|
8000726: 2302 movs r3, #2
|
|
8000728: 60bb str r3, [r7, #8]
|
|
800072a: 2300 movs r3, #0
|
|
800072c: 607b str r3, [r7, #4]
|
|
800072e: 2302 movs r3, #2
|
|
8000730: 603b str r3, [r7, #0]
|
|
|
|
/* Get MSI Range frequency--------------------------------------------------*/
|
|
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
|
|
8000732: 4b4f ldr r3, [pc, #316] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
8000734: 681b ldr r3, [r3, #0]
|
|
8000736: f003 0308 and.w r3, r3, #8
|
|
800073a: 2b00 cmp r3, #0
|
|
800073c: d107 bne.n 800074e <SystemCoreClockUpdate+0x3a>
|
|
{ /* MSISRANGE from RCC_CSR applies */
|
|
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
|
|
800073e: 4b4c ldr r3, [pc, #304] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
8000740: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
8000744: 0a1b lsrs r3, r3, #8
|
|
8000746: f003 030f and.w r3, r3, #15
|
|
800074a: 617b str r3, [r7, #20]
|
|
800074c: e005 b.n 800075a <SystemCoreClockUpdate+0x46>
|
|
}
|
|
else
|
|
{ /* MSIRANGE from RCC_CR applies */
|
|
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
|
|
800074e: 4b48 ldr r3, [pc, #288] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
8000750: 681b ldr r3, [r3, #0]
|
|
8000752: 091b lsrs r3, r3, #4
|
|
8000754: f003 030f and.w r3, r3, #15
|
|
8000758: 617b str r3, [r7, #20]
|
|
}
|
|
/*MSI frequency range in HZ*/
|
|
msirange = MSIRangeTable[msirange];
|
|
800075a: 4a46 ldr r2, [pc, #280] ; (8000874 <SystemCoreClockUpdate+0x160>)
|
|
800075c: 697b ldr r3, [r7, #20]
|
|
800075e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8000762: 617b str r3, [r7, #20]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
8000764: 4b42 ldr r3, [pc, #264] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
8000766: 689b ldr r3, [r3, #8]
|
|
8000768: f003 030c and.w r3, r3, #12
|
|
800076c: 2b0c cmp r3, #12
|
|
800076e: d865 bhi.n 800083c <SystemCoreClockUpdate+0x128>
|
|
8000770: a201 add r2, pc, #4 ; (adr r2, 8000778 <SystemCoreClockUpdate+0x64>)
|
|
8000772: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8000776: bf00 nop
|
|
8000778: 080007ad .word 0x080007ad
|
|
800077c: 0800083d .word 0x0800083d
|
|
8000780: 0800083d .word 0x0800083d
|
|
8000784: 0800083d .word 0x0800083d
|
|
8000788: 080007b5 .word 0x080007b5
|
|
800078c: 0800083d .word 0x0800083d
|
|
8000790: 0800083d .word 0x0800083d
|
|
8000794: 0800083d .word 0x0800083d
|
|
8000798: 080007bd .word 0x080007bd
|
|
800079c: 0800083d .word 0x0800083d
|
|
80007a0: 0800083d .word 0x0800083d
|
|
80007a4: 0800083d .word 0x0800083d
|
|
80007a8: 080007c5 .word 0x080007c5
|
|
{
|
|
case 0x00: /* MSI used as system clock source */
|
|
SystemCoreClock = msirange;
|
|
80007ac: 4a32 ldr r2, [pc, #200] ; (8000878 <SystemCoreClockUpdate+0x164>)
|
|
80007ae: 697b ldr r3, [r7, #20]
|
|
80007b0: 6013 str r3, [r2, #0]
|
|
break;
|
|
80007b2: e047 b.n 8000844 <SystemCoreClockUpdate+0x130>
|
|
|
|
case 0x04: /* HSI used as system clock source */
|
|
SystemCoreClock = HSI_VALUE;
|
|
80007b4: 4b30 ldr r3, [pc, #192] ; (8000878 <SystemCoreClockUpdate+0x164>)
|
|
80007b6: 4a31 ldr r2, [pc, #196] ; (800087c <SystemCoreClockUpdate+0x168>)
|
|
80007b8: 601a str r2, [r3, #0]
|
|
break;
|
|
80007ba: e043 b.n 8000844 <SystemCoreClockUpdate+0x130>
|
|
|
|
case 0x08: /* HSE used as system clock source */
|
|
SystemCoreClock = HSE_VALUE;
|
|
80007bc: 4b2e ldr r3, [pc, #184] ; (8000878 <SystemCoreClockUpdate+0x164>)
|
|
80007be: 4a30 ldr r2, [pc, #192] ; (8000880 <SystemCoreClockUpdate+0x16c>)
|
|
80007c0: 601a str r2, [r3, #0]
|
|
break;
|
|
80007c2: e03f b.n 8000844 <SystemCoreClockUpdate+0x130>
|
|
|
|
case 0x0C: /* PLL used as system clock source */
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
|
80007c4: 4b2a ldr r3, [pc, #168] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
80007c6: 68db ldr r3, [r3, #12]
|
|
80007c8: f003 0303 and.w r3, r3, #3
|
|
80007cc: 607b str r3, [r7, #4]
|
|
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
|
|
80007ce: 4b28 ldr r3, [pc, #160] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
80007d0: 68db ldr r3, [r3, #12]
|
|
80007d2: 091b lsrs r3, r3, #4
|
|
80007d4: f003 0307 and.w r3, r3, #7
|
|
80007d8: 3301 adds r3, #1
|
|
80007da: 603b str r3, [r7, #0]
|
|
|
|
switch (pllsource)
|
|
80007dc: 687b ldr r3, [r7, #4]
|
|
80007de: 2b02 cmp r3, #2
|
|
80007e0: d002 beq.n 80007e8 <SystemCoreClockUpdate+0xd4>
|
|
80007e2: 2b03 cmp r3, #3
|
|
80007e4: d006 beq.n 80007f4 <SystemCoreClockUpdate+0xe0>
|
|
80007e6: e00b b.n 8000800 <SystemCoreClockUpdate+0xec>
|
|
{
|
|
case 0x02: /* HSI used as PLL clock source */
|
|
pllvco = (HSI_VALUE / pllm);
|
|
80007e8: 4a24 ldr r2, [pc, #144] ; (800087c <SystemCoreClockUpdate+0x168>)
|
|
80007ea: 683b ldr r3, [r7, #0]
|
|
80007ec: fbb2 f3f3 udiv r3, r2, r3
|
|
80007f0: 613b str r3, [r7, #16]
|
|
break;
|
|
80007f2: e00b b.n 800080c <SystemCoreClockUpdate+0xf8>
|
|
|
|
case 0x03: /* HSE used as PLL clock source */
|
|
pllvco = (HSE_VALUE / pllm);
|
|
80007f4: 4a22 ldr r2, [pc, #136] ; (8000880 <SystemCoreClockUpdate+0x16c>)
|
|
80007f6: 683b ldr r3, [r7, #0]
|
|
80007f8: fbb2 f3f3 udiv r3, r2, r3
|
|
80007fc: 613b str r3, [r7, #16]
|
|
break;
|
|
80007fe: e005 b.n 800080c <SystemCoreClockUpdate+0xf8>
|
|
|
|
default: /* MSI used as PLL clock source */
|
|
pllvco = (msirange / pllm);
|
|
8000800: 697a ldr r2, [r7, #20]
|
|
8000802: 683b ldr r3, [r7, #0]
|
|
8000804: fbb2 f3f3 udiv r3, r2, r3
|
|
8000808: 613b str r3, [r7, #16]
|
|
break;
|
|
800080a: bf00 nop
|
|
}
|
|
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
|
|
800080c: 4b18 ldr r3, [pc, #96] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
800080e: 68db ldr r3, [r3, #12]
|
|
8000810: 0a1b lsrs r3, r3, #8
|
|
8000812: f003 027f and.w r2, r3, #127 ; 0x7f
|
|
8000816: 693b ldr r3, [r7, #16]
|
|
8000818: fb02 f303 mul.w r3, r2, r3
|
|
800081c: 613b str r3, [r7, #16]
|
|
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
|
|
800081e: 4b14 ldr r3, [pc, #80] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
8000820: 68db ldr r3, [r3, #12]
|
|
8000822: 0e5b lsrs r3, r3, #25
|
|
8000824: f003 0303 and.w r3, r3, #3
|
|
8000828: 3301 adds r3, #1
|
|
800082a: 005b lsls r3, r3, #1
|
|
800082c: 60bb str r3, [r7, #8]
|
|
SystemCoreClock = pllvco/pllr;
|
|
800082e: 693a ldr r2, [r7, #16]
|
|
8000830: 68bb ldr r3, [r7, #8]
|
|
8000832: fbb2 f3f3 udiv r3, r2, r3
|
|
8000836: 4a10 ldr r2, [pc, #64] ; (8000878 <SystemCoreClockUpdate+0x164>)
|
|
8000838: 6013 str r3, [r2, #0]
|
|
break;
|
|
800083a: e003 b.n 8000844 <SystemCoreClockUpdate+0x130>
|
|
|
|
default:
|
|
SystemCoreClock = msirange;
|
|
800083c: 4a0e ldr r2, [pc, #56] ; (8000878 <SystemCoreClockUpdate+0x164>)
|
|
800083e: 697b ldr r3, [r7, #20]
|
|
8000840: 6013 str r3, [r2, #0]
|
|
break;
|
|
8000842: bf00 nop
|
|
}
|
|
/* Compute HCLK clock frequency --------------------------------------------*/
|
|
/* Get HCLK prescaler */
|
|
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
|
|
8000844: 4b0a ldr r3, [pc, #40] ; (8000870 <SystemCoreClockUpdate+0x15c>)
|
|
8000846: 689b ldr r3, [r3, #8]
|
|
8000848: 091b lsrs r3, r3, #4
|
|
800084a: f003 030f and.w r3, r3, #15
|
|
800084e: 4a0d ldr r2, [pc, #52] ; (8000884 <SystemCoreClockUpdate+0x170>)
|
|
8000850: 5cd3 ldrb r3, [r2, r3]
|
|
8000852: 60fb str r3, [r7, #12]
|
|
/* HCLK clock frequency */
|
|
SystemCoreClock >>= tmp;
|
|
8000854: 4b08 ldr r3, [pc, #32] ; (8000878 <SystemCoreClockUpdate+0x164>)
|
|
8000856: 681a ldr r2, [r3, #0]
|
|
8000858: 68fb ldr r3, [r7, #12]
|
|
800085a: fa22 f303 lsr.w r3, r2, r3
|
|
800085e: 4a06 ldr r2, [pc, #24] ; (8000878 <SystemCoreClockUpdate+0x164>)
|
|
8000860: 6013 str r3, [r2, #0]
|
|
}
|
|
8000862: bf00 nop
|
|
8000864: 371c adds r7, #28
|
|
8000866: 46bd mov sp, r7
|
|
8000868: f85d 7b04 ldr.w r7, [sp], #4
|
|
800086c: 4770 bx lr
|
|
800086e: bf00 nop
|
|
8000870: 40021000 .word 0x40021000
|
|
8000874: 0800099c .word 0x0800099c
|
|
8000878: 20000000 .word 0x20000000
|
|
800087c: 00f42400 .word 0x00f42400
|
|
8000880: 007a1200 .word 0x007a1200
|
|
8000884: 0800098c .word 0x0800098c
|
|
|
|
08000888 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8000888: f8df d034 ldr.w sp, [pc, #52] ; 80008c0 <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
800088c: f7ff ff0c bl 80006a8 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
movs r1, #0
|
|
8000890: 2100 movs r1, #0
|
|
b LoopCopyDataInit
|
|
8000892: e003 b.n 800089c <LoopCopyDataInit>
|
|
|
|
08000894 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r3, =_sidata
|
|
8000894: 4b0b ldr r3, [pc, #44] ; (80008c4 <LoopForever+0x6>)
|
|
ldr r3, [r3, r1]
|
|
8000896: 585b ldr r3, [r3, r1]
|
|
str r3, [r0, r1]
|
|
8000898: 5043 str r3, [r0, r1]
|
|
adds r1, r1, #4
|
|
800089a: 3104 adds r1, #4
|
|
|
|
0800089c <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
ldr r0, =_sdata
|
|
800089c: 480a ldr r0, [pc, #40] ; (80008c8 <LoopForever+0xa>)
|
|
ldr r3, =_edata
|
|
800089e: 4b0b ldr r3, [pc, #44] ; (80008cc <LoopForever+0xe>)
|
|
adds r2, r0, r1
|
|
80008a0: 1842 adds r2, r0, r1
|
|
cmp r2, r3
|
|
80008a2: 429a cmp r2, r3
|
|
bcc CopyDataInit
|
|
80008a4: d3f6 bcc.n 8000894 <CopyDataInit>
|
|
ldr r2, =_sbss
|
|
80008a6: 4a0a ldr r2, [pc, #40] ; (80008d0 <LoopForever+0x12>)
|
|
b LoopFillZerobss
|
|
80008a8: e002 b.n 80008b0 <LoopFillZerobss>
|
|
|
|
080008aa <FillZerobss>:
|
|
/* Zero fill the bss segment. */
|
|
FillZerobss:
|
|
movs r3, #0
|
|
80008aa: 2300 movs r3, #0
|
|
str r3, [r2], #4
|
|
80008ac: f842 3b04 str.w r3, [r2], #4
|
|
|
|
080008b0 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
ldr r3, = _ebss
|
|
80008b0: 4b08 ldr r3, [pc, #32] ; (80008d4 <LoopForever+0x16>)
|
|
cmp r2, r3
|
|
80008b2: 429a cmp r2, r3
|
|
bcc FillZerobss
|
|
80008b4: d3f9 bcc.n 80008aa <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
80008b6: f000 f839 bl 800092c <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
80008ba: f7ff fe7f bl 80005bc <main>
|
|
|
|
080008be <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
80008be: e7fe b.n 80008be <LoopForever>
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
80008c0: 20018000 .word 0x20018000
|
|
ldr r3, =_sidata
|
|
80008c4: 080009d4 .word 0x080009d4
|
|
ldr r0, =_sdata
|
|
80008c8: 20000000 .word 0x20000000
|
|
ldr r3, =_edata
|
|
80008cc: 20000004 .word 0x20000004
|
|
ldr r2, =_sbss
|
|
80008d0: 20000004 .word 0x20000004
|
|
ldr r3, = _ebss
|
|
80008d4: 20000028 .word 0x20000028
|
|
|
|
080008d8 <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80008d8: e7fe b.n 80008d8 <ADC1_2_IRQHandler>
|
|
...
|
|
|
|
080008dc <LL_InitTick>:
|
|
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
|
* @param Ticks Number of ticks
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
|
{
|
|
80008dc: b480 push {r7}
|
|
80008de: b083 sub sp, #12
|
|
80008e0: af00 add r7, sp, #0
|
|
80008e2: 6078 str r0, [r7, #4]
|
|
80008e4: 6039 str r1, [r7, #0]
|
|
/* Configure the SysTick to have interrupt in 1ms time base */
|
|
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
|
80008e6: 687a ldr r2, [r7, #4]
|
|
80008e8: 683b ldr r3, [r7, #0]
|
|
80008ea: fbb2 f3f3 udiv r3, r2, r3
|
|
80008ee: 4a07 ldr r2, [pc, #28] ; (800090c <LL_InitTick+0x30>)
|
|
80008f0: 3b01 subs r3, #1
|
|
80008f2: 6053 str r3, [r2, #4]
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
80008f4: 4b05 ldr r3, [pc, #20] ; (800090c <LL_InitTick+0x30>)
|
|
80008f6: 2200 movs r2, #0
|
|
80008f8: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
80008fa: 4b04 ldr r3, [pc, #16] ; (800090c <LL_InitTick+0x30>)
|
|
80008fc: 2205 movs r2, #5
|
|
80008fe: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_ENABLE_Msk;
|
|
}
|
|
8000900: bf00 nop
|
|
8000902: 370c adds r7, #12
|
|
8000904: 46bd mov sp, r7
|
|
8000906: f85d 7b04 ldr.w r7, [sp], #4
|
|
800090a: 4770 bx lr
|
|
800090c: e000e010 .word 0xe000e010
|
|
|
|
08000910 <LL_Init1msTick>:
|
|
* @param HCLKFrequency HCLK frequency in Hz
|
|
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
|
|
* @retval None
|
|
*/
|
|
void LL_Init1msTick(uint32_t HCLKFrequency)
|
|
{
|
|
8000910: b580 push {r7, lr}
|
|
8000912: b082 sub sp, #8
|
|
8000914: af00 add r7, sp, #0
|
|
8000916: 6078 str r0, [r7, #4]
|
|
/* Use frequency provided in argument */
|
|
LL_InitTick(HCLKFrequency, 1000U);
|
|
8000918: f44f 717a mov.w r1, #1000 ; 0x3e8
|
|
800091c: 6878 ldr r0, [r7, #4]
|
|
800091e: f7ff ffdd bl 80008dc <LL_InitTick>
|
|
}
|
|
8000922: bf00 nop
|
|
8000924: 3708 adds r7, #8
|
|
8000926: 46bd mov sp, r7
|
|
8000928: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800092c <__libc_init_array>:
|
|
800092c: b570 push {r4, r5, r6, lr}
|
|
800092e: 4e0d ldr r6, [pc, #52] ; (8000964 <__libc_init_array+0x38>)
|
|
8000930: 4c0d ldr r4, [pc, #52] ; (8000968 <__libc_init_array+0x3c>)
|
|
8000932: 1ba4 subs r4, r4, r6
|
|
8000934: 10a4 asrs r4, r4, #2
|
|
8000936: 2500 movs r5, #0
|
|
8000938: 42a5 cmp r5, r4
|
|
800093a: d109 bne.n 8000950 <__libc_init_array+0x24>
|
|
800093c: 4e0b ldr r6, [pc, #44] ; (800096c <__libc_init_array+0x40>)
|
|
800093e: 4c0c ldr r4, [pc, #48] ; (8000970 <__libc_init_array+0x44>)
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8000940: f000 f818 bl 8000974 <_init>
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8000944: 1ba4 subs r4, r4, r6
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8000946: 10a4 asrs r4, r4, #2
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8000948: 2500 movs r5, #0
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800094a: 42a5 cmp r5, r4
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800094c: d105 bne.n 800095a <__libc_init_array+0x2e>
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800094e: bd70 pop {r4, r5, r6, pc}
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8000950: f856 3025 ldr.w r3, [r6, r5, lsl #2]
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8000954: 4798 blx r3
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8000956: 3501 adds r5, #1
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|
8000958: e7ee b.n 8000938 <__libc_init_array+0xc>
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800095a: f856 3025 ldr.w r3, [r6, r5, lsl #2]
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|
800095e: 4798 blx r3
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|
8000960: 3501 adds r5, #1
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8000962: e7f2 b.n 800094a <__libc_init_array+0x1e>
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8000964: 080009cc .word 0x080009cc
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8000968: 080009cc .word 0x080009cc
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800096c: 080009cc .word 0x080009cc
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|
8000970: 080009d0 .word 0x080009d0
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|
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|
08000974 <_init>:
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|
8000974: b5f8 push {r3, r4, r5, r6, r7, lr}
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|
8000976: bf00 nop
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|
8000978: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800097a: bc08 pop {r3}
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|
800097c: 469e mov lr, r3
|
|
800097e: 4770 bx lr
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|
|
|
08000980 <_fini>:
|
|
8000980: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8000982: bf00 nop
|
|
8000984: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8000986: bc08 pop {r3}
|
|
8000988: 469e mov lr, r3
|
|
800098a: 4770 bx lr
|