2407 lines
82 KiB
Text
2407 lines
82 KiB
Text
|
|
RealOne.elf: file format elf32-littlearm
|
|
|
|
Sections:
|
|
Idx Name Size VMA LMA File off Algn
|
|
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
1 .text 00000ca8 08000188 08000188 00010188 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
|
2 .rodata 00000000 08000e30 08000e30 00020010 2**0
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
3 .ARM.extab 00000000 08000e30 08000e30 00020010 2**0
|
|
CONTENTS
|
|
4 .ARM 00000000 08000e30 08000e30 00020010 2**0
|
|
CONTENTS
|
|
5 .preinit_array 00000000 08000e30 08000e30 00020010 2**0
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
6 .init_array 00000004 08000e30 08000e30 00010e30 2**2
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
7 .fini_array 00000004 08000e34 08000e34 00010e34 2**2
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
8 .data 00000010 20000000 08000e38 00020000 2**2
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
9 .bss 00000024 20000010 08000e48 00020010 2**2
|
|
ALLOC
|
|
10 ._user_heap_stack 00000604 20000034 08000e48 00020034 2**0
|
|
ALLOC
|
|
11 .ARM.attributes 00000030 00000000 00000000 00020010 2**0
|
|
CONTENTS, READONLY
|
|
12 .debug_info 00004920 00000000 00000000 00020040 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
13 .debug_abbrev 00000d51 00000000 00000000 00024960 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
14 .debug_aranges 000005b8 00000000 00000000 000256b8 2**3
|
|
CONTENTS, READONLY, DEBUGGING
|
|
15 .debug_ranges 00000540 00000000 00000000 00025c70 2**3
|
|
CONTENTS, READONLY, DEBUGGING
|
|
16 .debug_macro 00026337 00000000 00000000 000261b0 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
17 .debug_line 000040e6 00000000 00000000 0004c4e7 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
18 .debug_str 000ee792 00000000 00000000 000505cd 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
19 .comment 0000007b 00000000 00000000 0013ed5f 2**0
|
|
CONTENTS, READONLY
|
|
20 .debug_frame 000015c0 00000000 00000000 0013eddc 2**2
|
|
CONTENTS, READONLY, DEBUGGING
|
|
|
|
Disassembly of section .text:
|
|
|
|
08000188 <__do_global_dtors_aux>:
|
|
8000188: b510 push {r4, lr}
|
|
800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
|
|
800018c: 7823 ldrb r3, [r4, #0]
|
|
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
|
|
8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
|
|
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
|
|
8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
|
|
8000196: f3af 8000 nop.w
|
|
800019a: 2301 movs r3, #1
|
|
800019c: 7023 strb r3, [r4, #0]
|
|
800019e: bd10 pop {r4, pc}
|
|
80001a0: 20000010 .word 0x20000010
|
|
80001a4: 00000000 .word 0x00000000
|
|
80001a8: 08000e18 .word 0x08000e18
|
|
|
|
080001ac <frame_dummy>:
|
|
80001ac: b508 push {r3, lr}
|
|
80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
|
|
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
|
|
80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
|
|
80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
|
|
80001b6: f3af 8000 nop.w
|
|
80001ba: bd08 pop {r3, pc}
|
|
80001bc: 00000000 .word 0x00000000
|
|
80001c0: 20000014 .word 0x20000014
|
|
80001c4: 08000e18 .word 0x08000e18
|
|
|
|
080001c8 <LL_AHB2_GRP1_EnableClock>:
|
|
*
|
|
* (*) value not defined in all devices.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
80001c8: b480 push {r7}
|
|
80001ca: b085 sub sp, #20
|
|
80001cc: af00 add r7, sp, #0
|
|
80001ce: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->AHB2ENR, Periphs);
|
|
80001d0: 4b08 ldr r3, [pc, #32] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
|
|
80001d2: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
80001d4: 4907 ldr r1, [pc, #28] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
|
|
80001d6: 687b ldr r3, [r7, #4]
|
|
80001d8: 4313 orrs r3, r2
|
|
80001da: 64cb str r3, [r1, #76] ; 0x4c
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
|
|
80001dc: 4b05 ldr r3, [pc, #20] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
|
|
80001de: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
80001e0: 687b ldr r3, [r7, #4]
|
|
80001e2: 4013 ands r3, r2
|
|
80001e4: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
80001e6: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80001e8: bf00 nop
|
|
80001ea: 3714 adds r7, #20
|
|
80001ec: 46bd mov sp, r7
|
|
80001ee: f85d 7b04 ldr.w r7, [sp], #4
|
|
80001f2: 4770 bx lr
|
|
80001f4: 40021000 .word 0x40021000
|
|
|
|
080001f8 <LL_GPIO_SetPinMode>:
|
|
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
|
* @arg @ref LL_GPIO_MODE_ANALOG
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
|
|
{
|
|
80001f8: b480 push {r7}
|
|
80001fa: b08b sub sp, #44 ; 0x2c
|
|
80001fc: af00 add r7, sp, #0
|
|
80001fe: 60f8 str r0, [r7, #12]
|
|
8000200: 60b9 str r1, [r7, #8]
|
|
8000202: 607a str r2, [r7, #4]
|
|
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
|
|
8000204: 68fb ldr r3, [r7, #12]
|
|
8000206: 681a ldr r2, [r3, #0]
|
|
8000208: 68bb ldr r3, [r7, #8]
|
|
800020a: 617b str r3, [r7, #20]
|
|
uint32_t result;
|
|
|
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
|
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
|
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800020c: 697b ldr r3, [r7, #20]
|
|
800020e: fa93 f3a3 rbit r3, r3
|
|
8000212: 613b str r3, [r7, #16]
|
|
result |= value & 1U;
|
|
s--;
|
|
}
|
|
result <<= s; /* shift when v's highest bits are zero */
|
|
#endif
|
|
return result;
|
|
8000214: 693b ldr r3, [r7, #16]
|
|
8000216: 61bb str r3, [r7, #24]
|
|
optimisations using the logic "value was passed to __builtin_clz, so it
|
|
is non-zero".
|
|
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
|
|
single CLZ instruction.
|
|
*/
|
|
if (value == 0U)
|
|
8000218: 69bb ldr r3, [r7, #24]
|
|
800021a: 2b00 cmp r3, #0
|
|
800021c: d101 bne.n 8000222 <LL_GPIO_SetPinMode+0x2a>
|
|
{
|
|
return 32U;
|
|
800021e: 2320 movs r3, #32
|
|
8000220: e003 b.n 800022a <LL_GPIO_SetPinMode+0x32>
|
|
}
|
|
return __builtin_clz(value);
|
|
8000222: 69bb ldr r3, [r7, #24]
|
|
8000224: fab3 f383 clz r3, r3
|
|
8000228: b2db uxtb r3, r3
|
|
800022a: 005b lsls r3, r3, #1
|
|
800022c: 2103 movs r1, #3
|
|
800022e: fa01 f303 lsl.w r3, r1, r3
|
|
8000232: 43db mvns r3, r3
|
|
8000234: 401a ands r2, r3
|
|
8000236: 68bb ldr r3, [r7, #8]
|
|
8000238: 623b str r3, [r7, #32]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800023a: 6a3b ldr r3, [r7, #32]
|
|
800023c: fa93 f3a3 rbit r3, r3
|
|
8000240: 61fb str r3, [r7, #28]
|
|
return result;
|
|
8000242: 69fb ldr r3, [r7, #28]
|
|
8000244: 627b str r3, [r7, #36] ; 0x24
|
|
if (value == 0U)
|
|
8000246: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000248: 2b00 cmp r3, #0
|
|
800024a: d101 bne.n 8000250 <LL_GPIO_SetPinMode+0x58>
|
|
return 32U;
|
|
800024c: 2320 movs r3, #32
|
|
800024e: e003 b.n 8000258 <LL_GPIO_SetPinMode+0x60>
|
|
return __builtin_clz(value);
|
|
8000250: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000252: fab3 f383 clz r3, r3
|
|
8000256: b2db uxtb r3, r3
|
|
8000258: 005b lsls r3, r3, #1
|
|
800025a: 6879 ldr r1, [r7, #4]
|
|
800025c: fa01 f303 lsl.w r3, r1, r3
|
|
8000260: 431a orrs r2, r3
|
|
8000262: 68fb ldr r3, [r7, #12]
|
|
8000264: 601a str r2, [r3, #0]
|
|
}
|
|
8000266: bf00 nop
|
|
8000268: 372c adds r7, #44 ; 0x2c
|
|
800026a: 46bd mov sp, r7
|
|
800026c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000270: 4770 bx lr
|
|
|
|
08000272 <LL_GPIO_SetPinOutputType>:
|
|
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
|
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
|
|
{
|
|
8000272: b480 push {r7}
|
|
8000274: b085 sub sp, #20
|
|
8000276: af00 add r7, sp, #0
|
|
8000278: 60f8 str r0, [r7, #12]
|
|
800027a: 60b9 str r1, [r7, #8]
|
|
800027c: 607a str r2, [r7, #4]
|
|
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
|
|
800027e: 68fb ldr r3, [r7, #12]
|
|
8000280: 685a ldr r2, [r3, #4]
|
|
8000282: 68bb ldr r3, [r7, #8]
|
|
8000284: 43db mvns r3, r3
|
|
8000286: 401a ands r2, r3
|
|
8000288: 68bb ldr r3, [r7, #8]
|
|
800028a: 6879 ldr r1, [r7, #4]
|
|
800028c: fb01 f303 mul.w r3, r1, r3
|
|
8000290: 431a orrs r2, r3
|
|
8000292: 68fb ldr r3, [r7, #12]
|
|
8000294: 605a str r2, [r3, #4]
|
|
}
|
|
8000296: bf00 nop
|
|
8000298: 3714 adds r7, #20
|
|
800029a: 46bd mov sp, r7
|
|
800029c: f85d 7b04 ldr.w r7, [sp], #4
|
|
80002a0: 4770 bx lr
|
|
|
|
080002a2 <LL_GPIO_IsInputPinSet>:
|
|
* @arg @ref LL_GPIO_PIN_15
|
|
* @arg @ref LL_GPIO_PIN_ALL
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
|
{
|
|
80002a2: b480 push {r7}
|
|
80002a4: b083 sub sp, #12
|
|
80002a6: af00 add r7, sp, #0
|
|
80002a8: 6078 str r0, [r7, #4]
|
|
80002aa: 6039 str r1, [r7, #0]
|
|
return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
|
|
80002ac: 687b ldr r3, [r7, #4]
|
|
80002ae: 691a ldr r2, [r3, #16]
|
|
80002b0: 683b ldr r3, [r7, #0]
|
|
80002b2: 4013 ands r3, r2
|
|
80002b4: 683a ldr r2, [r7, #0]
|
|
80002b6: 429a cmp r2, r3
|
|
80002b8: d101 bne.n 80002be <LL_GPIO_IsInputPinSet+0x1c>
|
|
80002ba: 2301 movs r3, #1
|
|
80002bc: e000 b.n 80002c0 <LL_GPIO_IsInputPinSet+0x1e>
|
|
80002be: 2300 movs r3, #0
|
|
}
|
|
80002c0: 4618 mov r0, r3
|
|
80002c2: 370c adds r7, #12
|
|
80002c4: 46bd mov sp, r7
|
|
80002c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80002ca: 4770 bx lr
|
|
|
|
080002cc <LL_GPIO_SetOutputPin>:
|
|
* @arg @ref LL_GPIO_PIN_15
|
|
* @arg @ref LL_GPIO_PIN_ALL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
|
{
|
|
80002cc: b480 push {r7}
|
|
80002ce: b083 sub sp, #12
|
|
80002d0: af00 add r7, sp, #0
|
|
80002d2: 6078 str r0, [r7, #4]
|
|
80002d4: 6039 str r1, [r7, #0]
|
|
WRITE_REG(GPIOx->BSRR, PinMask);
|
|
80002d6: 687b ldr r3, [r7, #4]
|
|
80002d8: 683a ldr r2, [r7, #0]
|
|
80002da: 619a str r2, [r3, #24]
|
|
}
|
|
80002dc: bf00 nop
|
|
80002de: 370c adds r7, #12
|
|
80002e0: 46bd mov sp, r7
|
|
80002e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80002e6: 4770 bx lr
|
|
|
|
080002e8 <LL_GPIO_ResetOutputPin>:
|
|
* @arg @ref LL_GPIO_PIN_15
|
|
* @arg @ref LL_GPIO_PIN_ALL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
|
{
|
|
80002e8: b480 push {r7}
|
|
80002ea: b083 sub sp, #12
|
|
80002ec: af00 add r7, sp, #0
|
|
80002ee: 6078 str r0, [r7, #4]
|
|
80002f0: 6039 str r1, [r7, #0]
|
|
WRITE_REG(GPIOx->BRR, PinMask);
|
|
80002f2: 687b ldr r3, [r7, #4]
|
|
80002f4: 683a ldr r2, [r7, #0]
|
|
80002f6: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
80002f8: bf00 nop
|
|
80002fa: 370c adds r7, #12
|
|
80002fc: 46bd mov sp, r7
|
|
80002fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000302: 4770 bx lr
|
|
|
|
08000304 <LL_GPIO_TogglePin>:
|
|
* @arg @ref LL_GPIO_PIN_15
|
|
* @arg @ref LL_GPIO_PIN_ALL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
|
{
|
|
8000304: b480 push {r7}
|
|
8000306: b085 sub sp, #20
|
|
8000308: af00 add r7, sp, #0
|
|
800030a: 6078 str r0, [r7, #4]
|
|
800030c: 6039 str r1, [r7, #0]
|
|
uint32_t odr = READ_REG(GPIOx->ODR);
|
|
800030e: 687b ldr r3, [r7, #4]
|
|
8000310: 695b ldr r3, [r3, #20]
|
|
8000312: 60fb str r3, [r7, #12]
|
|
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
|
|
8000314: 68fa ldr r2, [r7, #12]
|
|
8000316: 683b ldr r3, [r7, #0]
|
|
8000318: 4013 ands r3, r2
|
|
800031a: 041a lsls r2, r3, #16
|
|
800031c: 68fb ldr r3, [r7, #12]
|
|
800031e: 43d9 mvns r1, r3
|
|
8000320: 683b ldr r3, [r7, #0]
|
|
8000322: 400b ands r3, r1
|
|
8000324: 431a orrs r2, r3
|
|
8000326: 687b ldr r3, [r7, #4]
|
|
8000328: 619a str r2, [r3, #24]
|
|
}
|
|
800032a: bf00 nop
|
|
800032c: 3714 adds r7, #20
|
|
800032e: 46bd mov sp, r7
|
|
8000330: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000334: 4770 bx lr
|
|
...
|
|
|
|
08000338 <GPIO_init>:
|
|
#define BUT_PORT GPIOC
|
|
#define BUT_PIN LL_GPIO_PIN_13
|
|
#define CLK_PIN LL_GPIO_PIN_10
|
|
|
|
void GPIO_init(void)
|
|
{
|
|
8000338: b580 push {r7, lr}
|
|
800033a: af00 add r7, sp, #0
|
|
// PORT A
|
|
LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA );
|
|
800033c: 2001 movs r0, #1
|
|
800033e: f7ff ff43 bl 80001c8 <LL_AHB2_GRP1_EnableClock>
|
|
// Green LED (user LED) - PA5
|
|
LL_GPIO_SetPinMode( LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT );
|
|
8000342: 2201 movs r2, #1
|
|
8000344: 2120 movs r1, #32
|
|
8000346: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
800034a: f7ff ff55 bl 80001f8 <LL_GPIO_SetPinMode>
|
|
LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL );
|
|
800034e: 2200 movs r2, #0
|
|
8000350: 2120 movs r1, #32
|
|
8000352: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
8000356: f7ff ff8c bl 8000272 <LL_GPIO_SetPinOutputType>
|
|
|
|
// PORT C
|
|
LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC );
|
|
800035a: 2004 movs r0, #4
|
|
800035c: f7ff ff34 bl 80001c8 <LL_AHB2_GRP1_EnableClock>
|
|
// Blue button - PC13
|
|
LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT );
|
|
8000360: 2200 movs r2, #0
|
|
8000362: f44f 5100 mov.w r1, #8192 ; 0x2000
|
|
8000366: 4805 ldr r0, [pc, #20] ; (800037c <GPIO_init+0x44>)
|
|
8000368: f7ff ff46 bl 80001f8 <LL_GPIO_SetPinMode>
|
|
LL_GPIO_SetPinMode( BUT_PORT, CLK_PIN, LL_GPIO_MODE_OUTPUT );
|
|
800036c: 2201 movs r2, #1
|
|
800036e: f44f 6180 mov.w r1, #1024 ; 0x400
|
|
8000372: 4802 ldr r0, [pc, #8] ; (800037c <GPIO_init+0x44>)
|
|
8000374: f7ff ff40 bl 80001f8 <LL_GPIO_SetPinMode>
|
|
}
|
|
8000378: bf00 nop
|
|
800037a: bd80 pop {r7, pc}
|
|
800037c: 48000800 .word 0x48000800
|
|
|
|
08000380 <CLK_TOGGLE>:
|
|
|
|
void CLK_TOGGLE(){
|
|
8000380: b580 push {r7, lr}
|
|
8000382: af00 add r7, sp, #0
|
|
LL_GPIO_TogglePin(BUT_PORT, CLK_PIN);
|
|
8000384: f44f 6180 mov.w r1, #1024 ; 0x400
|
|
8000388: 4802 ldr r0, [pc, #8] ; (8000394 <CLK_TOGGLE+0x14>)
|
|
800038a: f7ff ffbb bl 8000304 <LL_GPIO_TogglePin>
|
|
}
|
|
800038e: bf00 nop
|
|
8000390: bd80 pop {r7, pc}
|
|
8000392: bf00 nop
|
|
8000394: 48000800 .word 0x48000800
|
|
|
|
08000398 <LED_GREEN>:
|
|
|
|
void LED_GREEN( int val )
|
|
{
|
|
8000398: b580 push {r7, lr}
|
|
800039a: b082 sub sp, #8
|
|
800039c: af00 add r7, sp, #0
|
|
800039e: 6078 str r0, [r7, #4]
|
|
if ( val )
|
|
80003a0: 687b ldr r3, [r7, #4]
|
|
80003a2: 2b00 cmp r3, #0
|
|
80003a4: d005 beq.n 80003b2 <LED_GREEN+0x1a>
|
|
LL_GPIO_SetOutputPin( LED_PORT, LED_PIN );
|
|
80003a6: 2120 movs r1, #32
|
|
80003a8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80003ac: f7ff ff8e bl 80002cc <LL_GPIO_SetOutputPin>
|
|
else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
|
|
}
|
|
80003b0: e004 b.n 80003bc <LED_GREEN+0x24>
|
|
else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
|
|
80003b2: 2120 movs r1, #32
|
|
80003b4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80003b8: f7ff ff96 bl 80002e8 <LL_GPIO_ResetOutputPin>
|
|
}
|
|
80003bc: bf00 nop
|
|
80003be: 3708 adds r7, #8
|
|
80003c0: 46bd mov sp, r7
|
|
80003c2: bd80 pop {r7, pc}
|
|
|
|
080003c4 <BLUE_BUTTON>:
|
|
|
|
int BLUE_BUTTON()
|
|
{
|
|
80003c4: b580 push {r7, lr}
|
|
80003c6: af00 add r7, sp, #0
|
|
return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) );
|
|
80003c8: f44f 5100 mov.w r1, #8192 ; 0x2000
|
|
80003cc: 4805 ldr r0, [pc, #20] ; (80003e4 <BLUE_BUTTON+0x20>)
|
|
80003ce: f7ff ff68 bl 80002a2 <LL_GPIO_IsInputPinSet>
|
|
80003d2: 4603 mov r3, r0
|
|
80003d4: 2b00 cmp r3, #0
|
|
80003d6: bf0c ite eq
|
|
80003d8: 2301 moveq r3, #1
|
|
80003da: 2300 movne r3, #0
|
|
80003dc: b2db uxtb r3, r3
|
|
}
|
|
80003de: 4618 mov r0, r3
|
|
80003e0: bd80 pop {r7, pc}
|
|
80003e2: bf00 nop
|
|
80003e4: 48000800 .word 0x48000800
|
|
|
|
080003e8 <LL_RCC_LSE_Enable>:
|
|
* @brief Enable Low Speed External (LSE) crystal.
|
|
* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
|
|
{
|
|
80003e8: b480 push {r7}
|
|
80003ea: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
80003ec: 4b06 ldr r3, [pc, #24] ; (8000408 <LL_RCC_LSE_Enable+0x20>)
|
|
80003ee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
80003f2: 4a05 ldr r2, [pc, #20] ; (8000408 <LL_RCC_LSE_Enable+0x20>)
|
|
80003f4: f043 0301 orr.w r3, r3, #1
|
|
80003f8: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
}
|
|
80003fc: bf00 nop
|
|
80003fe: 46bd mov sp, r7
|
|
8000400: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000404: 4770 bx lr
|
|
8000406: bf00 nop
|
|
8000408: 40021000 .word 0x40021000
|
|
|
|
0800040c <LL_RCC_LSE_SetDriveCapability>:
|
|
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
|
|
* @arg @ref LL_RCC_LSEDRIVE_HIGH
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
|
|
{
|
|
800040c: b480 push {r7}
|
|
800040e: b083 sub sp, #12
|
|
8000410: af00 add r7, sp, #0
|
|
8000412: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
|
|
8000414: 4b07 ldr r3, [pc, #28] ; (8000434 <LL_RCC_LSE_SetDriveCapability+0x28>)
|
|
8000416: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800041a: f023 0218 bic.w r2, r3, #24
|
|
800041e: 4905 ldr r1, [pc, #20] ; (8000434 <LL_RCC_LSE_SetDriveCapability+0x28>)
|
|
8000420: 687b ldr r3, [r7, #4]
|
|
8000422: 4313 orrs r3, r2
|
|
8000424: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
8000428: bf00 nop
|
|
800042a: 370c adds r7, #12
|
|
800042c: 46bd mov sp, r7
|
|
800042e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000432: 4770 bx lr
|
|
8000434: 40021000 .word 0x40021000
|
|
|
|
08000438 <LL_RCC_LSE_IsReady>:
|
|
* @brief Check if LSE oscillator Ready
|
|
* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
|
|
{
|
|
8000438: b480 push {r7}
|
|
800043a: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
|
|
800043c: 4b07 ldr r3, [pc, #28] ; (800045c <LL_RCC_LSE_IsReady+0x24>)
|
|
800043e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8000442: f003 0302 and.w r3, r3, #2
|
|
8000446: 2b02 cmp r3, #2
|
|
8000448: d101 bne.n 800044e <LL_RCC_LSE_IsReady+0x16>
|
|
800044a: 2301 movs r3, #1
|
|
800044c: e000 b.n 8000450 <LL_RCC_LSE_IsReady+0x18>
|
|
800044e: 2300 movs r3, #0
|
|
}
|
|
8000450: 4618 mov r0, r3
|
|
8000452: 46bd mov sp, r7
|
|
8000454: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000458: 4770 bx lr
|
|
800045a: bf00 nop
|
|
800045c: 40021000 .word 0x40021000
|
|
|
|
08000460 <LL_RCC_MSI_Enable>:
|
|
* @brief Enable MSI oscillator
|
|
* @rmtoll CR MSION LL_RCC_MSI_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
|
|
{
|
|
8000460: b480 push {r7}
|
|
8000462: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSION);
|
|
8000464: 4b05 ldr r3, [pc, #20] ; (800047c <LL_RCC_MSI_Enable+0x1c>)
|
|
8000466: 681b ldr r3, [r3, #0]
|
|
8000468: 4a04 ldr r2, [pc, #16] ; (800047c <LL_RCC_MSI_Enable+0x1c>)
|
|
800046a: f043 0301 orr.w r3, r3, #1
|
|
800046e: 6013 str r3, [r2, #0]
|
|
}
|
|
8000470: bf00 nop
|
|
8000472: 46bd mov sp, r7
|
|
8000474: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000478: 4770 bx lr
|
|
800047a: bf00 nop
|
|
800047c: 40021000 .word 0x40021000
|
|
|
|
08000480 <LL_RCC_MSI_IsReady>:
|
|
* @brief Check if MSI oscillator Ready
|
|
* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
|
|
{
|
|
8000480: b480 push {r7}
|
|
8000482: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
|
|
8000484: 4b06 ldr r3, [pc, #24] ; (80004a0 <LL_RCC_MSI_IsReady+0x20>)
|
|
8000486: 681b ldr r3, [r3, #0]
|
|
8000488: f003 0302 and.w r3, r3, #2
|
|
800048c: 2b02 cmp r3, #2
|
|
800048e: d101 bne.n 8000494 <LL_RCC_MSI_IsReady+0x14>
|
|
8000490: 2301 movs r3, #1
|
|
8000492: e000 b.n 8000496 <LL_RCC_MSI_IsReady+0x16>
|
|
8000494: 2300 movs r3, #0
|
|
}
|
|
8000496: 4618 mov r0, r3
|
|
8000498: 46bd mov sp, r7
|
|
800049a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800049e: 4770 bx lr
|
|
80004a0: 40021000 .word 0x40021000
|
|
|
|
080004a4 <LL_RCC_MSI_EnablePLLMode>:
|
|
* ready
|
|
* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
|
|
{
|
|
80004a4: b480 push {r7}
|
|
80004a6: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
|
|
80004a8: 4b05 ldr r3, [pc, #20] ; (80004c0 <LL_RCC_MSI_EnablePLLMode+0x1c>)
|
|
80004aa: 681b ldr r3, [r3, #0]
|
|
80004ac: 4a04 ldr r2, [pc, #16] ; (80004c0 <LL_RCC_MSI_EnablePLLMode+0x1c>)
|
|
80004ae: f043 0304 orr.w r3, r3, #4
|
|
80004b2: 6013 str r3, [r2, #0]
|
|
}
|
|
80004b4: bf00 nop
|
|
80004b6: 46bd mov sp, r7
|
|
80004b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80004bc: 4770 bx lr
|
|
80004be: bf00 nop
|
|
80004c0: 40021000 .word 0x40021000
|
|
|
|
080004c4 <LL_RCC_MSI_EnableRangeSelection>:
|
|
* MSISRANGE
|
|
* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
|
|
{
|
|
80004c4: b480 push {r7}
|
|
80004c6: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
|
|
80004c8: 4b05 ldr r3, [pc, #20] ; (80004e0 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
|
|
80004ca: 681b ldr r3, [r3, #0]
|
|
80004cc: 4a04 ldr r2, [pc, #16] ; (80004e0 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
|
|
80004ce: f043 0308 orr.w r3, r3, #8
|
|
80004d2: 6013 str r3, [r2, #0]
|
|
}
|
|
80004d4: bf00 nop
|
|
80004d6: 46bd mov sp, r7
|
|
80004d8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80004dc: 4770 bx lr
|
|
80004de: bf00 nop
|
|
80004e0: 40021000 .word 0x40021000
|
|
|
|
080004e4 <LL_RCC_MSI_SetRange>:
|
|
* @arg @ref LL_RCC_MSIRANGE_10
|
|
* @arg @ref LL_RCC_MSIRANGE_11
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
|
|
{
|
|
80004e4: b480 push {r7}
|
|
80004e6: b083 sub sp, #12
|
|
80004e8: af00 add r7, sp, #0
|
|
80004ea: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
|
|
80004ec: 4b06 ldr r3, [pc, #24] ; (8000508 <LL_RCC_MSI_SetRange+0x24>)
|
|
80004ee: 681b ldr r3, [r3, #0]
|
|
80004f0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
80004f4: 4904 ldr r1, [pc, #16] ; (8000508 <LL_RCC_MSI_SetRange+0x24>)
|
|
80004f6: 687b ldr r3, [r7, #4]
|
|
80004f8: 4313 orrs r3, r2
|
|
80004fa: 600b str r3, [r1, #0]
|
|
}
|
|
80004fc: bf00 nop
|
|
80004fe: 370c adds r7, #12
|
|
8000500: 46bd mov sp, r7
|
|
8000502: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000506: 4770 bx lr
|
|
8000508: 40021000 .word 0x40021000
|
|
|
|
0800050c <LL_RCC_MSI_SetCalibTrimming>:
|
|
* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
|
|
* @param Value Between Min_Data = 0 and Max_Data = 255
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
|
|
{
|
|
800050c: b480 push {r7}
|
|
800050e: b083 sub sp, #12
|
|
8000510: af00 add r7, sp, #0
|
|
8000512: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
|
|
8000514: 4b07 ldr r3, [pc, #28] ; (8000534 <LL_RCC_MSI_SetCalibTrimming+0x28>)
|
|
8000516: 685b ldr r3, [r3, #4]
|
|
8000518: f423 427f bic.w r2, r3, #65280 ; 0xff00
|
|
800051c: 687b ldr r3, [r7, #4]
|
|
800051e: 021b lsls r3, r3, #8
|
|
8000520: 4904 ldr r1, [pc, #16] ; (8000534 <LL_RCC_MSI_SetCalibTrimming+0x28>)
|
|
8000522: 4313 orrs r3, r2
|
|
8000524: 604b str r3, [r1, #4]
|
|
}
|
|
8000526: bf00 nop
|
|
8000528: 370c adds r7, #12
|
|
800052a: 46bd mov sp, r7
|
|
800052c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000530: 4770 bx lr
|
|
8000532: bf00 nop
|
|
8000534: 40021000 .word 0x40021000
|
|
|
|
08000538 <LL_RCC_SetSysClkSource>:
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
|
|
{
|
|
8000538: b480 push {r7}
|
|
800053a: b083 sub sp, #12
|
|
800053c: af00 add r7, sp, #0
|
|
800053e: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
|
|
8000540: 4b06 ldr r3, [pc, #24] ; (800055c <LL_RCC_SetSysClkSource+0x24>)
|
|
8000542: 689b ldr r3, [r3, #8]
|
|
8000544: f023 0203 bic.w r2, r3, #3
|
|
8000548: 4904 ldr r1, [pc, #16] ; (800055c <LL_RCC_SetSysClkSource+0x24>)
|
|
800054a: 687b ldr r3, [r7, #4]
|
|
800054c: 4313 orrs r3, r2
|
|
800054e: 608b str r3, [r1, #8]
|
|
}
|
|
8000550: bf00 nop
|
|
8000552: 370c adds r7, #12
|
|
8000554: 46bd mov sp, r7
|
|
8000556: f85d 7b04 ldr.w r7, [sp], #4
|
|
800055a: 4770 bx lr
|
|
800055c: 40021000 .word 0x40021000
|
|
|
|
08000560 <LL_RCC_GetSysClkSource>:
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
|
|
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
|
|
{
|
|
8000560: b480 push {r7}
|
|
8000562: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
|
|
8000564: 4b04 ldr r3, [pc, #16] ; (8000578 <LL_RCC_GetSysClkSource+0x18>)
|
|
8000566: 689b ldr r3, [r3, #8]
|
|
8000568: f003 030c and.w r3, r3, #12
|
|
}
|
|
800056c: 4618 mov r0, r3
|
|
800056e: 46bd mov sp, r7
|
|
8000570: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000574: 4770 bx lr
|
|
8000576: bf00 nop
|
|
8000578: 40021000 .word 0x40021000
|
|
|
|
0800057c <LL_RCC_SetAHBPrescaler>:
|
|
* @arg @ref LL_RCC_SYSCLK_DIV_256
|
|
* @arg @ref LL_RCC_SYSCLK_DIV_512
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
|
|
{
|
|
800057c: b480 push {r7}
|
|
800057e: b083 sub sp, #12
|
|
8000580: af00 add r7, sp, #0
|
|
8000582: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
|
|
8000584: 4b06 ldr r3, [pc, #24] ; (80005a0 <LL_RCC_SetAHBPrescaler+0x24>)
|
|
8000586: 689b ldr r3, [r3, #8]
|
|
8000588: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
800058c: 4904 ldr r1, [pc, #16] ; (80005a0 <LL_RCC_SetAHBPrescaler+0x24>)
|
|
800058e: 687b ldr r3, [r7, #4]
|
|
8000590: 4313 orrs r3, r2
|
|
8000592: 608b str r3, [r1, #8]
|
|
}
|
|
8000594: bf00 nop
|
|
8000596: 370c adds r7, #12
|
|
8000598: 46bd mov sp, r7
|
|
800059a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800059e: 4770 bx lr
|
|
80005a0: 40021000 .word 0x40021000
|
|
|
|
080005a4 <LL_RCC_SetAPB1Prescaler>:
|
|
* @arg @ref LL_RCC_APB1_DIV_8
|
|
* @arg @ref LL_RCC_APB1_DIV_16
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
|
|
{
|
|
80005a4: b480 push {r7}
|
|
80005a6: b083 sub sp, #12
|
|
80005a8: af00 add r7, sp, #0
|
|
80005aa: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
|
|
80005ac: 4b06 ldr r3, [pc, #24] ; (80005c8 <LL_RCC_SetAPB1Prescaler+0x24>)
|
|
80005ae: 689b ldr r3, [r3, #8]
|
|
80005b0: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
80005b4: 4904 ldr r1, [pc, #16] ; (80005c8 <LL_RCC_SetAPB1Prescaler+0x24>)
|
|
80005b6: 687b ldr r3, [r7, #4]
|
|
80005b8: 4313 orrs r3, r2
|
|
80005ba: 608b str r3, [r1, #8]
|
|
}
|
|
80005bc: bf00 nop
|
|
80005be: 370c adds r7, #12
|
|
80005c0: 46bd mov sp, r7
|
|
80005c2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80005c6: 4770 bx lr
|
|
80005c8: 40021000 .word 0x40021000
|
|
|
|
080005cc <LL_RCC_SetAPB2Prescaler>:
|
|
* @arg @ref LL_RCC_APB2_DIV_8
|
|
* @arg @ref LL_RCC_APB2_DIV_16
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
|
|
{
|
|
80005cc: b480 push {r7}
|
|
80005ce: b083 sub sp, #12
|
|
80005d0: af00 add r7, sp, #0
|
|
80005d2: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
|
|
80005d4: 4b06 ldr r3, [pc, #24] ; (80005f0 <LL_RCC_SetAPB2Prescaler+0x24>)
|
|
80005d6: 689b ldr r3, [r3, #8]
|
|
80005d8: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
80005dc: 4904 ldr r1, [pc, #16] ; (80005f0 <LL_RCC_SetAPB2Prescaler+0x24>)
|
|
80005de: 687b ldr r3, [r7, #4]
|
|
80005e0: 4313 orrs r3, r2
|
|
80005e2: 608b str r3, [r1, #8]
|
|
}
|
|
80005e4: bf00 nop
|
|
80005e6: 370c adds r7, #12
|
|
80005e8: 46bd mov sp, r7
|
|
80005ea: f85d 7b04 ldr.w r7, [sp], #4
|
|
80005ee: 4770 bx lr
|
|
80005f0: 40021000 .word 0x40021000
|
|
|
|
080005f4 <LL_RCC_SetRTCClockSource>:
|
|
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
|
|
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
|
|
{
|
|
80005f4: b480 push {r7}
|
|
80005f6: b083 sub sp, #12
|
|
80005f8: af00 add r7, sp, #0
|
|
80005fa: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
|
|
80005fc: 4b07 ldr r3, [pc, #28] ; (800061c <LL_RCC_SetRTCClockSource+0x28>)
|
|
80005fe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8000602: f423 7240 bic.w r2, r3, #768 ; 0x300
|
|
8000606: 4905 ldr r1, [pc, #20] ; (800061c <LL_RCC_SetRTCClockSource+0x28>)
|
|
8000608: 687b ldr r3, [r7, #4]
|
|
800060a: 4313 orrs r3, r2
|
|
800060c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
8000610: bf00 nop
|
|
8000612: 370c adds r7, #12
|
|
8000614: 46bd mov sp, r7
|
|
8000616: f85d 7b04 ldr.w r7, [sp], #4
|
|
800061a: 4770 bx lr
|
|
800061c: 40021000 .word 0x40021000
|
|
|
|
08000620 <LL_RCC_EnableRTC>:
|
|
* @brief Enable RTC
|
|
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_EnableRTC(void)
|
|
{
|
|
8000620: b480 push {r7}
|
|
8000622: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
|
|
8000624: 4b06 ldr r3, [pc, #24] ; (8000640 <LL_RCC_EnableRTC+0x20>)
|
|
8000626: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800062a: 4a05 ldr r2, [pc, #20] ; (8000640 <LL_RCC_EnableRTC+0x20>)
|
|
800062c: f443 4300 orr.w r3, r3, #32768 ; 0x8000
|
|
8000630: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
}
|
|
8000634: bf00 nop
|
|
8000636: 46bd mov sp, r7
|
|
8000638: f85d 7b04 ldr.w r7, [sp], #4
|
|
800063c: 4770 bx lr
|
|
800063e: bf00 nop
|
|
8000640: 40021000 .word 0x40021000
|
|
|
|
08000644 <LL_RCC_ForceBackupDomainReset>:
|
|
* @brief Force the Backup domain reset
|
|
* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
|
|
{
|
|
8000644: b480 push {r7}
|
|
8000646: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
|
|
8000648: 4b06 ldr r3, [pc, #24] ; (8000664 <LL_RCC_ForceBackupDomainReset+0x20>)
|
|
800064a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800064e: 4a05 ldr r2, [pc, #20] ; (8000664 <LL_RCC_ForceBackupDomainReset+0x20>)
|
|
8000650: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8000654: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
}
|
|
8000658: bf00 nop
|
|
800065a: 46bd mov sp, r7
|
|
800065c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000660: 4770 bx lr
|
|
8000662: bf00 nop
|
|
8000664: 40021000 .word 0x40021000
|
|
|
|
08000668 <LL_RCC_ReleaseBackupDomainReset>:
|
|
* @brief Release the Backup domain reset
|
|
* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
|
|
{
|
|
8000668: b480 push {r7}
|
|
800066a: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
|
|
800066c: 4b06 ldr r3, [pc, #24] ; (8000688 <LL_RCC_ReleaseBackupDomainReset+0x20>)
|
|
800066e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8000672: 4a05 ldr r2, [pc, #20] ; (8000688 <LL_RCC_ReleaseBackupDomainReset+0x20>)
|
|
8000674: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8000678: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
}
|
|
800067c: bf00 nop
|
|
800067e: 46bd mov sp, r7
|
|
8000680: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000684: 4770 bx lr
|
|
8000686: bf00 nop
|
|
8000688: 40021000 .word 0x40021000
|
|
|
|
0800068c <LL_RCC_PLL_Enable>:
|
|
* @brief Enable PLL
|
|
* @rmtoll CR PLLON LL_RCC_PLL_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
|
|
{
|
|
800068c: b480 push {r7}
|
|
800068e: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_PLLON);
|
|
8000690: 4b05 ldr r3, [pc, #20] ; (80006a8 <LL_RCC_PLL_Enable+0x1c>)
|
|
8000692: 681b ldr r3, [r3, #0]
|
|
8000694: 4a04 ldr r2, [pc, #16] ; (80006a8 <LL_RCC_PLL_Enable+0x1c>)
|
|
8000696: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
800069a: 6013 str r3, [r2, #0]
|
|
}
|
|
800069c: bf00 nop
|
|
800069e: 46bd mov sp, r7
|
|
80006a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80006a4: 4770 bx lr
|
|
80006a6: bf00 nop
|
|
80006a8: 40021000 .word 0x40021000
|
|
|
|
080006ac <LL_RCC_PLL_IsReady>:
|
|
* @brief Check if PLL Ready
|
|
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
|
|
{
|
|
80006ac: b480 push {r7}
|
|
80006ae: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
|
|
80006b0: 4b07 ldr r3, [pc, #28] ; (80006d0 <LL_RCC_PLL_IsReady+0x24>)
|
|
80006b2: 681b ldr r3, [r3, #0]
|
|
80006b4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80006b8: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
|
|
80006bc: d101 bne.n 80006c2 <LL_RCC_PLL_IsReady+0x16>
|
|
80006be: 2301 movs r3, #1
|
|
80006c0: e000 b.n 80006c4 <LL_RCC_PLL_IsReady+0x18>
|
|
80006c2: 2300 movs r3, #0
|
|
}
|
|
80006c4: 4618 mov r0, r3
|
|
80006c6: 46bd mov sp, r7
|
|
80006c8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80006cc: 4770 bx lr
|
|
80006ce: bf00 nop
|
|
80006d0: 40021000 .word 0x40021000
|
|
|
|
080006d4 <LL_RCC_PLL_ConfigDomain_SYS>:
|
|
* @arg @ref LL_RCC_PLLR_DIV_6
|
|
* @arg @ref LL_RCC_PLLR_DIV_8
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
|
|
{
|
|
80006d4: b480 push {r7}
|
|
80006d6: b085 sub sp, #20
|
|
80006d8: af00 add r7, sp, #0
|
|
80006da: 60f8 str r0, [r7, #12]
|
|
80006dc: 60b9 str r1, [r7, #8]
|
|
80006de: 607a str r2, [r7, #4]
|
|
80006e0: 603b str r3, [r7, #0]
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
|
|
80006e2: 4b0a ldr r3, [pc, #40] ; (800070c <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
|
|
80006e4: 68da ldr r2, [r3, #12]
|
|
80006e6: 4b0a ldr r3, [pc, #40] ; (8000710 <LL_RCC_PLL_ConfigDomain_SYS+0x3c>)
|
|
80006e8: 4013 ands r3, r2
|
|
80006ea: 68f9 ldr r1, [r7, #12]
|
|
80006ec: 68ba ldr r2, [r7, #8]
|
|
80006ee: 4311 orrs r1, r2
|
|
80006f0: 687a ldr r2, [r7, #4]
|
|
80006f2: 0212 lsls r2, r2, #8
|
|
80006f4: 4311 orrs r1, r2
|
|
80006f6: 683a ldr r2, [r7, #0]
|
|
80006f8: 430a orrs r2, r1
|
|
80006fa: 4904 ldr r1, [pc, #16] ; (800070c <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
|
|
80006fc: 4313 orrs r3, r2
|
|
80006fe: 60cb str r3, [r1, #12]
|
|
Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
|
|
}
|
|
8000700: bf00 nop
|
|
8000702: 3714 adds r7, #20
|
|
8000704: 46bd mov sp, r7
|
|
8000706: f85d 7b04 ldr.w r7, [sp], #4
|
|
800070a: 4770 bx lr
|
|
800070c: 40021000 .word 0x40021000
|
|
8000710: f9ff808c .word 0xf9ff808c
|
|
|
|
08000714 <LL_RCC_PLL_EnableDomain_SYS>:
|
|
* @brief Enable PLL output mapped on SYSCLK domain
|
|
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
|
|
{
|
|
8000714: b480 push {r7}
|
|
8000716: af00 add r7, sp, #0
|
|
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
|
|
8000718: 4b05 ldr r3, [pc, #20] ; (8000730 <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
|
|
800071a: 68db ldr r3, [r3, #12]
|
|
800071c: 4a04 ldr r2, [pc, #16] ; (8000730 <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
|
|
800071e: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
8000722: 60d3 str r3, [r2, #12]
|
|
}
|
|
8000724: bf00 nop
|
|
8000726: 46bd mov sp, r7
|
|
8000728: f85d 7b04 ldr.w r7, [sp], #4
|
|
800072c: 4770 bx lr
|
|
800072e: bf00 nop
|
|
8000730: 40021000 .word 0x40021000
|
|
|
|
08000734 <LL_APB1_GRP1_EnableClock>:
|
|
*
|
|
* (*) value not defined in all devices.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
8000734: b480 push {r7}
|
|
8000736: b085 sub sp, #20
|
|
8000738: af00 add r7, sp, #0
|
|
800073a: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APB1ENR1, Periphs);
|
|
800073c: 4b08 ldr r3, [pc, #32] ; (8000760 <LL_APB1_GRP1_EnableClock+0x2c>)
|
|
800073e: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8000740: 4907 ldr r1, [pc, #28] ; (8000760 <LL_APB1_GRP1_EnableClock+0x2c>)
|
|
8000742: 687b ldr r3, [r7, #4]
|
|
8000744: 4313 orrs r3, r2
|
|
8000746: 658b str r3, [r1, #88] ; 0x58
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
|
|
8000748: 4b05 ldr r3, [pc, #20] ; (8000760 <LL_APB1_GRP1_EnableClock+0x2c>)
|
|
800074a: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
800074c: 687b ldr r3, [r7, #4]
|
|
800074e: 4013 ands r3, r2
|
|
8000750: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8000752: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000754: bf00 nop
|
|
8000756: 3714 adds r7, #20
|
|
8000758: 46bd mov sp, r7
|
|
800075a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800075e: 4770 bx lr
|
|
8000760: 40021000 .word 0x40021000
|
|
|
|
08000764 <LL_FLASH_SetLatency>:
|
|
*
|
|
* (*) value not defined in all devices.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
|
|
{
|
|
8000764: b480 push {r7}
|
|
8000766: b083 sub sp, #12
|
|
8000768: af00 add r7, sp, #0
|
|
800076a: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
|
|
800076c: 4b06 ldr r3, [pc, #24] ; (8000788 <LL_FLASH_SetLatency+0x24>)
|
|
800076e: 681b ldr r3, [r3, #0]
|
|
8000770: f023 0207 bic.w r2, r3, #7
|
|
8000774: 4904 ldr r1, [pc, #16] ; (8000788 <LL_FLASH_SetLatency+0x24>)
|
|
8000776: 687b ldr r3, [r7, #4]
|
|
8000778: 4313 orrs r3, r2
|
|
800077a: 600b str r3, [r1, #0]
|
|
}
|
|
800077c: bf00 nop
|
|
800077e: 370c adds r7, #12
|
|
8000780: 46bd mov sp, r7
|
|
8000782: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000786: 4770 bx lr
|
|
8000788: 40022000 .word 0x40022000
|
|
|
|
0800078c <LL_FLASH_GetLatency>:
|
|
* @arg @ref LL_FLASH_LATENCY_15 (*)
|
|
*
|
|
* (*) value not defined in all devices.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
|
|
{
|
|
800078c: b480 push {r7}
|
|
800078e: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
|
|
8000790: 4b04 ldr r3, [pc, #16] ; (80007a4 <LL_FLASH_GetLatency+0x18>)
|
|
8000792: 681b ldr r3, [r3, #0]
|
|
8000794: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8000798: 4618 mov r0, r3
|
|
800079a: 46bd mov sp, r7
|
|
800079c: f85d 7b04 ldr.w r7, [sp], #4
|
|
80007a0: 4770 bx lr
|
|
80007a2: bf00 nop
|
|
80007a4: 40022000 .word 0x40022000
|
|
|
|
080007a8 <LL_SYSTICK_EnableIT>:
|
|
* @brief Enable SysTick exception request
|
|
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
|
|
{
|
|
80007a8: b480 push {r7}
|
|
80007aa: af00 add r7, sp, #0
|
|
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
|
80007ac: 4b05 ldr r3, [pc, #20] ; (80007c4 <LL_SYSTICK_EnableIT+0x1c>)
|
|
80007ae: 681b ldr r3, [r3, #0]
|
|
80007b0: 4a04 ldr r2, [pc, #16] ; (80007c4 <LL_SYSTICK_EnableIT+0x1c>)
|
|
80007b2: f043 0302 orr.w r3, r3, #2
|
|
80007b6: 6013 str r3, [r2, #0]
|
|
}
|
|
80007b8: bf00 nop
|
|
80007ba: 46bd mov sp, r7
|
|
80007bc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80007c0: 4770 bx lr
|
|
80007c2: bf00 nop
|
|
80007c4: e000e010 .word 0xe000e010
|
|
|
|
080007c8 <LL_LPM_EnableSleep>:
|
|
* @brief Processor uses sleep as its low power mode
|
|
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_LPM_EnableSleep(void)
|
|
{
|
|
80007c8: b480 push {r7}
|
|
80007ca: af00 add r7, sp, #0
|
|
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
80007cc: 4b05 ldr r3, [pc, #20] ; (80007e4 <LL_LPM_EnableSleep+0x1c>)
|
|
80007ce: 691b ldr r3, [r3, #16]
|
|
80007d0: 4a04 ldr r2, [pc, #16] ; (80007e4 <LL_LPM_EnableSleep+0x1c>)
|
|
80007d2: f023 0304 bic.w r3, r3, #4
|
|
80007d6: 6113 str r3, [r2, #16]
|
|
}
|
|
80007d8: bf00 nop
|
|
80007da: 46bd mov sp, r7
|
|
80007dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80007e0: 4770 bx lr
|
|
80007e2: bf00 nop
|
|
80007e4: e000ed00 .word 0xe000ed00
|
|
|
|
080007e8 <LL_PWR_SetRegulVoltageScaling>:
|
|
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
|
|
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
80007e8: b480 push {r7}
|
|
80007ea: b083 sub sp, #12
|
|
80007ec: af00 add r7, sp, #0
|
|
80007ee: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
|
|
80007f0: 4b06 ldr r3, [pc, #24] ; (800080c <LL_PWR_SetRegulVoltageScaling+0x24>)
|
|
80007f2: 681b ldr r3, [r3, #0]
|
|
80007f4: f423 62c0 bic.w r2, r3, #1536 ; 0x600
|
|
80007f8: 4904 ldr r1, [pc, #16] ; (800080c <LL_PWR_SetRegulVoltageScaling+0x24>)
|
|
80007fa: 687b ldr r3, [r7, #4]
|
|
80007fc: 4313 orrs r3, r2
|
|
80007fe: 600b str r3, [r1, #0]
|
|
}
|
|
8000800: bf00 nop
|
|
8000802: 370c adds r7, #12
|
|
8000804: 46bd mov sp, r7
|
|
8000806: f85d 7b04 ldr.w r7, [sp], #4
|
|
800080a: 4770 bx lr
|
|
800080c: 40007000 .word 0x40007000
|
|
|
|
08000810 <LL_PWR_EnableBkUpAccess>:
|
|
* @brief Enable access to the backup domain
|
|
* @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
|
|
{
|
|
8000810: b480 push {r7}
|
|
8000812: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8000814: 4b05 ldr r3, [pc, #20] ; (800082c <LL_PWR_EnableBkUpAccess+0x1c>)
|
|
8000816: 681b ldr r3, [r3, #0]
|
|
8000818: 4a04 ldr r2, [pc, #16] ; (800082c <LL_PWR_EnableBkUpAccess+0x1c>)
|
|
800081a: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
800081e: 6013 str r3, [r2, #0]
|
|
}
|
|
8000820: bf00 nop
|
|
8000822: 46bd mov sp, r7
|
|
8000824: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000828: 4770 bx lr
|
|
800082a: bf00 nop
|
|
800082c: 40007000 .word 0x40007000
|
|
|
|
08000830 <SysTick_Handler>:
|
|
volatile uint32_t msTicks = 0;
|
|
volatile uint8_t expe = 2;
|
|
volatile uint8_t blue_mode = 0;
|
|
|
|
void SysTick_Handler()
|
|
{
|
|
8000830: b580 push {r7, lr}
|
|
8000832: af00 add r7, sp, #0
|
|
if ( BLUE_BUTTON() ){
|
|
8000834: f7ff fdc6 bl 80003c4 <BLUE_BUTTON>
|
|
8000838: 4603 mov r3, r0
|
|
800083a: 2b00 cmp r3, #0
|
|
800083c: d002 beq.n 8000844 <SysTick_Handler+0x14>
|
|
blue_mode = 1 ;
|
|
800083e: 4b15 ldr r3, [pc, #84] ; (8000894 <SysTick_Handler+0x64>)
|
|
8000840: 2201 movs r2, #1
|
|
8000842: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
|
|
8000844: 4b14 ldr r3, [pc, #80] ; (8000898 <SysTick_Handler+0x68>)
|
|
8000846: 681b ldr r3, [r3, #0]
|
|
8000848: 3301 adds r3, #1
|
|
800084a: 4a13 ldr r2, [pc, #76] ; (8000898 <SysTick_Handler+0x68>)
|
|
800084c: 6013 str r3, [r2, #0]
|
|
if (msTicks == 5 * expe){
|
|
800084e: 4b13 ldr r3, [pc, #76] ; (800089c <SysTick_Handler+0x6c>)
|
|
8000850: 781b ldrb r3, [r3, #0]
|
|
8000852: b2db uxtb r3, r3
|
|
8000854: 461a mov r2, r3
|
|
8000856: 4613 mov r3, r2
|
|
8000858: 009b lsls r3, r3, #2
|
|
800085a: 4413 add r3, r2
|
|
800085c: 461a mov r2, r3
|
|
800085e: 4b0e ldr r3, [pc, #56] ; (8000898 <SysTick_Handler+0x68>)
|
|
8000860: 681b ldr r3, [r3, #0]
|
|
8000862: 429a cmp r2, r3
|
|
8000864: d103 bne.n 800086e <SysTick_Handler+0x3e>
|
|
LED_GREEN(0);
|
|
8000866: 2000 movs r0, #0
|
|
8000868: f7ff fd96 bl 8000398 <LED_GREEN>
|
|
800086c: e009 b.n 8000882 <SysTick_Handler+0x52>
|
|
}else if(msTicks >= 200){
|
|
800086e: 4b0a ldr r3, [pc, #40] ; (8000898 <SysTick_Handler+0x68>)
|
|
8000870: 681b ldr r3, [r3, #0]
|
|
8000872: 2bc7 cmp r3, #199 ; 0xc7
|
|
8000874: d905 bls.n 8000882 <SysTick_Handler+0x52>
|
|
msTicks = 0;
|
|
8000876: 4b08 ldr r3, [pc, #32] ; (8000898 <SysTick_Handler+0x68>)
|
|
8000878: 2200 movs r2, #0
|
|
800087a: 601a str r2, [r3, #0]
|
|
LED_GREEN(1);
|
|
800087c: 2001 movs r0, #1
|
|
800087e: f7ff fd8b bl 8000398 <LED_GREEN>
|
|
}
|
|
if(expe == 2){
|
|
8000882: 4b06 ldr r3, [pc, #24] ; (800089c <SysTick_Handler+0x6c>)
|
|
8000884: 781b ldrb r3, [r3, #0]
|
|
8000886: b2db uxtb r3, r3
|
|
8000888: 2b02 cmp r3, #2
|
|
800088a: d101 bne.n 8000890 <SysTick_Handler+0x60>
|
|
CLK_TOGGLE();
|
|
800088c: f7ff fd78 bl 8000380 <CLK_TOGGLE>
|
|
}
|
|
}
|
|
8000890: bf00 nop
|
|
8000892: bd80 pop {r7, pc}
|
|
8000894: 20000030 .word 0x20000030
|
|
8000898: 2000002c .word 0x2000002c
|
|
800089c: 20000000 .word 0x20000000
|
|
|
|
080008a0 <main>:
|
|
|
|
|
|
|
|
|
|
int main(void)
|
|
{
|
|
80008a0: b580 push {r7, lr}
|
|
80008a2: af00 add r7, sp, #0
|
|
// LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
|
|
// LL_PWR_EnableBkUpAccess();
|
|
// RTC->BKP0R = expe;
|
|
// }
|
|
// LL_PWR_DisableBkUpAccess();
|
|
switch(expe){
|
|
80008a4: 4b15 ldr r3, [pc, #84] ; (80008fc <main+0x5c>)
|
|
80008a6: 781b ldrb r3, [r3, #0]
|
|
80008a8: b2db uxtb r3, r3
|
|
80008aa: 2b01 cmp r3, #1
|
|
80008ac: d002 beq.n 80008b4 <main+0x14>
|
|
80008ae: 2b02 cmp r3, #2
|
|
80008b0: d003 beq.n 80008ba <main+0x1a>
|
|
80008b2: e005 b.n 80008c0 <main+0x20>
|
|
case 1:
|
|
/* Configure the system clock */
|
|
SystemClock_Config_80M();
|
|
80008b4: f000 f890 bl 80009d8 <SystemClock_Config_80M>
|
|
break;
|
|
80008b8: e002 b.n 80008c0 <main+0x20>
|
|
case 2:
|
|
/* Configure the system clock */
|
|
SystemClock_Config_24M_LSE();
|
|
80008ba: f000 f825 bl 8000908 <SystemClock_Config_24M_LSE>
|
|
break;
|
|
80008be: bf00 nop
|
|
|
|
|
|
|
|
|
|
// config GPIO
|
|
GPIO_init();
|
|
80008c0: f7ff fd3a bl 8000338 <GPIO_init>
|
|
|
|
// init systick timer (tick period at 1 ms)
|
|
LL_Init1msTick( SystemCoreClock );
|
|
80008c4: 4b0e ldr r3, [pc, #56] ; (8000900 <main+0x60>)
|
|
80008c6: 681b ldr r3, [r3, #0]
|
|
80008c8: 4618 mov r0, r3
|
|
80008ca: f000 fa65 bl 8000d98 <LL_Init1msTick>
|
|
LL_SYSTICK_EnableIT();
|
|
80008ce: f7ff ff6b bl 80007a8 <LL_SYSTICK_EnableIT>
|
|
|
|
//Setup Sleep mode
|
|
LL_LPM_EnableSleep();
|
|
80008d2: f7ff ff79 bl 80007c8 <LL_LPM_EnableSleep>
|
|
//LL_LPM_EnableSleepOnExit();
|
|
|
|
while (1) {
|
|
if (blue_mode){
|
|
80008d6: 4b0b ldr r3, [pc, #44] ; (8000904 <main+0x64>)
|
|
80008d8: 781b ldrb r3, [r3, #0]
|
|
80008da: b2db uxtb r3, r3
|
|
80008dc: 2b00 cmp r3, #0
|
|
80008de: d0fa beq.n 80008d6 <main+0x36>
|
|
switch(expe){
|
|
80008e0: 4b06 ldr r3, [pc, #24] ; (80008fc <main+0x5c>)
|
|
80008e2: 781b ldrb r3, [r3, #0]
|
|
80008e4: b2db uxtb r3, r3
|
|
80008e6: 2b01 cmp r3, #1
|
|
80008e8: d002 beq.n 80008f0 <main+0x50>
|
|
80008ea: 2b02 cmp r3, #2
|
|
80008ec: d002 beq.n 80008f4 <main+0x54>
|
|
80008ee: e004 b.n 80008fa <main+0x5a>
|
|
case 1:
|
|
__WFI();
|
|
80008f0: bf30 wfi
|
|
break;
|
|
80008f2: e002 b.n 80008fa <main+0x5a>
|
|
case 2:
|
|
LL_RCC_MSI_EnablePLLMode();
|
|
80008f4: f7ff fdd6 bl 80004a4 <LL_RCC_MSI_EnablePLLMode>
|
|
break;
|
|
80008f8: bf00 nop
|
|
if (blue_mode){
|
|
80008fa: e7ec b.n 80008d6 <main+0x36>
|
|
80008fc: 20000000 .word 0x20000000
|
|
8000900: 20000004 .word 0x20000004
|
|
8000904: 20000030 .word 0x20000030
|
|
|
|
08000908 <SystemClock_Config_24M_LSE>:
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
* 24Mhz + RTC + LSE
|
|
*/
|
|
void SystemClock_Config_24M_LSE(void)
|
|
{
|
|
8000908: b580 push {r7, lr}
|
|
800090a: af00 add r7, sp, #0
|
|
LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
|
|
800090c: f04f 5080 mov.w r0, #268435456 ; 0x10000000
|
|
8000910: f7ff ff10 bl 8000734 <LL_APB1_GRP1_EnableClock>
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
|
|
8000914: 2001 movs r0, #1
|
|
8000916: f7ff ff25 bl 8000764 <LL_FLASH_SetLatency>
|
|
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_1)
|
|
800091a: bf00 nop
|
|
800091c: f7ff ff36 bl 800078c <LL_FLASH_GetLatency>
|
|
8000920: 4603 mov r3, r0
|
|
8000922: 2b01 cmp r3, #1
|
|
8000924: d1fa bne.n 800091c <SystemClock_Config_24M_LSE+0x14>
|
|
{
|
|
}
|
|
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
|
|
8000926: f44f 7000 mov.w r0, #512 ; 0x200
|
|
800092a: f7ff ff5d bl 80007e8 <LL_PWR_SetRegulVoltageScaling>
|
|
LL_RCC_MSI_Enable();
|
|
800092e: f7ff fd97 bl 8000460 <LL_RCC_MSI_Enable>
|
|
|
|
/* Wait till MSI is ready */
|
|
while(LL_RCC_MSI_IsReady() != 1)
|
|
8000932: bf00 nop
|
|
8000934: f7ff fda4 bl 8000480 <LL_RCC_MSI_IsReady>
|
|
8000938: 4603 mov r3, r0
|
|
800093a: 2b01 cmp r3, #1
|
|
800093c: d1fa bne.n 8000934 <SystemClock_Config_24M_LSE+0x2c>
|
|
{
|
|
|
|
}
|
|
|
|
LL_PWR_EnableBkUpAccess();
|
|
800093e: f7ff ff67 bl 8000810 <LL_PWR_EnableBkUpAccess>
|
|
LL_RCC_ForceBackupDomainReset();
|
|
8000942: f7ff fe7f bl 8000644 <LL_RCC_ForceBackupDomainReset>
|
|
LL_RCC_ReleaseBackupDomainReset();
|
|
8000946: f7ff fe8f bl 8000668 <LL_RCC_ReleaseBackupDomainReset>
|
|
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW);
|
|
800094a: 2000 movs r0, #0
|
|
800094c: f7ff fd5e bl 800040c <LL_RCC_LSE_SetDriveCapability>
|
|
|
|
LL_RCC_MSI_EnableRangeSelection();
|
|
8000950: f7ff fdb8 bl 80004c4 <LL_RCC_MSI_EnableRangeSelection>
|
|
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
|
|
8000954: 2060 movs r0, #96 ; 0x60
|
|
8000956: f7ff fdc5 bl 80004e4 <LL_RCC_MSI_SetRange>
|
|
LL_RCC_MSI_SetCalibTrimming(0);
|
|
800095a: 2000 movs r0, #0
|
|
800095c: f7ff fdd6 bl 800050c <LL_RCC_MSI_SetCalibTrimming>
|
|
// LL_RCC_MSI_EnablePLLMode();
|
|
|
|
LL_RCC_LSE_Enable();
|
|
8000960: f7ff fd42 bl 80003e8 <LL_RCC_LSE_Enable>
|
|
|
|
/* Wait till LSE is ready */
|
|
while(LL_RCC_LSE_IsReady() != 1)
|
|
8000964: bf00 nop
|
|
8000966: f7ff fd67 bl 8000438 <LL_RCC_LSE_IsReady>
|
|
800096a: 4603 mov r3, r0
|
|
800096c: 2b01 cmp r3, #1
|
|
800096e: d1fa bne.n 8000966 <SystemClock_Config_24M_LSE+0x5e>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
|
|
8000970: f44f 7080 mov.w r0, #256 ; 0x100
|
|
8000974: f7ff fe3e bl 80005f4 <LL_RCC_SetRTCClockSource>
|
|
LL_RCC_EnableRTC();
|
|
8000978: f7ff fe52 bl 8000620 <LL_RCC_EnableRTC>
|
|
|
|
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 24, LL_RCC_PLLR_DIV_4);
|
|
800097c: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8000980: 2218 movs r2, #24
|
|
8000982: 2100 movs r1, #0
|
|
8000984: 2001 movs r0, #1
|
|
8000986: f7ff fea5 bl 80006d4 <LL_RCC_PLL_ConfigDomain_SYS>
|
|
LL_RCC_PLL_EnableDomain_SYS();
|
|
800098a: f7ff fec3 bl 8000714 <LL_RCC_PLL_EnableDomain_SYS>
|
|
LL_RCC_PLL_Enable();
|
|
800098e: f7ff fe7d bl 800068c <LL_RCC_PLL_Enable>
|
|
|
|
/* Wait till PLL is ready */
|
|
while(LL_RCC_PLL_IsReady() != 1)
|
|
8000992: bf00 nop
|
|
8000994: f7ff fe8a bl 80006ac <LL_RCC_PLL_IsReady>
|
|
8000998: 4603 mov r3, r0
|
|
800099a: 2b01 cmp r3, #1
|
|
800099c: d1fa bne.n 8000994 <SystemClock_Config_24M_LSE+0x8c>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
800099e: 2003 movs r0, #3
|
|
80009a0: f7ff fdca bl 8000538 <LL_RCC_SetSysClkSource>
|
|
|
|
/* Wait till System clock is ready */
|
|
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
|
80009a4: bf00 nop
|
|
80009a6: f7ff fddb bl 8000560 <LL_RCC_GetSysClkSource>
|
|
80009aa: 4603 mov r3, r0
|
|
80009ac: 2b0c cmp r3, #12
|
|
80009ae: d1fa bne.n 80009a6 <SystemClock_Config_24M_LSE+0x9e>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
80009b0: 2000 movs r0, #0
|
|
80009b2: f7ff fde3 bl 800057c <LL_RCC_SetAHBPrescaler>
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
|
|
80009b6: 2000 movs r0, #0
|
|
80009b8: f7ff fdf4 bl 80005a4 <LL_RCC_SetAPB1Prescaler>
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
|
80009bc: 2000 movs r0, #0
|
|
80009be: f7ff fe05 bl 80005cc <LL_RCC_SetAPB2Prescaler>
|
|
LL_SetSystemCoreClock(24000000);
|
|
80009c2: 4804 ldr r0, [pc, #16] ; (80009d4 <SystemClock_Config_24M_LSE+0xcc>)
|
|
80009c4: f000 f9f4 bl 8000db0 <LL_SetSystemCoreClock>
|
|
|
|
/* Update the time base */
|
|
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
|
|
80009c8: 2000 movs r0, #0
|
|
80009ca: f000 f8d9 bl 8000b80 <HAL_InitTick>
|
|
{
|
|
// Error_Handler();
|
|
}
|
|
}
|
|
80009ce: bf00 nop
|
|
80009d0: bd80 pop {r7, pc}
|
|
80009d2: bf00 nop
|
|
80009d4: 016e3600 .word 0x016e3600
|
|
|
|
080009d8 <SystemClock_Config_80M>:
|
|
|
|
|
|
void SystemClock_Config_80M(void)
|
|
{
|
|
80009d8: b580 push {r7, lr}
|
|
80009da: af00 add r7, sp, #0
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
|
|
80009dc: 2004 movs r0, #4
|
|
80009de: f7ff fec1 bl 8000764 <LL_FLASH_SetLatency>
|
|
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4)
|
|
80009e2: bf00 nop
|
|
80009e4: f7ff fed2 bl 800078c <LL_FLASH_GetLatency>
|
|
80009e8: 4603 mov r3, r0
|
|
80009ea: 2b04 cmp r3, #4
|
|
80009ec: d1fa bne.n 80009e4 <SystemClock_Config_80M+0xc>
|
|
{
|
|
}
|
|
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
|
|
80009ee: f44f 7000 mov.w r0, #512 ; 0x200
|
|
80009f2: f7ff fef9 bl 80007e8 <LL_PWR_SetRegulVoltageScaling>
|
|
LL_RCC_MSI_Enable();
|
|
80009f6: f7ff fd33 bl 8000460 <LL_RCC_MSI_Enable>
|
|
|
|
/* Wait till MSI is ready */
|
|
while(LL_RCC_MSI_IsReady() != 1)
|
|
80009fa: bf00 nop
|
|
80009fc: f7ff fd40 bl 8000480 <LL_RCC_MSI_IsReady>
|
|
8000a00: 4603 mov r3, r0
|
|
8000a02: 2b01 cmp r3, #1
|
|
8000a04: d1fa bne.n 80009fc <SystemClock_Config_80M+0x24>
|
|
{
|
|
|
|
}
|
|
LL_RCC_MSI_EnableRangeSelection();
|
|
8000a06: f7ff fd5d bl 80004c4 <LL_RCC_MSI_EnableRangeSelection>
|
|
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
|
|
8000a0a: 2060 movs r0, #96 ; 0x60
|
|
8000a0c: f7ff fd6a bl 80004e4 <LL_RCC_MSI_SetRange>
|
|
LL_RCC_MSI_SetCalibTrimming(0);
|
|
8000a10: 2000 movs r0, #0
|
|
8000a12: f7ff fd7b bl 800050c <LL_RCC_MSI_SetCalibTrimming>
|
|
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);
|
|
8000a16: 2300 movs r3, #0
|
|
8000a18: 2228 movs r2, #40 ; 0x28
|
|
8000a1a: 2100 movs r1, #0
|
|
8000a1c: 2001 movs r0, #1
|
|
8000a1e: f7ff fe59 bl 80006d4 <LL_RCC_PLL_ConfigDomain_SYS>
|
|
LL_RCC_PLL_EnableDomain_SYS();
|
|
8000a22: f7ff fe77 bl 8000714 <LL_RCC_PLL_EnableDomain_SYS>
|
|
LL_RCC_PLL_Enable();
|
|
8000a26: f7ff fe31 bl 800068c <LL_RCC_PLL_Enable>
|
|
|
|
/* Wait till PLL is ready */
|
|
while(LL_RCC_PLL_IsReady() != 1)
|
|
8000a2a: bf00 nop
|
|
8000a2c: f7ff fe3e bl 80006ac <LL_RCC_PLL_IsReady>
|
|
8000a30: 4603 mov r3, r0
|
|
8000a32: 2b01 cmp r3, #1
|
|
8000a34: d1fa bne.n 8000a2c <SystemClock_Config_80M+0x54>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
8000a36: 2003 movs r0, #3
|
|
8000a38: f7ff fd7e bl 8000538 <LL_RCC_SetSysClkSource>
|
|
|
|
/* Wait till System clock is ready */
|
|
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
|
8000a3c: bf00 nop
|
|
8000a3e: f7ff fd8f bl 8000560 <LL_RCC_GetSysClkSource>
|
|
8000a42: 4603 mov r3, r0
|
|
8000a44: 2b0c cmp r3, #12
|
|
8000a46: d1fa bne.n 8000a3e <SystemClock_Config_80M+0x66>
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
8000a48: 2000 movs r0, #0
|
|
8000a4a: f7ff fd97 bl 800057c <LL_RCC_SetAHBPrescaler>
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
|
|
8000a4e: 2000 movs r0, #0
|
|
8000a50: f7ff fda8 bl 80005a4 <LL_RCC_SetAPB1Prescaler>
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
|
8000a54: 2000 movs r0, #0
|
|
8000a56: f7ff fdb9 bl 80005cc <LL_RCC_SetAPB2Prescaler>
|
|
LL_SetSystemCoreClock(80000000);
|
|
8000a5a: 4804 ldr r0, [pc, #16] ; (8000a6c <SystemClock_Config_80M+0x94>)
|
|
8000a5c: f000 f9a8 bl 8000db0 <LL_SetSystemCoreClock>
|
|
|
|
/* Update the time base */
|
|
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
|
|
8000a60: 2000 movs r0, #0
|
|
8000a62: f000 f88d bl 8000b80 <HAL_InitTick>
|
|
{
|
|
// Error_Handler();
|
|
}
|
|
}
|
|
8000a66: bf00 nop
|
|
8000a68: bd80 pop {r7, pc}
|
|
8000a6a: bf00 nop
|
|
8000a6c: 04c4b400 .word 0x04c4b400
|
|
|
|
08000a70 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000a70: b480 push {r7}
|
|
8000a72: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 1 */
|
|
}
|
|
8000a74: bf00 nop
|
|
8000a76: 46bd mov sp, r7
|
|
8000a78: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000a7c: 4770 bx lr
|
|
|
|
08000a7e <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8000a7e: b480 push {r7}
|
|
8000a80: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8000a82: e7fe b.n 8000a82 <HardFault_Handler+0x4>
|
|
|
|
08000a84 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8000a84: b480 push {r7}
|
|
8000a86: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8000a88: e7fe b.n 8000a88 <MemManage_Handler+0x4>
|
|
|
|
08000a8a <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8000a8a: b480 push {r7}
|
|
8000a8c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8000a8e: e7fe b.n 8000a8e <BusFault_Handler+0x4>
|
|
|
|
08000a90 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000a90: b480 push {r7}
|
|
8000a92: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000a94: e7fe b.n 8000a94 <UsageFault_Handler+0x4>
|
|
|
|
08000a96 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8000a96: b480 push {r7}
|
|
8000a98: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8000a9a: bf00 nop
|
|
8000a9c: 46bd mov sp, r7
|
|
8000a9e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000aa2: 4770 bx lr
|
|
|
|
08000aa4 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000aa4: b480 push {r7}
|
|
8000aa6: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8000aa8: bf00 nop
|
|
8000aaa: 46bd mov sp, r7
|
|
8000aac: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000ab0: 4770 bx lr
|
|
|
|
08000ab2 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000ab2: b480 push {r7}
|
|
8000ab4: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8000ab6: bf00 nop
|
|
8000ab8: 46bd mov sp, r7
|
|
8000aba: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000abe: 4770 bx lr
|
|
|
|
08000ac0 <SystemInit>:
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
8000ac0: b480 push {r7}
|
|
8000ac2: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
8000ac4: 4b17 ldr r3, [pc, #92] ; (8000b24 <SystemInit+0x64>)
|
|
8000ac6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8000aca: 4a16 ldr r2, [pc, #88] ; (8000b24 <SystemInit+0x64>)
|
|
8000acc: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
|
8000ad0: f8c2 3088 str.w r3, [r2, #136] ; 0x88
|
|
#endif
|
|
|
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
|
/* Set MSION bit */
|
|
RCC->CR |= RCC_CR_MSION;
|
|
8000ad4: 4b14 ldr r3, [pc, #80] ; (8000b28 <SystemInit+0x68>)
|
|
8000ad6: 681b ldr r3, [r3, #0]
|
|
8000ad8: 4a13 ldr r2, [pc, #76] ; (8000b28 <SystemInit+0x68>)
|
|
8000ada: f043 0301 orr.w r3, r3, #1
|
|
8000ade: 6013 str r3, [r2, #0]
|
|
|
|
/* Reset CFGR register */
|
|
RCC->CFGR = 0x00000000U;
|
|
8000ae0: 4b11 ldr r3, [pc, #68] ; (8000b28 <SystemInit+0x68>)
|
|
8000ae2: 2200 movs r2, #0
|
|
8000ae4: 609a str r2, [r3, #8]
|
|
|
|
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
|
RCC->CR &= 0xEAF6FFFFU;
|
|
8000ae6: 4b10 ldr r3, [pc, #64] ; (8000b28 <SystemInit+0x68>)
|
|
8000ae8: 681b ldr r3, [r3, #0]
|
|
8000aea: 4a0f ldr r2, [pc, #60] ; (8000b28 <SystemInit+0x68>)
|
|
8000aec: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
|
|
8000af0: f423 2310 bic.w r3, r3, #589824 ; 0x90000
|
|
8000af4: 6013 str r3, [r2, #0]
|
|
|
|
/* Reset PLLCFGR register */
|
|
RCC->PLLCFGR = 0x00001000U;
|
|
8000af6: 4b0c ldr r3, [pc, #48] ; (8000b28 <SystemInit+0x68>)
|
|
8000af8: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
8000afc: 60da str r2, [r3, #12]
|
|
|
|
/* Reset HSEBYP bit */
|
|
RCC->CR &= 0xFFFBFFFFU;
|
|
8000afe: 4b0a ldr r3, [pc, #40] ; (8000b28 <SystemInit+0x68>)
|
|
8000b00: 681b ldr r3, [r3, #0]
|
|
8000b02: 4a09 ldr r2, [pc, #36] ; (8000b28 <SystemInit+0x68>)
|
|
8000b04: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8000b08: 6013 str r3, [r2, #0]
|
|
|
|
/* Disable all interrupts */
|
|
RCC->CIER = 0x00000000U;
|
|
8000b0a: 4b07 ldr r3, [pc, #28] ; (8000b28 <SystemInit+0x68>)
|
|
8000b0c: 2200 movs r2, #0
|
|
8000b0e: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
|
#ifdef VECT_TAB_SRAM
|
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#else
|
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
|
8000b10: 4b04 ldr r3, [pc, #16] ; (8000b24 <SystemInit+0x64>)
|
|
8000b12: f04f 6200 mov.w r2, #134217728 ; 0x8000000
|
|
8000b16: 609a str r2, [r3, #8]
|
|
#endif
|
|
}
|
|
8000b18: bf00 nop
|
|
8000b1a: 46bd mov sp, r7
|
|
8000b1c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b20: 4770 bx lr
|
|
8000b22: bf00 nop
|
|
8000b24: e000ed00 .word 0xe000ed00
|
|
8000b28: 40021000 .word 0x40021000
|
|
|
|
08000b2c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8000b2c: f8df d034 ldr.w sp, [pc, #52] ; 8000b64 <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8000b30: f7ff ffc6 bl 8000ac0 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
movs r1, #0
|
|
8000b34: 2100 movs r1, #0
|
|
b LoopCopyDataInit
|
|
8000b36: e003 b.n 8000b40 <LoopCopyDataInit>
|
|
|
|
08000b38 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r3, =_sidata
|
|
8000b38: 4b0b ldr r3, [pc, #44] ; (8000b68 <LoopForever+0x6>)
|
|
ldr r3, [r3, r1]
|
|
8000b3a: 585b ldr r3, [r3, r1]
|
|
str r3, [r0, r1]
|
|
8000b3c: 5043 str r3, [r0, r1]
|
|
adds r1, r1, #4
|
|
8000b3e: 3104 adds r1, #4
|
|
|
|
08000b40 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
ldr r0, =_sdata
|
|
8000b40: 480a ldr r0, [pc, #40] ; (8000b6c <LoopForever+0xa>)
|
|
ldr r3, =_edata
|
|
8000b42: 4b0b ldr r3, [pc, #44] ; (8000b70 <LoopForever+0xe>)
|
|
adds r2, r0, r1
|
|
8000b44: 1842 adds r2, r0, r1
|
|
cmp r2, r3
|
|
8000b46: 429a cmp r2, r3
|
|
bcc CopyDataInit
|
|
8000b48: d3f6 bcc.n 8000b38 <CopyDataInit>
|
|
ldr r2, =_sbss
|
|
8000b4a: 4a0a ldr r2, [pc, #40] ; (8000b74 <LoopForever+0x12>)
|
|
b LoopFillZerobss
|
|
8000b4c: e002 b.n 8000b54 <LoopFillZerobss>
|
|
|
|
08000b4e <FillZerobss>:
|
|
/* Zero fill the bss segment. */
|
|
FillZerobss:
|
|
movs r3, #0
|
|
8000b4e: 2300 movs r3, #0
|
|
str r3, [r2], #4
|
|
8000b50: f842 3b04 str.w r3, [r2], #4
|
|
|
|
08000b54 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
ldr r3, = _ebss
|
|
8000b54: 4b08 ldr r3, [pc, #32] ; (8000b78 <LoopForever+0x16>)
|
|
cmp r2, r3
|
|
8000b56: 429a cmp r2, r3
|
|
bcc FillZerobss
|
|
8000b58: d3f9 bcc.n 8000b4e <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8000b5a: f000 f939 bl 8000dd0 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8000b5e: f7ff fe9f bl 80008a0 <main>
|
|
|
|
08000b62 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
8000b62: e7fe b.n 8000b62 <LoopForever>
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8000b64: 20018000 .word 0x20018000
|
|
ldr r3, =_sidata
|
|
8000b68: 08000e38 .word 0x08000e38
|
|
ldr r0, =_sdata
|
|
8000b6c: 20000000 .word 0x20000000
|
|
ldr r3, =_edata
|
|
8000b70: 20000010 .word 0x20000010
|
|
ldr r2, =_sbss
|
|
8000b74: 20000010 .word 0x20000010
|
|
ldr r3, = _ebss
|
|
8000b78: 20000034 .word 0x20000034
|
|
|
|
08000b7c <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8000b7c: e7fe b.n 8000b7c <ADC1_2_IRQHandler>
|
|
...
|
|
|
|
08000b80 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8000b80: b580 push {r7, lr}
|
|
8000b82: b084 sub sp, #16
|
|
8000b84: af00 add r7, sp, #0
|
|
8000b86: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8000b88: 2300 movs r3, #0
|
|
8000b8a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
8000b8c: 4b17 ldr r3, [pc, #92] ; (8000bec <HAL_InitTick+0x6c>)
|
|
8000b8e: 781b ldrb r3, [r3, #0]
|
|
8000b90: 2b00 cmp r3, #0
|
|
8000b92: d023 beq.n 8000bdc <HAL_InitTick+0x5c>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
|
|
8000b94: 4b16 ldr r3, [pc, #88] ; (8000bf0 <HAL_InitTick+0x70>)
|
|
8000b96: 681a ldr r2, [r3, #0]
|
|
8000b98: 4b14 ldr r3, [pc, #80] ; (8000bec <HAL_InitTick+0x6c>)
|
|
8000b9a: 781b ldrb r3, [r3, #0]
|
|
8000b9c: 4619 mov r1, r3
|
|
8000b9e: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
8000ba2: fbb3 f3f1 udiv r3, r3, r1
|
|
8000ba6: fbb2 f3f3 udiv r3, r2, r3
|
|
8000baa: 4618 mov r0, r3
|
|
8000bac: f000 f8ce bl 8000d4c <HAL_SYSTICK_Config>
|
|
8000bb0: 4603 mov r3, r0
|
|
8000bb2: 2b00 cmp r3, #0
|
|
8000bb4: d10f bne.n 8000bd6 <HAL_InitTick+0x56>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8000bb6: 687b ldr r3, [r7, #4]
|
|
8000bb8: 2b0f cmp r3, #15
|
|
8000bba: d809 bhi.n 8000bd0 <HAL_InitTick+0x50>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8000bbc: 2200 movs r2, #0
|
|
8000bbe: 6879 ldr r1, [r7, #4]
|
|
8000bc0: f04f 30ff mov.w r0, #4294967295
|
|
8000bc4: f000 f8a6 bl 8000d14 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8000bc8: 4a0a ldr r2, [pc, #40] ; (8000bf4 <HAL_InitTick+0x74>)
|
|
8000bca: 687b ldr r3, [r7, #4]
|
|
8000bcc: 6013 str r3, [r2, #0]
|
|
8000bce: e007 b.n 8000be0 <HAL_InitTick+0x60>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000bd0: 2301 movs r3, #1
|
|
8000bd2: 73fb strb r3, [r7, #15]
|
|
8000bd4: e004 b.n 8000be0 <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000bd6: 2301 movs r3, #1
|
|
8000bd8: 73fb strb r3, [r7, #15]
|
|
8000bda: e001 b.n 8000be0 <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000bdc: 2301 movs r3, #1
|
|
8000bde: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8000be0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8000be2: 4618 mov r0, r3
|
|
8000be4: 3710 adds r7, #16
|
|
8000be6: 46bd mov sp, r7
|
|
8000be8: bd80 pop {r7, pc}
|
|
8000bea: bf00 nop
|
|
8000bec: 2000000c .word 0x2000000c
|
|
8000bf0: 20000004 .word 0x20000004
|
|
8000bf4: 20000008 .word 0x20000008
|
|
|
|
08000bf8 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8000bf8: b480 push {r7}
|
|
8000bfa: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8000bfc: 4b04 ldr r3, [pc, #16] ; (8000c10 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8000bfe: 68db ldr r3, [r3, #12]
|
|
8000c00: 0a1b lsrs r3, r3, #8
|
|
8000c02: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8000c06: 4618 mov r0, r3
|
|
8000c08: 46bd mov sp, r7
|
|
8000c0a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000c0e: 4770 bx lr
|
|
8000c10: e000ed00 .word 0xe000ed00
|
|
|
|
08000c14 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8000c14: b480 push {r7}
|
|
8000c16: b083 sub sp, #12
|
|
8000c18: af00 add r7, sp, #0
|
|
8000c1a: 4603 mov r3, r0
|
|
8000c1c: 6039 str r1, [r7, #0]
|
|
8000c1e: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8000c20: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000c24: 2b00 cmp r3, #0
|
|
8000c26: db0a blt.n 8000c3e <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8000c28: 683b ldr r3, [r7, #0]
|
|
8000c2a: b2da uxtb r2, r3
|
|
8000c2c: 490c ldr r1, [pc, #48] ; (8000c60 <__NVIC_SetPriority+0x4c>)
|
|
8000c2e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000c32: 0112 lsls r2, r2, #4
|
|
8000c34: b2d2 uxtb r2, r2
|
|
8000c36: 440b add r3, r1
|
|
8000c38: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8000c3c: e00a b.n 8000c54 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8000c3e: 683b ldr r3, [r7, #0]
|
|
8000c40: b2da uxtb r2, r3
|
|
8000c42: 4908 ldr r1, [pc, #32] ; (8000c64 <__NVIC_SetPriority+0x50>)
|
|
8000c44: 79fb ldrb r3, [r7, #7]
|
|
8000c46: f003 030f and.w r3, r3, #15
|
|
8000c4a: 3b04 subs r3, #4
|
|
8000c4c: 0112 lsls r2, r2, #4
|
|
8000c4e: b2d2 uxtb r2, r2
|
|
8000c50: 440b add r3, r1
|
|
8000c52: 761a strb r2, [r3, #24]
|
|
}
|
|
8000c54: bf00 nop
|
|
8000c56: 370c adds r7, #12
|
|
8000c58: 46bd mov sp, r7
|
|
8000c5a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000c5e: 4770 bx lr
|
|
8000c60: e000e100 .word 0xe000e100
|
|
8000c64: e000ed00 .word 0xe000ed00
|
|
|
|
08000c68 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000c68: b480 push {r7}
|
|
8000c6a: b089 sub sp, #36 ; 0x24
|
|
8000c6c: af00 add r7, sp, #0
|
|
8000c6e: 60f8 str r0, [r7, #12]
|
|
8000c70: 60b9 str r1, [r7, #8]
|
|
8000c72: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000c74: 68fb ldr r3, [r7, #12]
|
|
8000c76: f003 0307 and.w r3, r3, #7
|
|
8000c7a: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8000c7c: 69fb ldr r3, [r7, #28]
|
|
8000c7e: f1c3 0307 rsb r3, r3, #7
|
|
8000c82: 2b04 cmp r3, #4
|
|
8000c84: bf28 it cs
|
|
8000c86: 2304 movcs r3, #4
|
|
8000c88: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8000c8a: 69fb ldr r3, [r7, #28]
|
|
8000c8c: 3304 adds r3, #4
|
|
8000c8e: 2b06 cmp r3, #6
|
|
8000c90: d902 bls.n 8000c98 <NVIC_EncodePriority+0x30>
|
|
8000c92: 69fb ldr r3, [r7, #28]
|
|
8000c94: 3b03 subs r3, #3
|
|
8000c96: e000 b.n 8000c9a <NVIC_EncodePriority+0x32>
|
|
8000c98: 2300 movs r3, #0
|
|
8000c9a: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8000c9c: f04f 32ff mov.w r2, #4294967295
|
|
8000ca0: 69bb ldr r3, [r7, #24]
|
|
8000ca2: fa02 f303 lsl.w r3, r2, r3
|
|
8000ca6: 43da mvns r2, r3
|
|
8000ca8: 68bb ldr r3, [r7, #8]
|
|
8000caa: 401a ands r2, r3
|
|
8000cac: 697b ldr r3, [r7, #20]
|
|
8000cae: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8000cb0: f04f 31ff mov.w r1, #4294967295
|
|
8000cb4: 697b ldr r3, [r7, #20]
|
|
8000cb6: fa01 f303 lsl.w r3, r1, r3
|
|
8000cba: 43d9 mvns r1, r3
|
|
8000cbc: 687b ldr r3, [r7, #4]
|
|
8000cbe: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8000cc0: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8000cc2: 4618 mov r0, r3
|
|
8000cc4: 3724 adds r7, #36 ; 0x24
|
|
8000cc6: 46bd mov sp, r7
|
|
8000cc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000ccc: 4770 bx lr
|
|
...
|
|
|
|
08000cd0 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8000cd0: b580 push {r7, lr}
|
|
8000cd2: b082 sub sp, #8
|
|
8000cd4: af00 add r7, sp, #0
|
|
8000cd6: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8000cd8: 687b ldr r3, [r7, #4]
|
|
8000cda: 3b01 subs r3, #1
|
|
8000cdc: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
8000ce0: d301 bcc.n 8000ce6 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8000ce2: 2301 movs r3, #1
|
|
8000ce4: e00f b.n 8000d06 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8000ce6: 4a0a ldr r2, [pc, #40] ; (8000d10 <SysTick_Config+0x40>)
|
|
8000ce8: 687b ldr r3, [r7, #4]
|
|
8000cea: 3b01 subs r3, #1
|
|
8000cec: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8000cee: 210f movs r1, #15
|
|
8000cf0: f04f 30ff mov.w r0, #4294967295
|
|
8000cf4: f7ff ff8e bl 8000c14 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8000cf8: 4b05 ldr r3, [pc, #20] ; (8000d10 <SysTick_Config+0x40>)
|
|
8000cfa: 2200 movs r2, #0
|
|
8000cfc: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8000cfe: 4b04 ldr r3, [pc, #16] ; (8000d10 <SysTick_Config+0x40>)
|
|
8000d00: 2207 movs r2, #7
|
|
8000d02: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8000d04: 2300 movs r3, #0
|
|
}
|
|
8000d06: 4618 mov r0, r3
|
|
8000d08: 3708 adds r7, #8
|
|
8000d0a: 46bd mov sp, r7
|
|
8000d0c: bd80 pop {r7, pc}
|
|
8000d0e: bf00 nop
|
|
8000d10: e000e010 .word 0xe000e010
|
|
|
|
08000d14 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000d14: b580 push {r7, lr}
|
|
8000d16: b086 sub sp, #24
|
|
8000d18: af00 add r7, sp, #0
|
|
8000d1a: 4603 mov r3, r0
|
|
8000d1c: 60b9 str r1, [r7, #8]
|
|
8000d1e: 607a str r2, [r7, #4]
|
|
8000d20: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8000d22: 2300 movs r3, #0
|
|
8000d24: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8000d26: f7ff ff67 bl 8000bf8 <__NVIC_GetPriorityGrouping>
|
|
8000d2a: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8000d2c: 687a ldr r2, [r7, #4]
|
|
8000d2e: 68b9 ldr r1, [r7, #8]
|
|
8000d30: 6978 ldr r0, [r7, #20]
|
|
8000d32: f7ff ff99 bl 8000c68 <NVIC_EncodePriority>
|
|
8000d36: 4602 mov r2, r0
|
|
8000d38: f997 300f ldrsb.w r3, [r7, #15]
|
|
8000d3c: 4611 mov r1, r2
|
|
8000d3e: 4618 mov r0, r3
|
|
8000d40: f7ff ff68 bl 8000c14 <__NVIC_SetPriority>
|
|
}
|
|
8000d44: bf00 nop
|
|
8000d46: 3718 adds r7, #24
|
|
8000d48: 46bd mov sp, r7
|
|
8000d4a: bd80 pop {r7, pc}
|
|
|
|
08000d4c <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8000d4c: b580 push {r7, lr}
|
|
8000d4e: b082 sub sp, #8
|
|
8000d50: af00 add r7, sp, #0
|
|
8000d52: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8000d54: 6878 ldr r0, [r7, #4]
|
|
8000d56: f7ff ffbb bl 8000cd0 <SysTick_Config>
|
|
8000d5a: 4603 mov r3, r0
|
|
}
|
|
8000d5c: 4618 mov r0, r3
|
|
8000d5e: 3708 adds r7, #8
|
|
8000d60: 46bd mov sp, r7
|
|
8000d62: bd80 pop {r7, pc}
|
|
|
|
08000d64 <LL_InitTick>:
|
|
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
|
* @param Ticks Number of ticks
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
|
{
|
|
8000d64: b480 push {r7}
|
|
8000d66: b083 sub sp, #12
|
|
8000d68: af00 add r7, sp, #0
|
|
8000d6a: 6078 str r0, [r7, #4]
|
|
8000d6c: 6039 str r1, [r7, #0]
|
|
/* Configure the SysTick to have interrupt in 1ms time base */
|
|
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
|
8000d6e: 687a ldr r2, [r7, #4]
|
|
8000d70: 683b ldr r3, [r7, #0]
|
|
8000d72: fbb2 f3f3 udiv r3, r2, r3
|
|
8000d76: 4a07 ldr r2, [pc, #28] ; (8000d94 <LL_InitTick+0x30>)
|
|
8000d78: 3b01 subs r3, #1
|
|
8000d7a: 6053 str r3, [r2, #4]
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8000d7c: 4b05 ldr r3, [pc, #20] ; (8000d94 <LL_InitTick+0x30>)
|
|
8000d7e: 2200 movs r2, #0
|
|
8000d80: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8000d82: 4b04 ldr r3, [pc, #16] ; (8000d94 <LL_InitTick+0x30>)
|
|
8000d84: 2205 movs r2, #5
|
|
8000d86: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
|
}
|
|
8000d88: bf00 nop
|
|
8000d8a: 370c adds r7, #12
|
|
8000d8c: 46bd mov sp, r7
|
|
8000d8e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000d92: 4770 bx lr
|
|
8000d94: e000e010 .word 0xe000e010
|
|
|
|
08000d98 <LL_Init1msTick>:
|
|
* @param HCLKFrequency HCLK frequency in Hz
|
|
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
|
|
* @retval None
|
|
*/
|
|
void LL_Init1msTick(uint32_t HCLKFrequency)
|
|
{
|
|
8000d98: b580 push {r7, lr}
|
|
8000d9a: b082 sub sp, #8
|
|
8000d9c: af00 add r7, sp, #0
|
|
8000d9e: 6078 str r0, [r7, #4]
|
|
/* Use frequency provided in argument */
|
|
LL_InitTick(HCLKFrequency, 100U);
|
|
8000da0: 2164 movs r1, #100 ; 0x64
|
|
8000da2: 6878 ldr r0, [r7, #4]
|
|
8000da4: f7ff ffde bl 8000d64 <LL_InitTick>
|
|
}
|
|
8000da8: bf00 nop
|
|
8000daa: 3708 adds r7, #8
|
|
8000dac: 46bd mov sp, r7
|
|
8000dae: bd80 pop {r7, pc}
|
|
|
|
08000db0 <LL_SetSystemCoreClock>:
|
|
* @note Variable can be calculated also through SystemCoreClockUpdate function.
|
|
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
|
* @retval None
|
|
*/
|
|
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
|
|
{
|
|
8000db0: b480 push {r7}
|
|
8000db2: b083 sub sp, #12
|
|
8000db4: af00 add r7, sp, #0
|
|
8000db6: 6078 str r0, [r7, #4]
|
|
/* HCLK clock frequency */
|
|
SystemCoreClock = HCLKFrequency;
|
|
8000db8: 4a04 ldr r2, [pc, #16] ; (8000dcc <LL_SetSystemCoreClock+0x1c>)
|
|
8000dba: 687b ldr r3, [r7, #4]
|
|
8000dbc: 6013 str r3, [r2, #0]
|
|
}
|
|
8000dbe: bf00 nop
|
|
8000dc0: 370c adds r7, #12
|
|
8000dc2: 46bd mov sp, r7
|
|
8000dc4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000dc8: 4770 bx lr
|
|
8000dca: bf00 nop
|
|
8000dcc: 20000004 .word 0x20000004
|
|
|
|
08000dd0 <__libc_init_array>:
|
|
8000dd0: b570 push {r4, r5, r6, lr}
|
|
8000dd2: 4e0d ldr r6, [pc, #52] ; (8000e08 <__libc_init_array+0x38>)
|
|
8000dd4: 4c0d ldr r4, [pc, #52] ; (8000e0c <__libc_init_array+0x3c>)
|
|
8000dd6: 1ba4 subs r4, r4, r6
|
|
8000dd8: 10a4 asrs r4, r4, #2
|
|
8000dda: 2500 movs r5, #0
|
|
8000ddc: 42a5 cmp r5, r4
|
|
8000dde: d109 bne.n 8000df4 <__libc_init_array+0x24>
|
|
8000de0: 4e0b ldr r6, [pc, #44] ; (8000e10 <__libc_init_array+0x40>)
|
|
8000de2: 4c0c ldr r4, [pc, #48] ; (8000e14 <__libc_init_array+0x44>)
|
|
8000de4: f000 f818 bl 8000e18 <_init>
|
|
8000de8: 1ba4 subs r4, r4, r6
|
|
8000dea: 10a4 asrs r4, r4, #2
|
|
8000dec: 2500 movs r5, #0
|
|
8000dee: 42a5 cmp r5, r4
|
|
8000df0: d105 bne.n 8000dfe <__libc_init_array+0x2e>
|
|
8000df2: bd70 pop {r4, r5, r6, pc}
|
|
8000df4: f856 3025 ldr.w r3, [r6, r5, lsl #2]
|
|
8000df8: 4798 blx r3
|
|
8000dfa: 3501 adds r5, #1
|
|
8000dfc: e7ee b.n 8000ddc <__libc_init_array+0xc>
|
|
8000dfe: f856 3025 ldr.w r3, [r6, r5, lsl #2]
|
|
8000e02: 4798 blx r3
|
|
8000e04: 3501 adds r5, #1
|
|
8000e06: e7f2 b.n 8000dee <__libc_init_array+0x1e>
|
|
8000e08: 08000e30 .word 0x08000e30
|
|
8000e0c: 08000e30 .word 0x08000e30
|
|
8000e10: 08000e30 .word 0x08000e30
|
|
8000e14: 08000e34 .word 0x08000e34
|
|
|
|
08000e18 <_init>:
|
|
8000e18: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8000e1a: bf00 nop
|
|
8000e1c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8000e1e: bc08 pop {r3}
|
|
8000e20: 469e mov lr, r3
|
|
8000e22: 4770 bx lr
|
|
|
|
08000e24 <_fini>:
|
|
8000e24: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8000e26: bf00 nop
|
|
8000e28: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8000e2a: bc08 pop {r3}
|
|
8000e2c: 469e mov lr, r3
|
|
8000e2e: 4770 bx lr
|