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LoPoSo/L476_ats_blink-master/Debug/L476_ats_blink-master.list
bray 59e2872b16 Before RTC read and stuff
2020-11-17 08:17:00 +01:00

2517 lines
87 KiB
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L476_ats_blink-master.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00000cb8 08000188 08000188 00010188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000000 08000e40 08000e40 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
3 .ARM.extab 00000000 08000e40 08000e40 0002000c 2**0
CONTENTS
4 .ARM 00000000 08000e40 08000e40 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08000e40 08000e40 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08000e40 08000e40 00010e40 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08000e44 08000e44 00010e44 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08000e48 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000044 2000000c 08000e54 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000600 20000050 08000e54 00020050 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00005a68 00000000 00000000 0002003c 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 00000ea3 00000000 00000000 00025aa4 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 00000630 00000000 00000000 00026948 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 000005a8 00000000 00000000 00026f78 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 00026368 00000000 00000000 00027520 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 00004aac 00000000 00000000 0004d888 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 000eeb27 00000000 00000000 00052334 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 00140e5b 2**0
CONTENTS, READONLY
20 .debug_frame 000017b4 00000000 00000000 00140ed8 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000000c .word 0x2000000c
80001a4: 00000000 .word 0x00000000
80001a8: 08000e28 .word 0x08000e28
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000010 .word 0x20000010
80001c4: 08000e28 .word 0x08000e28
080001c8 <LL_RCC_LSE_Enable>:
* @brief Enable Low Speed External (LSE) crystal.
* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
{
80001c8: b480 push {r7}
80001ca: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
80001cc: 4b06 ldr r3, [pc, #24] ; (80001e8 <LL_RCC_LSE_Enable+0x20>)
80001ce: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80001d2: 4a05 ldr r2, [pc, #20] ; (80001e8 <LL_RCC_LSE_Enable+0x20>)
80001d4: f043 0301 orr.w r3, r3, #1
80001d8: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
80001dc: bf00 nop
80001de: 46bd mov sp, r7
80001e0: f85d 7b04 ldr.w r7, [sp], #4
80001e4: 4770 bx lr
80001e6: bf00 nop
80001e8: 40021000 .word 0x40021000
080001ec <LL_RCC_LSE_SetDriveCapability>:
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
* @arg @ref LL_RCC_LSEDRIVE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
{
80001ec: b480 push {r7}
80001ee: b083 sub sp, #12
80001f0: af00 add r7, sp, #0
80001f2: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
80001f4: 4b07 ldr r3, [pc, #28] ; (8000214 <LL_RCC_LSE_SetDriveCapability+0x28>)
80001f6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80001fa: f023 0218 bic.w r2, r3, #24
80001fe: 4905 ldr r1, [pc, #20] ; (8000214 <LL_RCC_LSE_SetDriveCapability+0x28>)
8000200: 687b ldr r3, [r7, #4]
8000202: 4313 orrs r3, r2
8000204: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
8000208: bf00 nop
800020a: 370c adds r7, #12
800020c: 46bd mov sp, r7
800020e: f85d 7b04 ldr.w r7, [sp], #4
8000212: 4770 bx lr
8000214: 40021000 .word 0x40021000
08000218 <LL_RCC_LSE_IsReady>:
* @brief Check if LSE oscillator Ready
* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
{
8000218: b480 push {r7}
800021a: af00 add r7, sp, #0
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
800021c: 4b07 ldr r3, [pc, #28] ; (800023c <LL_RCC_LSE_IsReady+0x24>)
800021e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8000222: f003 0302 and.w r3, r3, #2
8000226: 2b02 cmp r3, #2
8000228: d101 bne.n 800022e <LL_RCC_LSE_IsReady+0x16>
800022a: 2301 movs r3, #1
800022c: e000 b.n 8000230 <LL_RCC_LSE_IsReady+0x18>
800022e: 2300 movs r3, #0
}
8000230: 4618 mov r0, r3
8000232: 46bd mov sp, r7
8000234: f85d 7b04 ldr.w r7, [sp], #4
8000238: 4770 bx lr
800023a: bf00 nop
800023c: 40021000 .word 0x40021000
08000240 <LL_RCC_MSI_Enable>:
* @brief Enable MSI oscillator
* @rmtoll CR MSION LL_RCC_MSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
{
8000240: b480 push {r7}
8000242: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSION);
8000244: 4b05 ldr r3, [pc, #20] ; (800025c <LL_RCC_MSI_Enable+0x1c>)
8000246: 681b ldr r3, [r3, #0]
8000248: 4a04 ldr r2, [pc, #16] ; (800025c <LL_RCC_MSI_Enable+0x1c>)
800024a: f043 0301 orr.w r3, r3, #1
800024e: 6013 str r3, [r2, #0]
}
8000250: bf00 nop
8000252: 46bd mov sp, r7
8000254: f85d 7b04 ldr.w r7, [sp], #4
8000258: 4770 bx lr
800025a: bf00 nop
800025c: 40021000 .word 0x40021000
08000260 <LL_RCC_MSI_IsReady>:
* @brief Check if MSI oscillator Ready
* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
{
8000260: b480 push {r7}
8000262: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
8000264: 4b06 ldr r3, [pc, #24] ; (8000280 <LL_RCC_MSI_IsReady+0x20>)
8000266: 681b ldr r3, [r3, #0]
8000268: f003 0302 and.w r3, r3, #2
800026c: 2b02 cmp r3, #2
800026e: d101 bne.n 8000274 <LL_RCC_MSI_IsReady+0x14>
8000270: 2301 movs r3, #1
8000272: e000 b.n 8000276 <LL_RCC_MSI_IsReady+0x16>
8000274: 2300 movs r3, #0
}
8000276: 4618 mov r0, r3
8000278: 46bd mov sp, r7
800027a: f85d 7b04 ldr.w r7, [sp], #4
800027e: 4770 bx lr
8000280: 40021000 .word 0x40021000
08000284 <LL_RCC_MSI_EnablePLLMode>:
* ready
* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
{
8000284: b480 push {r7}
8000286: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
8000288: 4b05 ldr r3, [pc, #20] ; (80002a0 <LL_RCC_MSI_EnablePLLMode+0x1c>)
800028a: 681b ldr r3, [r3, #0]
800028c: 4a04 ldr r2, [pc, #16] ; (80002a0 <LL_RCC_MSI_EnablePLLMode+0x1c>)
800028e: f043 0304 orr.w r3, r3, #4
8000292: 6013 str r3, [r2, #0]
}
8000294: bf00 nop
8000296: 46bd mov sp, r7
8000298: f85d 7b04 ldr.w r7, [sp], #4
800029c: 4770 bx lr
800029e: bf00 nop
80002a0: 40021000 .word 0x40021000
080002a4 <LL_RCC_MSI_EnableRangeSelection>:
* MSISRANGE
* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
{
80002a4: b480 push {r7}
80002a6: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
80002a8: 4b05 ldr r3, [pc, #20] ; (80002c0 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
80002aa: 681b ldr r3, [r3, #0]
80002ac: 4a04 ldr r2, [pc, #16] ; (80002c0 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
80002ae: f043 0308 orr.w r3, r3, #8
80002b2: 6013 str r3, [r2, #0]
}
80002b4: bf00 nop
80002b6: 46bd mov sp, r7
80002b8: f85d 7b04 ldr.w r7, [sp], #4
80002bc: 4770 bx lr
80002be: bf00 nop
80002c0: 40021000 .word 0x40021000
080002c4 <LL_RCC_MSI_SetRange>:
* @arg @ref LL_RCC_MSIRANGE_10
* @arg @ref LL_RCC_MSIRANGE_11
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
{
80002c4: b480 push {r7}
80002c6: b083 sub sp, #12
80002c8: af00 add r7, sp, #0
80002ca: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
80002cc: 4b06 ldr r3, [pc, #24] ; (80002e8 <LL_RCC_MSI_SetRange+0x24>)
80002ce: 681b ldr r3, [r3, #0]
80002d0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
80002d4: 4904 ldr r1, [pc, #16] ; (80002e8 <LL_RCC_MSI_SetRange+0x24>)
80002d6: 687b ldr r3, [r7, #4]
80002d8: 4313 orrs r3, r2
80002da: 600b str r3, [r1, #0]
}
80002dc: bf00 nop
80002de: 370c adds r7, #12
80002e0: 46bd mov sp, r7
80002e2: f85d 7b04 ldr.w r7, [sp], #4
80002e6: 4770 bx lr
80002e8: 40021000 .word 0x40021000
080002ec <LL_RCC_MSI_SetCalibTrimming>:
* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
* @param Value Between Min_Data = 0 and Max_Data = 255
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
{
80002ec: b480 push {r7}
80002ee: b083 sub sp, #12
80002f0: af00 add r7, sp, #0
80002f2: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
80002f4: 4b07 ldr r3, [pc, #28] ; (8000314 <LL_RCC_MSI_SetCalibTrimming+0x28>)
80002f6: 685b ldr r3, [r3, #4]
80002f8: f423 427f bic.w r2, r3, #65280 ; 0xff00
80002fc: 687b ldr r3, [r7, #4]
80002fe: 021b lsls r3, r3, #8
8000300: 4904 ldr r1, [pc, #16] ; (8000314 <LL_RCC_MSI_SetCalibTrimming+0x28>)
8000302: 4313 orrs r3, r2
8000304: 604b str r3, [r1, #4]
}
8000306: bf00 nop
8000308: 370c adds r7, #12
800030a: 46bd mov sp, r7
800030c: f85d 7b04 ldr.w r7, [sp], #4
8000310: 4770 bx lr
8000312: bf00 nop
8000314: 40021000 .word 0x40021000
08000318 <LL_RCC_SetSysClkSource>:
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
8000318: b480 push {r7}
800031a: b083 sub sp, #12
800031c: af00 add r7, sp, #0
800031e: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
8000320: 4b06 ldr r3, [pc, #24] ; (800033c <LL_RCC_SetSysClkSource+0x24>)
8000322: 689b ldr r3, [r3, #8]
8000324: f023 0203 bic.w r2, r3, #3
8000328: 4904 ldr r1, [pc, #16] ; (800033c <LL_RCC_SetSysClkSource+0x24>)
800032a: 687b ldr r3, [r7, #4]
800032c: 4313 orrs r3, r2
800032e: 608b str r3, [r1, #8]
}
8000330: bf00 nop
8000332: 370c adds r7, #12
8000334: 46bd mov sp, r7
8000336: f85d 7b04 ldr.w r7, [sp], #4
800033a: 4770 bx lr
800033c: 40021000 .word 0x40021000
08000340 <LL_RCC_GetSysClkSource>:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
8000340: b480 push {r7}
8000342: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
8000344: 4b04 ldr r3, [pc, #16] ; (8000358 <LL_RCC_GetSysClkSource+0x18>)
8000346: 689b ldr r3, [r3, #8]
8000348: f003 030c and.w r3, r3, #12
}
800034c: 4618 mov r0, r3
800034e: 46bd mov sp, r7
8000350: f85d 7b04 ldr.w r7, [sp], #4
8000354: 4770 bx lr
8000356: bf00 nop
8000358: 40021000 .word 0x40021000
0800035c <LL_RCC_SetAHBPrescaler>:
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
800035c: b480 push {r7}
800035e: b083 sub sp, #12
8000360: af00 add r7, sp, #0
8000362: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
8000364: 4b06 ldr r3, [pc, #24] ; (8000380 <LL_RCC_SetAHBPrescaler+0x24>)
8000366: 689b ldr r3, [r3, #8]
8000368: f023 02f0 bic.w r2, r3, #240 ; 0xf0
800036c: 4904 ldr r1, [pc, #16] ; (8000380 <LL_RCC_SetAHBPrescaler+0x24>)
800036e: 687b ldr r3, [r7, #4]
8000370: 4313 orrs r3, r2
8000372: 608b str r3, [r1, #8]
}
8000374: bf00 nop
8000376: 370c adds r7, #12
8000378: 46bd mov sp, r7
800037a: f85d 7b04 ldr.w r7, [sp], #4
800037e: 4770 bx lr
8000380: 40021000 .word 0x40021000
08000384 <LL_RCC_SetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
8000384: b480 push {r7}
8000386: b083 sub sp, #12
8000388: af00 add r7, sp, #0
800038a: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
800038c: 4b06 ldr r3, [pc, #24] ; (80003a8 <LL_RCC_SetAPB1Prescaler+0x24>)
800038e: 689b ldr r3, [r3, #8]
8000390: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8000394: 4904 ldr r1, [pc, #16] ; (80003a8 <LL_RCC_SetAPB1Prescaler+0x24>)
8000396: 687b ldr r3, [r7, #4]
8000398: 4313 orrs r3, r2
800039a: 608b str r3, [r1, #8]
}
800039c: bf00 nop
800039e: 370c adds r7, #12
80003a0: 46bd mov sp, r7
80003a2: f85d 7b04 ldr.w r7, [sp], #4
80003a6: 4770 bx lr
80003a8: 40021000 .word 0x40021000
080003ac <LL_RCC_SetAPB2Prescaler>:
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
{
80003ac: b480 push {r7}
80003ae: b083 sub sp, #12
80003b0: af00 add r7, sp, #0
80003b2: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
80003b4: 4b06 ldr r3, [pc, #24] ; (80003d0 <LL_RCC_SetAPB2Prescaler+0x24>)
80003b6: 689b ldr r3, [r3, #8]
80003b8: f423 5260 bic.w r2, r3, #14336 ; 0x3800
80003bc: 4904 ldr r1, [pc, #16] ; (80003d0 <LL_RCC_SetAPB2Prescaler+0x24>)
80003be: 687b ldr r3, [r7, #4]
80003c0: 4313 orrs r3, r2
80003c2: 608b str r3, [r1, #8]
}
80003c4: bf00 nop
80003c6: 370c adds r7, #12
80003c8: 46bd mov sp, r7
80003ca: f85d 7b04 ldr.w r7, [sp], #4
80003ce: 4770 bx lr
80003d0: 40021000 .word 0x40021000
080003d4 <LL_RCC_SetRTCClockSource>:
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
{
80003d4: b480 push {r7}
80003d6: b083 sub sp, #12
80003d8: af00 add r7, sp, #0
80003da: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
80003dc: 4b07 ldr r3, [pc, #28] ; (80003fc <LL_RCC_SetRTCClockSource+0x28>)
80003de: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80003e2: f423 7240 bic.w r2, r3, #768 ; 0x300
80003e6: 4905 ldr r1, [pc, #20] ; (80003fc <LL_RCC_SetRTCClockSource+0x28>)
80003e8: 687b ldr r3, [r7, #4]
80003ea: 4313 orrs r3, r2
80003ec: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
80003f0: bf00 nop
80003f2: 370c adds r7, #12
80003f4: 46bd mov sp, r7
80003f6: f85d 7b04 ldr.w r7, [sp], #4
80003fa: 4770 bx lr
80003fc: 40021000 .word 0x40021000
08000400 <LL_RCC_EnableRTC>:
* @brief Enable RTC
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableRTC(void)
{
8000400: b480 push {r7}
8000402: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
8000404: 4b06 ldr r3, [pc, #24] ; (8000420 <LL_RCC_EnableRTC+0x20>)
8000406: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800040a: 4a05 ldr r2, [pc, #20] ; (8000420 <LL_RCC_EnableRTC+0x20>)
800040c: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8000410: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
8000414: bf00 nop
8000416: 46bd mov sp, r7
8000418: f85d 7b04 ldr.w r7, [sp], #4
800041c: 4770 bx lr
800041e: bf00 nop
8000420: 40021000 .word 0x40021000
08000424 <LL_RCC_ForceBackupDomainReset>:
* @brief Force the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
{
8000424: b480 push {r7}
8000426: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
8000428: 4b06 ldr r3, [pc, #24] ; (8000444 <LL_RCC_ForceBackupDomainReset+0x20>)
800042a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800042e: 4a05 ldr r2, [pc, #20] ; (8000444 <LL_RCC_ForceBackupDomainReset+0x20>)
8000430: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000434: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
8000438: bf00 nop
800043a: 46bd mov sp, r7
800043c: f85d 7b04 ldr.w r7, [sp], #4
8000440: 4770 bx lr
8000442: bf00 nop
8000444: 40021000 .word 0x40021000
08000448 <LL_RCC_ReleaseBackupDomainReset>:
* @brief Release the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
{
8000448: b480 push {r7}
800044a: af00 add r7, sp, #0
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
800044c: 4b06 ldr r3, [pc, #24] ; (8000468 <LL_RCC_ReleaseBackupDomainReset+0x20>)
800044e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8000452: 4a05 ldr r2, [pc, #20] ; (8000468 <LL_RCC_ReleaseBackupDomainReset+0x20>)
8000454: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000458: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
800045c: bf00 nop
800045e: 46bd mov sp, r7
8000460: f85d 7b04 ldr.w r7, [sp], #4
8000464: 4770 bx lr
8000466: bf00 nop
8000468: 40021000 .word 0x40021000
0800046c <LL_RCC_PLL_Enable>:
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
800046c: b480 push {r7}
800046e: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_PLLON);
8000470: 4b05 ldr r3, [pc, #20] ; (8000488 <LL_RCC_PLL_Enable+0x1c>)
8000472: 681b ldr r3, [r3, #0]
8000474: 4a04 ldr r2, [pc, #16] ; (8000488 <LL_RCC_PLL_Enable+0x1c>)
8000476: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
800047a: 6013 str r3, [r2, #0]
}
800047c: bf00 nop
800047e: 46bd mov sp, r7
8000480: f85d 7b04 ldr.w r7, [sp], #4
8000484: 4770 bx lr
8000486: bf00 nop
8000488: 40021000 .word 0x40021000
0800048c <LL_RCC_PLL_IsReady>:
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
800048c: b480 push {r7}
800048e: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
8000490: 4b07 ldr r3, [pc, #28] ; (80004b0 <LL_RCC_PLL_IsReady+0x24>)
8000492: 681b ldr r3, [r3, #0]
8000494: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000498: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
800049c: d101 bne.n 80004a2 <LL_RCC_PLL_IsReady+0x16>
800049e: 2301 movs r3, #1
80004a0: e000 b.n 80004a4 <LL_RCC_PLL_IsReady+0x18>
80004a2: 2300 movs r3, #0
}
80004a4: 4618 mov r0, r3
80004a6: 46bd mov sp, r7
80004a8: f85d 7b04 ldr.w r7, [sp], #4
80004ac: 4770 bx lr
80004ae: bf00 nop
80004b0: 40021000 .word 0x40021000
080004b4 <LL_RCC_PLL_ConfigDomain_SYS>:
* @arg @ref LL_RCC_PLLR_DIV_6
* @arg @ref LL_RCC_PLLR_DIV_8
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
80004b4: b480 push {r7}
80004b6: b085 sub sp, #20
80004b8: af00 add r7, sp, #0
80004ba: 60f8 str r0, [r7, #12]
80004bc: 60b9 str r1, [r7, #8]
80004be: 607a str r2, [r7, #4]
80004c0: 603b str r3, [r7, #0]
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
80004c2: 4b0a ldr r3, [pc, #40] ; (80004ec <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
80004c4: 68da ldr r2, [r3, #12]
80004c6: 4b0a ldr r3, [pc, #40] ; (80004f0 <LL_RCC_PLL_ConfigDomain_SYS+0x3c>)
80004c8: 4013 ands r3, r2
80004ca: 68f9 ldr r1, [r7, #12]
80004cc: 68ba ldr r2, [r7, #8]
80004ce: 4311 orrs r1, r2
80004d0: 687a ldr r2, [r7, #4]
80004d2: 0212 lsls r2, r2, #8
80004d4: 4311 orrs r1, r2
80004d6: 683a ldr r2, [r7, #0]
80004d8: 430a orrs r2, r1
80004da: 4904 ldr r1, [pc, #16] ; (80004ec <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
80004dc: 4313 orrs r3, r2
80004de: 60cb str r3, [r1, #12]
Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
}
80004e0: bf00 nop
80004e2: 3714 adds r7, #20
80004e4: 46bd mov sp, r7
80004e6: f85d 7b04 ldr.w r7, [sp], #4
80004ea: 4770 bx lr
80004ec: 40021000 .word 0x40021000
80004f0: f9ff808c .word 0xf9ff808c
080004f4 <LL_RCC_PLL_EnableDomain_SYS>:
* @brief Enable PLL output mapped on SYSCLK domain
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
{
80004f4: b480 push {r7}
80004f6: af00 add r7, sp, #0
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
80004f8: 4b05 ldr r3, [pc, #20] ; (8000510 <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
80004fa: 68db ldr r3, [r3, #12]
80004fc: 4a04 ldr r2, [pc, #16] ; (8000510 <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
80004fe: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8000502: 60d3 str r3, [r2, #12]
}
8000504: bf00 nop
8000506: 46bd mov sp, r7
8000508: f85d 7b04 ldr.w r7, [sp], #4
800050c: 4770 bx lr
800050e: bf00 nop
8000510: 40021000 .word 0x40021000
08000514 <LL_FLASH_SetLatency>:
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
8000514: b480 push {r7}
8000516: b083 sub sp, #12
8000518: af00 add r7, sp, #0
800051a: 6078 str r0, [r7, #4]
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
800051c: 4b06 ldr r3, [pc, #24] ; (8000538 <LL_FLASH_SetLatency+0x24>)
800051e: 681b ldr r3, [r3, #0]
8000520: f023 0207 bic.w r2, r3, #7
8000524: 4904 ldr r1, [pc, #16] ; (8000538 <LL_FLASH_SetLatency+0x24>)
8000526: 687b ldr r3, [r7, #4]
8000528: 4313 orrs r3, r2
800052a: 600b str r3, [r1, #0]
}
800052c: bf00 nop
800052e: 370c adds r7, #12
8000530: 46bd mov sp, r7
8000532: f85d 7b04 ldr.w r7, [sp], #4
8000536: 4770 bx lr
8000538: 40022000 .word 0x40022000
0800053c <LL_FLASH_GetLatency>:
* @arg @ref LL_FLASH_LATENCY_15 (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
800053c: b480 push {r7}
800053e: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
8000540: 4b04 ldr r3, [pc, #16] ; (8000554 <LL_FLASH_GetLatency+0x18>)
8000542: 681b ldr r3, [r3, #0]
8000544: f003 0307 and.w r3, r3, #7
}
8000548: 4618 mov r0, r3
800054a: 46bd mov sp, r7
800054c: f85d 7b04 ldr.w r7, [sp], #4
8000550: 4770 bx lr
8000552: bf00 nop
8000554: 40022000 .word 0x40022000
08000558 <LL_PWR_SetRegulVoltageScaling>:
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
{
8000558: b480 push {r7}
800055a: b083 sub sp, #12
800055c: af00 add r7, sp, #0
800055e: 6078 str r0, [r7, #4]
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
8000560: 4b06 ldr r3, [pc, #24] ; (800057c <LL_PWR_SetRegulVoltageScaling+0x24>)
8000562: 681b ldr r3, [r3, #0]
8000564: f423 62c0 bic.w r2, r3, #1536 ; 0x600
8000568: 4904 ldr r1, [pc, #16] ; (800057c <LL_PWR_SetRegulVoltageScaling+0x24>)
800056a: 687b ldr r3, [r7, #4]
800056c: 4313 orrs r3, r2
800056e: 600b str r3, [r1, #0]
}
8000570: bf00 nop
8000572: 370c adds r7, #12
8000574: 46bd mov sp, r7
8000576: f85d 7b04 ldr.w r7, [sp], #4
800057a: 4770 bx lr
800057c: 40007000 .word 0x40007000
08000580 <LL_PWR_EnableBkUpAccess>:
* @brief Enable access to the backup domain
* @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
8000580: b480 push {r7}
8000582: af00 add r7, sp, #0
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8000584: 4b05 ldr r3, [pc, #20] ; (800059c <LL_PWR_EnableBkUpAccess+0x1c>)
8000586: 681b ldr r3, [r3, #0]
8000588: 4a04 ldr r2, [pc, #16] ; (800059c <LL_PWR_EnableBkUpAccess+0x1c>)
800058a: f443 7380 orr.w r3, r3, #256 ; 0x100
800058e: 6013 str r3, [r2, #0]
}
8000590: bf00 nop
8000592: 46bd mov sp, r7
8000594: f85d 7b04 ldr.w r7, [sp], #4
8000598: 4770 bx lr
800059a: bf00 nop
800059c: 40007000 .word 0x40007000
080005a0 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80005a0: b580 push {r7, lr}
80005a2: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80005a4: f000 f99f bl 80008e6 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80005a8: f000 f806 bl 80005b8 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80005ac: f000 f896 bl 80006dc <MX_GPIO_Init>
MX_RTC_Init();
80005b0: f000 f86c bl 800068c <MX_RTC_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
80005b4: e7fe b.n 80005b4 <main+0x14>
...
080005b8 <SystemClock_Config>:
* @brief System Clock Configuration
* @retval None
* 24Mhz + RTC + LSE
*/
void SystemClock_Config(void)
{
80005b8: b580 push {r7, lr}
80005ba: af00 add r7, sp, #0
LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
80005bc: 2001 movs r0, #1
80005be: f7ff ffa9 bl 8000514 <LL_FLASH_SetLatency>
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_1)
80005c2: bf00 nop
80005c4: f7ff ffba bl 800053c <LL_FLASH_GetLatency>
80005c8: 4603 mov r3, r0
80005ca: 2b01 cmp r3, #1
80005cc: d1fa bne.n 80005c4 <SystemClock_Config+0xc>
{
}
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
80005ce: f44f 7000 mov.w r0, #512 ; 0x200
80005d2: f7ff ffc1 bl 8000558 <LL_PWR_SetRegulVoltageScaling>
LL_RCC_MSI_Enable();
80005d6: f7ff fe33 bl 8000240 <LL_RCC_MSI_Enable>
/* Wait till MSI is ready */
while(LL_RCC_MSI_IsReady() != 1)
80005da: bf00 nop
80005dc: f7ff fe40 bl 8000260 <LL_RCC_MSI_IsReady>
80005e0: 4603 mov r3, r0
80005e2: 2b01 cmp r3, #1
80005e4: d1fa bne.n 80005dc <SystemClock_Config+0x24>
{
}
LL_RCC_MSI_EnablePLLMode();
80005e6: f7ff fe4d bl 8000284 <LL_RCC_MSI_EnablePLLMode>
LL_RCC_MSI_EnableRangeSelection();
80005ea: f7ff fe5b bl 80002a4 <LL_RCC_MSI_EnableRangeSelection>
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
80005ee: 2060 movs r0, #96 ; 0x60
80005f0: f7ff fe68 bl 80002c4 <LL_RCC_MSI_SetRange>
LL_RCC_MSI_SetCalibTrimming(0);
80005f4: 2000 movs r0, #0
80005f6: f7ff fe79 bl 80002ec <LL_RCC_MSI_SetCalibTrimming>
LL_PWR_EnableBkUpAccess();
80005fa: f7ff ffc1 bl 8000580 <LL_PWR_EnableBkUpAccess>
LL_RCC_ForceBackupDomainReset();
80005fe: f7ff ff11 bl 8000424 <LL_RCC_ForceBackupDomainReset>
LL_RCC_ReleaseBackupDomainReset();
8000602: f7ff ff21 bl 8000448 <LL_RCC_ReleaseBackupDomainReset>
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW);
8000606: 2000 movs r0, #0
8000608: f7ff fdf0 bl 80001ec <LL_RCC_LSE_SetDriveCapability>
LL_RCC_LSE_Enable();
800060c: f7ff fddc bl 80001c8 <LL_RCC_LSE_Enable>
/* Wait till LSE is ready */
while(LL_RCC_LSE_IsReady() != 1)
8000610: bf00 nop
8000612: f7ff fe01 bl 8000218 <LL_RCC_LSE_IsReady>
8000616: 4603 mov r3, r0
8000618: 2b01 cmp r3, #1
800061a: d1fa bne.n 8000612 <SystemClock_Config+0x5a>
{
}
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
800061c: f44f 7080 mov.w r0, #256 ; 0x100
8000620: f7ff fed8 bl 80003d4 <LL_RCC_SetRTCClockSource>
LL_RCC_EnableRTC();
8000624: f7ff feec bl 8000400 <LL_RCC_EnableRTC>
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 24, LL_RCC_PLLR_DIV_4);
8000628: f04f 7300 mov.w r3, #33554432 ; 0x2000000
800062c: 2218 movs r2, #24
800062e: 2100 movs r1, #0
8000630: 2001 movs r0, #1
8000632: f7ff ff3f bl 80004b4 <LL_RCC_PLL_ConfigDomain_SYS>
LL_RCC_PLL_EnableDomain_SYS();
8000636: f7ff ff5d bl 80004f4 <LL_RCC_PLL_EnableDomain_SYS>
LL_RCC_PLL_Enable();
800063a: f7ff ff17 bl 800046c <LL_RCC_PLL_Enable>
/* Wait till PLL is ready */
while(LL_RCC_PLL_IsReady() != 1)
800063e: bf00 nop
8000640: f7ff ff24 bl 800048c <LL_RCC_PLL_IsReady>
8000644: 4603 mov r3, r0
8000646: 2b01 cmp r3, #1
8000648: d1fa bne.n 8000640 <SystemClock_Config+0x88>
{
}
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
800064a: 2003 movs r0, #3
800064c: f7ff fe64 bl 8000318 <LL_RCC_SetSysClkSource>
/* Wait till System clock is ready */
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
8000650: bf00 nop
8000652: f7ff fe75 bl 8000340 <LL_RCC_GetSysClkSource>
8000656: 4603 mov r3, r0
8000658: 2b0c cmp r3, #12
800065a: d1fa bne.n 8000652 <SystemClock_Config+0x9a>
{
}
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
800065c: 2000 movs r0, #0
800065e: f7ff fe7d bl 800035c <LL_RCC_SetAHBPrescaler>
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
8000662: 2000 movs r0, #0
8000664: f7ff fe8e bl 8000384 <LL_RCC_SetAPB1Prescaler>
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
8000668: 2000 movs r0, #0
800066a: f7ff fe9f bl 80003ac <LL_RCC_SetAPB2Prescaler>
LL_SetSystemCoreClock(24000000);
800066e: 4806 ldr r0, [pc, #24] ; (8000688 <SystemClock_Config+0xd0>)
8000670: f000 fba6 bl 8000dc0 <LL_SetSystemCoreClock>
/* Update the time base */
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
8000674: 2000 movs r0, #0
8000676: f000 f94f bl 8000918 <HAL_InitTick>
800067a: 4603 mov r3, r0
800067c: 2b00 cmp r3, #0
800067e: d001 beq.n 8000684 <SystemClock_Config+0xcc>
{
Error_Handler();
8000680: f000 f85c bl 800073c <Error_Handler>
}
}
8000684: bf00 nop
8000686: bd80 pop {r7, pc}
8000688: 016e3600 .word 0x016e3600
0800068c <MX_RTC_Init>:
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static void MX_RTC_Init(void)
{
800068c: b580 push {r7, lr}
800068e: af00 add r7, sp, #0
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/** Initialize RTC Only
*/
hrtc.Instance = RTC;
8000690: 4b10 ldr r3, [pc, #64] ; (80006d4 <MX_RTC_Init+0x48>)
8000692: 4a11 ldr r2, [pc, #68] ; (80006d8 <MX_RTC_Init+0x4c>)
8000694: 601a str r2, [r3, #0]
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
8000696: 4b0f ldr r3, [pc, #60] ; (80006d4 <MX_RTC_Init+0x48>)
8000698: 2200 movs r2, #0
800069a: 605a str r2, [r3, #4]
hrtc.Init.AsynchPrediv = 127;
800069c: 4b0d ldr r3, [pc, #52] ; (80006d4 <MX_RTC_Init+0x48>)
800069e: 227f movs r2, #127 ; 0x7f
80006a0: 609a str r2, [r3, #8]
hrtc.Init.SynchPrediv = 255;
80006a2: 4b0c ldr r3, [pc, #48] ; (80006d4 <MX_RTC_Init+0x48>)
80006a4: 22ff movs r2, #255 ; 0xff
80006a6: 60da str r2, [r3, #12]
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
80006a8: 4b0a ldr r3, [pc, #40] ; (80006d4 <MX_RTC_Init+0x48>)
80006aa: 2200 movs r2, #0
80006ac: 611a str r2, [r3, #16]
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;
80006ae: 4b09 ldr r3, [pc, #36] ; (80006d4 <MX_RTC_Init+0x48>)
80006b0: 2200 movs r2, #0
80006b2: 615a str r2, [r3, #20]
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
80006b4: 4b07 ldr r3, [pc, #28] ; (80006d4 <MX_RTC_Init+0x48>)
80006b6: 2200 movs r2, #0
80006b8: 619a str r2, [r3, #24]
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
80006ba: 4b06 ldr r3, [pc, #24] ; (80006d4 <MX_RTC_Init+0x48>)
80006bc: 2200 movs r2, #0
80006be: 61da str r2, [r3, #28]
if (HAL_RTC_Init(&hrtc) != HAL_OK)
80006c0: 4804 ldr r0, [pc, #16] ; (80006d4 <MX_RTC_Init+0x48>)
80006c2: f000 fa6a bl 8000b9a <HAL_RTC_Init>
80006c6: 4603 mov r3, r0
80006c8: 2b00 cmp r3, #0
80006ca: d001 beq.n 80006d0 <MX_RTC_Init+0x44>
{
Error_Handler();
80006cc: f000 f836 bl 800073c <Error_Handler>
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
80006d0: bf00 nop
80006d2: bd80 pop {r7, pc}
80006d4: 20000028 .word 0x20000028
80006d8: 40002800 .word 0x40002800
080006dc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80006dc: b480 push {r7}
80006de: b085 sub sp, #20
80006e0: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80006e2: 4b15 ldr r3, [pc, #84] ; (8000738 <MX_GPIO_Init+0x5c>)
80006e4: 6cdb ldr r3, [r3, #76] ; 0x4c
80006e6: 4a14 ldr r2, [pc, #80] ; (8000738 <MX_GPIO_Init+0x5c>)
80006e8: f043 0304 orr.w r3, r3, #4
80006ec: 64d3 str r3, [r2, #76] ; 0x4c
80006ee: 4b12 ldr r3, [pc, #72] ; (8000738 <MX_GPIO_Init+0x5c>)
80006f0: 6cdb ldr r3, [r3, #76] ; 0x4c
80006f2: f003 0304 and.w r3, r3, #4
80006f6: 60fb str r3, [r7, #12]
80006f8: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80006fa: 4b0f ldr r3, [pc, #60] ; (8000738 <MX_GPIO_Init+0x5c>)
80006fc: 6cdb ldr r3, [r3, #76] ; 0x4c
80006fe: 4a0e ldr r2, [pc, #56] ; (8000738 <MX_GPIO_Init+0x5c>)
8000700: f043 0301 orr.w r3, r3, #1
8000704: 64d3 str r3, [r2, #76] ; 0x4c
8000706: 4b0c ldr r3, [pc, #48] ; (8000738 <MX_GPIO_Init+0x5c>)
8000708: 6cdb ldr r3, [r3, #76] ; 0x4c
800070a: f003 0301 and.w r3, r3, #1
800070e: 60bb str r3, [r7, #8]
8000710: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000712: 4b09 ldr r3, [pc, #36] ; (8000738 <MX_GPIO_Init+0x5c>)
8000714: 6cdb ldr r3, [r3, #76] ; 0x4c
8000716: 4a08 ldr r2, [pc, #32] ; (8000738 <MX_GPIO_Init+0x5c>)
8000718: f043 0302 orr.w r3, r3, #2
800071c: 64d3 str r3, [r2, #76] ; 0x4c
800071e: 4b06 ldr r3, [pc, #24] ; (8000738 <MX_GPIO_Init+0x5c>)
8000720: 6cdb ldr r3, [r3, #76] ; 0x4c
8000722: f003 0302 and.w r3, r3, #2
8000726: 607b str r3, [r7, #4]
8000728: 687b ldr r3, [r7, #4]
}
800072a: bf00 nop
800072c: 3714 adds r7, #20
800072e: 46bd mov sp, r7
8000730: f85d 7b04 ldr.w r7, [sp], #4
8000734: 4770 bx lr
8000736: bf00 nop
8000738: 40021000 .word 0x40021000
0800073c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800073c: b480 push {r7}
800073e: af00 add r7, sp, #0
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
8000740: bf00 nop
8000742: 46bd mov sp, r7
8000744: f85d 7b04 ldr.w r7, [sp], #4
8000748: 4770 bx lr
...
0800074c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800074c: b480 push {r7}
800074e: b083 sub sp, #12
8000750: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000752: 4b0f ldr r3, [pc, #60] ; (8000790 <HAL_MspInit+0x44>)
8000754: 6e1b ldr r3, [r3, #96] ; 0x60
8000756: 4a0e ldr r2, [pc, #56] ; (8000790 <HAL_MspInit+0x44>)
8000758: f043 0301 orr.w r3, r3, #1
800075c: 6613 str r3, [r2, #96] ; 0x60
800075e: 4b0c ldr r3, [pc, #48] ; (8000790 <HAL_MspInit+0x44>)
8000760: 6e1b ldr r3, [r3, #96] ; 0x60
8000762: f003 0301 and.w r3, r3, #1
8000766: 607b str r3, [r7, #4]
8000768: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800076a: 4b09 ldr r3, [pc, #36] ; (8000790 <HAL_MspInit+0x44>)
800076c: 6d9b ldr r3, [r3, #88] ; 0x58
800076e: 4a08 ldr r2, [pc, #32] ; (8000790 <HAL_MspInit+0x44>)
8000770: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000774: 6593 str r3, [r2, #88] ; 0x58
8000776: 4b06 ldr r3, [pc, #24] ; (8000790 <HAL_MspInit+0x44>)
8000778: 6d9b ldr r3, [r3, #88] ; 0x58
800077a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800077e: 603b str r3, [r7, #0]
8000780: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000782: bf00 nop
8000784: 370c adds r7, #12
8000786: 46bd mov sp, r7
8000788: f85d 7b04 ldr.w r7, [sp], #4
800078c: 4770 bx lr
800078e: bf00 nop
8000790: 40021000 .word 0x40021000
08000794 <HAL_RTC_MspInit>:
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
8000794: b480 push {r7}
8000796: b083 sub sp, #12
8000798: af00 add r7, sp, #0
800079a: 6078 str r0, [r7, #4]
if(hrtc->Instance==RTC)
800079c: 687b ldr r3, [r7, #4]
800079e: 681b ldr r3, [r3, #0]
80007a0: 4a08 ldr r2, [pc, #32] ; (80007c4 <HAL_RTC_MspInit+0x30>)
80007a2: 4293 cmp r3, r2
80007a4: d107 bne.n 80007b6 <HAL_RTC_MspInit+0x22>
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE();
80007a6: 4b08 ldr r3, [pc, #32] ; (80007c8 <HAL_RTC_MspInit+0x34>)
80007a8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80007ac: 4a06 ldr r2, [pc, #24] ; (80007c8 <HAL_RTC_MspInit+0x34>)
80007ae: f443 4300 orr.w r3, r3, #32768 ; 0x8000
80007b2: f8c2 3090 str.w r3, [r2, #144] ; 0x90
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
80007b6: bf00 nop
80007b8: 370c adds r7, #12
80007ba: 46bd mov sp, r7
80007bc: f85d 7b04 ldr.w r7, [sp], #4
80007c0: 4770 bx lr
80007c2: bf00 nop
80007c4: 40002800 .word 0x40002800
80007c8: 40021000 .word 0x40021000
080007cc <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80007cc: b480 push {r7}
80007ce: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
80007d0: bf00 nop
80007d2: 46bd mov sp, r7
80007d4: f85d 7b04 ldr.w r7, [sp], #4
80007d8: 4770 bx lr
080007da <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80007da: b480 push {r7}
80007dc: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80007de: e7fe b.n 80007de <HardFault_Handler+0x4>
080007e0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80007e0: b480 push {r7}
80007e2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80007e4: e7fe b.n 80007e4 <MemManage_Handler+0x4>
080007e6 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80007e6: b480 push {r7}
80007e8: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80007ea: e7fe b.n 80007ea <BusFault_Handler+0x4>
080007ec <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80007ec: b480 push {r7}
80007ee: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80007f0: e7fe b.n 80007f0 <UsageFault_Handler+0x4>
080007f2 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80007f2: b480 push {r7}
80007f4: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80007f6: bf00 nop
80007f8: 46bd mov sp, r7
80007fa: f85d 7b04 ldr.w r7, [sp], #4
80007fe: 4770 bx lr
08000800 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000800: b480 push {r7}
8000802: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000804: bf00 nop
8000806: 46bd mov sp, r7
8000808: f85d 7b04 ldr.w r7, [sp], #4
800080c: 4770 bx lr
0800080e <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800080e: b480 push {r7}
8000810: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000812: bf00 nop
8000814: 46bd mov sp, r7
8000816: f85d 7b04 ldr.w r7, [sp], #4
800081a: 4770 bx lr
0800081c <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
800081c: b580 push {r7, lr}
800081e: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000820: f000 f8b6 bl 8000990 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000824: bf00 nop
8000826: bd80 pop {r7, pc}
08000828 <SystemInit>:
* @param None
* @retval None
*/
void SystemInit(void)
{
8000828: b480 push {r7}
800082a: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
800082c: 4b17 ldr r3, [pc, #92] ; (800088c <SystemInit+0x64>)
800082e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000832: 4a16 ldr r2, [pc, #88] ; (800088c <SystemInit+0x64>)
8000834: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000838: f8c2 3088 str.w r3, [r2, #136] ; 0x88
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC->CR |= RCC_CR_MSION;
800083c: 4b14 ldr r3, [pc, #80] ; (8000890 <SystemInit+0x68>)
800083e: 681b ldr r3, [r3, #0]
8000840: 4a13 ldr r2, [pc, #76] ; (8000890 <SystemInit+0x68>)
8000842: f043 0301 orr.w r3, r3, #1
8000846: 6013 str r3, [r2, #0]
/* Reset CFGR register */
RCC->CFGR = 0x00000000U;
8000848: 4b11 ldr r3, [pc, #68] ; (8000890 <SystemInit+0x68>)
800084a: 2200 movs r2, #0
800084c: 609a str r2, [r3, #8]
/* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC->CR &= 0xEAF6FFFFU;
800084e: 4b10 ldr r3, [pc, #64] ; (8000890 <SystemInit+0x68>)
8000850: 681b ldr r3, [r3, #0]
8000852: 4a0f ldr r2, [pc, #60] ; (8000890 <SystemInit+0x68>)
8000854: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
8000858: f423 2310 bic.w r3, r3, #589824 ; 0x90000
800085c: 6013 str r3, [r2, #0]
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00001000U;
800085e: 4b0c ldr r3, [pc, #48] ; (8000890 <SystemInit+0x68>)
8000860: f44f 5280 mov.w r2, #4096 ; 0x1000
8000864: 60da str r2, [r3, #12]
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
8000866: 4b0a ldr r3, [pc, #40] ; (8000890 <SystemInit+0x68>)
8000868: 681b ldr r3, [r3, #0]
800086a: 4a09 ldr r2, [pc, #36] ; (8000890 <SystemInit+0x68>)
800086c: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000870: 6013 str r3, [r2, #0]
/* Disable all interrupts */
RCC->CIER = 0x00000000U;
8000872: 4b07 ldr r3, [pc, #28] ; (8000890 <SystemInit+0x68>)
8000874: 2200 movs r2, #0
8000876: 619a str r2, [r3, #24]
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
8000878: 4b04 ldr r3, [pc, #16] ; (800088c <SystemInit+0x64>)
800087a: f04f 6200 mov.w r2, #134217728 ; 0x8000000
800087e: 609a str r2, [r3, #8]
#endif
}
8000880: bf00 nop
8000882: 46bd mov sp, r7
8000884: f85d 7b04 ldr.w r7, [sp], #4
8000888: 4770 bx lr
800088a: bf00 nop
800088c: e000ed00 .word 0xe000ed00
8000890: 40021000 .word 0x40021000
08000894 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
8000894: f8df d034 ldr.w sp, [pc, #52] ; 80008cc <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
8000898: f7ff ffc6 bl 8000828 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
800089c: 2100 movs r1, #0
b LoopCopyDataInit
800089e: e003 b.n 80008a8 <LoopCopyDataInit>
080008a0 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
80008a0: 4b0b ldr r3, [pc, #44] ; (80008d0 <LoopForever+0x6>)
ldr r3, [r3, r1]
80008a2: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
80008a4: 5043 str r3, [r0, r1]
adds r1, r1, #4
80008a6: 3104 adds r1, #4
080008a8 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
80008a8: 480a ldr r0, [pc, #40] ; (80008d4 <LoopForever+0xa>)
ldr r3, =_edata
80008aa: 4b0b ldr r3, [pc, #44] ; (80008d8 <LoopForever+0xe>)
adds r2, r0, r1
80008ac: 1842 adds r2, r0, r1
cmp r2, r3
80008ae: 429a cmp r2, r3
bcc CopyDataInit
80008b0: d3f6 bcc.n 80008a0 <CopyDataInit>
ldr r2, =_sbss
80008b2: 4a0a ldr r2, [pc, #40] ; (80008dc <LoopForever+0x12>)
b LoopFillZerobss
80008b4: e002 b.n 80008bc <LoopFillZerobss>
080008b6 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
80008b6: 2300 movs r3, #0
str r3, [r2], #4
80008b8: f842 3b04 str.w r3, [r2], #4
080008bc <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
80008bc: 4b08 ldr r3, [pc, #32] ; (80008e0 <LoopForever+0x16>)
cmp r2, r3
80008be: 429a cmp r2, r3
bcc FillZerobss
80008c0: d3f9 bcc.n 80008b6 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80008c2: f000 fa8d bl 8000de0 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80008c6: f7ff fe6b bl 80005a0 <main>
080008ca <LoopForever>:
LoopForever:
b LoopForever
80008ca: e7fe b.n 80008ca <LoopForever>
ldr sp, =_estack /* Set stack pointer */
80008cc: 20018000 .word 0x20018000
ldr r3, =_sidata
80008d0: 08000e48 .word 0x08000e48
ldr r0, =_sdata
80008d4: 20000000 .word 0x20000000
ldr r3, =_edata
80008d8: 2000000c .word 0x2000000c
ldr r2, =_sbss
80008dc: 2000000c .word 0x2000000c
ldr r3, = _ebss
80008e0: 20000050 .word 0x20000050
080008e4 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80008e4: e7fe b.n 80008e4 <ADC1_2_IRQHandler>
080008e6 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80008e6: b580 push {r7, lr}
80008e8: b082 sub sp, #8
80008ea: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
80008ec: 2300 movs r3, #0
80008ee: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80008f0: 2003 movs r0, #3
80008f2: f000 f91f bl 8000b34 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
80008f6: 2000 movs r0, #0
80008f8: f000 f80e bl 8000918 <HAL_InitTick>
80008fc: 4603 mov r3, r0
80008fe: 2b00 cmp r3, #0
8000900: d002 beq.n 8000908 <HAL_Init+0x22>
{
status = HAL_ERROR;
8000902: 2301 movs r3, #1
8000904: 71fb strb r3, [r7, #7]
8000906: e001 b.n 800090c <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8000908: f7ff ff20 bl 800074c <HAL_MspInit>
}
/* Return function status */
return status;
800090c: 79fb ldrb r3, [r7, #7]
}
800090e: 4618 mov r0, r3
8000910: 3708 adds r7, #8
8000912: 46bd mov sp, r7
8000914: bd80 pop {r7, pc}
...
08000918 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000918: b580 push {r7, lr}
800091a: b084 sub sp, #16
800091c: af00 add r7, sp, #0
800091e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000920: 2300 movs r3, #0
8000922: 73fb strb r3, [r7, #15]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8000924: 4b17 ldr r3, [pc, #92] ; (8000984 <HAL_InitTick+0x6c>)
8000926: 781b ldrb r3, [r3, #0]
8000928: 2b00 cmp r3, #0
800092a: d023 beq.n 8000974 <HAL_InitTick+0x5c>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
800092c: 4b16 ldr r3, [pc, #88] ; (8000988 <HAL_InitTick+0x70>)
800092e: 681a ldr r2, [r3, #0]
8000930: 4b14 ldr r3, [pc, #80] ; (8000984 <HAL_InitTick+0x6c>)
8000932: 781b ldrb r3, [r3, #0]
8000934: 4619 mov r1, r3
8000936: f44f 737a mov.w r3, #1000 ; 0x3e8
800093a: fbb3 f3f1 udiv r3, r3, r1
800093e: fbb2 f3f3 udiv r3, r2, r3
8000942: 4618 mov r0, r3
8000944: f000 f91d bl 8000b82 <HAL_SYSTICK_Config>
8000948: 4603 mov r3, r0
800094a: 2b00 cmp r3, #0
800094c: d10f bne.n 800096e <HAL_InitTick+0x56>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800094e: 687b ldr r3, [r7, #4]
8000950: 2b0f cmp r3, #15
8000952: d809 bhi.n 8000968 <HAL_InitTick+0x50>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000954: 2200 movs r2, #0
8000956: 6879 ldr r1, [r7, #4]
8000958: f04f 30ff mov.w r0, #4294967295
800095c: f000 f8f5 bl 8000b4a <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000960: 4a0a ldr r2, [pc, #40] ; (800098c <HAL_InitTick+0x74>)
8000962: 687b ldr r3, [r7, #4]
8000964: 6013 str r3, [r2, #0]
8000966: e007 b.n 8000978 <HAL_InitTick+0x60>
}
else
{
status = HAL_ERROR;
8000968: 2301 movs r3, #1
800096a: 73fb strb r3, [r7, #15]
800096c: e004 b.n 8000978 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
800096e: 2301 movs r3, #1
8000970: 73fb strb r3, [r7, #15]
8000972: e001 b.n 8000978 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
8000974: 2301 movs r3, #1
8000976: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8000978: 7bfb ldrb r3, [r7, #15]
}
800097a: 4618 mov r0, r3
800097c: 3710 adds r7, #16
800097e: 46bd mov sp, r7
8000980: bd80 pop {r7, pc}
8000982: bf00 nop
8000984: 20000008 .word 0x20000008
8000988: 20000000 .word 0x20000000
800098c: 20000004 .word 0x20000004
08000990 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000990: b480 push {r7}
8000992: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
8000994: 4b06 ldr r3, [pc, #24] ; (80009b0 <HAL_IncTick+0x20>)
8000996: 781b ldrb r3, [r3, #0]
8000998: 461a mov r2, r3
800099a: 4b06 ldr r3, [pc, #24] ; (80009b4 <HAL_IncTick+0x24>)
800099c: 681b ldr r3, [r3, #0]
800099e: 4413 add r3, r2
80009a0: 4a04 ldr r2, [pc, #16] ; (80009b4 <HAL_IncTick+0x24>)
80009a2: 6013 str r3, [r2, #0]
}
80009a4: bf00 nop
80009a6: 46bd mov sp, r7
80009a8: f85d 7b04 ldr.w r7, [sp], #4
80009ac: 4770 bx lr
80009ae: bf00 nop
80009b0: 20000008 .word 0x20000008
80009b4: 2000004c .word 0x2000004c
080009b8 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80009b8: b480 push {r7}
80009ba: af00 add r7, sp, #0
return uwTick;
80009bc: 4b03 ldr r3, [pc, #12] ; (80009cc <HAL_GetTick+0x14>)
80009be: 681b ldr r3, [r3, #0]
}
80009c0: 4618 mov r0, r3
80009c2: 46bd mov sp, r7
80009c4: f85d 7b04 ldr.w r7, [sp], #4
80009c8: 4770 bx lr
80009ca: bf00 nop
80009cc: 2000004c .word 0x2000004c
080009d0 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80009d0: b480 push {r7}
80009d2: b085 sub sp, #20
80009d4: af00 add r7, sp, #0
80009d6: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80009d8: 687b ldr r3, [r7, #4]
80009da: f003 0307 and.w r3, r3, #7
80009de: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80009e0: 4b0c ldr r3, [pc, #48] ; (8000a14 <__NVIC_SetPriorityGrouping+0x44>)
80009e2: 68db ldr r3, [r3, #12]
80009e4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80009e6: 68ba ldr r2, [r7, #8]
80009e8: f64f 03ff movw r3, #63743 ; 0xf8ff
80009ec: 4013 ands r3, r2
80009ee: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80009f0: 68fb ldr r3, [r7, #12]
80009f2: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80009f4: 68bb ldr r3, [r7, #8]
80009f6: 4313 orrs r3, r2
reg_value = (reg_value |
80009f8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
80009fc: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000a00: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000a02: 4a04 ldr r2, [pc, #16] ; (8000a14 <__NVIC_SetPriorityGrouping+0x44>)
8000a04: 68bb ldr r3, [r7, #8]
8000a06: 60d3 str r3, [r2, #12]
}
8000a08: bf00 nop
8000a0a: 3714 adds r7, #20
8000a0c: 46bd mov sp, r7
8000a0e: f85d 7b04 ldr.w r7, [sp], #4
8000a12: 4770 bx lr
8000a14: e000ed00 .word 0xe000ed00
08000a18 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000a18: b480 push {r7}
8000a1a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000a1c: 4b04 ldr r3, [pc, #16] ; (8000a30 <__NVIC_GetPriorityGrouping+0x18>)
8000a1e: 68db ldr r3, [r3, #12]
8000a20: 0a1b lsrs r3, r3, #8
8000a22: f003 0307 and.w r3, r3, #7
}
8000a26: 4618 mov r0, r3
8000a28: 46bd mov sp, r7
8000a2a: f85d 7b04 ldr.w r7, [sp], #4
8000a2e: 4770 bx lr
8000a30: e000ed00 .word 0xe000ed00
08000a34 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000a34: b480 push {r7}
8000a36: b083 sub sp, #12
8000a38: af00 add r7, sp, #0
8000a3a: 4603 mov r3, r0
8000a3c: 6039 str r1, [r7, #0]
8000a3e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000a40: f997 3007 ldrsb.w r3, [r7, #7]
8000a44: 2b00 cmp r3, #0
8000a46: db0a blt.n 8000a5e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000a48: 683b ldr r3, [r7, #0]
8000a4a: b2da uxtb r2, r3
8000a4c: 490c ldr r1, [pc, #48] ; (8000a80 <__NVIC_SetPriority+0x4c>)
8000a4e: f997 3007 ldrsb.w r3, [r7, #7]
8000a52: 0112 lsls r2, r2, #4
8000a54: b2d2 uxtb r2, r2
8000a56: 440b add r3, r1
8000a58: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000a5c: e00a b.n 8000a74 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000a5e: 683b ldr r3, [r7, #0]
8000a60: b2da uxtb r2, r3
8000a62: 4908 ldr r1, [pc, #32] ; (8000a84 <__NVIC_SetPriority+0x50>)
8000a64: 79fb ldrb r3, [r7, #7]
8000a66: f003 030f and.w r3, r3, #15
8000a6a: 3b04 subs r3, #4
8000a6c: 0112 lsls r2, r2, #4
8000a6e: b2d2 uxtb r2, r2
8000a70: 440b add r3, r1
8000a72: 761a strb r2, [r3, #24]
}
8000a74: bf00 nop
8000a76: 370c adds r7, #12
8000a78: 46bd mov sp, r7
8000a7a: f85d 7b04 ldr.w r7, [sp], #4
8000a7e: 4770 bx lr
8000a80: e000e100 .word 0xe000e100
8000a84: e000ed00 .word 0xe000ed00
08000a88 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000a88: b480 push {r7}
8000a8a: b089 sub sp, #36 ; 0x24
8000a8c: af00 add r7, sp, #0
8000a8e: 60f8 str r0, [r7, #12]
8000a90: 60b9 str r1, [r7, #8]
8000a92: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000a94: 68fb ldr r3, [r7, #12]
8000a96: f003 0307 and.w r3, r3, #7
8000a9a: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000a9c: 69fb ldr r3, [r7, #28]
8000a9e: f1c3 0307 rsb r3, r3, #7
8000aa2: 2b04 cmp r3, #4
8000aa4: bf28 it cs
8000aa6: 2304 movcs r3, #4
8000aa8: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000aaa: 69fb ldr r3, [r7, #28]
8000aac: 3304 adds r3, #4
8000aae: 2b06 cmp r3, #6
8000ab0: d902 bls.n 8000ab8 <NVIC_EncodePriority+0x30>
8000ab2: 69fb ldr r3, [r7, #28]
8000ab4: 3b03 subs r3, #3
8000ab6: e000 b.n 8000aba <NVIC_EncodePriority+0x32>
8000ab8: 2300 movs r3, #0
8000aba: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000abc: f04f 32ff mov.w r2, #4294967295
8000ac0: 69bb ldr r3, [r7, #24]
8000ac2: fa02 f303 lsl.w r3, r2, r3
8000ac6: 43da mvns r2, r3
8000ac8: 68bb ldr r3, [r7, #8]
8000aca: 401a ands r2, r3
8000acc: 697b ldr r3, [r7, #20]
8000ace: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000ad0: f04f 31ff mov.w r1, #4294967295
8000ad4: 697b ldr r3, [r7, #20]
8000ad6: fa01 f303 lsl.w r3, r1, r3
8000ada: 43d9 mvns r1, r3
8000adc: 687b ldr r3, [r7, #4]
8000ade: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000ae0: 4313 orrs r3, r2
);
}
8000ae2: 4618 mov r0, r3
8000ae4: 3724 adds r7, #36 ; 0x24
8000ae6: 46bd mov sp, r7
8000ae8: f85d 7b04 ldr.w r7, [sp], #4
8000aec: 4770 bx lr
...
08000af0 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000af0: b580 push {r7, lr}
8000af2: b082 sub sp, #8
8000af4: af00 add r7, sp, #0
8000af6: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000af8: 687b ldr r3, [r7, #4]
8000afa: 3b01 subs r3, #1
8000afc: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8000b00: d301 bcc.n 8000b06 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000b02: 2301 movs r3, #1
8000b04: e00f b.n 8000b26 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000b06: 4a0a ldr r2, [pc, #40] ; (8000b30 <SysTick_Config+0x40>)
8000b08: 687b ldr r3, [r7, #4]
8000b0a: 3b01 subs r3, #1
8000b0c: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000b0e: 210f movs r1, #15
8000b10: f04f 30ff mov.w r0, #4294967295
8000b14: f7ff ff8e bl 8000a34 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000b18: 4b05 ldr r3, [pc, #20] ; (8000b30 <SysTick_Config+0x40>)
8000b1a: 2200 movs r2, #0
8000b1c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000b1e: 4b04 ldr r3, [pc, #16] ; (8000b30 <SysTick_Config+0x40>)
8000b20: 2207 movs r2, #7
8000b22: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000b24: 2300 movs r3, #0
}
8000b26: 4618 mov r0, r3
8000b28: 3708 adds r7, #8
8000b2a: 46bd mov sp, r7
8000b2c: bd80 pop {r7, pc}
8000b2e: bf00 nop
8000b30: e000e010 .word 0xe000e010
08000b34 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000b34: b580 push {r7, lr}
8000b36: b082 sub sp, #8
8000b38: af00 add r7, sp, #0
8000b3a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000b3c: 6878 ldr r0, [r7, #4]
8000b3e: f7ff ff47 bl 80009d0 <__NVIC_SetPriorityGrouping>
}
8000b42: bf00 nop
8000b44: 3708 adds r7, #8
8000b46: 46bd mov sp, r7
8000b48: bd80 pop {r7, pc}
08000b4a <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000b4a: b580 push {r7, lr}
8000b4c: b086 sub sp, #24
8000b4e: af00 add r7, sp, #0
8000b50: 4603 mov r3, r0
8000b52: 60b9 str r1, [r7, #8]
8000b54: 607a str r2, [r7, #4]
8000b56: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8000b58: 2300 movs r3, #0
8000b5a: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000b5c: f7ff ff5c bl 8000a18 <__NVIC_GetPriorityGrouping>
8000b60: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000b62: 687a ldr r2, [r7, #4]
8000b64: 68b9 ldr r1, [r7, #8]
8000b66: 6978 ldr r0, [r7, #20]
8000b68: f7ff ff8e bl 8000a88 <NVIC_EncodePriority>
8000b6c: 4602 mov r2, r0
8000b6e: f997 300f ldrsb.w r3, [r7, #15]
8000b72: 4611 mov r1, r2
8000b74: 4618 mov r0, r3
8000b76: f7ff ff5d bl 8000a34 <__NVIC_SetPriority>
}
8000b7a: bf00 nop
8000b7c: 3718 adds r7, #24
8000b7e: 46bd mov sp, r7
8000b80: bd80 pop {r7, pc}
08000b82 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000b82: b580 push {r7, lr}
8000b84: b082 sub sp, #8
8000b86: af00 add r7, sp, #0
8000b88: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000b8a: 6878 ldr r0, [r7, #4]
8000b8c: f7ff ffb0 bl 8000af0 <SysTick_Config>
8000b90: 4603 mov r3, r0
}
8000b92: 4618 mov r0, r3
8000b94: 3708 adds r7, #8
8000b96: 46bd mov sp, r7
8000b98: bd80 pop {r7, pc}
08000b9a <HAL_RTC_Init>:
* @brief Initialize the RTC peripheral
* @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
8000b9a: b580 push {r7, lr}
8000b9c: b084 sub sp, #16
8000b9e: af00 add r7, sp, #0
8000ba0: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_ERROR;
8000ba2: 2301 movs r3, #1
8000ba4: 73fb strb r3, [r7, #15]
/* Check the RTC peripheral state */
if (hrtc != NULL)
8000ba6: 687b ldr r3, [r7, #4]
8000ba8: 2b00 cmp r3, #0
8000baa: d06c beq.n 8000c86 <HAL_RTC_Init+0xec>
{
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
}
}
#else /* #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
if (hrtc->State == HAL_RTC_STATE_RESET)
8000bac: 687b ldr r3, [r7, #4]
8000bae: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
8000bb2: b2db uxtb r3, r3
8000bb4: 2b00 cmp r3, #0
8000bb6: d106 bne.n 8000bc6 <HAL_RTC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
8000bb8: 687b ldr r3, [r7, #4]
8000bba: 2200 movs r2, #0
8000bbc: f883 2020 strb.w r2, [r3, #32]
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
8000bc0: 6878 ldr r0, [r7, #4]
8000bc2: f7ff fde7 bl 8000794 <HAL_RTC_MspInit>
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
/* Process TAMP ip offset from RTC one */
hrtc->TampOffset = (TAMP_BASE - RTC_BASE);
#endif
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
8000bc6: 687b ldr r3, [r7, #4]
8000bc8: 2202 movs r2, #2
8000bca: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
8000bce: 687b ldr r3, [r7, #4]
8000bd0: 681b ldr r3, [r3, #0]
8000bd2: 22ca movs r2, #202 ; 0xca
8000bd4: 625a str r2, [r3, #36] ; 0x24
8000bd6: 687b ldr r3, [r7, #4]
8000bd8: 681b ldr r3, [r3, #0]
8000bda: 2253 movs r2, #83 ; 0x53
8000bdc: 625a str r2, [r3, #36] ; 0x24
/* Enter Initialization mode */
status = RTC_EnterInitMode(hrtc);
8000bde: 6878 ldr r0, [r7, #4]
8000be0: f000 f87c bl 8000cdc <RTC_EnterInitMode>
8000be4: 4603 mov r3, r0
8000be6: 73fb strb r3, [r7, #15]
if (status == HAL_OK)
8000be8: 7bfb ldrb r3, [r7, #15]
8000bea: 2b00 cmp r3, #0
8000bec: d14b bne.n 8000c86 <HAL_RTC_Init+0xec>
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
/* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */
hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
#else
/* Clear RTC_CR FMT, OSEL and POL Bits */
hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL);
8000bee: 687b ldr r3, [r7, #4]
8000bf0: 681b ldr r3, [r3, #0]
8000bf2: 689b ldr r3, [r3, #8]
8000bf4: 687a ldr r2, [r7, #4]
8000bf6: 6812 ldr r2, [r2, #0]
8000bf8: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000
8000bfc: f023 0340 bic.w r3, r3, #64 ; 0x40
8000c00: 6093 str r3, [r2, #8]
#endif
/* Set RTC_CR register */
hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
8000c02: 687b ldr r3, [r7, #4]
8000c04: 681b ldr r3, [r3, #0]
8000c06: 6899 ldr r1, [r3, #8]
8000c08: 687b ldr r3, [r7, #4]
8000c0a: 685a ldr r2, [r3, #4]
8000c0c: 687b ldr r3, [r7, #4]
8000c0e: 691b ldr r3, [r3, #16]
8000c10: 431a orrs r2, r3
8000c12: 687b ldr r3, [r7, #4]
8000c14: 699b ldr r3, [r3, #24]
8000c16: 431a orrs r2, r3
8000c18: 687b ldr r3, [r7, #4]
8000c1a: 681b ldr r3, [r3, #0]
8000c1c: 430a orrs r2, r1
8000c1e: 609a str r2, [r3, #8]
/* Configure the RTC PRER */
hrtc->Instance->PRER = (hrtc->Init.SynchPrediv);
8000c20: 687b ldr r3, [r7, #4]
8000c22: 681b ldr r3, [r3, #0]
8000c24: 687a ldr r2, [r7, #4]
8000c26: 68d2 ldr r2, [r2, #12]
8000c28: 611a str r2, [r3, #16]
hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
8000c2a: 687b ldr r3, [r7, #4]
8000c2c: 681b ldr r3, [r3, #0]
8000c2e: 6919 ldr r1, [r3, #16]
8000c30: 687b ldr r3, [r7, #4]
8000c32: 689b ldr r3, [r3, #8]
8000c34: 041a lsls r2, r3, #16
8000c36: 687b ldr r3, [r7, #4]
8000c38: 681b ldr r3, [r3, #0]
8000c3a: 430a orrs r2, r1
8000c3c: 611a str r2, [r3, #16]
/* Configure the Binary mode */
MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
#endif
/* Exit Initialization mode */
status = RTC_ExitInitMode(hrtc);
8000c3e: 6878 ldr r0, [r7, #4]
8000c40: f000 f880 bl 8000d44 <RTC_ExitInitMode>
8000c44: 4603 mov r3, r0
8000c46: 73fb strb r3, [r7, #15]
if (status == HAL_OK)
8000c48: 7bfb ldrb r3, [r7, #15]
8000c4a: 2b00 cmp r3, #0
8000c4c: d11b bne.n 8000c86 <HAL_RTC_Init+0xec>
{
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN);
hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
#else
hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
8000c4e: 687b ldr r3, [r7, #4]
8000c50: 681b ldr r3, [r3, #0]
8000c52: 6cda ldr r2, [r3, #76] ; 0x4c
8000c54: 687b ldr r3, [r7, #4]
8000c56: 681b ldr r3, [r3, #0]
8000c58: f022 0203 bic.w r2, r2, #3
8000c5c: 64da str r2, [r3, #76] ; 0x4c
hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
8000c5e: 687b ldr r3, [r7, #4]
8000c60: 681b ldr r3, [r3, #0]
8000c62: 6cd9 ldr r1, [r3, #76] ; 0x4c
8000c64: 687b ldr r3, [r7, #4]
8000c66: 69da ldr r2, [r3, #28]
8000c68: 687b ldr r3, [r7, #4]
8000c6a: 695b ldr r3, [r3, #20]
8000c6c: 431a orrs r2, r3
8000c6e: 687b ldr r3, [r7, #4]
8000c70: 681b ldr r3, [r3, #0]
8000c72: 430a orrs r2, r1
8000c74: 64da str r2, [r3, #76] ; 0x4c
#endif
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8000c76: 687b ldr r3, [r7, #4]
8000c78: 681b ldr r3, [r3, #0]
8000c7a: 22ff movs r2, #255 ; 0xff
8000c7c: 625a str r2, [r3, #36] ; 0x24
hrtc->State = HAL_RTC_STATE_READY;
8000c7e: 687b ldr r3, [r7, #4]
8000c80: 2201 movs r2, #1
8000c82: f883 2021 strb.w r2, [r3, #33] ; 0x21
}
}
}
return status;
8000c86: 7bfb ldrb r3, [r7, #15]
}
8000c88: 4618 mov r0, r3
8000c8a: 3710 adds r7, #16
8000c8c: 46bd mov sp, r7
8000c8e: bd80 pop {r7, pc}
08000c90 <HAL_RTC_WaitForSynchro>:
* correctly copied into the RTC_TR and RTC_DR shadow registers.
* @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
{
8000c90: b580 push {r7, lr}
8000c92: b084 sub sp, #16
8000c94: af00 add r7, sp, #0
8000c96: 6078 str r0, [r7, #4]
/* Clear RSF flag */
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK;
#else
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
8000c98: 687b ldr r3, [r7, #4]
8000c9a: 681b ldr r3, [r3, #0]
8000c9c: 68da ldr r2, [r3, #12]
8000c9e: 687b ldr r3, [r7, #4]
8000ca0: 681b ldr r3, [r3, #0]
8000ca2: f022 02a0 bic.w r2, r2, #160 ; 0xa0
8000ca6: 60da str r2, [r3, #12]
#endif
tickstart = HAL_GetTick();
8000ca8: f7ff fe86 bl 80009b8 <HAL_GetTick>
8000cac: 60f8 str r0, [r7, #12]
/* Wait the registers to be synchronised */
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U)
#else
while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
8000cae: e009 b.n 8000cc4 <HAL_RTC_WaitForSynchro+0x34>
#endif
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
8000cb0: f7ff fe82 bl 80009b8 <HAL_GetTick>
8000cb4: 4602 mov r2, r0
8000cb6: 68fb ldr r3, [r7, #12]
8000cb8: 1ad3 subs r3, r2, r3
8000cba: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8000cbe: d901 bls.n 8000cc4 <HAL_RTC_WaitForSynchro+0x34>
{
return HAL_TIMEOUT;
8000cc0: 2303 movs r3, #3
8000cc2: e007 b.n 8000cd4 <HAL_RTC_WaitForSynchro+0x44>
while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
8000cc4: 687b ldr r3, [r7, #4]
8000cc6: 681b ldr r3, [r3, #0]
8000cc8: 68db ldr r3, [r3, #12]
8000cca: f003 0320 and.w r3, r3, #32
8000cce: 2b00 cmp r3, #0
8000cd0: d0ee beq.n 8000cb0 <HAL_RTC_WaitForSynchro+0x20>
}
}
return HAL_OK;
8000cd2: 2300 movs r3, #0
}
8000cd4: 4618 mov r0, r3
8000cd6: 3710 adds r7, #16
8000cd8: 46bd mov sp, r7
8000cda: bd80 pop {r7, pc}
08000cdc <RTC_EnterInitMode>:
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
8000cdc: b580 push {r7, lr}
8000cde: b084 sub sp, #16
8000ce0: af00 add r7, sp, #0
8000ce2: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
8000ce4: 2300 movs r3, #0
8000ce6: 73fb strb r3, [r7, #15]
hrtc->State = HAL_RTC_STATE_TIMEOUT;
}
}
}
#else /* #if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */
if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
8000ce8: 687b ldr r3, [r7, #4]
8000cea: 681b ldr r3, [r3, #0]
8000cec: 68db ldr r3, [r3, #12]
8000cee: f003 0340 and.w r3, r3, #64 ; 0x40
8000cf2: 2b00 cmp r3, #0
8000cf4: d120 bne.n 8000d38 <RTC_EnterInitMode+0x5c>
{
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
8000cf6: 687b ldr r3, [r7, #4]
8000cf8: 681b ldr r3, [r3, #0]
8000cfa: f04f 32ff mov.w r2, #4294967295
8000cfe: 60da str r2, [r3, #12]
tickstart = HAL_GetTick();
8000d00: f7ff fe5a bl 80009b8 <HAL_GetTick>
8000d04: 60b8 str r0, [r7, #8]
/* Wait till RTC is in INIT state and if Time out is reached exit */
while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT))
8000d06: e00d b.n 8000d24 <RTC_EnterInitMode+0x48>
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
8000d08: f7ff fe56 bl 80009b8 <HAL_GetTick>
8000d0c: 4602 mov r2, r0
8000d0e: 68bb ldr r3, [r7, #8]
8000d10: 1ad3 subs r3, r2, r3
8000d12: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8000d16: d905 bls.n 8000d24 <RTC_EnterInitMode+0x48>
{
status = HAL_TIMEOUT;
8000d18: 2303 movs r3, #3
8000d1a: 73fb strb r3, [r7, #15]
hrtc->State = HAL_RTC_STATE_TIMEOUT;
8000d1c: 687b ldr r3, [r7, #4]
8000d1e: 2203 movs r2, #3
8000d20: f883 2021 strb.w r2, [r3, #33] ; 0x21
while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT))
8000d24: 687b ldr r3, [r7, #4]
8000d26: 681b ldr r3, [r3, #0]
8000d28: 68db ldr r3, [r3, #12]
8000d2a: f003 0340 and.w r3, r3, #64 ; 0x40
8000d2e: 2b00 cmp r3, #0
8000d30: d102 bne.n 8000d38 <RTC_EnterInitMode+0x5c>
8000d32: 7bfb ldrb r3, [r7, #15]
8000d34: 2b03 cmp r3, #3
8000d36: d1e7 bne.n 8000d08 <RTC_EnterInitMode+0x2c>
}
}
}
#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */
return status;
8000d38: 7bfb ldrb r3, [r7, #15]
}
8000d3a: 4618 mov r0, r3
8000d3c: 3710 adds r7, #16
8000d3e: 46bd mov sp, r7
8000d40: bd80 pop {r7, pc}
...
08000d44 <RTC_ExitInitMode>:
* @brief Exit the RTC Initialization mode.
* @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
{
8000d44: b580 push {r7, lr}
8000d46: b084 sub sp, #16
8000d48: af00 add r7, sp, #0
8000d4a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000d4c: 2300 movs r3, #0
8000d4e: 73fb strb r3, [r7, #15]
/* Exit Initialization mode */
#if defined(STM32L412xx) || defined(STM32L422xx) || defined(STM32L4P5xx) || defined(STM32L4Q5xx)
CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
#else
/* Exit Initialization mode */
CLEAR_BIT(RTC->ISR, RTC_ISR_INIT);
8000d50: 4b1a ldr r3, [pc, #104] ; (8000dbc <RTC_ExitInitMode+0x78>)
8000d52: 68db ldr r3, [r3, #12]
8000d54: 4a19 ldr r2, [pc, #100] ; (8000dbc <RTC_ExitInitMode+0x78>)
8000d56: f023 0380 bic.w r3, r3, #128 ; 0x80
8000d5a: 60d3 str r3, [r2, #12]
#endif
/* If CR_BYPSHAD bit = 0, wait for synchro */
if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
8000d5c: 4b17 ldr r3, [pc, #92] ; (8000dbc <RTC_ExitInitMode+0x78>)
8000d5e: 689b ldr r3, [r3, #8]
8000d60: f003 0320 and.w r3, r3, #32
8000d64: 2b00 cmp r3, #0
8000d66: d10c bne.n 8000d82 <RTC_ExitInitMode+0x3e>
{
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
8000d68: 6878 ldr r0, [r7, #4]
8000d6a: f7ff ff91 bl 8000c90 <HAL_RTC_WaitForSynchro>
8000d6e: 4603 mov r3, r0
8000d70: 2b00 cmp r3, #0
8000d72: d01e beq.n 8000db2 <RTC_ExitInitMode+0x6e>
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
8000d74: 687b ldr r3, [r7, #4]
8000d76: 2203 movs r2, #3
8000d78: f883 2021 strb.w r2, [r3, #33] ; 0x21
status = HAL_TIMEOUT;
8000d7c: 2303 movs r3, #3
8000d7e: 73fb strb r3, [r7, #15]
8000d80: e017 b.n 8000db2 <RTC_ExitInitMode+0x6e>
}
}
else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry */
{
/* Clear BYPSHAD bit */
CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
8000d82: 4b0e ldr r3, [pc, #56] ; (8000dbc <RTC_ExitInitMode+0x78>)
8000d84: 689b ldr r3, [r3, #8]
8000d86: 4a0d ldr r2, [pc, #52] ; (8000dbc <RTC_ExitInitMode+0x78>)
8000d88: f023 0320 bic.w r3, r3, #32
8000d8c: 6093 str r3, [r2, #8]
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
8000d8e: 6878 ldr r0, [r7, #4]
8000d90: f7ff ff7e bl 8000c90 <HAL_RTC_WaitForSynchro>
8000d94: 4603 mov r3, r0
8000d96: 2b00 cmp r3, #0
8000d98: d005 beq.n 8000da6 <RTC_ExitInitMode+0x62>
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
8000d9a: 687b ldr r3, [r7, #4]
8000d9c: 2203 movs r2, #3
8000d9e: f883 2021 strb.w r2, [r3, #33] ; 0x21
status = HAL_TIMEOUT;
8000da2: 2303 movs r3, #3
8000da4: 73fb strb r3, [r7, #15]
}
/* Restore BYPSHAD bit */
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
8000da6: 4b05 ldr r3, [pc, #20] ; (8000dbc <RTC_ExitInitMode+0x78>)
8000da8: 689b ldr r3, [r3, #8]
8000daa: 4a04 ldr r2, [pc, #16] ; (8000dbc <RTC_ExitInitMode+0x78>)
8000dac: f043 0320 orr.w r3, r3, #32
8000db0: 6093 str r3, [r2, #8]
}
return status;
8000db2: 7bfb ldrb r3, [r7, #15]
}
8000db4: 4618 mov r0, r3
8000db6: 3710 adds r7, #16
8000db8: 46bd mov sp, r7
8000dba: bd80 pop {r7, pc}
8000dbc: 40002800 .word 0x40002800
08000dc0 <LL_SetSystemCoreClock>:
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
8000dc0: b480 push {r7}
8000dc2: b083 sub sp, #12
8000dc4: af00 add r7, sp, #0
8000dc6: 6078 str r0, [r7, #4]
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
8000dc8: 4a04 ldr r2, [pc, #16] ; (8000ddc <LL_SetSystemCoreClock+0x1c>)
8000dca: 687b ldr r3, [r7, #4]
8000dcc: 6013 str r3, [r2, #0]
}
8000dce: bf00 nop
8000dd0: 370c adds r7, #12
8000dd2: 46bd mov sp, r7
8000dd4: f85d 7b04 ldr.w r7, [sp], #4
8000dd8: 4770 bx lr
8000dda: bf00 nop
8000ddc: 20000000 .word 0x20000000
08000de0 <__libc_init_array>:
8000de0: b570 push {r4, r5, r6, lr}
8000de2: 4e0d ldr r6, [pc, #52] ; (8000e18 <__libc_init_array+0x38>)
8000de4: 4c0d ldr r4, [pc, #52] ; (8000e1c <__libc_init_array+0x3c>)
8000de6: 1ba4 subs r4, r4, r6
8000de8: 10a4 asrs r4, r4, #2
8000dea: 2500 movs r5, #0
8000dec: 42a5 cmp r5, r4
8000dee: d109 bne.n 8000e04 <__libc_init_array+0x24>
8000df0: 4e0b ldr r6, [pc, #44] ; (8000e20 <__libc_init_array+0x40>)
8000df2: 4c0c ldr r4, [pc, #48] ; (8000e24 <__libc_init_array+0x44>)
8000df4: f000 f818 bl 8000e28 <_init>
8000df8: 1ba4 subs r4, r4, r6
8000dfa: 10a4 asrs r4, r4, #2
8000dfc: 2500 movs r5, #0
8000dfe: 42a5 cmp r5, r4
8000e00: d105 bne.n 8000e0e <__libc_init_array+0x2e>
8000e02: bd70 pop {r4, r5, r6, pc}
8000e04: f856 3025 ldr.w r3, [r6, r5, lsl #2]
8000e08: 4798 blx r3
8000e0a: 3501 adds r5, #1
8000e0c: e7ee b.n 8000dec <__libc_init_array+0xc>
8000e0e: f856 3025 ldr.w r3, [r6, r5, lsl #2]
8000e12: 4798 blx r3
8000e14: 3501 adds r5, #1
8000e16: e7f2 b.n 8000dfe <__libc_init_array+0x1e>
8000e18: 08000e40 .word 0x08000e40
8000e1c: 08000e40 .word 0x08000e40
8000e20: 08000e40 .word 0x08000e40
8000e24: 08000e44 .word 0x08000e44
08000e28 <_init>:
8000e28: b5f8 push {r3, r4, r5, r6, r7, lr}
8000e2a: bf00 nop
8000e2c: bcf8 pop {r3, r4, r5, r6, r7}
8000e2e: bc08 pop {r3}
8000e30: 469e mov lr, r3
8000e32: 4770 bx lr
08000e34 <_fini>:
8000e34: b5f8 push {r3, r4, r5, r6, r7, lr}
8000e36: bf00 nop
8000e38: bcf8 pop {r3, r4, r5, r6, r7}
8000e3a: bc08 pop {r3}
8000e3c: 469e mov lr, r3
8000e3e: 4770 bx lr
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