63 lines
No EOL
1.5 KiB
Text
63 lines
No EOL
1.5 KiB
Text
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
* 24Mhz + RTC + LSE
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
|
|
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_1)
|
|
{
|
|
}
|
|
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
|
|
LL_RCC_MSI_Enable();
|
|
|
|
/* Wait till MSI is ready */
|
|
while(LL_RCC_MSI_IsReady() != 1)
|
|
{
|
|
|
|
}
|
|
LL_RCC_MSI_EnablePLLMode();
|
|
LL_RCC_MSI_EnableRangeSelection();
|
|
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
|
|
LL_RCC_MSI_SetCalibTrimming(0);
|
|
LL_PWR_EnableBkUpAccess();
|
|
LL_RCC_ForceBackupDomainReset();
|
|
LL_RCC_ReleaseBackupDomainReset();
|
|
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW);
|
|
LL_RCC_LSE_Enable();
|
|
|
|
/* Wait till LSE is ready */
|
|
while(LL_RCC_LSE_IsReady() != 1)
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
|
|
LL_RCC_EnableRTC();
|
|
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 24, LL_RCC_PLLR_DIV_4);
|
|
LL_RCC_PLL_EnableDomain_SYS();
|
|
LL_RCC_PLL_Enable();
|
|
|
|
/* Wait till PLL is ready */
|
|
while(LL_RCC_PLL_IsReady() != 1)
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
|
|
/* Wait till System clock is ready */
|
|
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
|
{
|
|
|
|
}
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
|
LL_SetSystemCoreClock(24000000);
|
|
|
|
/* Update the time base */
|
|
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
} |