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LoPoSo/RealOne/Debug/RealOne.list
bray f2830f7c22 expe 3 and 4
2020-11-17 10:50:11 +01:00

2636 lines
90 KiB
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RealOne.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00000e0c 08000188 08000188 00010188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000000 08000f94 08000f94 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
3 .ARM.extab 00000000 08000f94 08000f94 0002000c 2**0
CONTENTS
4 .ARM 00000000 08000f94 08000f94 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08000f94 08000f94 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08000f94 08000f94 00010f94 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08000f98 08000f98 00010f98 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08000f9c 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000024 2000000c 08000fa8 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000600 20000030 08000fa8 00020030 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00004be7 00000000 00000000 0002003c 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 00000d51 00000000 00000000 00024c23 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 000005c0 00000000 00000000 00025978 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 00000548 00000000 00000000 00025f38 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 00026337 00000000 00000000 00026480 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 00004155 00000000 00000000 0004c7b7 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 000ee8e8 00000000 00000000 0005090c 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 0013f1f4 2**0
CONTENTS, READONLY
20 .debug_frame 000015dc 00000000 00000000 0013f270 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000000c .word 0x2000000c
80001a4: 00000000 .word 0x00000000
80001a8: 08000f7c .word 0x08000f7c
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000010 .word 0x20000010
80001c4: 08000f7c .word 0x08000f7c
080001c8 <LL_AHB2_GRP1_EnableClock>:
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
80001c8: b480 push {r7}
80001ca: b085 sub sp, #20
80001cc: af00 add r7, sp, #0
80001ce: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB2ENR, Periphs);
80001d0: 4b08 ldr r3, [pc, #32] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
80001d2: 6cda ldr r2, [r3, #76] ; 0x4c
80001d4: 4907 ldr r1, [pc, #28] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
80001d6: 687b ldr r3, [r7, #4]
80001d8: 4313 orrs r3, r2
80001da: 64cb str r3, [r1, #76] ; 0x4c
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
80001dc: 4b05 ldr r3, [pc, #20] ; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
80001de: 6cda ldr r2, [r3, #76] ; 0x4c
80001e0: 687b ldr r3, [r7, #4]
80001e2: 4013 ands r3, r2
80001e4: 60fb str r3, [r7, #12]
(void)tmpreg;
80001e6: 68fb ldr r3, [r7, #12]
}
80001e8: bf00 nop
80001ea: 3714 adds r7, #20
80001ec: 46bd mov sp, r7
80001ee: f85d 7b04 ldr.w r7, [sp], #4
80001f2: 4770 bx lr
80001f4: 40021000 .word 0x40021000
080001f8 <LL_GPIO_SetPinMode>:
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
80001f8: b480 push {r7}
80001fa: b08b sub sp, #44 ; 0x2c
80001fc: af00 add r7, sp, #0
80001fe: 60f8 str r0, [r7, #12]
8000200: 60b9 str r1, [r7, #8]
8000202: 607a str r2, [r7, #4]
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
8000204: 68fb ldr r3, [r7, #12]
8000206: 681a ldr r2, [r3, #0]
8000208: 68bb ldr r3, [r7, #8]
800020a: 617b str r3, [r7, #20]
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800020c: 697b ldr r3, [r7, #20]
800020e: fa93 f3a3 rbit r3, r3
8000212: 613b str r3, [r7, #16]
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8000214: 693b ldr r3, [r7, #16]
8000216: 61bb str r3, [r7, #24]
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
8000218: 69bb ldr r3, [r7, #24]
800021a: 2b00 cmp r3, #0
800021c: d101 bne.n 8000222 <LL_GPIO_SetPinMode+0x2a>
{
return 32U;
800021e: 2320 movs r3, #32
8000220: e003 b.n 800022a <LL_GPIO_SetPinMode+0x32>
}
return __builtin_clz(value);
8000222: 69bb ldr r3, [r7, #24]
8000224: fab3 f383 clz r3, r3
8000228: b2db uxtb r3, r3
800022a: 005b lsls r3, r3, #1
800022c: 2103 movs r1, #3
800022e: fa01 f303 lsl.w r3, r1, r3
8000232: 43db mvns r3, r3
8000234: 401a ands r2, r3
8000236: 68bb ldr r3, [r7, #8]
8000238: 623b str r3, [r7, #32]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800023a: 6a3b ldr r3, [r7, #32]
800023c: fa93 f3a3 rbit r3, r3
8000240: 61fb str r3, [r7, #28]
return result;
8000242: 69fb ldr r3, [r7, #28]
8000244: 627b str r3, [r7, #36] ; 0x24
if (value == 0U)
8000246: 6a7b ldr r3, [r7, #36] ; 0x24
8000248: 2b00 cmp r3, #0
800024a: d101 bne.n 8000250 <LL_GPIO_SetPinMode+0x58>
return 32U;
800024c: 2320 movs r3, #32
800024e: e003 b.n 8000258 <LL_GPIO_SetPinMode+0x60>
return __builtin_clz(value);
8000250: 6a7b ldr r3, [r7, #36] ; 0x24
8000252: fab3 f383 clz r3, r3
8000256: b2db uxtb r3, r3
8000258: 005b lsls r3, r3, #1
800025a: 6879 ldr r1, [r7, #4]
800025c: fa01 f303 lsl.w r3, r1, r3
8000260: 431a orrs r2, r3
8000262: 68fb ldr r3, [r7, #12]
8000264: 601a str r2, [r3, #0]
}
8000266: bf00 nop
8000268: 372c adds r7, #44 ; 0x2c
800026a: 46bd mov sp, r7
800026c: f85d 7b04 ldr.w r7, [sp], #4
8000270: 4770 bx lr
08000272 <LL_GPIO_SetPinOutputType>:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
8000272: b480 push {r7}
8000274: b085 sub sp, #20
8000276: af00 add r7, sp, #0
8000278: 60f8 str r0, [r7, #12]
800027a: 60b9 str r1, [r7, #8]
800027c: 607a str r2, [r7, #4]
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
800027e: 68fb ldr r3, [r7, #12]
8000280: 685a ldr r2, [r3, #4]
8000282: 68bb ldr r3, [r7, #8]
8000284: 43db mvns r3, r3
8000286: 401a ands r2, r3
8000288: 68bb ldr r3, [r7, #8]
800028a: 6879 ldr r1, [r7, #4]
800028c: fb01 f303 mul.w r3, r1, r3
8000290: 431a orrs r2, r3
8000292: 68fb ldr r3, [r7, #12]
8000294: 605a str r2, [r3, #4]
}
8000296: bf00 nop
8000298: 3714 adds r7, #20
800029a: 46bd mov sp, r7
800029c: f85d 7b04 ldr.w r7, [sp], #4
80002a0: 4770 bx lr
080002a2 <LL_GPIO_IsInputPinSet>:
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
80002a2: b480 push {r7}
80002a4: b083 sub sp, #12
80002a6: af00 add r7, sp, #0
80002a8: 6078 str r0, [r7, #4]
80002aa: 6039 str r1, [r7, #0]
return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
80002ac: 687b ldr r3, [r7, #4]
80002ae: 691a ldr r2, [r3, #16]
80002b0: 683b ldr r3, [r7, #0]
80002b2: 4013 ands r3, r2
80002b4: 683a ldr r2, [r7, #0]
80002b6: 429a cmp r2, r3
80002b8: d101 bne.n 80002be <LL_GPIO_IsInputPinSet+0x1c>
80002ba: 2301 movs r3, #1
80002bc: e000 b.n 80002c0 <LL_GPIO_IsInputPinSet+0x1e>
80002be: 2300 movs r3, #0
}
80002c0: 4618 mov r0, r3
80002c2: 370c adds r7, #12
80002c4: 46bd mov sp, r7
80002c6: f85d 7b04 ldr.w r7, [sp], #4
80002ca: 4770 bx lr
080002cc <LL_GPIO_SetOutputPin>:
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
80002cc: b480 push {r7}
80002ce: b083 sub sp, #12
80002d0: af00 add r7, sp, #0
80002d2: 6078 str r0, [r7, #4]
80002d4: 6039 str r1, [r7, #0]
WRITE_REG(GPIOx->BSRR, PinMask);
80002d6: 687b ldr r3, [r7, #4]
80002d8: 683a ldr r2, [r7, #0]
80002da: 619a str r2, [r3, #24]
}
80002dc: bf00 nop
80002de: 370c adds r7, #12
80002e0: 46bd mov sp, r7
80002e2: f85d 7b04 ldr.w r7, [sp], #4
80002e6: 4770 bx lr
080002e8 <LL_GPIO_ResetOutputPin>:
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
80002e8: b480 push {r7}
80002ea: b083 sub sp, #12
80002ec: af00 add r7, sp, #0
80002ee: 6078 str r0, [r7, #4]
80002f0: 6039 str r1, [r7, #0]
WRITE_REG(GPIOx->BRR, PinMask);
80002f2: 687b ldr r3, [r7, #4]
80002f4: 683a ldr r2, [r7, #0]
80002f6: 629a str r2, [r3, #40] ; 0x28
}
80002f8: bf00 nop
80002fa: 370c adds r7, #12
80002fc: 46bd mov sp, r7
80002fe: f85d 7b04 ldr.w r7, [sp], #4
8000302: 4770 bx lr
08000304 <LL_GPIO_TogglePin>:
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
8000304: b480 push {r7}
8000306: b085 sub sp, #20
8000308: af00 add r7, sp, #0
800030a: 6078 str r0, [r7, #4]
800030c: 6039 str r1, [r7, #0]
uint32_t odr = READ_REG(GPIOx->ODR);
800030e: 687b ldr r3, [r7, #4]
8000310: 695b ldr r3, [r3, #20]
8000312: 60fb str r3, [r7, #12]
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
8000314: 68fa ldr r2, [r7, #12]
8000316: 683b ldr r3, [r7, #0]
8000318: 4013 ands r3, r2
800031a: 041a lsls r2, r3, #16
800031c: 68fb ldr r3, [r7, #12]
800031e: 43d9 mvns r1, r3
8000320: 683b ldr r3, [r7, #0]
8000322: 400b ands r3, r1
8000324: 431a orrs r2, r3
8000326: 687b ldr r3, [r7, #4]
8000328: 619a str r2, [r3, #24]
}
800032a: bf00 nop
800032c: 3714 adds r7, #20
800032e: 46bd mov sp, r7
8000330: f85d 7b04 ldr.w r7, [sp], #4
8000334: 4770 bx lr
...
08000338 <GPIO_init>:
#define BUT_PORT GPIOC
#define BUT_PIN LL_GPIO_PIN_13
#define CLK_PIN LL_GPIO_PIN_10
void GPIO_init(void)
{
8000338: b580 push {r7, lr}
800033a: af00 add r7, sp, #0
// PORT A
LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA );
800033c: 2001 movs r0, #1
800033e: f7ff ff43 bl 80001c8 <LL_AHB2_GRP1_EnableClock>
// Green LED (user LED) - PA5
LL_GPIO_SetPinMode( LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT );
8000342: 2201 movs r2, #1
8000344: 2120 movs r1, #32
8000346: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800034a: f7ff ff55 bl 80001f8 <LL_GPIO_SetPinMode>
LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL );
800034e: 2200 movs r2, #0
8000350: 2120 movs r1, #32
8000352: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8000356: f7ff ff8c bl 8000272 <LL_GPIO_SetPinOutputType>
// PORT C
LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC );
800035a: 2004 movs r0, #4
800035c: f7ff ff34 bl 80001c8 <LL_AHB2_GRP1_EnableClock>
// Blue button - PC13
LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT );
8000360: 2200 movs r2, #0
8000362: f44f 5100 mov.w r1, #8192 ; 0x2000
8000366: 4805 ldr r0, [pc, #20] ; (800037c <GPIO_init+0x44>)
8000368: f7ff ff46 bl 80001f8 <LL_GPIO_SetPinMode>
LL_GPIO_SetPinMode( BUT_PORT, CLK_PIN, LL_GPIO_MODE_OUTPUT );
800036c: 2201 movs r2, #1
800036e: f44f 6180 mov.w r1, #1024 ; 0x400
8000372: 4802 ldr r0, [pc, #8] ; (800037c <GPIO_init+0x44>)
8000374: f7ff ff40 bl 80001f8 <LL_GPIO_SetPinMode>
}
8000378: bf00 nop
800037a: bd80 pop {r7, pc}
800037c: 48000800 .word 0x48000800
08000380 <CLK_TOGGLE>:
void CLK_TOGGLE(){
8000380: b580 push {r7, lr}
8000382: af00 add r7, sp, #0
LL_GPIO_TogglePin(BUT_PORT, CLK_PIN);
8000384: f44f 6180 mov.w r1, #1024 ; 0x400
8000388: 4802 ldr r0, [pc, #8] ; (8000394 <CLK_TOGGLE+0x14>)
800038a: f7ff ffbb bl 8000304 <LL_GPIO_TogglePin>
}
800038e: bf00 nop
8000390: bd80 pop {r7, pc}
8000392: bf00 nop
8000394: 48000800 .word 0x48000800
08000398 <LED_GREEN>:
void LED_GREEN( int val )
{
8000398: b580 push {r7, lr}
800039a: b082 sub sp, #8
800039c: af00 add r7, sp, #0
800039e: 6078 str r0, [r7, #4]
if ( val )
80003a0: 687b ldr r3, [r7, #4]
80003a2: 2b00 cmp r3, #0
80003a4: d005 beq.n 80003b2 <LED_GREEN+0x1a>
LL_GPIO_SetOutputPin( LED_PORT, LED_PIN );
80003a6: 2120 movs r1, #32
80003a8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
80003ac: f7ff ff8e bl 80002cc <LL_GPIO_SetOutputPin>
else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
}
80003b0: e004 b.n 80003bc <LED_GREEN+0x24>
else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
80003b2: 2120 movs r1, #32
80003b4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
80003b8: f7ff ff96 bl 80002e8 <LL_GPIO_ResetOutputPin>
}
80003bc: bf00 nop
80003be: 3708 adds r7, #8
80003c0: 46bd mov sp, r7
80003c2: bd80 pop {r7, pc}
080003c4 <BLUE_BUTTON>:
int BLUE_BUTTON()
{
80003c4: b580 push {r7, lr}
80003c6: af00 add r7, sp, #0
return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) );
80003c8: f44f 5100 mov.w r1, #8192 ; 0x2000
80003cc: 4805 ldr r0, [pc, #20] ; (80003e4 <BLUE_BUTTON+0x20>)
80003ce: f7ff ff68 bl 80002a2 <LL_GPIO_IsInputPinSet>
80003d2: 4603 mov r3, r0
80003d4: 2b00 cmp r3, #0
80003d6: bf0c ite eq
80003d8: 2301 moveq r3, #1
80003da: 2300 movne r3, #0
80003dc: b2db uxtb r3, r3
}
80003de: 4618 mov r0, r3
80003e0: bd80 pop {r7, pc}
80003e2: bf00 nop
80003e4: 48000800 .word 0x48000800
080003e8 <LL_RCC_LSE_Enable>:
* @brief Enable Low Speed External (LSE) crystal.
* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
{
80003e8: b480 push {r7}
80003ea: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
80003ec: 4b06 ldr r3, [pc, #24] ; (8000408 <LL_RCC_LSE_Enable+0x20>)
80003ee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80003f2: 4a05 ldr r2, [pc, #20] ; (8000408 <LL_RCC_LSE_Enable+0x20>)
80003f4: f043 0301 orr.w r3, r3, #1
80003f8: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
80003fc: bf00 nop
80003fe: 46bd mov sp, r7
8000400: f85d 7b04 ldr.w r7, [sp], #4
8000404: 4770 bx lr
8000406: bf00 nop
8000408: 40021000 .word 0x40021000
0800040c <LL_RCC_LSE_SetDriveCapability>:
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
* @arg @ref LL_RCC_LSEDRIVE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
{
800040c: b480 push {r7}
800040e: b083 sub sp, #12
8000410: af00 add r7, sp, #0
8000412: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
8000414: 4b07 ldr r3, [pc, #28] ; (8000434 <LL_RCC_LSE_SetDriveCapability+0x28>)
8000416: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800041a: f023 0218 bic.w r2, r3, #24
800041e: 4905 ldr r1, [pc, #20] ; (8000434 <LL_RCC_LSE_SetDriveCapability+0x28>)
8000420: 687b ldr r3, [r7, #4]
8000422: 4313 orrs r3, r2
8000424: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
8000428: bf00 nop
800042a: 370c adds r7, #12
800042c: 46bd mov sp, r7
800042e: f85d 7b04 ldr.w r7, [sp], #4
8000432: 4770 bx lr
8000434: 40021000 .word 0x40021000
08000438 <LL_RCC_LSE_IsReady>:
* @brief Check if LSE oscillator Ready
* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
{
8000438: b480 push {r7}
800043a: af00 add r7, sp, #0
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
800043c: 4b07 ldr r3, [pc, #28] ; (800045c <LL_RCC_LSE_IsReady+0x24>)
800043e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8000442: f003 0302 and.w r3, r3, #2
8000446: 2b02 cmp r3, #2
8000448: d101 bne.n 800044e <LL_RCC_LSE_IsReady+0x16>
800044a: 2301 movs r3, #1
800044c: e000 b.n 8000450 <LL_RCC_LSE_IsReady+0x18>
800044e: 2300 movs r3, #0
}
8000450: 4618 mov r0, r3
8000452: 46bd mov sp, r7
8000454: f85d 7b04 ldr.w r7, [sp], #4
8000458: 4770 bx lr
800045a: bf00 nop
800045c: 40021000 .word 0x40021000
08000460 <LL_RCC_MSI_Enable>:
* @brief Enable MSI oscillator
* @rmtoll CR MSION LL_RCC_MSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
{
8000460: b480 push {r7}
8000462: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSION);
8000464: 4b05 ldr r3, [pc, #20] ; (800047c <LL_RCC_MSI_Enable+0x1c>)
8000466: 681b ldr r3, [r3, #0]
8000468: 4a04 ldr r2, [pc, #16] ; (800047c <LL_RCC_MSI_Enable+0x1c>)
800046a: f043 0301 orr.w r3, r3, #1
800046e: 6013 str r3, [r2, #0]
}
8000470: bf00 nop
8000472: 46bd mov sp, r7
8000474: f85d 7b04 ldr.w r7, [sp], #4
8000478: 4770 bx lr
800047a: bf00 nop
800047c: 40021000 .word 0x40021000
08000480 <LL_RCC_MSI_IsReady>:
* @brief Check if MSI oscillator Ready
* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
{
8000480: b480 push {r7}
8000482: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
8000484: 4b06 ldr r3, [pc, #24] ; (80004a0 <LL_RCC_MSI_IsReady+0x20>)
8000486: 681b ldr r3, [r3, #0]
8000488: f003 0302 and.w r3, r3, #2
800048c: 2b02 cmp r3, #2
800048e: d101 bne.n 8000494 <LL_RCC_MSI_IsReady+0x14>
8000490: 2301 movs r3, #1
8000492: e000 b.n 8000496 <LL_RCC_MSI_IsReady+0x16>
8000494: 2300 movs r3, #0
}
8000496: 4618 mov r0, r3
8000498: 46bd mov sp, r7
800049a: f85d 7b04 ldr.w r7, [sp], #4
800049e: 4770 bx lr
80004a0: 40021000 .word 0x40021000
080004a4 <LL_RCC_MSI_EnablePLLMode>:
* ready
* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
{
80004a4: b480 push {r7}
80004a6: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
80004a8: 4b05 ldr r3, [pc, #20] ; (80004c0 <LL_RCC_MSI_EnablePLLMode+0x1c>)
80004aa: 681b ldr r3, [r3, #0]
80004ac: 4a04 ldr r2, [pc, #16] ; (80004c0 <LL_RCC_MSI_EnablePLLMode+0x1c>)
80004ae: f043 0304 orr.w r3, r3, #4
80004b2: 6013 str r3, [r2, #0]
}
80004b4: bf00 nop
80004b6: 46bd mov sp, r7
80004b8: f85d 7b04 ldr.w r7, [sp], #4
80004bc: 4770 bx lr
80004be: bf00 nop
80004c0: 40021000 .word 0x40021000
080004c4 <LL_RCC_MSI_EnableRangeSelection>:
* MSISRANGE
* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
{
80004c4: b480 push {r7}
80004c6: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
80004c8: 4b05 ldr r3, [pc, #20] ; (80004e0 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
80004ca: 681b ldr r3, [r3, #0]
80004cc: 4a04 ldr r2, [pc, #16] ; (80004e0 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
80004ce: f043 0308 orr.w r3, r3, #8
80004d2: 6013 str r3, [r2, #0]
}
80004d4: bf00 nop
80004d6: 46bd mov sp, r7
80004d8: f85d 7b04 ldr.w r7, [sp], #4
80004dc: 4770 bx lr
80004de: bf00 nop
80004e0: 40021000 .word 0x40021000
080004e4 <LL_RCC_MSI_SetRange>:
* @arg @ref LL_RCC_MSIRANGE_10
* @arg @ref LL_RCC_MSIRANGE_11
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
{
80004e4: b480 push {r7}
80004e6: b083 sub sp, #12
80004e8: af00 add r7, sp, #0
80004ea: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
80004ec: 4b06 ldr r3, [pc, #24] ; (8000508 <LL_RCC_MSI_SetRange+0x24>)
80004ee: 681b ldr r3, [r3, #0]
80004f0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
80004f4: 4904 ldr r1, [pc, #16] ; (8000508 <LL_RCC_MSI_SetRange+0x24>)
80004f6: 687b ldr r3, [r7, #4]
80004f8: 4313 orrs r3, r2
80004fa: 600b str r3, [r1, #0]
}
80004fc: bf00 nop
80004fe: 370c adds r7, #12
8000500: 46bd mov sp, r7
8000502: f85d 7b04 ldr.w r7, [sp], #4
8000506: 4770 bx lr
8000508: 40021000 .word 0x40021000
0800050c <LL_RCC_MSI_SetCalibTrimming>:
* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
* @param Value Between Min_Data = 0 and Max_Data = 255
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
{
800050c: b480 push {r7}
800050e: b083 sub sp, #12
8000510: af00 add r7, sp, #0
8000512: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
8000514: 4b07 ldr r3, [pc, #28] ; (8000534 <LL_RCC_MSI_SetCalibTrimming+0x28>)
8000516: 685b ldr r3, [r3, #4]
8000518: f423 427f bic.w r2, r3, #65280 ; 0xff00
800051c: 687b ldr r3, [r7, #4]
800051e: 021b lsls r3, r3, #8
8000520: 4904 ldr r1, [pc, #16] ; (8000534 <LL_RCC_MSI_SetCalibTrimming+0x28>)
8000522: 4313 orrs r3, r2
8000524: 604b str r3, [r1, #4]
}
8000526: bf00 nop
8000528: 370c adds r7, #12
800052a: 46bd mov sp, r7
800052c: f85d 7b04 ldr.w r7, [sp], #4
8000530: 4770 bx lr
8000532: bf00 nop
8000534: 40021000 .word 0x40021000
08000538 <LL_RCC_SetSysClkSource>:
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
8000538: b480 push {r7}
800053a: b083 sub sp, #12
800053c: af00 add r7, sp, #0
800053e: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
8000540: 4b06 ldr r3, [pc, #24] ; (800055c <LL_RCC_SetSysClkSource+0x24>)
8000542: 689b ldr r3, [r3, #8]
8000544: f023 0203 bic.w r2, r3, #3
8000548: 4904 ldr r1, [pc, #16] ; (800055c <LL_RCC_SetSysClkSource+0x24>)
800054a: 687b ldr r3, [r7, #4]
800054c: 4313 orrs r3, r2
800054e: 608b str r3, [r1, #8]
}
8000550: bf00 nop
8000552: 370c adds r7, #12
8000554: 46bd mov sp, r7
8000556: f85d 7b04 ldr.w r7, [sp], #4
800055a: 4770 bx lr
800055c: 40021000 .word 0x40021000
08000560 <LL_RCC_GetSysClkSource>:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
8000560: b480 push {r7}
8000562: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
8000564: 4b04 ldr r3, [pc, #16] ; (8000578 <LL_RCC_GetSysClkSource+0x18>)
8000566: 689b ldr r3, [r3, #8]
8000568: f003 030c and.w r3, r3, #12
}
800056c: 4618 mov r0, r3
800056e: 46bd mov sp, r7
8000570: f85d 7b04 ldr.w r7, [sp], #4
8000574: 4770 bx lr
8000576: bf00 nop
8000578: 40021000 .word 0x40021000
0800057c <LL_RCC_SetAHBPrescaler>:
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
800057c: b480 push {r7}
800057e: b083 sub sp, #12
8000580: af00 add r7, sp, #0
8000582: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
8000584: 4b06 ldr r3, [pc, #24] ; (80005a0 <LL_RCC_SetAHBPrescaler+0x24>)
8000586: 689b ldr r3, [r3, #8]
8000588: f023 02f0 bic.w r2, r3, #240 ; 0xf0
800058c: 4904 ldr r1, [pc, #16] ; (80005a0 <LL_RCC_SetAHBPrescaler+0x24>)
800058e: 687b ldr r3, [r7, #4]
8000590: 4313 orrs r3, r2
8000592: 608b str r3, [r1, #8]
}
8000594: bf00 nop
8000596: 370c adds r7, #12
8000598: 46bd mov sp, r7
800059a: f85d 7b04 ldr.w r7, [sp], #4
800059e: 4770 bx lr
80005a0: 40021000 .word 0x40021000
080005a4 <LL_RCC_SetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
80005a4: b480 push {r7}
80005a6: b083 sub sp, #12
80005a8: af00 add r7, sp, #0
80005aa: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
80005ac: 4b06 ldr r3, [pc, #24] ; (80005c8 <LL_RCC_SetAPB1Prescaler+0x24>)
80005ae: 689b ldr r3, [r3, #8]
80005b0: f423 62e0 bic.w r2, r3, #1792 ; 0x700
80005b4: 4904 ldr r1, [pc, #16] ; (80005c8 <LL_RCC_SetAPB1Prescaler+0x24>)
80005b6: 687b ldr r3, [r7, #4]
80005b8: 4313 orrs r3, r2
80005ba: 608b str r3, [r1, #8]
}
80005bc: bf00 nop
80005be: 370c adds r7, #12
80005c0: 46bd mov sp, r7
80005c2: f85d 7b04 ldr.w r7, [sp], #4
80005c6: 4770 bx lr
80005c8: 40021000 .word 0x40021000
080005cc <LL_RCC_SetAPB2Prescaler>:
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
{
80005cc: b480 push {r7}
80005ce: b083 sub sp, #12
80005d0: af00 add r7, sp, #0
80005d2: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
80005d4: 4b06 ldr r3, [pc, #24] ; (80005f0 <LL_RCC_SetAPB2Prescaler+0x24>)
80005d6: 689b ldr r3, [r3, #8]
80005d8: f423 5260 bic.w r2, r3, #14336 ; 0x3800
80005dc: 4904 ldr r1, [pc, #16] ; (80005f0 <LL_RCC_SetAPB2Prescaler+0x24>)
80005de: 687b ldr r3, [r7, #4]
80005e0: 4313 orrs r3, r2
80005e2: 608b str r3, [r1, #8]
}
80005e4: bf00 nop
80005e6: 370c adds r7, #12
80005e8: 46bd mov sp, r7
80005ea: f85d 7b04 ldr.w r7, [sp], #4
80005ee: 4770 bx lr
80005f0: 40021000 .word 0x40021000
080005f4 <LL_RCC_SetRTCClockSource>:
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
{
80005f4: b480 push {r7}
80005f6: b083 sub sp, #12
80005f8: af00 add r7, sp, #0
80005fa: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
80005fc: 4b07 ldr r3, [pc, #28] ; (800061c <LL_RCC_SetRTCClockSource+0x28>)
80005fe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8000602: f423 7240 bic.w r2, r3, #768 ; 0x300
8000606: 4905 ldr r1, [pc, #20] ; (800061c <LL_RCC_SetRTCClockSource+0x28>)
8000608: 687b ldr r3, [r7, #4]
800060a: 4313 orrs r3, r2
800060c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
8000610: bf00 nop
8000612: 370c adds r7, #12
8000614: 46bd mov sp, r7
8000616: f85d 7b04 ldr.w r7, [sp], #4
800061a: 4770 bx lr
800061c: 40021000 .word 0x40021000
08000620 <LL_RCC_EnableRTC>:
* @brief Enable RTC
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableRTC(void)
{
8000620: b480 push {r7}
8000622: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
8000624: 4b06 ldr r3, [pc, #24] ; (8000640 <LL_RCC_EnableRTC+0x20>)
8000626: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800062a: 4a05 ldr r2, [pc, #20] ; (8000640 <LL_RCC_EnableRTC+0x20>)
800062c: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8000630: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
8000634: bf00 nop
8000636: 46bd mov sp, r7
8000638: f85d 7b04 ldr.w r7, [sp], #4
800063c: 4770 bx lr
800063e: bf00 nop
8000640: 40021000 .word 0x40021000
08000644 <LL_RCC_ReleaseBackupDomainReset>:
* @brief Release the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
{
8000644: b480 push {r7}
8000646: af00 add r7, sp, #0
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
8000648: 4b06 ldr r3, [pc, #24] ; (8000664 <LL_RCC_ReleaseBackupDomainReset+0x20>)
800064a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800064e: 4a05 ldr r2, [pc, #20] ; (8000664 <LL_RCC_ReleaseBackupDomainReset+0x20>)
8000650: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000654: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
8000658: bf00 nop
800065a: 46bd mov sp, r7
800065c: f85d 7b04 ldr.w r7, [sp], #4
8000660: 4770 bx lr
8000662: bf00 nop
8000664: 40021000 .word 0x40021000
08000668 <LL_RCC_PLL_Enable>:
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
8000668: b480 push {r7}
800066a: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_PLLON);
800066c: 4b05 ldr r3, [pc, #20] ; (8000684 <LL_RCC_PLL_Enable+0x1c>)
800066e: 681b ldr r3, [r3, #0]
8000670: 4a04 ldr r2, [pc, #16] ; (8000684 <LL_RCC_PLL_Enable+0x1c>)
8000672: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8000676: 6013 str r3, [r2, #0]
}
8000678: bf00 nop
800067a: 46bd mov sp, r7
800067c: f85d 7b04 ldr.w r7, [sp], #4
8000680: 4770 bx lr
8000682: bf00 nop
8000684: 40021000 .word 0x40021000
08000688 <LL_RCC_PLL_IsReady>:
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
8000688: b480 push {r7}
800068a: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
800068c: 4b07 ldr r3, [pc, #28] ; (80006ac <LL_RCC_PLL_IsReady+0x24>)
800068e: 681b ldr r3, [r3, #0]
8000690: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000694: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
8000698: d101 bne.n 800069e <LL_RCC_PLL_IsReady+0x16>
800069a: 2301 movs r3, #1
800069c: e000 b.n 80006a0 <LL_RCC_PLL_IsReady+0x18>
800069e: 2300 movs r3, #0
}
80006a0: 4618 mov r0, r3
80006a2: 46bd mov sp, r7
80006a4: f85d 7b04 ldr.w r7, [sp], #4
80006a8: 4770 bx lr
80006aa: bf00 nop
80006ac: 40021000 .word 0x40021000
080006b0 <LL_RCC_PLL_ConfigDomain_SYS>:
* @arg @ref LL_RCC_PLLR_DIV_6
* @arg @ref LL_RCC_PLLR_DIV_8
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
80006b0: b480 push {r7}
80006b2: b085 sub sp, #20
80006b4: af00 add r7, sp, #0
80006b6: 60f8 str r0, [r7, #12]
80006b8: 60b9 str r1, [r7, #8]
80006ba: 607a str r2, [r7, #4]
80006bc: 603b str r3, [r7, #0]
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
80006be: 4b0a ldr r3, [pc, #40] ; (80006e8 <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
80006c0: 68da ldr r2, [r3, #12]
80006c2: 4b0a ldr r3, [pc, #40] ; (80006ec <LL_RCC_PLL_ConfigDomain_SYS+0x3c>)
80006c4: 4013 ands r3, r2
80006c6: 68f9 ldr r1, [r7, #12]
80006c8: 68ba ldr r2, [r7, #8]
80006ca: 4311 orrs r1, r2
80006cc: 687a ldr r2, [r7, #4]
80006ce: 0212 lsls r2, r2, #8
80006d0: 4311 orrs r1, r2
80006d2: 683a ldr r2, [r7, #0]
80006d4: 430a orrs r2, r1
80006d6: 4904 ldr r1, [pc, #16] ; (80006e8 <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
80006d8: 4313 orrs r3, r2
80006da: 60cb str r3, [r1, #12]
Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
}
80006dc: bf00 nop
80006de: 3714 adds r7, #20
80006e0: 46bd mov sp, r7
80006e2: f85d 7b04 ldr.w r7, [sp], #4
80006e6: 4770 bx lr
80006e8: 40021000 .word 0x40021000
80006ec: f9ff808c .word 0xf9ff808c
080006f0 <LL_RCC_PLL_EnableDomain_SYS>:
* @brief Enable PLL output mapped on SYSCLK domain
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
{
80006f0: b480 push {r7}
80006f2: af00 add r7, sp, #0
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
80006f4: 4b05 ldr r3, [pc, #20] ; (800070c <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
80006f6: 68db ldr r3, [r3, #12]
80006f8: 4a04 ldr r2, [pc, #16] ; (800070c <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
80006fa: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
80006fe: 60d3 str r3, [r2, #12]
}
8000700: bf00 nop
8000702: 46bd mov sp, r7
8000704: f85d 7b04 ldr.w r7, [sp], #4
8000708: 4770 bx lr
800070a: bf00 nop
800070c: 40021000 .word 0x40021000
08000710 <LL_APB1_GRP1_EnableClock>:
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
{
8000710: b480 push {r7}
8000712: b085 sub sp, #20
8000714: af00 add r7, sp, #0
8000716: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1ENR1, Periphs);
8000718: 4b08 ldr r3, [pc, #32] ; (800073c <LL_APB1_GRP1_EnableClock+0x2c>)
800071a: 6d9a ldr r2, [r3, #88] ; 0x58
800071c: 4907 ldr r1, [pc, #28] ; (800073c <LL_APB1_GRP1_EnableClock+0x2c>)
800071e: 687b ldr r3, [r7, #4]
8000720: 4313 orrs r3, r2
8000722: 658b str r3, [r1, #88] ; 0x58
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
8000724: 4b05 ldr r3, [pc, #20] ; (800073c <LL_APB1_GRP1_EnableClock+0x2c>)
8000726: 6d9a ldr r2, [r3, #88] ; 0x58
8000728: 687b ldr r3, [r7, #4]
800072a: 4013 ands r3, r2
800072c: 60fb str r3, [r7, #12]
(void)tmpreg;
800072e: 68fb ldr r3, [r7, #12]
}
8000730: bf00 nop
8000732: 3714 adds r7, #20
8000734: 46bd mov sp, r7
8000736: f85d 7b04 ldr.w r7, [sp], #4
800073a: 4770 bx lr
800073c: 40021000 .word 0x40021000
08000740 <LL_FLASH_SetLatency>:
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
8000740: b480 push {r7}
8000742: b083 sub sp, #12
8000744: af00 add r7, sp, #0
8000746: 6078 str r0, [r7, #4]
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
8000748: 4b06 ldr r3, [pc, #24] ; (8000764 <LL_FLASH_SetLatency+0x24>)
800074a: 681b ldr r3, [r3, #0]
800074c: f023 0207 bic.w r2, r3, #7
8000750: 4904 ldr r1, [pc, #16] ; (8000764 <LL_FLASH_SetLatency+0x24>)
8000752: 687b ldr r3, [r7, #4]
8000754: 4313 orrs r3, r2
8000756: 600b str r3, [r1, #0]
}
8000758: bf00 nop
800075a: 370c adds r7, #12
800075c: 46bd mov sp, r7
800075e: f85d 7b04 ldr.w r7, [sp], #4
8000762: 4770 bx lr
8000764: 40022000 .word 0x40022000
08000768 <LL_FLASH_GetLatency>:
* @arg @ref LL_FLASH_LATENCY_15 (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
8000768: b480 push {r7}
800076a: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
800076c: 4b04 ldr r3, [pc, #16] ; (8000780 <LL_FLASH_GetLatency+0x18>)
800076e: 681b ldr r3, [r3, #0]
8000770: f003 0307 and.w r3, r3, #7
}
8000774: 4618 mov r0, r3
8000776: 46bd mov sp, r7
8000778: f85d 7b04 ldr.w r7, [sp], #4
800077c: 4770 bx lr
800077e: bf00 nop
8000780: 40022000 .word 0x40022000
08000784 <LL_SYSTICK_EnableIT>:
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
8000784: b480 push {r7}
8000786: af00 add r7, sp, #0
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
8000788: 4b05 ldr r3, [pc, #20] ; (80007a0 <LL_SYSTICK_EnableIT+0x1c>)
800078a: 681b ldr r3, [r3, #0]
800078c: 4a04 ldr r2, [pc, #16] ; (80007a0 <LL_SYSTICK_EnableIT+0x1c>)
800078e: f043 0302 orr.w r3, r3, #2
8000792: 6013 str r3, [r2, #0]
}
8000794: bf00 nop
8000796: 46bd mov sp, r7
8000798: f85d 7b04 ldr.w r7, [sp], #4
800079c: 4770 bx lr
800079e: bf00 nop
80007a0: e000e010 .word 0xe000e010
080007a4 <LL_LPM_EnableSleep>:
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
80007a4: b480 push {r7}
80007a6: af00 add r7, sp, #0
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
80007a8: 4b05 ldr r3, [pc, #20] ; (80007c0 <LL_LPM_EnableSleep+0x1c>)
80007aa: 691b ldr r3, [r3, #16]
80007ac: 4a04 ldr r2, [pc, #16] ; (80007c0 <LL_LPM_EnableSleep+0x1c>)
80007ae: f023 0304 bic.w r3, r3, #4
80007b2: 6113 str r3, [r2, #16]
}
80007b4: bf00 nop
80007b6: 46bd mov sp, r7
80007b8: f85d 7b04 ldr.w r7, [sp], #4
80007bc: 4770 bx lr
80007be: bf00 nop
80007c0: e000ed00 .word 0xe000ed00
080007c4 <LL_PWR_SetRegulVoltageScaling>:
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
{
80007c4: b480 push {r7}
80007c6: b083 sub sp, #12
80007c8: af00 add r7, sp, #0
80007ca: 6078 str r0, [r7, #4]
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
80007cc: 4b06 ldr r3, [pc, #24] ; (80007e8 <LL_PWR_SetRegulVoltageScaling+0x24>)
80007ce: 681b ldr r3, [r3, #0]
80007d0: f423 62c0 bic.w r2, r3, #1536 ; 0x600
80007d4: 4904 ldr r1, [pc, #16] ; (80007e8 <LL_PWR_SetRegulVoltageScaling+0x24>)
80007d6: 687b ldr r3, [r7, #4]
80007d8: 4313 orrs r3, r2
80007da: 600b str r3, [r1, #0]
}
80007dc: bf00 nop
80007de: 370c adds r7, #12
80007e0: 46bd mov sp, r7
80007e2: f85d 7b04 ldr.w r7, [sp], #4
80007e6: 4770 bx lr
80007e8: 40007000 .word 0x40007000
080007ec <LL_PWR_EnableBkUpAccess>:
* @brief Enable access to the backup domain
* @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
80007ec: b480 push {r7}
80007ee: af00 add r7, sp, #0
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80007f0: 4b05 ldr r3, [pc, #20] ; (8000808 <LL_PWR_EnableBkUpAccess+0x1c>)
80007f2: 681b ldr r3, [r3, #0]
80007f4: 4a04 ldr r2, [pc, #16] ; (8000808 <LL_PWR_EnableBkUpAccess+0x1c>)
80007f6: f443 7380 orr.w r3, r3, #256 ; 0x100
80007fa: 6013 str r3, [r2, #0]
}
80007fc: bf00 nop
80007fe: 46bd mov sp, r7
8000800: f85d 7b04 ldr.w r7, [sp], #4
8000804: 4770 bx lr
8000806: bf00 nop
8000808: 40007000 .word 0x40007000
0800080c <LL_PWR_DisableBkUpAccess>:
* @brief Disable access to the backup domain
* @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
800080c: b480 push {r7}
800080e: af00 add r7, sp, #0
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
8000810: 4b05 ldr r3, [pc, #20] ; (8000828 <LL_PWR_DisableBkUpAccess+0x1c>)
8000812: 681b ldr r3, [r3, #0]
8000814: 4a04 ldr r2, [pc, #16] ; (8000828 <LL_PWR_DisableBkUpAccess+0x1c>)
8000816: f423 7380 bic.w r3, r3, #256 ; 0x100
800081a: 6013 str r3, [r2, #0]
}
800081c: bf00 nop
800081e: 46bd mov sp, r7
8000820: f85d 7b04 ldr.w r7, [sp], #4
8000824: 4770 bx lr
8000826: bf00 nop
8000828: 40007000 .word 0x40007000
0800082c <SysTick_Handler>:
volatile uint32_t msTicks = 0;
volatile uint8_t expe = 0;
volatile uint8_t blue_mode = 0;
void SysTick_Handler()
{
800082c: b580 push {r7, lr}
800082e: af00 add r7, sp, #0
if ( BLUE_BUTTON() ){
8000830: f7ff fdc8 bl 80003c4 <BLUE_BUTTON>
8000834: 4603 mov r3, r0
8000836: 2b00 cmp r3, #0
8000838: d002 beq.n 8000840 <SysTick_Handler+0x14>
blue_mode = 1 ;
800083a: 4b18 ldr r3, [pc, #96] ; (800089c <SysTick_Handler+0x70>)
800083c: 2201 movs r2, #1
800083e: 701a strb r2, [r3, #0]
}
msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
8000840: 4b17 ldr r3, [pc, #92] ; (80008a0 <SysTick_Handler+0x74>)
8000842: 681b ldr r3, [r3, #0]
8000844: 3301 adds r3, #1
8000846: 4a16 ldr r2, [pc, #88] ; (80008a0 <SysTick_Handler+0x74>)
8000848: 6013 str r3, [r2, #0]
if (msTicks == 5 * expe){
800084a: 4b16 ldr r3, [pc, #88] ; (80008a4 <SysTick_Handler+0x78>)
800084c: 781b ldrb r3, [r3, #0]
800084e: b2db uxtb r3, r3
8000850: 461a mov r2, r3
8000852: 4613 mov r3, r2
8000854: 009b lsls r3, r3, #2
8000856: 4413 add r3, r2
8000858: 461a mov r2, r3
800085a: 4b11 ldr r3, [pc, #68] ; (80008a0 <SysTick_Handler+0x74>)
800085c: 681b ldr r3, [r3, #0]
800085e: 429a cmp r2, r3
8000860: d103 bne.n 800086a <SysTick_Handler+0x3e>
LED_GREEN(0);
8000862: 2000 movs r0, #0
8000864: f7ff fd98 bl 8000398 <LED_GREEN>
8000868: e009 b.n 800087e <SysTick_Handler+0x52>
}else if(msTicks >= 200){
800086a: 4b0d ldr r3, [pc, #52] ; (80008a0 <SysTick_Handler+0x74>)
800086c: 681b ldr r3, [r3, #0]
800086e: 2bc7 cmp r3, #199 ; 0xc7
8000870: d905 bls.n 800087e <SysTick_Handler+0x52>
msTicks = 0;
8000872: 4b0b ldr r3, [pc, #44] ; (80008a0 <SysTick_Handler+0x74>)
8000874: 2200 movs r2, #0
8000876: 601a str r2, [r3, #0]
LED_GREEN(1);
8000878: 2001 movs r0, #1
800087a: f7ff fd8d bl 8000398 <LED_GREEN>
}
if(expe == 2 || expe == 4){
800087e: 4b09 ldr r3, [pc, #36] ; (80008a4 <SysTick_Handler+0x78>)
8000880: 781b ldrb r3, [r3, #0]
8000882: b2db uxtb r3, r3
8000884: 2b02 cmp r3, #2
8000886: d004 beq.n 8000892 <SysTick_Handler+0x66>
8000888: 4b06 ldr r3, [pc, #24] ; (80008a4 <SysTick_Handler+0x78>)
800088a: 781b ldrb r3, [r3, #0]
800088c: b2db uxtb r3, r3
800088e: 2b04 cmp r3, #4
8000890: d101 bne.n 8000896 <SysTick_Handler+0x6a>
CLK_TOGGLE();
8000892: f7ff fd75 bl 8000380 <CLK_TOGGLE>
}
}
8000896: bf00 nop
8000898: bd80 pop {r7, pc}
800089a: bf00 nop
800089c: 2000002d .word 0x2000002d
80008a0: 20000028 .word 0x20000028
80008a4: 2000002c .word 0x2000002c
080008a8 <main>:
int main(void)
{
80008a8: b580 push {r7, lr}
80008aa: af00 add r7, sp, #0
// config GPIO
GPIO_init();
80008ac: f7ff fd44 bl 8000338 <GPIO_init>
// if (RCC->BDCR & RCC_BDCR_LSEON) {
LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
80008b0: f04f 5080 mov.w r0, #268435456 ; 0x10000000
80008b4: f7ff ff2c bl 8000710 <LL_APB1_GRP1_EnableClock>
LL_PWR_EnableBkUpAccess();
80008b8: f7ff ff98 bl 80007ec <LL_PWR_EnableBkUpAccess>
//expe = register RTC
expe = RTC->BKP0R;
80008bc: 4b35 ldr r3, [pc, #212] ; (8000994 <main+0xec>)
80008be: 6d1b ldr r3, [r3, #80] ; 0x50
80008c0: b2da uxtb r2, r3
80008c2: 4b35 ldr r3, [pc, #212] ; (8000998 <main+0xf0>)
80008c4: 701a strb r2, [r3, #0]
if (expe == 0) {
80008c6: 4b34 ldr r3, [pc, #208] ; (8000998 <main+0xf0>)
80008c8: 781b ldrb r3, [r3, #0]
80008ca: b2db uxtb r3, r3
80008cc: 2b00 cmp r3, #0
80008ce: d10f bne.n 80008f0 <main+0x48>
SystemClock_Config_24M_LSE();
80008d0: f000 f8ce bl 8000a70 <SystemClock_Config_24M_LSE>
expe = 1;
80008d4: 4b30 ldr r3, [pc, #192] ; (8000998 <main+0xf0>)
80008d6: 2201 movs r2, #1
80008d8: 701a strb r2, [r3, #0]
LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
80008da: f04f 5080 mov.w r0, #268435456 ; 0x10000000
80008de: f7ff ff17 bl 8000710 <LL_APB1_GRP1_EnableClock>
LL_PWR_EnableBkUpAccess();
80008e2: f7ff ff83 bl 80007ec <LL_PWR_EnableBkUpAccess>
RTC->BKP0R = expe;
80008e6: 4b2c ldr r3, [pc, #176] ; (8000998 <main+0xf0>)
80008e8: 781b ldrb r3, [r3, #0]
80008ea: b2da uxtb r2, r3
80008ec: 4b29 ldr r3, [pc, #164] ; (8000994 <main+0xec>)
80008ee: 651a str r2, [r3, #80] ; 0x50
}
if (BLUE_BUTTON()){
80008f0: f7ff fd68 bl 80003c4 <BLUE_BUTTON>
80008f4: 4603 mov r3, r0
80008f6: 2b00 cmp r3, #0
80008f8: d013 beq.n 8000922 <main+0x7a>
expe ++;
80008fa: 4b27 ldr r3, [pc, #156] ; (8000998 <main+0xf0>)
80008fc: 781b ldrb r3, [r3, #0]
80008fe: b2db uxtb r3, r3
8000900: 3301 adds r3, #1
8000902: b2da uxtb r2, r3
8000904: 4b24 ldr r3, [pc, #144] ; (8000998 <main+0xf0>)
8000906: 701a strb r2, [r3, #0]
if (expe > 4) expe = 1;
8000908: 4b23 ldr r3, [pc, #140] ; (8000998 <main+0xf0>)
800090a: 781b ldrb r3, [r3, #0]
800090c: b2db uxtb r3, r3
800090e: 2b04 cmp r3, #4
8000910: d902 bls.n 8000918 <main+0x70>
8000912: 4b21 ldr r3, [pc, #132] ; (8000998 <main+0xf0>)
8000914: 2201 movs r2, #1
8000916: 701a strb r2, [r3, #0]
RTC->BKP0R = expe;
8000918: 4b1f ldr r3, [pc, #124] ; (8000998 <main+0xf0>)
800091a: 781b ldrb r3, [r3, #0]
800091c: b2da uxtb r2, r3
800091e: 4b1d ldr r3, [pc, #116] ; (8000994 <main+0xec>)
8000920: 651a str r2, [r3, #80] ; 0x50
}
// }else{
// }
LL_PWR_DisableBkUpAccess();
8000922: f7ff ff73 bl 800080c <LL_PWR_DisableBkUpAccess>
switch(expe){
8000926: 4b1c ldr r3, [pc, #112] ; (8000998 <main+0xf0>)
8000928: 781b ldrb r3, [r3, #0]
800092a: b2db uxtb r3, r3
800092c: 2b01 cmp r3, #1
800092e: d002 beq.n 8000936 <main+0x8e>
8000930: 2b02 cmp r3, #2
8000932: d003 beq.n 800093c <main+0x94>
8000934: e005 b.n 8000942 <main+0x9a>
case 1:
/* Configure the system clock */
SystemClock_Config_80M();
8000936: f000 f901 bl 8000b3c <SystemClock_Config_80M>
break;
800093a: e005 b.n 8000948 <main+0xa0>
case 2:
/* Configure the system clock */
SystemClock_Config_24M_LSE();
800093c: f000 f898 bl 8000a70 <SystemClock_Config_24M_LSE>
break;
8000940: e002 b.n 8000948 <main+0xa0>
default: //case 3 to 8
SystemClock_Config_24M_LSE_FL3_VS2();
8000942: f000 f82f bl 80009a4 <SystemClock_Config_24M_LSE_FL3_VS2>
break;
8000946: bf00 nop
}
// init systick timer (tick period at 1 ms)
LL_Init1msTick( SystemCoreClock );
8000948: 4b14 ldr r3, [pc, #80] ; (800099c <main+0xf4>)
800094a: 681b ldr r3, [r3, #0]
800094c: 4618 mov r0, r3
800094e: f000 fad5 bl 8000efc <LL_Init1msTick>
LL_SYSTICK_EnableIT();
8000952: f7ff ff17 bl 8000784 <LL_SYSTICK_EnableIT>
//Setup Sleep mode
LL_LPM_EnableSleep();
8000956: f7ff ff25 bl 80007a4 <LL_LPM_EnableSleep>
//LL_LPM_EnableSleepOnExit();
while (1) {
if (blue_mode){
800095a: 4b11 ldr r3, [pc, #68] ; (80009a0 <main+0xf8>)
800095c: 781b ldrb r3, [r3, #0]
800095e: b2db uxtb r3, r3
8000960: 2b00 cmp r3, #0
8000962: d0fa beq.n 800095a <main+0xb2>
switch(expe){
8000964: 4b0c ldr r3, [pc, #48] ; (8000998 <main+0xf0>)
8000966: 781b ldrb r3, [r3, #0]
8000968: b2db uxtb r3, r3
800096a: 3b01 subs r3, #1
800096c: 2b03 cmp r3, #3
800096e: d8f4 bhi.n 800095a <main+0xb2>
8000970: a201 add r2, pc, #4 ; (adr r2, 8000978 <main+0xd0>)
8000972: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8000976: bf00 nop
8000978: 08000989 .word 0x08000989
800097c: 0800098d .word 0x0800098d
8000980: 08000989 .word 0x08000989
8000984: 0800098d .word 0x0800098d
case 1:
case 3:
__WFI();
8000988: bf30 wfi
break;
800098a: e002 b.n 8000992 <main+0xea>
case 2:
case 4:
LL_RCC_MSI_EnablePLLMode();
800098c: f7ff fd8a bl 80004a4 <LL_RCC_MSI_EnablePLLMode>
break;
8000990: bf00 nop
if (blue_mode){
8000992: e7e2 b.n 800095a <main+0xb2>
8000994: 40002800 .word 0x40002800
8000998: 2000002c .word 0x2000002c
800099c: 20000000 .word 0x20000000
80009a0: 2000002d .word 0x2000002d
080009a4 <SystemClock_Config_24M_LSE_FL3_VS2>:
}
}
}
void SystemClock_Config_24M_LSE_FL3_VS2(void){
80009a4: b580 push {r7, lr}
80009a6: af00 add r7, sp, #0
LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
80009a8: f04f 5080 mov.w r0, #268435456 ; 0x10000000
80009ac: f7ff feb0 bl 8000710 <LL_APB1_GRP1_EnableClock>
LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
80009b0: 2003 movs r0, #3
80009b2: f7ff fec5 bl 8000740 <LL_FLASH_SetLatency>
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_3)
80009b6: bf00 nop
80009b8: f7ff fed6 bl 8000768 <LL_FLASH_GetLatency>
80009bc: 4603 mov r3, r0
80009be: 2b03 cmp r3, #3
80009c0: d1fa bne.n 80009b8 <SystemClock_Config_24M_LSE_FL3_VS2+0x14>
{
}
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
80009c2: f44f 6080 mov.w r0, #1024 ; 0x400
80009c6: f7ff fefd bl 80007c4 <LL_PWR_SetRegulVoltageScaling>
LL_RCC_MSI_Enable();
80009ca: f7ff fd49 bl 8000460 <LL_RCC_MSI_Enable>
/* Wait till MSI is ready */
while(LL_RCC_MSI_IsReady() != 1)
80009ce: bf00 nop
80009d0: f7ff fd56 bl 8000480 <LL_RCC_MSI_IsReady>
80009d4: 4603 mov r3, r0
80009d6: 2b01 cmp r3, #1
80009d8: d1fa bne.n 80009d0 <SystemClock_Config_24M_LSE_FL3_VS2+0x2c>
{
}
LL_PWR_EnableBkUpAccess();
80009da: f7ff ff07 bl 80007ec <LL_PWR_EnableBkUpAccess>
// LL_RCC_ForceBackupDomainReset();
LL_RCC_ReleaseBackupDomainReset();
80009de: f7ff fe31 bl 8000644 <LL_RCC_ReleaseBackupDomainReset>
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW);
80009e2: 2000 movs r0, #0
80009e4: f7ff fd12 bl 800040c <LL_RCC_LSE_SetDriveCapability>
LL_RCC_MSI_EnableRangeSelection();
80009e8: f7ff fd6c bl 80004c4 <LL_RCC_MSI_EnableRangeSelection>
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
80009ec: 2060 movs r0, #96 ; 0x60
80009ee: f7ff fd79 bl 80004e4 <LL_RCC_MSI_SetRange>
LL_RCC_MSI_SetCalibTrimming(0);
80009f2: 2000 movs r0, #0
80009f4: f7ff fd8a bl 800050c <LL_RCC_MSI_SetCalibTrimming>
// LL_RCC_MSI_EnablePLLMode();
LL_RCC_LSE_Enable();
80009f8: f7ff fcf6 bl 80003e8 <LL_RCC_LSE_Enable>
/* Wait till LSE is ready */
while(LL_RCC_LSE_IsReady() != 1)
80009fc: bf00 nop
80009fe: f7ff fd1b bl 8000438 <LL_RCC_LSE_IsReady>
8000a02: 4603 mov r3, r0
8000a04: 2b01 cmp r3, #1
8000a06: d1fa bne.n 80009fe <SystemClock_Config_24M_LSE_FL3_VS2+0x5a>
{
}
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
8000a08: f44f 7080 mov.w r0, #256 ; 0x100
8000a0c: f7ff fdf2 bl 80005f4 <LL_RCC_SetRTCClockSource>
LL_RCC_EnableRTC();
8000a10: f7ff fe06 bl 8000620 <LL_RCC_EnableRTC>
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 24, LL_RCC_PLLR_DIV_4);
8000a14: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8000a18: 2218 movs r2, #24
8000a1a: 2100 movs r1, #0
8000a1c: 2001 movs r0, #1
8000a1e: f7ff fe47 bl 80006b0 <LL_RCC_PLL_ConfigDomain_SYS>
LL_RCC_PLL_EnableDomain_SYS();
8000a22: f7ff fe65 bl 80006f0 <LL_RCC_PLL_EnableDomain_SYS>
LL_RCC_PLL_Enable();
8000a26: f7ff fe1f bl 8000668 <LL_RCC_PLL_Enable>
/* Wait till PLL is ready */
while(LL_RCC_PLL_IsReady() != 1)
8000a2a: bf00 nop
8000a2c: f7ff fe2c bl 8000688 <LL_RCC_PLL_IsReady>
8000a30: 4603 mov r3, r0
8000a32: 2b01 cmp r3, #1
8000a34: d1fa bne.n 8000a2c <SystemClock_Config_24M_LSE_FL3_VS2+0x88>
{
}
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
8000a36: 2003 movs r0, #3
8000a38: f7ff fd7e bl 8000538 <LL_RCC_SetSysClkSource>
/* Wait till System clock is ready */
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
8000a3c: bf00 nop
8000a3e: f7ff fd8f bl 8000560 <LL_RCC_GetSysClkSource>
8000a42: 4603 mov r3, r0
8000a44: 2b0c cmp r3, #12
8000a46: d1fa bne.n 8000a3e <SystemClock_Config_24M_LSE_FL3_VS2+0x9a>
{
}
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
8000a48: 2000 movs r0, #0
8000a4a: f7ff fd97 bl 800057c <LL_RCC_SetAHBPrescaler>
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
8000a4e: 2000 movs r0, #0
8000a50: f7ff fda8 bl 80005a4 <LL_RCC_SetAPB1Prescaler>
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
8000a54: 2000 movs r0, #0
8000a56: f7ff fdb9 bl 80005cc <LL_RCC_SetAPB2Prescaler>
LL_SetSystemCoreClock(24000000);
8000a5a: 4804 ldr r0, [pc, #16] ; (8000a6c <SystemClock_Config_24M_LSE_FL3_VS2+0xc8>)
8000a5c: f000 fa5a bl 8000f14 <LL_SetSystemCoreClock>
/* Update the time base */
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
8000a60: 2000 movs r0, #0
8000a62: f000 f93f bl 8000ce4 <HAL_InitTick>
{
// Error_Handler();
}
}
8000a66: bf00 nop
8000a68: bd80 pop {r7, pc}
8000a6a: bf00 nop
8000a6c: 016e3600 .word 0x016e3600
08000a70 <SystemClock_Config_24M_LSE>:
* @brief System Clock Configuration
* @retval None
* 24Mhz + RTC + LSE
*/
void SystemClock_Config_24M_LSE(void)
{
8000a70: b580 push {r7, lr}
8000a72: af00 add r7, sp, #0
LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
8000a74: f04f 5080 mov.w r0, #268435456 ; 0x10000000
8000a78: f7ff fe4a bl 8000710 <LL_APB1_GRP1_EnableClock>
LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
8000a7c: 2001 movs r0, #1
8000a7e: f7ff fe5f bl 8000740 <LL_FLASH_SetLatency>
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_1)
8000a82: bf00 nop
8000a84: f7ff fe70 bl 8000768 <LL_FLASH_GetLatency>
8000a88: 4603 mov r3, r0
8000a8a: 2b01 cmp r3, #1
8000a8c: d1fa bne.n 8000a84 <SystemClock_Config_24M_LSE+0x14>
{
}
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
8000a8e: f44f 7000 mov.w r0, #512 ; 0x200
8000a92: f7ff fe97 bl 80007c4 <LL_PWR_SetRegulVoltageScaling>
LL_RCC_MSI_Enable();
8000a96: f7ff fce3 bl 8000460 <LL_RCC_MSI_Enable>
/* Wait till MSI is ready */
while(LL_RCC_MSI_IsReady() != 1)
8000a9a: bf00 nop
8000a9c: f7ff fcf0 bl 8000480 <LL_RCC_MSI_IsReady>
8000aa0: 4603 mov r3, r0
8000aa2: 2b01 cmp r3, #1
8000aa4: d1fa bne.n 8000a9c <SystemClock_Config_24M_LSE+0x2c>
{
}
LL_PWR_EnableBkUpAccess();
8000aa6: f7ff fea1 bl 80007ec <LL_PWR_EnableBkUpAccess>
// LL_RCC_ForceBackupDomainReset();
LL_RCC_ReleaseBackupDomainReset();
8000aaa: f7ff fdcb bl 8000644 <LL_RCC_ReleaseBackupDomainReset>
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW);
8000aae: 2000 movs r0, #0
8000ab0: f7ff fcac bl 800040c <LL_RCC_LSE_SetDriveCapability>
LL_RCC_MSI_EnableRangeSelection();
8000ab4: f7ff fd06 bl 80004c4 <LL_RCC_MSI_EnableRangeSelection>
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
8000ab8: 2060 movs r0, #96 ; 0x60
8000aba: f7ff fd13 bl 80004e4 <LL_RCC_MSI_SetRange>
LL_RCC_MSI_SetCalibTrimming(0);
8000abe: 2000 movs r0, #0
8000ac0: f7ff fd24 bl 800050c <LL_RCC_MSI_SetCalibTrimming>
// LL_RCC_MSI_EnablePLLMode();
LL_RCC_LSE_Enable();
8000ac4: f7ff fc90 bl 80003e8 <LL_RCC_LSE_Enable>
/* Wait till LSE is ready */
while(LL_RCC_LSE_IsReady() != 1)
8000ac8: bf00 nop
8000aca: f7ff fcb5 bl 8000438 <LL_RCC_LSE_IsReady>
8000ace: 4603 mov r3, r0
8000ad0: 2b01 cmp r3, #1
8000ad2: d1fa bne.n 8000aca <SystemClock_Config_24M_LSE+0x5a>
{
}
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
8000ad4: f44f 7080 mov.w r0, #256 ; 0x100
8000ad8: f7ff fd8c bl 80005f4 <LL_RCC_SetRTCClockSource>
LL_RCC_EnableRTC();
8000adc: f7ff fda0 bl 8000620 <LL_RCC_EnableRTC>
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 24, LL_RCC_PLLR_DIV_4);
8000ae0: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8000ae4: 2218 movs r2, #24
8000ae6: 2100 movs r1, #0
8000ae8: 2001 movs r0, #1
8000aea: f7ff fde1 bl 80006b0 <LL_RCC_PLL_ConfigDomain_SYS>
LL_RCC_PLL_EnableDomain_SYS();
8000aee: f7ff fdff bl 80006f0 <LL_RCC_PLL_EnableDomain_SYS>
LL_RCC_PLL_Enable();
8000af2: f7ff fdb9 bl 8000668 <LL_RCC_PLL_Enable>
/* Wait till PLL is ready */
while(LL_RCC_PLL_IsReady() != 1)
8000af6: bf00 nop
8000af8: f7ff fdc6 bl 8000688 <LL_RCC_PLL_IsReady>
8000afc: 4603 mov r3, r0
8000afe: 2b01 cmp r3, #1
8000b00: d1fa bne.n 8000af8 <SystemClock_Config_24M_LSE+0x88>
{
}
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
8000b02: 2003 movs r0, #3
8000b04: f7ff fd18 bl 8000538 <LL_RCC_SetSysClkSource>
/* Wait till System clock is ready */
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
8000b08: bf00 nop
8000b0a: f7ff fd29 bl 8000560 <LL_RCC_GetSysClkSource>
8000b0e: 4603 mov r3, r0
8000b10: 2b0c cmp r3, #12
8000b12: d1fa bne.n 8000b0a <SystemClock_Config_24M_LSE+0x9a>
{
}
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
8000b14: 2000 movs r0, #0
8000b16: f7ff fd31 bl 800057c <LL_RCC_SetAHBPrescaler>
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
8000b1a: 2000 movs r0, #0
8000b1c: f7ff fd42 bl 80005a4 <LL_RCC_SetAPB1Prescaler>
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
8000b20: 2000 movs r0, #0
8000b22: f7ff fd53 bl 80005cc <LL_RCC_SetAPB2Prescaler>
LL_SetSystemCoreClock(24000000);
8000b26: 4804 ldr r0, [pc, #16] ; (8000b38 <SystemClock_Config_24M_LSE+0xc8>)
8000b28: f000 f9f4 bl 8000f14 <LL_SetSystemCoreClock>
/* Update the time base */
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
8000b2c: 2000 movs r0, #0
8000b2e: f000 f8d9 bl 8000ce4 <HAL_InitTick>
{
// Error_Handler();
}
}
8000b32: bf00 nop
8000b34: bd80 pop {r7, pc}
8000b36: bf00 nop
8000b38: 016e3600 .word 0x016e3600
08000b3c <SystemClock_Config_80M>:
void SystemClock_Config_80M(void)
{
8000b3c: b580 push {r7, lr}
8000b3e: af00 add r7, sp, #0
LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
8000b40: 2004 movs r0, #4
8000b42: f7ff fdfd bl 8000740 <LL_FLASH_SetLatency>
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4)
8000b46: bf00 nop
8000b48: f7ff fe0e bl 8000768 <LL_FLASH_GetLatency>
8000b4c: 4603 mov r3, r0
8000b4e: 2b04 cmp r3, #4
8000b50: d1fa bne.n 8000b48 <SystemClock_Config_80M+0xc>
{
}
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
8000b52: f44f 7000 mov.w r0, #512 ; 0x200
8000b56: f7ff fe35 bl 80007c4 <LL_PWR_SetRegulVoltageScaling>
LL_RCC_MSI_Enable();
8000b5a: f7ff fc81 bl 8000460 <LL_RCC_MSI_Enable>
/* Wait till MSI is ready */
while(LL_RCC_MSI_IsReady() != 1)
8000b5e: bf00 nop
8000b60: f7ff fc8e bl 8000480 <LL_RCC_MSI_IsReady>
8000b64: 4603 mov r3, r0
8000b66: 2b01 cmp r3, #1
8000b68: d1fa bne.n 8000b60 <SystemClock_Config_80M+0x24>
{
}
LL_RCC_MSI_EnableRangeSelection();
8000b6a: f7ff fcab bl 80004c4 <LL_RCC_MSI_EnableRangeSelection>
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
8000b6e: 2060 movs r0, #96 ; 0x60
8000b70: f7ff fcb8 bl 80004e4 <LL_RCC_MSI_SetRange>
LL_RCC_MSI_SetCalibTrimming(0);
8000b74: 2000 movs r0, #0
8000b76: f7ff fcc9 bl 800050c <LL_RCC_MSI_SetCalibTrimming>
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);
8000b7a: 2300 movs r3, #0
8000b7c: 2228 movs r2, #40 ; 0x28
8000b7e: 2100 movs r1, #0
8000b80: 2001 movs r0, #1
8000b82: f7ff fd95 bl 80006b0 <LL_RCC_PLL_ConfigDomain_SYS>
LL_RCC_PLL_EnableDomain_SYS();
8000b86: f7ff fdb3 bl 80006f0 <LL_RCC_PLL_EnableDomain_SYS>
LL_RCC_PLL_Enable();
8000b8a: f7ff fd6d bl 8000668 <LL_RCC_PLL_Enable>
/* Wait till PLL is ready */
while(LL_RCC_PLL_IsReady() != 1)
8000b8e: bf00 nop
8000b90: f7ff fd7a bl 8000688 <LL_RCC_PLL_IsReady>
8000b94: 4603 mov r3, r0
8000b96: 2b01 cmp r3, #1
8000b98: d1fa bne.n 8000b90 <SystemClock_Config_80M+0x54>
{
}
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
8000b9a: 2003 movs r0, #3
8000b9c: f7ff fccc bl 8000538 <LL_RCC_SetSysClkSource>
/* Wait till System clock is ready */
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
8000ba0: bf00 nop
8000ba2: f7ff fcdd bl 8000560 <LL_RCC_GetSysClkSource>
8000ba6: 4603 mov r3, r0
8000ba8: 2b0c cmp r3, #12
8000baa: d1fa bne.n 8000ba2 <SystemClock_Config_80M+0x66>
{
}
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
8000bac: 2000 movs r0, #0
8000bae: f7ff fce5 bl 800057c <LL_RCC_SetAHBPrescaler>
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
8000bb2: 2000 movs r0, #0
8000bb4: f7ff fcf6 bl 80005a4 <LL_RCC_SetAPB1Prescaler>
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
8000bb8: 2000 movs r0, #0
8000bba: f7ff fd07 bl 80005cc <LL_RCC_SetAPB2Prescaler>
LL_SetSystemCoreClock(80000000);
8000bbe: 4804 ldr r0, [pc, #16] ; (8000bd0 <SystemClock_Config_80M+0x94>)
8000bc0: f000 f9a8 bl 8000f14 <LL_SetSystemCoreClock>
/* Update the time base */
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
8000bc4: 2000 movs r0, #0
8000bc6: f000 f88d bl 8000ce4 <HAL_InitTick>
{
// Error_Handler();
}
}
8000bca: bf00 nop
8000bcc: bd80 pop {r7, pc}
8000bce: bf00 nop
8000bd0: 04c4b400 .word 0x04c4b400
08000bd4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000bd4: b480 push {r7}
8000bd6: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
8000bd8: bf00 nop
8000bda: 46bd mov sp, r7
8000bdc: f85d 7b04 ldr.w r7, [sp], #4
8000be0: 4770 bx lr
08000be2 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000be2: b480 push {r7}
8000be4: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000be6: e7fe b.n 8000be6 <HardFault_Handler+0x4>
08000be8 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000be8: b480 push {r7}
8000bea: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000bec: e7fe b.n 8000bec <MemManage_Handler+0x4>
08000bee <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000bee: b480 push {r7}
8000bf0: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000bf2: e7fe b.n 8000bf2 <BusFault_Handler+0x4>
08000bf4 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000bf4: b480 push {r7}
8000bf6: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000bf8: e7fe b.n 8000bf8 <UsageFault_Handler+0x4>
08000bfa <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000bfa: b480 push {r7}
8000bfc: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000bfe: bf00 nop
8000c00: 46bd mov sp, r7
8000c02: f85d 7b04 ldr.w r7, [sp], #4
8000c06: 4770 bx lr
08000c08 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000c08: b480 push {r7}
8000c0a: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000c0c: bf00 nop
8000c0e: 46bd mov sp, r7
8000c10: f85d 7b04 ldr.w r7, [sp], #4
8000c14: 4770 bx lr
08000c16 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000c16: b480 push {r7}
8000c18: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000c1a: bf00 nop
8000c1c: 46bd mov sp, r7
8000c1e: f85d 7b04 ldr.w r7, [sp], #4
8000c22: 4770 bx lr
08000c24 <SystemInit>:
* @param None
* @retval None
*/
void SystemInit(void)
{
8000c24: b480 push {r7}
8000c26: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000c28: 4b17 ldr r3, [pc, #92] ; (8000c88 <SystemInit+0x64>)
8000c2a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000c2e: 4a16 ldr r2, [pc, #88] ; (8000c88 <SystemInit+0x64>)
8000c30: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000c34: f8c2 3088 str.w r3, [r2, #136] ; 0x88
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC->CR |= RCC_CR_MSION;
8000c38: 4b14 ldr r3, [pc, #80] ; (8000c8c <SystemInit+0x68>)
8000c3a: 681b ldr r3, [r3, #0]
8000c3c: 4a13 ldr r2, [pc, #76] ; (8000c8c <SystemInit+0x68>)
8000c3e: f043 0301 orr.w r3, r3, #1
8000c42: 6013 str r3, [r2, #0]
/* Reset CFGR register */
RCC->CFGR = 0x00000000U;
8000c44: 4b11 ldr r3, [pc, #68] ; (8000c8c <SystemInit+0x68>)
8000c46: 2200 movs r2, #0
8000c48: 609a str r2, [r3, #8]
/* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC->CR &= 0xEAF6FFFFU;
8000c4a: 4b10 ldr r3, [pc, #64] ; (8000c8c <SystemInit+0x68>)
8000c4c: 681b ldr r3, [r3, #0]
8000c4e: 4a0f ldr r2, [pc, #60] ; (8000c8c <SystemInit+0x68>)
8000c50: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
8000c54: f423 2310 bic.w r3, r3, #589824 ; 0x90000
8000c58: 6013 str r3, [r2, #0]
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00001000U;
8000c5a: 4b0c ldr r3, [pc, #48] ; (8000c8c <SystemInit+0x68>)
8000c5c: f44f 5280 mov.w r2, #4096 ; 0x1000
8000c60: 60da str r2, [r3, #12]
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
8000c62: 4b0a ldr r3, [pc, #40] ; (8000c8c <SystemInit+0x68>)
8000c64: 681b ldr r3, [r3, #0]
8000c66: 4a09 ldr r2, [pc, #36] ; (8000c8c <SystemInit+0x68>)
8000c68: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000c6c: 6013 str r3, [r2, #0]
/* Disable all interrupts */
RCC->CIER = 0x00000000U;
8000c6e: 4b07 ldr r3, [pc, #28] ; (8000c8c <SystemInit+0x68>)
8000c70: 2200 movs r2, #0
8000c72: 619a str r2, [r3, #24]
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
8000c74: 4b04 ldr r3, [pc, #16] ; (8000c88 <SystemInit+0x64>)
8000c76: f04f 6200 mov.w r2, #134217728 ; 0x8000000
8000c7a: 609a str r2, [r3, #8]
#endif
}
8000c7c: bf00 nop
8000c7e: 46bd mov sp, r7
8000c80: f85d 7b04 ldr.w r7, [sp], #4
8000c84: 4770 bx lr
8000c86: bf00 nop
8000c88: e000ed00 .word 0xe000ed00
8000c8c: 40021000 .word 0x40021000
08000c90 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
8000c90: f8df d034 ldr.w sp, [pc, #52] ; 8000cc8 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
8000c94: f7ff ffc6 bl 8000c24 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8000c98: 2100 movs r1, #0
b LoopCopyDataInit
8000c9a: e003 b.n 8000ca4 <LoopCopyDataInit>
08000c9c <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8000c9c: 4b0b ldr r3, [pc, #44] ; (8000ccc <LoopForever+0x6>)
ldr r3, [r3, r1]
8000c9e: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
8000ca0: 5043 str r3, [r0, r1]
adds r1, r1, #4
8000ca2: 3104 adds r1, #4
08000ca4 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
8000ca4: 480a ldr r0, [pc, #40] ; (8000cd0 <LoopForever+0xa>)
ldr r3, =_edata
8000ca6: 4b0b ldr r3, [pc, #44] ; (8000cd4 <LoopForever+0xe>)
adds r2, r0, r1
8000ca8: 1842 adds r2, r0, r1
cmp r2, r3
8000caa: 429a cmp r2, r3
bcc CopyDataInit
8000cac: d3f6 bcc.n 8000c9c <CopyDataInit>
ldr r2, =_sbss
8000cae: 4a0a ldr r2, [pc, #40] ; (8000cd8 <LoopForever+0x12>)
b LoopFillZerobss
8000cb0: e002 b.n 8000cb8 <LoopFillZerobss>
08000cb2 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
8000cb2: 2300 movs r3, #0
str r3, [r2], #4
8000cb4: f842 3b04 str.w r3, [r2], #4
08000cb8 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8000cb8: 4b08 ldr r3, [pc, #32] ; (8000cdc <LoopForever+0x16>)
cmp r2, r3
8000cba: 429a cmp r2, r3
bcc FillZerobss
8000cbc: d3f9 bcc.n 8000cb2 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000cbe: f000 f939 bl 8000f34 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000cc2: f7ff fdf1 bl 80008a8 <main>
08000cc6 <LoopForever>:
LoopForever:
b LoopForever
8000cc6: e7fe b.n 8000cc6 <LoopForever>
ldr sp, =_estack /* Set stack pointer */
8000cc8: 20018000 .word 0x20018000
ldr r3, =_sidata
8000ccc: 08000f9c .word 0x08000f9c
ldr r0, =_sdata
8000cd0: 20000000 .word 0x20000000
ldr r3, =_edata
8000cd4: 2000000c .word 0x2000000c
ldr r2, =_sbss
8000cd8: 2000000c .word 0x2000000c
ldr r3, = _ebss
8000cdc: 20000030 .word 0x20000030
08000ce0 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000ce0: e7fe b.n 8000ce0 <ADC1_2_IRQHandler>
...
08000ce4 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000ce4: b580 push {r7, lr}
8000ce6: b084 sub sp, #16
8000ce8: af00 add r7, sp, #0
8000cea: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000cec: 2300 movs r3, #0
8000cee: 73fb strb r3, [r7, #15]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8000cf0: 4b17 ldr r3, [pc, #92] ; (8000d50 <HAL_InitTick+0x6c>)
8000cf2: 781b ldrb r3, [r3, #0]
8000cf4: 2b00 cmp r3, #0
8000cf6: d023 beq.n 8000d40 <HAL_InitTick+0x5c>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
8000cf8: 4b16 ldr r3, [pc, #88] ; (8000d54 <HAL_InitTick+0x70>)
8000cfa: 681a ldr r2, [r3, #0]
8000cfc: 4b14 ldr r3, [pc, #80] ; (8000d50 <HAL_InitTick+0x6c>)
8000cfe: 781b ldrb r3, [r3, #0]
8000d00: 4619 mov r1, r3
8000d02: f44f 737a mov.w r3, #1000 ; 0x3e8
8000d06: fbb3 f3f1 udiv r3, r3, r1
8000d0a: fbb2 f3f3 udiv r3, r2, r3
8000d0e: 4618 mov r0, r3
8000d10: f000 f8ce bl 8000eb0 <HAL_SYSTICK_Config>
8000d14: 4603 mov r3, r0
8000d16: 2b00 cmp r3, #0
8000d18: d10f bne.n 8000d3a <HAL_InitTick+0x56>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000d1a: 687b ldr r3, [r7, #4]
8000d1c: 2b0f cmp r3, #15
8000d1e: d809 bhi.n 8000d34 <HAL_InitTick+0x50>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000d20: 2200 movs r2, #0
8000d22: 6879 ldr r1, [r7, #4]
8000d24: f04f 30ff mov.w r0, #4294967295
8000d28: f000 f8a6 bl 8000e78 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000d2c: 4a0a ldr r2, [pc, #40] ; (8000d58 <HAL_InitTick+0x74>)
8000d2e: 687b ldr r3, [r7, #4]
8000d30: 6013 str r3, [r2, #0]
8000d32: e007 b.n 8000d44 <HAL_InitTick+0x60>
}
else
{
status = HAL_ERROR;
8000d34: 2301 movs r3, #1
8000d36: 73fb strb r3, [r7, #15]
8000d38: e004 b.n 8000d44 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
8000d3a: 2301 movs r3, #1
8000d3c: 73fb strb r3, [r7, #15]
8000d3e: e001 b.n 8000d44 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
8000d40: 2301 movs r3, #1
8000d42: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8000d44: 7bfb ldrb r3, [r7, #15]
}
8000d46: 4618 mov r0, r3
8000d48: 3710 adds r7, #16
8000d4a: 46bd mov sp, r7
8000d4c: bd80 pop {r7, pc}
8000d4e: bf00 nop
8000d50: 20000008 .word 0x20000008
8000d54: 20000000 .word 0x20000000
8000d58: 20000004 .word 0x20000004
08000d5c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000d5c: b480 push {r7}
8000d5e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000d60: 4b04 ldr r3, [pc, #16] ; (8000d74 <__NVIC_GetPriorityGrouping+0x18>)
8000d62: 68db ldr r3, [r3, #12]
8000d64: 0a1b lsrs r3, r3, #8
8000d66: f003 0307 and.w r3, r3, #7
}
8000d6a: 4618 mov r0, r3
8000d6c: 46bd mov sp, r7
8000d6e: f85d 7b04 ldr.w r7, [sp], #4
8000d72: 4770 bx lr
8000d74: e000ed00 .word 0xe000ed00
08000d78 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000d78: b480 push {r7}
8000d7a: b083 sub sp, #12
8000d7c: af00 add r7, sp, #0
8000d7e: 4603 mov r3, r0
8000d80: 6039 str r1, [r7, #0]
8000d82: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000d84: f997 3007 ldrsb.w r3, [r7, #7]
8000d88: 2b00 cmp r3, #0
8000d8a: db0a blt.n 8000da2 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000d8c: 683b ldr r3, [r7, #0]
8000d8e: b2da uxtb r2, r3
8000d90: 490c ldr r1, [pc, #48] ; (8000dc4 <__NVIC_SetPriority+0x4c>)
8000d92: f997 3007 ldrsb.w r3, [r7, #7]
8000d96: 0112 lsls r2, r2, #4
8000d98: b2d2 uxtb r2, r2
8000d9a: 440b add r3, r1
8000d9c: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000da0: e00a b.n 8000db8 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000da2: 683b ldr r3, [r7, #0]
8000da4: b2da uxtb r2, r3
8000da6: 4908 ldr r1, [pc, #32] ; (8000dc8 <__NVIC_SetPriority+0x50>)
8000da8: 79fb ldrb r3, [r7, #7]
8000daa: f003 030f and.w r3, r3, #15
8000dae: 3b04 subs r3, #4
8000db0: 0112 lsls r2, r2, #4
8000db2: b2d2 uxtb r2, r2
8000db4: 440b add r3, r1
8000db6: 761a strb r2, [r3, #24]
}
8000db8: bf00 nop
8000dba: 370c adds r7, #12
8000dbc: 46bd mov sp, r7
8000dbe: f85d 7b04 ldr.w r7, [sp], #4
8000dc2: 4770 bx lr
8000dc4: e000e100 .word 0xe000e100
8000dc8: e000ed00 .word 0xe000ed00
08000dcc <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000dcc: b480 push {r7}
8000dce: b089 sub sp, #36 ; 0x24
8000dd0: af00 add r7, sp, #0
8000dd2: 60f8 str r0, [r7, #12]
8000dd4: 60b9 str r1, [r7, #8]
8000dd6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000dd8: 68fb ldr r3, [r7, #12]
8000dda: f003 0307 and.w r3, r3, #7
8000dde: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000de0: 69fb ldr r3, [r7, #28]
8000de2: f1c3 0307 rsb r3, r3, #7
8000de6: 2b04 cmp r3, #4
8000de8: bf28 it cs
8000dea: 2304 movcs r3, #4
8000dec: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000dee: 69fb ldr r3, [r7, #28]
8000df0: 3304 adds r3, #4
8000df2: 2b06 cmp r3, #6
8000df4: d902 bls.n 8000dfc <NVIC_EncodePriority+0x30>
8000df6: 69fb ldr r3, [r7, #28]
8000df8: 3b03 subs r3, #3
8000dfa: e000 b.n 8000dfe <NVIC_EncodePriority+0x32>
8000dfc: 2300 movs r3, #0
8000dfe: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000e00: f04f 32ff mov.w r2, #4294967295
8000e04: 69bb ldr r3, [r7, #24]
8000e06: fa02 f303 lsl.w r3, r2, r3
8000e0a: 43da mvns r2, r3
8000e0c: 68bb ldr r3, [r7, #8]
8000e0e: 401a ands r2, r3
8000e10: 697b ldr r3, [r7, #20]
8000e12: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000e14: f04f 31ff mov.w r1, #4294967295
8000e18: 697b ldr r3, [r7, #20]
8000e1a: fa01 f303 lsl.w r3, r1, r3
8000e1e: 43d9 mvns r1, r3
8000e20: 687b ldr r3, [r7, #4]
8000e22: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000e24: 4313 orrs r3, r2
);
}
8000e26: 4618 mov r0, r3
8000e28: 3724 adds r7, #36 ; 0x24
8000e2a: 46bd mov sp, r7
8000e2c: f85d 7b04 ldr.w r7, [sp], #4
8000e30: 4770 bx lr
...
08000e34 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000e34: b580 push {r7, lr}
8000e36: b082 sub sp, #8
8000e38: af00 add r7, sp, #0
8000e3a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000e3c: 687b ldr r3, [r7, #4]
8000e3e: 3b01 subs r3, #1
8000e40: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8000e44: d301 bcc.n 8000e4a <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000e46: 2301 movs r3, #1
8000e48: e00f b.n 8000e6a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000e4a: 4a0a ldr r2, [pc, #40] ; (8000e74 <SysTick_Config+0x40>)
8000e4c: 687b ldr r3, [r7, #4]
8000e4e: 3b01 subs r3, #1
8000e50: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000e52: 210f movs r1, #15
8000e54: f04f 30ff mov.w r0, #4294967295
8000e58: f7ff ff8e bl 8000d78 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000e5c: 4b05 ldr r3, [pc, #20] ; (8000e74 <SysTick_Config+0x40>)
8000e5e: 2200 movs r2, #0
8000e60: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000e62: 4b04 ldr r3, [pc, #16] ; (8000e74 <SysTick_Config+0x40>)
8000e64: 2207 movs r2, #7
8000e66: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000e68: 2300 movs r3, #0
}
8000e6a: 4618 mov r0, r3
8000e6c: 3708 adds r7, #8
8000e6e: 46bd mov sp, r7
8000e70: bd80 pop {r7, pc}
8000e72: bf00 nop
8000e74: e000e010 .word 0xe000e010
08000e78 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000e78: b580 push {r7, lr}
8000e7a: b086 sub sp, #24
8000e7c: af00 add r7, sp, #0
8000e7e: 4603 mov r3, r0
8000e80: 60b9 str r1, [r7, #8]
8000e82: 607a str r2, [r7, #4]
8000e84: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8000e86: 2300 movs r3, #0
8000e88: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000e8a: f7ff ff67 bl 8000d5c <__NVIC_GetPriorityGrouping>
8000e8e: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000e90: 687a ldr r2, [r7, #4]
8000e92: 68b9 ldr r1, [r7, #8]
8000e94: 6978 ldr r0, [r7, #20]
8000e96: f7ff ff99 bl 8000dcc <NVIC_EncodePriority>
8000e9a: 4602 mov r2, r0
8000e9c: f997 300f ldrsb.w r3, [r7, #15]
8000ea0: 4611 mov r1, r2
8000ea2: 4618 mov r0, r3
8000ea4: f7ff ff68 bl 8000d78 <__NVIC_SetPriority>
}
8000ea8: bf00 nop
8000eaa: 3718 adds r7, #24
8000eac: 46bd mov sp, r7
8000eae: bd80 pop {r7, pc}
08000eb0 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000eb0: b580 push {r7, lr}
8000eb2: b082 sub sp, #8
8000eb4: af00 add r7, sp, #0
8000eb6: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000eb8: 6878 ldr r0, [r7, #4]
8000eba: f7ff ffbb bl 8000e34 <SysTick_Config>
8000ebe: 4603 mov r3, r0
}
8000ec0: 4618 mov r0, r3
8000ec2: 3708 adds r7, #8
8000ec4: 46bd mov sp, r7
8000ec6: bd80 pop {r7, pc}
08000ec8 <LL_InitTick>:
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
8000ec8: b480 push {r7}
8000eca: b083 sub sp, #12
8000ecc: af00 add r7, sp, #0
8000ece: 6078 str r0, [r7, #4]
8000ed0: 6039 str r1, [r7, #0]
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
8000ed2: 687a ldr r2, [r7, #4]
8000ed4: 683b ldr r3, [r7, #0]
8000ed6: fbb2 f3f3 udiv r3, r2, r3
8000eda: 4a07 ldr r2, [pc, #28] ; (8000ef8 <LL_InitTick+0x30>)
8000edc: 3b01 subs r3, #1
8000ede: 6053 str r3, [r2, #4]
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000ee0: 4b05 ldr r3, [pc, #20] ; (8000ef8 <LL_InitTick+0x30>)
8000ee2: 2200 movs r2, #0
8000ee4: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000ee6: 4b04 ldr r3, [pc, #16] ; (8000ef8 <LL_InitTick+0x30>)
8000ee8: 2205 movs r2, #5
8000eea: 601a str r2, [r3, #0]
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
8000eec: bf00 nop
8000eee: 370c adds r7, #12
8000ef0: 46bd mov sp, r7
8000ef2: f85d 7b04 ldr.w r7, [sp], #4
8000ef6: 4770 bx lr
8000ef8: e000e010 .word 0xe000e010
08000efc <LL_Init1msTick>:
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
8000efc: b580 push {r7, lr}
8000efe: b082 sub sp, #8
8000f00: af00 add r7, sp, #0
8000f02: 6078 str r0, [r7, #4]
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 100U);
8000f04: 2164 movs r1, #100 ; 0x64
8000f06: 6878 ldr r0, [r7, #4]
8000f08: f7ff ffde bl 8000ec8 <LL_InitTick>
}
8000f0c: bf00 nop
8000f0e: 3708 adds r7, #8
8000f10: 46bd mov sp, r7
8000f12: bd80 pop {r7, pc}
08000f14 <LL_SetSystemCoreClock>:
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
8000f14: b480 push {r7}
8000f16: b083 sub sp, #12
8000f18: af00 add r7, sp, #0
8000f1a: 6078 str r0, [r7, #4]
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
8000f1c: 4a04 ldr r2, [pc, #16] ; (8000f30 <LL_SetSystemCoreClock+0x1c>)
8000f1e: 687b ldr r3, [r7, #4]
8000f20: 6013 str r3, [r2, #0]
}
8000f22: bf00 nop
8000f24: 370c adds r7, #12
8000f26: 46bd mov sp, r7
8000f28: f85d 7b04 ldr.w r7, [sp], #4
8000f2c: 4770 bx lr
8000f2e: bf00 nop
8000f30: 20000000 .word 0x20000000
08000f34 <__libc_init_array>:
8000f34: b570 push {r4, r5, r6, lr}
8000f36: 4e0d ldr r6, [pc, #52] ; (8000f6c <__libc_init_array+0x38>)
8000f38: 4c0d ldr r4, [pc, #52] ; (8000f70 <__libc_init_array+0x3c>)
8000f3a: 1ba4 subs r4, r4, r6
8000f3c: 10a4 asrs r4, r4, #2
8000f3e: 2500 movs r5, #0
8000f40: 42a5 cmp r5, r4
8000f42: d109 bne.n 8000f58 <__libc_init_array+0x24>
8000f44: 4e0b ldr r6, [pc, #44] ; (8000f74 <__libc_init_array+0x40>)
8000f46: 4c0c ldr r4, [pc, #48] ; (8000f78 <__libc_init_array+0x44>)
8000f48: f000 f818 bl 8000f7c <_init>
8000f4c: 1ba4 subs r4, r4, r6
8000f4e: 10a4 asrs r4, r4, #2
8000f50: 2500 movs r5, #0
8000f52: 42a5 cmp r5, r4
8000f54: d105 bne.n 8000f62 <__libc_init_array+0x2e>
8000f56: bd70 pop {r4, r5, r6, pc}
8000f58: f856 3025 ldr.w r3, [r6, r5, lsl #2]
8000f5c: 4798 blx r3
8000f5e: 3501 adds r5, #1
8000f60: e7ee b.n 8000f40 <__libc_init_array+0xc>
8000f62: f856 3025 ldr.w r3, [r6, r5, lsl #2]
8000f66: 4798 blx r3
8000f68: 3501 adds r5, #1
8000f6a: e7f2 b.n 8000f52 <__libc_init_array+0x1e>
8000f6c: 08000f94 .word 0x08000f94
8000f70: 08000f94 .word 0x08000f94
8000f74: 08000f94 .word 0x08000f94
8000f78: 08000f98 .word 0x08000f98
08000f7c <_init>:
8000f7c: b5f8 push {r3, r4, r5, r6, r7, lr}
8000f7e: bf00 nop
8000f80: bcf8 pop {r3, r4, r5, r6, r7}
8000f82: bc08 pop {r3}
8000f84: 469e mov lr, r3
8000f86: 4770 bx lr
08000f88 <_fini>:
8000f88: b5f8 push {r3, r4, r5, r6, r7, lr}
8000f8a: bf00 nop
8000f8c: bcf8 pop {r3, r4, r5, r6, r7}
8000f8e: bc08 pop {r3}
8000f90: 469e mov lr, r3
8000f92: 4770 bx lr
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