L476_ats_blink-master.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00000814 08000188 08000188 00010188 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000040 0800099c 0800099c 0001099c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080009dc 080009dc 00020004 2**0 CONTENTS 4 .ARM 00000000 080009dc 080009dc 00020004 2**0 CONTENTS 5 .preinit_array 00000000 080009dc 080009dc 00020004 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080009dc 080009dc 000109dc 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 080009e0 080009e0 000109e0 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000004 20000000 080009e4 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000001c 20000004 080009e8 00020004 2**2 ALLOC 10 ._user_heap_stack 00000600 20000020 080009e8 00020020 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 00020004 2**0 CONTENTS, READONLY 12 .debug_info 0000206d 00000000 00000000 00020034 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 0000074a 00000000 00000000 000220a1 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 000002d0 00000000 00000000 000227f0 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 00000278 00000000 00000000 00022ac0 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 0001e117 00000000 00000000 00022d38 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 00001fee 00000000 00000000 00040e4f 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 000a94c9 00000000 00000000 00042e3d 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 000ec306 2**0 CONTENTS, READONLY 20 .debug_frame 000009e4 00000000 00000000 000ec384 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 08000188 <__do_global_dtors_aux>: 8000188: b510 push {r4, lr} 800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>) 800018c: 7823 ldrb r3, [r4, #0] 800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16> 8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>) 8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12> 8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>) 8000196: f3af 8000 nop.w 800019a: 2301 movs r3, #1 800019c: 7023 strb r3, [r4, #0] 800019e: bd10 pop {r4, pc} 80001a0: 20000004 .word 0x20000004 80001a4: 00000000 .word 0x00000000 80001a8: 08000984 .word 0x08000984 080001ac : 80001ac: b508 push {r3, lr} 80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc ) 80001b0: b11b cbz r3, 80001ba 80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 ) 80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 ) 80001b6: f3af 8000 nop.w 80001ba: bd08 pop {r3, pc} 80001bc: 00000000 .word 0x00000000 80001c0: 20000008 .word 0x20000008 80001c4: 08000984 .word 0x08000984 080001c8 : * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) { 80001c8: b480 push {r7} 80001ca: b085 sub sp, #20 80001cc: af00 add r7, sp, #0 80001ce: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, Periphs); 80001d0: 4b08 ldr r3, [pc, #32] ; (80001f4 ) 80001d2: 6cda ldr r2, [r3, #76] ; 0x4c 80001d4: 4907 ldr r1, [pc, #28] ; (80001f4 ) 80001d6: 687b ldr r3, [r7, #4] 80001d8: 4313 orrs r3, r2 80001da: 64cb str r3, [r1, #76] ; 0x4c /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 80001dc: 4b05 ldr r3, [pc, #20] ; (80001f4 ) 80001de: 6cda ldr r2, [r3, #76] ; 0x4c 80001e0: 687b ldr r3, [r7, #4] 80001e2: 4013 ands r3, r2 80001e4: 60fb str r3, [r7, #12] (void)tmpreg; 80001e6: 68fb ldr r3, [r7, #12] } 80001e8: bf00 nop 80001ea: 3714 adds r7, #20 80001ec: 46bd mov sp, r7 80001ee: f85d 7b04 ldr.w r7, [sp], #4 80001f2: 4770 bx lr 80001f4: 40021000 .word 0x40021000 080001f8 : * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { 80001f8: b480 push {r7} 80001fa: b08b sub sp, #44 ; 0x2c 80001fc: af00 add r7, sp, #0 80001fe: 60f8 str r0, [r7, #12] 8000200: 60b9 str r1, [r7, #8] 8000202: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); 8000204: 68fb ldr r3, [r7, #12] 8000206: 681a ldr r2, [r3, #0] 8000208: 68bb ldr r3, [r7, #8] 800020a: 617b str r3, [r7, #20] uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800020c: 697b ldr r3, [r7, #20] 800020e: fa93 f3a3 rbit r3, r3 8000212: 613b str r3, [r7, #16] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8000214: 693b ldr r3, [r7, #16] 8000216: 61bb str r3, [r7, #24] optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8000218: 69bb ldr r3, [r7, #24] 800021a: 2b00 cmp r3, #0 800021c: d101 bne.n 8000222 { return 32U; 800021e: 2320 movs r3, #32 8000220: e003 b.n 800022a } return __builtin_clz(value); 8000222: 69bb ldr r3, [r7, #24] 8000224: fab3 f383 clz r3, r3 8000228: b2db uxtb r3, r3 800022a: 005b lsls r3, r3, #1 800022c: 2103 movs r1, #3 800022e: fa01 f303 lsl.w r3, r1, r3 8000232: 43db mvns r3, r3 8000234: 401a ands r2, r3 8000236: 68bb ldr r3, [r7, #8] 8000238: 623b str r3, [r7, #32] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800023a: 6a3b ldr r3, [r7, #32] 800023c: fa93 f3a3 rbit r3, r3 8000240: 61fb str r3, [r7, #28] return result; 8000242: 69fb ldr r3, [r7, #28] 8000244: 627b str r3, [r7, #36] ; 0x24 if (value == 0U) 8000246: 6a7b ldr r3, [r7, #36] ; 0x24 8000248: 2b00 cmp r3, #0 800024a: d101 bne.n 8000250 return 32U; 800024c: 2320 movs r3, #32 800024e: e003 b.n 8000258 return __builtin_clz(value); 8000250: 6a7b ldr r3, [r7, #36] ; 0x24 8000252: fab3 f383 clz r3, r3 8000256: b2db uxtb r3, r3 8000258: 005b lsls r3, r3, #1 800025a: 6879 ldr r1, [r7, #4] 800025c: fa01 f303 lsl.w r3, r1, r3 8000260: 431a orrs r2, r3 8000262: 68fb ldr r3, [r7, #12] 8000264: 601a str r2, [r3, #0] } 8000266: bf00 nop 8000268: 372c adds r7, #44 ; 0x2c 800026a: 46bd mov sp, r7 800026c: f85d 7b04 ldr.w r7, [sp], #4 8000270: 4770 bx lr 08000272 : * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { 8000272: b480 push {r7} 8000274: b085 sub sp, #20 8000276: af00 add r7, sp, #0 8000278: 60f8 str r0, [r7, #12] 800027a: 60b9 str r1, [r7, #8] 800027c: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); 800027e: 68fb ldr r3, [r7, #12] 8000280: 685a ldr r2, [r3, #4] 8000282: 68bb ldr r3, [r7, #8] 8000284: 43db mvns r3, r3 8000286: 401a ands r2, r3 8000288: 68bb ldr r3, [r7, #8] 800028a: 6879 ldr r1, [r7, #4] 800028c: fb01 f303 mul.w r3, r1, r3 8000290: 431a orrs r2, r3 8000292: 68fb ldr r3, [r7, #12] 8000294: 605a str r2, [r3, #4] } 8000296: bf00 nop 8000298: 3714 adds r7, #20 800029a: 46bd mov sp, r7 800029c: f85d 7b04 ldr.w r7, [sp], #4 80002a0: 4770 bx lr 080002a2 : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 80002a2: b480 push {r7} 80002a4: b083 sub sp, #12 80002a6: af00 add r7, sp, #0 80002a8: 6078 str r0, [r7, #4] 80002aa: 6039 str r1, [r7, #0] return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); 80002ac: 687b ldr r3, [r7, #4] 80002ae: 691a ldr r2, [r3, #16] 80002b0: 683b ldr r3, [r7, #0] 80002b2: 4013 ands r3, r2 80002b4: 683a ldr r2, [r7, #0] 80002b6: 429a cmp r2, r3 80002b8: d101 bne.n 80002be 80002ba: 2301 movs r3, #1 80002bc: e000 b.n 80002c0 80002be: 2300 movs r3, #0 } 80002c0: 4618 mov r0, r3 80002c2: 370c adds r7, #12 80002c4: 46bd mov sp, r7 80002c6: f85d 7b04 ldr.w r7, [sp], #4 80002ca: 4770 bx lr 080002cc : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 80002cc: b480 push {r7} 80002ce: b083 sub sp, #12 80002d0: af00 add r7, sp, #0 80002d2: 6078 str r0, [r7, #4] 80002d4: 6039 str r1, [r7, #0] WRITE_REG(GPIOx->BSRR, PinMask); 80002d6: 687b ldr r3, [r7, #4] 80002d8: 683a ldr r2, [r7, #0] 80002da: 619a str r2, [r3, #24] } 80002dc: bf00 nop 80002de: 370c adds r7, #12 80002e0: 46bd mov sp, r7 80002e2: f85d 7b04 ldr.w r7, [sp], #4 80002e6: 4770 bx lr 080002e8 : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 80002e8: b480 push {r7} 80002ea: b083 sub sp, #12 80002ec: af00 add r7, sp, #0 80002ee: 6078 str r0, [r7, #4] 80002f0: 6039 str r1, [r7, #0] WRITE_REG(GPIOx->BRR, PinMask); 80002f2: 687b ldr r3, [r7, #4] 80002f4: 683a ldr r2, [r7, #0] 80002f6: 629a str r2, [r3, #40] ; 0x28 } 80002f8: bf00 nop 80002fa: 370c adds r7, #12 80002fc: 46bd mov sp, r7 80002fe: f85d 7b04 ldr.w r7, [sp], #4 8000302: 4770 bx lr 08000304 : #define LED_PIN LL_GPIO_PIN_5 #define BUT_PORT GPIOC #define BUT_PIN LL_GPIO_PIN_13 void GPIO_init(void) { 8000304: b580 push {r7, lr} 8000306: af00 add r7, sp, #0 // PORT A LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA ); 8000308: 2001 movs r0, #1 800030a: f7ff ff5d bl 80001c8 // Green LED (user LED) - PA5 LL_GPIO_SetPinMode( LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT ); 800030e: 2201 movs r2, #1 8000310: 2120 movs r1, #32 8000312: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8000316: f7ff ff6f bl 80001f8 LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL ); 800031a: 2200 movs r2, #0 800031c: 2120 movs r1, #32 800031e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8000322: f7ff ffa6 bl 8000272 // PORT C LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC ); 8000326: 2004 movs r0, #4 8000328: f7ff ff4e bl 80001c8 // Blue button - PC13 LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT ); 800032c: 2200 movs r2, #0 800032e: f44f 5100 mov.w r1, #8192 ; 0x2000 8000332: 4802 ldr r0, [pc, #8] ; (800033c ) 8000334: f7ff ff60 bl 80001f8 } 8000338: bf00 nop 800033a: bd80 pop {r7, pc} 800033c: 48000800 .word 0x48000800 08000340 : void LED_GREEN( int val ) { 8000340: b580 push {r7, lr} 8000342: b082 sub sp, #8 8000344: af00 add r7, sp, #0 8000346: 6078 str r0, [r7, #4] if ( val ) 8000348: 687b ldr r3, [r7, #4] 800034a: 2b00 cmp r3, #0 800034c: d005 beq.n 800035a LL_GPIO_SetOutputPin( LED_PORT, LED_PIN ); 800034e: 2120 movs r1, #32 8000350: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8000354: f7ff ffba bl 80002cc else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN ); } 8000358: e004 b.n 8000364 else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN ); 800035a: 2120 movs r1, #32 800035c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8000360: f7ff ffc2 bl 80002e8 } 8000364: bf00 nop 8000366: 3708 adds r7, #8 8000368: 46bd mov sp, r7 800036a: bd80 pop {r7, pc} 0800036c : int BLUE_BUTTON() { 800036c: b580 push {r7, lr} 800036e: af00 add r7, sp, #0 return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) ); 8000370: f44f 5100 mov.w r1, #8192 ; 0x2000 8000374: 4805 ldr r0, [pc, #20] ; (800038c ) 8000376: f7ff ff94 bl 80002a2 800037a: 4603 mov r3, r0 800037c: 2b00 cmp r3, #0 800037e: bf0c ite eq 8000380: 2301 moveq r3, #1 8000382: 2300 movne r3, #0 8000384: b2db uxtb r3, r3 } 8000386: 4618 mov r0, r3 8000388: bd80 pop {r7, pc} 800038a: bf00 nop 800038c: 48000800 .word 0x48000800 08000390 : * @brief Enable MSI oscillator * @rmtoll CR MSION LL_RCC_MSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_MSI_Enable(void) { 8000390: b480 push {r7} 8000392: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSION); 8000394: 4b05 ldr r3, [pc, #20] ; (80003ac ) 8000396: 681b ldr r3, [r3, #0] 8000398: 4a04 ldr r2, [pc, #16] ; (80003ac ) 800039a: f043 0301 orr.w r3, r3, #1 800039e: 6013 str r3, [r2, #0] } 80003a0: bf00 nop 80003a2: 46bd mov sp, r7 80003a4: f85d 7b04 ldr.w r7, [sp], #4 80003a8: 4770 bx lr 80003aa: bf00 nop 80003ac: 40021000 .word 0x40021000 080003b0 : * @brief Check if MSI oscillator Ready * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) { 80003b0: b480 push {r7} 80003b2: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL); 80003b4: 4b06 ldr r3, [pc, #24] ; (80003d0 ) 80003b6: 681b ldr r3, [r3, #0] 80003b8: f003 0302 and.w r3, r3, #2 80003bc: 2b02 cmp r3, #2 80003be: d101 bne.n 80003c4 80003c0: 2301 movs r3, #1 80003c2: e000 b.n 80003c6 80003c4: 2300 movs r3, #0 } 80003c6: 4618 mov r0, r3 80003c8: 46bd mov sp, r7 80003ca: f85d 7b04 ldr.w r7, [sp], #4 80003ce: 4770 bx lr 80003d0: 40021000 .word 0x40021000 080003d4 : * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL * @retval None */ __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) { 80003d4: b480 push {r7} 80003d6: b083 sub sp, #12 80003d8: af00 add r7, sp, #0 80003da: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 80003dc: 4b06 ldr r3, [pc, #24] ; (80003f8 ) 80003de: 689b ldr r3, [r3, #8] 80003e0: f023 0203 bic.w r2, r3, #3 80003e4: 4904 ldr r1, [pc, #16] ; (80003f8 ) 80003e6: 687b ldr r3, [r7, #4] 80003e8: 4313 orrs r3, r2 80003ea: 608b str r3, [r1, #8] } 80003ec: bf00 nop 80003ee: 370c adds r7, #12 80003f0: 46bd mov sp, r7 80003f2: f85d 7b04 ldr.w r7, [sp], #4 80003f6: 4770 bx lr 80003f8: 40021000 .word 0x40021000 080003fc : * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL */ __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) { 80003fc: b480 push {r7} 80003fe: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 8000400: 4b04 ldr r3, [pc, #16] ; (8000414 ) 8000402: 689b ldr r3, [r3, #8] 8000404: f003 030c and.w r3, r3, #12 } 8000408: 4618 mov r0, r3 800040a: 46bd mov sp, r7 800040c: f85d 7b04 ldr.w r7, [sp], #4 8000410: 4770 bx lr 8000412: bf00 nop 8000414: 40021000 .word 0x40021000 08000418 : * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval None */ __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) { 8000418: b480 push {r7} 800041a: b083 sub sp, #12 800041c: af00 add r7, sp, #0 800041e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 8000420: 4b06 ldr r3, [pc, #24] ; (800043c ) 8000422: 689b ldr r3, [r3, #8] 8000424: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8000428: 4904 ldr r1, [pc, #16] ; (800043c ) 800042a: 687b ldr r3, [r7, #4] 800042c: 4313 orrs r3, r2 800042e: 608b str r3, [r1, #8] } 8000430: bf00 nop 8000432: 370c adds r7, #12 8000434: 46bd mov sp, r7 8000436: f85d 7b04 ldr.w r7, [sp], #4 800043a: 4770 bx lr 800043c: 40021000 .word 0x40021000 08000440 : * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) { 8000440: b480 push {r7} 8000442: b083 sub sp, #12 8000444: af00 add r7, sp, #0 8000446: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 8000448: 4b06 ldr r3, [pc, #24] ; (8000464 ) 800044a: 689b ldr r3, [r3, #8] 800044c: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8000450: 4904 ldr r1, [pc, #16] ; (8000464 ) 8000452: 687b ldr r3, [r7, #4] 8000454: 4313 orrs r3, r2 8000456: 608b str r3, [r1, #8] } 8000458: bf00 nop 800045a: 370c adds r7, #12 800045c: 46bd mov sp, r7 800045e: f85d 7b04 ldr.w r7, [sp], #4 8000462: 4770 bx lr 8000464: 40021000 .word 0x40021000 08000468 : * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) { 8000468: b480 push {r7} 800046a: b083 sub sp, #12 800046c: af00 add r7, sp, #0 800046e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 8000470: 4b06 ldr r3, [pc, #24] ; (800048c ) 8000472: 689b ldr r3, [r3, #8] 8000474: f423 5260 bic.w r2, r3, #14336 ; 0x3800 8000478: 4904 ldr r1, [pc, #16] ; (800048c ) 800047a: 687b ldr r3, [r7, #4] 800047c: 4313 orrs r3, r2 800047e: 608b str r3, [r1, #8] } 8000480: bf00 nop 8000482: 370c adds r7, #12 8000484: 46bd mov sp, r7 8000486: f85d 7b04 ldr.w r7, [sp], #4 800048a: 4770 bx lr 800048c: 40021000 .word 0x40021000 08000490 : * @brief Enable PLL * @rmtoll CR PLLON LL_RCC_PLL_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Enable(void) { 8000490: b480 push {r7} 8000492: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_PLLON); 8000494: 4b05 ldr r3, [pc, #20] ; (80004ac ) 8000496: 681b ldr r3, [r3, #0] 8000498: 4a04 ldr r2, [pc, #16] ; (80004ac ) 800049a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 800049e: 6013 str r3, [r2, #0] } 80004a0: bf00 nop 80004a2: 46bd mov sp, r7 80004a4: f85d 7b04 ldr.w r7, [sp], #4 80004a8: 4770 bx lr 80004aa: bf00 nop 80004ac: 40021000 .word 0x40021000 080004b0 : * @brief Check if PLL Ready * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { 80004b0: b480 push {r7} 80004b2: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL); 80004b4: 4b07 ldr r3, [pc, #28] ; (80004d4 ) 80004b6: 681b ldr r3, [r3, #0] 80004b8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80004bc: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80004c0: d101 bne.n 80004c6 80004c2: 2301 movs r3, #1 80004c4: e000 b.n 80004c8 80004c6: 2300 movs r3, #0 } 80004c8: 4618 mov r0, r3 80004ca: 46bd mov sp, r7 80004cc: f85d 7b04 ldr.w r7, [sp], #4 80004d0: 4770 bx lr 80004d2: bf00 nop 80004d4: 40021000 .word 0x40021000 080004d8 : * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_8 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) { 80004d8: b480 push {r7} 80004da: b085 sub sp, #20 80004dc: af00 add r7, sp, #0 80004de: 60f8 str r0, [r7, #12] 80004e0: 60b9 str r1, [r7, #8] 80004e2: 607a str r2, [r7, #4] 80004e4: 603b str r3, [r7, #0] MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 80004e6: 4b0a ldr r3, [pc, #40] ; (8000510 ) 80004e8: 68da ldr r2, [r3, #12] 80004ea: 4b0a ldr r3, [pc, #40] ; (8000514 ) 80004ec: 4013 ands r3, r2 80004ee: 68f9 ldr r1, [r7, #12] 80004f0: 68ba ldr r2, [r7, #8] 80004f2: 4311 orrs r1, r2 80004f4: 687a ldr r2, [r7, #4] 80004f6: 0212 lsls r2, r2, #8 80004f8: 4311 orrs r1, r2 80004fa: 683a ldr r2, [r7, #0] 80004fc: 430a orrs r2, r1 80004fe: 4904 ldr r1, [pc, #16] ; (8000510 ) 8000500: 4313 orrs r3, r2 8000502: 60cb str r3, [r1, #12] Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); } 8000504: bf00 nop 8000506: 3714 adds r7, #20 8000508: 46bd mov sp, r7 800050a: f85d 7b04 ldr.w r7, [sp], #4 800050e: 4770 bx lr 8000510: 40021000 .word 0x40021000 8000514: f9ff808c .word 0xf9ff808c 08000518 : * @brief Enable PLL output mapped on SYSCLK domain * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS * @retval None */ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) { 8000518: b480 push {r7} 800051a: af00 add r7, sp, #0 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); 800051c: 4b05 ldr r3, [pc, #20] ; (8000534 ) 800051e: 68db ldr r3, [r3, #12] 8000520: 4a04 ldr r2, [pc, #16] ; (8000534 ) 8000522: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8000526: 60d3 str r3, [r2, #12] } 8000528: bf00 nop 800052a: 46bd mov sp, r7 800052c: f85d 7b04 ldr.w r7, [sp], #4 8000530: 4770 bx lr 8000532: bf00 nop 8000534: 40021000 .word 0x40021000 08000538 : * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) { 8000538: b480 push {r7} 800053a: b083 sub sp, #12 800053c: af00 add r7, sp, #0 800053e: 6078 str r0, [r7, #4] MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 8000540: 4b06 ldr r3, [pc, #24] ; (800055c ) 8000542: 681b ldr r3, [r3, #0] 8000544: f023 0207 bic.w r2, r3, #7 8000548: 4904 ldr r1, [pc, #16] ; (800055c ) 800054a: 687b ldr r3, [r7, #4] 800054c: 4313 orrs r3, r2 800054e: 600b str r3, [r1, #0] } 8000550: bf00 nop 8000552: 370c adds r7, #12 8000554: 46bd mov sp, r7 8000556: f85d 7b04 ldr.w r7, [sp], #4 800055a: 4770 bx lr 800055c: 40022000 .word 0x40022000 08000560
: //} void SystemClock_Config(void); int main(void) { 8000560: b580 push {r7, lr} 8000562: af00 add r7, sp, #0 /* Configure the system clock */ SystemClock_Config(); 8000564: f000 f820 bl 80005a8 // config GPIO GPIO_init(); 8000568: f7ff fecc bl 8000304 // init systick timer (tick period at 1 ms) LL_Init1msTick( SystemCoreClock ); 800056c: 4b0d ldr r3, [pc, #52] ; (80005a4 ) 800056e: 681b ldr r3, [r3, #0] 8000570: 4618 mov r0, r3 8000572: f000 f9af bl 80008d4 while (1) { if ( BLUE_BUTTON() ) 8000576: f7ff fef9 bl 800036c 800057a: 4603 mov r3, r0 800057c: 2b00 cmp r3, #0 800057e: d003 beq.n 8000588 LED_GREEN(1); 8000580: 2001 movs r0, #1 8000582: f7ff fedd bl 8000340 8000586: e7f6 b.n 8000576 else { LED_GREEN(0); 8000588: 2000 movs r0, #0 800058a: f7ff fed9 bl 8000340 LL_mDelay(950); 800058e: f240 30b6 movw r0, #950 ; 0x3b6 8000592: f000 f9ad bl 80008f0 LED_GREEN(1); 8000596: 2001 movs r0, #1 8000598: f7ff fed2 bl 8000340 LL_mDelay(50); 800059c: 2032 movs r0, #50 ; 0x32 800059e: f000 f9a7 bl 80008f0 if ( BLUE_BUTTON() ) 80005a2: e7e8 b.n 8000576 80005a4: 20000000 .word 0x20000000 080005a8 : * PLL_R = 2 * Flash Latency(WS) = 4 * @param None * @retval None */ void SystemClock_Config(void) { 80005a8: b580 push {r7, lr} 80005aa: af00 add r7, sp, #0 /* MSI configuration and activation */ LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); 80005ac: 2004 movs r0, #4 80005ae: f7ff ffc3 bl 8000538 LL_RCC_MSI_Enable(); 80005b2: f7ff feed bl 8000390 while (LL_RCC_MSI_IsReady() != 1) 80005b6: bf00 nop 80005b8: f7ff fefa bl 80003b0 80005bc: 4603 mov r3, r0 80005be: 2b01 cmp r3, #1 80005c0: d1fa bne.n 80005b8 { }; /* Main PLL configuration and activation */ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2); 80005c2: 2300 movs r3, #0 80005c4: 2228 movs r2, #40 ; 0x28 80005c6: 2100 movs r1, #0 80005c8: 2001 movs r0, #1 80005ca: f7ff ff85 bl 80004d8 LL_RCC_PLL_Enable(); 80005ce: f7ff ff5f bl 8000490 LL_RCC_PLL_EnableDomain_SYS(); 80005d2: f7ff ffa1 bl 8000518 while(LL_RCC_PLL_IsReady() != 1) 80005d6: bf00 nop 80005d8: f7ff ff6a bl 80004b0 80005dc: 4603 mov r3, r0 80005de: 2b01 cmp r3, #1 80005e0: d1fa bne.n 80005d8 { }; /* Sysclk activation on the main PLL */ LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); 80005e2: 2000 movs r0, #0 80005e4: f7ff ff18 bl 8000418 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); 80005e8: 2003 movs r0, #3 80005ea: f7ff fef3 bl 80003d4 while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) 80005ee: bf00 nop 80005f0: f7ff ff04 bl 80003fc 80005f4: 4603 mov r3, r0 80005f6: 2b0c cmp r3, #12 80005f8: d1fa bne.n 80005f0 { }; /* Set APB1 & APB2 prescaler*/ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); 80005fa: 2000 movs r0, #0 80005fc: f7ff ff20 bl 8000440 LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); 8000600: 2000 movs r0, #0 8000602: f7ff ff31 bl 8000468 /* Update the global variable called SystemCoreClock */ SystemCoreClockUpdate(); 8000606: f000 f867 bl 80006d8 } 800060a: bf00 nop 800060c: bd80 pop {r7, pc} 0800060e : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800060e: b480 push {r7} 8000610: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 8000612: bf00 nop 8000614: 46bd mov sp, r7 8000616: f85d 7b04 ldr.w r7, [sp], #4 800061a: 4770 bx lr 0800061c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800061c: b480 push {r7} 800061e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000620: e7fe b.n 8000620 08000622 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000622: b480 push {r7} 8000624: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000626: e7fe b.n 8000626 08000628 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8000628: b480 push {r7} 800062a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800062c: e7fe b.n 800062c 0800062e : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800062e: b480 push {r7} 8000630: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000632: e7fe b.n 8000632 08000634 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000634: b480 push {r7} 8000636: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000638: bf00 nop 800063a: 46bd mov sp, r7 800063c: f85d 7b04 ldr.w r7, [sp], #4 8000640: 4770 bx lr 08000642 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000642: b480 push {r7} 8000644: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000646: bf00 nop 8000648: 46bd mov sp, r7 800064a: f85d 7b04 ldr.w r7, [sp], #4 800064e: 4770 bx lr 08000650 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000650: b480 push {r7} 8000652: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000654: bf00 nop 8000656: 46bd mov sp, r7 8000658: f85d 7b04 ldr.w r7, [sp], #4 800065c: 4770 bx lr 0800065e : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800065e: b480 push {r7} 8000660: af00 add r7, sp, #0 /* USER CODE END SysTick_IRQn 0 */ /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000662: bf00 nop 8000664: 46bd mov sp, r7 8000666: f85d 7b04 ldr.w r7, [sp], #4 800066a: 4770 bx lr 0800066c : * @param None * @retval None */ void SystemInit(void) { 800066c: b480 push {r7} 800066e: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8000670: 4b17 ldr r3, [pc, #92] ; (80006d0 ) 8000672: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8000676: 4a16 ldr r2, [pc, #88] ; (80006d0 ) 8000678: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 800067c: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ RCC->CR |= RCC_CR_MSION; 8000680: 4b14 ldr r3, [pc, #80] ; (80006d4 ) 8000682: 681b ldr r3, [r3, #0] 8000684: 4a13 ldr r2, [pc, #76] ; (80006d4 ) 8000686: f043 0301 orr.w r3, r3, #1 800068a: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000U; 800068c: 4b11 ldr r3, [pc, #68] ; (80006d4 ) 800068e: 2200 movs r2, #0 8000690: 609a str r2, [r3, #8] /* Reset HSEON, CSSON , HSION, and PLLON bits */ RCC->CR &= 0xEAF6FFFFU; 8000692: 4b10 ldr r3, [pc, #64] ; (80006d4 ) 8000694: 681b ldr r3, [r3, #0] 8000696: 4a0f ldr r2, [pc, #60] ; (80006d4 ) 8000698: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000 800069c: f423 2310 bic.w r3, r3, #589824 ; 0x90000 80006a0: 6013 str r3, [r2, #0] /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x00001000U; 80006a2: 4b0c ldr r3, [pc, #48] ; (80006d4 ) 80006a4: f44f 5280 mov.w r2, #4096 ; 0x1000 80006a8: 60da str r2, [r3, #12] /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 80006aa: 4b0a ldr r3, [pc, #40] ; (80006d4 ) 80006ac: 681b ldr r3, [r3, #0] 80006ae: 4a09 ldr r2, [pc, #36] ; (80006d4 ) 80006b0: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80006b4: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000U; 80006b6: 4b07 ldr r3, [pc, #28] ; (80006d4 ) 80006b8: 2200 movs r2, #0 80006ba: 619a str r2, [r3, #24] /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 80006bc: 4b04 ldr r3, [pc, #16] ; (80006d0 ) 80006be: f04f 6200 mov.w r2, #134217728 ; 0x8000000 80006c2: 609a str r2, [r3, #8] #endif } 80006c4: bf00 nop 80006c6: 46bd mov sp, r7 80006c8: f85d 7b04 ldr.w r7, [sp], #4 80006cc: 4770 bx lr 80006ce: bf00 nop 80006d0: e000ed00 .word 0xe000ed00 80006d4: 40021000 .word 0x40021000 080006d8 : * * @param None * @retval None */ void SystemCoreClockUpdate(void) { 80006d8: b480 push {r7} 80006da: b087 sub sp, #28 80006dc: af00 add r7, sp, #0 uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; 80006de: 2300 movs r3, #0 80006e0: 60fb str r3, [r7, #12] 80006e2: 2300 movs r3, #0 80006e4: 617b str r3, [r7, #20] 80006e6: 2300 movs r3, #0 80006e8: 613b str r3, [r7, #16] 80006ea: 2302 movs r3, #2 80006ec: 60bb str r3, [r7, #8] 80006ee: 2300 movs r3, #0 80006f0: 607b str r3, [r7, #4] 80006f2: 2302 movs r3, #2 80006f4: 603b str r3, [r7, #0] /* Get MSI Range frequency--------------------------------------------------*/ if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) 80006f6: 4b4f ldr r3, [pc, #316] ; (8000834 ) 80006f8: 681b ldr r3, [r3, #0] 80006fa: f003 0308 and.w r3, r3, #8 80006fe: 2b00 cmp r3, #0 8000700: d107 bne.n 8000712 { /* MSISRANGE from RCC_CSR applies */ msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; 8000702: 4b4c ldr r3, [pc, #304] ; (8000834 ) 8000704: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8000708: 0a1b lsrs r3, r3, #8 800070a: f003 030f and.w r3, r3, #15 800070e: 617b str r3, [r7, #20] 8000710: e005 b.n 800071e } else { /* MSIRANGE from RCC_CR applies */ msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; 8000712: 4b48 ldr r3, [pc, #288] ; (8000834 ) 8000714: 681b ldr r3, [r3, #0] 8000716: 091b lsrs r3, r3, #4 8000718: f003 030f and.w r3, r3, #15 800071c: 617b str r3, [r7, #20] } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; 800071e: 4a46 ldr r2, [pc, #280] ; (8000838 ) 8000720: 697b ldr r3, [r7, #20] 8000722: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000726: 617b str r3, [r7, #20] /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8000728: 4b42 ldr r3, [pc, #264] ; (8000834 ) 800072a: 689b ldr r3, [r3, #8] 800072c: f003 030c and.w r3, r3, #12 8000730: 2b0c cmp r3, #12 8000732: d865 bhi.n 8000800 8000734: a201 add r2, pc, #4 ; (adr r2, 800073c ) 8000736: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800073a: bf00 nop 800073c: 08000771 .word 0x08000771 8000740: 08000801 .word 0x08000801 8000744: 08000801 .word 0x08000801 8000748: 08000801 .word 0x08000801 800074c: 08000779 .word 0x08000779 8000750: 08000801 .word 0x08000801 8000754: 08000801 .word 0x08000801 8000758: 08000801 .word 0x08000801 800075c: 08000781 .word 0x08000781 8000760: 08000801 .word 0x08000801 8000764: 08000801 .word 0x08000801 8000768: 08000801 .word 0x08000801 800076c: 08000789 .word 0x08000789 { case 0x00: /* MSI used as system clock source */ SystemCoreClock = msirange; 8000770: 4a32 ldr r2, [pc, #200] ; (800083c ) 8000772: 697b ldr r3, [r7, #20] 8000774: 6013 str r3, [r2, #0] break; 8000776: e047 b.n 8000808 case 0x04: /* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; 8000778: 4b30 ldr r3, [pc, #192] ; (800083c ) 800077a: 4a31 ldr r2, [pc, #196] ; (8000840 ) 800077c: 601a str r2, [r3, #0] break; 800077e: e043 b.n 8000808 case 0x08: /* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; 8000780: 4b2e ldr r3, [pc, #184] ; (800083c ) 8000782: 4a30 ldr r2, [pc, #192] ; (8000844 ) 8000784: 601a str r2, [r3, #0] break; 8000786: e03f b.n 8000808 case 0x0C: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 8000788: 4b2a ldr r3, [pc, #168] ; (8000834 ) 800078a: 68db ldr r3, [r3, #12] 800078c: f003 0303 and.w r3, r3, #3 8000790: 607b str r3, [r7, #4] pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; 8000792: 4b28 ldr r3, [pc, #160] ; (8000834 ) 8000794: 68db ldr r3, [r3, #12] 8000796: 091b lsrs r3, r3, #4 8000798: f003 0307 and.w r3, r3, #7 800079c: 3301 adds r3, #1 800079e: 603b str r3, [r7, #0] switch (pllsource) 80007a0: 687b ldr r3, [r7, #4] 80007a2: 2b02 cmp r3, #2 80007a4: d002 beq.n 80007ac 80007a6: 2b03 cmp r3, #3 80007a8: d006 beq.n 80007b8 80007aa: e00b b.n 80007c4 { case 0x02: /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm); 80007ac: 4a24 ldr r2, [pc, #144] ; (8000840 ) 80007ae: 683b ldr r3, [r7, #0] 80007b0: fbb2 f3f3 udiv r3, r2, r3 80007b4: 613b str r3, [r7, #16] break; 80007b6: e00b b.n 80007d0 case 0x03: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm); 80007b8: 4a22 ldr r2, [pc, #136] ; (8000844 ) 80007ba: 683b ldr r3, [r7, #0] 80007bc: fbb2 f3f3 udiv r3, r2, r3 80007c0: 613b str r3, [r7, #16] break; 80007c2: e005 b.n 80007d0 default: /* MSI used as PLL clock source */ pllvco = (msirange / pllm); 80007c4: 697a ldr r2, [r7, #20] 80007c6: 683b ldr r3, [r7, #0] 80007c8: fbb2 f3f3 udiv r3, r2, r3 80007cc: 613b str r3, [r7, #16] break; 80007ce: bf00 nop } pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); 80007d0: 4b18 ldr r3, [pc, #96] ; (8000834 ) 80007d2: 68db ldr r3, [r3, #12] 80007d4: 0a1b lsrs r3, r3, #8 80007d6: f003 027f and.w r2, r3, #127 ; 0x7f 80007da: 693b ldr r3, [r7, #16] 80007dc: fb02 f303 mul.w r3, r2, r3 80007e0: 613b str r3, [r7, #16] pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; 80007e2: 4b14 ldr r3, [pc, #80] ; (8000834 ) 80007e4: 68db ldr r3, [r3, #12] 80007e6: 0e5b lsrs r3, r3, #25 80007e8: f003 0303 and.w r3, r3, #3 80007ec: 3301 adds r3, #1 80007ee: 005b lsls r3, r3, #1 80007f0: 60bb str r3, [r7, #8] SystemCoreClock = pllvco/pllr; 80007f2: 693a ldr r2, [r7, #16] 80007f4: 68bb ldr r3, [r7, #8] 80007f6: fbb2 f3f3 udiv r3, r2, r3 80007fa: 4a10 ldr r2, [pc, #64] ; (800083c ) 80007fc: 6013 str r3, [r2, #0] break; 80007fe: e003 b.n 8000808 default: SystemCoreClock = msirange; 8000800: 4a0e ldr r2, [pc, #56] ; (800083c ) 8000802: 697b ldr r3, [r7, #20] 8000804: 6013 str r3, [r2, #0] break; 8000806: bf00 nop } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; 8000808: 4b0a ldr r3, [pc, #40] ; (8000834 ) 800080a: 689b ldr r3, [r3, #8] 800080c: 091b lsrs r3, r3, #4 800080e: f003 030f and.w r3, r3, #15 8000812: 4a0d ldr r2, [pc, #52] ; (8000848 ) 8000814: 5cd3 ldrb r3, [r2, r3] 8000816: 60fb str r3, [r7, #12] /* HCLK clock frequency */ SystemCoreClock >>= tmp; 8000818: 4b08 ldr r3, [pc, #32] ; (800083c ) 800081a: 681a ldr r2, [r3, #0] 800081c: 68fb ldr r3, [r7, #12] 800081e: fa22 f303 lsr.w r3, r2, r3 8000822: 4a06 ldr r2, [pc, #24] ; (800083c ) 8000824: 6013 str r3, [r2, #0] } 8000826: bf00 nop 8000828: 371c adds r7, #28 800082a: 46bd mov sp, r7 800082c: f85d 7b04 ldr.w r7, [sp], #4 8000830: 4770 bx lr 8000832: bf00 nop 8000834: 40021000 .word 0x40021000 8000838: 080009ac .word 0x080009ac 800083c: 20000000 .word 0x20000000 8000840: 00f42400 .word 0x00f42400 8000844: 007a1200 .word 0x007a1200 8000848: 0800099c .word 0x0800099c 0800084c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Set stack pointer */ 800084c: f8df d034 ldr.w sp, [pc, #52] ; 8000884 /* Call the clock system initialization function.*/ bl SystemInit 8000850: f7ff ff0c bl 800066c /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8000854: 2100 movs r1, #0 b LoopCopyDataInit 8000856: e003 b.n 8000860 08000858 : CopyDataInit: ldr r3, =_sidata 8000858: 4b0b ldr r3, [pc, #44] ; (8000888 ) ldr r3, [r3, r1] 800085a: 585b ldr r3, [r3, r1] str r3, [r0, r1] 800085c: 5043 str r3, [r0, r1] adds r1, r1, #4 800085e: 3104 adds r1, #4 08000860 : LoopCopyDataInit: ldr r0, =_sdata 8000860: 480a ldr r0, [pc, #40] ; (800088c ) ldr r3, =_edata 8000862: 4b0b ldr r3, [pc, #44] ; (8000890 ) adds r2, r0, r1 8000864: 1842 adds r2, r0, r1 cmp r2, r3 8000866: 429a cmp r2, r3 bcc CopyDataInit 8000868: d3f6 bcc.n 8000858 ldr r2, =_sbss 800086a: 4a0a ldr r2, [pc, #40] ; (8000894 ) b LoopFillZerobss 800086c: e002 b.n 8000874 0800086e : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 800086e: 2300 movs r3, #0 str r3, [r2], #4 8000870: f842 3b04 str.w r3, [r2], #4 08000874 : LoopFillZerobss: ldr r3, = _ebss 8000874: 4b08 ldr r3, [pc, #32] ; (8000898 ) cmp r2, r3 8000876: 429a cmp r2, r3 bcc FillZerobss 8000878: d3f9 bcc.n 800086e /* Call static constructors */ bl __libc_init_array 800087a: f000 f85f bl 800093c <__libc_init_array> /* Call the application's entry point.*/ bl main 800087e: f7ff fe6f bl 8000560
08000882 : LoopForever: b LoopForever 8000882: e7fe b.n 8000882 ldr sp, =_estack /* Set stack pointer */ 8000884: 20018000 .word 0x20018000 ldr r3, =_sidata 8000888: 080009e4 .word 0x080009e4 ldr r0, =_sdata 800088c: 20000000 .word 0x20000000 ldr r3, =_edata 8000890: 20000004 .word 0x20000004 ldr r2, =_sbss 8000894: 20000004 .word 0x20000004 ldr r3, = _ebss 8000898: 20000020 .word 0x20000020 0800089c : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800089c: e7fe b.n 800089c ... 080008a0 : * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param Ticks Number of ticks * @retval None */ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) { 80008a0: b480 push {r7} 80008a2: b083 sub sp, #12 80008a4: af00 add r7, sp, #0 80008a6: 6078 str r0, [r7, #4] 80008a8: 6039 str r1, [r7, #0] /* Configure the SysTick to have interrupt in 1ms time base */ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ 80008aa: 687a ldr r2, [r7, #4] 80008ac: 683b ldr r3, [r7, #0] 80008ae: fbb2 f3f3 udiv r3, r2, r3 80008b2: 4a07 ldr r2, [pc, #28] ; (80008d0 ) 80008b4: 3b01 subs r3, #1 80008b6: 6053 str r3, [r2, #4] SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80008b8: 4b05 ldr r3, [pc, #20] ; (80008d0 ) 80008ba: 2200 movs r2, #0 80008bc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80008be: 4b04 ldr r3, [pc, #16] ; (80008d0 ) 80008c0: 2205 movs r2, #5 80008c2: 601a str r2, [r3, #0] SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ } 80008c4: bf00 nop 80008c6: 370c adds r7, #12 80008c8: 46bd mov sp, r7 80008ca: f85d 7b04 ldr.w r7, [sp], #4 80008ce: 4770 bx lr 80008d0: e000e010 .word 0xe000e010 080008d4 : * @param HCLKFrequency HCLK frequency in Hz * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq * @retval None */ void LL_Init1msTick(uint32_t HCLKFrequency) { 80008d4: b580 push {r7, lr} 80008d6: b082 sub sp, #8 80008d8: af00 add r7, sp, #0 80008da: 6078 str r0, [r7, #4] /* Use frequency provided in argument */ LL_InitTick(HCLKFrequency, 1000U); 80008dc: f44f 717a mov.w r1, #1000 ; 0x3e8 80008e0: 6878 ldr r0, [r7, #4] 80008e2: f7ff ffdd bl 80008a0 } 80008e6: bf00 nop 80008e8: 3708 adds r7, #8 80008ea: 46bd mov sp, r7 80008ec: bd80 pop {r7, pc} ... 080008f0 : * will configure Systick to 1ms * @param Delay specifies the delay time length, in milliseconds. * @retval None */ void LL_mDelay(uint32_t Delay) { 80008f0: b480 push {r7} 80008f2: b085 sub sp, #20 80008f4: af00 add r7, sp, #0 80008f6: 6078 str r0, [r7, #4] __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ 80008f8: 4b0f ldr r3, [pc, #60] ; (8000938 ) 80008fa: 681b ldr r3, [r3, #0] 80008fc: 60bb str r3, [r7, #8] uint32_t tmpDelay = Delay; 80008fe: 687b ldr r3, [r7, #4] 8000900: 60fb str r3, [r7, #12] /* Add this code to indicate that local variable is not used */ ((void)tmp); 8000902: 68bb ldr r3, [r7, #8] /* Add a period to guaranty minimum wait */ if(tmpDelay < LL_MAX_DELAY) 8000904: 68fb ldr r3, [r7, #12] 8000906: f1b3 3fff cmp.w r3, #4294967295 800090a: d00c beq.n 8000926 { tmpDelay++; 800090c: 68fb ldr r3, [r7, #12] 800090e: 3301 adds r3, #1 8000910: 60fb str r3, [r7, #12] } while (tmpDelay != 0U) 8000912: e008 b.n 8000926 { if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) 8000914: 4b08 ldr r3, [pc, #32] ; (8000938 ) 8000916: 681b ldr r3, [r3, #0] 8000918: f403 3380 and.w r3, r3, #65536 ; 0x10000 800091c: 2b00 cmp r3, #0 800091e: d002 beq.n 8000926 { tmpDelay--; 8000920: 68fb ldr r3, [r7, #12] 8000922: 3b01 subs r3, #1 8000924: 60fb str r3, [r7, #12] while (tmpDelay != 0U) 8000926: 68fb ldr r3, [r7, #12] 8000928: 2b00 cmp r3, #0 800092a: d1f3 bne.n 8000914 } } } 800092c: bf00 nop 800092e: 3714 adds r7, #20 8000930: 46bd mov sp, r7 8000932: f85d 7b04 ldr.w r7, [sp], #4 8000936: 4770 bx lr 8000938: e000e010 .word 0xe000e010 0800093c <__libc_init_array>: 800093c: b570 push {r4, r5, r6, lr} 800093e: 4e0d ldr r6, [pc, #52] ; (8000974 <__libc_init_array+0x38>) 8000940: 4c0d ldr r4, [pc, #52] ; (8000978 <__libc_init_array+0x3c>) 8000942: 1ba4 subs r4, r4, r6 8000944: 10a4 asrs r4, r4, #2 8000946: 2500 movs r5, #0 8000948: 42a5 cmp r5, r4 800094a: d109 bne.n 8000960 <__libc_init_array+0x24> 800094c: 4e0b ldr r6, [pc, #44] ; (800097c <__libc_init_array+0x40>) 800094e: 4c0c ldr r4, [pc, #48] ; (8000980 <__libc_init_array+0x44>) 8000950: f000 f818 bl 8000984 <_init> 8000954: 1ba4 subs r4, r4, r6 8000956: 10a4 asrs r4, r4, #2 8000958: 2500 movs r5, #0 800095a: 42a5 cmp r5, r4 800095c: d105 bne.n 800096a <__libc_init_array+0x2e> 800095e: bd70 pop {r4, r5, r6, pc} 8000960: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8000964: 4798 blx r3 8000966: 3501 adds r5, #1 8000968: e7ee b.n 8000948 <__libc_init_array+0xc> 800096a: f856 3025 ldr.w r3, [r6, r5, lsl #2] 800096e: 4798 blx r3 8000970: 3501 adds r5, #1 8000972: e7f2 b.n 800095a <__libc_init_array+0x1e> 8000974: 080009dc .word 0x080009dc 8000978: 080009dc .word 0x080009dc 800097c: 080009dc .word 0x080009dc 8000980: 080009e0 .word 0x080009e0 08000984 <_init>: 8000984: b5f8 push {r3, r4, r5, r6, r7, lr} 8000986: bf00 nop 8000988: bcf8 pop {r3, r4, r5, r6, r7} 800098a: bc08 pop {r3} 800098c: 469e mov lr, r3 800098e: 4770 bx lr 08000990 <_fini>: 8000990: b5f8 push {r3, r4, r5, r6, r7, lr} 8000992: bf00 nop 8000994: bcf8 pop {r3, r4, r5, r6, r7} 8000996: bc08 pop {r3} 8000998: 469e mov lr, r3 800099a: 4770 bx lr