L476_ats_blink-master.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00000890 08000188 08000188 00010188 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000040 08000a18 08000a18 00010a18 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08000a58 08000a58 00020004 2**0 CONTENTS 4 .ARM 00000000 08000a58 08000a58 00020004 2**0 CONTENTS 5 .preinit_array 00000000 08000a58 08000a58 00020004 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08000a58 08000a58 00010a58 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08000a5c 08000a5c 00010a5c 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000004 20000000 08000a60 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000024 20000004 08000a64 00020004 2**2 ALLOC 10 ._user_heap_stack 00000600 20000028 08000a64 00020028 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 00020004 2**0 CONTENTS, READONLY 12 .debug_info 00002a6f 00000000 00000000 00020034 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 0000086e 00000000 00000000 00022aa3 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 000002f0 00000000 00000000 00023318 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 00000298 00000000 00000000 00023608 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 0002572e 00000000 00000000 000238a0 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 00002b6b 00000000 00000000 00048fce 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 000ed85b 00000000 00000000 0004bb39 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 00139394 2**0 CONTENTS, READONLY 20 .debug_frame 00000a64 00000000 00000000 00139410 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 08000188 <__do_global_dtors_aux>: 8000188: b510 push {r4, lr} 800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>) 800018c: 7823 ldrb r3, [r4, #0] 800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16> 8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>) 8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12> 8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>) 8000196: f3af 8000 nop.w 800019a: 2301 movs r3, #1 800019c: 7023 strb r3, [r4, #0] 800019e: bd10 pop {r4, pc} 80001a0: 20000004 .word 0x20000004 80001a4: 00000000 .word 0x00000000 80001a8: 08000a00 .word 0x08000a00 080001ac : 80001ac: b508 push {r3, lr} 80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc ) 80001b0: b11b cbz r3, 80001ba 80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 ) 80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 ) 80001b6: f3af 8000 nop.w 80001ba: bd08 pop {r3, pc} 80001bc: 00000000 .word 0x00000000 80001c0: 20000008 .word 0x20000008 80001c4: 08000a00 .word 0x08000a00 080001c8 : * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) { 80001c8: b480 push {r7} 80001ca: b085 sub sp, #20 80001cc: af00 add r7, sp, #0 80001ce: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, Periphs); 80001d0: 4b08 ldr r3, [pc, #32] ; (80001f4 ) 80001d2: 6cda ldr r2, [r3, #76] ; 0x4c 80001d4: 4907 ldr r1, [pc, #28] ; (80001f4 ) 80001d6: 687b ldr r3, [r7, #4] 80001d8: 4313 orrs r3, r2 80001da: 64cb str r3, [r1, #76] ; 0x4c /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 80001dc: 4b05 ldr r3, [pc, #20] ; (80001f4 ) 80001de: 6cda ldr r2, [r3, #76] ; 0x4c 80001e0: 687b ldr r3, [r7, #4] 80001e2: 4013 ands r3, r2 80001e4: 60fb str r3, [r7, #12] (void)tmpreg; 80001e6: 68fb ldr r3, [r7, #12] } 80001e8: bf00 nop 80001ea: 3714 adds r7, #20 80001ec: 46bd mov sp, r7 80001ee: f85d 7b04 ldr.w r7, [sp], #4 80001f2: 4770 bx lr 80001f4: 40021000 .word 0x40021000 080001f8 : * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { 80001f8: b480 push {r7} 80001fa: b08b sub sp, #44 ; 0x2c 80001fc: af00 add r7, sp, #0 80001fe: 60f8 str r0, [r7, #12] 8000200: 60b9 str r1, [r7, #8] 8000202: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); 8000204: 68fb ldr r3, [r7, #12] 8000206: 681a ldr r2, [r3, #0] 8000208: 68bb ldr r3, [r7, #8] 800020a: 617b str r3, [r7, #20] uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800020c: 697b ldr r3, [r7, #20] 800020e: fa93 f3a3 rbit r3, r3 8000212: 613b str r3, [r7, #16] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8000214: 693b ldr r3, [r7, #16] 8000216: 61bb str r3, [r7, #24] optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8000218: 69bb ldr r3, [r7, #24] 800021a: 2b00 cmp r3, #0 800021c: d101 bne.n 8000222 { return 32U; 800021e: 2320 movs r3, #32 8000220: e003 b.n 800022a } return __builtin_clz(value); 8000222: 69bb ldr r3, [r7, #24] 8000224: fab3 f383 clz r3, r3 8000228: b2db uxtb r3, r3 800022a: 005b lsls r3, r3, #1 800022c: 2103 movs r1, #3 800022e: fa01 f303 lsl.w r3, r1, r3 8000232: 43db mvns r3, r3 8000234: 401a ands r2, r3 8000236: 68bb ldr r3, [r7, #8] 8000238: 623b str r3, [r7, #32] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800023a: 6a3b ldr r3, [r7, #32] 800023c: fa93 f3a3 rbit r3, r3 8000240: 61fb str r3, [r7, #28] return result; 8000242: 69fb ldr r3, [r7, #28] 8000244: 627b str r3, [r7, #36] ; 0x24 if (value == 0U) 8000246: 6a7b ldr r3, [r7, #36] ; 0x24 8000248: 2b00 cmp r3, #0 800024a: d101 bne.n 8000250 return 32U; 800024c: 2320 movs r3, #32 800024e: e003 b.n 8000258 return __builtin_clz(value); 8000250: 6a7b ldr r3, [r7, #36] ; 0x24 8000252: fab3 f383 clz r3, r3 8000256: b2db uxtb r3, r3 8000258: 005b lsls r3, r3, #1 800025a: 6879 ldr r1, [r7, #4] 800025c: fa01 f303 lsl.w r3, r1, r3 8000260: 431a orrs r2, r3 8000262: 68fb ldr r3, [r7, #12] 8000264: 601a str r2, [r3, #0] } 8000266: bf00 nop 8000268: 372c adds r7, #44 ; 0x2c 800026a: 46bd mov sp, r7 800026c: f85d 7b04 ldr.w r7, [sp], #4 8000270: 4770 bx lr 08000272 : * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { 8000272: b480 push {r7} 8000274: b085 sub sp, #20 8000276: af00 add r7, sp, #0 8000278: 60f8 str r0, [r7, #12] 800027a: 60b9 str r1, [r7, #8] 800027c: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); 800027e: 68fb ldr r3, [r7, #12] 8000280: 685a ldr r2, [r3, #4] 8000282: 68bb ldr r3, [r7, #8] 8000284: 43db mvns r3, r3 8000286: 401a ands r2, r3 8000288: 68bb ldr r3, [r7, #8] 800028a: 6879 ldr r1, [r7, #4] 800028c: fb01 f303 mul.w r3, r1, r3 8000290: 431a orrs r2, r3 8000292: 68fb ldr r3, [r7, #12] 8000294: 605a str r2, [r3, #4] } 8000296: bf00 nop 8000298: 3714 adds r7, #20 800029a: 46bd mov sp, r7 800029c: f85d 7b04 ldr.w r7, [sp], #4 80002a0: 4770 bx lr 080002a2 : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 80002a2: b480 push {r7} 80002a4: b083 sub sp, #12 80002a6: af00 add r7, sp, #0 80002a8: 6078 str r0, [r7, #4] 80002aa: 6039 str r1, [r7, #0] return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); 80002ac: 687b ldr r3, [r7, #4] 80002ae: 691a ldr r2, [r3, #16] 80002b0: 683b ldr r3, [r7, #0] 80002b2: 4013 ands r3, r2 80002b4: 683a ldr r2, [r7, #0] 80002b6: 429a cmp r2, r3 80002b8: d101 bne.n 80002be 80002ba: 2301 movs r3, #1 80002bc: e000 b.n 80002c0 80002be: 2300 movs r3, #0 } 80002c0: 4618 mov r0, r3 80002c2: 370c adds r7, #12 80002c4: 46bd mov sp, r7 80002c6: f85d 7b04 ldr.w r7, [sp], #4 80002ca: 4770 bx lr 080002cc : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 80002cc: b480 push {r7} 80002ce: b083 sub sp, #12 80002d0: af00 add r7, sp, #0 80002d2: 6078 str r0, [r7, #4] 80002d4: 6039 str r1, [r7, #0] WRITE_REG(GPIOx->BSRR, PinMask); 80002d6: 687b ldr r3, [r7, #4] 80002d8: 683a ldr r2, [r7, #0] 80002da: 619a str r2, [r3, #24] } 80002dc: bf00 nop 80002de: 370c adds r7, #12 80002e0: 46bd mov sp, r7 80002e2: f85d 7b04 ldr.w r7, [sp], #4 80002e6: 4770 bx lr 080002e8 : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 80002e8: b480 push {r7} 80002ea: b083 sub sp, #12 80002ec: af00 add r7, sp, #0 80002ee: 6078 str r0, [r7, #4] 80002f0: 6039 str r1, [r7, #0] WRITE_REG(GPIOx->BRR, PinMask); 80002f2: 687b ldr r3, [r7, #4] 80002f4: 683a ldr r2, [r7, #0] 80002f6: 629a str r2, [r3, #40] ; 0x28 } 80002f8: bf00 nop 80002fa: 370c adds r7, #12 80002fc: 46bd mov sp, r7 80002fe: f85d 7b04 ldr.w r7, [sp], #4 8000302: 4770 bx lr 08000304 : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 8000304: b480 push {r7} 8000306: b085 sub sp, #20 8000308: af00 add r7, sp, #0 800030a: 6078 str r0, [r7, #4] 800030c: 6039 str r1, [r7, #0] uint32_t odr = READ_REG(GPIOx->ODR); 800030e: 687b ldr r3, [r7, #4] 8000310: 695b ldr r3, [r3, #20] 8000312: 60fb str r3, [r7, #12] WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); 8000314: 68fa ldr r2, [r7, #12] 8000316: 683b ldr r3, [r7, #0] 8000318: 4013 ands r3, r2 800031a: 041a lsls r2, r3, #16 800031c: 68fb ldr r3, [r7, #12] 800031e: 43d9 mvns r1, r3 8000320: 683b ldr r3, [r7, #0] 8000322: 400b ands r3, r1 8000324: 431a orrs r2, r3 8000326: 687b ldr r3, [r7, #4] 8000328: 619a str r2, [r3, #24] } 800032a: bf00 nop 800032c: 3714 adds r7, #20 800032e: 46bd mov sp, r7 8000330: f85d 7b04 ldr.w r7, [sp], #4 8000334: 4770 bx lr ... 08000338 : #define BUT_PORT GPIOC #define BUT_PIN LL_GPIO_PIN_13 #define CLK_PIN LL_GPIO_PIN_10 void GPIO_init(void) { 8000338: b580 push {r7, lr} 800033a: af00 add r7, sp, #0 // PORT A LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA ); 800033c: 2001 movs r0, #1 800033e: f7ff ff43 bl 80001c8 // Green LED (user LED) - PA5 LL_GPIO_SetPinMode( LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT ); 8000342: 2201 movs r2, #1 8000344: 2120 movs r1, #32 8000346: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 800034a: f7ff ff55 bl 80001f8 LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL ); 800034e: 2200 movs r2, #0 8000350: 2120 movs r1, #32 8000352: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8000356: f7ff ff8c bl 8000272 // PORT C LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC ); 800035a: 2004 movs r0, #4 800035c: f7ff ff34 bl 80001c8 // Blue button - PC13 LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT ); 8000360: 2200 movs r2, #0 8000362: f44f 5100 mov.w r1, #8192 ; 0x2000 8000366: 4805 ldr r0, [pc, #20] ; (800037c ) 8000368: f7ff ff46 bl 80001f8 LL_GPIO_SetPinMode( BUT_PORT, CLK_PIN, LL_GPIO_MODE_OUTPUT ); 800036c: 2201 movs r2, #1 800036e: f44f 6180 mov.w r1, #1024 ; 0x400 8000372: 4802 ldr r0, [pc, #8] ; (800037c ) 8000374: f7ff ff40 bl 80001f8 } 8000378: bf00 nop 800037a: bd80 pop {r7, pc} 800037c: 48000800 .word 0x48000800 08000380 : void CLK_TOGGLE(){ 8000380: b580 push {r7, lr} 8000382: af00 add r7, sp, #0 LL_GPIO_TogglePin(BUT_PORT, CLK_PIN); 8000384: f44f 6180 mov.w r1, #1024 ; 0x400 8000388: 4802 ldr r0, [pc, #8] ; (8000394 ) 800038a: f7ff ffbb bl 8000304 } 800038e: bf00 nop 8000390: bd80 pop {r7, pc} 8000392: bf00 nop 8000394: 48000800 .word 0x48000800 08000398 : void LED_GREEN( int val ) { 8000398: b580 push {r7, lr} 800039a: b082 sub sp, #8 800039c: af00 add r7, sp, #0 800039e: 6078 str r0, [r7, #4] if ( val ) 80003a0: 687b ldr r3, [r7, #4] 80003a2: 2b00 cmp r3, #0 80003a4: d005 beq.n 80003b2 LL_GPIO_SetOutputPin( LED_PORT, LED_PIN ); 80003a6: 2120 movs r1, #32 80003a8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 80003ac: f7ff ff8e bl 80002cc else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN ); } 80003b0: e004 b.n 80003bc else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN ); 80003b2: 2120 movs r1, #32 80003b4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 80003b8: f7ff ff96 bl 80002e8 } 80003bc: bf00 nop 80003be: 3708 adds r7, #8 80003c0: 46bd mov sp, r7 80003c2: bd80 pop {r7, pc} 080003c4 : int BLUE_BUTTON() { 80003c4: b580 push {r7, lr} 80003c6: af00 add r7, sp, #0 return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) ); 80003c8: f44f 5100 mov.w r1, #8192 ; 0x2000 80003cc: 4805 ldr r0, [pc, #20] ; (80003e4 ) 80003ce: f7ff ff68 bl 80002a2 80003d2: 4603 mov r3, r0 80003d4: 2b00 cmp r3, #0 80003d6: bf0c ite eq 80003d8: 2301 moveq r3, #1 80003da: 2300 movne r3, #0 80003dc: b2db uxtb r3, r3 } 80003de: 4618 mov r0, r3 80003e0: bd80 pop {r7, pc} 80003e2: bf00 nop 80003e4: 48000800 .word 0x48000800 080003e8 : * @brief Enable MSI oscillator * @rmtoll CR MSION LL_RCC_MSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_MSI_Enable(void) { 80003e8: b480 push {r7} 80003ea: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSION); 80003ec: 4b05 ldr r3, [pc, #20] ; (8000404 ) 80003ee: 681b ldr r3, [r3, #0] 80003f0: 4a04 ldr r2, [pc, #16] ; (8000404 ) 80003f2: f043 0301 orr.w r3, r3, #1 80003f6: 6013 str r3, [r2, #0] } 80003f8: bf00 nop 80003fa: 46bd mov sp, r7 80003fc: f85d 7b04 ldr.w r7, [sp], #4 8000400: 4770 bx lr 8000402: bf00 nop 8000404: 40021000 .word 0x40021000 08000408 : * @brief Check if MSI oscillator Ready * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) { 8000408: b480 push {r7} 800040a: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL); 800040c: 4b06 ldr r3, [pc, #24] ; (8000428 ) 800040e: 681b ldr r3, [r3, #0] 8000410: f003 0302 and.w r3, r3, #2 8000414: 2b02 cmp r3, #2 8000416: d101 bne.n 800041c 8000418: 2301 movs r3, #1 800041a: e000 b.n 800041e 800041c: 2300 movs r3, #0 } 800041e: 4618 mov r0, r3 8000420: 46bd mov sp, r7 8000422: f85d 7b04 ldr.w r7, [sp], #4 8000426: 4770 bx lr 8000428: 40021000 .word 0x40021000 0800042c : * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL * @retval None */ __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) { 800042c: b480 push {r7} 800042e: b083 sub sp, #12 8000430: af00 add r7, sp, #0 8000432: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 8000434: 4b06 ldr r3, [pc, #24] ; (8000450 ) 8000436: 689b ldr r3, [r3, #8] 8000438: f023 0203 bic.w r2, r3, #3 800043c: 4904 ldr r1, [pc, #16] ; (8000450 ) 800043e: 687b ldr r3, [r7, #4] 8000440: 4313 orrs r3, r2 8000442: 608b str r3, [r1, #8] } 8000444: bf00 nop 8000446: 370c adds r7, #12 8000448: 46bd mov sp, r7 800044a: f85d 7b04 ldr.w r7, [sp], #4 800044e: 4770 bx lr 8000450: 40021000 .word 0x40021000 08000454 : * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL */ __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) { 8000454: b480 push {r7} 8000456: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 8000458: 4b04 ldr r3, [pc, #16] ; (800046c ) 800045a: 689b ldr r3, [r3, #8] 800045c: f003 030c and.w r3, r3, #12 } 8000460: 4618 mov r0, r3 8000462: 46bd mov sp, r7 8000464: f85d 7b04 ldr.w r7, [sp], #4 8000468: 4770 bx lr 800046a: bf00 nop 800046c: 40021000 .word 0x40021000 08000470 : * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval None */ __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) { 8000470: b480 push {r7} 8000472: b083 sub sp, #12 8000474: af00 add r7, sp, #0 8000476: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 8000478: 4b06 ldr r3, [pc, #24] ; (8000494 ) 800047a: 689b ldr r3, [r3, #8] 800047c: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8000480: 4904 ldr r1, [pc, #16] ; (8000494 ) 8000482: 687b ldr r3, [r7, #4] 8000484: 4313 orrs r3, r2 8000486: 608b str r3, [r1, #8] } 8000488: bf00 nop 800048a: 370c adds r7, #12 800048c: 46bd mov sp, r7 800048e: f85d 7b04 ldr.w r7, [sp], #4 8000492: 4770 bx lr 8000494: 40021000 .word 0x40021000 08000498 : * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) { 8000498: b480 push {r7} 800049a: b083 sub sp, #12 800049c: af00 add r7, sp, #0 800049e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 80004a0: 4b06 ldr r3, [pc, #24] ; (80004bc ) 80004a2: 689b ldr r3, [r3, #8] 80004a4: f423 62e0 bic.w r2, r3, #1792 ; 0x700 80004a8: 4904 ldr r1, [pc, #16] ; (80004bc ) 80004aa: 687b ldr r3, [r7, #4] 80004ac: 4313 orrs r3, r2 80004ae: 608b str r3, [r1, #8] } 80004b0: bf00 nop 80004b2: 370c adds r7, #12 80004b4: 46bd mov sp, r7 80004b6: f85d 7b04 ldr.w r7, [sp], #4 80004ba: 4770 bx lr 80004bc: 40021000 .word 0x40021000 080004c0 : * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) { 80004c0: b480 push {r7} 80004c2: b083 sub sp, #12 80004c4: af00 add r7, sp, #0 80004c6: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 80004c8: 4b06 ldr r3, [pc, #24] ; (80004e4 ) 80004ca: 689b ldr r3, [r3, #8] 80004cc: f423 5260 bic.w r2, r3, #14336 ; 0x3800 80004d0: 4904 ldr r1, [pc, #16] ; (80004e4 ) 80004d2: 687b ldr r3, [r7, #4] 80004d4: 4313 orrs r3, r2 80004d6: 608b str r3, [r1, #8] } 80004d8: bf00 nop 80004da: 370c adds r7, #12 80004dc: 46bd mov sp, r7 80004de: f85d 7b04 ldr.w r7, [sp], #4 80004e2: 4770 bx lr 80004e4: 40021000 .word 0x40021000 080004e8 : * @brief Enable PLL * @rmtoll CR PLLON LL_RCC_PLL_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Enable(void) { 80004e8: b480 push {r7} 80004ea: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_PLLON); 80004ec: 4b05 ldr r3, [pc, #20] ; (8000504 ) 80004ee: 681b ldr r3, [r3, #0] 80004f0: 4a04 ldr r2, [pc, #16] ; (8000504 ) 80004f2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 80004f6: 6013 str r3, [r2, #0] } 80004f8: bf00 nop 80004fa: 46bd mov sp, r7 80004fc: f85d 7b04 ldr.w r7, [sp], #4 8000500: 4770 bx lr 8000502: bf00 nop 8000504: 40021000 .word 0x40021000 08000508 : * @brief Check if PLL Ready * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { 8000508: b480 push {r7} 800050a: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL); 800050c: 4b07 ldr r3, [pc, #28] ; (800052c ) 800050e: 681b ldr r3, [r3, #0] 8000510: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000514: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8000518: d101 bne.n 800051e 800051a: 2301 movs r3, #1 800051c: e000 b.n 8000520 800051e: 2300 movs r3, #0 } 8000520: 4618 mov r0, r3 8000522: 46bd mov sp, r7 8000524: f85d 7b04 ldr.w r7, [sp], #4 8000528: 4770 bx lr 800052a: bf00 nop 800052c: 40021000 .word 0x40021000 08000530 : * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_8 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) { 8000530: b480 push {r7} 8000532: b085 sub sp, #20 8000534: af00 add r7, sp, #0 8000536: 60f8 str r0, [r7, #12] 8000538: 60b9 str r1, [r7, #8] 800053a: 607a str r2, [r7, #4] 800053c: 603b str r3, [r7, #0] MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 800053e: 4b0a ldr r3, [pc, #40] ; (8000568 ) 8000540: 68da ldr r2, [r3, #12] 8000542: 4b0a ldr r3, [pc, #40] ; (800056c ) 8000544: 4013 ands r3, r2 8000546: 68f9 ldr r1, [r7, #12] 8000548: 68ba ldr r2, [r7, #8] 800054a: 4311 orrs r1, r2 800054c: 687a ldr r2, [r7, #4] 800054e: 0212 lsls r2, r2, #8 8000550: 4311 orrs r1, r2 8000552: 683a ldr r2, [r7, #0] 8000554: 430a orrs r2, r1 8000556: 4904 ldr r1, [pc, #16] ; (8000568 ) 8000558: 4313 orrs r3, r2 800055a: 60cb str r3, [r1, #12] Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); } 800055c: bf00 nop 800055e: 3714 adds r7, #20 8000560: 46bd mov sp, r7 8000562: f85d 7b04 ldr.w r7, [sp], #4 8000566: 4770 bx lr 8000568: 40021000 .word 0x40021000 800056c: f9ff808c .word 0xf9ff808c 08000570 : * @brief Enable PLL output mapped on SYSCLK domain * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS * @retval None */ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) { 8000570: b480 push {r7} 8000572: af00 add r7, sp, #0 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); 8000574: 4b05 ldr r3, [pc, #20] ; (800058c ) 8000576: 68db ldr r3, [r3, #12] 8000578: 4a04 ldr r2, [pc, #16] ; (800058c ) 800057a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 800057e: 60d3 str r3, [r2, #12] } 8000580: bf00 nop 8000582: 46bd mov sp, r7 8000584: f85d 7b04 ldr.w r7, [sp], #4 8000588: 4770 bx lr 800058a: bf00 nop 800058c: 40021000 .word 0x40021000 08000590 : * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) { 8000590: b480 push {r7} 8000592: b083 sub sp, #12 8000594: af00 add r7, sp, #0 8000596: 6078 str r0, [r7, #4] MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 8000598: 4b06 ldr r3, [pc, #24] ; (80005b4 ) 800059a: 681b ldr r3, [r3, #0] 800059c: f023 0207 bic.w r2, r3, #7 80005a0: 4904 ldr r1, [pc, #16] ; (80005b4 ) 80005a2: 687b ldr r3, [r7, #4] 80005a4: 4313 orrs r3, r2 80005a6: 600b str r3, [r1, #0] } 80005a8: bf00 nop 80005aa: 370c adds r7, #12 80005ac: 46bd mov sp, r7 80005ae: f85d 7b04 ldr.w r7, [sp], #4 80005b2: 4770 bx lr 80005b4: 40022000 .word 0x40022000 080005b8 : * @brief Enable SysTick exception request * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT * @retval None */ __STATIC_INLINE void LL_SYSTICK_EnableIT(void) { 80005b8: b480 push {r7} 80005ba: af00 add r7, sp, #0 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 80005bc: 4b05 ldr r3, [pc, #20] ; (80005d4 ) 80005be: 681b ldr r3, [r3, #0] 80005c0: 4a04 ldr r2, [pc, #16] ; (80005d4 ) 80005c2: f043 0302 orr.w r3, r3, #2 80005c6: 6013 str r3, [r2, #0] } 80005c8: bf00 nop 80005ca: 46bd mov sp, r7 80005cc: f85d 7b04 ldr.w r7, [sp], #4 80005d0: 4770 bx lr 80005d2: bf00 nop 80005d4: e000e010 .word 0xe000e010 080005d8 : * @brief Processor uses sleep as its low power mode * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep * @retval None */ __STATIC_INLINE void LL_LPM_EnableSleep(void) { 80005d8: b480 push {r7} 80005da: af00 add r7, sp, #0 /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 80005dc: 4b05 ldr r3, [pc, #20] ; (80005f4 ) 80005de: 691b ldr r3, [r3, #16] 80005e0: 4a04 ldr r2, [pc, #16] ; (80005f4 ) 80005e2: f023 0304 bic.w r3, r3, #4 80005e6: 6113 str r3, [r2, #16] } 80005e8: bf00 nop 80005ea: 46bd mov sp, r7 80005ec: f85d 7b04 ldr.w r7, [sp], #4 80005f0: 4770 bx lr 80005f2: bf00 nop 80005f4: e000ed00 .word 0xe000ed00 080005f8 : volatile uint32_t msTicks = 0; volatile uint8_t expe = 0; volatile uint8_t blue_mode = 0; void SysTick_Handler() { 80005f8: b580 push {r7, lr} 80005fa: af00 add r7, sp, #0 if ( BLUE_BUTTON() ){ 80005fc: f7ff fee2 bl 80003c4 8000600: 4603 mov r3, r0 8000602: 2b00 cmp r3, #0 8000604: d002 beq.n 800060c blue_mode = 1 ; 8000606: 4b0f ldr r3, [pc, #60] ; (8000644 ) 8000608: 2201 movs r2, #1 800060a: 701a strb r2, [r3, #0] } msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */ 800060c: 4b0e ldr r3, [pc, #56] ; (8000648 ) 800060e: 681b ldr r3, [r3, #0] 8000610: 3301 adds r3, #1 8000612: 4a0d ldr r2, [pc, #52] ; (8000648 ) 8000614: 6013 str r3, [r2, #0] if (msTicks == 5){ 8000616: 4b0c ldr r3, [pc, #48] ; (8000648 ) 8000618: 681b ldr r3, [r3, #0] 800061a: 2b05 cmp r3, #5 800061c: d103 bne.n 8000626 LED_GREEN(0); 800061e: 2000 movs r0, #0 8000620: f7ff feba bl 8000398 8000624: e009 b.n 800063a }else if(msTicks >= 200){ 8000626: 4b08 ldr r3, [pc, #32] ; (8000648 ) 8000628: 681b ldr r3, [r3, #0] 800062a: 2bc7 cmp r3, #199 ; 0xc7 800062c: d905 bls.n 800063a msTicks = 0; 800062e: 4b06 ldr r3, [pc, #24] ; (8000648 ) 8000630: 2200 movs r2, #0 8000632: 601a str r2, [r3, #0] LED_GREEN(1); 8000634: 2001 movs r0, #1 8000636: f7ff feaf bl 8000398 } CLK_TOGGLE(); 800063a: f7ff fea1 bl 8000380 } 800063e: bf00 nop 8000640: bd80 pop {r7, pc} 8000642: bf00 nop 8000644: 20000024 .word 0x20000024 8000648: 20000020 .word 0x20000020 0800064c
: // //void SystemClock_Config(void); int main(void) { 800064c: b580 push {r7, lr} 800064e: af00 add r7, sp, #0 /* Configure the system clock */ SystemClock_Config(); 8000650: f000 f816 bl 8000680 // config GPIO GPIO_init(); 8000654: f7ff fe70 bl 8000338 // init systick timer (tick period at 1 ms) LL_Init1msTick( SystemCoreClock ); 8000658: 4b07 ldr r3, [pc, #28] ; (8000678 ) 800065a: 681b ldr r3, [r3, #0] 800065c: 4618 mov r0, r3 800065e: f000 f99f bl 80009a0 LL_SYSTICK_EnableIT(); 8000662: f7ff ffa9 bl 80005b8 //Setup Sleep mode LL_LPM_EnableSleep(); 8000666: f7ff ffb7 bl 80005d8 //LL_LPM_EnableSleepOnExit(); while (1) { if (blue_mode){ 800066a: 4b04 ldr r3, [pc, #16] ; (800067c ) 800066c: 781b ldrb r3, [r3, #0] 800066e: b2db uxtb r3, r3 8000670: 2b00 cmp r3, #0 8000672: d0fa beq.n 800066a __WFI(); 8000674: bf30 wfi if (blue_mode){ 8000676: e7f8 b.n 800066a 8000678: 20000000 .word 0x20000000 800067c: 20000024 .word 0x20000024 08000680 : * PLL_R = 2 * Flash Latency(WS) = 4 * @param None * @retval None */ void SystemClock_Config(void) { 8000680: b580 push {r7, lr} 8000682: af00 add r7, sp, #0 /* MSI configuration and activation */ LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); 8000684: 2004 movs r0, #4 8000686: f7ff ff83 bl 8000590 LL_RCC_MSI_Enable(); 800068a: f7ff fead bl 80003e8 while (LL_RCC_MSI_IsReady() != 1) 800068e: bf00 nop 8000690: f7ff feba bl 8000408 8000694: 4603 mov r3, r0 8000696: 2b01 cmp r3, #1 8000698: d1fa bne.n 8000690 { }; /* Main PLL configuration and activation */ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2); 800069a: 2300 movs r3, #0 800069c: 2228 movs r2, #40 ; 0x28 800069e: 2100 movs r1, #0 80006a0: 2001 movs r0, #1 80006a2: f7ff ff45 bl 8000530 LL_RCC_PLL_Enable(); 80006a6: f7ff ff1f bl 80004e8 LL_RCC_PLL_EnableDomain_SYS(); 80006aa: f7ff ff61 bl 8000570 while(LL_RCC_PLL_IsReady() != 1) 80006ae: bf00 nop 80006b0: f7ff ff2a bl 8000508 80006b4: 4603 mov r3, r0 80006b6: 2b01 cmp r3, #1 80006b8: d1fa bne.n 80006b0 { }; /* Sysclk activation on the main PLL */ LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); 80006ba: 2000 movs r0, #0 80006bc: f7ff fed8 bl 8000470 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); 80006c0: 2003 movs r0, #3 80006c2: f7ff feb3 bl 800042c while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) 80006c6: bf00 nop 80006c8: f7ff fec4 bl 8000454 80006cc: 4603 mov r3, r0 80006ce: 2b0c cmp r3, #12 80006d0: d1fa bne.n 80006c8 { }; /* Set APB1 & APB2 prescaler*/ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); 80006d2: 2000 movs r0, #0 80006d4: f7ff fee0 bl 8000498 LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); 80006d8: 2000 movs r0, #0 80006da: f7ff fef1 bl 80004c0 /* Update the global variable called SystemCoreClock */ SystemCoreClockUpdate(); 80006de: f000 f861 bl 80007a4 } 80006e2: bf00 nop 80006e4: bd80 pop {r7, pc} 080006e6 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80006e6: b480 push {r7} 80006e8: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 80006ea: bf00 nop 80006ec: 46bd mov sp, r7 80006ee: f85d 7b04 ldr.w r7, [sp], #4 80006f2: 4770 bx lr 080006f4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80006f4: b480 push {r7} 80006f6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80006f8: e7fe b.n 80006f8 080006fa : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80006fa: b480 push {r7} 80006fc: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80006fe: e7fe b.n 80006fe 08000700 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8000700: b480 push {r7} 8000702: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000704: e7fe b.n 8000704 08000706 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000706: b480 push {r7} 8000708: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800070a: e7fe b.n 800070a 0800070c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800070c: b480 push {r7} 800070e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000710: bf00 nop 8000712: 46bd mov sp, r7 8000714: f85d 7b04 ldr.w r7, [sp], #4 8000718: 4770 bx lr 0800071a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800071a: b480 push {r7} 800071c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800071e: bf00 nop 8000720: 46bd mov sp, r7 8000722: f85d 7b04 ldr.w r7, [sp], #4 8000726: 4770 bx lr 08000728 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000728: b480 push {r7} 800072a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800072c: bf00 nop 800072e: 46bd mov sp, r7 8000730: f85d 7b04 ldr.w r7, [sp], #4 8000734: 4770 bx lr ... 08000738 : * @param None * @retval None */ void SystemInit(void) { 8000738: b480 push {r7} 800073a: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 800073c: 4b17 ldr r3, [pc, #92] ; (800079c ) 800073e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8000742: 4a16 ldr r2, [pc, #88] ; (800079c ) 8000744: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8000748: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ RCC->CR |= RCC_CR_MSION; 800074c: 4b14 ldr r3, [pc, #80] ; (80007a0 ) 800074e: 681b ldr r3, [r3, #0] 8000750: 4a13 ldr r2, [pc, #76] ; (80007a0 ) 8000752: f043 0301 orr.w r3, r3, #1 8000756: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000U; 8000758: 4b11 ldr r3, [pc, #68] ; (80007a0 ) 800075a: 2200 movs r2, #0 800075c: 609a str r2, [r3, #8] /* Reset HSEON, CSSON , HSION, and PLLON bits */ RCC->CR &= 0xEAF6FFFFU; 800075e: 4b10 ldr r3, [pc, #64] ; (80007a0 ) 8000760: 681b ldr r3, [r3, #0] 8000762: 4a0f ldr r2, [pc, #60] ; (80007a0 ) 8000764: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000 8000768: f423 2310 bic.w r3, r3, #589824 ; 0x90000 800076c: 6013 str r3, [r2, #0] /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x00001000U; 800076e: 4b0c ldr r3, [pc, #48] ; (80007a0 ) 8000770: f44f 5280 mov.w r2, #4096 ; 0x1000 8000774: 60da str r2, [r3, #12] /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8000776: 4b0a ldr r3, [pc, #40] ; (80007a0 ) 8000778: 681b ldr r3, [r3, #0] 800077a: 4a09 ldr r2, [pc, #36] ; (80007a0 ) 800077c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000780: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000U; 8000782: 4b07 ldr r3, [pc, #28] ; (80007a0 ) 8000784: 2200 movs r2, #0 8000786: 619a str r2, [r3, #24] /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 8000788: 4b04 ldr r3, [pc, #16] ; (800079c ) 800078a: f04f 6200 mov.w r2, #134217728 ; 0x8000000 800078e: 609a str r2, [r3, #8] #endif } 8000790: bf00 nop 8000792: 46bd mov sp, r7 8000794: f85d 7b04 ldr.w r7, [sp], #4 8000798: 4770 bx lr 800079a: bf00 nop 800079c: e000ed00 .word 0xe000ed00 80007a0: 40021000 .word 0x40021000 080007a4 : * * @param None * @retval None */ void SystemCoreClockUpdate(void) { 80007a4: b480 push {r7} 80007a6: b087 sub sp, #28 80007a8: af00 add r7, sp, #0 uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; 80007aa: 2300 movs r3, #0 80007ac: 60fb str r3, [r7, #12] 80007ae: 2300 movs r3, #0 80007b0: 617b str r3, [r7, #20] 80007b2: 2300 movs r3, #0 80007b4: 613b str r3, [r7, #16] 80007b6: 2302 movs r3, #2 80007b8: 60bb str r3, [r7, #8] 80007ba: 2300 movs r3, #0 80007bc: 607b str r3, [r7, #4] 80007be: 2302 movs r3, #2 80007c0: 603b str r3, [r7, #0] /* Get MSI Range frequency--------------------------------------------------*/ if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) 80007c2: 4b4f ldr r3, [pc, #316] ; (8000900 ) 80007c4: 681b ldr r3, [r3, #0] 80007c6: f003 0308 and.w r3, r3, #8 80007ca: 2b00 cmp r3, #0 80007cc: d107 bne.n 80007de { /* MSISRANGE from RCC_CSR applies */ msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; 80007ce: 4b4c ldr r3, [pc, #304] ; (8000900 ) 80007d0: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 80007d4: 0a1b lsrs r3, r3, #8 80007d6: f003 030f and.w r3, r3, #15 80007da: 617b str r3, [r7, #20] 80007dc: e005 b.n 80007ea } else { /* MSIRANGE from RCC_CR applies */ msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; 80007de: 4b48 ldr r3, [pc, #288] ; (8000900 ) 80007e0: 681b ldr r3, [r3, #0] 80007e2: 091b lsrs r3, r3, #4 80007e4: f003 030f and.w r3, r3, #15 80007e8: 617b str r3, [r7, #20] } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; 80007ea: 4a46 ldr r2, [pc, #280] ; (8000904 ) 80007ec: 697b ldr r3, [r7, #20] 80007ee: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80007f2: 617b str r3, [r7, #20] /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 80007f4: 4b42 ldr r3, [pc, #264] ; (8000900 ) 80007f6: 689b ldr r3, [r3, #8] 80007f8: f003 030c and.w r3, r3, #12 80007fc: 2b0c cmp r3, #12 80007fe: d865 bhi.n 80008cc 8000800: a201 add r2, pc, #4 ; (adr r2, 8000808 ) 8000802: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000806: bf00 nop 8000808: 0800083d .word 0x0800083d 800080c: 080008cd .word 0x080008cd 8000810: 080008cd .word 0x080008cd 8000814: 080008cd .word 0x080008cd 8000818: 08000845 .word 0x08000845 800081c: 080008cd .word 0x080008cd 8000820: 080008cd .word 0x080008cd 8000824: 080008cd .word 0x080008cd 8000828: 0800084d .word 0x0800084d 800082c: 080008cd .word 0x080008cd 8000830: 080008cd .word 0x080008cd 8000834: 080008cd .word 0x080008cd 8000838: 08000855 .word 0x08000855 { case 0x00: /* MSI used as system clock source */ SystemCoreClock = msirange; 800083c: 4a32 ldr r2, [pc, #200] ; (8000908 ) 800083e: 697b ldr r3, [r7, #20] 8000840: 6013 str r3, [r2, #0] break; 8000842: e047 b.n 80008d4 case 0x04: /* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; 8000844: 4b30 ldr r3, [pc, #192] ; (8000908 ) 8000846: 4a31 ldr r2, [pc, #196] ; (800090c ) 8000848: 601a str r2, [r3, #0] break; 800084a: e043 b.n 80008d4 case 0x08: /* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; 800084c: 4b2e ldr r3, [pc, #184] ; (8000908 ) 800084e: 4a30 ldr r2, [pc, #192] ; (8000910 ) 8000850: 601a str r2, [r3, #0] break; 8000852: e03f b.n 80008d4 case 0x0C: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 8000854: 4b2a ldr r3, [pc, #168] ; (8000900 ) 8000856: 68db ldr r3, [r3, #12] 8000858: f003 0303 and.w r3, r3, #3 800085c: 607b str r3, [r7, #4] pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; 800085e: 4b28 ldr r3, [pc, #160] ; (8000900 ) 8000860: 68db ldr r3, [r3, #12] 8000862: 091b lsrs r3, r3, #4 8000864: f003 0307 and.w r3, r3, #7 8000868: 3301 adds r3, #1 800086a: 603b str r3, [r7, #0] switch (pllsource) 800086c: 687b ldr r3, [r7, #4] 800086e: 2b02 cmp r3, #2 8000870: d002 beq.n 8000878 8000872: 2b03 cmp r3, #3 8000874: d006 beq.n 8000884 8000876: e00b b.n 8000890 { case 0x02: /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm); 8000878: 4a24 ldr r2, [pc, #144] ; (800090c ) 800087a: 683b ldr r3, [r7, #0] 800087c: fbb2 f3f3 udiv r3, r2, r3 8000880: 613b str r3, [r7, #16] break; 8000882: e00b b.n 800089c case 0x03: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm); 8000884: 4a22 ldr r2, [pc, #136] ; (8000910 ) 8000886: 683b ldr r3, [r7, #0] 8000888: fbb2 f3f3 udiv r3, r2, r3 800088c: 613b str r3, [r7, #16] break; 800088e: e005 b.n 800089c default: /* MSI used as PLL clock source */ pllvco = (msirange / pllm); 8000890: 697a ldr r2, [r7, #20] 8000892: 683b ldr r3, [r7, #0] 8000894: fbb2 f3f3 udiv r3, r2, r3 8000898: 613b str r3, [r7, #16] break; 800089a: bf00 nop } pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); 800089c: 4b18 ldr r3, [pc, #96] ; (8000900 ) 800089e: 68db ldr r3, [r3, #12] 80008a0: 0a1b lsrs r3, r3, #8 80008a2: f003 027f and.w r2, r3, #127 ; 0x7f 80008a6: 693b ldr r3, [r7, #16] 80008a8: fb02 f303 mul.w r3, r2, r3 80008ac: 613b str r3, [r7, #16] pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; 80008ae: 4b14 ldr r3, [pc, #80] ; (8000900 ) 80008b0: 68db ldr r3, [r3, #12] 80008b2: 0e5b lsrs r3, r3, #25 80008b4: f003 0303 and.w r3, r3, #3 80008b8: 3301 adds r3, #1 80008ba: 005b lsls r3, r3, #1 80008bc: 60bb str r3, [r7, #8] SystemCoreClock = pllvco/pllr; 80008be: 693a ldr r2, [r7, #16] 80008c0: 68bb ldr r3, [r7, #8] 80008c2: fbb2 f3f3 udiv r3, r2, r3 80008c6: 4a10 ldr r2, [pc, #64] ; (8000908 ) 80008c8: 6013 str r3, [r2, #0] break; 80008ca: e003 b.n 80008d4 default: SystemCoreClock = msirange; 80008cc: 4a0e ldr r2, [pc, #56] ; (8000908 ) 80008ce: 697b ldr r3, [r7, #20] 80008d0: 6013 str r3, [r2, #0] break; 80008d2: bf00 nop } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; 80008d4: 4b0a ldr r3, [pc, #40] ; (8000900 ) 80008d6: 689b ldr r3, [r3, #8] 80008d8: 091b lsrs r3, r3, #4 80008da: f003 030f and.w r3, r3, #15 80008de: 4a0d ldr r2, [pc, #52] ; (8000914 ) 80008e0: 5cd3 ldrb r3, [r2, r3] 80008e2: 60fb str r3, [r7, #12] /* HCLK clock frequency */ SystemCoreClock >>= tmp; 80008e4: 4b08 ldr r3, [pc, #32] ; (8000908 ) 80008e6: 681a ldr r2, [r3, #0] 80008e8: 68fb ldr r3, [r7, #12] 80008ea: fa22 f303 lsr.w r3, r2, r3 80008ee: 4a06 ldr r2, [pc, #24] ; (8000908 ) 80008f0: 6013 str r3, [r2, #0] } 80008f2: bf00 nop 80008f4: 371c adds r7, #28 80008f6: 46bd mov sp, r7 80008f8: f85d 7b04 ldr.w r7, [sp], #4 80008fc: 4770 bx lr 80008fe: bf00 nop 8000900: 40021000 .word 0x40021000 8000904: 08000a28 .word 0x08000a28 8000908: 20000000 .word 0x20000000 800090c: 00f42400 .word 0x00f42400 8000910: 007a1200 .word 0x007a1200 8000914: 08000a18 .word 0x08000a18 08000918 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Set stack pointer */ 8000918: f8df d034 ldr.w sp, [pc, #52] ; 8000950 /* Call the clock system initialization function.*/ bl SystemInit 800091c: f7ff ff0c bl 8000738 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8000920: 2100 movs r1, #0 b LoopCopyDataInit 8000922: e003 b.n 800092c 08000924 : CopyDataInit: ldr r3, =_sidata 8000924: 4b0b ldr r3, [pc, #44] ; (8000954 ) ldr r3, [r3, r1] 8000926: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8000928: 5043 str r3, [r0, r1] adds r1, r1, #4 800092a: 3104 adds r1, #4 0800092c : LoopCopyDataInit: ldr r0, =_sdata 800092c: 480a ldr r0, [pc, #40] ; (8000958 ) ldr r3, =_edata 800092e: 4b0b ldr r3, [pc, #44] ; (800095c ) adds r2, r0, r1 8000930: 1842 adds r2, r0, r1 cmp r2, r3 8000932: 429a cmp r2, r3 bcc CopyDataInit 8000934: d3f6 bcc.n 8000924 ldr r2, =_sbss 8000936: 4a0a ldr r2, [pc, #40] ; (8000960 ) b LoopFillZerobss 8000938: e002 b.n 8000940 0800093a : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 800093a: 2300 movs r3, #0 str r3, [r2], #4 800093c: f842 3b04 str.w r3, [r2], #4 08000940 : LoopFillZerobss: ldr r3, = _ebss 8000940: 4b08 ldr r3, [pc, #32] ; (8000964 ) cmp r2, r3 8000942: 429a cmp r2, r3 bcc FillZerobss 8000944: d3f9 bcc.n 800093a /* Call static constructors */ bl __libc_init_array 8000946: f000 f837 bl 80009b8 <__libc_init_array> /* Call the application's entry point.*/ bl main 800094a: f7ff fe7f bl 800064c
0800094e : LoopForever: b LoopForever 800094e: e7fe b.n 800094e ldr sp, =_estack /* Set stack pointer */ 8000950: 20018000 .word 0x20018000 ldr r3, =_sidata 8000954: 08000a60 .word 0x08000a60 ldr r0, =_sdata 8000958: 20000000 .word 0x20000000 ldr r3, =_edata 800095c: 20000004 .word 0x20000004 ldr r2, =_sbss 8000960: 20000004 .word 0x20000004 ldr r3, = _ebss 8000964: 20000028 .word 0x20000028 08000968 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000968: e7fe b.n 8000968 ... 0800096c : * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param Ticks Number of ticks * @retval None */ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) { 800096c: b480 push {r7} 800096e: b083 sub sp, #12 8000970: af00 add r7, sp, #0 8000972: 6078 str r0, [r7, #4] 8000974: 6039 str r1, [r7, #0] /* Configure the SysTick to have interrupt in 1ms time base */ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ 8000976: 687a ldr r2, [r7, #4] 8000978: 683b ldr r3, [r7, #0] 800097a: fbb2 f3f3 udiv r3, r2, r3 800097e: 4a07 ldr r2, [pc, #28] ; (800099c ) 8000980: 3b01 subs r3, #1 8000982: 6053 str r3, [r2, #4] SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000984: 4b05 ldr r3, [pc, #20] ; (800099c ) 8000986: 2200 movs r2, #0 8000988: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800098a: 4b04 ldr r3, [pc, #16] ; (800099c ) 800098c: 2205 movs r2, #5 800098e: 601a str r2, [r3, #0] SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ } 8000990: bf00 nop 8000992: 370c adds r7, #12 8000994: 46bd mov sp, r7 8000996: f85d 7b04 ldr.w r7, [sp], #4 800099a: 4770 bx lr 800099c: e000e010 .word 0xe000e010 080009a0 : * @param HCLKFrequency HCLK frequency in Hz * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq * @retval None */ void LL_Init1msTick(uint32_t HCLKFrequency) { 80009a0: b580 push {r7, lr} 80009a2: b082 sub sp, #8 80009a4: af00 add r7, sp, #0 80009a6: 6078 str r0, [r7, #4] /* Use frequency provided in argument */ LL_InitTick(HCLKFrequency, 100U); 80009a8: 2164 movs r1, #100 ; 0x64 80009aa: 6878 ldr r0, [r7, #4] 80009ac: f7ff ffde bl 800096c } 80009b0: bf00 nop 80009b2: 3708 adds r7, #8 80009b4: 46bd mov sp, r7 80009b6: bd80 pop {r7, pc} 080009b8 <__libc_init_array>: 80009b8: b570 push {r4, r5, r6, lr} 80009ba: 4e0d ldr r6, [pc, #52] ; (80009f0 <__libc_init_array+0x38>) 80009bc: 4c0d ldr r4, [pc, #52] ; (80009f4 <__libc_init_array+0x3c>) 80009be: 1ba4 subs r4, r4, r6 80009c0: 10a4 asrs r4, r4, #2 80009c2: 2500 movs r5, #0 80009c4: 42a5 cmp r5, r4 80009c6: d109 bne.n 80009dc <__libc_init_array+0x24> 80009c8: 4e0b ldr r6, [pc, #44] ; (80009f8 <__libc_init_array+0x40>) 80009ca: 4c0c ldr r4, [pc, #48] ; (80009fc <__libc_init_array+0x44>) 80009cc: f000 f818 bl 8000a00 <_init> 80009d0: 1ba4 subs r4, r4, r6 80009d2: 10a4 asrs r4, r4, #2 80009d4: 2500 movs r5, #0 80009d6: 42a5 cmp r5, r4 80009d8: d105 bne.n 80009e6 <__libc_init_array+0x2e> 80009da: bd70 pop {r4, r5, r6, pc} 80009dc: f856 3025 ldr.w r3, [r6, r5, lsl #2] 80009e0: 4798 blx r3 80009e2: 3501 adds r5, #1 80009e4: e7ee b.n 80009c4 <__libc_init_array+0xc> 80009e6: f856 3025 ldr.w r3, [r6, r5, lsl #2] 80009ea: 4798 blx r3 80009ec: 3501 adds r5, #1 80009ee: e7f2 b.n 80009d6 <__libc_init_array+0x1e> 80009f0: 08000a58 .word 0x08000a58 80009f4: 08000a58 .word 0x08000a58 80009f8: 08000a58 .word 0x08000a58 80009fc: 08000a5c .word 0x08000a5c 08000a00 <_init>: 8000a00: b5f8 push {r3, r4, r5, r6, r7, lr} 8000a02: bf00 nop 8000a04: bcf8 pop {r3, r4, r5, r6, r7} 8000a06: bc08 pop {r3} 8000a08: 469e mov lr, r3 8000a0a: 4770 bx lr 08000a0c <_fini>: 8000a0c: b5f8 push {r3, r4, r5, r6, r7, lr} 8000a0e: bf00 nop 8000a10: bcf8 pop {r3, r4, r5, r6, r7} 8000a12: bc08 pop {r3} 8000a14: 469e mov lr, r3 8000a16: 4770 bx lr