diff --git a/.gitignore b/.gitignore
index e2dd02c..b6ff256 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,3 @@
-/.metadata/
-Debug
+/.metadata/
+Debug
Release
\ No newline at end of file
diff --git a/L476_ats_blink-master/.cproject b/L476_ats_blink-master/.cproject
index fa99011..86c8c82 100644
--- a/L476_ats_blink-master/.cproject
+++ b/L476_ats_blink-master/.cproject
@@ -1,181 +1,181 @@
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diff --git a/L476_ats_blink-master/.mxproject b/L476_ats_blink-master/.mxproject
index b0adf27..8df0b92 100644
--- a/L476_ats_blink-master/.mxproject
+++ b/L476_ats_blink-master/.mxproject
@@ -1,26 +1,26 @@
-[PreviousLibFiles]
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.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
-
-[PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;Core\Src\stm32l4xx_it.c;Core\Src\stm32l4xx_hal_msp.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Core\Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Core\Src/system_stm32l4xx.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;;
-HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32L4xx\Include;Drivers\CMSIS\Include;Core\Inc;
-CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32L476xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
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-HeaderFileListSize=4
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-HeaderFiles#1=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/stm32_assert.h
-HeaderFiles#2=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/stm32l4xx_hal_conf.h
-HeaderFiles#3=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/main.h
-HeaderFolderListSize=1
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-HeaderFiles=;
-SourceFileListSize=3
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-SourceFiles#1=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src/stm32l4xx_hal_msp.c
-SourceFiles#2=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src/main.c
-SourceFolderListSize=1
-SourcePath#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src
-SourceFiles=;
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+[PreviousLibFiles]
+LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core\Src\main.c;Core\Src\stm32l4xx_it.c;Core\Src\stm32l4xx_hal_msp.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Core\Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Core\Src/system_stm32l4xx.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;;
+HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32L4xx\Include;Drivers\CMSIS\Include;Core\Inc;
+CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32L476xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=4
+HeaderFiles#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/stm32l4xx_it.h
+HeaderFiles#1=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/stm32_assert.h
+HeaderFiles#2=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/stm32l4xx_hal_conf.h
+HeaderFiles#3=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/main.h
+HeaderFolderListSize=1
+HeaderPath#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src/stm32l4xx_it.c
+SourceFiles#1=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src/stm32l4xx_hal_msp.c
+SourceFiles#2=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src/main.c
+SourceFolderListSize=1
+SourcePath#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src
+SourceFiles=;
+
diff --git a/L476_ats_blink-master/Core/Inc/main.h b/L476_ats_blink-master/Core/Inc/main.h
index 460e791..ea61c70 100644
--- a/L476_ats_blink-master/Core/Inc/main.h
+++ b/L476_ats_blink-master/Core/Inc/main.h
@@ -1,81 +1,81 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file : main.h
- * @brief : Header for main.c file.
- * This file contains the common defines of the application.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved. :
- 80001ac: b508 push {r3, lr}
- 80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc )
- 80001b0: b11b cbz r3, 80001ba
- 80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 )
- 80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 )
- 80001b6: f3af 8000 nop.w
- 80001ba: bd08 pop {r3, pc}
- 80001bc: 00000000 .word 0x00000000
- 80001c0: 20000008 .word 0x20000008
- 80001c4: 080009a4 .word 0x080009a4
-
-080001c8 :
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
-{
- 80001c8: b480 push {r7}
- 80001ca: b085 sub sp, #20
- 80001cc: af00 add r7, sp, #0
- 80001ce: 6078 str r0, [r7, #4]
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB2ENR, Periphs);
- 80001d0: 4b08 ldr r3, [pc, #32] ; (80001f4 )
- 80001d2: 6cda ldr r2, [r3, #76] ; 0x4c
- 80001d4: 4907 ldr r1, [pc, #28] ; (80001f4 )
- 80001d6: 687b ldr r3, [r7, #4]
- 80001d8: 4313 orrs r3, r2
- 80001da: 64cb str r3, [r1, #76] ; 0x4c
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
- 80001dc: 4b05 ldr r3, [pc, #20] ; (80001f4 )
- 80001de: 6cda ldr r2, [r3, #76] ; 0x4c
- 80001e0: 687b ldr r3, [r7, #4]
- 80001e2: 4013 ands r3, r2
- 80001e4: 60fb str r3, [r7, #12]
- (void)tmpreg;
- 80001e6: 68fb ldr r3, [r7, #12]
-}
- 80001e8: bf00 nop
- 80001ea: 3714 adds r7, #20
- 80001ec: 46bd mov sp, r7
- 80001ee: f85d 7b04 ldr.w r7, [sp], #4
- 80001f2: 4770 bx lr
- 80001f4: 40021000 .word 0x40021000
-
-080001f8 :
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @arg @ref LL_GPIO_MODE_ANALOG
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
- 80001f8: b480 push {r7}
- 80001fa: b08b sub sp, #44 ; 0x2c
- 80001fc: af00 add r7, sp, #0
- 80001fe: 60f8 str r0, [r7, #12]
- 8000200: 60b9 str r1, [r7, #8]
- 8000202: 607a str r2, [r7, #4]
- MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
- 8000204: 68fb ldr r3, [r7, #12]
- 8000206: 681a ldr r2, [r3, #0]
- 8000208: 68bb ldr r3, [r7, #8]
- 800020a: 617b str r3, [r7, #20]
- uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- 800020c: 697b ldr r3, [r7, #20]
- 800020e: fa93 f3a3 rbit r3, r3
- 8000212: 613b str r3, [r7, #16]
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
-#endif
- return result;
- 8000214: 693b ldr r3, [r7, #16]
- 8000216: 61bb str r3, [r7, #24]
- optimisations using the logic "value was passed to __builtin_clz, so it
- is non-zero".
- ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
- single CLZ instruction.
- */
- if (value == 0U)
- 8000218: 69bb ldr r3, [r7, #24]
- 800021a: 2b00 cmp r3, #0
- 800021c: d101 bne.n 8000222
- {
- return 32U;
- 800021e: 2320 movs r3, #32
- 8000220: e003 b.n 800022a
- }
- return __builtin_clz(value);
- 8000222: 69bb ldr r3, [r7, #24]
- 8000224: fab3 f383 clz r3, r3
- 8000228: b2db uxtb r3, r3
- 800022a: 005b lsls r3, r3, #1
- 800022c: 2103 movs r1, #3
- 800022e: fa01 f303 lsl.w r3, r1, r3
- 8000232: 43db mvns r3, r3
- 8000234: 401a ands r2, r3
- 8000236: 68bb ldr r3, [r7, #8]
- 8000238: 623b str r3, [r7, #32]
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- 800023a: 6a3b ldr r3, [r7, #32]
- 800023c: fa93 f3a3 rbit r3, r3
- 8000240: 61fb str r3, [r7, #28]
- return result;
- 8000242: 69fb ldr r3, [r7, #28]
- 8000244: 627b str r3, [r7, #36] ; 0x24
- if (value == 0U)
- 8000246: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000248: 2b00 cmp r3, #0
- 800024a: d101 bne.n 8000250
- return 32U;
- 800024c: 2320 movs r3, #32
- 800024e: e003 b.n 8000258
- return __builtin_clz(value);
- 8000250: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000252: fab3 f383 clz r3, r3
- 8000256: b2db uxtb r3, r3
- 8000258: 005b lsls r3, r3, #1
- 800025a: 6879 ldr r1, [r7, #4]
- 800025c: fa01 f303 lsl.w r3, r1, r3
- 8000260: 431a orrs r2, r3
- 8000262: 68fb ldr r3, [r7, #12]
- 8000264: 601a str r2, [r3, #0]
-}
- 8000266: bf00 nop
- 8000268: 372c adds r7, #44 ; 0x2c
- 800026a: 46bd mov sp, r7
- 800026c: f85d 7b04 ldr.w r7, [sp], #4
- 8000270: 4770 bx lr
-
-08000272 :
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
-{
- 8000272: b480 push {r7}
- 8000274: b085 sub sp, #20
- 8000276: af00 add r7, sp, #0
- 8000278: 60f8 str r0, [r7, #12]
- 800027a: 60b9 str r1, [r7, #8]
- 800027c: 607a str r2, [r7, #4]
- MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
- 800027e: 68fb ldr r3, [r7, #12]
- 8000280: 685a ldr r2, [r3, #4]
- 8000282: 68bb ldr r3, [r7, #8]
- 8000284: 43db mvns r3, r3
- 8000286: 401a ands r2, r3
- 8000288: 68bb ldr r3, [r7, #8]
- 800028a: 6879 ldr r1, [r7, #4]
- 800028c: fb01 f303 mul.w r3, r1, r3
- 8000290: 431a orrs r2, r3
- 8000292: 68fb ldr r3, [r7, #12]
- 8000294: 605a str r2, [r3, #4]
-}
- 8000296: bf00 nop
- 8000298: 3714 adds r7, #20
- 800029a: 46bd mov sp, r7
- 800029c: f85d 7b04 ldr.w r7, [sp], #4
- 80002a0: 4770 bx lr
-
-080002a2 :
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- 80002a2: b480 push {r7}
- 80002a4: b083 sub sp, #12
- 80002a6: af00 add r7, sp, #0
- 80002a8: 6078 str r0, [r7, #4]
- 80002aa: 6039 str r1, [r7, #0]
- return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
- 80002ac: 687b ldr r3, [r7, #4]
- 80002ae: 691a ldr r2, [r3, #16]
- 80002b0: 683b ldr r3, [r7, #0]
- 80002b2: 4013 ands r3, r2
- 80002b4: 683a ldr r2, [r7, #0]
- 80002b6: 429a cmp r2, r3
- 80002b8: d101 bne.n 80002be
- 80002ba: 2301 movs r3, #1
- 80002bc: e000 b.n 80002c0
- 80002be: 2300 movs r3, #0
-}
- 80002c0: 4618 mov r0, r3
- 80002c2: 370c adds r7, #12
- 80002c4: 46bd mov sp, r7
- 80002c6: f85d 7b04 ldr.w r7, [sp], #4
- 80002ca: 4770 bx lr
-
-080002cc :
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- 80002cc: b480 push {r7}
- 80002ce: b083 sub sp, #12
- 80002d0: af00 add r7, sp, #0
- 80002d2: 6078 str r0, [r7, #4]
- 80002d4: 6039 str r1, [r7, #0]
- WRITE_REG(GPIOx->BSRR, PinMask);
- 80002d6: 687b ldr r3, [r7, #4]
- 80002d8: 683a ldr r2, [r7, #0]
- 80002da: 619a str r2, [r3, #24]
-}
- 80002dc: bf00 nop
- 80002de: 370c adds r7, #12
- 80002e0: 46bd mov sp, r7
- 80002e2: f85d 7b04 ldr.w r7, [sp], #4
- 80002e6: 4770 bx lr
-
-080002e8 :
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- 80002e8: b480 push {r7}
- 80002ea: b083 sub sp, #12
- 80002ec: af00 add r7, sp, #0
- 80002ee: 6078 str r0, [r7, #4]
- 80002f0: 6039 str r1, [r7, #0]
- WRITE_REG(GPIOx->BRR, PinMask);
- 80002f2: 687b ldr r3, [r7, #4]
- 80002f4: 683a ldr r2, [r7, #0]
- 80002f6: 629a str r2, [r3, #40] ; 0x28
-}
- 80002f8: bf00 nop
- 80002fa: 370c adds r7, #12
- 80002fc: 46bd mov sp, r7
- 80002fe: f85d 7b04 ldr.w r7, [sp], #4
- 8000302: 4770 bx lr
-
-08000304 :
-#define LED_PIN LL_GPIO_PIN_5
-#define BUT_PORT GPIOC
-#define BUT_PIN LL_GPIO_PIN_13
-
-void GPIO_init(void)
-{
- 8000304: b580 push {r7, lr}
- 8000306: af00 add r7, sp, #0
-// PORT A
-LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA );
- 8000308: 2001 movs r0, #1
- 800030a: f7ff ff5d bl 80001c8
-// Green LED (user LED) - PA5
-LL_GPIO_SetPinMode( LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT );
- 800030e: 2201 movs r2, #1
- 8000310: 2120 movs r1, #32
- 8000312: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
- 8000316: f7ff ff6f bl 80001f8
-LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL );
- 800031a: 2200 movs r2, #0
- 800031c: 2120 movs r1, #32
- 800031e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
- 8000322: f7ff ffa6 bl 8000272
-
-// PORT C
-LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC );
- 8000326: 2004 movs r0, #4
- 8000328: f7ff ff4e bl 80001c8
-// Blue button - PC13
-LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT );
- 800032c: 2200 movs r2, #0
- 800032e: f44f 5100 mov.w r1, #8192 ; 0x2000
- 8000332: 4802 ldr r0, [pc, #8] ; (800033c )
- 8000334: f7ff ff60 bl 80001f8
-}
- 8000338: bf00 nop
- 800033a: bd80 pop {r7, pc}
- 800033c: 48000800 .word 0x48000800
-
-08000340 :
-
-
-void LED_GREEN( int val )
-{
- 8000340: b580 push {r7, lr}
- 8000342: b082 sub sp, #8
- 8000344: af00 add r7, sp, #0
- 8000346: 6078 str r0, [r7, #4]
-if ( val )
- 8000348: 687b ldr r3, [r7, #4]
- 800034a: 2b00 cmp r3, #0
- 800034c: d005 beq.n 800035a
- LL_GPIO_SetOutputPin( LED_PORT, LED_PIN );
- 800034e: 2120 movs r1, #32
- 8000350: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
- 8000354: f7ff ffba bl 80002cc
-else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
-}
- 8000358: e004 b.n 8000364
-else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
- 800035a: 2120 movs r1, #32
- 800035c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
- 8000360: f7ff ffc2 bl 80002e8
-}
- 8000364: bf00 nop
- 8000366: 3708 adds r7, #8
- 8000368: 46bd mov sp, r7
- 800036a: bd80 pop {r7, pc}
-
-0800036c :
-
-int BLUE_BUTTON()
-{
- 800036c: b580 push {r7, lr}
- 800036e: af00 add r7, sp, #0
-return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) );
- 8000370: f44f 5100 mov.w r1, #8192 ; 0x2000
- 8000374: 4805 ldr r0, [pc, #20] ; (800038c )
- 8000376: f7ff ff94 bl 80002a2
- 800037a: 4603 mov r3, r0
- 800037c: 2b00 cmp r3, #0
- 800037e: bf0c ite eq
- 8000380: 2301 moveq r3, #1
- 8000382: 2300 movne r3, #0
- 8000384: b2db uxtb r3, r3
-}
- 8000386: 4618 mov r0, r3
- 8000388: bd80 pop {r7, pc}
- 800038a: bf00 nop
- 800038c: 48000800 .word 0x48000800
-
-08000390 :
- * @brief Enable MSI oscillator
- * @rmtoll CR MSION LL_RCC_MSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_MSI_Enable(void)
-{
- 8000390: b480 push {r7}
- 8000392: af00 add r7, sp, #0
- SET_BIT(RCC->CR, RCC_CR_MSION);
- 8000394: 4b05 ldr r3, [pc, #20] ; (80003ac )
- 8000396: 681b ldr r3, [r3, #0]
- 8000398: 4a04 ldr r2, [pc, #16] ; (80003ac )
- 800039a: f043 0301 orr.w r3, r3, #1
- 800039e: 6013 str r3, [r2, #0]
-}
- 80003a0: bf00 nop
- 80003a2: 46bd mov sp, r7
- 80003a4: f85d 7b04 ldr.w r7, [sp], #4
- 80003a8: 4770 bx lr
- 80003aa: bf00 nop
- 80003ac: 40021000 .word 0x40021000
-
-080003b0 :
- * @brief Check if MSI oscillator Ready
- * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
-{
- 80003b0: b480 push {r7}
- 80003b2: af00 add r7, sp, #0
- return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
- 80003b4: 4b06 ldr r3, [pc, #24] ; (80003d0 )
- 80003b6: 681b ldr r3, [r3, #0]
- 80003b8: f003 0302 and.w r3, r3, #2
- 80003bc: 2b02 cmp r3, #2
- 80003be: d101 bne.n 80003c4
- 80003c0: 2301 movs r3, #1
- 80003c2: e000 b.n 80003c6
- 80003c4: 2300 movs r3, #0
-}
- 80003c6: 4618 mov r0, r3
- 80003c8: 46bd mov sp, r7
- 80003ca: f85d 7b04 ldr.w r7, [sp], #4
- 80003ce: 4770 bx lr
- 80003d0: 40021000 .word 0x40021000
-
-080003d4 :
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
- 80003d4: b480 push {r7}
- 80003d6: b083 sub sp, #12
- 80003d8: af00 add r7, sp, #0
- 80003da: 6078 str r0, [r7, #4]
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
- 80003dc: 4b06 ldr r3, [pc, #24] ; (80003f8 )
- 80003de: 689b ldr r3, [r3, #8]
- 80003e0: f023 0203 bic.w r2, r3, #3
- 80003e4: 4904 ldr r1, [pc, #16] ; (80003f8 )
- 80003e6: 687b ldr r3, [r7, #4]
- 80003e8: 4313 orrs r3, r2
- 80003ea: 608b str r3, [r1, #8]
-}
- 80003ec: bf00 nop
- 80003ee: 370c adds r7, #12
- 80003f0: 46bd mov sp, r7
- 80003f2: f85d 7b04 ldr.w r7, [sp], #4
- 80003f6: 4770 bx lr
- 80003f8: 40021000 .word 0x40021000
-
-080003fc :
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
- 80003fc: b480 push {r7}
- 80003fe: af00 add r7, sp, #0
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
- 8000400: 4b04 ldr r3, [pc, #16] ; (8000414 )
- 8000402: 689b ldr r3, [r3, #8]
- 8000404: f003 030c and.w r3, r3, #12
-}
- 8000408: 4618 mov r0, r3
- 800040a: 46bd mov sp, r7
- 800040c: f85d 7b04 ldr.w r7, [sp], #4
- 8000410: 4770 bx lr
- 8000412: bf00 nop
- 8000414: 40021000 .word 0x40021000
-
-08000418 :
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
- 8000418: b480 push {r7}
- 800041a: b083 sub sp, #12
- 800041c: af00 add r7, sp, #0
- 800041e: 6078 str r0, [r7, #4]
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
- 8000420: 4b06 ldr r3, [pc, #24] ; (800043c )
- 8000422: 689b ldr r3, [r3, #8]
- 8000424: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 8000428: 4904 ldr r1, [pc, #16] ; (800043c )
- 800042a: 687b ldr r3, [r7, #4]
- 800042c: 4313 orrs r3, r2
- 800042e: 608b str r3, [r1, #8]
-}
- 8000430: bf00 nop
- 8000432: 370c adds r7, #12
- 8000434: 46bd mov sp, r7
- 8000436: f85d 7b04 ldr.w r7, [sp], #4
- 800043a: 4770 bx lr
- 800043c: 40021000 .word 0x40021000
-
-08000440 :
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
- 8000440: b480 push {r7}
- 8000442: b083 sub sp, #12
- 8000444: af00 add r7, sp, #0
- 8000446: 6078 str r0, [r7, #4]
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
- 8000448: 4b06 ldr r3, [pc, #24] ; (8000464 )
- 800044a: 689b ldr r3, [r3, #8]
- 800044c: f423 62e0 bic.w r2, r3, #1792 ; 0x700
- 8000450: 4904 ldr r1, [pc, #16] ; (8000464 )
- 8000452: 687b ldr r3, [r7, #4]
- 8000454: 4313 orrs r3, r2
- 8000456: 608b str r3, [r1, #8]
-}
- 8000458: bf00 nop
- 800045a: 370c adds r7, #12
- 800045c: 46bd mov sp, r7
- 800045e: f85d 7b04 ldr.w r7, [sp], #4
- 8000462: 4770 bx lr
- 8000464: 40021000 .word 0x40021000
-
-08000468 :
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
- 8000468: b480 push {r7}
- 800046a: b083 sub sp, #12
- 800046c: af00 add r7, sp, #0
- 800046e: 6078 str r0, [r7, #4]
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
- 8000470: 4b06 ldr r3, [pc, #24] ; (800048c )
- 8000472: 689b ldr r3, [r3, #8]
- 8000474: f423 5260 bic.w r2, r3, #14336 ; 0x3800
- 8000478: 4904 ldr r1, [pc, #16] ; (800048c )
- 800047a: 687b ldr r3, [r7, #4]
- 800047c: 4313 orrs r3, r2
- 800047e: 608b str r3, [r1, #8]
-}
- 8000480: bf00 nop
- 8000482: 370c adds r7, #12
- 8000484: 46bd mov sp, r7
- 8000486: f85d 7b04 ldr.w r7, [sp], #4
- 800048a: 4770 bx lr
- 800048c: 40021000 .word 0x40021000
-
-08000490 :
- * @brief Enable PLL
- * @rmtoll CR PLLON LL_RCC_PLL_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
- 8000490: b480 push {r7}
- 8000492: af00 add r7, sp, #0
- SET_BIT(RCC->CR, RCC_CR_PLLON);
- 8000494: 4b05 ldr r3, [pc, #20] ; (80004ac )
- 8000496: 681b ldr r3, [r3, #0]
- 8000498: 4a04 ldr r2, [pc, #16] ; (80004ac )
- 800049a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 800049e: 6013 str r3, [r2, #0]
-}
- 80004a0: bf00 nop
- 80004a2: 46bd mov sp, r7
- 80004a4: f85d 7b04 ldr.w r7, [sp], #4
- 80004a8: 4770 bx lr
- 80004aa: bf00 nop
- 80004ac: 40021000 .word 0x40021000
-
-080004b0 :
- * @brief Check if PLL Ready
- * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
- 80004b0: b480 push {r7}
- 80004b2: af00 add r7, sp, #0
- return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
- 80004b4: 4b07 ldr r3, [pc, #28] ; (80004d4 )
- 80004b6: 681b ldr r3, [r3, #0]
- 80004b8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80004bc: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 80004c0: d101 bne.n 80004c6
- 80004c2: 2301 movs r3, #1
- 80004c4: e000 b.n 80004c8
- 80004c6: 2300 movs r3, #0
-}
- 80004c8: 4618 mov r0, r3
- 80004ca: 46bd mov sp, r7
- 80004cc: f85d 7b04 ldr.w r7, [sp], #4
- 80004d0: 4770 bx lr
- 80004d2: bf00 nop
- 80004d4: 40021000 .word 0x40021000
-
-080004d8 :
- * @arg @ref LL_RCC_PLLR_DIV_6
- * @arg @ref LL_RCC_PLLR_DIV_8
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
-{
- 80004d8: b480 push {r7}
- 80004da: b085 sub sp, #20
- 80004dc: af00 add r7, sp, #0
- 80004de: 60f8 str r0, [r7, #12]
- 80004e0: 60b9 str r1, [r7, #8]
- 80004e2: 607a str r2, [r7, #4]
- 80004e4: 603b str r3, [r7, #0]
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
- 80004e6: 4b0a ldr r3, [pc, #40] ; (8000510 )
- 80004e8: 68da ldr r2, [r3, #12]
- 80004ea: 4b0a ldr r3, [pc, #40] ; (8000514 )
- 80004ec: 4013 ands r3, r2
- 80004ee: 68f9 ldr r1, [r7, #12]
- 80004f0: 68ba ldr r2, [r7, #8]
- 80004f2: 4311 orrs r1, r2
- 80004f4: 687a ldr r2, [r7, #4]
- 80004f6: 0212 lsls r2, r2, #8
- 80004f8: 4311 orrs r1, r2
- 80004fa: 683a ldr r2, [r7, #0]
- 80004fc: 430a orrs r2, r1
- 80004fe: 4904 ldr r1, [pc, #16] ; (8000510 )
- 8000500: 4313 orrs r3, r2
- 8000502: 60cb str r3, [r1, #12]
- Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
-}
- 8000504: bf00 nop
- 8000506: 3714 adds r7, #20
- 8000508: 46bd mov sp, r7
- 800050a: f85d 7b04 ldr.w r7, [sp], #4
- 800050e: 4770 bx lr
- 8000510: 40021000 .word 0x40021000
- 8000514: f9ff808c .word 0xf9ff808c
-
-08000518 :
- * @brief Enable PLL output mapped on SYSCLK domain
- * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
-{
- 8000518: b480 push {r7}
- 800051a: af00 add r7, sp, #0
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
- 800051c: 4b05 ldr r3, [pc, #20] ; (8000534 )
- 800051e: 68db ldr r3, [r3, #12]
- 8000520: 4a04 ldr r2, [pc, #16] ; (8000534 )
- 8000522: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 8000526: 60d3 str r3, [r2, #12]
-}
- 8000528: bf00 nop
- 800052a: 46bd mov sp, r7
- 800052c: f85d 7b04 ldr.w r7, [sp], #4
- 8000530: 4770 bx lr
- 8000532: bf00 nop
- 8000534: 40021000 .word 0x40021000
-
-08000538 :
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
- 8000538: b480 push {r7}
- 800053a: b083 sub sp, #12
- 800053c: af00 add r7, sp, #0
- 800053e: 6078 str r0, [r7, #4]
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
- 8000540: 4b06 ldr r3, [pc, #24] ; (800055c )
- 8000542: 681b ldr r3, [r3, #0]
- 8000544: f023 0207 bic.w r2, r3, #7
- 8000548: 4904 ldr r1, [pc, #16] ; (800055c )
- 800054a: 687b ldr r3, [r7, #4]
- 800054c: 4313 orrs r3, r2
- 800054e: 600b str r3, [r1, #0]
-}
- 8000550: bf00 nop
- 8000552: 370c adds r7, #12
- 8000554: 46bd mov sp, r7
- 8000556: f85d 7b04 ldr.w r7, [sp], #4
- 800055a: 4770 bx lr
- 800055c: 40022000 .word 0x40022000
-
-08000560 :
- * @brief Enable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
- 8000560: b480 push {r7}
- 8000562: af00 add r7, sp, #0
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
- 8000564: 4b05 ldr r3, [pc, #20] ; (800057c )
- 8000566: 681b ldr r3, [r3, #0]
- 8000568: 4a04 ldr r2, [pc, #16] ; (800057c )
- 800056a: f043 0302 orr.w r3, r3, #2
- 800056e: 6013 str r3, [r2, #0]
-}
- 8000570: bf00 nop
- 8000572: 46bd mov sp, r7
- 8000574: f85d 7b04 ldr.w r7, [sp], #4
- 8000578: 4770 bx lr
- 800057a: bf00 nop
- 800057c: e000e010 .word 0xe000e010
-
-08000580 :
- * @brief Processor uses sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
- 8000580: b480 push {r7}
- 8000582: af00 add r7, sp, #0
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
- 8000584: 4b05 ldr r3, [pc, #20] ; (800059c )
- 8000586: 691b ldr r3, [r3, #16]
- 8000588: 4a04 ldr r2, [pc, #16] ; (800059c )
- 800058a: f023 0304 bic.w r3, r3, #4
- 800058e: 6113 str r3, [r2, #16]
-}
- 8000590: bf00 nop
- 8000592: 46bd mov sp, r7
- 8000594: f85d 7b04 ldr.w r7, [sp], #4
- 8000598: 4770 bx lr
- 800059a: bf00 nop
- 800059c: e000ed00 .word 0xe000ed00
-
-080005a0 :
-volatile uint32_t msTicks = 0;
-volatile uint8_t expe = 0;
-volatile uint8_t blue_mode = 0;
-
-void SysTick_Handler()
-{
- 80005a0: b580 push {r7, lr}
- 80005a2: af00 add r7, sp, #0
- if ( BLUE_BUTTON() ){
- 80005a4: f7ff fee2 bl 800036c
- 80005a8: 4603 mov r3, r0
- 80005aa: 2b00 cmp r3, #0
- 80005ac: d002 beq.n 80005b4
- blue_mode = 1 ;
- 80005ae: 4b0e ldr r3, [pc, #56] ; (80005e8 )
- 80005b0: 2201 movs r2, #1
- 80005b2: 701a strb r2, [r3, #0]
- }
-
- msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
- 80005b4: 4b0d ldr r3, [pc, #52] ; (80005ec )
- 80005b6: 681b ldr r3, [r3, #0]
- 80005b8: 3301 adds r3, #1
- 80005ba: 4a0c ldr r2, [pc, #48] ; (80005ec )
- 80005bc: 6013 str r3, [r2, #0]
- if (msTicks == 5){
- 80005be: 4b0b ldr r3, [pc, #44] ; (80005ec )
- 80005c0: 681b ldr r3, [r3, #0]
- 80005c2: 2b05 cmp r3, #5
- 80005c4: d103 bne.n 80005ce
- LED_GREEN(0);
- 80005c6: 2000 movs r0, #0
- 80005c8: f7ff feba bl 8000340
- }else if(msTicks >= 200){
- msTicks = 0;
- LED_GREEN(1);
- }
-}
- 80005cc: e009 b.n 80005e2
- }else if(msTicks >= 200){
- 80005ce: 4b07 ldr r3, [pc, #28] ; (80005ec )
- 80005d0: 681b ldr r3, [r3, #0]
- 80005d2: 2bc7 cmp r3, #199 ; 0xc7
- 80005d4: d905 bls.n 80005e2
- msTicks = 0;
- 80005d6: 4b05 ldr r3, [pc, #20] ; (80005ec )
- 80005d8: 2200 movs r2, #0
- 80005da: 601a str r2, [r3, #0]
- LED_GREEN(1);
- 80005dc: 2001 movs r0, #1
- 80005de: f7ff feaf bl 8000340
-}
- 80005e2: bf00 nop
- 80005e4: bd80 pop {r7, pc}
- 80005e6: bf00 nop
- 80005e8: 20000024 .word 0x20000024
- 80005ec: 20000020 .word 0x20000020
-
-080005f0 :
-
-void SystemClock_Config(void);
-
-int main(void)
-{
- 80005f0: b580 push {r7, lr}
- 80005f2: af00 add r7, sp, #0
-/* Configure the system clock */
-SystemClock_Config();
- 80005f4: f000 f816 bl 8000624
-
-// config GPIO
-GPIO_init();
- 80005f8: f7ff fe84 bl 8000304
-
-// init systick timer (tick period at 1 ms)
-LL_Init1msTick( SystemCoreClock );
- 80005fc: 4b07 ldr r3, [pc, #28] ; (800061c )
- 80005fe: 681b ldr r3, [r3, #0]
- 8000600: 4618 mov r0, r3
- 8000602: f000 f99f bl 8000944
-LL_SYSTICK_EnableIT();
- 8000606: f7ff ffab bl 8000560
-
-//Setup Sleep mode
-LL_LPM_EnableSleep();
- 800060a: f7ff ffb9 bl 8000580
-//LL_LPM_EnableSleepOnExit();
-
-while (1) {
- if (blue_mode){
- 800060e: 4b04 ldr r3, [pc, #16] ; (8000620 )
- 8000610: 781b ldrb r3, [r3, #0]
- 8000612: b2db uxtb r3, r3
- 8000614: 2b00 cmp r3, #0
- 8000616: d0fa beq.n 800060e
- __WFI();
- 8000618: bf30 wfi
- if (blue_mode){
- 800061a: e7f8 b.n 800060e
- 800061c: 20000000 .word 0x20000000
- 8000620: 20000024 .word 0x20000024
-
-08000624 :
- * PLL_R = 2
- * Flash Latency(WS) = 4
- * @param None
- * @retval None
- */
-void SystemClock_Config(void) {
- 8000624: b580 push {r7, lr}
- 8000626: af00 add r7, sp, #0
-/* MSI configuration and activation */
-LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
- 8000628: 2004 movs r0, #4
- 800062a: f7ff ff85 bl 8000538
-LL_RCC_MSI_Enable();
- 800062e: f7ff feaf bl 8000390
-while (LL_RCC_MSI_IsReady() != 1)
- 8000632: bf00 nop
- 8000634: f7ff febc bl 80003b0
- 8000638: 4603 mov r3, r0
- 800063a: 2b01 cmp r3, #1
- 800063c: d1fa bne.n 8000634
- { };
-
-/* Main PLL configuration and activation */
-LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);
- 800063e: 2300 movs r3, #0
- 8000640: 2228 movs r2, #40 ; 0x28
- 8000642: 2100 movs r1, #0
- 8000644: 2001 movs r0, #1
- 8000646: f7ff ff47 bl 80004d8
-LL_RCC_PLL_Enable();
- 800064a: f7ff ff21 bl 8000490
-LL_RCC_PLL_EnableDomain_SYS();
- 800064e: f7ff ff63 bl 8000518
-while(LL_RCC_PLL_IsReady() != 1)
- 8000652: bf00 nop
- 8000654: f7ff ff2c bl 80004b0
- 8000658: 4603 mov r3, r0
- 800065a: 2b01 cmp r3, #1
- 800065c: d1fa bne.n 8000654
- { };
-
-/* Sysclk activation on the main PLL */
-LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
- 800065e: 2000 movs r0, #0
- 8000660: f7ff feda bl 8000418
-LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- 8000664: 2003 movs r0, #3
- 8000666: f7ff feb5 bl 80003d4
-while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- 800066a: bf00 nop
- 800066c: f7ff fec6 bl 80003fc
- 8000670: 4603 mov r3, r0
- 8000672: 2b0c cmp r3, #12
- 8000674: d1fa bne.n 800066c
- { };
-
-/* Set APB1 & APB2 prescaler*/
-LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
- 8000676: 2000 movs r0, #0
- 8000678: f7ff fee2 bl 8000440
-LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
- 800067c: 2000 movs r0, #0
- 800067e: f7ff fef3 bl 8000468
-
-/* Update the global variable called SystemCoreClock */
-SystemCoreClockUpdate();
- 8000682: f000 f861 bl 8000748
-}
- 8000686: bf00 nop
- 8000688: bd80 pop {r7, pc}
-
-0800068a :
-/******************************************************************************/
-/**
- * @brief This function handles Non maskable interrupt.
- */
-void NMI_Handler(void)
-{
- 800068a: b480 push {r7}
- 800068c: af00 add r7, sp, #0
-
- /* USER CODE END NonMaskableInt_IRQn 0 */
- /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-
- /* USER CODE END NonMaskableInt_IRQn 1 */
-}
- 800068e: bf00 nop
- 8000690: 46bd mov sp, r7
- 8000692: f85d 7b04 ldr.w r7, [sp], #4
- 8000696: 4770 bx lr
-
-08000698 :
-
-/**
- * @brief This function handles Hard fault interrupt.
- */
-void HardFault_Handler(void)
-{
- 8000698: b480 push {r7}
- 800069a: af00 add r7, sp, #0
- /* USER CODE BEGIN HardFault_IRQn 0 */
-
- /* USER CODE END HardFault_IRQn 0 */
- while (1)
- 800069c: e7fe b.n 800069c
-
-0800069e :
-
-/**
- * @brief This function handles Memory management fault.
- */
-void MemManage_Handler(void)
-{
- 800069e: b480 push {r7}
- 80006a0: af00 add r7, sp, #0
- /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
- /* USER CODE END MemoryManagement_IRQn 0 */
- while (1)
- 80006a2: e7fe b.n 80006a2
-
-080006a4 :
-
-/**
- * @brief This function handles Prefetch fault, memory access fault.
- */
-void BusFault_Handler(void)
-{
- 80006a4: b480 push {r7}
- 80006a6: af00 add r7, sp, #0
- /* USER CODE BEGIN BusFault_IRQn 0 */
-
- /* USER CODE END BusFault_IRQn 0 */
- while (1)
- 80006a8: e7fe b.n 80006a8
-
-080006aa :
-
-/**
- * @brief This function handles Undefined instruction or illegal state.
- */
-void UsageFault_Handler(void)
-{
- 80006aa: b480 push {r7}
- 80006ac: af00 add r7, sp, #0
- /* USER CODE BEGIN UsageFault_IRQn 0 */
-
- /* USER CODE END UsageFault_IRQn 0 */
- while (1)
- 80006ae: e7fe b.n 80006ae
-
-080006b0 :
-
-/**
- * @brief This function handles System service call via SWI instruction.
- */
-void SVC_Handler(void)
-{
- 80006b0: b480 push {r7}
- 80006b2: af00 add r7, sp, #0
-
- /* USER CODE END SVCall_IRQn 0 */
- /* USER CODE BEGIN SVCall_IRQn 1 */
-
- /* USER CODE END SVCall_IRQn 1 */
-}
- 80006b4: bf00 nop
- 80006b6: 46bd mov sp, r7
- 80006b8: f85d 7b04 ldr.w r7, [sp], #4
- 80006bc: 4770 bx lr
-
-080006be :
-
-/**
- * @brief This function handles Debug monitor.
- */
-void DebugMon_Handler(void)
-{
- 80006be: b480 push {r7}
- 80006c0: af00 add r7, sp, #0
-
- /* USER CODE END DebugMonitor_IRQn 0 */
- /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
- /* USER CODE END DebugMonitor_IRQn 1 */
-}
- 80006c2: bf00 nop
- 80006c4: 46bd mov sp, r7
- 80006c6: f85d 7b04 ldr.w r7, [sp], #4
- 80006ca: 4770 bx lr
-
-080006cc :
-
-/**
- * @brief This function handles Pendable request for system service.
- */
-void PendSV_Handler(void)
-{
- 80006cc: b480 push {r7}
- 80006ce: af00 add r7, sp, #0
-
- /* USER CODE END PendSV_IRQn 0 */
- /* USER CODE BEGIN PendSV_IRQn 1 */
-
- /* USER CODE END PendSV_IRQn 1 */
-}
- 80006d0: bf00 nop
- 80006d2: 46bd mov sp, r7
- 80006d4: f85d 7b04 ldr.w r7, [sp], #4
- 80006d8: 4770 bx lr
- ...
-
-080006dc :
- * @param None
- * @retval None
- */
-
-void SystemInit(void)
-{
- 80006dc: b480 push {r7}
- 80006de: af00 add r7, sp, #0
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 80006e0: 4b17 ldr r3, [pc, #92] ; (8000740 )
- 80006e2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80006e6: 4a16 ldr r2, [pc, #88] ; (8000740 )
- 80006e8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 80006ec: f8c2 3088 str.w r3, [r2, #136] ; 0x88
- #endif
-
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set MSION bit */
- RCC->CR |= RCC_CR_MSION;
- 80006f0: 4b14 ldr r3, [pc, #80] ; (8000744 )
- 80006f2: 681b ldr r3, [r3, #0]
- 80006f4: 4a13 ldr r2, [pc, #76] ; (8000744 )
- 80006f6: f043 0301 orr.w r3, r3, #1
- 80006fa: 6013 str r3, [r2, #0]
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000U;
- 80006fc: 4b11 ldr r3, [pc, #68] ; (8000744 )
- 80006fe: 2200 movs r2, #0
- 8000700: 609a str r2, [r3, #8]
-
- /* Reset HSEON, CSSON , HSION, and PLLON bits */
- RCC->CR &= 0xEAF6FFFFU;
- 8000702: 4b10 ldr r3, [pc, #64] ; (8000744 )
- 8000704: 681b ldr r3, [r3, #0]
- 8000706: 4a0f ldr r2, [pc, #60] ; (8000744 )
- 8000708: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
- 800070c: f423 2310 bic.w r3, r3, #589824 ; 0x90000
- 8000710: 6013 str r3, [r2, #0]
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x00001000U;
- 8000712: 4b0c ldr r3, [pc, #48] ; (8000744 )
- 8000714: f44f 5280 mov.w r2, #4096 ; 0x1000
- 8000718: 60da str r2, [r3, #12]
-
- /* Reset HSEBYP bit */
- RCC->CR &= 0xFFFBFFFFU;
- 800071a: 4b0a ldr r3, [pc, #40] ; (8000744 )
- 800071c: 681b ldr r3, [r3, #0]
- 800071e: 4a09 ldr r2, [pc, #36] ; (8000744 )
- 8000720: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8000724: 6013 str r3, [r2, #0]
-
- /* Disable all interrupts */
- RCC->CIER = 0x00000000U;
- 8000726: 4b07 ldr r3, [pc, #28] ; (8000744 )
- 8000728: 2200 movs r2, #0
- 800072a: 619a str r2, [r3, #24]
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 800072c: 4b04 ldr r3, [pc, #16] ; (8000740 )
- 800072e: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 8000732: 609a str r2, [r3, #8]
-#endif
-}
- 8000734: bf00 nop
- 8000736: 46bd mov sp, r7
- 8000738: f85d 7b04 ldr.w r7, [sp], #4
- 800073c: 4770 bx lr
- 800073e: bf00 nop
- 8000740: e000ed00 .word 0xe000ed00
- 8000744: 40021000 .word 0x40021000
-
-08000748 :
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- 8000748: b480 push {r7}
- 800074a: b087 sub sp, #28
- 800074c: af00 add r7, sp, #0
- uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
- 800074e: 2300 movs r3, #0
- 8000750: 60fb str r3, [r7, #12]
- 8000752: 2300 movs r3, #0
- 8000754: 617b str r3, [r7, #20]
- 8000756: 2300 movs r3, #0
- 8000758: 613b str r3, [r7, #16]
- 800075a: 2302 movs r3, #2
- 800075c: 60bb str r3, [r7, #8]
- 800075e: 2300 movs r3, #0
- 8000760: 607b str r3, [r7, #4]
- 8000762: 2302 movs r3, #2
- 8000764: 603b str r3, [r7, #0]
-
- /* Get MSI Range frequency--------------------------------------------------*/
- if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
- 8000766: 4b4f ldr r3, [pc, #316] ; (80008a4 )
- 8000768: 681b ldr r3, [r3, #0]
- 800076a: f003 0308 and.w r3, r3, #8
- 800076e: 2b00 cmp r3, #0
- 8000770: d107 bne.n 8000782
- { /* MSISRANGE from RCC_CSR applies */
- msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
- 8000772: 4b4c ldr r3, [pc, #304] ; (80008a4 )
- 8000774: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
- 8000778: 0a1b lsrs r3, r3, #8
- 800077a: f003 030f and.w r3, r3, #15
- 800077e: 617b str r3, [r7, #20]
- 8000780: e005 b.n 800078e
- }
- else
- { /* MSIRANGE from RCC_CR applies */
- msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
- 8000782: 4b48 ldr r3, [pc, #288] ; (80008a4 )
- 8000784: 681b ldr r3, [r3, #0]
- 8000786: 091b lsrs r3, r3, #4
- 8000788: f003 030f and.w r3, r3, #15
- 800078c: 617b str r3, [r7, #20]
- }
- /*MSI frequency range in HZ*/
- msirange = MSIRangeTable[msirange];
- 800078e: 4a46 ldr r2, [pc, #280] ; (80008a8 )
- 8000790: 697b ldr r3, [r7, #20]
- 8000792: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 8000796: 617b str r3, [r7, #20]
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (RCC->CFGR & RCC_CFGR_SWS)
- 8000798: 4b42 ldr r3, [pc, #264] ; (80008a4 )
- 800079a: 689b ldr r3, [r3, #8]
- 800079c: f003 030c and.w r3, r3, #12
- 80007a0: 2b0c cmp r3, #12
- 80007a2: d865 bhi.n 8000870
- 80007a4: a201 add r2, pc, #4 ; (adr r2, 80007ac )
- 80007a6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 80007aa: bf00 nop
- 80007ac: 080007e1 .word 0x080007e1
- 80007b0: 08000871 .word 0x08000871
- 80007b4: 08000871 .word 0x08000871
- 80007b8: 08000871 .word 0x08000871
- 80007bc: 080007e9 .word 0x080007e9
- 80007c0: 08000871 .word 0x08000871
- 80007c4: 08000871 .word 0x08000871
- 80007c8: 08000871 .word 0x08000871
- 80007cc: 080007f1 .word 0x080007f1
- 80007d0: 08000871 .word 0x08000871
- 80007d4: 08000871 .word 0x08000871
- 80007d8: 08000871 .word 0x08000871
- 80007dc: 080007f9 .word 0x080007f9
- {
- case 0x00: /* MSI used as system clock source */
- SystemCoreClock = msirange;
- 80007e0: 4a32 ldr r2, [pc, #200] ; (80008ac )
- 80007e2: 697b ldr r3, [r7, #20]
- 80007e4: 6013 str r3, [r2, #0]
- break;
- 80007e6: e047 b.n 8000878
-
- case 0x04: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- 80007e8: 4b30 ldr r3, [pc, #192] ; (80008ac )
- 80007ea: 4a31 ldr r2, [pc, #196] ; (80008b0 )
- 80007ec: 601a str r2, [r3, #0]
- break;
- 80007ee: e043 b.n 8000878
-
- case 0x08: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- 80007f0: 4b2e ldr r3, [pc, #184] ; (80008ac )
- 80007f2: 4a30 ldr r2, [pc, #192] ; (80008b4 )
- 80007f4: 601a str r2, [r3, #0]
- break;
- 80007f6: e03f b.n 8000878
-
- case 0x0C: /* PLL used as system clock source */
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
- 80007f8: 4b2a ldr r3, [pc, #168] ; (80008a4 )
- 80007fa: 68db ldr r3, [r3, #12]
- 80007fc: f003 0303 and.w r3, r3, #3
- 8000800: 607b str r3, [r7, #4]
- pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
- 8000802: 4b28 ldr r3, [pc, #160] ; (80008a4 )
- 8000804: 68db ldr r3, [r3, #12]
- 8000806: 091b lsrs r3, r3, #4
- 8000808: f003 0307 and.w r3, r3, #7
- 800080c: 3301 adds r3, #1
- 800080e: 603b str r3, [r7, #0]
-
- switch (pllsource)
- 8000810: 687b ldr r3, [r7, #4]
- 8000812: 2b02 cmp r3, #2
- 8000814: d002 beq.n 800081c
- 8000816: 2b03 cmp r3, #3
- 8000818: d006 beq.n 8000828
- 800081a: e00b b.n 8000834
- {
- case 0x02: /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm);
- 800081c: 4a24 ldr r2, [pc, #144] ; (80008b0 )
- 800081e: 683b ldr r3, [r7, #0]
- 8000820: fbb2 f3f3 udiv r3, r2, r3
- 8000824: 613b str r3, [r7, #16]
- break;
- 8000826: e00b b.n 8000840
-
- case 0x03: /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm);
- 8000828: 4a22 ldr r2, [pc, #136] ; (80008b4 )
- 800082a: 683b ldr r3, [r7, #0]
- 800082c: fbb2 f3f3 udiv r3, r2, r3
- 8000830: 613b str r3, [r7, #16]
- break;
- 8000832: e005 b.n 8000840
-
- default: /* MSI used as PLL clock source */
- pllvco = (msirange / pllm);
- 8000834: 697a ldr r2, [r7, #20]
- 8000836: 683b ldr r3, [r7, #0]
- 8000838: fbb2 f3f3 udiv r3, r2, r3
- 800083c: 613b str r3, [r7, #16]
- break;
- 800083e: bf00 nop
- }
- pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
- 8000840: 4b18 ldr r3, [pc, #96] ; (80008a4 )
- 8000842: 68db ldr r3, [r3, #12]
- 8000844: 0a1b lsrs r3, r3, #8
- 8000846: f003 027f and.w r2, r3, #127 ; 0x7f
- 800084a: 693b ldr r3, [r7, #16]
- 800084c: fb02 f303 mul.w r3, r2, r3
- 8000850: 613b str r3, [r7, #16]
- pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
- 8000852: 4b14 ldr r3, [pc, #80] ; (80008a4 )
- 8000854: 68db ldr r3, [r3, #12]
- 8000856: 0e5b lsrs r3, r3, #25
- 8000858: f003 0303 and.w r3, r3, #3
- 800085c: 3301 adds r3, #1
- 800085e: 005b lsls r3, r3, #1
- 8000860: 60bb str r3, [r7, #8]
- SystemCoreClock = pllvco/pllr;
- 8000862: 693a ldr r2, [r7, #16]
- 8000864: 68bb ldr r3, [r7, #8]
- 8000866: fbb2 f3f3 udiv r3, r2, r3
- 800086a: 4a10 ldr r2, [pc, #64] ; (80008ac )
- 800086c: 6013 str r3, [r2, #0]
- break;
- 800086e: e003 b.n 8000878
-
- default:
- SystemCoreClock = msirange;
- 8000870: 4a0e ldr r2, [pc, #56] ; (80008ac )
- 8000872: 697b ldr r3, [r7, #20]
- 8000874: 6013 str r3, [r2, #0]
- break;
- 8000876: bf00 nop
- }
- /* Compute HCLK clock frequency --------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
- 8000878: 4b0a ldr r3, [pc, #40] ; (80008a4 )
- 800087a: 689b ldr r3, [r3, #8]
- 800087c: 091b lsrs r3, r3, #4
- 800087e: f003 030f and.w r3, r3, #15
- 8000882: 4a0d ldr r2, [pc, #52] ; (80008b8 )
- 8000884: 5cd3 ldrb r3, [r2, r3]
- 8000886: 60fb str r3, [r7, #12]
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
- 8000888: 4b08 ldr r3, [pc, #32] ; (80008ac )
- 800088a: 681a ldr r2, [r3, #0]
- 800088c: 68fb ldr r3, [r7, #12]
- 800088e: fa22 f303 lsr.w r3, r2, r3
- 8000892: 4a06 ldr r2, [pc, #24] ; (80008ac )
- 8000894: 6013 str r3, [r2, #0]
-}
- 8000896: bf00 nop
- 8000898: 371c adds r7, #28
- 800089a: 46bd mov sp, r7
- 800089c: f85d 7b04 ldr.w r7, [sp], #4
- 80008a0: 4770 bx lr
- 80008a2: bf00 nop
- 80008a4: 40021000 .word 0x40021000
- 80008a8: 080009cc .word 0x080009cc
- 80008ac: 20000000 .word 0x20000000
- 80008b0: 00f42400 .word 0x00f42400
- 80008b4: 007a1200 .word 0x007a1200
- 80008b8: 080009bc .word 0x080009bc
-
-080008bc :
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* Set stack pointer */
- 80008bc: f8df d034 ldr.w sp, [pc, #52] ; 80008f4
-
-/* Call the clock system initialization function.*/
- bl SystemInit
- 80008c0: f7ff ff0c bl 80006dc
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- 80008c4: 2100 movs r1, #0
- b LoopCopyDataInit
- 80008c6: e003 b.n 80008d0
-
-080008c8 :
-
-CopyDataInit:
- ldr r3, =_sidata
- 80008c8: 4b0b ldr r3, [pc, #44] ; (80008f8 )
- ldr r3, [r3, r1]
- 80008ca: 585b ldr r3, [r3, r1]
- str r3, [r0, r1]
- 80008cc: 5043 str r3, [r0, r1]
- adds r1, r1, #4
- 80008ce: 3104 adds r1, #4
-
-080008d0 :
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- 80008d0: 480a ldr r0, [pc, #40] ; (80008fc )
- ldr r3, =_edata
- 80008d2: 4b0b ldr r3, [pc, #44] ; (8000900 )
- adds r2, r0, r1
- 80008d4: 1842 adds r2, r0, r1
- cmp r2, r3
- 80008d6: 429a cmp r2, r3
- bcc CopyDataInit
- 80008d8: d3f6 bcc.n 80008c8
- ldr r2, =_sbss
- 80008da: 4a0a ldr r2, [pc, #40] ; (8000904 )
- b LoopFillZerobss
- 80008dc: e002 b.n 80008e4
-
-080008de :
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- 80008de: 2300 movs r3, #0
- str r3, [r2], #4
- 80008e0: f842 3b04 str.w r3, [r2], #4
-
-080008e4 :
-
-LoopFillZerobss:
- ldr r3, = _ebss
- 80008e4: 4b08 ldr r3, [pc, #32] ; (8000908 )
- cmp r2, r3
- 80008e6: 429a cmp r2, r3
- bcc FillZerobss
- 80008e8: d3f9 bcc.n 80008de
-
-/* Call static constructors */
- bl __libc_init_array
- 80008ea: f000 f837 bl 800095c <__libc_init_array>
-/* Call the application's entry point.*/
- bl main
- 80008ee: f7ff fe7f bl 80005f0
-
-080008f2 :
-
-LoopForever:
- b LoopForever
- 80008f2: e7fe b.n 80008f2
- ldr sp, =_estack /* Set stack pointer */
- 80008f4: 20018000 .word 0x20018000
- ldr r3, =_sidata
- 80008f8: 08000a04 .word 0x08000a04
- ldr r0, =_sdata
- 80008fc: 20000000 .word 0x20000000
- ldr r3, =_edata
- 8000900: 20000004 .word 0x20000004
- ldr r2, =_sbss
- 8000904: 20000004 .word 0x20000004
- ldr r3, = _ebss
- 8000908: 20000028 .word 0x20000028
-
-0800090c :
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- 800090c: e7fe b.n 800090c
- ...
-
-08000910 :
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
- * @retval None
- */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
- 8000910: b480 push {r7}
- 8000912: b083 sub sp, #12
- 8000914: af00 add r7, sp, #0
- 8000916: 6078 str r0, [r7, #4]
- 8000918: 6039 str r1, [r7, #0]
- /* Configure the SysTick to have interrupt in 1ms time base */
- SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- 800091a: 687a ldr r2, [r7, #4]
- 800091c: 683b ldr r3, [r7, #0]
- 800091e: fbb2 f3f3 udiv r3, r2, r3
- 8000922: 4a07 ldr r2, [pc, #28] ; (8000940 )
- 8000924: 3b01 subs r3, #1
- 8000926: 6053 str r3, [r2, #4]
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8000928: 4b05 ldr r3, [pc, #20] ; (8000940 )
- 800092a: 2200 movs r2, #0
- 800092c: 609a str r2, [r3, #8]
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 800092e: 4b04 ldr r3, [pc, #16] ; (8000940 )
- 8000930: 2205 movs r2, #5
- 8000932: 601a str r2, [r3, #0]
- SysTick_CTRL_ENABLE_Msk;
-}
- 8000934: bf00 nop
- 8000936: 370c adds r7, #12
- 8000938: 46bd mov sp, r7
- 800093a: f85d 7b04 ldr.w r7, [sp], #4
- 800093e: 4770 bx lr
- 8000940: e000e010 .word 0xe000e010
-
-08000944 :
- * @param HCLKFrequency HCLK frequency in Hz
- * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
- * @retval None
- */
-void LL_Init1msTick(uint32_t HCLKFrequency)
-{
- 8000944: b580 push {r7, lr}
- 8000946: b082 sub sp, #8
- 8000948: af00 add r7, sp, #0
- 800094a: 6078 str r0, [r7, #4]
- /* Use frequency provided in argument */
- LL_InitTick(HCLKFrequency, 100U);
- 800094c: 2164 movs r1, #100 ; 0x64
- 800094e: 6878 ldr r0, [r7, #4]
- 8000950: f7ff ffde bl 8000910
-}
- 8000954: bf00 nop
- 8000956: 3708 adds r7, #8
- 8000958: 46bd mov sp, r7
- 800095a: bd80 pop {r7, pc}
-
-0800095c <__libc_init_array>:
- 800095c: b570 push {r4, r5, r6, lr}
- 800095e: 4e0d ldr r6, [pc, #52] ; (8000994 <__libc_init_array+0x38>)
- 8000960: 4c0d ldr r4, [pc, #52] ; (8000998 <__libc_init_array+0x3c>)
- 8000962: 1ba4 subs r4, r4, r6
- 8000964: 10a4 asrs r4, r4, #2
- 8000966: 2500 movs r5, #0
- 8000968: 42a5 cmp r5, r4
- 800096a: d109 bne.n 8000980 <__libc_init_array+0x24>
- 800096c: 4e0b ldr r6, [pc, #44] ; (800099c <__libc_init_array+0x40>)
- 800096e: 4c0c ldr r4, [pc, #48] ; (80009a0 <__libc_init_array+0x44>)
- 8000970: f000 f818 bl 80009a4 <_init>
- 8000974: 1ba4 subs r4, r4, r6
- 8000976: 10a4 asrs r4, r4, #2
- 8000978: 2500 movs r5, #0
- 800097a: 42a5 cmp r5, r4
- 800097c: d105 bne.n 800098a <__libc_init_array+0x2e>
- 800097e: bd70 pop {r4, r5, r6, pc}
- 8000980: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8000984: 4798 blx r3
- 8000986: 3501 adds r5, #1
- 8000988: e7ee b.n 8000968 <__libc_init_array+0xc>
- 800098a: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 800098e: 4798 blx r3
- 8000990: 3501 adds r5, #1
- 8000992: e7f2 b.n 800097a <__libc_init_array+0x1e>
- 8000994: 080009fc .word 0x080009fc
- 8000998: 080009fc .word 0x080009fc
- 800099c: 080009fc .word 0x080009fc
- 80009a0: 08000a00 .word 0x08000a00
-
-080009a4 <_init>:
- 80009a4: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80009a6: bf00 nop
- 80009a8: bcf8 pop {r3, r4, r5, r6, r7}
- 80009aa: bc08 pop {r3}
- 80009ac: 469e mov lr, r3
- 80009ae: 4770 bx lr
-
-080009b0 <_fini>:
- 80009b0: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80009b2: bf00 nop
- 80009b4: bcf8 pop {r3, r4, r5, r6, r7}
- 80009b6: bc08 pop {r3}
- 80009b8: 469e mov lr, r3
- 80009ba: 4770 bx lr
+
+L476_ats_blink-master.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .isr_vector 00000188 08000000 08000000 00010000 2**0
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 1 .text 00000834 08000188 08000188 00010188 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 2 .rodata 00000040 080009bc 080009bc 000109bc 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 3 .ARM.extab 00000000 080009fc 080009fc 00020004 2**0
+ CONTENTS
+ 4 .ARM 00000000 080009fc 080009fc 00020004 2**0
+ CONTENTS
+ 5 .preinit_array 00000000 080009fc 080009fc 00020004 2**0
+ CONTENTS, ALLOC, LOAD, DATA
+ 6 .init_array 00000004 080009fc 080009fc 000109fc 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 7 .fini_array 00000004 08000a00 08000a00 00010a00 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 8 .data 00000004 20000000 08000a04 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 9 .bss 00000024 20000004 08000a08 00020004 2**2
+ ALLOC
+ 10 ._user_heap_stack 00000600 20000028 08000a08 00020028 2**0
+ ALLOC
+ 11 .ARM.attributes 00000030 00000000 00000000 00020004 2**0
+ CONTENTS, READONLY
+ 12 .debug_info 000022b2 00000000 00000000 00020034 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 13 .debug_abbrev 00000771 00000000 00000000 000222e6 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 14 .debug_aranges 000002e0 00000000 00000000 00022a58 2**3
+ CONTENTS, READONLY, DEBUGGING
+ 15 .debug_ranges 00000288 00000000 00000000 00022d38 2**3
+ CONTENTS, READONLY, DEBUGGING
+ 16 .debug_macro 0001e120 00000000 00000000 00022fc0 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 17 .debug_line 00002035 00000000 00000000 000410e0 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 18 .debug_str 000a94c1 00000000 00000000 00043115 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 19 .comment 0000007b 00000000 00000000 000ec5d6 2**0
+ CONTENTS, READONLY
+ 20 .debug_frame 00000a20 00000000 00000000 000ec654 2**2
+ CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+08000188 <__do_global_dtors_aux>:
+ 8000188: b510 push {r4, lr}
+ 800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
+ 800018c: 7823 ldrb r3, [r4, #0]
+ 800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
+ 8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
+ 8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
+ 8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
+ 8000196: f3af 8000 nop.w
+ 800019a: 2301 movs r3, #1
+ 800019c: 7023 strb r3, [r4, #0]
+ 800019e: bd10 pop {r4, pc}
+ 80001a0: 20000004 .word 0x20000004
+ 80001a4: 00000000 .word 0x00000000
+ 80001a8: 080009a4 .word 0x080009a4
+
+080001ac :
+ 80001ac: b508 push {r3, lr}
+ 80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc )
+ 80001b0: b11b cbz r3, 80001ba
+ 80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 )
+ 80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 )
+ 80001b6: f3af 8000 nop.w
+ 80001ba: bd08 pop {r3, pc}
+ 80001bc: 00000000 .word 0x00000000
+ 80001c0: 20000008 .word 0x20000008
+ 80001c4: 080009a4 .word 0x080009a4
+
+080001c8 :
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ 80001c8: b480 push {r7}
+ 80001ca: b085 sub sp, #20
+ 80001cc: af00 add r7, sp, #0
+ 80001ce: 6078 str r0, [r7, #4]
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2ENR, Periphs);
+ 80001d0: 4b08 ldr r3, [pc, #32] ; (80001f4 )
+ 80001d2: 6cda ldr r2, [r3, #76] ; 0x4c
+ 80001d4: 4907 ldr r1, [pc, #28] ; (80001f4 )
+ 80001d6: 687b ldr r3, [r7, #4]
+ 80001d8: 4313 orrs r3, r2
+ 80001da: 64cb str r3, [r1, #76] ; 0x4c
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+ 80001dc: 4b05 ldr r3, [pc, #20] ; (80001f4 )
+ 80001de: 6cda ldr r2, [r3, #76] ; 0x4c
+ 80001e0: 687b ldr r3, [r7, #4]
+ 80001e2: 4013 ands r3, r2
+ 80001e4: 60fb str r3, [r7, #12]
+ (void)tmpreg;
+ 80001e6: 68fb ldr r3, [r7, #12]
+}
+ 80001e8: bf00 nop
+ 80001ea: 3714 adds r7, #20
+ 80001ec: 46bd mov sp, r7
+ 80001ee: f85d 7b04 ldr.w r7, [sp], #4
+ 80001f2: 4770 bx lr
+ 80001f4: 40021000 .word 0x40021000
+
+080001f8 :
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ 80001f8: b480 push {r7}
+ 80001fa: b08b sub sp, #44 ; 0x2c
+ 80001fc: af00 add r7, sp, #0
+ 80001fe: 60f8 str r0, [r7, #12]
+ 8000200: 60b9 str r1, [r7, #8]
+ 8000202: 607a str r2, [r7, #4]
+ MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+ 8000204: 68fb ldr r3, [r7, #12]
+ 8000206: 681a ldr r2, [r3, #0]
+ 8000208: 68bb ldr r3, [r7, #8]
+ 800020a: 617b str r3, [r7, #20]
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 800020c: 697b ldr r3, [r7, #20]
+ 800020e: fa93 f3a3 rbit r3, r3
+ 8000212: 613b str r3, [r7, #16]
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+ 8000214: 693b ldr r3, [r7, #16]
+ 8000216: 61bb str r3, [r7, #24]
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ 8000218: 69bb ldr r3, [r7, #24]
+ 800021a: 2b00 cmp r3, #0
+ 800021c: d101 bne.n 8000222
+ {
+ return 32U;
+ 800021e: 2320 movs r3, #32
+ 8000220: e003 b.n 800022a
+ }
+ return __builtin_clz(value);
+ 8000222: 69bb ldr r3, [r7, #24]
+ 8000224: fab3 f383 clz r3, r3
+ 8000228: b2db uxtb r3, r3
+ 800022a: 005b lsls r3, r3, #1
+ 800022c: 2103 movs r1, #3
+ 800022e: fa01 f303 lsl.w r3, r1, r3
+ 8000232: 43db mvns r3, r3
+ 8000234: 401a ands r2, r3
+ 8000236: 68bb ldr r3, [r7, #8]
+ 8000238: 623b str r3, [r7, #32]
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 800023a: 6a3b ldr r3, [r7, #32]
+ 800023c: fa93 f3a3 rbit r3, r3
+ 8000240: 61fb str r3, [r7, #28]
+ return result;
+ 8000242: 69fb ldr r3, [r7, #28]
+ 8000244: 627b str r3, [r7, #36] ; 0x24
+ if (value == 0U)
+ 8000246: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000248: 2b00 cmp r3, #0
+ 800024a: d101 bne.n 8000250
+ return 32U;
+ 800024c: 2320 movs r3, #32
+ 800024e: e003 b.n 8000258
+ return __builtin_clz(value);
+ 8000250: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000252: fab3 f383 clz r3, r3
+ 8000256: b2db uxtb r3, r3
+ 8000258: 005b lsls r3, r3, #1
+ 800025a: 6879 ldr r1, [r7, #4]
+ 800025c: fa01 f303 lsl.w r3, r1, r3
+ 8000260: 431a orrs r2, r3
+ 8000262: 68fb ldr r3, [r7, #12]
+ 8000264: 601a str r2, [r3, #0]
+}
+ 8000266: bf00 nop
+ 8000268: 372c adds r7, #44 ; 0x2c
+ 800026a: 46bd mov sp, r7
+ 800026c: f85d 7b04 ldr.w r7, [sp], #4
+ 8000270: 4770 bx lr
+
+08000272 :
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+ 8000272: b480 push {r7}
+ 8000274: b085 sub sp, #20
+ 8000276: af00 add r7, sp, #0
+ 8000278: 60f8 str r0, [r7, #12]
+ 800027a: 60b9 str r1, [r7, #8]
+ 800027c: 607a str r2, [r7, #4]
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+ 800027e: 68fb ldr r3, [r7, #12]
+ 8000280: 685a ldr r2, [r3, #4]
+ 8000282: 68bb ldr r3, [r7, #8]
+ 8000284: 43db mvns r3, r3
+ 8000286: 401a ands r2, r3
+ 8000288: 68bb ldr r3, [r7, #8]
+ 800028a: 6879 ldr r1, [r7, #4]
+ 800028c: fb01 f303 mul.w r3, r1, r3
+ 8000290: 431a orrs r2, r3
+ 8000292: 68fb ldr r3, [r7, #12]
+ 8000294: 605a str r2, [r3, #4]
+}
+ 8000296: bf00 nop
+ 8000298: 3714 adds r7, #20
+ 800029a: 46bd mov sp, r7
+ 800029c: f85d 7b04 ldr.w r7, [sp], #4
+ 80002a0: 4770 bx lr
+
+080002a2 :
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ 80002a2: b480 push {r7}
+ 80002a4: b083 sub sp, #12
+ 80002a6: af00 add r7, sp, #0
+ 80002a8: 6078 str r0, [r7, #4]
+ 80002aa: 6039 str r1, [r7, #0]
+ return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+ 80002ac: 687b ldr r3, [r7, #4]
+ 80002ae: 691a ldr r2, [r3, #16]
+ 80002b0: 683b ldr r3, [r7, #0]
+ 80002b2: 4013 ands r3, r2
+ 80002b4: 683a ldr r2, [r7, #0]
+ 80002b6: 429a cmp r2, r3
+ 80002b8: d101 bne.n 80002be
+ 80002ba: 2301 movs r3, #1
+ 80002bc: e000 b.n 80002c0
+ 80002be: 2300 movs r3, #0
+}
+ 80002c0: 4618 mov r0, r3
+ 80002c2: 370c adds r7, #12
+ 80002c4: 46bd mov sp, r7
+ 80002c6: f85d 7b04 ldr.w r7, [sp], #4
+ 80002ca: 4770 bx lr
+
+080002cc :
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ 80002cc: b480 push {r7}
+ 80002ce: b083 sub sp, #12
+ 80002d0: af00 add r7, sp, #0
+ 80002d2: 6078 str r0, [r7, #4]
+ 80002d4: 6039 str r1, [r7, #0]
+ WRITE_REG(GPIOx->BSRR, PinMask);
+ 80002d6: 687b ldr r3, [r7, #4]
+ 80002d8: 683a ldr r2, [r7, #0]
+ 80002da: 619a str r2, [r3, #24]
+}
+ 80002dc: bf00 nop
+ 80002de: 370c adds r7, #12
+ 80002e0: 46bd mov sp, r7
+ 80002e2: f85d 7b04 ldr.w r7, [sp], #4
+ 80002e6: 4770 bx lr
+
+080002e8 :
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ 80002e8: b480 push {r7}
+ 80002ea: b083 sub sp, #12
+ 80002ec: af00 add r7, sp, #0
+ 80002ee: 6078 str r0, [r7, #4]
+ 80002f0: 6039 str r1, [r7, #0]
+ WRITE_REG(GPIOx->BRR, PinMask);
+ 80002f2: 687b ldr r3, [r7, #4]
+ 80002f4: 683a ldr r2, [r7, #0]
+ 80002f6: 629a str r2, [r3, #40] ; 0x28
+}
+ 80002f8: bf00 nop
+ 80002fa: 370c adds r7, #12
+ 80002fc: 46bd mov sp, r7
+ 80002fe: f85d 7b04 ldr.w r7, [sp], #4
+ 8000302: 4770 bx lr
+
+08000304 :
+#define LED_PIN LL_GPIO_PIN_5
+#define BUT_PORT GPIOC
+#define BUT_PIN LL_GPIO_PIN_13
+
+void GPIO_init(void)
+{
+ 8000304: b580 push {r7, lr}
+ 8000306: af00 add r7, sp, #0
+// PORT A
+LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA );
+ 8000308: 2001 movs r0, #1
+ 800030a: f7ff ff5d bl 80001c8
+// Green LED (user LED) - PA5
+LL_GPIO_SetPinMode( LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT );
+ 800030e: 2201 movs r2, #1
+ 8000310: 2120 movs r1, #32
+ 8000312: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
+ 8000316: f7ff ff6f bl 80001f8
+LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL );
+ 800031a: 2200 movs r2, #0
+ 800031c: 2120 movs r1, #32
+ 800031e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
+ 8000322: f7ff ffa6 bl 8000272
+
+// PORT C
+LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC );
+ 8000326: 2004 movs r0, #4
+ 8000328: f7ff ff4e bl 80001c8
+// Blue button - PC13
+LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT );
+ 800032c: 2200 movs r2, #0
+ 800032e: f44f 5100 mov.w r1, #8192 ; 0x2000
+ 8000332: 4802 ldr r0, [pc, #8] ; (800033c )
+ 8000334: f7ff ff60 bl 80001f8
+}
+ 8000338: bf00 nop
+ 800033a: bd80 pop {r7, pc}
+ 800033c: 48000800 .word 0x48000800
+
+08000340 :
+
+
+void LED_GREEN( int val )
+{
+ 8000340: b580 push {r7, lr}
+ 8000342: b082 sub sp, #8
+ 8000344: af00 add r7, sp, #0
+ 8000346: 6078 str r0, [r7, #4]
+if ( val )
+ 8000348: 687b ldr r3, [r7, #4]
+ 800034a: 2b00 cmp r3, #0
+ 800034c: d005 beq.n 800035a
+ LL_GPIO_SetOutputPin( LED_PORT, LED_PIN );
+ 800034e: 2120 movs r1, #32
+ 8000350: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
+ 8000354: f7ff ffba bl 80002cc
+else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
+}
+ 8000358: e004 b.n 8000364
+else LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
+ 800035a: 2120 movs r1, #32
+ 800035c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
+ 8000360: f7ff ffc2 bl 80002e8
+}
+ 8000364: bf00 nop
+ 8000366: 3708 adds r7, #8
+ 8000368: 46bd mov sp, r7
+ 800036a: bd80 pop {r7, pc}
+
+0800036c :
+
+int BLUE_BUTTON()
+{
+ 800036c: b580 push {r7, lr}
+ 800036e: af00 add r7, sp, #0
+return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) );
+ 8000370: f44f 5100 mov.w r1, #8192 ; 0x2000
+ 8000374: 4805 ldr r0, [pc, #20] ; (800038c )
+ 8000376: f7ff ff94 bl 80002a2
+ 800037a: 4603 mov r3, r0
+ 800037c: 2b00 cmp r3, #0
+ 800037e: bf0c ite eq
+ 8000380: 2301 moveq r3, #1
+ 8000382: 2300 movne r3, #0
+ 8000384: b2db uxtb r3, r3
+}
+ 8000386: 4618 mov r0, r3
+ 8000388: bd80 pop {r7, pc}
+ 800038a: bf00 nop
+ 800038c: 48000800 .word 0x48000800
+
+08000390 :
+ * @brief Enable MSI oscillator
+ * @rmtoll CR MSION LL_RCC_MSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_Enable(void)
+{
+ 8000390: b480 push {r7}
+ 8000392: af00 add r7, sp, #0
+ SET_BIT(RCC->CR, RCC_CR_MSION);
+ 8000394: 4b05 ldr r3, [pc, #20] ; (80003ac )
+ 8000396: 681b ldr r3, [r3, #0]
+ 8000398: 4a04 ldr r2, [pc, #16] ; (80003ac )
+ 800039a: f043 0301 orr.w r3, r3, #1
+ 800039e: 6013 str r3, [r2, #0]
+}
+ 80003a0: bf00 nop
+ 80003a2: 46bd mov sp, r7
+ 80003a4: f85d 7b04 ldr.w r7, [sp], #4
+ 80003a8: 4770 bx lr
+ 80003aa: bf00 nop
+ 80003ac: 40021000 .word 0x40021000
+
+080003b0 :
+ * @brief Check if MSI oscillator Ready
+ * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
+{
+ 80003b0: b480 push {r7}
+ 80003b2: af00 add r7, sp, #0
+ return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
+ 80003b4: 4b06 ldr r3, [pc, #24] ; (80003d0 )
+ 80003b6: 681b ldr r3, [r3, #0]
+ 80003b8: f003 0302 and.w r3, r3, #2
+ 80003bc: 2b02 cmp r3, #2
+ 80003be: d101 bne.n 80003c4
+ 80003c0: 2301 movs r3, #1
+ 80003c2: e000 b.n 80003c6
+ 80003c4: 2300 movs r3, #0
+}
+ 80003c6: 4618 mov r0, r3
+ 80003c8: 46bd mov sp, r7
+ 80003ca: f85d 7b04 ldr.w r7, [sp], #4
+ 80003ce: 4770 bx lr
+ 80003d0: 40021000 .word 0x40021000
+
+080003d4 :
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+ 80003d4: b480 push {r7}
+ 80003d6: b083 sub sp, #12
+ 80003d8: af00 add r7, sp, #0
+ 80003da: 6078 str r0, [r7, #4]
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+ 80003dc: 4b06 ldr r3, [pc, #24] ; (80003f8 )
+ 80003de: 689b ldr r3, [r3, #8]
+ 80003e0: f023 0203 bic.w r2, r3, #3
+ 80003e4: 4904 ldr r1, [pc, #16] ; (80003f8 )
+ 80003e6: 687b ldr r3, [r7, #4]
+ 80003e8: 4313 orrs r3, r2
+ 80003ea: 608b str r3, [r1, #8]
+}
+ 80003ec: bf00 nop
+ 80003ee: 370c adds r7, #12
+ 80003f0: 46bd mov sp, r7
+ 80003f2: f85d 7b04 ldr.w r7, [sp], #4
+ 80003f6: 4770 bx lr
+ 80003f8: 40021000 .word 0x40021000
+
+080003fc