diff --git a/L476_ats_blink-master/.cproject b/L476_ats_blink-master/.cproject
index 32e8b10..fa99011 100644
--- a/L476_ats_blink-master/.cproject
+++ b/L476_ats_blink-master/.cproject
@@ -36,28 +36,17 @@
@@ -117,7 +106,7 @@
-
+
@@ -128,27 +117,16 @@
@@ -199,4 +177,5 @@
+
diff --git a/L476_ats_blink-master/.mxproject b/L476_ats_blink-master/.mxproject
index e91bbe3..b0adf27 100644
--- a/L476_ats_blink-master/.mxproject
+++ b/L476_ats_blink-master/.mxproject
@@ -1,24 +1,26 @@
[PreviousLibFiles]
-LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
[PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;Core\Src\stm32l4xx_it.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c;Core\Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c;Core\Src/system_stm32l4xx.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;;
-HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32L4xx\Include;Drivers\CMSIS\Include;Core\Inc;
-CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:4000000;EXTERNALSAI1_CLOCK_VALUE:2097000;EXTERNALSAI2_CLOCK_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:32000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;STM32L476xx;USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:4000000;EXTERNALSAI1_CLOCK_VALUE:2097000;EXTERNALSAI2_CLOCK_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:32000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;
+SourceFiles=Core\Src\main.c;Core\Src\stm32l4xx_it.c;Core\Src\stm32l4xx_hal_msp.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Core\Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Core\Src/system_stm32l4xx.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;;
+HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32L4xx\Include;Drivers\CMSIS\Include;Core\Inc;
+CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32L476xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
[PreviousGenFiles]
AdvancedFolderStructure=true
-HeaderFileListSize=3
-HeaderFiles#0=C:/Users/adminaboyer/alex/enseignements_2020_21/TP_Prog_faible_energie/WorkSpace_STM32CubeIDE/L476_ats_blink-master/Core/Inc/stm32l4xx_it.h
-HeaderFiles#1=C:/Users/adminaboyer/alex/enseignements_2020_21/TP_Prog_faible_energie/WorkSpace_STM32CubeIDE/L476_ats_blink-master/Core/Inc/stm32_assert.h
-HeaderFiles#2=C:/Users/adminaboyer/alex/enseignements_2020_21/TP_Prog_faible_energie/WorkSpace_STM32CubeIDE/L476_ats_blink-master/Core/Inc/main.h
+HeaderFileListSize=4
+HeaderFiles#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/stm32l4xx_it.h
+HeaderFiles#1=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/stm32_assert.h
+HeaderFiles#2=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/stm32l4xx_hal_conf.h
+HeaderFiles#3=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc/main.h
HeaderFolderListSize=1
-HeaderPath#0=C:/Users/adminaboyer/alex/enseignements_2020_21/TP_Prog_faible_energie/WorkSpace_STM32CubeIDE/L476_ats_blink-master/Core/Inc
+HeaderPath#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Inc
HeaderFiles=;
-SourceFileListSize=2
-SourceFiles#0=C:/Users/adminaboyer/alex/enseignements_2020_21/TP_Prog_faible_energie/WorkSpace_STM32CubeIDE/L476_ats_blink-master/Core/Src/stm32l4xx_it.c
-SourceFiles#1=C:/Users/adminaboyer/alex/enseignements_2020_21/TP_Prog_faible_energie/WorkSpace_STM32CubeIDE/L476_ats_blink-master/Core/Src/main.c
+SourceFileListSize=3
+SourceFiles#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src/stm32l4xx_it.c
+SourceFiles#1=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src/stm32l4xx_hal_msp.c
+SourceFiles#2=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src/main.c
SourceFolderListSize=1
-SourcePath#0=C:/Users/adminaboyer/alex/enseignements_2020_21/TP_Prog_faible_energie/WorkSpace_STM32CubeIDE/L476_ats_blink-master/Core/Src
+SourcePath#0=C:/Users/camer/Desktop/LoPoSo/L476_ats_blink-master/Core/Src
SourceFiles=;
diff --git a/L476_ats_blink-master/Core/Inc/main.h b/L476_ats_blink-master/Core/Inc/main.h
index 510f87b..460e791 100644
--- a/L476_ats_blink-master/Core/Inc/main.h
+++ b/L476_ats_blink-master/Core/Inc/main.h
@@ -28,6 +28,7 @@ extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
#include "stm32l4xx_ll_crs.h"
#include "stm32l4xx_ll_rcc.h"
#include "stm32l4xx_ll_bus.h"
@@ -39,10 +40,6 @@ extern "C" {
#include "stm32l4xx_ll_dma.h"
#include "stm32l4xx_ll_gpio.h"
-#if defined(USE_FULL_ASSERT)
-#include "stm32_assert.h"
-#endif /* USE_FULL_ASSERT */
-
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
@@ -71,18 +68,6 @@ void Error_Handler(void);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
-#ifndef NVIC_PRIORITYGROUP_0
-#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
- 1 bit for subpriority */
-#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
- 0 bit for subpriority */
-#endif
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
diff --git a/L476_ats_blink-master/Core/Src/main.c b/L476_ats_blink-master/Core/Src/main.c
index 7a03724..b0c1462 100644
--- a/L476_ats_blink-master/Core/Src/main.c
+++ b/L476_ats_blink-master/Core/Src/main.c
@@ -24,11 +24,14 @@ volatile uint8_t blue_mode = 0;
void SysTick_Handler()
{
+ if ( BLUE_BUTTON() ){
+ blue_mode = 1 ;
+ }
msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
- if (msTicks == 50){
+ if (msTicks == 5){
LED_GREEN(0);
- }else if(msTicks >= 1000){
+ }else if(msTicks >= 200){
msTicks = 0;
LED_GREEN(1);
}
@@ -48,11 +51,15 @@ GPIO_init();
LL_Init1msTick( SystemCoreClock );
LL_SYSTICK_EnableIT();
+//Setup Sleep mode
+LL_LPM_EnableSleep();
+//LL_LPM_EnableSleepOnExit();
while (1) {
- if ( BLUE_BUTTON() ){
- blue_mode = 1;
+ if (blue_mode){
+ __WFI();
}
+
// else {
// LED_GREEN(0);
// LL_mDelay(950);
@@ -85,20 +92,20 @@ LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
LL_RCC_MSI_Enable();
while (LL_RCC_MSI_IsReady() != 1)
{ };
-
+
/* Main PLL configuration and activation */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);
LL_RCC_PLL_Enable();
LL_RCC_PLL_EnableDomain_SYS();
while(LL_RCC_PLL_IsReady() != 1)
{ };
-
+
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{ };
-
+
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
diff --git a/L476_ats_blink-master/Core/Src/stm32l4xx_it.c b/L476_ats_blink-master/Core/Src/stm32l4xx_it.c
index 613bc7a..a08e99e 100644
--- a/L476_ats_blink-master/Core/Src/stm32l4xx_it.c
+++ b/L476_ats_blink-master/Core/Src/stm32l4xx_it.c
@@ -179,16 +179,16 @@ void PendSV_Handler(void)
/**
* @brief This function handles System tick timer.
*/
-//void SysTick_Handler(void)
-//{
-// /* USER CODE BEGIN SysTick_IRQn 0 */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
//
-// /* USER CODE END SysTick_IRQn 0 */
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ /* USER CODE BEGIN SysTick_IRQn 1 */
//
-// /* USER CODE BEGIN SysTick_IRQn 1 */
-//
-// /* USER CODE END SysTick_IRQn 1 */
-//}
+ /* USER CODE END SysTick_IRQn 1 */
+}
/******************************************************************************/
/* STM32L4xx Peripheral Interrupt Handlers */
diff --git a/L476_ats_blink-master/Debug/Core/Src/main.o b/L476_ats_blink-master/Debug/Core/Src/main.o
index a25367f..f4cc805 100644
Binary files a/L476_ats_blink-master/Debug/Core/Src/main.o and b/L476_ats_blink-master/Debug/Core/Src/main.o differ
diff --git a/L476_ats_blink-master/Debug/Core/Src/main.su b/L476_ats_blink-master/Debug/Core/Src/main.su
index 70c16be..7678bba 100644
--- a/L476_ats_blink-master/Debug/Core/Src/main.su
+++ b/L476_ats_blink-master/Debug/Core/Src/main.su
@@ -11,6 +11,7 @@ stm32l4xx_ll_rcc.h:3800:22:LL_RCC_PLL_ConfigDomain_SYS 24 static
stm32l4xx_ll_rcc.h:4178:22:LL_RCC_PLL_EnableDomain_SYS 4 static
stm32l4xx_ll_system.h:1400:22:LL_FLASH_SetLatency 16 static
stm32l4xx_ll_cortex.h:272:22:LL_SYSTICK_EnableIT 4 static
+stm32l4xx_ll_cortex.h:310:22:LL_LPM_EnableSleep 4 static
main.c:25:6:SysTick_Handler 8 static
-main.c:39:5:main 8 static
-main.c:82:6:SystemClock_Config 8 static
+main.c:42:5:main 8 static,ignoring_inline_asm
+main.c:89:6:SystemClock_Config 8 static
diff --git a/L476_ats_blink-master/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.o b/L476_ats_blink-master/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.o
index 501c2d7..53b9d64 100644
Binary files a/L476_ats_blink-master/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.o and b/L476_ats_blink-master/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.o differ
diff --git a/L476_ats_blink-master/Debug/L476_ats_blink-master.bin b/L476_ats_blink-master/Debug/L476_ats_blink-master.bin
index 6afe729..6a1428c 100644
Binary files a/L476_ats_blink-master/Debug/L476_ats_blink-master.bin and b/L476_ats_blink-master/Debug/L476_ats_blink-master.bin differ
diff --git a/L476_ats_blink-master/Debug/L476_ats_blink-master.elf b/L476_ats_blink-master/Debug/L476_ats_blink-master.elf
index ecbc6bf..7a3bbf5 100644
Binary files a/L476_ats_blink-master/Debug/L476_ats_blink-master.elf and b/L476_ats_blink-master/Debug/L476_ats_blink-master.elf differ
diff --git a/L476_ats_blink-master/Debug/L476_ats_blink-master.list b/L476_ats_blink-master/Debug/L476_ats_blink-master.list
index 8ca194f..7173645 100644
--- a/L476_ats_blink-master/Debug/L476_ats_blink-master.list
+++ b/L476_ats_blink-master/Debug/L476_ats_blink-master.list
@@ -5,45 +5,45 @@ Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 00000804 08000188 08000188 00010188 2**2
+ 1 .text 00000834 08000188 08000188 00010188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000040 0800098c 0800098c 0001098c 2**2
+ 2 .rodata 00000040 080009bc 080009bc 000109bc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 080009cc 080009cc 00020004 2**0
+ 3 .ARM.extab 00000000 080009fc 080009fc 00020004 2**0
CONTENTS
- 4 .ARM 00000000 080009cc 080009cc 00020004 2**0
+ 4 .ARM 00000000 080009fc 080009fc 00020004 2**0
CONTENTS
- 5 .preinit_array 00000000 080009cc 080009cc 00020004 2**0
+ 5 .preinit_array 00000000 080009fc 080009fc 00020004 2**0
CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000004 080009cc 080009cc 000109cc 2**2
+ 6 .init_array 00000004 080009fc 080009fc 000109fc 2**2
CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 080009d0 080009d0 000109d0 2**2
+ 7 .fini_array 00000004 08000a00 08000a00 00010a00 2**2
CONTENTS, ALLOC, LOAD, DATA
- 8 .data 00000004 20000000 080009d4 00020000 2**2
+ 8 .data 00000004 20000000 08000a04 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 00000024 20000004 080009d8 00020004 2**2
+ 9 .bss 00000024 20000004 08000a08 00020004 2**2
ALLOC
- 10 ._user_heap_stack 00000600 20000028 080009d8 00020028 2**0
+ 10 ._user_heap_stack 00000600 20000028 08000a08 00020028 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00020004 2**0
CONTENTS, READONLY
- 12 .debug_info 00002106 00000000 00000000 00020034 2**0
+ 12 .debug_info 000022b2 00000000 00000000 00020034 2**0
CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 00000771 00000000 00000000 0002213a 2**0
+ 13 .debug_abbrev 00000771 00000000 00000000 000222e6 2**0
CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 000002d8 00000000 00000000 000228b0 2**3
+ 14 .debug_aranges 000002e0 00000000 00000000 00022a58 2**3
CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000280 00000000 00000000 00022b88 2**3
+ 15 .debug_ranges 00000288 00000000 00000000 00022d38 2**3
CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 0001e120 00000000 00000000 00022e08 2**0
+ 16 .debug_macro 0001e120 00000000 00000000 00022fc0 2**0
CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 0000201e 00000000 00000000 00040f28 2**0
+ 17 .debug_line 00002035 00000000 00000000 000410e0 2**0
CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000a94ae 00000000 00000000 00042f46 2**0
+ 18 .debug_str 000a94c1 00000000 00000000 00043115 2**0
CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 000ec3f4 2**0
+ 19 .comment 0000007b 00000000 00000000 000ec5d6 2**0
CONTENTS, READONLY
- 20 .debug_frame 00000a00 00000000 00000000 000ec470 2**2
+ 20 .debug_frame 00000a20 00000000 00000000 000ec654 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
@@ -62,7 +62,7 @@ Disassembly of section .text:
800019e: bd10 pop {r4, pc}
80001a0: 20000004 .word 0x20000004
80001a4: 00000000 .word 0x00000000
- 80001a8: 08000974 .word 0x08000974
+ 80001a8: 080009a4 .word 0x080009a4
080001ac :
80001ac: b508 push {r3, lr}
@@ -74,7 +74,7 @@ Disassembly of section .text:
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000008 .word 0x20000008
- 80001c4: 08000974 .word 0x08000974
+ 80001c4: 080009a4 .word 0x080009a4
080001c8 :
*
@@ -742,814 +742,852 @@ __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
800057a: bf00 nop
800057c: e000e010 .word 0xe000e010
-08000580 :
+08000580 :
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+ 8000580: b480 push {r7}
+ 8000582: af00 add r7, sp, #0
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 8000584: 4b05 ldr r3, [pc, #20] ; (800059c )
+ 8000586: 691b ldr r3, [r3, #16]
+ 8000588: 4a04 ldr r2, [pc, #16] ; (800059c )
+ 800058a: f023 0304 bic.w r3, r3, #4
+ 800058e: 6113 str r3, [r2, #16]
+}
+ 8000590: bf00 nop
+ 8000592: 46bd mov sp, r7
+ 8000594: f85d 7b04 ldr.w r7, [sp], #4
+ 8000598: 4770 bx lr
+ 800059a: bf00 nop
+ 800059c: e000ed00 .word 0xe000ed00
+
+080005a0 :
volatile uint32_t msTicks = 0;
volatile uint8_t expe = 0;
volatile uint8_t blue_mode = 0;
void SysTick_Handler()
{
- 8000580: b580 push {r7, lr}
- 8000582: af00 add r7, sp, #0
+ 80005a0: b580 push {r7, lr}
+ 80005a2: af00 add r7, sp, #0
+ if ( BLUE_BUTTON() ){
+ 80005a4: f7ff fee2 bl 800036c
+ 80005a8: 4603 mov r3, r0
+ 80005aa: 2b00 cmp r3, #0
+ 80005ac: d002 beq.n 80005b4
+ blue_mode = 1 ;
+ 80005ae: 4b0e ldr r3, [pc, #56] ; (80005e8 )
+ 80005b0: 2201 movs r2, #1
+ 80005b2: 701a strb r2, [r3, #0]
+ }
msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
- 8000584: 4b0c ldr r3, [pc, #48] ; (80005b8 )
- 8000586: 681b ldr r3, [r3, #0]
- 8000588: 3301 adds r3, #1
- 800058a: 4a0b ldr r2, [pc, #44] ; (80005b8 )
- 800058c: 6013 str r3, [r2, #0]
- if (msTicks == 50){
- 800058e: 4b0a ldr r3, [pc, #40] ; (80005b8 )
- 8000590: 681b ldr r3, [r3, #0]
- 8000592: 2b32 cmp r3, #50 ; 0x32
- 8000594: d103 bne.n 800059e
+ 80005b4: 4b0d ldr r3, [pc, #52] ; (80005ec )
+ 80005b6: 681b ldr r3, [r3, #0]
+ 80005b8: 3301 adds r3, #1
+ 80005ba: 4a0c ldr r2, [pc, #48] ; (80005ec )
+ 80005bc: 6013 str r3, [r2, #0]
+ if (msTicks == 5){
+ 80005be: 4b0b ldr r3, [pc, #44] ; (80005ec )
+ 80005c0: 681b ldr r3, [r3, #0]
+ 80005c2: 2b05 cmp r3, #5
+ 80005c4: d103 bne.n 80005ce
LED_GREEN(0);
- 8000596: 2000 movs r0, #0
- 8000598: f7ff fed2 bl 8000340
- }else if(msTicks >= 1000){
+ 80005c6: 2000 movs r0, #0
+ 80005c8: f7ff feba bl 8000340
+ }else if(msTicks >= 200){
msTicks = 0;
LED_GREEN(1);
}
}
- 800059c: e00a b.n 80005b4
- }else if(msTicks >= 1000){
- 800059e: 4b06 ldr r3, [pc, #24] ; (80005b8 )
- 80005a0: 681b ldr r3, [r3, #0]
- 80005a2: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
- 80005a6: d305 bcc.n 80005b4
+ 80005cc: e009 b.n 80005e2
+ }else if(msTicks >= 200){
+ 80005ce: 4b07 ldr r3, [pc, #28] ; (80005ec )
+ 80005d0: 681b ldr r3, [r3, #0]
+ 80005d2: 2bc7 cmp r3, #199 ; 0xc7
+ 80005d4: d905 bls.n 80005e2
msTicks = 0;
- 80005a8: 4b03 ldr r3, [pc, #12] ; (80005b8 )
- 80005aa: 2200 movs r2, #0
- 80005ac: 601a str r2, [r3, #0]
+ 80005d6: 4b05 ldr r3, [pc, #20] ; (80005ec )
+ 80005d8: 2200 movs r2, #0
+ 80005da: 601a str r2, [r3, #0]
LED_GREEN(1);
- 80005ae: 2001 movs r0, #1
- 80005b0: f7ff fec6 bl 8000340
+ 80005dc: 2001 movs r0, #1
+ 80005de: f7ff feaf bl 8000340
}
- 80005b4: bf00 nop
- 80005b6: bd80 pop {r7, pc}
- 80005b8: 20000020 .word 0x20000020
+ 80005e2: bf00 nop
+ 80005e4: bd80 pop {r7, pc}
+ 80005e6: bf00 nop
+ 80005e8: 20000024 .word 0x20000024
+ 80005ec: 20000020 .word 0x20000020
-080005bc :
+080005f0 :
void SystemClock_Config(void);
int main(void)
{
- 80005bc: b580 push {r7, lr}
- 80005be: af00 add r7, sp, #0
+ 80005f0: b580 push {r7, lr}
+ 80005f2: af00 add r7, sp, #0
/* Configure the system clock */
SystemClock_Config();
- 80005c0: f000 f816 bl 80005f0
+ 80005f4: f000 f816 bl 8000624
// config GPIO
GPIO_init();
- 80005c4: f7ff fe9e bl 8000304
+ 80005f8: f7ff fe84 bl 8000304
// init systick timer (tick period at 1 ms)
LL_Init1msTick( SystemCoreClock );
- 80005c8: 4b07 ldr r3, [pc, #28] ; (80005e8 )
- 80005ca: 681b ldr r3, [r3, #0]
- 80005cc: 4618 mov r0, r3
- 80005ce: f000 f99f bl 8000910
+ 80005fc: 4b07 ldr r3, [pc, #28] ; (800061c )
+ 80005fe: 681b ldr r3, [r3, #0]
+ 8000600: 4618 mov r0, r3
+ 8000602: f000 f99f bl 8000944
LL_SYSTICK_EnableIT();
- 80005d2: f7ff ffc5 bl 8000560
+ 8000606: f7ff ffab bl 8000560
+//Setup Sleep mode
+LL_LPM_EnableSleep();
+ 800060a: f7ff ffb9 bl 8000580
+//LL_LPM_EnableSleepOnExit();
while (1) {
- if ( BLUE_BUTTON() ){
- 80005d6: f7ff fec9 bl 800036c
- 80005da: 4603 mov r3, r0
- 80005dc: 2b00 cmp r3, #0
- 80005de: d0fa beq.n 80005d6
- blue_mode = 1;
- 80005e0: 4b02 ldr r3, [pc, #8] ; (80005ec )
- 80005e2: 2201 movs r2, #1
- 80005e4: 701a strb r2, [r3, #0]
- if ( BLUE_BUTTON() ){
- 80005e6: e7f6 b.n 80005d6
- 80005e8: 20000000 .word 0x20000000
- 80005ec: 20000024 .word 0x20000024
+ if (blue_mode){
+ 800060e: 4b04 ldr r3, [pc, #16] ; (8000620 )
+ 8000610: 781b ldrb r3, [r3, #0]
+ 8000612: b2db uxtb r3, r3
+ 8000614: 2b00 cmp r3, #0
+ 8000616: d0fa beq.n 800060e
+ __WFI();
+ 8000618: bf30 wfi
+ if (blue_mode){
+ 800061a: e7f8 b.n 800060e
+ 800061c: 20000000 .word 0x20000000
+ 8000620: 20000024 .word 0x20000024
-080005f0 :
+08000624 :
* PLL_R = 2
* Flash Latency(WS) = 4
* @param None
* @retval None
*/
void SystemClock_Config(void) {
- 80005f0: b580 push {r7, lr}
- 80005f2: af00 add r7, sp, #0
+ 8000624: b580 push {r7, lr}
+ 8000626: af00 add r7, sp, #0
/* MSI configuration and activation */
LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
- 80005f4: 2004 movs r0, #4
- 80005f6: f7ff ff9f bl 8000538
+ 8000628: 2004 movs r0, #4
+ 800062a: f7ff ff85 bl 8000538
LL_RCC_MSI_Enable();
- 80005fa: f7ff fec9 bl 8000390
+ 800062e: f7ff feaf bl 8000390
while (LL_RCC_MSI_IsReady() != 1)
- 80005fe: bf00 nop
- 8000600: f7ff fed6 bl 80003b0
- 8000604: 4603 mov r3, r0
- 8000606: 2b01 cmp r3, #1
- 8000608: d1fa bne.n 8000600
+ 8000632: bf00 nop
+ 8000634: f7ff febc bl 80003b0
+ 8000638: 4603 mov r3, r0
+ 800063a: 2b01 cmp r3, #1
+ 800063c: d1fa bne.n 8000634
{ };
/* Main PLL configuration and activation */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);
- 800060a: 2300 movs r3, #0
- 800060c: 2228 movs r2, #40 ; 0x28
- 800060e: 2100 movs r1, #0
- 8000610: 2001 movs r0, #1
- 8000612: f7ff ff61 bl 80004d8
+ 800063e: 2300 movs r3, #0
+ 8000640: 2228 movs r2, #40 ; 0x28
+ 8000642: 2100 movs r1, #0
+ 8000644: 2001 movs r0, #1
+ 8000646: f7ff ff47 bl 80004d8
LL_RCC_PLL_Enable();
- 8000616: f7ff ff3b bl 8000490
+ 800064a: f7ff ff21 bl 8000490
LL_RCC_PLL_EnableDomain_SYS();
- 800061a: f7ff ff7d bl 8000518
+ 800064e: f7ff ff63 bl 8000518
while(LL_RCC_PLL_IsReady() != 1)
- 800061e: bf00 nop
- 8000620: f7ff ff46 bl 80004b0
- 8000624: 4603 mov r3, r0
- 8000626: 2b01 cmp r3, #1
- 8000628: d1fa bne.n 8000620
+ 8000652: bf00 nop
+ 8000654: f7ff ff2c bl 80004b0
+ 8000658: 4603 mov r3, r0
+ 800065a: 2b01 cmp r3, #1
+ 800065c: d1fa bne.n 8000654
{ };
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
- 800062a: 2000 movs r0, #0
- 800062c: f7ff fef4 bl 8000418
+ 800065e: 2000 movs r0, #0
+ 8000660: f7ff feda bl 8000418
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- 8000630: 2003 movs r0, #3
- 8000632: f7ff fecf bl 80003d4
+ 8000664: 2003 movs r0, #3
+ 8000666: f7ff feb5 bl 80003d4
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- 8000636: bf00 nop
- 8000638: f7ff fee0 bl 80003fc
- 800063c: 4603 mov r3, r0
- 800063e: 2b0c cmp r3, #12
- 8000640: d1fa bne.n 8000638
+ 800066a: bf00 nop
+ 800066c: f7ff fec6 bl 80003fc
+ 8000670: 4603 mov r3, r0
+ 8000672: 2b0c cmp r3, #12
+ 8000674: d1fa bne.n 800066c
{ };
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
- 8000642: 2000 movs r0, #0
- 8000644: f7ff fefc bl 8000440
+ 8000676: 2000 movs r0, #0
+ 8000678: f7ff fee2 bl 8000440
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
- 8000648: 2000 movs r0, #0
- 800064a: f7ff ff0d bl 8000468
+ 800067c: 2000 movs r0, #0
+ 800067e: f7ff fef3 bl 8000468
/* Update the global variable called SystemCoreClock */
SystemCoreClockUpdate();
- 800064e: f000 f861 bl 8000714
+ 8000682: f000 f861 bl 8000748
}
- 8000652: bf00 nop
- 8000654: bd80 pop {r7, pc}
+ 8000686: bf00 nop
+ 8000688: bd80 pop {r7, pc}
-08000656 :
+0800068a :
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
- 8000656: b480 push {r7}
- 8000658: af00 add r7, sp, #0
+ 800068a: b480 push {r7}
+ 800068c: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
- 800065a: bf00 nop
- 800065c: 46bd mov sp, r7
- 800065e: f85d 7b04 ldr.w r7, [sp], #4
- 8000662: 4770 bx lr
+ 800068e: bf00 nop
+ 8000690: 46bd mov sp, r7
+ 8000692: f85d 7b04 ldr.w r7, [sp], #4
+ 8000696: 4770 bx lr
-08000664 :
+08000698 :
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
- 8000664: b480 push {r7}
- 8000666: af00 add r7, sp, #0
+ 8000698: b480 push {r7}
+ 800069a: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
- 8000668: e7fe b.n 8000668
+ 800069c: e7fe b.n 800069c
-0800066a :
+0800069e :
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
- 800066a: b480 push {r7}
- 800066c: af00 add r7, sp, #0
+ 800069e: b480 push {r7}
+ 80006a0: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
- 800066e: e7fe b.n 800066e
+ 80006a2: e7fe b.n 80006a2
-08000670 :
+080006a4 :
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
- 8000670: b480 push {r7}
- 8000672: af00 add r7, sp, #0
+ 80006a4: b480 push {r7}
+ 80006a6: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
- 8000674: e7fe b.n 8000674
+ 80006a8: e7fe b.n 80006a8
-08000676 :
+080006aa :
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
- 8000676: b480 push {r7}
- 8000678: af00 add r7, sp, #0
+ 80006aa: b480 push {r7}
+ 80006ac: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
- 800067a: e7fe b.n 800067a
+ 80006ae: e7fe b.n 80006ae
-0800067c :
+080006b0 :
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
- 800067c: b480 push {r7}
- 800067e: af00 add r7, sp, #0
+ 80006b0: b480 push {r7}
+ 80006b2: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
- 8000680: bf00 nop
- 8000682: 46bd mov sp, r7
- 8000684: f85d 7b04 ldr.w r7, [sp], #4
- 8000688: 4770 bx lr
+ 80006b4: bf00 nop
+ 80006b6: 46bd mov sp, r7
+ 80006b8: f85d 7b04 ldr.w r7, [sp], #4
+ 80006bc: 4770 bx lr
-0800068a :
+080006be :
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
- 800068a: b480 push {r7}
- 800068c: af00 add r7, sp, #0
+ 80006be: b480 push {r7}
+ 80006c0: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
- 800068e: bf00 nop
- 8000690: 46bd mov sp, r7
- 8000692: f85d 7b04 ldr.w r7, [sp], #4
- 8000696: 4770 bx lr
+ 80006c2: bf00 nop
+ 80006c4: 46bd mov sp, r7
+ 80006c6: f85d 7b04 ldr.w r7, [sp], #4
+ 80006ca: 4770 bx lr
-08000698 :
+080006cc :
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
- 8000698: b480 push {r7}
- 800069a: af00 add r7, sp, #0
+ 80006cc: b480 push {r7}
+ 80006ce: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
- 800069c: bf00 nop
- 800069e: 46bd mov sp, r7
- 80006a0: f85d 7b04 ldr.w r7, [sp], #4
- 80006a4: 4770 bx lr
+ 80006d0: bf00 nop
+ 80006d2: 46bd mov sp, r7
+ 80006d4: f85d 7b04 ldr.w r7, [sp], #4
+ 80006d8: 4770 bx lr
...
-080006a8 :
+080006dc :
* @param None
* @retval None
*/
void SystemInit(void)
{
- 80006a8: b480 push {r7}
- 80006aa: af00 add r7, sp, #0
+ 80006dc: b480 push {r7}
+ 80006de: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 80006ac: 4b17 ldr r3, [pc, #92] ; (800070c )
- 80006ae: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80006b2: 4a16 ldr r2, [pc, #88] ; (800070c )
- 80006b4: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 80006b8: f8c2 3088 str.w r3, [r2, #136] ; 0x88
+ 80006e0: 4b17 ldr r3, [pc, #92] ; (8000740 )
+ 80006e2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 80006e6: 4a16 ldr r2, [pc, #88] ; (8000740 )
+ 80006e8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
+ 80006ec: f8c2 3088 str.w r3, [r2, #136] ; 0x88
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC->CR |= RCC_CR_MSION;
- 80006bc: 4b14 ldr r3, [pc, #80] ; (8000710 )
- 80006be: 681b ldr r3, [r3, #0]
- 80006c0: 4a13 ldr r2, [pc, #76] ; (8000710 )
- 80006c2: f043 0301 orr.w r3, r3, #1
- 80006c6: 6013 str r3, [r2, #0]
+ 80006f0: 4b14 ldr r3, [pc, #80] ; (8000744 )
+ 80006f2: 681b ldr r3, [r3, #0]
+ 80006f4: 4a13 ldr r2, [pc, #76] ; (8000744 )
+ 80006f6: f043 0301 orr.w r3, r3, #1
+ 80006fa: 6013 str r3, [r2, #0]
/* Reset CFGR register */
RCC->CFGR = 0x00000000U;
- 80006c8: 4b11 ldr r3, [pc, #68] ; (8000710 )
- 80006ca: 2200 movs r2, #0
- 80006cc: 609a str r2, [r3, #8]
+ 80006fc: 4b11 ldr r3, [pc, #68] ; (8000744 )
+ 80006fe: 2200 movs r2, #0
+ 8000700: 609a str r2, [r3, #8]
/* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC->CR &= 0xEAF6FFFFU;
- 80006ce: 4b10 ldr r3, [pc, #64] ; (8000710 )
- 80006d0: 681b ldr r3, [r3, #0]
- 80006d2: 4a0f ldr r2, [pc, #60] ; (8000710 )
- 80006d4: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
- 80006d8: f423 2310 bic.w r3, r3, #589824 ; 0x90000
- 80006dc: 6013 str r3, [r2, #0]
+ 8000702: 4b10 ldr r3, [pc, #64] ; (8000744 )
+ 8000704: 681b ldr r3, [r3, #0]
+ 8000706: 4a0f ldr r2, [pc, #60] ; (8000744 )
+ 8000708: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
+ 800070c: f423 2310 bic.w r3, r3, #589824 ; 0x90000
+ 8000710: 6013 str r3, [r2, #0]
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00001000U;
- 80006de: 4b0c ldr r3, [pc, #48] ; (8000710 )
- 80006e0: f44f 5280 mov.w r2, #4096 ; 0x1000
- 80006e4: 60da str r2, [r3, #12]
+ 8000712: 4b0c ldr r3, [pc, #48] ; (8000744 )
+ 8000714: f44f 5280 mov.w r2, #4096 ; 0x1000
+ 8000718: 60da str r2, [r3, #12]
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
- 80006e6: 4b0a ldr r3, [pc, #40] ; (8000710 )
- 80006e8: 681b ldr r3, [r3, #0]
- 80006ea: 4a09 ldr r2, [pc, #36] ; (8000710 )
- 80006ec: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80006f0: 6013 str r3, [r2, #0]
+ 800071a: 4b0a ldr r3, [pc, #40] ; (8000744 )
+ 800071c: 681b ldr r3, [r3, #0]
+ 800071e: 4a09 ldr r2, [pc, #36] ; (8000744 )
+ 8000720: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8000724: 6013 str r3, [r2, #0]
/* Disable all interrupts */
RCC->CIER = 0x00000000U;
- 80006f2: 4b07 ldr r3, [pc, #28] ; (8000710 )
- 80006f4: 2200 movs r2, #0
- 80006f6: 619a str r2, [r3, #24]
+ 8000726: 4b07 ldr r3, [pc, #28] ; (8000744 )
+ 8000728: 2200 movs r2, #0
+ 800072a: 619a str r2, [r3, #24]
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 80006f8: 4b04 ldr r3, [pc, #16] ; (800070c )
- 80006fa: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 80006fe: 609a str r2, [r3, #8]
+ 800072c: 4b04 ldr r3, [pc, #16] ; (8000740 )
+ 800072e: f04f 6200 mov.w r2, #134217728 ; 0x8000000
+ 8000732: 609a str r2, [r3, #8]
#endif
}
- 8000700: bf00 nop
- 8000702: 46bd mov sp, r7
- 8000704: f85d 7b04 ldr.w r7, [sp], #4
- 8000708: 4770 bx lr
- 800070a: bf00 nop
- 800070c: e000ed00 .word 0xe000ed00
- 8000710: 40021000 .word 0x40021000
+ 8000734: bf00 nop
+ 8000736: 46bd mov sp, r7
+ 8000738: f85d 7b04 ldr.w r7, [sp], #4
+ 800073c: 4770 bx lr
+ 800073e: bf00 nop
+ 8000740: e000ed00 .word 0xe000ed00
+ 8000744: 40021000 .word 0x40021000
-08000714 :
+08000748 :
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
- 8000714: b480 push {r7}
- 8000716: b087 sub sp, #28
- 8000718: af00 add r7, sp, #0
+ 8000748: b480 push {r7}
+ 800074a: b087 sub sp, #28
+ 800074c: af00 add r7, sp, #0
uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
- 800071a: 2300 movs r3, #0
- 800071c: 60fb str r3, [r7, #12]
- 800071e: 2300 movs r3, #0
- 8000720: 617b str r3, [r7, #20]
- 8000722: 2300 movs r3, #0
- 8000724: 613b str r3, [r7, #16]
- 8000726: 2302 movs r3, #2
- 8000728: 60bb str r3, [r7, #8]
- 800072a: 2300 movs r3, #0
- 800072c: 607b str r3, [r7, #4]
- 800072e: 2302 movs r3, #2
- 8000730: 603b str r3, [r7, #0]
+ 800074e: 2300 movs r3, #0
+ 8000750: 60fb str r3, [r7, #12]
+ 8000752: 2300 movs r3, #0
+ 8000754: 617b str r3, [r7, #20]
+ 8000756: 2300 movs r3, #0
+ 8000758: 613b str r3, [r7, #16]
+ 800075a: 2302 movs r3, #2
+ 800075c: 60bb str r3, [r7, #8]
+ 800075e: 2300 movs r3, #0
+ 8000760: 607b str r3, [r7, #4]
+ 8000762: 2302 movs r3, #2
+ 8000764: 603b str r3, [r7, #0]
/* Get MSI Range frequency--------------------------------------------------*/
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
- 8000732: 4b4f ldr r3, [pc, #316] ; (8000870 )
- 8000734: 681b ldr r3, [r3, #0]
- 8000736: f003 0308 and.w r3, r3, #8
- 800073a: 2b00 cmp r3, #0
- 800073c: d107 bne.n 800074e
+ 8000766: 4b4f ldr r3, [pc, #316] ; (80008a4 )
+ 8000768: 681b ldr r3, [r3, #0]
+ 800076a: f003 0308 and.w r3, r3, #8
+ 800076e: 2b00 cmp r3, #0
+ 8000770: d107 bne.n 8000782
{ /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
- 800073e: 4b4c ldr r3, [pc, #304] ; (8000870 )
- 8000740: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
- 8000744: 0a1b lsrs r3, r3, #8
- 8000746: f003 030f and.w r3, r3, #15
- 800074a: 617b str r3, [r7, #20]
- 800074c: e005 b.n 800075a
+ 8000772: 4b4c ldr r3, [pc, #304] ; (80008a4 )
+ 8000774: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
+ 8000778: 0a1b lsrs r3, r3, #8
+ 800077a: f003 030f and.w r3, r3, #15
+ 800077e: 617b str r3, [r7, #20]
+ 8000780: e005 b.n 800078e
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
- 800074e: 4b48 ldr r3, [pc, #288] ; (8000870 )
- 8000750: 681b ldr r3, [r3, #0]
- 8000752: 091b lsrs r3, r3, #4
- 8000754: f003 030f and.w r3, r3, #15
- 8000758: 617b str r3, [r7, #20]
+ 8000782: 4b48 ldr r3, [pc, #288] ; (80008a4 )
+ 8000784: 681b ldr r3, [r3, #0]
+ 8000786: 091b lsrs r3, r3, #4
+ 8000788: f003 030f and.w r3, r3, #15
+ 800078c: 617b str r3, [r7, #20]
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
- 800075a: 4a46 ldr r2, [pc, #280] ; (8000874 )
- 800075c: 697b ldr r3, [r7, #20]
- 800075e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 8000762: 617b str r3, [r7, #20]
+ 800078e: 4a46 ldr r2, [pc, #280] ; (80008a8 )
+ 8000790: 697b ldr r3, [r7, #20]
+ 8000792: f852 3023 ldr.w r3, [r2, r3, lsl #2]
+ 8000796: 617b str r3, [r7, #20]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
- 8000764: 4b42 ldr r3, [pc, #264] ; (8000870 )
- 8000766: 689b ldr r3, [r3, #8]
- 8000768: f003 030c and.w r3, r3, #12
- 800076c: 2b0c cmp r3, #12
- 800076e: d865 bhi.n 800083c
- 8000770: a201 add r2, pc, #4 ; (adr r2, 8000778 )
- 8000772: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8000776: bf00 nop
- 8000778: 080007ad .word 0x080007ad
- 800077c: 0800083d .word 0x0800083d
- 8000780: 0800083d .word 0x0800083d
- 8000784: 0800083d .word 0x0800083d
- 8000788: 080007b5 .word 0x080007b5
- 800078c: 0800083d .word 0x0800083d
- 8000790: 0800083d .word 0x0800083d
- 8000794: 0800083d .word 0x0800083d
- 8000798: 080007bd .word 0x080007bd
- 800079c: 0800083d .word 0x0800083d
- 80007a0: 0800083d .word 0x0800083d
- 80007a4: 0800083d .word 0x0800083d
- 80007a8: 080007c5 .word 0x080007c5
+ 8000798: 4b42 ldr r3, [pc, #264] ; (80008a4 )
+ 800079a: 689b ldr r3, [r3, #8]
+ 800079c: f003 030c and.w r3, r3, #12
+ 80007a0: 2b0c cmp r3, #12
+ 80007a2: d865 bhi.n 8000870
+ 80007a4: a201 add r2, pc, #4 ; (adr r2, 80007ac )
+ 80007a6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 80007aa: bf00 nop
+ 80007ac: 080007e1 .word 0x080007e1
+ 80007b0: 08000871 .word 0x08000871
+ 80007b4: 08000871 .word 0x08000871
+ 80007b8: 08000871 .word 0x08000871
+ 80007bc: 080007e9 .word 0x080007e9
+ 80007c0: 08000871 .word 0x08000871
+ 80007c4: 08000871 .word 0x08000871
+ 80007c8: 08000871 .word 0x08000871
+ 80007cc: 080007f1 .word 0x080007f1
+ 80007d0: 08000871 .word 0x08000871
+ 80007d4: 08000871 .word 0x08000871
+ 80007d8: 08000871 .word 0x08000871
+ 80007dc: 080007f9 .word 0x080007f9
{
case 0x00: /* MSI used as system clock source */
SystemCoreClock = msirange;
- 80007ac: 4a32 ldr r2, [pc, #200] ; (8000878 )
- 80007ae: 697b ldr r3, [r7, #20]
- 80007b0: 6013 str r3, [r2, #0]
+ 80007e0: 4a32 ldr r2, [pc, #200] ; (80008ac )
+ 80007e2: 697b ldr r3, [r7, #20]
+ 80007e4: 6013 str r3, [r2, #0]
break;
- 80007b2: e047 b.n 8000844
+ 80007e6: e047 b.n 8000878
case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
- 80007b4: 4b30 ldr r3, [pc, #192] ; (8000878 )
- 80007b6: 4a31 ldr r2, [pc, #196] ; (800087c )
- 80007b8: 601a str r2, [r3, #0]
+ 80007e8: 4b30 ldr r3, [pc, #192] ; (80008ac )
+ 80007ea: 4a31 ldr r2, [pc, #196] ; (80008b0 )
+ 80007ec: 601a str r2, [r3, #0]
break;
- 80007ba: e043 b.n 8000844
+ 80007ee: e043 b.n 8000878
case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
- 80007bc: 4b2e ldr r3, [pc, #184] ; (8000878 )
- 80007be: 4a30 ldr r2, [pc, #192] ; (8000880 )
- 80007c0: 601a str r2, [r3, #0]
+ 80007f0: 4b2e ldr r3, [pc, #184] ; (80008ac )
+ 80007f2: 4a30 ldr r2, [pc, #192] ; (80008b4 )
+ 80007f4: 601a str r2, [r3, #0]
break;
- 80007c2: e03f b.n 8000844
+ 80007f6: e03f b.n 8000878
case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
- 80007c4: 4b2a ldr r3, [pc, #168] ; (8000870 )
- 80007c6: 68db ldr r3, [r3, #12]
- 80007c8: f003 0303 and.w r3, r3, #3
- 80007cc: 607b str r3, [r7, #4]
+ 80007f8: 4b2a ldr r3, [pc, #168] ; (80008a4 )
+ 80007fa: 68db ldr r3, [r3, #12]
+ 80007fc: f003 0303 and.w r3, r3, #3
+ 8000800: 607b str r3, [r7, #4]
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
- 80007ce: 4b28 ldr r3, [pc, #160] ; (8000870 )
- 80007d0: 68db ldr r3, [r3, #12]
- 80007d2: 091b lsrs r3, r3, #4
- 80007d4: f003 0307 and.w r3, r3, #7
- 80007d8: 3301 adds r3, #1
- 80007da: 603b str r3, [r7, #0]
+ 8000802: 4b28 ldr r3, [pc, #160] ; (80008a4 )
+ 8000804: 68db ldr r3, [r3, #12]
+ 8000806: 091b lsrs r3, r3, #4
+ 8000808: f003 0307 and.w r3, r3, #7
+ 800080c: 3301 adds r3, #1
+ 800080e: 603b str r3, [r7, #0]
switch (pllsource)
- 80007dc: 687b ldr r3, [r7, #4]
- 80007de: 2b02 cmp r3, #2
- 80007e0: d002 beq.n 80007e8
- 80007e2: 2b03 cmp r3, #3
- 80007e4: d006 beq.n 80007f4
- 80007e6: e00b b.n 8000800
+ 8000810: 687b ldr r3, [r7, #4]
+ 8000812: 2b02 cmp r3, #2
+ 8000814: d002 beq.n 800081c
+ 8000816: 2b03 cmp r3, #3
+ 8000818: d006 beq.n 8000828
+ 800081a: e00b b.n 8000834
{
case 0x02: /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm);
- 80007e8: 4a24 ldr r2, [pc, #144] ; (800087c )
- 80007ea: 683b ldr r3, [r7, #0]
- 80007ec: fbb2 f3f3 udiv r3, r2, r3
- 80007f0: 613b str r3, [r7, #16]
+ 800081c: 4a24 ldr r2, [pc, #144] ; (80008b0 )
+ 800081e: 683b ldr r3, [r7, #0]
+ 8000820: fbb2 f3f3 udiv r3, r2, r3
+ 8000824: 613b str r3, [r7, #16]
break;
- 80007f2: e00b b.n 800080c
+ 8000826: e00b b.n 8000840
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
- 80007f4: 4a22 ldr r2, [pc, #136] ; (8000880 )
- 80007f6: 683b ldr r3, [r7, #0]
- 80007f8: fbb2 f3f3 udiv r3, r2, r3
- 80007fc: 613b str r3, [r7, #16]
+ 8000828: 4a22 ldr r2, [pc, #136] ; (80008b4 )
+ 800082a: 683b ldr r3, [r7, #0]
+ 800082c: fbb2 f3f3 udiv r3, r2, r3
+ 8000830: 613b str r3, [r7, #16]
break;
- 80007fe: e005 b.n 800080c
+ 8000832: e005 b.n 8000840
default: /* MSI used as PLL clock source */
pllvco = (msirange / pllm);
- 8000800: 697a ldr r2, [r7, #20]
- 8000802: 683b ldr r3, [r7, #0]
- 8000804: fbb2 f3f3 udiv r3, r2, r3
- 8000808: 613b str r3, [r7, #16]
+ 8000834: 697a ldr r2, [r7, #20]
+ 8000836: 683b ldr r3, [r7, #0]
+ 8000838: fbb2 f3f3 udiv r3, r2, r3
+ 800083c: 613b str r3, [r7, #16]
break;
- 800080a: bf00 nop
+ 800083e: bf00 nop
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
- 800080c: 4b18 ldr r3, [pc, #96] ; (8000870 )
- 800080e: 68db ldr r3, [r3, #12]
- 8000810: 0a1b lsrs r3, r3, #8
- 8000812: f003 027f and.w r2, r3, #127 ; 0x7f
- 8000816: 693b ldr r3, [r7, #16]
- 8000818: fb02 f303 mul.w r3, r2, r3
- 800081c: 613b str r3, [r7, #16]
+ 8000840: 4b18 ldr r3, [pc, #96] ; (80008a4 )
+ 8000842: 68db ldr r3, [r3, #12]
+ 8000844: 0a1b lsrs r3, r3, #8
+ 8000846: f003 027f and.w r2, r3, #127 ; 0x7f
+ 800084a: 693b ldr r3, [r7, #16]
+ 800084c: fb02 f303 mul.w r3, r2, r3
+ 8000850: 613b str r3, [r7, #16]
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
- 800081e: 4b14 ldr r3, [pc, #80] ; (8000870 )
- 8000820: 68db ldr r3, [r3, #12]
- 8000822: 0e5b lsrs r3, r3, #25
- 8000824: f003 0303 and.w r3, r3, #3
- 8000828: 3301 adds r3, #1
- 800082a: 005b lsls r3, r3, #1
- 800082c: 60bb str r3, [r7, #8]
+ 8000852: 4b14 ldr r3, [pc, #80] ; (80008a4 )
+ 8000854: 68db ldr r3, [r3, #12]
+ 8000856: 0e5b lsrs r3, r3, #25
+ 8000858: f003 0303 and.w r3, r3, #3
+ 800085c: 3301 adds r3, #1
+ 800085e: 005b lsls r3, r3, #1
+ 8000860: 60bb str r3, [r7, #8]
SystemCoreClock = pllvco/pllr;
- 800082e: 693a ldr r2, [r7, #16]
- 8000830: 68bb ldr r3, [r7, #8]
- 8000832: fbb2 f3f3 udiv r3, r2, r3
- 8000836: 4a10 ldr r2, [pc, #64] ; (8000878 )
- 8000838: 6013 str r3, [r2, #0]
+ 8000862: 693a ldr r2, [r7, #16]
+ 8000864: 68bb ldr r3, [r7, #8]
+ 8000866: fbb2 f3f3 udiv r3, r2, r3
+ 800086a: 4a10 ldr r2, [pc, #64] ; (80008ac )
+ 800086c: 6013 str r3, [r2, #0]
break;
- 800083a: e003 b.n 8000844
+ 800086e: e003 b.n 8000878
default:
SystemCoreClock = msirange;
- 800083c: 4a0e ldr r2, [pc, #56] ; (8000878 )
- 800083e: 697b ldr r3, [r7, #20]
- 8000840: 6013 str r3, [r2, #0]
+ 8000870: 4a0e ldr r2, [pc, #56] ; (80008ac )
+ 8000872: 697b ldr r3, [r7, #20]
+ 8000874: 6013 str r3, [r2, #0]
break;
- 8000842: bf00 nop
+ 8000876: bf00 nop
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
- 8000844: 4b0a ldr r3, [pc, #40] ; (8000870 )
- 8000846: 689b ldr r3, [r3, #8]
- 8000848: 091b lsrs r3, r3, #4
- 800084a: f003 030f and.w r3, r3, #15
- 800084e: 4a0d ldr r2, [pc, #52] ; (8000884 )
- 8000850: 5cd3 ldrb r3, [r2, r3]
- 8000852: 60fb str r3, [r7, #12]
+ 8000878: 4b0a ldr r3, [pc, #40] ; (80008a4 )
+ 800087a: 689b ldr r3, [r3, #8]
+ 800087c: 091b lsrs r3, r3, #4
+ 800087e: f003 030f and.w r3, r3, #15
+ 8000882: 4a0d ldr r2, [pc, #52] ; (80008b8 )
+ 8000884: 5cd3 ldrb r3, [r2, r3]
+ 8000886: 60fb str r3, [r7, #12]
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
- 8000854: 4b08 ldr r3, [pc, #32] ; (8000878 )
- 8000856: 681a ldr r2, [r3, #0]
- 8000858: 68fb ldr r3, [r7, #12]
- 800085a: fa22 f303 lsr.w r3, r2, r3
- 800085e: 4a06 ldr r2, [pc, #24] ; (8000878 )
- 8000860: 6013 str r3, [r2, #0]
+ 8000888: 4b08 ldr r3, [pc, #32] ; (80008ac )
+ 800088a: 681a ldr r2, [r3, #0]
+ 800088c: 68fb ldr r3, [r7, #12]
+ 800088e: fa22 f303 lsr.w r3, r2, r3
+ 8000892: 4a06 ldr r2, [pc, #24] ; (80008ac )
+ 8000894: 6013 str r3, [r2, #0]
}
- 8000862: bf00 nop
- 8000864: 371c adds r7, #28
- 8000866: 46bd mov sp, r7
- 8000868: f85d 7b04 ldr.w r7, [sp], #4
- 800086c: 4770 bx lr
- 800086e: bf00 nop
- 8000870: 40021000 .word 0x40021000
- 8000874: 0800099c .word 0x0800099c
- 8000878: 20000000 .word 0x20000000
- 800087c: 00f42400 .word 0x00f42400
- 8000880: 007a1200 .word 0x007a1200
- 8000884: 0800098c .word 0x0800098c
+ 8000896: bf00 nop
+ 8000898: 371c adds r7, #28
+ 800089a: 46bd mov sp, r7
+ 800089c: f85d 7b04 ldr.w r7, [sp], #4
+ 80008a0: 4770 bx lr
+ 80008a2: bf00 nop
+ 80008a4: 40021000 .word 0x40021000
+ 80008a8: 080009cc .word 0x080009cc
+ 80008ac: 20000000 .word 0x20000000
+ 80008b0: 00f42400 .word 0x00f42400
+ 80008b4: 007a1200 .word 0x007a1200
+ 80008b8: 080009bc .word 0x080009bc
-08000888 :
+080008bc :
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
- 8000888: f8df d034 ldr.w sp, [pc, #52] ; 80008c0
+ 80008bc: f8df d034 ldr.w sp, [pc, #52] ; 80008f4
/* Call the clock system initialization function.*/
bl SystemInit
- 800088c: f7ff ff0c bl 80006a8
+ 80008c0: f7ff ff0c bl 80006dc
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
- 8000890: 2100 movs r1, #0
+ 80008c4: 2100 movs r1, #0
b LoopCopyDataInit
- 8000892: e003 b.n 800089c
+ 80008c6: e003 b.n 80008d0
-08000894 :
+080008c8 :
CopyDataInit:
ldr r3, =_sidata
- 8000894: 4b0b ldr r3, [pc, #44] ; (80008c4 )
+ 80008c8: 4b0b ldr r3, [pc, #44] ; (80008f8 )
ldr r3, [r3, r1]
- 8000896: 585b ldr r3, [r3, r1]
+ 80008ca: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
- 8000898: 5043 str r3, [r0, r1]
+ 80008cc: 5043 str r3, [r0, r1]
adds r1, r1, #4
- 800089a: 3104 adds r1, #4
+ 80008ce: 3104 adds r1, #4
-0800089c :
+080008d0 :
LoopCopyDataInit:
ldr r0, =_sdata
- 800089c: 480a ldr r0, [pc, #40] ; (80008c8 )
+ 80008d0: 480a ldr r0, [pc, #40] ; (80008fc )
ldr r3, =_edata
- 800089e: 4b0b ldr r3, [pc, #44] ; (80008cc )
+ 80008d2: 4b0b ldr r3, [pc, #44] ; (8000900 )
adds r2, r0, r1
- 80008a0: 1842 adds r2, r0, r1
+ 80008d4: 1842 adds r2, r0, r1
cmp r2, r3
- 80008a2: 429a cmp r2, r3
+ 80008d6: 429a cmp r2, r3
bcc CopyDataInit
- 80008a4: d3f6 bcc.n 8000894
+ 80008d8: d3f6 bcc.n 80008c8
ldr r2, =_sbss
- 80008a6: 4a0a ldr r2, [pc, #40] ; (80008d0 )
+ 80008da: 4a0a ldr r2, [pc, #40] ; (8000904 )
b LoopFillZerobss
- 80008a8: e002 b.n 80008b0
+ 80008dc: e002 b.n 80008e4
-080008aa :
+080008de :
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
- 80008aa: 2300 movs r3, #0
+ 80008de: 2300 movs r3, #0
str r3, [r2], #4
- 80008ac: f842 3b04 str.w r3, [r2], #4
+ 80008e0: f842 3b04 str.w r3, [r2], #4
-080008b0 :
+080008e4 :
LoopFillZerobss:
ldr r3, = _ebss
- 80008b0: 4b08 ldr r3, [pc, #32] ; (80008d4 )
+ 80008e4: 4b08 ldr r3, [pc, #32] ; (8000908 )
cmp r2, r3
- 80008b2: 429a cmp r2, r3
+ 80008e6: 429a cmp r2, r3
bcc FillZerobss
- 80008b4: d3f9 bcc.n 80008aa
+ 80008e8: d3f9 bcc.n 80008de
/* Call static constructors */
bl __libc_init_array
- 80008b6: f000 f839 bl 800092c <__libc_init_array>
+ 80008ea: f000 f837 bl 800095c <__libc_init_array>
/* Call the application's entry point.*/
bl main
- 80008ba: f7ff fe7f bl 80005bc
+ 80008ee: f7ff fe7f bl 80005f0
-080008be :
+080008f2 :
LoopForever:
b LoopForever
- 80008be: e7fe b.n 80008be
+ 80008f2: e7fe b.n 80008f2
ldr sp, =_estack /* Set stack pointer */
- 80008c0: 20018000 .word 0x20018000
+ 80008f4: 20018000 .word 0x20018000
ldr r3, =_sidata
- 80008c4: 080009d4 .word 0x080009d4
+ 80008f8: 08000a04 .word 0x08000a04
ldr r0, =_sdata
- 80008c8: 20000000 .word 0x20000000
+ 80008fc: 20000000 .word 0x20000000
ldr r3, =_edata
- 80008cc: 20000004 .word 0x20000004
+ 8000900: 20000004 .word 0x20000004
ldr r2, =_sbss
- 80008d0: 20000004 .word 0x20000004
+ 8000904: 20000004 .word 0x20000004
ldr r3, = _ebss
- 80008d4: 20000028 .word 0x20000028
+ 8000908: 20000028 .word 0x20000028
-080008d8 :
+0800090c :
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- 80008d8: e7fe b.n 80008d8
+ 800090c: e7fe b.n 800090c
...
-080008dc :
+08000910 :
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
- 80008dc: b480 push {r7}
- 80008de: b083 sub sp, #12
- 80008e0: af00 add r7, sp, #0
- 80008e2: 6078 str r0, [r7, #4]
- 80008e4: 6039 str r1, [r7, #0]
+ 8000910: b480 push {r7}
+ 8000912: b083 sub sp, #12
+ 8000914: af00 add r7, sp, #0
+ 8000916: 6078 str r0, [r7, #4]
+ 8000918: 6039 str r1, [r7, #0]
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- 80008e6: 687a ldr r2, [r7, #4]
- 80008e8: 683b ldr r3, [r7, #0]
- 80008ea: fbb2 f3f3 udiv r3, r2, r3
- 80008ee: 4a07 ldr r2, [pc, #28] ; (800090c )
- 80008f0: 3b01 subs r3, #1
- 80008f2: 6053 str r3, [r2, #4]
+ 800091a: 687a ldr r2, [r7, #4]
+ 800091c: 683b ldr r3, [r7, #0]
+ 800091e: fbb2 f3f3 udiv r3, r2, r3
+ 8000922: 4a07 ldr r2, [pc, #28] ; (8000940 )
+ 8000924: 3b01 subs r3, #1
+ 8000926: 6053 str r3, [r2, #4]
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 80008f4: 4b05 ldr r3, [pc, #20] ; (800090c )
- 80008f6: 2200 movs r2, #0
- 80008f8: 609a str r2, [r3, #8]
+ 8000928: 4b05 ldr r3, [pc, #20] ; (8000940