
RealOne.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000188  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00001208  08000188  08000188  00010188  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000000  08001390  08001390  0002000c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  3 .ARM.extab    00000000  08001390  08001390  0002000c  2**0
                  CONTENTS
  4 .ARM          00000000  08001390  08001390  0002000c  2**0
                  CONTENTS
  5 .preinit_array 00000000  08001390  08001390  0002000c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08001390  08001390  00011390  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  08001394  08001394  00011394  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         0000000c  20000000  08001398  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000024  2000000c  080013a4  0002000c  2**2
                  ALLOC
 10 ._user_heap_stack 00000600  20000030  080013a4  00020030  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  0002000c  2**0
                  CONTENTS, READONLY
 12 .debug_info   00005321  00000000  00000000  0002003c  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_abbrev 00000e11  00000000  00000000  0002535d  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_aranges 00000668  00000000  00000000  00026170  2**3
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_ranges 000005f0  00000000  00000000  000267d8  2**3
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_macro  0002682e  00000000  00000000  00026dc8  2**0
                  CONTENTS, READONLY, DEBUGGING
 17 .debug_line   00004387  00000000  00000000  0004d5f6  2**0
                  CONTENTS, READONLY, DEBUGGING
 18 .debug_str    000f056b  00000000  00000000  0005197d  2**0
                  CONTENTS, READONLY, DEBUGGING
 19 .comment      0000007b  00000000  00000000  00141ee8  2**0
                  CONTENTS, READONLY
 20 .debug_frame  000018fc  00000000  00000000  00141f64  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

08000188 <__do_global_dtors_aux>:
 8000188:	b510      	push	{r4, lr}
 800018a:	4c05      	ldr	r4, [pc, #20]	; (80001a0 <__do_global_dtors_aux+0x18>)
 800018c:	7823      	ldrb	r3, [r4, #0]
 800018e:	b933      	cbnz	r3, 800019e <__do_global_dtors_aux+0x16>
 8000190:	4b04      	ldr	r3, [pc, #16]	; (80001a4 <__do_global_dtors_aux+0x1c>)
 8000192:	b113      	cbz	r3, 800019a <__do_global_dtors_aux+0x12>
 8000194:	4804      	ldr	r0, [pc, #16]	; (80001a8 <__do_global_dtors_aux+0x20>)
 8000196:	f3af 8000 	nop.w
 800019a:	2301      	movs	r3, #1
 800019c:	7023      	strb	r3, [r4, #0]
 800019e:	bd10      	pop	{r4, pc}
 80001a0:	2000000c 	.word	0x2000000c
 80001a4:	00000000 	.word	0x00000000
 80001a8:	08001378 	.word	0x08001378

080001ac <frame_dummy>:
 80001ac:	b508      	push	{r3, lr}
 80001ae:	4b03      	ldr	r3, [pc, #12]	; (80001bc <frame_dummy+0x10>)
 80001b0:	b11b      	cbz	r3, 80001ba <frame_dummy+0xe>
 80001b2:	4903      	ldr	r1, [pc, #12]	; (80001c0 <frame_dummy+0x14>)
 80001b4:	4803      	ldr	r0, [pc, #12]	; (80001c4 <frame_dummy+0x18>)
 80001b6:	f3af 8000 	nop.w
 80001ba:	bd08      	pop	{r3, pc}
 80001bc:	00000000 	.word	0x00000000
 80001c0:	20000010 	.word	0x20000010
 80001c4:	08001378 	.word	0x08001378

080001c8 <LL_AHB2_GRP1_EnableClock>:
  *
  *         (*) value not defined in all devices.
  * @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
 80001c8:	b480      	push	{r7}
 80001ca:	b085      	sub	sp, #20
 80001cc:	af00      	add	r7, sp, #0
 80001ce:	6078      	str	r0, [r7, #4]
  __IO uint32_t tmpreg;
  SET_BIT(RCC->AHB2ENR, Periphs);
 80001d0:	4b08      	ldr	r3, [pc, #32]	; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
 80001d2:	6cda      	ldr	r2, [r3, #76]	; 0x4c
 80001d4:	4907      	ldr	r1, [pc, #28]	; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
 80001d6:	687b      	ldr	r3, [r7, #4]
 80001d8:	4313      	orrs	r3, r2
 80001da:	64cb      	str	r3, [r1, #76]	; 0x4c
  /* Delay after an RCC peripheral clock enabling */
  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
 80001dc:	4b05      	ldr	r3, [pc, #20]	; (80001f4 <LL_AHB2_GRP1_EnableClock+0x2c>)
 80001de:	6cda      	ldr	r2, [r3, #76]	; 0x4c
 80001e0:	687b      	ldr	r3, [r7, #4]
 80001e2:	4013      	ands	r3, r2
 80001e4:	60fb      	str	r3, [r7, #12]
  (void)tmpreg;
 80001e6:	68fb      	ldr	r3, [r7, #12]
}
 80001e8:	bf00      	nop
 80001ea:	3714      	adds	r7, #20
 80001ec:	46bd      	mov	sp, r7
 80001ee:	f85d 7b04 	ldr.w	r7, [sp], #4
 80001f2:	4770      	bx	lr
 80001f4:	40021000 	.word	0x40021000

080001f8 <LL_GPIO_SetPinMode>:
  *         @arg @ref LL_GPIO_MODE_ALTERNATE
  *         @arg @ref LL_GPIO_MODE_ANALOG
  * @retval None
  */
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
 80001f8:	b480      	push	{r7}
 80001fa:	b08b      	sub	sp, #44	; 0x2c
 80001fc:	af00      	add	r7, sp, #0
 80001fe:	60f8      	str	r0, [r7, #12]
 8000200:	60b9      	str	r1, [r7, #8]
 8000202:	607a      	str	r2, [r7, #4]
  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
 8000204:	68fb      	ldr	r3, [r7, #12]
 8000206:	681a      	ldr	r2, [r3, #0]
 8000208:	68bb      	ldr	r3, [r7, #8]
 800020a:	617b      	str	r3, [r7, #20]
  uint32_t result;

#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800020c:	697b      	ldr	r3, [r7, #20]
 800020e:	fa93 f3a3 	rbit	r3, r3
 8000212:	613b      	str	r3, [r7, #16]
    result |= value & 1U;
    s--;
  }
  result <<= s;                        /* shift when v's highest bits are zero */
#endif
  return result;
 8000214:	693b      	ldr	r3, [r7, #16]
 8000216:	61bb      	str	r3, [r7, #24]
     optimisations using the logic "value was passed to __builtin_clz, so it
     is non-zero".
     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
     single CLZ instruction.
   */
  if (value == 0U)
 8000218:	69bb      	ldr	r3, [r7, #24]
 800021a:	2b00      	cmp	r3, #0
 800021c:	d101      	bne.n	8000222 <LL_GPIO_SetPinMode+0x2a>
  {
    return 32U;
 800021e:	2320      	movs	r3, #32
 8000220:	e003      	b.n	800022a <LL_GPIO_SetPinMode+0x32>
  }
  return __builtin_clz(value);
 8000222:	69bb      	ldr	r3, [r7, #24]
 8000224:	fab3 f383 	clz	r3, r3
 8000228:	b2db      	uxtb	r3, r3
 800022a:	005b      	lsls	r3, r3, #1
 800022c:	2103      	movs	r1, #3
 800022e:	fa01 f303 	lsl.w	r3, r1, r3
 8000232:	43db      	mvns	r3, r3
 8000234:	401a      	ands	r2, r3
 8000236:	68bb      	ldr	r3, [r7, #8]
 8000238:	623b      	str	r3, [r7, #32]
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800023a:	6a3b      	ldr	r3, [r7, #32]
 800023c:	fa93 f3a3 	rbit	r3, r3
 8000240:	61fb      	str	r3, [r7, #28]
  return result;
 8000242:	69fb      	ldr	r3, [r7, #28]
 8000244:	627b      	str	r3, [r7, #36]	; 0x24
  if (value == 0U)
 8000246:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8000248:	2b00      	cmp	r3, #0
 800024a:	d101      	bne.n	8000250 <LL_GPIO_SetPinMode+0x58>
    return 32U;
 800024c:	2320      	movs	r3, #32
 800024e:	e003      	b.n	8000258 <LL_GPIO_SetPinMode+0x60>
  return __builtin_clz(value);
 8000250:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8000252:	fab3 f383 	clz	r3, r3
 8000256:	b2db      	uxtb	r3, r3
 8000258:	005b      	lsls	r3, r3, #1
 800025a:	6879      	ldr	r1, [r7, #4]
 800025c:	fa01 f303 	lsl.w	r3, r1, r3
 8000260:	431a      	orrs	r2, r3
 8000262:	68fb      	ldr	r3, [r7, #12]
 8000264:	601a      	str	r2, [r3, #0]
}
 8000266:	bf00      	nop
 8000268:	372c      	adds	r7, #44	; 0x2c
 800026a:	46bd      	mov	sp, r7
 800026c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000270:	4770      	bx	lr

08000272 <LL_GPIO_SetPinOutputType>:
  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
  * @retval None
  */
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
 8000272:	b480      	push	{r7}
 8000274:	b085      	sub	sp, #20
 8000276:	af00      	add	r7, sp, #0
 8000278:	60f8      	str	r0, [r7, #12]
 800027a:	60b9      	str	r1, [r7, #8]
 800027c:	607a      	str	r2, [r7, #4]
  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
 800027e:	68fb      	ldr	r3, [r7, #12]
 8000280:	685a      	ldr	r2, [r3, #4]
 8000282:	68bb      	ldr	r3, [r7, #8]
 8000284:	43db      	mvns	r3, r3
 8000286:	401a      	ands	r2, r3
 8000288:	68bb      	ldr	r3, [r7, #8]
 800028a:	6879      	ldr	r1, [r7, #4]
 800028c:	fb01 f303 	mul.w	r3, r1, r3
 8000290:	431a      	orrs	r2, r3
 8000292:	68fb      	ldr	r3, [r7, #12]
 8000294:	605a      	str	r2, [r3, #4]
}
 8000296:	bf00      	nop
 8000298:	3714      	adds	r7, #20
 800029a:	46bd      	mov	sp, r7
 800029c:	f85d 7b04 	ldr.w	r7, [sp], #4
 80002a0:	4770      	bx	lr

080002a2 <LL_GPIO_IsInputPinSet>:
  *         @arg @ref LL_GPIO_PIN_15
  *         @arg @ref LL_GPIO_PIN_ALL
  * @retval State of bit (1 or 0).
  */
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
 80002a2:	b480      	push	{r7}
 80002a4:	b083      	sub	sp, #12
 80002a6:	af00      	add	r7, sp, #0
 80002a8:	6078      	str	r0, [r7, #4]
 80002aa:	6039      	str	r1, [r7, #0]
  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
 80002ac:	687b      	ldr	r3, [r7, #4]
 80002ae:	691a      	ldr	r2, [r3, #16]
 80002b0:	683b      	ldr	r3, [r7, #0]
 80002b2:	4013      	ands	r3, r2
 80002b4:	683a      	ldr	r2, [r7, #0]
 80002b6:	429a      	cmp	r2, r3
 80002b8:	d101      	bne.n	80002be <LL_GPIO_IsInputPinSet+0x1c>
 80002ba:	2301      	movs	r3, #1
 80002bc:	e000      	b.n	80002c0 <LL_GPIO_IsInputPinSet+0x1e>
 80002be:	2300      	movs	r3, #0
}
 80002c0:	4618      	mov	r0, r3
 80002c2:	370c      	adds	r7, #12
 80002c4:	46bd      	mov	sp, r7
 80002c6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80002ca:	4770      	bx	lr

080002cc <LL_GPIO_SetOutputPin>:
  *         @arg @ref LL_GPIO_PIN_15
  *         @arg @ref LL_GPIO_PIN_ALL
  * @retval None
  */
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
 80002cc:	b480      	push	{r7}
 80002ce:	b083      	sub	sp, #12
 80002d0:	af00      	add	r7, sp, #0
 80002d2:	6078      	str	r0, [r7, #4]
 80002d4:	6039      	str	r1, [r7, #0]
  WRITE_REG(GPIOx->BSRR, PinMask);
 80002d6:	687b      	ldr	r3, [r7, #4]
 80002d8:	683a      	ldr	r2, [r7, #0]
 80002da:	619a      	str	r2, [r3, #24]
}
 80002dc:	bf00      	nop
 80002de:	370c      	adds	r7, #12
 80002e0:	46bd      	mov	sp, r7
 80002e2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80002e6:	4770      	bx	lr

080002e8 <LL_GPIO_ResetOutputPin>:
  *         @arg @ref LL_GPIO_PIN_15
  *         @arg @ref LL_GPIO_PIN_ALL
  * @retval None
  */
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
 80002e8:	b480      	push	{r7}
 80002ea:	b083      	sub	sp, #12
 80002ec:	af00      	add	r7, sp, #0
 80002ee:	6078      	str	r0, [r7, #4]
 80002f0:	6039      	str	r1, [r7, #0]
  WRITE_REG(GPIOx->BRR, PinMask);
 80002f2:	687b      	ldr	r3, [r7, #4]
 80002f4:	683a      	ldr	r2, [r7, #0]
 80002f6:	629a      	str	r2, [r3, #40]	; 0x28
}
 80002f8:	bf00      	nop
 80002fa:	370c      	adds	r7, #12
 80002fc:	46bd      	mov	sp, r7
 80002fe:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000302:	4770      	bx	lr

08000304 <LL_GPIO_TogglePin>:
  *         @arg @ref LL_GPIO_PIN_15
  *         @arg @ref LL_GPIO_PIN_ALL
  * @retval None
  */
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
 8000304:	b480      	push	{r7}
 8000306:	b085      	sub	sp, #20
 8000308:	af00      	add	r7, sp, #0
 800030a:	6078      	str	r0, [r7, #4]
 800030c:	6039      	str	r1, [r7, #0]
  uint32_t odr = READ_REG(GPIOx->ODR);
 800030e:	687b      	ldr	r3, [r7, #4]
 8000310:	695b      	ldr	r3, [r3, #20]
 8000312:	60fb      	str	r3, [r7, #12]
  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
 8000314:	68fa      	ldr	r2, [r7, #12]
 8000316:	683b      	ldr	r3, [r7, #0]
 8000318:	4013      	ands	r3, r2
 800031a:	041a      	lsls	r2, r3, #16
 800031c:	68fb      	ldr	r3, [r7, #12]
 800031e:	43d9      	mvns	r1, r3
 8000320:	683b      	ldr	r3, [r7, #0]
 8000322:	400b      	ands	r3, r1
 8000324:	431a      	orrs	r2, r3
 8000326:	687b      	ldr	r3, [r7, #4]
 8000328:	619a      	str	r2, [r3, #24]
}
 800032a:	bf00      	nop
 800032c:	3714      	adds	r7, #20
 800032e:	46bd      	mov	sp, r7
 8000330:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000334:	4770      	bx	lr
	...

08000338 <GPIO_init>:
#define BUT_PORT GPIOC
#define BUT_PIN LL_GPIO_PIN_13
#define CLK_PIN LL_GPIO_PIN_10

void GPIO_init(void)
{
 8000338:	b580      	push	{r7, lr}
 800033a:	af00      	add	r7, sp, #0
// PORT A
LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOA );
 800033c:	2001      	movs	r0, #1
 800033e:	f7ff ff43 	bl	80001c8 <LL_AHB2_GRP1_EnableClock>
// Green LED (user LED) - PA5
LL_GPIO_SetPinMode(       LED_PORT, LED_PIN, LL_GPIO_MODE_OUTPUT );
 8000342:	2201      	movs	r2, #1
 8000344:	2120      	movs	r1, #32
 8000346:	f04f 4090 	mov.w	r0, #1207959552	; 0x48000000
 800034a:	f7ff ff55 	bl	80001f8 <LL_GPIO_SetPinMode>
LL_GPIO_SetPinOutputType( LED_PORT, LED_PIN, LL_GPIO_OUTPUT_PUSHPULL );
 800034e:	2200      	movs	r2, #0
 8000350:	2120      	movs	r1, #32
 8000352:	f04f 4090 	mov.w	r0, #1207959552	; 0x48000000
 8000356:	f7ff ff8c 	bl	8000272 <LL_GPIO_SetPinOutputType>

// PORT C
LL_AHB2_GRP1_EnableClock( LL_AHB2_GRP1_PERIPH_GPIOC );
 800035a:	2004      	movs	r0, #4
 800035c:	f7ff ff34 	bl	80001c8 <LL_AHB2_GRP1_EnableClock>
// Blue button - PC13
LL_GPIO_SetPinMode( BUT_PORT, BUT_PIN, LL_GPIO_MODE_INPUT );
 8000360:	2200      	movs	r2, #0
 8000362:	f44f 5100 	mov.w	r1, #8192	; 0x2000
 8000366:	4805      	ldr	r0, [pc, #20]	; (800037c <GPIO_init+0x44>)
 8000368:	f7ff ff46 	bl	80001f8 <LL_GPIO_SetPinMode>
LL_GPIO_SetPinMode( BUT_PORT, CLK_PIN, LL_GPIO_MODE_OUTPUT );
 800036c:	2201      	movs	r2, #1
 800036e:	f44f 6180 	mov.w	r1, #1024	; 0x400
 8000372:	4802      	ldr	r0, [pc, #8]	; (800037c <GPIO_init+0x44>)
 8000374:	f7ff ff40 	bl	80001f8 <LL_GPIO_SetPinMode>
}
 8000378:	bf00      	nop
 800037a:	bd80      	pop	{r7, pc}
 800037c:	48000800 	.word	0x48000800

08000380 <CLK_TOGGLE>:

void CLK_TOGGLE(){
 8000380:	b580      	push	{r7, lr}
 8000382:	af00      	add	r7, sp, #0
	LL_GPIO_TogglePin(BUT_PORT, CLK_PIN);
 8000384:	f44f 6180 	mov.w	r1, #1024	; 0x400
 8000388:	4802      	ldr	r0, [pc, #8]	; (8000394 <CLK_TOGGLE+0x14>)
 800038a:	f7ff ffbb 	bl	8000304 <LL_GPIO_TogglePin>
}
 800038e:	bf00      	nop
 8000390:	bd80      	pop	{r7, pc}
 8000392:	bf00      	nop
 8000394:	48000800 	.word	0x48000800

08000398 <LED_GREEN>:

void LED_GREEN( int val )
{
 8000398:	b580      	push	{r7, lr}
 800039a:	b082      	sub	sp, #8
 800039c:	af00      	add	r7, sp, #0
 800039e:	6078      	str	r0, [r7, #4]
if	( val )
 80003a0:	687b      	ldr	r3, [r7, #4]
 80003a2:	2b00      	cmp	r3, #0
 80003a4:	d005      	beq.n	80003b2 <LED_GREEN+0x1a>
	LL_GPIO_SetOutputPin(   LED_PORT, LED_PIN );
 80003a6:	2120      	movs	r1, #32
 80003a8:	f04f 4090 	mov.w	r0, #1207959552	; 0x48000000
 80003ac:	f7ff ff8e 	bl	80002cc <LL_GPIO_SetOutputPin>
else	LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
}
 80003b0:	e004      	b.n	80003bc <LED_GREEN+0x24>
else	LL_GPIO_ResetOutputPin( LED_PORT, LED_PIN );
 80003b2:	2120      	movs	r1, #32
 80003b4:	f04f 4090 	mov.w	r0, #1207959552	; 0x48000000
 80003b8:	f7ff ff96 	bl	80002e8 <LL_GPIO_ResetOutputPin>
}
 80003bc:	bf00      	nop
 80003be:	3708      	adds	r7, #8
 80003c0:	46bd      	mov	sp, r7
 80003c2:	bd80      	pop	{r7, pc}

080003c4 <BLUE_BUTTON>:

int BLUE_BUTTON()
{
 80003c4:	b580      	push	{r7, lr}
 80003c6:	af00      	add	r7, sp, #0
return ( !LL_GPIO_IsInputPinSet( BUT_PORT, BUT_PIN ) );
 80003c8:	f44f 5100 	mov.w	r1, #8192	; 0x2000
 80003cc:	4805      	ldr	r0, [pc, #20]	; (80003e4 <BLUE_BUTTON+0x20>)
 80003ce:	f7ff ff68 	bl	80002a2 <LL_GPIO_IsInputPinSet>
 80003d2:	4603      	mov	r3, r0
 80003d4:	2b00      	cmp	r3, #0
 80003d6:	bf0c      	ite	eq
 80003d8:	2301      	moveq	r3, #1
 80003da:	2300      	movne	r3, #0
 80003dc:	b2db      	uxtb	r3, r3
}
 80003de:	4618      	mov	r0, r3
 80003e0:	bd80      	pop	{r7, pc}
 80003e2:	bf00      	nop
 80003e4:	48000800 	.word	0x48000800

080003e8 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 80003e8:	b480      	push	{r7}
 80003ea:	b083      	sub	sp, #12
 80003ec:	af00      	add	r7, sp, #0
 80003ee:	4603      	mov	r3, r0
 80003f0:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80003f2:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80003f6:	2b00      	cmp	r3, #0
 80003f8:	db0b      	blt.n	8000412 <__NVIC_EnableIRQ+0x2a>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 80003fa:	79fb      	ldrb	r3, [r7, #7]
 80003fc:	f003 021f 	and.w	r2, r3, #31
 8000400:	4907      	ldr	r1, [pc, #28]	; (8000420 <__NVIC_EnableIRQ+0x38>)
 8000402:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000406:	095b      	lsrs	r3, r3, #5
 8000408:	2001      	movs	r0, #1
 800040a:	fa00 f202 	lsl.w	r2, r0, r2
 800040e:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    __COMPILER_BARRIER();
  }
}
 8000412:	bf00      	nop
 8000414:	370c      	adds	r7, #12
 8000416:	46bd      	mov	sp, r7
 8000418:	f85d 7b04 	ldr.w	r7, [sp], #4
 800041c:	4770      	bx	lr
 800041e:	bf00      	nop
 8000420:	e000e100 	.word	0xe000e100

08000424 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8000424:	b480      	push	{r7}
 8000426:	b083      	sub	sp, #12
 8000428:	af00      	add	r7, sp, #0
 800042a:	4603      	mov	r3, r0
 800042c:	6039      	str	r1, [r7, #0]
 800042e:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8000430:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000434:	2b00      	cmp	r3, #0
 8000436:	db0a      	blt.n	800044e <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000438:	683b      	ldr	r3, [r7, #0]
 800043a:	b2da      	uxtb	r2, r3
 800043c:	490c      	ldr	r1, [pc, #48]	; (8000470 <__NVIC_SetPriority+0x4c>)
 800043e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000442:	0112      	lsls	r2, r2, #4
 8000444:	b2d2      	uxtb	r2, r2
 8000446:	440b      	add	r3, r1
 8000448:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 800044c:	e00a      	b.n	8000464 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800044e:	683b      	ldr	r3, [r7, #0]
 8000450:	b2da      	uxtb	r2, r3
 8000452:	4908      	ldr	r1, [pc, #32]	; (8000474 <__NVIC_SetPriority+0x50>)
 8000454:	79fb      	ldrb	r3, [r7, #7]
 8000456:	f003 030f 	and.w	r3, r3, #15
 800045a:	3b04      	subs	r3, #4
 800045c:	0112      	lsls	r2, r2, #4
 800045e:	b2d2      	uxtb	r2, r2
 8000460:	440b      	add	r3, r1
 8000462:	761a      	strb	r2, [r3, #24]
}
 8000464:	bf00      	nop
 8000466:	370c      	adds	r7, #12
 8000468:	46bd      	mov	sp, r7
 800046a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800046e:	4770      	bx	lr
 8000470:	e000e100 	.word	0xe000e100
 8000474:	e000ed00 	.word	0xe000ed00

08000478 <LL_RCC_LSE_Enable>:
  * @brief  Enable  Low Speed External (LSE) crystal.
  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
  * @retval None
  */
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
{
 8000478:	b480      	push	{r7}
 800047a:	af00      	add	r7, sp, #0
  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
 800047c:	4b06      	ldr	r3, [pc, #24]	; (8000498 <LL_RCC_LSE_Enable+0x20>)
 800047e:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8000482:	4a05      	ldr	r2, [pc, #20]	; (8000498 <LL_RCC_LSE_Enable+0x20>)
 8000484:	f043 0301 	orr.w	r3, r3, #1
 8000488:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
}
 800048c:	bf00      	nop
 800048e:	46bd      	mov	sp, r7
 8000490:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000494:	4770      	bx	lr
 8000496:	bf00      	nop
 8000498:	40021000 	.word	0x40021000

0800049c <LL_RCC_LSE_SetDriveCapability>:
  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
  * @retval None
  */
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
{
 800049c:	b480      	push	{r7}
 800049e:	b083      	sub	sp, #12
 80004a0:	af00      	add	r7, sp, #0
 80004a2:	6078      	str	r0, [r7, #4]
  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
 80004a4:	4b07      	ldr	r3, [pc, #28]	; (80004c4 <LL_RCC_LSE_SetDriveCapability+0x28>)
 80004a6:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80004aa:	f023 0218 	bic.w	r2, r3, #24
 80004ae:	4905      	ldr	r1, [pc, #20]	; (80004c4 <LL_RCC_LSE_SetDriveCapability+0x28>)
 80004b0:	687b      	ldr	r3, [r7, #4]
 80004b2:	4313      	orrs	r3, r2
 80004b4:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
}
 80004b8:	bf00      	nop
 80004ba:	370c      	adds	r7, #12
 80004bc:	46bd      	mov	sp, r7
 80004be:	f85d 7b04 	ldr.w	r7, [sp], #4
 80004c2:	4770      	bx	lr
 80004c4:	40021000 	.word	0x40021000

080004c8 <LL_RCC_LSE_IsReady>:
  * @brief  Check if LSE oscillator Ready
  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
  * @retval State of bit (1 or 0).
  */
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
{
 80004c8:	b480      	push	{r7}
 80004ca:	af00      	add	r7, sp, #0
  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
 80004cc:	4b07      	ldr	r3, [pc, #28]	; (80004ec <LL_RCC_LSE_IsReady+0x24>)
 80004ce:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80004d2:	f003 0302 	and.w	r3, r3, #2
 80004d6:	2b02      	cmp	r3, #2
 80004d8:	d101      	bne.n	80004de <LL_RCC_LSE_IsReady+0x16>
 80004da:	2301      	movs	r3, #1
 80004dc:	e000      	b.n	80004e0 <LL_RCC_LSE_IsReady+0x18>
 80004de:	2300      	movs	r3, #0
}
 80004e0:	4618      	mov	r0, r3
 80004e2:	46bd      	mov	sp, r7
 80004e4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80004e8:	4770      	bx	lr
 80004ea:	bf00      	nop
 80004ec:	40021000 	.word	0x40021000

080004f0 <LL_RCC_MSI_Enable>:
  * @brief  Enable MSI oscillator
  * @rmtoll CR           MSION         LL_RCC_MSI_Enable
  * @retval None
  */
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
{
 80004f0:	b480      	push	{r7}
 80004f2:	af00      	add	r7, sp, #0
  SET_BIT(RCC->CR, RCC_CR_MSION);
 80004f4:	4b05      	ldr	r3, [pc, #20]	; (800050c <LL_RCC_MSI_Enable+0x1c>)
 80004f6:	681b      	ldr	r3, [r3, #0]
 80004f8:	4a04      	ldr	r2, [pc, #16]	; (800050c <LL_RCC_MSI_Enable+0x1c>)
 80004fa:	f043 0301 	orr.w	r3, r3, #1
 80004fe:	6013      	str	r3, [r2, #0]
}
 8000500:	bf00      	nop
 8000502:	46bd      	mov	sp, r7
 8000504:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000508:	4770      	bx	lr
 800050a:	bf00      	nop
 800050c:	40021000 	.word	0x40021000

08000510 <LL_RCC_MSI_IsReady>:
  * @brief  Check if MSI oscillator Ready
  * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
  * @retval State of bit (1 or 0).
  */
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
{
 8000510:	b480      	push	{r7}
 8000512:	af00      	add	r7, sp, #0
  return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
 8000514:	4b06      	ldr	r3, [pc, #24]	; (8000530 <LL_RCC_MSI_IsReady+0x20>)
 8000516:	681b      	ldr	r3, [r3, #0]
 8000518:	f003 0302 	and.w	r3, r3, #2
 800051c:	2b02      	cmp	r3, #2
 800051e:	d101      	bne.n	8000524 <LL_RCC_MSI_IsReady+0x14>
 8000520:	2301      	movs	r3, #1
 8000522:	e000      	b.n	8000526 <LL_RCC_MSI_IsReady+0x16>
 8000524:	2300      	movs	r3, #0
}
 8000526:	4618      	mov	r0, r3
 8000528:	46bd      	mov	sp, r7
 800052a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800052e:	4770      	bx	lr
 8000530:	40021000 	.word	0x40021000

08000534 <LL_RCC_MSI_EnablePLLMode>:
  *       ready
  * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_EnablePLLMode
  * @retval None
  */
__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
{
 8000534:	b480      	push	{r7}
 8000536:	af00      	add	r7, sp, #0
  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
 8000538:	4b05      	ldr	r3, [pc, #20]	; (8000550 <LL_RCC_MSI_EnablePLLMode+0x1c>)
 800053a:	681b      	ldr	r3, [r3, #0]
 800053c:	4a04      	ldr	r2, [pc, #16]	; (8000550 <LL_RCC_MSI_EnablePLLMode+0x1c>)
 800053e:	f043 0304 	orr.w	r3, r3, #4
 8000542:	6013      	str	r3, [r2, #0]
}
 8000544:	bf00      	nop
 8000546:	46bd      	mov	sp, r7
 8000548:	f85d 7b04 	ldr.w	r7, [sp], #4
 800054c:	4770      	bx	lr
 800054e:	bf00      	nop
 8000550:	40021000 	.word	0x40021000

08000554 <LL_RCC_MSI_EnableRangeSelection>:
  *       MSISRANGE
  * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_EnableRangeSelection
  * @retval None
  */
__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
{
 8000554:	b480      	push	{r7}
 8000556:	af00      	add	r7, sp, #0
  SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
 8000558:	4b05      	ldr	r3, [pc, #20]	; (8000570 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
 800055a:	681b      	ldr	r3, [r3, #0]
 800055c:	4a04      	ldr	r2, [pc, #16]	; (8000570 <LL_RCC_MSI_EnableRangeSelection+0x1c>)
 800055e:	f043 0308 	orr.w	r3, r3, #8
 8000562:	6013      	str	r3, [r2, #0]
}
 8000564:	bf00      	nop
 8000566:	46bd      	mov	sp, r7
 8000568:	f85d 7b04 	ldr.w	r7, [sp], #4
 800056c:	4770      	bx	lr
 800056e:	bf00      	nop
 8000570:	40021000 	.word	0x40021000

08000574 <LL_RCC_MSI_SetRange>:
  *         @arg @ref LL_RCC_MSIRANGE_10
  *         @arg @ref LL_RCC_MSIRANGE_11
  * @retval None
  */
__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
{
 8000574:	b480      	push	{r7}
 8000576:	b083      	sub	sp, #12
 8000578:	af00      	add	r7, sp, #0
 800057a:	6078      	str	r0, [r7, #4]
  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
 800057c:	4b06      	ldr	r3, [pc, #24]	; (8000598 <LL_RCC_MSI_SetRange+0x24>)
 800057e:	681b      	ldr	r3, [r3, #0]
 8000580:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8000584:	4904      	ldr	r1, [pc, #16]	; (8000598 <LL_RCC_MSI_SetRange+0x24>)
 8000586:	687b      	ldr	r3, [r7, #4]
 8000588:	4313      	orrs	r3, r2
 800058a:	600b      	str	r3, [r1, #0]
}
 800058c:	bf00      	nop
 800058e:	370c      	adds	r7, #12
 8000590:	46bd      	mov	sp, r7
 8000592:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000596:	4770      	bx	lr
 8000598:	40021000 	.word	0x40021000

0800059c <LL_RCC_MSI_SetCalibTrimming>:
  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
  * @param  Value Between Min_Data = 0 and Max_Data = 255
  * @retval None
  */
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
{
 800059c:	b480      	push	{r7}
 800059e:	b083      	sub	sp, #12
 80005a0:	af00      	add	r7, sp, #0
 80005a2:	6078      	str	r0, [r7, #4]
  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
 80005a4:	4b07      	ldr	r3, [pc, #28]	; (80005c4 <LL_RCC_MSI_SetCalibTrimming+0x28>)
 80005a6:	685b      	ldr	r3, [r3, #4]
 80005a8:	f423 427f 	bic.w	r2, r3, #65280	; 0xff00
 80005ac:	687b      	ldr	r3, [r7, #4]
 80005ae:	021b      	lsls	r3, r3, #8
 80005b0:	4904      	ldr	r1, [pc, #16]	; (80005c4 <LL_RCC_MSI_SetCalibTrimming+0x28>)
 80005b2:	4313      	orrs	r3, r2
 80005b4:	604b      	str	r3, [r1, #4]
}
 80005b6:	bf00      	nop
 80005b8:	370c      	adds	r7, #12
 80005ba:	46bd      	mov	sp, r7
 80005bc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80005c0:	4770      	bx	lr
 80005c2:	bf00      	nop
 80005c4:	40021000 	.word	0x40021000

080005c8 <LL_RCC_SetSysClkSource>:
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
  * @retval None
  */
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
 80005c8:	b480      	push	{r7}
 80005ca:	b083      	sub	sp, #12
 80005cc:	af00      	add	r7, sp, #0
 80005ce:	6078      	str	r0, [r7, #4]
  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
 80005d0:	4b06      	ldr	r3, [pc, #24]	; (80005ec <LL_RCC_SetSysClkSource+0x24>)
 80005d2:	689b      	ldr	r3, [r3, #8]
 80005d4:	f023 0203 	bic.w	r2, r3, #3
 80005d8:	4904      	ldr	r1, [pc, #16]	; (80005ec <LL_RCC_SetSysClkSource+0x24>)
 80005da:	687b      	ldr	r3, [r7, #4]
 80005dc:	4313      	orrs	r3, r2
 80005de:	608b      	str	r3, [r1, #8]
}
 80005e0:	bf00      	nop
 80005e2:	370c      	adds	r7, #12
 80005e4:	46bd      	mov	sp, r7
 80005e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80005ea:	4770      	bx	lr
 80005ec:	40021000 	.word	0x40021000

080005f0 <LL_RCC_GetSysClkSource>:
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
  */
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
 80005f0:	b480      	push	{r7}
 80005f2:	af00      	add	r7, sp, #0
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
 80005f4:	4b04      	ldr	r3, [pc, #16]	; (8000608 <LL_RCC_GetSysClkSource+0x18>)
 80005f6:	689b      	ldr	r3, [r3, #8]
 80005f8:	f003 030c 	and.w	r3, r3, #12
}
 80005fc:	4618      	mov	r0, r3
 80005fe:	46bd      	mov	sp, r7
 8000600:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000604:	4770      	bx	lr
 8000606:	bf00      	nop
 8000608:	40021000 	.word	0x40021000

0800060c <LL_RCC_SetAHBPrescaler>:
  *         @arg @ref LL_RCC_SYSCLK_DIV_256
  *         @arg @ref LL_RCC_SYSCLK_DIV_512
  * @retval None
  */
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
 800060c:	b480      	push	{r7}
 800060e:	b083      	sub	sp, #12
 8000610:	af00      	add	r7, sp, #0
 8000612:	6078      	str	r0, [r7, #4]
  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
 8000614:	4b06      	ldr	r3, [pc, #24]	; (8000630 <LL_RCC_SetAHBPrescaler+0x24>)
 8000616:	689b      	ldr	r3, [r3, #8]
 8000618:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 800061c:	4904      	ldr	r1, [pc, #16]	; (8000630 <LL_RCC_SetAHBPrescaler+0x24>)
 800061e:	687b      	ldr	r3, [r7, #4]
 8000620:	4313      	orrs	r3, r2
 8000622:	608b      	str	r3, [r1, #8]
}
 8000624:	bf00      	nop
 8000626:	370c      	adds	r7, #12
 8000628:	46bd      	mov	sp, r7
 800062a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800062e:	4770      	bx	lr
 8000630:	40021000 	.word	0x40021000

08000634 <LL_RCC_SetAPB1Prescaler>:
  *         @arg @ref LL_RCC_APB1_DIV_8
  *         @arg @ref LL_RCC_APB1_DIV_16
  * @retval None
  */
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
 8000634:	b480      	push	{r7}
 8000636:	b083      	sub	sp, #12
 8000638:	af00      	add	r7, sp, #0
 800063a:	6078      	str	r0, [r7, #4]
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
 800063c:	4b06      	ldr	r3, [pc, #24]	; (8000658 <LL_RCC_SetAPB1Prescaler+0x24>)
 800063e:	689b      	ldr	r3, [r3, #8]
 8000640:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
 8000644:	4904      	ldr	r1, [pc, #16]	; (8000658 <LL_RCC_SetAPB1Prescaler+0x24>)
 8000646:	687b      	ldr	r3, [r7, #4]
 8000648:	4313      	orrs	r3, r2
 800064a:	608b      	str	r3, [r1, #8]
}
 800064c:	bf00      	nop
 800064e:	370c      	adds	r7, #12
 8000650:	46bd      	mov	sp, r7
 8000652:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000656:	4770      	bx	lr
 8000658:	40021000 	.word	0x40021000

0800065c <LL_RCC_SetAPB2Prescaler>:
  *         @arg @ref LL_RCC_APB2_DIV_8
  *         @arg @ref LL_RCC_APB2_DIV_16
  * @retval None
  */
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
{
 800065c:	b480      	push	{r7}
 800065e:	b083      	sub	sp, #12
 8000660:	af00      	add	r7, sp, #0
 8000662:	6078      	str	r0, [r7, #4]
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
 8000664:	4b06      	ldr	r3, [pc, #24]	; (8000680 <LL_RCC_SetAPB2Prescaler+0x24>)
 8000666:	689b      	ldr	r3, [r3, #8]
 8000668:	f423 5260 	bic.w	r2, r3, #14336	; 0x3800
 800066c:	4904      	ldr	r1, [pc, #16]	; (8000680 <LL_RCC_SetAPB2Prescaler+0x24>)
 800066e:	687b      	ldr	r3, [r7, #4]
 8000670:	4313      	orrs	r3, r2
 8000672:	608b      	str	r3, [r1, #8]
}
 8000674:	bf00      	nop
 8000676:	370c      	adds	r7, #12
 8000678:	46bd      	mov	sp, r7
 800067a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800067e:	4770      	bx	lr
 8000680:	40021000 	.word	0x40021000

08000684 <LL_RCC_SetRTCClockSource>:
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
  * @retval None
  */
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
{
 8000684:	b480      	push	{r7}
 8000686:	b083      	sub	sp, #12
 8000688:	af00      	add	r7, sp, #0
 800068a:	6078      	str	r0, [r7, #4]
  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
 800068c:	4b07      	ldr	r3, [pc, #28]	; (80006ac <LL_RCC_SetRTCClockSource+0x28>)
 800068e:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8000692:	f423 7240 	bic.w	r2, r3, #768	; 0x300
 8000696:	4905      	ldr	r1, [pc, #20]	; (80006ac <LL_RCC_SetRTCClockSource+0x28>)
 8000698:	687b      	ldr	r3, [r7, #4]
 800069a:	4313      	orrs	r3, r2
 800069c:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
}
 80006a0:	bf00      	nop
 80006a2:	370c      	adds	r7, #12
 80006a4:	46bd      	mov	sp, r7
 80006a6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80006aa:	4770      	bx	lr
 80006ac:	40021000 	.word	0x40021000

080006b0 <LL_RCC_EnableRTC>:
  * @brief  Enable RTC
  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
  * @retval None
  */
__STATIC_INLINE void LL_RCC_EnableRTC(void)
{
 80006b0:	b480      	push	{r7}
 80006b2:	af00      	add	r7, sp, #0
  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
 80006b4:	4b06      	ldr	r3, [pc, #24]	; (80006d0 <LL_RCC_EnableRTC+0x20>)
 80006b6:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80006ba:	4a05      	ldr	r2, [pc, #20]	; (80006d0 <LL_RCC_EnableRTC+0x20>)
 80006bc:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
 80006c0:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
}
 80006c4:	bf00      	nop
 80006c6:	46bd      	mov	sp, r7
 80006c8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80006cc:	4770      	bx	lr
 80006ce:	bf00      	nop
 80006d0:	40021000 	.word	0x40021000

080006d4 <LL_RCC_ReleaseBackupDomainReset>:
  * @brief  Release the Backup domain reset
  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
  * @retval None
  */
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
{
 80006d4:	b480      	push	{r7}
 80006d6:	af00      	add	r7, sp, #0
  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
 80006d8:	4b06      	ldr	r3, [pc, #24]	; (80006f4 <LL_RCC_ReleaseBackupDomainReset+0x20>)
 80006da:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80006de:	4a05      	ldr	r2, [pc, #20]	; (80006f4 <LL_RCC_ReleaseBackupDomainReset+0x20>)
 80006e0:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 80006e4:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
}
 80006e8:	bf00      	nop
 80006ea:	46bd      	mov	sp, r7
 80006ec:	f85d 7b04 	ldr.w	r7, [sp], #4
 80006f0:	4770      	bx	lr
 80006f2:	bf00      	nop
 80006f4:	40021000 	.word	0x40021000

080006f8 <LL_RCC_PLL_Enable>:
  * @brief  Enable PLL
  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
  * @retval None
  */
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
 80006f8:	b480      	push	{r7}
 80006fa:	af00      	add	r7, sp, #0
  SET_BIT(RCC->CR, RCC_CR_PLLON);
 80006fc:	4b05      	ldr	r3, [pc, #20]	; (8000714 <LL_RCC_PLL_Enable+0x1c>)
 80006fe:	681b      	ldr	r3, [r3, #0]
 8000700:	4a04      	ldr	r2, [pc, #16]	; (8000714 <LL_RCC_PLL_Enable+0x1c>)
 8000702:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 8000706:	6013      	str	r3, [r2, #0]
}
 8000708:	bf00      	nop
 800070a:	46bd      	mov	sp, r7
 800070c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000710:	4770      	bx	lr
 8000712:	bf00      	nop
 8000714:	40021000 	.word	0x40021000

08000718 <LL_RCC_PLL_IsReady>:
  * @brief  Check if PLL Ready
  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
  * @retval State of bit (1 or 0).
  */
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
 8000718:	b480      	push	{r7}
 800071a:	af00      	add	r7, sp, #0
  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
 800071c:	4b07      	ldr	r3, [pc, #28]	; (800073c <LL_RCC_PLL_IsReady+0x24>)
 800071e:	681b      	ldr	r3, [r3, #0]
 8000720:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8000724:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
 8000728:	d101      	bne.n	800072e <LL_RCC_PLL_IsReady+0x16>
 800072a:	2301      	movs	r3, #1
 800072c:	e000      	b.n	8000730 <LL_RCC_PLL_IsReady+0x18>
 800072e:	2300      	movs	r3, #0
}
 8000730:	4618      	mov	r0, r3
 8000732:	46bd      	mov	sp, r7
 8000734:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000738:	4770      	bx	lr
 800073a:	bf00      	nop
 800073c:	40021000 	.word	0x40021000

08000740 <LL_RCC_PLL_ConfigDomain_SYS>:
  *         @arg @ref LL_RCC_PLLR_DIV_6
  *         @arg @ref LL_RCC_PLLR_DIV_8
  * @retval None
  */
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
 8000740:	b480      	push	{r7}
 8000742:	b085      	sub	sp, #20
 8000744:	af00      	add	r7, sp, #0
 8000746:	60f8      	str	r0, [r7, #12]
 8000748:	60b9      	str	r1, [r7, #8]
 800074a:	607a      	str	r2, [r7, #4]
 800074c:	603b      	str	r3, [r7, #0]
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
 800074e:	4b0a      	ldr	r3, [pc, #40]	; (8000778 <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
 8000750:	68da      	ldr	r2, [r3, #12]
 8000752:	4b0a      	ldr	r3, [pc, #40]	; (800077c <LL_RCC_PLL_ConfigDomain_SYS+0x3c>)
 8000754:	4013      	ands	r3, r2
 8000756:	68f9      	ldr	r1, [r7, #12]
 8000758:	68ba      	ldr	r2, [r7, #8]
 800075a:	4311      	orrs	r1, r2
 800075c:	687a      	ldr	r2, [r7, #4]
 800075e:	0212      	lsls	r2, r2, #8
 8000760:	4311      	orrs	r1, r2
 8000762:	683a      	ldr	r2, [r7, #0]
 8000764:	430a      	orrs	r2, r1
 8000766:	4904      	ldr	r1, [pc, #16]	; (8000778 <LL_RCC_PLL_ConfigDomain_SYS+0x38>)
 8000768:	4313      	orrs	r3, r2
 800076a:	60cb      	str	r3, [r1, #12]
             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
}
 800076c:	bf00      	nop
 800076e:	3714      	adds	r7, #20
 8000770:	46bd      	mov	sp, r7
 8000772:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000776:	4770      	bx	lr
 8000778:	40021000 	.word	0x40021000
 800077c:	f9ff808c 	.word	0xf9ff808c

08000780 <LL_RCC_PLL_EnableDomain_SYS>:
  * @brief  Enable PLL output mapped on SYSCLK domain
  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
  * @retval None
  */
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
{
 8000780:	b480      	push	{r7}
 8000782:	af00      	add	r7, sp, #0
  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
 8000784:	4b05      	ldr	r3, [pc, #20]	; (800079c <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
 8000786:	68db      	ldr	r3, [r3, #12]
 8000788:	4a04      	ldr	r2, [pc, #16]	; (800079c <LL_RCC_PLL_EnableDomain_SYS+0x1c>)
 800078a:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 800078e:	60d3      	str	r3, [r2, #12]
}
 8000790:	bf00      	nop
 8000792:	46bd      	mov	sp, r7
 8000794:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000798:	4770      	bx	lr
 800079a:	bf00      	nop
 800079c:	40021000 	.word	0x40021000

080007a0 <LL_APB1_GRP1_EnableClock>:
  *
  *         (*) value not defined in all devices.
  * @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
{
 80007a0:	b480      	push	{r7}
 80007a2:	b085      	sub	sp, #20
 80007a4:	af00      	add	r7, sp, #0
 80007a6:	6078      	str	r0, [r7, #4]
  __IO uint32_t tmpreg;
  SET_BIT(RCC->APB1ENR1, Periphs);
 80007a8:	4b08      	ldr	r3, [pc, #32]	; (80007cc <LL_APB1_GRP1_EnableClock+0x2c>)
 80007aa:	6d9a      	ldr	r2, [r3, #88]	; 0x58
 80007ac:	4907      	ldr	r1, [pc, #28]	; (80007cc <LL_APB1_GRP1_EnableClock+0x2c>)
 80007ae:	687b      	ldr	r3, [r7, #4]
 80007b0:	4313      	orrs	r3, r2
 80007b2:	658b      	str	r3, [r1, #88]	; 0x58
  /* Delay after an RCC peripheral clock enabling */
  tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
 80007b4:	4b05      	ldr	r3, [pc, #20]	; (80007cc <LL_APB1_GRP1_EnableClock+0x2c>)
 80007b6:	6d9a      	ldr	r2, [r3, #88]	; 0x58
 80007b8:	687b      	ldr	r3, [r7, #4]
 80007ba:	4013      	ands	r3, r2
 80007bc:	60fb      	str	r3, [r7, #12]
  (void)tmpreg;
 80007be:	68fb      	ldr	r3, [r7, #12]
}
 80007c0:	bf00      	nop
 80007c2:	3714      	adds	r7, #20
 80007c4:	46bd      	mov	sp, r7
 80007c6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80007ca:	4770      	bx	lr
 80007cc:	40021000 	.word	0x40021000

080007d0 <LL_FLASH_SetLatency>:
  *
  *         (*) value not defined in all devices.
  * @retval None
  */
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
 80007d0:	b480      	push	{r7}
 80007d2:	b083      	sub	sp, #12
 80007d4:	af00      	add	r7, sp, #0
 80007d6:	6078      	str	r0, [r7, #4]
  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
 80007d8:	4b06      	ldr	r3, [pc, #24]	; (80007f4 <LL_FLASH_SetLatency+0x24>)
 80007da:	681b      	ldr	r3, [r3, #0]
 80007dc:	f023 0207 	bic.w	r2, r3, #7
 80007e0:	4904      	ldr	r1, [pc, #16]	; (80007f4 <LL_FLASH_SetLatency+0x24>)
 80007e2:	687b      	ldr	r3, [r7, #4]
 80007e4:	4313      	orrs	r3, r2
 80007e6:	600b      	str	r3, [r1, #0]
}
 80007e8:	bf00      	nop
 80007ea:	370c      	adds	r7, #12
 80007ec:	46bd      	mov	sp, r7
 80007ee:	f85d 7b04 	ldr.w	r7, [sp], #4
 80007f2:	4770      	bx	lr
 80007f4:	40022000 	.word	0x40022000

080007f8 <LL_FLASH_GetLatency>:
  *         @arg @ref LL_FLASH_LATENCY_15 (*)
  *
  *         (*) value not defined in all devices.
  */
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
 80007f8:	b480      	push	{r7}
 80007fa:	af00      	add	r7, sp, #0
  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
 80007fc:	4b04      	ldr	r3, [pc, #16]	; (8000810 <LL_FLASH_GetLatency+0x18>)
 80007fe:	681b      	ldr	r3, [r3, #0]
 8000800:	f003 0307 	and.w	r3, r3, #7
}
 8000804:	4618      	mov	r0, r3
 8000806:	46bd      	mov	sp, r7
 8000808:	f85d 7b04 	ldr.w	r7, [sp], #4
 800080c:	4770      	bx	lr
 800080e:	bf00      	nop
 8000810:	40022000 	.word	0x40022000

08000814 <LL_EXTI_EnableIT_0_31>:
  *         @arg @ref LL_EXTI_LINE_ALL_0_31
  * @note   Please check each device line mapping for EXTI Line availability
  * @retval None
  */
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
 8000814:	b480      	push	{r7}
 8000816:	b083      	sub	sp, #12
 8000818:	af00      	add	r7, sp, #0
 800081a:	6078      	str	r0, [r7, #4]
  SET_BIT(EXTI->IMR1, ExtiLine);
 800081c:	4b05      	ldr	r3, [pc, #20]	; (8000834 <LL_EXTI_EnableIT_0_31+0x20>)
 800081e:	681a      	ldr	r2, [r3, #0]
 8000820:	4904      	ldr	r1, [pc, #16]	; (8000834 <LL_EXTI_EnableIT_0_31+0x20>)
 8000822:	687b      	ldr	r3, [r7, #4]
 8000824:	4313      	orrs	r3, r2
 8000826:	600b      	str	r3, [r1, #0]
}
 8000828:	bf00      	nop
 800082a:	370c      	adds	r7, #12
 800082c:	46bd      	mov	sp, r7
 800082e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000832:	4770      	bx	lr
 8000834:	40010400 	.word	0x40010400

08000838 <LL_EXTI_EnableRisingTrig_0_31>:
  *         @arg @ref LL_EXTI_LINE_31
  * @note   Please check each device line mapping for EXTI Line availability
  * @retval None
  */
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
 8000838:	b480      	push	{r7}
 800083a:	b083      	sub	sp, #12
 800083c:	af00      	add	r7, sp, #0
 800083e:	6078      	str	r0, [r7, #4]
  SET_BIT(EXTI->RTSR1, ExtiLine);
 8000840:	4b05      	ldr	r3, [pc, #20]	; (8000858 <LL_EXTI_EnableRisingTrig_0_31+0x20>)
 8000842:	689a      	ldr	r2, [r3, #8]
 8000844:	4904      	ldr	r1, [pc, #16]	; (8000858 <LL_EXTI_EnableRisingTrig_0_31+0x20>)
 8000846:	687b      	ldr	r3, [r7, #4]
 8000848:	4313      	orrs	r3, r2
 800084a:	608b      	str	r3, [r1, #8]

}
 800084c:	bf00      	nop
 800084e:	370c      	adds	r7, #12
 8000850:	46bd      	mov	sp, r7
 8000852:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000856:	4770      	bx	lr
 8000858:	40010400 	.word	0x40010400

0800085c <LL_EXTI_ClearFlag_0_31>:
  *         @arg @ref LL_EXTI_LINE_31
  * @note   Please check each device line mapping for EXTI Line availability
  * @retval None
  */
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
{
 800085c:	b480      	push	{r7}
 800085e:	b083      	sub	sp, #12
 8000860:	af00      	add	r7, sp, #0
 8000862:	6078      	str	r0, [r7, #4]
  WRITE_REG(EXTI->PR1, ExtiLine);
 8000864:	4a04      	ldr	r2, [pc, #16]	; (8000878 <LL_EXTI_ClearFlag_0_31+0x1c>)
 8000866:	687b      	ldr	r3, [r7, #4]
 8000868:	6153      	str	r3, [r2, #20]
}
 800086a:	bf00      	nop
 800086c:	370c      	adds	r7, #12
 800086e:	46bd      	mov	sp, r7
 8000870:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000874:	4770      	bx	lr
 8000876:	bf00      	nop
 8000878:	40010400 	.word	0x40010400

0800087c <LL_SYSTICK_EnableIT>:
  * @brief  Enable SysTick exception request
  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
  * @retval None
  */
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
 800087c:	b480      	push	{r7}
 800087e:	af00      	add	r7, sp, #0
  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 8000880:	4b05      	ldr	r3, [pc, #20]	; (8000898 <LL_SYSTICK_EnableIT+0x1c>)
 8000882:	681b      	ldr	r3, [r3, #0]
 8000884:	4a04      	ldr	r2, [pc, #16]	; (8000898 <LL_SYSTICK_EnableIT+0x1c>)
 8000886:	f043 0302 	orr.w	r3, r3, #2
 800088a:	6013      	str	r3, [r2, #0]
}
 800088c:	bf00      	nop
 800088e:	46bd      	mov	sp, r7
 8000890:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000894:	4770      	bx	lr
 8000896:	bf00      	nop
 8000898:	e000e010 	.word	0xe000e010

0800089c <LL_LPM_EnableSleep>:
  * @brief  Processor uses sleep as its low power mode
  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
  * @retval None
  */
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
 800089c:	b480      	push	{r7}
 800089e:	af00      	add	r7, sp, #0
  /* Clear SLEEPDEEP bit of Cortex System Control Register */
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 80008a0:	4b05      	ldr	r3, [pc, #20]	; (80008b8 <LL_LPM_EnableSleep+0x1c>)
 80008a2:	691b      	ldr	r3, [r3, #16]
 80008a4:	4a04      	ldr	r2, [pc, #16]	; (80008b8 <LL_LPM_EnableSleep+0x1c>)
 80008a6:	f023 0304 	bic.w	r3, r3, #4
 80008aa:	6113      	str	r3, [r2, #16]
}
 80008ac:	bf00      	nop
 80008ae:	46bd      	mov	sp, r7
 80008b0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80008b4:	4770      	bx	lr
 80008b6:	bf00      	nop
 80008b8:	e000ed00 	.word	0xe000ed00

080008bc <LL_LPM_EnableDeepSleep>:
  * @brief  Processor uses deep sleep as its low power mode
  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
  * @retval None
  */
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
 80008bc:	b480      	push	{r7}
 80008be:	af00      	add	r7, sp, #0
  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 80008c0:	4b05      	ldr	r3, [pc, #20]	; (80008d8 <LL_LPM_EnableDeepSleep+0x1c>)
 80008c2:	691b      	ldr	r3, [r3, #16]
 80008c4:	4a04      	ldr	r2, [pc, #16]	; (80008d8 <LL_LPM_EnableDeepSleep+0x1c>)
 80008c6:	f043 0304 	orr.w	r3, r3, #4
 80008ca:	6113      	str	r3, [r2, #16]
}
 80008cc:	bf00      	nop
 80008ce:	46bd      	mov	sp, r7
 80008d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80008d4:	4770      	bx	lr
 80008d6:	bf00      	nop
 80008d8:	e000ed00 	.word	0xe000ed00

080008dc <LL_PWR_SetRegulVoltageScaling>:
  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
  * @retval None
  */
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
{
 80008dc:	b480      	push	{r7}
 80008de:	b083      	sub	sp, #12
 80008e0:	af00      	add	r7, sp, #0
 80008e2:	6078      	str	r0, [r7, #4]
  MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
 80008e4:	4b06      	ldr	r3, [pc, #24]	; (8000900 <LL_PWR_SetRegulVoltageScaling+0x24>)
 80008e6:	681b      	ldr	r3, [r3, #0]
 80008e8:	f423 62c0 	bic.w	r2, r3, #1536	; 0x600
 80008ec:	4904      	ldr	r1, [pc, #16]	; (8000900 <LL_PWR_SetRegulVoltageScaling+0x24>)
 80008ee:	687b      	ldr	r3, [r7, #4]
 80008f0:	4313      	orrs	r3, r2
 80008f2:	600b      	str	r3, [r1, #0]
}
 80008f4:	bf00      	nop
 80008f6:	370c      	adds	r7, #12
 80008f8:	46bd      	mov	sp, r7
 80008fa:	f85d 7b04 	ldr.w	r7, [sp], #4
 80008fe:	4770      	bx	lr
 8000900:	40007000 	.word	0x40007000

08000904 <LL_PWR_EnableBkUpAccess>:
  * @brief  Enable access to the backup domain
  * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
  * @retval None
  */
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
 8000904:	b480      	push	{r7}
 8000906:	af00      	add	r7, sp, #0
  SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8000908:	4b05      	ldr	r3, [pc, #20]	; (8000920 <LL_PWR_EnableBkUpAccess+0x1c>)
 800090a:	681b      	ldr	r3, [r3, #0]
 800090c:	4a04      	ldr	r2, [pc, #16]	; (8000920 <LL_PWR_EnableBkUpAccess+0x1c>)
 800090e:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000912:	6013      	str	r3, [r2, #0]
}
 8000914:	bf00      	nop
 8000916:	46bd      	mov	sp, r7
 8000918:	f85d 7b04 	ldr.w	r7, [sp], #4
 800091c:	4770      	bx	lr
 800091e:	bf00      	nop
 8000920:	40007000 	.word	0x40007000

08000924 <LL_PWR_DisableBkUpAccess>:
  * @brief  Disable access to the backup domain
  * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
  * @retval None
  */
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
 8000924:	b480      	push	{r7}
 8000926:	af00      	add	r7, sp, #0
  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
 8000928:	4b05      	ldr	r3, [pc, #20]	; (8000940 <LL_PWR_DisableBkUpAccess+0x1c>)
 800092a:	681b      	ldr	r3, [r3, #0]
 800092c:	4a04      	ldr	r2, [pc, #16]	; (8000940 <LL_PWR_DisableBkUpAccess+0x1c>)
 800092e:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 8000932:	6013      	str	r3, [r2, #0]
}
 8000934:	bf00      	nop
 8000936:	46bd      	mov	sp, r7
 8000938:	f85d 7b04 	ldr.w	r7, [sp], #4
 800093c:	4770      	bx	lr
 800093e:	bf00      	nop
 8000940:	40007000 	.word	0x40007000

08000944 <LL_PWR_SetPowerMode>:
  *         @arg @ref LL_PWR_MODE_STANDBY
  *         @arg @ref LL_PWR_MODE_SHUTDOWN
  * @retval None
  */
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
{
 8000944:	b480      	push	{r7}
 8000946:	b083      	sub	sp, #12
 8000948:	af00      	add	r7, sp, #0
 800094a:	6078      	str	r0, [r7, #4]
  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
 800094c:	4b06      	ldr	r3, [pc, #24]	; (8000968 <LL_PWR_SetPowerMode+0x24>)
 800094e:	681b      	ldr	r3, [r3, #0]
 8000950:	f023 0207 	bic.w	r2, r3, #7
 8000954:	4904      	ldr	r1, [pc, #16]	; (8000968 <LL_PWR_SetPowerMode+0x24>)
 8000956:	687b      	ldr	r3, [r7, #4]
 8000958:	4313      	orrs	r3, r2
 800095a:	600b      	str	r3, [r1, #0]
}
 800095c:	bf00      	nop
 800095e:	370c      	adds	r7, #12
 8000960:	46bd      	mov	sp, r7
 8000962:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000966:	4770      	bx	lr
 8000968:	40007000 	.word	0x40007000

0800096c <LL_PWR_EnableInternWU>:
  * @brief  Enable Internal Wake-up line
  * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
  * @retval None
  */
__STATIC_INLINE void LL_PWR_EnableInternWU(void)
{
 800096c:	b480      	push	{r7}
 800096e:	af00      	add	r7, sp, #0
  SET_BIT(PWR->CR3, PWR_CR3_EIWF);
 8000970:	4b05      	ldr	r3, [pc, #20]	; (8000988 <LL_PWR_EnableInternWU+0x1c>)
 8000972:	689b      	ldr	r3, [r3, #8]
 8000974:	4a04      	ldr	r2, [pc, #16]	; (8000988 <LL_PWR_EnableInternWU+0x1c>)
 8000976:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
 800097a:	6093      	str	r3, [r2, #8]
}
 800097c:	bf00      	nop
 800097e:	46bd      	mov	sp, r7
 8000980:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000984:	4770      	bx	lr
 8000986:	bf00      	nop
 8000988:	40007000 	.word	0x40007000

0800098c <LL_RTC_EnableWriteProtection>:
   * @rmtoll WPR          KEY           LL_RTC_EnableWriteProtection
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
 {
 800098c:	b480      	push	{r7}
 800098e:	b083      	sub	sp, #12
 8000990:	af00      	add	r7, sp, #0
 8000992:	6078      	str	r0, [r7, #4]
   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
 8000994:	687b      	ldr	r3, [r7, #4]
 8000996:	22ff      	movs	r2, #255	; 0xff
 8000998:	625a      	str	r2, [r3, #36]	; 0x24
 }
 800099a:	bf00      	nop
 800099c:	370c      	adds	r7, #12
 800099e:	46bd      	mov	sp, r7
 80009a0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80009a4:	4770      	bx	lr

080009a6 <LL_RTC_DisableWriteProtection>:
   * @rmtoll WPR          KEY           LL_RTC_DisableWriteProtection
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
 {
 80009a6:	b480      	push	{r7}
 80009a8:	b083      	sub	sp, #12
 80009aa:	af00      	add	r7, sp, #0
 80009ac:	6078      	str	r0, [r7, #4]
   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
 80009ae:	687b      	ldr	r3, [r7, #4]
 80009b0:	22ca      	movs	r2, #202	; 0xca
 80009b2:	625a      	str	r2, [r3, #36]	; 0x24
   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
 80009b4:	687b      	ldr	r3, [r7, #4]
 80009b6:	2253      	movs	r2, #83	; 0x53
 80009b8:	625a      	str	r2, [r3, #36]	; 0x24
 }
 80009ba:	bf00      	nop
 80009bc:	370c      	adds	r7, #12
 80009be:	46bd      	mov	sp, r7
 80009c0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80009c4:	4770      	bx	lr

080009c6 <LL_RTC_WAKEUP_Enable>:
   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Enable
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
 {
 80009c6:	b480      	push	{r7}
 80009c8:	b083      	sub	sp, #12
 80009ca:	af00      	add	r7, sp, #0
 80009cc:	6078      	str	r0, [r7, #4]
   SET_BIT(RTCx->CR, RTC_CR_WUTE);
 80009ce:	687b      	ldr	r3, [r7, #4]
 80009d0:	689b      	ldr	r3, [r3, #8]
 80009d2:	f443 6280 	orr.w	r2, r3, #1024	; 0x400
 80009d6:	687b      	ldr	r3, [r7, #4]
 80009d8:	609a      	str	r2, [r3, #8]
 }
 80009da:	bf00      	nop
 80009dc:	370c      	adds	r7, #12
 80009de:	46bd      	mov	sp, r7
 80009e0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80009e4:	4770      	bx	lr

080009e6 <LL_RTC_WAKEUP_Disable>:
   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Disable
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
 {
 80009e6:	b480      	push	{r7}
 80009e8:	b083      	sub	sp, #12
 80009ea:	af00      	add	r7, sp, #0
 80009ec:	6078      	str	r0, [r7, #4]
   CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
 80009ee:	687b      	ldr	r3, [r7, #4]
 80009f0:	689b      	ldr	r3, [r3, #8]
 80009f2:	f423 6280 	bic.w	r2, r3, #1024	; 0x400
 80009f6:	687b      	ldr	r3, [r7, #4]
 80009f8:	609a      	str	r2, [r3, #8]
 }
 80009fa:	bf00      	nop
 80009fc:	370c      	adds	r7, #12
 80009fe:	46bd      	mov	sp, r7
 8000a00:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a04:	4770      	bx	lr

08000a06 <LL_RTC_WAKEUP_SetClock>:
   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
 {
 8000a06:	b480      	push	{r7}
 8000a08:	b083      	sub	sp, #12
 8000a0a:	af00      	add	r7, sp, #0
 8000a0c:	6078      	str	r0, [r7, #4]
 8000a0e:	6039      	str	r1, [r7, #0]
   MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
 8000a10:	687b      	ldr	r3, [r7, #4]
 8000a12:	689b      	ldr	r3, [r3, #8]
 8000a14:	f023 0207 	bic.w	r2, r3, #7
 8000a18:	683b      	ldr	r3, [r7, #0]
 8000a1a:	431a      	orrs	r2, r3
 8000a1c:	687b      	ldr	r3, [r7, #4]
 8000a1e:	609a      	str	r2, [r3, #8]
 }
 8000a20:	bf00      	nop
 8000a22:	370c      	adds	r7, #12
 8000a24:	46bd      	mov	sp, r7
 8000a26:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a2a:	4770      	bx	lr

08000a2c <LL_RTC_WAKEUP_SetAutoReload>:
   * @param  RTCx RTC Instance
   * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
 {
 8000a2c:	b480      	push	{r7}
 8000a2e:	b083      	sub	sp, #12
 8000a30:	af00      	add	r7, sp, #0
 8000a32:	6078      	str	r0, [r7, #4]
 8000a34:	6039      	str	r1, [r7, #0]
   MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
 8000a36:	687b      	ldr	r3, [r7, #4]
 8000a38:	695b      	ldr	r3, [r3, #20]
 8000a3a:	0c1b      	lsrs	r3, r3, #16
 8000a3c:	041b      	lsls	r3, r3, #16
 8000a3e:	683a      	ldr	r2, [r7, #0]
 8000a40:	431a      	orrs	r2, r3
 8000a42:	687b      	ldr	r3, [r7, #4]
 8000a44:	615a      	str	r2, [r3, #20]
 }
 8000a46:	bf00      	nop
 8000a48:	370c      	adds	r7, #12
 8000a4a:	46bd      	mov	sp, r7
 8000a4c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a50:	4770      	bx	lr

08000a52 <LL_RTC_ClearFlag_WUT>:
   * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
 {
 8000a52:	b480      	push	{r7}
 8000a54:	b083      	sub	sp, #12
 8000a56:	af00      	add	r7, sp, #0
 8000a58:	6078      	str	r0, [r7, #4]
   WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
 8000a5a:	687b      	ldr	r3, [r7, #4]
 8000a5c:	68db      	ldr	r3, [r3, #12]
 8000a5e:	b2db      	uxtb	r3, r3
 8000a60:	f463 6290 	orn	r2, r3, #1152	; 0x480
 8000a64:	687b      	ldr	r3, [r7, #4]
 8000a66:	60da      	str	r2, [r3, #12]
 }
 8000a68:	bf00      	nop
 8000a6a:	370c      	adds	r7, #12
 8000a6c:	46bd      	mov	sp, r7
 8000a6e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a72:	4770      	bx	lr

08000a74 <LL_RTC_IsActiveFlag_WUTW>:
   * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
   * @param  RTCx RTC Instance
   * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
 {
 8000a74:	b480      	push	{r7}
 8000a76:	b083      	sub	sp, #12
 8000a78:	af00      	add	r7, sp, #0
 8000a7a:	6078      	str	r0, [r7, #4]
   return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
 8000a7c:	687b      	ldr	r3, [r7, #4]
 8000a7e:	68db      	ldr	r3, [r3, #12]
 8000a80:	f003 0304 	and.w	r3, r3, #4
 8000a84:	2b04      	cmp	r3, #4
 8000a86:	bf0c      	ite	eq
 8000a88:	2301      	moveq	r3, #1
 8000a8a:	2300      	movne	r3, #0
 8000a8c:	b2db      	uxtb	r3, r3
 }
 8000a8e:	4618      	mov	r0, r3
 8000a90:	370c      	adds	r7, #12
 8000a92:	46bd      	mov	sp, r7
 8000a94:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a98:	4770      	bx	lr

08000a9a <LL_RTC_EnableIT_WUT>:
   * @rmtoll CR           WUTIE         LL_RTC_EnableIT_WUT
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
 {
 8000a9a:	b480      	push	{r7}
 8000a9c:	b083      	sub	sp, #12
 8000a9e:	af00      	add	r7, sp, #0
 8000aa0:	6078      	str	r0, [r7, #4]
   SET_BIT(RTCx->CR, RTC_CR_WUTIE);
 8000aa2:	687b      	ldr	r3, [r7, #4]
 8000aa4:	689b      	ldr	r3, [r3, #8]
 8000aa6:	f443 4280 	orr.w	r2, r3, #16384	; 0x4000
 8000aaa:	687b      	ldr	r3, [r7, #4]
 8000aac:	609a      	str	r2, [r3, #8]
 }
 8000aae:	bf00      	nop
 8000ab0:	370c      	adds	r7, #12
 8000ab2:	46bd      	mov	sp, r7
 8000ab4:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000ab8:	4770      	bx	lr
	...

08000abc <SysTick_Handler>:
volatile uint32_t msTicks = 0;
volatile uint8_t expe = 0;
volatile uint8_t blue_mode = 0;

void SysTick_Handler()
{
 8000abc:	b580      	push	{r7, lr}
 8000abe:	af00      	add	r7, sp, #0
	if	( BLUE_BUTTON() ){
 8000ac0:	f7ff fc80 	bl	80003c4 <BLUE_BUTTON>
 8000ac4:	4603      	mov	r3, r0
 8000ac6:	2b00      	cmp	r3, #0
 8000ac8:	d002      	beq.n	8000ad0 <SysTick_Handler+0x14>
		blue_mode = 1 ;
 8000aca:	4b18      	ldr	r3, [pc, #96]	; (8000b2c <SysTick_Handler+0x70>)
 8000acc:	2201      	movs	r2, #1
 8000ace:	701a      	strb	r2, [r3, #0]
	}

	msTicks++;                                                /* See startup file startup_LPC17xx.s for SysTick vector */
 8000ad0:	4b17      	ldr	r3, [pc, #92]	; (8000b30 <SysTick_Handler+0x74>)
 8000ad2:	681b      	ldr	r3, [r3, #0]
 8000ad4:	3301      	adds	r3, #1
 8000ad6:	4a16      	ldr	r2, [pc, #88]	; (8000b30 <SysTick_Handler+0x74>)
 8000ad8:	6013      	str	r3, [r2, #0]
	if (msTicks == 5 * expe){
 8000ada:	4b16      	ldr	r3, [pc, #88]	; (8000b34 <SysTick_Handler+0x78>)
 8000adc:	781b      	ldrb	r3, [r3, #0]
 8000ade:	b2db      	uxtb	r3, r3
 8000ae0:	461a      	mov	r2, r3
 8000ae2:	4613      	mov	r3, r2
 8000ae4:	009b      	lsls	r3, r3, #2
 8000ae6:	4413      	add	r3, r2
 8000ae8:	461a      	mov	r2, r3
 8000aea:	4b11      	ldr	r3, [pc, #68]	; (8000b30 <SysTick_Handler+0x74>)
 8000aec:	681b      	ldr	r3, [r3, #0]
 8000aee:	429a      	cmp	r2, r3
 8000af0:	d103      	bne.n	8000afa <SysTick_Handler+0x3e>
		LED_GREEN(0);
 8000af2:	2000      	movs	r0, #0
 8000af4:	f7ff fc50 	bl	8000398 <LED_GREEN>
 8000af8:	e009      	b.n	8000b0e <SysTick_Handler+0x52>
	}else if(msTicks >= 200){
 8000afa:	4b0d      	ldr	r3, [pc, #52]	; (8000b30 <SysTick_Handler+0x74>)
 8000afc:	681b      	ldr	r3, [r3, #0]
 8000afe:	2bc7      	cmp	r3, #199	; 0xc7
 8000b00:	d905      	bls.n	8000b0e <SysTick_Handler+0x52>
		msTicks = 0;
 8000b02:	4b0b      	ldr	r3, [pc, #44]	; (8000b30 <SysTick_Handler+0x74>)
 8000b04:	2200      	movs	r2, #0
 8000b06:	601a      	str	r2, [r3, #0]
		LED_GREEN(1);
 8000b08:	2001      	movs	r0, #1
 8000b0a:	f7ff fc45 	bl	8000398 <LED_GREEN>
	}
	if(expe == 2 || expe == 4){
 8000b0e:	4b09      	ldr	r3, [pc, #36]	; (8000b34 <SysTick_Handler+0x78>)
 8000b10:	781b      	ldrb	r3, [r3, #0]
 8000b12:	b2db      	uxtb	r3, r3
 8000b14:	2b02      	cmp	r3, #2
 8000b16:	d004      	beq.n	8000b22 <SysTick_Handler+0x66>
 8000b18:	4b06      	ldr	r3, [pc, #24]	; (8000b34 <SysTick_Handler+0x78>)
 8000b1a:	781b      	ldrb	r3, [r3, #0]
 8000b1c:	b2db      	uxtb	r3, r3
 8000b1e:	2b04      	cmp	r3, #4
 8000b20:	d101      	bne.n	8000b26 <SysTick_Handler+0x6a>
		CLK_TOGGLE();
 8000b22:	f7ff fc2d 	bl	8000380 <CLK_TOGGLE>
	}
}
 8000b26:	bf00      	nop
 8000b28:	bd80      	pop	{r7, pc}
 8000b2a:	bf00      	nop
 8000b2c:	2000002d 	.word	0x2000002d
 8000b30:	20000028 	.word	0x20000028
 8000b34:	2000002c 	.word	0x2000002c

08000b38 <main>:




int main(void)
{
 8000b38:	b580      	push	{r7, lr}
 8000b3a:	af00      	add	r7, sp, #0


	// config GPIO
	GPIO_init();
 8000b3c:	f7ff fbfc 	bl	8000338 <GPIO_init>

//	if (RCC->BDCR & RCC_BDCR_LSEON) {
		LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
 8000b40:	f04f 5080 	mov.w	r0, #268435456	; 0x10000000
 8000b44:	f7ff fe2c 	bl	80007a0 <LL_APB1_GRP1_EnableClock>
		LL_PWR_EnableBkUpAccess();
 8000b48:	f7ff fedc 	bl	8000904 <LL_PWR_EnableBkUpAccess>

		//expe = register RTC
		expe = RTC->BKP0R;
 8000b4c:	4b62      	ldr	r3, [pc, #392]	; (8000cd8 <main+0x1a0>)
 8000b4e:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8000b50:	b2da      	uxtb	r2, r3
 8000b52:	4b62      	ldr	r3, [pc, #392]	; (8000cdc <main+0x1a4>)
 8000b54:	701a      	strb	r2, [r3, #0]
		if (expe == 0) {
 8000b56:	4b61      	ldr	r3, [pc, #388]	; (8000cdc <main+0x1a4>)
 8000b58:	781b      	ldrb	r3, [r3, #0]
 8000b5a:	b2db      	uxtb	r3, r3
 8000b5c:	2b00      	cmp	r3, #0
 8000b5e:	d10f      	bne.n	8000b80 <main+0x48>
			SystemClock_Config_24M_LSE();
 8000b60:	f000 f928 	bl	8000db4 <SystemClock_Config_24M_LSE>
			expe = 1;
 8000b64:	4b5d      	ldr	r3, [pc, #372]	; (8000cdc <main+0x1a4>)
 8000b66:	2201      	movs	r2, #1
 8000b68:	701a      	strb	r2, [r3, #0]
			LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
 8000b6a:	f04f 5080 	mov.w	r0, #268435456	; 0x10000000
 8000b6e:	f7ff fe17 	bl	80007a0 <LL_APB1_GRP1_EnableClock>
			LL_PWR_EnableBkUpAccess();
 8000b72:	f7ff fec7 	bl	8000904 <LL_PWR_EnableBkUpAccess>
			RTC->BKP0R = expe;
 8000b76:	4b59      	ldr	r3, [pc, #356]	; (8000cdc <main+0x1a4>)
 8000b78:	781b      	ldrb	r3, [r3, #0]
 8000b7a:	b2da      	uxtb	r2, r3
 8000b7c:	4b56      	ldr	r3, [pc, #344]	; (8000cd8 <main+0x1a0>)
 8000b7e:	651a      	str	r2, [r3, #80]	; 0x50
		}

		if (BLUE_BUTTON()){
 8000b80:	f7ff fc20 	bl	80003c4 <BLUE_BUTTON>
 8000b84:	4603      	mov	r3, r0
 8000b86:	2b00      	cmp	r3, #0
 8000b88:	d016      	beq.n	8000bb8 <main+0x80>

			expe ++;
 8000b8a:	4b54      	ldr	r3, [pc, #336]	; (8000cdc <main+0x1a4>)
 8000b8c:	781b      	ldrb	r3, [r3, #0]
 8000b8e:	b2db      	uxtb	r3, r3
 8000b90:	3301      	adds	r3, #1
 8000b92:	b2da      	uxtb	r2, r3
 8000b94:	4b51      	ldr	r3, [pc, #324]	; (8000cdc <main+0x1a4>)
 8000b96:	701a      	strb	r2, [r3, #0]
			blue_mode = 0;
 8000b98:	4b51      	ldr	r3, [pc, #324]	; (8000ce0 <main+0x1a8>)
 8000b9a:	2200      	movs	r2, #0
 8000b9c:	701a      	strb	r2, [r3, #0]
			if (expe > 8) expe = 1;
 8000b9e:	4b4f      	ldr	r3, [pc, #316]	; (8000cdc <main+0x1a4>)
 8000ba0:	781b      	ldrb	r3, [r3, #0]
 8000ba2:	b2db      	uxtb	r3, r3
 8000ba4:	2b08      	cmp	r3, #8
 8000ba6:	d902      	bls.n	8000bae <main+0x76>
 8000ba8:	4b4c      	ldr	r3, [pc, #304]	; (8000cdc <main+0x1a4>)
 8000baa:	2201      	movs	r2, #1
 8000bac:	701a      	strb	r2, [r3, #0]
			RTC->BKP0R = expe;
 8000bae:	4b4b      	ldr	r3, [pc, #300]	; (8000cdc <main+0x1a4>)
 8000bb0:	781b      	ldrb	r3, [r3, #0]
 8000bb2:	b2da      	uxtb	r2, r3
 8000bb4:	4b48      	ldr	r3, [pc, #288]	; (8000cd8 <main+0x1a0>)
 8000bb6:	651a      	str	r2, [r3, #80]	; 0x50
		}
//	}else{

//	}
	LL_PWR_DisableBkUpAccess();
 8000bb8:	f7ff feb4 	bl	8000924 <LL_PWR_DisableBkUpAccess>
	switch(expe){
 8000bbc:	4b47      	ldr	r3, [pc, #284]	; (8000cdc <main+0x1a4>)
 8000bbe:	781b      	ldrb	r3, [r3, #0]
 8000bc0:	b2db      	uxtb	r3, r3
 8000bc2:	3b01      	subs	r3, #1
 8000bc4:	2b07      	cmp	r3, #7
 8000bc6:	d83a      	bhi.n	8000c3e <main+0x106>
 8000bc8:	a201      	add	r2, pc, #4	; (adr r2, 8000bd0 <main+0x98>)
 8000bca:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8000bce:	bf00      	nop
 8000bd0:	08000bf1 	.word	0x08000bf1
 8000bd4:	08000bfb 	.word	0x08000bfb
 8000bd8:	08000c01 	.word	0x08000c01
 8000bdc:	08000c0b 	.word	0x08000c0b
 8000be0:	08000c0f 	.word	0x08000c0f
 8000be4:	08000c1b 	.word	0x08000c1b
 8000be8:	08000c27 	.word	0x08000c27
 8000bec:	08000c33 	.word	0x08000c33
	case 1:

		/* Configure the system clock */
		SystemClock_Config_80M();
 8000bf0:	f000 f946 	bl	8000e80 <SystemClock_Config_80M>
		//Setup Sleep mode
		LL_LPM_EnableSleep();
 8000bf4:	f7ff fe52 	bl	800089c <LL_LPM_EnableSleep>
		break;
 8000bf8:	e021      	b.n	8000c3e <main+0x106>
	case 2:
		/* Configure the system clock */
		SystemClock_Config_24M_LSE();
 8000bfa:	f000 f8db 	bl	8000db4 <SystemClock_Config_24M_LSE>
		break;
 8000bfe:	e01e      	b.n	8000c3e <main+0x106>
	case 3:
		SystemClock_Config_24M_LSE_FL3_VS2();
 8000c00:	f000 f872 	bl	8000ce8 <SystemClock_Config_24M_LSE_FL3_VS2>
		LL_LPM_EnableSleep();
 8000c04:	f7ff fe4a 	bl	800089c <LL_LPM_EnableSleep>
		break;
 8000c08:	e019      	b.n	8000c3e <main+0x106>
	case 4:
		SystemClock_Config_24M_LSE_FL3_VS2();
 8000c0a:	f000 f86d 	bl	8000ce8 <SystemClock_Config_24M_LSE_FL3_VS2>
	case 5:
		SystemClock_Config_24M_LSE_FL3_VS2();
 8000c0e:	f000 f86b 	bl	8000ce8 <SystemClock_Config_24M_LSE_FL3_VS2>
		LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0);
 8000c12:	2000      	movs	r0, #0
 8000c14:	f7ff fe96 	bl	8000944 <LL_PWR_SetPowerMode>
		break;
 8000c18:	e011      	b.n	8000c3e <main+0x106>
	case 6:
		SystemClock_Config_24M_LSE_FL3_VS2();
 8000c1a:	f000 f865 	bl	8000ce8 <SystemClock_Config_24M_LSE_FL3_VS2>
		LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
 8000c1e:	2001      	movs	r0, #1
 8000c20:	f7ff fe90 	bl	8000944 <LL_PWR_SetPowerMode>
		break;
 8000c24:	e00b      	b.n	8000c3e <main+0x106>
	case 7:
		SystemClock_Config_24M_LSE_FL3_VS2();
 8000c26:	f000 f85f 	bl	8000ce8 <SystemClock_Config_24M_LSE_FL3_VS2>
		LL_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
 8000c2a:	2002      	movs	r0, #2
 8000c2c:	f7ff fe8a 	bl	8000944 <LL_PWR_SetPowerMode>
		break;
 8000c30:	e005      	b.n	8000c3e <main+0x106>
	case 8:
		SystemClock_Config_24M_LSE_FL3_VS2();
 8000c32:	f000 f859 	bl	8000ce8 <SystemClock_Config_24M_LSE_FL3_VS2>
		LL_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
 8000c36:	2004      	movs	r0, #4
 8000c38:	f7ff fe84 	bl	8000944 <LL_PWR_SetPowerMode>
		break;
 8000c3c:	bf00      	nop
	}


	// init systick timer (tick period at 1 ms)
	LL_Init1msTick( SystemCoreClock );
 8000c3e:	4b29      	ldr	r3, [pc, #164]	; (8000ce4 <main+0x1ac>)
 8000c40:	681b      	ldr	r3, [r3, #0]
 8000c42:	4618      	mov	r0, r3
 8000c44:	f000 fb58 	bl	80012f8 <LL_Init1msTick>
	LL_SYSTICK_EnableIT();
 8000c48:	f7ff fe18 	bl	800087c <LL_SYSTICK_EnableIT>


	//LL_LPM_EnableSleepOnExit();

	while (1)  {
		if (blue_mode){
 8000c4c:	4b24      	ldr	r3, [pc, #144]	; (8000ce0 <main+0x1a8>)
 8000c4e:	781b      	ldrb	r3, [r3, #0]
 8000c50:	b2db      	uxtb	r3, r3
 8000c52:	2b00      	cmp	r3, #0
 8000c54:	d036      	beq.n	8000cc4 <main+0x18c>
			switch(expe){
 8000c56:	4b21      	ldr	r3, [pc, #132]	; (8000cdc <main+0x1a4>)
 8000c58:	781b      	ldrb	r3, [r3, #0]
 8000c5a:	b2db      	uxtb	r3, r3
 8000c5c:	3b01      	subs	r3, #1
 8000c5e:	2b07      	cmp	r3, #7
 8000c60:	d8f4      	bhi.n	8000c4c <main+0x114>
 8000c62:	a201      	add	r2, pc, #4	; (adr r2, 8000c68 <main+0x130>)
 8000c64:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8000c68:	08000cb9 	.word	0x08000cb9
 8000c6c:	08000cbd 	.word	0x08000cbd
 8000c70:	08000cb9 	.word	0x08000cb9
 8000c74:	08000cbd 	.word	0x08000cbd
 8000c78:	08000c89 	.word	0x08000c89
 8000c7c:	08000c89 	.word	0x08000c89
 8000c80:	08000c89 	.word	0x08000c89
 8000c84:	08000caf 	.word	0x08000caf
			case 5:
			case 6:
			case 7:
				LL_LPM_EnableDeepSleep();
 8000c88:	f7ff fe18 	bl	80008bc <LL_LPM_EnableDeepSleep>
				RTC_wakeup_init_from_stop(20);
 8000c8c:	2014      	movs	r0, #20
 8000c8e:	f000 f97c 	bl	8000f8a <RTC_wakeup_init_from_stop>
				__WFI();
 8000c92:	bf30      	wfi
				blue_mode = 0;
 8000c94:	4b12      	ldr	r3, [pc, #72]	; (8000ce0 <main+0x1a8>)
 8000c96:	2200      	movs	r2, #0
 8000c98:	701a      	strb	r2, [r3, #0]

				SystemClock_Config_24M_LSE_FL3_VS2();
 8000c9a:	f000 f825 	bl	8000ce8 <SystemClock_Config_24M_LSE_FL3_VS2>
				LL_Init1msTick( SystemCoreClock );
 8000c9e:	4b11      	ldr	r3, [pc, #68]	; (8000ce4 <main+0x1ac>)
 8000ca0:	681b      	ldr	r3, [r3, #0]
 8000ca2:	4618      	mov	r0, r3
 8000ca4:	f000 fb28 	bl	80012f8 <LL_Init1msTick>
				LL_SYSTICK_EnableIT();
 8000ca8:	f7ff fde8 	bl	800087c <LL_SYSTICK_EnableIT>
				break;
 8000cac:	e012      	b.n	8000cd4 <main+0x19c>
			case 8:
				LL_LPM_EnableDeepSleep();
 8000cae:	f7ff fe05 	bl	80008bc <LL_LPM_EnableDeepSleep>
				RTC_wakeup_init_from_standby_or_shutdown(10);
 8000cb2:	200a      	movs	r0, #10
 8000cb4:	f000 f95c 	bl	8000f70 <RTC_wakeup_init_from_standby_or_shutdown>
			case 1:
			case 3:
				__WFI();
 8000cb8:	bf30      	wfi
				break;
 8000cba:	e00b      	b.n	8000cd4 <main+0x19c>
			case 2:
			case 4:
				LL_RCC_MSI_EnablePLLMode();
 8000cbc:	f7ff fc3a 	bl	8000534 <LL_RCC_MSI_EnablePLLMode>
				break;
 8000cc0:	bf00      	nop
 8000cc2:	e007      	b.n	8000cd4 <main+0x19c>
			}
		}else{
				if (expe > 4) {
 8000cc4:	4b05      	ldr	r3, [pc, #20]	; (8000cdc <main+0x1a4>)
 8000cc6:	781b      	ldrb	r3, [r3, #0]
 8000cc8:	b2db      	uxtb	r3, r3
 8000cca:	2b04      	cmp	r3, #4
 8000ccc:	d9be      	bls.n	8000c4c <main+0x114>
					LL_LPM_EnableSleep();
 8000cce:	f7ff fde5 	bl	800089c <LL_LPM_EnableSleep>
					__WFI();
 8000cd2:	bf30      	wfi
		if (blue_mode){
 8000cd4:	e7ba      	b.n	8000c4c <main+0x114>
 8000cd6:	bf00      	nop
 8000cd8:	40002800 	.word	0x40002800
 8000cdc:	2000002c 	.word	0x2000002c
 8000ce0:	2000002d 	.word	0x2000002d
 8000ce4:	20000000 	.word	0x20000000

08000ce8 <SystemClock_Config_24M_LSE_FL3_VS2>:
				}
		}
	}
}

void SystemClock_Config_24M_LSE_FL3_VS2(void){
 8000ce8:	b580      	push	{r7, lr}
 8000cea:	af00      	add	r7, sp, #0
	LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
 8000cec:	f04f 5080 	mov.w	r0, #268435456	; 0x10000000
 8000cf0:	f7ff fd56 	bl	80007a0 <LL_APB1_GRP1_EnableClock>
	LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
 8000cf4:	2003      	movs	r0, #3
 8000cf6:	f7ff fd6b 	bl	80007d0 <LL_FLASH_SetLatency>
	while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_3)
 8000cfa:	bf00      	nop
 8000cfc:	f7ff fd7c 	bl	80007f8 <LL_FLASH_GetLatency>
 8000d00:	4603      	mov	r3, r0
 8000d02:	2b03      	cmp	r3, #3
 8000d04:	d1fa      	bne.n	8000cfc <SystemClock_Config_24M_LSE_FL3_VS2+0x14>
	{
	}
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
 8000d06:	f44f 6080 	mov.w	r0, #1024	; 0x400
 8000d0a:	f7ff fde7 	bl	80008dc <LL_PWR_SetRegulVoltageScaling>
	LL_RCC_MSI_Enable();
 8000d0e:	f7ff fbef 	bl	80004f0 <LL_RCC_MSI_Enable>

	/* Wait till MSI is ready */
	while(LL_RCC_MSI_IsReady() != 1)
 8000d12:	bf00      	nop
 8000d14:	f7ff fbfc 	bl	8000510 <LL_RCC_MSI_IsReady>
 8000d18:	4603      	mov	r3, r0
 8000d1a:	2b01      	cmp	r3, #1
 8000d1c:	d1fa      	bne.n	8000d14 <SystemClock_Config_24M_LSE_FL3_VS2+0x2c>
	{

	}

	LL_PWR_EnableBkUpAccess();
 8000d1e:	f7ff fdf1 	bl	8000904 <LL_PWR_EnableBkUpAccess>
//	LL_RCC_ForceBackupDomainReset();
	LL_RCC_ReleaseBackupDomainReset();
 8000d22:	f7ff fcd7 	bl	80006d4 <LL_RCC_ReleaseBackupDomainReset>
	LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW);
 8000d26:	2000      	movs	r0, #0
 8000d28:	f7ff fbb8 	bl	800049c <LL_RCC_LSE_SetDriveCapability>

	LL_RCC_MSI_EnableRangeSelection();
 8000d2c:	f7ff fc12 	bl	8000554 <LL_RCC_MSI_EnableRangeSelection>
	LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
 8000d30:	2060      	movs	r0, #96	; 0x60
 8000d32:	f7ff fc1f 	bl	8000574 <LL_RCC_MSI_SetRange>
	LL_RCC_MSI_SetCalibTrimming(0);
 8000d36:	2000      	movs	r0, #0
 8000d38:	f7ff fc30 	bl	800059c <LL_RCC_MSI_SetCalibTrimming>
	//  LL_RCC_MSI_EnablePLLMode();

	LL_RCC_LSE_Enable();
 8000d3c:	f7ff fb9c 	bl	8000478 <LL_RCC_LSE_Enable>

	/* Wait till LSE is ready */
	while(LL_RCC_LSE_IsReady() != 1)
 8000d40:	bf00      	nop
 8000d42:	f7ff fbc1 	bl	80004c8 <LL_RCC_LSE_IsReady>
 8000d46:	4603      	mov	r3, r0
 8000d48:	2b01      	cmp	r3, #1
 8000d4a:	d1fa      	bne.n	8000d42 <SystemClock_Config_24M_LSE_FL3_VS2+0x5a>
	{

	}
	LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
 8000d4c:	f44f 7080 	mov.w	r0, #256	; 0x100
 8000d50:	f7ff fc98 	bl	8000684 <LL_RCC_SetRTCClockSource>
	LL_RCC_EnableRTC();
 8000d54:	f7ff fcac 	bl	80006b0 <LL_RCC_EnableRTC>

	LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 24, LL_RCC_PLLR_DIV_4);
 8000d58:	f04f 7300 	mov.w	r3, #33554432	; 0x2000000
 8000d5c:	2218      	movs	r2, #24
 8000d5e:	2100      	movs	r1, #0
 8000d60:	2001      	movs	r0, #1
 8000d62:	f7ff fced 	bl	8000740 <LL_RCC_PLL_ConfigDomain_SYS>
	LL_RCC_PLL_EnableDomain_SYS();
 8000d66:	f7ff fd0b 	bl	8000780 <LL_RCC_PLL_EnableDomain_SYS>
	LL_RCC_PLL_Enable();
 8000d6a:	f7ff fcc5 	bl	80006f8 <LL_RCC_PLL_Enable>

	/* Wait till PLL is ready */
	while(LL_RCC_PLL_IsReady() != 1)
 8000d6e:	bf00      	nop
 8000d70:	f7ff fcd2 	bl	8000718 <LL_RCC_PLL_IsReady>
 8000d74:	4603      	mov	r3, r0
 8000d76:	2b01      	cmp	r3, #1
 8000d78:	d1fa      	bne.n	8000d70 <SystemClock_Config_24M_LSE_FL3_VS2+0x88>
	{

	}
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
 8000d7a:	2003      	movs	r0, #3
 8000d7c:	f7ff fc24 	bl	80005c8 <LL_RCC_SetSysClkSource>

	/* Wait till System clock is ready */
	while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
 8000d80:	bf00      	nop
 8000d82:	f7ff fc35 	bl	80005f0 <LL_RCC_GetSysClkSource>
 8000d86:	4603      	mov	r3, r0
 8000d88:	2b0c      	cmp	r3, #12
 8000d8a:	d1fa      	bne.n	8000d82 <SystemClock_Config_24M_LSE_FL3_VS2+0x9a>
	{

	}
	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
 8000d8c:	2000      	movs	r0, #0
 8000d8e:	f7ff fc3d 	bl	800060c <LL_RCC_SetAHBPrescaler>
	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
 8000d92:	2000      	movs	r0, #0
 8000d94:	f7ff fc4e 	bl	8000634 <LL_RCC_SetAPB1Prescaler>
	LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
 8000d98:	2000      	movs	r0, #0
 8000d9a:	f7ff fc5f 	bl	800065c <LL_RCC_SetAPB2Prescaler>
	LL_SetSystemCoreClock(24000000);
 8000d9e:	4804      	ldr	r0, [pc, #16]	; (8000db0 <SystemClock_Config_24M_LSE_FL3_VS2+0xc8>)
 8000da0:	f000 fab6 	bl	8001310 <LL_SetSystemCoreClock>

	/* Update the time base */
	if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
 8000da4:	2000      	movs	r0, #0
 8000da6:	f000 f99b 	bl	80010e0 <HAL_InitTick>
	{
		//    Error_Handler();
	}
}
 8000daa:	bf00      	nop
 8000dac:	bd80      	pop	{r7, pc}
 8000dae:	bf00      	nop
 8000db0:	016e3600 	.word	0x016e3600

08000db4 <SystemClock_Config_24M_LSE>:
 * @brief System Clock Configuration
 * @retval None
 * 24Mhz + RTC + LSE
 */
void SystemClock_Config_24M_LSE(void)
{
 8000db4:	b580      	push	{r7, lr}
 8000db6:	af00      	add	r7, sp, #0
	LL_APB1_GRP1_EnableClock( LL_APB1_GRP1_PERIPH_PWR );
 8000db8:	f04f 5080 	mov.w	r0, #268435456	; 0x10000000
 8000dbc:	f7ff fcf0 	bl	80007a0 <LL_APB1_GRP1_EnableClock>
	LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
 8000dc0:	2001      	movs	r0, #1
 8000dc2:	f7ff fd05 	bl	80007d0 <LL_FLASH_SetLatency>
	while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_1)
 8000dc6:	bf00      	nop
 8000dc8:	f7ff fd16 	bl	80007f8 <LL_FLASH_GetLatency>
 8000dcc:	4603      	mov	r3, r0
 8000dce:	2b01      	cmp	r3, #1
 8000dd0:	d1fa      	bne.n	8000dc8 <SystemClock_Config_24M_LSE+0x14>
	{
	}
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
 8000dd2:	f44f 7000 	mov.w	r0, #512	; 0x200
 8000dd6:	f7ff fd81 	bl	80008dc <LL_PWR_SetRegulVoltageScaling>
	LL_RCC_MSI_Enable();
 8000dda:	f7ff fb89 	bl	80004f0 <LL_RCC_MSI_Enable>

	/* Wait till MSI is ready */
	while(LL_RCC_MSI_IsReady() != 1)
 8000dde:	bf00      	nop
 8000de0:	f7ff fb96 	bl	8000510 <LL_RCC_MSI_IsReady>
 8000de4:	4603      	mov	r3, r0
 8000de6:	2b01      	cmp	r3, #1
 8000de8:	d1fa      	bne.n	8000de0 <SystemClock_Config_24M_LSE+0x2c>
	{

	}

	LL_PWR_EnableBkUpAccess();
 8000dea:	f7ff fd8b 	bl	8000904 <LL_PWR_EnableBkUpAccess>
//	LL_RCC_ForceBackupDomainReset();
	LL_RCC_ReleaseBackupDomainReset();
 8000dee:	f7ff fc71 	bl	80006d4 <LL_RCC_ReleaseBackupDomainReset>
	LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW);
 8000df2:	2000      	movs	r0, #0
 8000df4:	f7ff fb52 	bl	800049c <LL_RCC_LSE_SetDriveCapability>

	LL_RCC_MSI_EnableRangeSelection();
 8000df8:	f7ff fbac 	bl	8000554 <LL_RCC_MSI_EnableRangeSelection>
	LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
 8000dfc:	2060      	movs	r0, #96	; 0x60
 8000dfe:	f7ff fbb9 	bl	8000574 <LL_RCC_MSI_SetRange>
	LL_RCC_MSI_SetCalibTrimming(0);
 8000e02:	2000      	movs	r0, #0
 8000e04:	f7ff fbca 	bl	800059c <LL_RCC_MSI_SetCalibTrimming>
	//  LL_RCC_MSI_EnablePLLMode();

	LL_RCC_LSE_Enable();
 8000e08:	f7ff fb36 	bl	8000478 <LL_RCC_LSE_Enable>

	/* Wait till LSE is ready */
	while(LL_RCC_LSE_IsReady() != 1)
 8000e0c:	bf00      	nop
 8000e0e:	f7ff fb5b 	bl	80004c8 <LL_RCC_LSE_IsReady>
 8000e12:	4603      	mov	r3, r0
 8000e14:	2b01      	cmp	r3, #1
 8000e16:	d1fa      	bne.n	8000e0e <SystemClock_Config_24M_LSE+0x5a>
	{

	}
	LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
 8000e18:	f44f 7080 	mov.w	r0, #256	; 0x100
 8000e1c:	f7ff fc32 	bl	8000684 <LL_RCC_SetRTCClockSource>
	LL_RCC_EnableRTC();
 8000e20:	f7ff fc46 	bl	80006b0 <LL_RCC_EnableRTC>

	LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 24, LL_RCC_PLLR_DIV_4);
 8000e24:	f04f 7300 	mov.w	r3, #33554432	; 0x2000000
 8000e28:	2218      	movs	r2, #24
 8000e2a:	2100      	movs	r1, #0
 8000e2c:	2001      	movs	r0, #1
 8000e2e:	f7ff fc87 	bl	8000740 <LL_RCC_PLL_ConfigDomain_SYS>
	LL_RCC_PLL_EnableDomain_SYS();
 8000e32:	f7ff fca5 	bl	8000780 <LL_RCC_PLL_EnableDomain_SYS>
	LL_RCC_PLL_Enable();
 8000e36:	f7ff fc5f 	bl	80006f8 <LL_RCC_PLL_Enable>

	/* Wait till PLL is ready */
	while(LL_RCC_PLL_IsReady() != 1)
 8000e3a:	bf00      	nop
 8000e3c:	f7ff fc6c 	bl	8000718 <LL_RCC_PLL_IsReady>
 8000e40:	4603      	mov	r3, r0
 8000e42:	2b01      	cmp	r3, #1
 8000e44:	d1fa      	bne.n	8000e3c <SystemClock_Config_24M_LSE+0x88>
	{

	}
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
 8000e46:	2003      	movs	r0, #3
 8000e48:	f7ff fbbe 	bl	80005c8 <LL_RCC_SetSysClkSource>

	/* Wait till System clock is ready */
	while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
 8000e4c:	bf00      	nop
 8000e4e:	f7ff fbcf 	bl	80005f0 <LL_RCC_GetSysClkSource>
 8000e52:	4603      	mov	r3, r0
 8000e54:	2b0c      	cmp	r3, #12
 8000e56:	d1fa      	bne.n	8000e4e <SystemClock_Config_24M_LSE+0x9a>
	{

	}
	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
 8000e58:	2000      	movs	r0, #0
 8000e5a:	f7ff fbd7 	bl	800060c <LL_RCC_SetAHBPrescaler>
	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
 8000e5e:	2000      	movs	r0, #0
 8000e60:	f7ff fbe8 	bl	8000634 <LL_RCC_SetAPB1Prescaler>
	LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
 8000e64:	2000      	movs	r0, #0
 8000e66:	f7ff fbf9 	bl	800065c <LL_RCC_SetAPB2Prescaler>
	LL_SetSystemCoreClock(24000000);
 8000e6a:	4804      	ldr	r0, [pc, #16]	; (8000e7c <SystemClock_Config_24M_LSE+0xc8>)
 8000e6c:	f000 fa50 	bl	8001310 <LL_SetSystemCoreClock>

	/* Update the time base */
	if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
 8000e70:	2000      	movs	r0, #0
 8000e72:	f000 f935 	bl	80010e0 <HAL_InitTick>
	{
		//    Error_Handler();
	}
}
 8000e76:	bf00      	nop
 8000e78:	bd80      	pop	{r7, pc}
 8000e7a:	bf00      	nop
 8000e7c:	016e3600 	.word	0x016e3600

08000e80 <SystemClock_Config_80M>:


void SystemClock_Config_80M(void)
{
 8000e80:	b580      	push	{r7, lr}
 8000e82:	af00      	add	r7, sp, #0
	LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
 8000e84:	2004      	movs	r0, #4
 8000e86:	f7ff fca3 	bl	80007d0 <LL_FLASH_SetLatency>
	while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4)
 8000e8a:	bf00      	nop
 8000e8c:	f7ff fcb4 	bl	80007f8 <LL_FLASH_GetLatency>
 8000e90:	4603      	mov	r3, r0
 8000e92:	2b04      	cmp	r3, #4
 8000e94:	d1fa      	bne.n	8000e8c <SystemClock_Config_80M+0xc>
	{
	}
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
 8000e96:	f44f 7000 	mov.w	r0, #512	; 0x200
 8000e9a:	f7ff fd1f 	bl	80008dc <LL_PWR_SetRegulVoltageScaling>
	LL_RCC_MSI_Enable();
 8000e9e:	f7ff fb27 	bl	80004f0 <LL_RCC_MSI_Enable>

	/* Wait till MSI is ready */
	while(LL_RCC_MSI_IsReady() != 1)
 8000ea2:	bf00      	nop
 8000ea4:	f7ff fb34 	bl	8000510 <LL_RCC_MSI_IsReady>
 8000ea8:	4603      	mov	r3, r0
 8000eaa:	2b01      	cmp	r3, #1
 8000eac:	d1fa      	bne.n	8000ea4 <SystemClock_Config_80M+0x24>
	{

	}
	LL_RCC_MSI_EnableRangeSelection();
 8000eae:	f7ff fb51 	bl	8000554 <LL_RCC_MSI_EnableRangeSelection>
	LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
 8000eb2:	2060      	movs	r0, #96	; 0x60
 8000eb4:	f7ff fb5e 	bl	8000574 <LL_RCC_MSI_SetRange>
	LL_RCC_MSI_SetCalibTrimming(0);
 8000eb8:	2000      	movs	r0, #0
 8000eba:	f7ff fb6f 	bl	800059c <LL_RCC_MSI_SetCalibTrimming>
	LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);
 8000ebe:	2300      	movs	r3, #0
 8000ec0:	2228      	movs	r2, #40	; 0x28
 8000ec2:	2100      	movs	r1, #0
 8000ec4:	2001      	movs	r0, #1
 8000ec6:	f7ff fc3b 	bl	8000740 <LL_RCC_PLL_ConfigDomain_SYS>
	LL_RCC_PLL_EnableDomain_SYS();
 8000eca:	f7ff fc59 	bl	8000780 <LL_RCC_PLL_EnableDomain_SYS>
	LL_RCC_PLL_Enable();
 8000ece:	f7ff fc13 	bl	80006f8 <LL_RCC_PLL_Enable>

	/* Wait till PLL is ready */
	while(LL_RCC_PLL_IsReady() != 1)
 8000ed2:	bf00      	nop
 8000ed4:	f7ff fc20 	bl	8000718 <LL_RCC_PLL_IsReady>
 8000ed8:	4603      	mov	r3, r0
 8000eda:	2b01      	cmp	r3, #1
 8000edc:	d1fa      	bne.n	8000ed4 <SystemClock_Config_80M+0x54>
	{

	}
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
 8000ede:	2003      	movs	r0, #3
 8000ee0:	f7ff fb72 	bl	80005c8 <LL_RCC_SetSysClkSource>

	/* Wait till System clock is ready */
	while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
 8000ee4:	bf00      	nop
 8000ee6:	f7ff fb83 	bl	80005f0 <LL_RCC_GetSysClkSource>
 8000eea:	4603      	mov	r3, r0
 8000eec:	2b0c      	cmp	r3, #12
 8000eee:	d1fa      	bne.n	8000ee6 <SystemClock_Config_80M+0x66>
	{

	}
	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
 8000ef0:	2000      	movs	r0, #0
 8000ef2:	f7ff fb8b 	bl	800060c <LL_RCC_SetAHBPrescaler>
	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
 8000ef6:	2000      	movs	r0, #0
 8000ef8:	f7ff fb9c 	bl	8000634 <LL_RCC_SetAPB1Prescaler>
	LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
 8000efc:	2000      	movs	r0, #0
 8000efe:	f7ff fbad 	bl	800065c <LL_RCC_SetAPB2Prescaler>
	LL_SetSystemCoreClock(80000000);
 8000f02:	4804      	ldr	r0, [pc, #16]	; (8000f14 <SystemClock_Config_80M+0x94>)
 8000f04:	f000 fa04 	bl	8001310 <LL_SetSystemCoreClock>

	/* Update the time base */
	if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
 8000f08:	2000      	movs	r0, #0
 8000f0a:	f000 f8e9 	bl	80010e0 <HAL_InitTick>
	{
		//    Error_Handler();
	}
}
 8000f0e:	bf00      	nop
 8000f10:	bd80      	pop	{r7, pc}
 8000f12:	bf00      	nop
 8000f14:	04c4b400 	.word	0x04c4b400

08000f18 <RTC_wakeup_init>:

// partie commune a toutes les utilisations du wakeup timer
static void RTC_wakeup_init( int delay )
{
 8000f18:	b580      	push	{r7, lr}
 8000f1a:	b082      	sub	sp, #8
 8000f1c:	af00      	add	r7, sp, #0
 8000f1e:	6078      	str	r0, [r7, #4]
LL_RTC_DisableWriteProtection( RTC );
 8000f20:	4812      	ldr	r0, [pc, #72]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f22:	f7ff fd40 	bl	80009a6 <LL_RTC_DisableWriteProtection>
LL_RTC_WAKEUP_Disable( RTC );
 8000f26:	4811      	ldr	r0, [pc, #68]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f28:	f7ff fd5d 	bl	80009e6 <LL_RTC_WAKEUP_Disable>
while	( !LL_RTC_IsActiveFlag_WUTW( RTC ) )
 8000f2c:	bf00      	nop
 8000f2e:	480f      	ldr	r0, [pc, #60]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f30:	f7ff fda0 	bl	8000a74 <LL_RTC_IsActiveFlag_WUTW>
 8000f34:	4603      	mov	r3, r0
 8000f36:	2b00      	cmp	r3, #0
 8000f38:	d0f9      	beq.n	8000f2e <RTC_wakeup_init+0x16>
	{ }
// connecter le timer a l'horloge 1Hz de la RTC
LL_RTC_WAKEUP_SetClock( RTC, LL_RTC_WAKEUPCLOCK_CKSPRE );
 8000f3a:	2104      	movs	r1, #4
 8000f3c:	480b      	ldr	r0, [pc, #44]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f3e:	f7ff fd62 	bl	8000a06 <LL_RTC_WAKEUP_SetClock>
// fixer la duree de temporisation
LL_RTC_WAKEUP_SetAutoReload( RTC, delay );	// 16 bits
 8000f42:	687b      	ldr	r3, [r7, #4]
 8000f44:	4619      	mov	r1, r3
 8000f46:	4809      	ldr	r0, [pc, #36]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f48:	f7ff fd70 	bl	8000a2c <LL_RTC_WAKEUP_SetAutoReload>
LL_RTC_ClearFlag_WUT(RTC);
 8000f4c:	4807      	ldr	r0, [pc, #28]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f4e:	f7ff fd80 	bl	8000a52 <LL_RTC_ClearFlag_WUT>
LL_RTC_EnableIT_WUT(RTC);
 8000f52:	4806      	ldr	r0, [pc, #24]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f54:	f7ff fda1 	bl	8000a9a <LL_RTC_EnableIT_WUT>
LL_RTC_WAKEUP_Enable(RTC);
 8000f58:	4804      	ldr	r0, [pc, #16]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f5a:	f7ff fd34 	bl	80009c6 <LL_RTC_WAKEUP_Enable>
LL_RTC_EnableWriteProtection(RTC);
 8000f5e:	4803      	ldr	r0, [pc, #12]	; (8000f6c <RTC_wakeup_init+0x54>)
 8000f60:	f7ff fd14 	bl	800098c <LL_RTC_EnableWriteProtection>
}
 8000f64:	bf00      	nop
 8000f66:	3708      	adds	r7, #8
 8000f68:	46bd      	mov	sp, r7
 8000f6a:	bd80      	pop	{r7, pc}
 8000f6c:	40002800 	.word	0x40002800

08000f70 <RTC_wakeup_init_from_standby_or_shutdown>:

// Dans le cas des modes STANDBY et SHUTDOWN, le MPU sera reveille par reset
// causé par 1 wakeup line (interne ou externe) (le NVIC n'est plus alimenté)
void RTC_wakeup_init_from_standby_or_shutdown( int delay )
{
 8000f70:	b580      	push	{r7, lr}
 8000f72:	b082      	sub	sp, #8
 8000f74:	af00      	add	r7, sp, #0
 8000f76:	6078      	str	r0, [r7, #4]
RTC_wakeup_init( delay );
 8000f78:	6878      	ldr	r0, [r7, #4]
 8000f7a:	f7ff ffcd 	bl	8000f18 <RTC_wakeup_init>
// enable the Internal Wake-up line
LL_PWR_EnableInternWU();	// ceci ne concerne que Standby et Shutdown, pas STOPx
 8000f7e:	f7ff fcf5 	bl	800096c <LL_PWR_EnableInternWU>
}
 8000f82:	bf00      	nop
 8000f84:	3708      	adds	r7, #8
 8000f86:	46bd      	mov	sp, r7
 8000f88:	bd80      	pop	{r7, pc}

08000f8a <RTC_wakeup_init_from_stop>:
// Dans le cas des modes STOPx, le MPU sera reveille par interruption
// le module EXTI et une partie du NVIC sont encore alimentes
// le contenu de la RAM et des registres étant préservé, le MPU
// reprend l'execution après l'instruction WFI
void RTC_wakeup_init_from_stop( int delay )
{
 8000f8a:	b580      	push	{r7, lr}
 8000f8c:	b082      	sub	sp, #8
 8000f8e:	af00      	add	r7, sp, #0
 8000f90:	6078      	str	r0, [r7, #4]
RTC_wakeup_init( delay );
 8000f92:	6878      	ldr	r0, [r7, #4]
 8000f94:	f7ff ffc0 	bl	8000f18 <RTC_wakeup_init>
// valider l'interrupt par la ligne 20 du module EXTI, qui est réservée au wakeup timer
LL_EXTI_EnableIT_0_31( LL_EXTI_LINE_20 );
 8000f98:	f44f 1080 	mov.w	r0, #1048576	; 0x100000
 8000f9c:	f7ff fc3a 	bl	8000814 <LL_EXTI_EnableIT_0_31>
LL_EXTI_EnableRisingTrig_0_31( LL_EXTI_LINE_20 );
 8000fa0:	f44f 1080 	mov.w	r0, #1048576	; 0x100000
 8000fa4:	f7ff fc48 	bl	8000838 <LL_EXTI_EnableRisingTrig_0_31>
// valider l'interrupt chez NVIC
NVIC_SetPriority( RTC_WKUP_IRQn, 1 );
 8000fa8:	2101      	movs	r1, #1
 8000faa:	2003      	movs	r0, #3
 8000fac:	f7ff fa3a 	bl	8000424 <__NVIC_SetPriority>
NVIC_EnableIRQ( RTC_WKUP_IRQn );
 8000fb0:	2003      	movs	r0, #3
 8000fb2:	f7ff fa19 	bl	80003e8 <__NVIC_EnableIRQ>
}
 8000fb6:	bf00      	nop
 8000fb8:	3708      	adds	r7, #8
 8000fba:	46bd      	mov	sp, r7
 8000fbc:	bd80      	pop	{r7, pc}

08000fbe <RTC_WKUP_IRQHandler>:

// wakeup timer interrupt Handler (inutile mais doit etre defini)
void RTC_WKUP_IRQHandler()
{
 8000fbe:	b580      	push	{r7, lr}
 8000fc0:	af00      	add	r7, sp, #0
LL_EXTI_ClearFlag_0_31( LL_EXTI_LINE_20 );
 8000fc2:	f44f 1080 	mov.w	r0, #1048576	; 0x100000
 8000fc6:	f7ff fc49 	bl	800085c <LL_EXTI_ClearFlag_0_31>
}
 8000fca:	bf00      	nop
 8000fcc:	bd80      	pop	{r7, pc}

08000fce <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8000fce:	b480      	push	{r7}
 8000fd0:	af00      	add	r7, sp, #0

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */

  /* USER CODE END NonMaskableInt_IRQn 1 */
}
 8000fd2:	bf00      	nop
 8000fd4:	46bd      	mov	sp, r7
 8000fd6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000fda:	4770      	bx	lr

08000fdc <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8000fdc:	b480      	push	{r7}
 8000fde:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8000fe0:	e7fe      	b.n	8000fe0 <HardFault_Handler+0x4>

08000fe2 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8000fe2:	b480      	push	{r7}
 8000fe4:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8000fe6:	e7fe      	b.n	8000fe6 <MemManage_Handler+0x4>

08000fe8 <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8000fe8:	b480      	push	{r7}
 8000fea:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8000fec:	e7fe      	b.n	8000fec <BusFault_Handler+0x4>

08000fee <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8000fee:	b480      	push	{r7}
 8000ff0:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8000ff2:	e7fe      	b.n	8000ff2 <UsageFault_Handler+0x4>

08000ff4 <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8000ff4:	b480      	push	{r7}
 8000ff6:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 8000ff8:	bf00      	nop
 8000ffa:	46bd      	mov	sp, r7
 8000ffc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001000:	4770      	bx	lr

08001002 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8001002:	b480      	push	{r7}
 8001004:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8001006:	bf00      	nop
 8001008:	46bd      	mov	sp, r7
 800100a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800100e:	4770      	bx	lr

08001010 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8001010:	b480      	push	{r7}
 8001012:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8001014:	bf00      	nop
 8001016:	46bd      	mov	sp, r7
 8001018:	f85d 7b04 	ldr.w	r7, [sp], #4
 800101c:	4770      	bx	lr
	...

08001020 <SystemInit>:
  * @param  None
  * @retval None
  */

void SystemInit(void)
{
 8001020:	b480      	push	{r7}
 8001022:	af00      	add	r7, sp, #0
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 8001024:	4b17      	ldr	r3, [pc, #92]	; (8001084 <SystemInit+0x64>)
 8001026:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 800102a:	4a16      	ldr	r2, [pc, #88]	; (8001084 <SystemInit+0x64>)
 800102c:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 8001030:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
  #endif

  /* Reset the RCC clock configuration to the default reset state ------------*/
  /* Set MSION bit */
  RCC->CR |= RCC_CR_MSION;
 8001034:	4b14      	ldr	r3, [pc, #80]	; (8001088 <SystemInit+0x68>)
 8001036:	681b      	ldr	r3, [r3, #0]
 8001038:	4a13      	ldr	r2, [pc, #76]	; (8001088 <SystemInit+0x68>)
 800103a:	f043 0301 	orr.w	r3, r3, #1
 800103e:	6013      	str	r3, [r2, #0]

  /* Reset CFGR register */
  RCC->CFGR = 0x00000000U;
 8001040:	4b11      	ldr	r3, [pc, #68]	; (8001088 <SystemInit+0x68>)
 8001042:	2200      	movs	r2, #0
 8001044:	609a      	str	r2, [r3, #8]

  /* Reset HSEON, CSSON , HSION, and PLLON bits */
  RCC->CR &= 0xEAF6FFFFU;
 8001046:	4b10      	ldr	r3, [pc, #64]	; (8001088 <SystemInit+0x68>)
 8001048:	681b      	ldr	r3, [r3, #0]
 800104a:	4a0f      	ldr	r2, [pc, #60]	; (8001088 <SystemInit+0x68>)
 800104c:	f023 53a8 	bic.w	r3, r3, #352321536	; 0x15000000
 8001050:	f423 2310 	bic.w	r3, r3, #589824	; 0x90000
 8001054:	6013      	str	r3, [r2, #0]

  /* Reset PLLCFGR register */
  RCC->PLLCFGR = 0x00001000U;
 8001056:	4b0c      	ldr	r3, [pc, #48]	; (8001088 <SystemInit+0x68>)
 8001058:	f44f 5280 	mov.w	r2, #4096	; 0x1000
 800105c:	60da      	str	r2, [r3, #12]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 800105e:	4b0a      	ldr	r3, [pc, #40]	; (8001088 <SystemInit+0x68>)
 8001060:	681b      	ldr	r3, [r3, #0]
 8001062:	4a09      	ldr	r2, [pc, #36]	; (8001088 <SystemInit+0x68>)
 8001064:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8001068:	6013      	str	r3, [r2, #0]

  /* Disable all interrupts */
  RCC->CIER = 0x00000000U;
 800106a:	4b07      	ldr	r3, [pc, #28]	; (8001088 <SystemInit+0x68>)
 800106c:	2200      	movs	r2, #0
 800106e:	619a      	str	r2, [r3, #24]

  /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 8001070:	4b04      	ldr	r3, [pc, #16]	; (8001084 <SystemInit+0x64>)
 8001072:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
 8001076:	609a      	str	r2, [r3, #8]
#endif
}
 8001078:	bf00      	nop
 800107a:	46bd      	mov	sp, r7
 800107c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001080:	4770      	bx	lr
 8001082:	bf00      	nop
 8001084:	e000ed00 	.word	0xe000ed00
 8001088:	40021000 	.word	0x40021000

0800108c <Reset_Handler>:

    .section	.text.Reset_Handler
	.weak	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:
  ldr   sp, =_estack    /* Set stack pointer */
 800108c:	f8df d034 	ldr.w	sp, [pc, #52]	; 80010c4 <LoopForever+0x2>

/* Call the clock system initialization function.*/
    bl  SystemInit
 8001090:	f7ff ffc6 	bl	8001020 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  movs	r1, #0
 8001094:	2100      	movs	r1, #0
  b	LoopCopyDataInit
 8001096:	e003      	b.n	80010a0 <LoopCopyDataInit>

08001098 <CopyDataInit>:

CopyDataInit:
	ldr	r3, =_sidata
 8001098:	4b0b      	ldr	r3, [pc, #44]	; (80010c8 <LoopForever+0x6>)
	ldr	r3, [r3, r1]
 800109a:	585b      	ldr	r3, [r3, r1]
	str	r3, [r0, r1]
 800109c:	5043      	str	r3, [r0, r1]
	adds	r1, r1, #4
 800109e:	3104      	adds	r1, #4

080010a0 <LoopCopyDataInit>:

LoopCopyDataInit:
	ldr	r0, =_sdata
 80010a0:	480a      	ldr	r0, [pc, #40]	; (80010cc <LoopForever+0xa>)
	ldr	r3, =_edata
 80010a2:	4b0b      	ldr	r3, [pc, #44]	; (80010d0 <LoopForever+0xe>)
	adds	r2, r0, r1
 80010a4:	1842      	adds	r2, r0, r1
	cmp	r2, r3
 80010a6:	429a      	cmp	r2, r3
	bcc	CopyDataInit
 80010a8:	d3f6      	bcc.n	8001098 <CopyDataInit>
	ldr	r2, =_sbss
 80010aa:	4a0a      	ldr	r2, [pc, #40]	; (80010d4 <LoopForever+0x12>)
	b	LoopFillZerobss
 80010ac:	e002      	b.n	80010b4 <LoopFillZerobss>

080010ae <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
	movs	r3, #0
 80010ae:	2300      	movs	r3, #0
	str	r3, [r2], #4
 80010b0:	f842 3b04 	str.w	r3, [r2], #4

080010b4 <LoopFillZerobss>:

LoopFillZerobss:
	ldr	r3, = _ebss
 80010b4:	4b08      	ldr	r3, [pc, #32]	; (80010d8 <LoopForever+0x16>)
	cmp	r2, r3
 80010b6:	429a      	cmp	r2, r3
	bcc	FillZerobss
 80010b8:	d3f9      	bcc.n	80010ae <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 80010ba:	f000 f939 	bl	8001330 <__libc_init_array>
/* Call the application's entry point.*/
	bl	main
 80010be:	f7ff fd3b 	bl	8000b38 <main>

080010c2 <LoopForever>:

LoopForever:
    b LoopForever
 80010c2:	e7fe      	b.n	80010c2 <LoopForever>
  ldr   sp, =_estack    /* Set stack pointer */
 80010c4:	20018000 	.word	0x20018000
	ldr	r3, =_sidata
 80010c8:	08001398 	.word	0x08001398
	ldr	r0, =_sdata
 80010cc:	20000000 	.word	0x20000000
	ldr	r3, =_edata
 80010d0:	2000000c 	.word	0x2000000c
	ldr	r2, =_sbss
 80010d4:	2000000c 	.word	0x2000000c
	ldr	r3, = _ebss
 80010d8:	20000030 	.word	0x20000030

080010dc <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section	.text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
	b	Infinite_Loop
 80010dc:	e7fe      	b.n	80010dc <ADC1_2_IRQHandler>
	...

080010e0 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority  Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 80010e0:	b580      	push	{r7, lr}
 80010e2:	b084      	sub	sp, #16
 80010e4:	af00      	add	r7, sp, #0
 80010e6:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef  status = HAL_OK;
 80010e8:	2300      	movs	r3, #0
 80010ea:	73fb      	strb	r3, [r7, #15]

  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
  if ((uint32_t)uwTickFreq != 0U)
 80010ec:	4b17      	ldr	r3, [pc, #92]	; (800114c <HAL_InitTick+0x6c>)
 80010ee:	781b      	ldrb	r3, [r3, #0]
 80010f0:	2b00      	cmp	r3, #0
 80010f2:	d023      	beq.n	800113c <HAL_InitTick+0x5c>
  {
    /*Configure the SysTick to have interrupt in 1ms time basis*/
    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
 80010f4:	4b16      	ldr	r3, [pc, #88]	; (8001150 <HAL_InitTick+0x70>)
 80010f6:	681a      	ldr	r2, [r3, #0]
 80010f8:	4b14      	ldr	r3, [pc, #80]	; (800114c <HAL_InitTick+0x6c>)
 80010fa:	781b      	ldrb	r3, [r3, #0]
 80010fc:	4619      	mov	r1, r3
 80010fe:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8001102:	fbb3 f3f1 	udiv	r3, r3, r1
 8001106:	fbb2 f3f3 	udiv	r3, r2, r3
 800110a:	4618      	mov	r0, r3
 800110c:	f000 f8ce 	bl	80012ac <HAL_SYSTICK_Config>
 8001110:	4603      	mov	r3, r0
 8001112:	2b00      	cmp	r3, #0
 8001114:	d10f      	bne.n	8001136 <HAL_InitTick+0x56>
    {
      /* Configure the SysTick IRQ priority */
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8001116:	687b      	ldr	r3, [r7, #4]
 8001118:	2b0f      	cmp	r3, #15
 800111a:	d809      	bhi.n	8001130 <HAL_InitTick+0x50>
      {
        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 800111c:	2200      	movs	r2, #0
 800111e:	6879      	ldr	r1, [r7, #4]
 8001120:	f04f 30ff 	mov.w	r0, #4294967295
 8001124:	f000 f8a6 	bl	8001274 <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 8001128:	4a0a      	ldr	r2, [pc, #40]	; (8001154 <HAL_InitTick+0x74>)
 800112a:	687b      	ldr	r3, [r7, #4]
 800112c:	6013      	str	r3, [r2, #0]
 800112e:	e007      	b.n	8001140 <HAL_InitTick+0x60>
      }
      else
      {
        status = HAL_ERROR;
 8001130:	2301      	movs	r3, #1
 8001132:	73fb      	strb	r3, [r7, #15]
 8001134:	e004      	b.n	8001140 <HAL_InitTick+0x60>
      }
    }
    else
    {
      status = HAL_ERROR;
 8001136:	2301      	movs	r3, #1
 8001138:	73fb      	strb	r3, [r7, #15]
 800113a:	e001      	b.n	8001140 <HAL_InitTick+0x60>
    }
  }
  else
  {
    status = HAL_ERROR;
 800113c:	2301      	movs	r3, #1
 800113e:	73fb      	strb	r3, [r7, #15]
  }

  /* Return function status */
  return status;
 8001140:	7bfb      	ldrb	r3, [r7, #15]
}
 8001142:	4618      	mov	r0, r3
 8001144:	3710      	adds	r7, #16
 8001146:	46bd      	mov	sp, r7
 8001148:	bd80      	pop	{r7, pc}
 800114a:	bf00      	nop
 800114c:	20000008 	.word	0x20000008
 8001150:	20000000 	.word	0x20000000
 8001154:	20000004 	.word	0x20000004

08001158 <__NVIC_GetPriorityGrouping>:
{
 8001158:	b480      	push	{r7}
 800115a:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 800115c:	4b04      	ldr	r3, [pc, #16]	; (8001170 <__NVIC_GetPriorityGrouping+0x18>)
 800115e:	68db      	ldr	r3, [r3, #12]
 8001160:	0a1b      	lsrs	r3, r3, #8
 8001162:	f003 0307 	and.w	r3, r3, #7
}
 8001166:	4618      	mov	r0, r3
 8001168:	46bd      	mov	sp, r7
 800116a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800116e:	4770      	bx	lr
 8001170:	e000ed00 	.word	0xe000ed00

08001174 <__NVIC_SetPriority>:
{
 8001174:	b480      	push	{r7}
 8001176:	b083      	sub	sp, #12
 8001178:	af00      	add	r7, sp, #0
 800117a:	4603      	mov	r3, r0
 800117c:	6039      	str	r1, [r7, #0]
 800117e:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8001180:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001184:	2b00      	cmp	r3, #0
 8001186:	db0a      	blt.n	800119e <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8001188:	683b      	ldr	r3, [r7, #0]
 800118a:	b2da      	uxtb	r2, r3
 800118c:	490c      	ldr	r1, [pc, #48]	; (80011c0 <__NVIC_SetPriority+0x4c>)
 800118e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001192:	0112      	lsls	r2, r2, #4
 8001194:	b2d2      	uxtb	r2, r2
 8001196:	440b      	add	r3, r1
 8001198:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
}
 800119c:	e00a      	b.n	80011b4 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800119e:	683b      	ldr	r3, [r7, #0]
 80011a0:	b2da      	uxtb	r2, r3
 80011a2:	4908      	ldr	r1, [pc, #32]	; (80011c4 <__NVIC_SetPriority+0x50>)
 80011a4:	79fb      	ldrb	r3, [r7, #7]
 80011a6:	f003 030f 	and.w	r3, r3, #15
 80011aa:	3b04      	subs	r3, #4
 80011ac:	0112      	lsls	r2, r2, #4
 80011ae:	b2d2      	uxtb	r2, r2
 80011b0:	440b      	add	r3, r1
 80011b2:	761a      	strb	r2, [r3, #24]
}
 80011b4:	bf00      	nop
 80011b6:	370c      	adds	r7, #12
 80011b8:	46bd      	mov	sp, r7
 80011ba:	f85d 7b04 	ldr.w	r7, [sp], #4
 80011be:	4770      	bx	lr
 80011c0:	e000e100 	.word	0xe000e100
 80011c4:	e000ed00 	.word	0xe000ed00

080011c8 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 80011c8:	b480      	push	{r7}
 80011ca:	b089      	sub	sp, #36	; 0x24
 80011cc:	af00      	add	r7, sp, #0
 80011ce:	60f8      	str	r0, [r7, #12]
 80011d0:	60b9      	str	r1, [r7, #8]
 80011d2:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 80011d4:	68fb      	ldr	r3, [r7, #12]
 80011d6:	f003 0307 	and.w	r3, r3, #7
 80011da:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 80011dc:	69fb      	ldr	r3, [r7, #28]
 80011de:	f1c3 0307 	rsb	r3, r3, #7
 80011e2:	2b04      	cmp	r3, #4
 80011e4:	bf28      	it	cs
 80011e6:	2304      	movcs	r3, #4
 80011e8:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 80011ea:	69fb      	ldr	r3, [r7, #28]
 80011ec:	3304      	adds	r3, #4
 80011ee:	2b06      	cmp	r3, #6
 80011f0:	d902      	bls.n	80011f8 <NVIC_EncodePriority+0x30>
 80011f2:	69fb      	ldr	r3, [r7, #28]
 80011f4:	3b03      	subs	r3, #3
 80011f6:	e000      	b.n	80011fa <NVIC_EncodePriority+0x32>
 80011f8:	2300      	movs	r3, #0
 80011fa:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80011fc:	f04f 32ff 	mov.w	r2, #4294967295
 8001200:	69bb      	ldr	r3, [r7, #24]
 8001202:	fa02 f303 	lsl.w	r3, r2, r3
 8001206:	43da      	mvns	r2, r3
 8001208:	68bb      	ldr	r3, [r7, #8]
 800120a:	401a      	ands	r2, r3
 800120c:	697b      	ldr	r3, [r7, #20]
 800120e:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8001210:	f04f 31ff 	mov.w	r1, #4294967295
 8001214:	697b      	ldr	r3, [r7, #20]
 8001216:	fa01 f303 	lsl.w	r3, r1, r3
 800121a:	43d9      	mvns	r1, r3
 800121c:	687b      	ldr	r3, [r7, #4]
 800121e:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8001220:	4313      	orrs	r3, r2
         );
}
 8001222:	4618      	mov	r0, r3
 8001224:	3724      	adds	r7, #36	; 0x24
 8001226:	46bd      	mov	sp, r7
 8001228:	f85d 7b04 	ldr.w	r7, [sp], #4
 800122c:	4770      	bx	lr
	...

08001230 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 8001230:	b580      	push	{r7, lr}
 8001232:	b082      	sub	sp, #8
 8001234:	af00      	add	r7, sp, #0
 8001236:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8001238:	687b      	ldr	r3, [r7, #4]
 800123a:	3b01      	subs	r3, #1
 800123c:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
 8001240:	d301      	bcc.n	8001246 <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 8001242:	2301      	movs	r3, #1
 8001244:	e00f      	b.n	8001266 <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8001246:	4a0a      	ldr	r2, [pc, #40]	; (8001270 <SysTick_Config+0x40>)
 8001248:	687b      	ldr	r3, [r7, #4]
 800124a:	3b01      	subs	r3, #1
 800124c:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 800124e:	210f      	movs	r1, #15
 8001250:	f04f 30ff 	mov.w	r0, #4294967295
 8001254:	f7ff ff8e 	bl	8001174 <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8001258:	4b05      	ldr	r3, [pc, #20]	; (8001270 <SysTick_Config+0x40>)
 800125a:	2200      	movs	r2, #0
 800125c:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 800125e:	4b04      	ldr	r3, [pc, #16]	; (8001270 <SysTick_Config+0x40>)
 8001260:	2207      	movs	r2, #7
 8001262:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 8001264:	2300      	movs	r3, #0
}
 8001266:	4618      	mov	r0, r3
 8001268:	3708      	adds	r7, #8
 800126a:	46bd      	mov	sp, r7
 800126c:	bd80      	pop	{r7, pc}
 800126e:	bf00      	nop
 8001270:	e000e010 	.word	0xe000e010

08001274 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8001274:	b580      	push	{r7, lr}
 8001276:	b086      	sub	sp, #24
 8001278:	af00      	add	r7, sp, #0
 800127a:	4603      	mov	r3, r0
 800127c:	60b9      	str	r1, [r7, #8]
 800127e:	607a      	str	r2, [r7, #4]
 8001280:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00;
 8001282:	2300      	movs	r3, #0
 8001284:	617b      	str	r3, [r7, #20]

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();
 8001286:	f7ff ff67 	bl	8001158 <__NVIC_GetPriorityGrouping>
 800128a:	6178      	str	r0, [r7, #20]

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 800128c:	687a      	ldr	r2, [r7, #4]
 800128e:	68b9      	ldr	r1, [r7, #8]
 8001290:	6978      	ldr	r0, [r7, #20]
 8001292:	f7ff ff99 	bl	80011c8 <NVIC_EncodePriority>
 8001296:	4602      	mov	r2, r0
 8001298:	f997 300f 	ldrsb.w	r3, [r7, #15]
 800129c:	4611      	mov	r1, r2
 800129e:	4618      	mov	r0, r3
 80012a0:	f7ff ff68 	bl	8001174 <__NVIC_SetPriority>
}
 80012a4:	bf00      	nop
 80012a6:	3718      	adds	r7, #24
 80012a8:	46bd      	mov	sp, r7
 80012aa:	bd80      	pop	{r7, pc}

080012ac <HAL_SYSTICK_Config>:
  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 80012ac:	b580      	push	{r7, lr}
 80012ae:	b082      	sub	sp, #8
 80012b0:	af00      	add	r7, sp, #0
 80012b2:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 80012b4:	6878      	ldr	r0, [r7, #4]
 80012b6:	f7ff ffbb 	bl	8001230 <SysTick_Config>
 80012ba:	4603      	mov	r3, r0
}
 80012bc:	4618      	mov	r0, r3
 80012be:	3708      	adds	r7, #8
 80012c0:	46bd      	mov	sp, r7
 80012c2:	bd80      	pop	{r7, pc}

080012c4 <LL_InitTick>:
  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
  * @param  Ticks Number of ticks
  * @retval None
  */
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
 80012c4:	b480      	push	{r7}
 80012c6:	b083      	sub	sp, #12
 80012c8:	af00      	add	r7, sp, #0
 80012ca:	6078      	str	r0, [r7, #4]
 80012cc:	6039      	str	r1, [r7, #0]
  /* Configure the SysTick to have interrupt in 1ms time base */
  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
 80012ce:	687a      	ldr	r2, [r7, #4]
 80012d0:	683b      	ldr	r3, [r7, #0]
 80012d2:	fbb2 f3f3 	udiv	r3, r2, r3
 80012d6:	4a07      	ldr	r2, [pc, #28]	; (80012f4 <LL_InitTick+0x30>)
 80012d8:	3b01      	subs	r3, #1
 80012da:	6053      	str	r3, [r2, #4]
  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
 80012dc:	4b05      	ldr	r3, [pc, #20]	; (80012f4 <LL_InitTick+0x30>)
 80012de:	2200      	movs	r2, #0
 80012e0:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80012e2:	4b04      	ldr	r3, [pc, #16]	; (80012f4 <LL_InitTick+0x30>)
 80012e4:	2205      	movs	r2, #5
 80012e6:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
}
 80012e8:	bf00      	nop
 80012ea:	370c      	adds	r7, #12
 80012ec:	46bd      	mov	sp, r7
 80012ee:	f85d 7b04 	ldr.w	r7, [sp], #4
 80012f2:	4770      	bx	lr
 80012f4:	e000e010 	.word	0xe000e010

080012f8 <LL_Init1msTick>:
  * @param  HCLKFrequency HCLK frequency in Hz
  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
  * @retval None
  */
void LL_Init1msTick(uint32_t HCLKFrequency)
{
 80012f8:	b580      	push	{r7, lr}
 80012fa:	b082      	sub	sp, #8
 80012fc:	af00      	add	r7, sp, #0
 80012fe:	6078      	str	r0, [r7, #4]
  /* Use frequency provided in argument */
  LL_InitTick(HCLKFrequency, 100U);
 8001300:	2164      	movs	r1, #100	; 0x64
 8001302:	6878      	ldr	r0, [r7, #4]
 8001304:	f7ff ffde 	bl	80012c4 <LL_InitTick>
}
 8001308:	bf00      	nop
 800130a:	3708      	adds	r7, #8
 800130c:	46bd      	mov	sp, r7
 800130e:	bd80      	pop	{r7, pc}

08001310 <LL_SetSystemCoreClock>:
  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
  * @retval None
  */
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
 8001310:	b480      	push	{r7}
 8001312:	b083      	sub	sp, #12
 8001314:	af00      	add	r7, sp, #0
 8001316:	6078      	str	r0, [r7, #4]
  /* HCLK clock frequency */
  SystemCoreClock = HCLKFrequency;
 8001318:	4a04      	ldr	r2, [pc, #16]	; (800132c <LL_SetSystemCoreClock+0x1c>)
 800131a:	687b      	ldr	r3, [r7, #4]
 800131c:	6013      	str	r3, [r2, #0]
}
 800131e:	bf00      	nop
 8001320:	370c      	adds	r7, #12
 8001322:	46bd      	mov	sp, r7
 8001324:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001328:	4770      	bx	lr
 800132a:	bf00      	nop
 800132c:	20000000 	.word	0x20000000

08001330 <__libc_init_array>:
 8001330:	b570      	push	{r4, r5, r6, lr}
 8001332:	4e0d      	ldr	r6, [pc, #52]	; (8001368 <__libc_init_array+0x38>)
 8001334:	4c0d      	ldr	r4, [pc, #52]	; (800136c <__libc_init_array+0x3c>)
 8001336:	1ba4      	subs	r4, r4, r6
 8001338:	10a4      	asrs	r4, r4, #2
 800133a:	2500      	movs	r5, #0
 800133c:	42a5      	cmp	r5, r4
 800133e:	d109      	bne.n	8001354 <__libc_init_array+0x24>
 8001340:	4e0b      	ldr	r6, [pc, #44]	; (8001370 <__libc_init_array+0x40>)
 8001342:	4c0c      	ldr	r4, [pc, #48]	; (8001374 <__libc_init_array+0x44>)
 8001344:	f000 f818 	bl	8001378 <_init>
 8001348:	1ba4      	subs	r4, r4, r6
 800134a:	10a4      	asrs	r4, r4, #2
 800134c:	2500      	movs	r5, #0
 800134e:	42a5      	cmp	r5, r4
 8001350:	d105      	bne.n	800135e <__libc_init_array+0x2e>
 8001352:	bd70      	pop	{r4, r5, r6, pc}
 8001354:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8001358:	4798      	blx	r3
 800135a:	3501      	adds	r5, #1
 800135c:	e7ee      	b.n	800133c <__libc_init_array+0xc>
 800135e:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8001362:	4798      	blx	r3
 8001364:	3501      	adds	r5, #1
 8001366:	e7f2      	b.n	800134e <__libc_init_array+0x1e>
 8001368:	08001390 	.word	0x08001390
 800136c:	08001390 	.word	0x08001390
 8001370:	08001390 	.word	0x08001390
 8001374:	08001394 	.word	0x08001394

08001378 <_init>:
 8001378:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800137a:	bf00      	nop
 800137c:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800137e:	bc08      	pop	{r3}
 8001380:	469e      	mov	lr, r3
 8001382:	4770      	bx	lr

08001384 <_fini>:
 8001384:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001386:	bf00      	nop
 8001388:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800138a:	bc08      	pop	{r3}
 800138c:	469e      	mov	lr, r3
 800138e:	4770      	bx	lr
