From 4e10472c3363df581900bb9aeb60719ae9a093eb Mon Sep 17 00:00:00 2001 From: vezde Date: Thu, 15 Sep 2022 15:44:21 +0200 Subject: [PATCH] premiers modules du firwmare dumber 3 --- .../dumber-v3/Gerber/dumber-v3-B_Adhesive.gbr | 176 + .../Gerber/dumber-v3-B_Courtyard.gbr | 821 + .../dumber-v3/Gerber/dumber-v3-B_Cu.gbr | 16455 +++++++++++ .../dumber-v3/Gerber/dumber-v3-B_Fab.gbr | 5758 ++++ .../dumber-v3/Gerber/dumber-v3-B_Mask.gbr | 685 + .../dumber-v3/Gerber/dumber-v3-B_Paste.gbr | 605 + .../Gerber/dumber-v3-B_Silkscreen.gbr | 2816 ++ .../dumber-v3/Gerber/dumber-v3-Edge_Cuts.gbr | 175 + .../dumber-v3/Gerber/dumber-v3-F_Adhesive.gbr | 176 + .../Gerber/dumber-v3-F_Courtyard.gbr | 414 + .../dumber-v3/Gerber/dumber-v3-F_Cu.gbr | 1433 + .../dumber-v3/Gerber/dumber-v3-F_Fab.gbr | 2405 ++ .../dumber-v3/Gerber/dumber-v3-F_Mask.gbr | 330 + .../dumber-v3/Gerber/dumber-v3-F_Paste.gbr | 268 + .../Gerber/dumber-v3-F_Silkscreen.gbr | 717 + .../dumber-v3/Gerber/dumber-v3-NPTH.drl | 13 + .../dumber-v3/Gerber/dumber-v3-PTH.drl | 207 + .../dumber-v3/Gerber/dumber-v3-job.gbrjob | 147 + .../pcb/Dumber-v3/dumber-v3/cpu.kicad_sch | 133 +- .../Dumber-v3/dumber-v3/dumber-v3-B_Cu.pdf | Bin 0 -> 33658 bytes .../dumber-v3/dumber-v3-Edge_Cuts.pdf | Bin 0 -> 3319 bytes .../Dumber-v3/dumber-v3/dumber-v3.kicad_pcb | 18125 ++++++++---- .../Dumber-v3/dumber-v3/dumber-v3.kicad_prl | 2 +- .../Dumber-v3/dumber-v3/dumber-v3.kicad_pro | 2 +- .../Dumber-v3/dumber-v3/dumber-v3.kicad_sch | 27 +- .../pcb/Dumber-v3/dumber-v3/fp-info-cache | 2 +- .../dumber-v3/power_charge.kicad_sch | 79 +- software/dumber3/.cproject | 5 +- .../.settings/stm32cubeide.project.prefs | 1 + software/dumber3/Core/Inc/FreeRTOSConfig.h | 2 +- software/dumber3/Core/Inc/batterie.h | 13 + software/dumber3/Core/Inc/config.h | 18 + software/dumber3/Core/Inc/leds.h | 33 + software/dumber3/Core/Inc/main.h | 10 + software/dumber3/Core/Inc/messages.h | 48 + software/dumber3/Core/Inc/moteurs.h | 15 + software/dumber3/Core/Inc/sequenceur.h | 13 + software/dumber3/Core/Inc/xbee.h | 13 + software/dumber3/Core/Src/batterie.c | 8 + software/dumber3/Core/Src/leds.c | 202 + software/dumber3/Core/Src/main.c | 787 +- software/dumber3/Core/Src/messages.c | 64 + software/dumber3/Core/Src/moteurs.c | 215 + software/dumber3/Core/Src/sequenceur.c | 8 + software/dumber3/Core/Src/xbee.c | 8 + software/dumber3/Debug/Core/Src/batterie.su | 0 software/dumber3/Debug/Core/Src/freertos.su | 2 + software/dumber3/Debug/Core/Src/leds.su | 3 + software/dumber3/Debug/Core/Src/main.su | 12 + software/dumber3/Debug/Core/Src/messages.su | 4 + software/dumber3/Debug/Core/Src/moteurs.su | 8 + software/dumber3/Debug/Core/Src/sequenceur.su | 0 .../dumber3/Debug/Core/Src/statemachine.su | 0 .../Debug/Core/Src/stm32l0xx_hal_msp.su | 12 + .../dumber3/Debug/Core/Src/stm32l0xx_it.su | 7 + software/dumber3/Debug/Core/Src/subdir.mk | 56 + software/dumber3/Debug/Core/Src/syscalls.su | 18 + software/dumber3/Debug/Core/Src/sysmem.su | 1 + .../Debug/Core/Src/system_stm32l0xx.su | 2 + software/dumber3/Debug/Core/Src/xbee.su | 0 software/dumber3/Debug/Core/Startup/subdir.mk | 20 + .../STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su | 31 + .../Src/stm32l0xx_hal_adc.su | 29 + .../Src/stm32l0xx_hal_adc_ex.su | 7 + .../Src/stm32l0xx_hal_cortex.su | 21 + .../Src/stm32l0xx_hal_dma.su | 13 + .../Src/stm32l0xx_hal_exti.su | 9 + .../Src/stm32l0xx_hal_flash.su | 13 + .../Src/stm32l0xx_hal_flash_ex.su | 25 + .../Src/stm32l0xx_hal_flash_ramfunc.su | 6 + .../Src/stm32l0xx_hal_gpio.su | 8 + .../Src/stm32l0xx_hal_i2c.su | 79 + .../Src/stm32l0xx_hal_i2c_ex.su | 4 + .../Src/stm32l0xx_hal_lptim.su | 42 + .../Src/stm32l0xx_hal_pwr.su | 12 + .../Src/stm32l0xx_hal_pwr_ex.su | 7 + .../Src/stm32l0xx_hal_rcc.su | 13 + .../Src/stm32l0xx_hal_rcc_ex.su | 8 + .../Src/stm32l0xx_hal_tim.su | 119 + .../Src/stm32l0xx_hal_tim_ex.su | 2 + .../Src/stm32l0xx_hal_uart.su | 66 + .../Src/stm32l0xx_hal_uart_ex.su | 12 + .../STM32L0xx_HAL_Driver/Src/subdir.mk | 80 + software/dumber3/Debug/Dumber3.bin | Bin 0 -> 31032 bytes software/dumber3/Debug/Dumber3.list | 22798 ++++++++++++++++ software/dumber3/Debug/Dumber3.map | 6594 +++++ .../Source/CMSIS_RTOS_V2/cmsis_os2.su | 66 + .../FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk | 20 + .../Third_Party/FreeRTOS/Source/croutine.su | 0 .../FreeRTOS/Source/event_groups.su | 15 + .../Third_Party/FreeRTOS/Source/list.su | 5 + .../Source/portable/GCC/ARM_CM0/port.su | 15 + .../Source/portable/GCC/ARM_CM0/subdir.mk | 20 + .../Source/portable/MemMang/heap_4.su | 7 + .../Source/portable/MemMang/subdir.mk | 20 + .../Third_Party/FreeRTOS/Source/queue.su | 40 + .../FreeRTOS/Source/stream_buffer.su | 25 + .../Third_Party/FreeRTOS/Source/subdir.mk | 38 + .../Third_Party/FreeRTOS/Source/tasks.su | 66 + .../Third_Party/FreeRTOS/Source/timers.su | 26 + software/dumber3/Debug/makefile | 104 + software/dumber3/Debug/objects.list | 45 + software/dumber3/Debug/objects.mk | 9 + software/dumber3/Debug/sources.mk | 30 + software/dumber3/Dumber3 Debug.launch | 80 + software/dumber3/Dumber3.ioc | 65 +- 106 files changed, 78458 insertions(+), 5815 deletions(-) create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Adhesive.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Courtyard.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Cu.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Fab.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Mask.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Paste.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Silkscreen.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-Edge_Cuts.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Adhesive.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Courtyard.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Cu.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Fab.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Mask.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Paste.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Silkscreen.gbr create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-NPTH.drl create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-PTH.drl create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-job.gbrjob create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-B_Cu.pdf create mode 100644 hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-Edge_Cuts.pdf create mode 100644 software/dumber3/Core/Inc/batterie.h create mode 100644 software/dumber3/Core/Inc/config.h create mode 100644 software/dumber3/Core/Inc/leds.h create mode 100644 software/dumber3/Core/Inc/messages.h create mode 100644 software/dumber3/Core/Inc/moteurs.h create mode 100644 software/dumber3/Core/Inc/sequenceur.h create mode 100644 software/dumber3/Core/Inc/xbee.h create mode 100644 software/dumber3/Core/Src/batterie.c create mode 100644 software/dumber3/Core/Src/leds.c create mode 100644 software/dumber3/Core/Src/messages.c create mode 100644 software/dumber3/Core/Src/moteurs.c create mode 100644 software/dumber3/Core/Src/sequenceur.c create mode 100644 software/dumber3/Core/Src/xbee.c create mode 100644 software/dumber3/Debug/Core/Src/batterie.su create mode 100644 software/dumber3/Debug/Core/Src/freertos.su create mode 100644 software/dumber3/Debug/Core/Src/leds.su create mode 100644 software/dumber3/Debug/Core/Src/main.su create mode 100644 software/dumber3/Debug/Core/Src/messages.su create mode 100644 software/dumber3/Debug/Core/Src/moteurs.su create mode 100644 software/dumber3/Debug/Core/Src/sequenceur.su create mode 100644 software/dumber3/Debug/Core/Src/statemachine.su create mode 100644 software/dumber3/Debug/Core/Src/stm32l0xx_hal_msp.su create mode 100644 software/dumber3/Debug/Core/Src/stm32l0xx_it.su create mode 100644 software/dumber3/Debug/Core/Src/subdir.mk create mode 100644 software/dumber3/Debug/Core/Src/syscalls.su create mode 100644 software/dumber3/Debug/Core/Src/sysmem.su create mode 100644 software/dumber3/Debug/Core/Src/system_stm32l0xx.su create mode 100644 software/dumber3/Debug/Core/Src/xbee.su create mode 100644 software/dumber3/Debug/Core/Startup/subdir.mk create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su create mode 100644 software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk create mode 100755 software/dumber3/Debug/Dumber3.bin create mode 100644 software/dumber3/Debug/Dumber3.list create mode 100644 software/dumber3/Debug/Dumber3.map create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su create mode 100644 software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su create mode 100644 software/dumber3/Debug/makefile create mode 100644 software/dumber3/Debug/objects.list create mode 100644 software/dumber3/Debug/objects.mk create mode 100644 software/dumber3/Debug/sources.mk create mode 100644 software/dumber3/Dumber3 Debug.launch diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Adhesive.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Adhesive.gbr new file mode 100644 index 0000000..19746e0 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Adhesive.gbr @@ -0,0 +1,176 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Glue,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Courtyard.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Courtyard.gbr new file mode 100644 index 0000000..c34f808 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Courtyard.gbr @@ -0,0 +1,821 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Other,User*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12C,0.050000*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.C,D1*% +X136495000Y-102265000D02* +X139095000Y-102265000D01* +X139095000Y-99665000D02* +X136495000Y-99665000D01* +X136495000Y-99665000D02* +X136495000Y-102265000D01* +X139095000Y-99665000D02* +X139095000Y-102265000D01* +%TO.C,C17*% +X155230000Y-104345000D02* +X155230000Y-107745000D01* +X155230000Y-107745000D02* +X157190000Y-107745000D01* +X157190000Y-107745000D02* +X157190000Y-104345000D01* +X157190000Y-104345000D02* +X155230000Y-104345000D01* +%TO.C,R10*% +X176432000Y-80050000D02* +X173072000Y-80050000D01* +X173072000Y-80050000D02* +X173072000Y-81950000D01* +X173072000Y-81950000D02* +X176432000Y-81950000D01* +X176432000Y-81950000D02* +X176432000Y-80050000D01* +%TO.C,U2*% +X153645000Y-109280000D02* +X154245000Y-109280000D01* +X150495000Y-118180000D02* +X153645000Y-118180000D01* +X145345000Y-116180000D02* +X145345000Y-113030000D01* +X153645000Y-116780000D02* +X154245000Y-116780000D01* +X153645000Y-118180000D02* +X153645000Y-116780000D01* +X154245000Y-116780000D02* +X154245000Y-116180000D01* +X147345000Y-109280000D02* +X146745000Y-109280000D01* +X155645000Y-116180000D02* +X155645000Y-113030000D01* +X147345000Y-118180000D02* +X147345000Y-116780000D01* +X146745000Y-116780000D02* +X146745000Y-116180000D01* +X150495000Y-118180000D02* +X147345000Y-118180000D01* +X150495000Y-107880000D02* +X147345000Y-107880000D01* +X155645000Y-109880000D02* +X155645000Y-113030000D01* +X146745000Y-116180000D02* +X145345000Y-116180000D01* +X146745000Y-109280000D02* +X146745000Y-109880000D01* +X154245000Y-116180000D02* +X155645000Y-116180000D01* +X146745000Y-109880000D02* +X145345000Y-109880000D01* +X147345000Y-116780000D02* +X146745000Y-116780000D01* +X145345000Y-109880000D02* +X145345000Y-113030000D01* +X150495000Y-107880000D02* +X153645000Y-107880000D01* +X153645000Y-107880000D02* +X153645000Y-109280000D01* +X154245000Y-109880000D02* +X155645000Y-109880000D01* +X154245000Y-109280000D02* +X154245000Y-109880000D01* +X147345000Y-107880000D02* +X147345000Y-109280000D01* +%TO.C,C4*% +X183805000Y-113870000D02* +X183805000Y-117270000D01* +X183805000Y-117270000D02* +X185765000Y-117270000D01* +X185765000Y-113870000D02* +X183805000Y-113870000D01* +X185765000Y-117270000D02* +X185765000Y-113870000D01* +%TO.C,R7*% +X172945000Y-113980000D02* +X176305000Y-113980000D01* +X176305000Y-112080000D02* +X172945000Y-112080000D01* +X172945000Y-112080000D02* +X172945000Y-113980000D01* +X176305000Y-113980000D02* +X176305000Y-112080000D01* +%TO.C,C20*% +X140625000Y-110060000D02* +X140625000Y-113460000D01* +X140625000Y-113460000D02* +X142585000Y-113460000D01* +X142585000Y-113460000D02* +X142585000Y-110060000D01* +X142585000Y-110060000D02* +X140625000Y-110060000D01* +%TO.C,R17*% +X171225000Y-124140000D02* +X171225000Y-122240000D01* +X171225000Y-122240000D02* +X167865000Y-122240000D01* +X167865000Y-124140000D02* +X171225000Y-124140000D01* +X167865000Y-122240000D02* +X167865000Y-124140000D01* +%TO.C,C6*% +X171975000Y-101255000D02* +X171975000Y-103215000D01* +X175375000Y-103215000D02* +X175375000Y-101255000D01* +X175375000Y-101255000D02* +X171975000Y-101255000D01* +X171975000Y-103215000D02* +X175375000Y-103215000D01* +%TO.C,R3*% +X177932500Y-123505000D02* +X177932500Y-121605000D01* +X174572500Y-123505000D02* +X177932500Y-123505000D01* +X174572500Y-121605000D02* +X174572500Y-123505000D01* +X177932500Y-121605000D02* +X174572500Y-121605000D01* +%TO.C,C19*% +X143800000Y-118000000D02* +X143800000Y-121400000D01* +X143800000Y-121400000D02* +X145760000Y-121400000D01* +X145760000Y-121400000D02* +X145760000Y-118000000D01* +X145760000Y-118000000D02* +X143800000Y-118000000D01* +%TO.C,U3*% +X116060000Y-103300000D02* +X116060000Y-99900000D01* +X116060000Y-99900000D02* +X120160000Y-99900000D01* +X120160000Y-99900000D02* +X120160000Y-103300000D01* +X120160000Y-103300000D02* +X116060000Y-103300000D01* +%TO.C,Q2*% +X129685000Y-110990000D02* +X133205000Y-110990000D01* +X133205000Y-107440000D02* +X133205000Y-110990000D01* +X133205000Y-107440000D02* +X129685000Y-107440000D01* +X129685000Y-110990000D02* +X129685000Y-107440000D01* +%TO.C,R24*% +X133125000Y-111445000D02* +X129765000Y-111445000D01* +X129765000Y-111445000D02* +X129765000Y-113345000D01* +X129765000Y-113345000D02* +X133125000Y-113345000D01* +X133125000Y-113345000D02* +X133125000Y-111445000D01* +%TO.C,R1*% +X129765000Y-103190000D02* +X129765000Y-105090000D01* +X129765000Y-105090000D02* +X133125000Y-105090000D01* +X133125000Y-103190000D02* +X129765000Y-103190000D01* +X133125000Y-105090000D02* +X133125000Y-103190000D01* +%TO.C,C7*% +X183805000Y-128790000D02* +X183805000Y-132190000D01* +X183805000Y-132190000D02* +X185765000Y-132190000D01* +X185765000Y-128790000D02* +X183805000Y-128790000D01* +X185765000Y-132190000D02* +X185765000Y-128790000D01* +%TO.C,R16*% +X115890000Y-122607500D02* +X117790000Y-122607500D01* +X115890000Y-119247500D02* +X115890000Y-122607500D01* +X117790000Y-119247500D02* +X115890000Y-119247500D01* +X117790000Y-122607500D02* +X117790000Y-119247500D01* +%TO.C,R13*% +X179385000Y-111535000D02* +X179385000Y-108175000D01* +X179385000Y-108175000D02* +X177485000Y-108175000D01* +X177485000Y-111535000D02* +X179385000Y-111535000D01* +X177485000Y-108175000D02* +X177485000Y-111535000D01* +%TO.C,U7*% +X153845000Y-103030000D02* +X147145000Y-103030000D01* +X147145000Y-97630000D02* +X147145000Y-103030000D01* +X153845000Y-97630000D02* +X147145000Y-97630000D01* +X153845000Y-97630000D02* +X153845000Y-103030000D01* +%TO.C,R21*% +X176305000Y-114620000D02* +X172945000Y-114620000D01* +X172945000Y-116520000D02* +X176305000Y-116520000D01* +X176305000Y-116520000D02* +X176305000Y-114620000D01* +X172945000Y-114620000D02* +X172945000Y-116520000D01* +%TO.C,C3*% +X187615000Y-104345000D02* +X187615000Y-107745000D01* +X187615000Y-107745000D02* +X189575000Y-107745000D01* +X189575000Y-104345000D02* +X187615000Y-104345000D01* +X189575000Y-107745000D02* +X189575000Y-104345000D01* +%TO.C,R2*% +X120875000Y-101285000D02* +X120875000Y-103185000D01* +X120875000Y-103185000D02* +X124235000Y-103185000D01* +X124235000Y-103185000D02* +X124235000Y-101285000D01* +X124235000Y-101285000D02* +X120875000Y-101285000D01* +%TO.C,JP1*% +X152795000Y-125115000D02* +X152795000Y-127615000D01* +X148195000Y-127615000D02* +X148195000Y-125115000D01* +X148195000Y-127615000D02* +X152795000Y-127615000D01* +X152795000Y-125115000D02* +X148195000Y-125115000D01* +%TO.C,C8*% +X175055000Y-92552500D02* +X175055000Y-90592500D01* +X171655000Y-92552500D02* +X175055000Y-92552500D01* +X171655000Y-90592500D02* +X171655000Y-92552500D01* +X175055000Y-90592500D02* +X171655000Y-90592500D01* +%TO.C,R5*% +X174572500Y-120965000D02* +X177932500Y-120965000D01* +X174572500Y-119065000D02* +X174572500Y-120965000D01* +X177932500Y-120965000D02* +X177932500Y-119065000D01* +X177932500Y-119065000D02* +X174572500Y-119065000D01* +%TO.C,R11*% +X181916500Y-85278000D02* +X181916500Y-83378000D01* +X178556500Y-85278000D02* +X181916500Y-85278000D01* +X181916500Y-83378000D02* +X178556500Y-83378000D01* +X178556500Y-83378000D02* +X178556500Y-85278000D01* +%TO.C,C5*% +X185892000Y-86028000D02* +X185892000Y-82628000D01* +X183932000Y-86028000D02* +X185892000Y-86028000D01* +X185892000Y-82628000D02* +X183932000Y-82628000D01* +X183932000Y-82628000D02* +X183932000Y-86028000D01* +%TO.C,R18*% +X171225000Y-124780000D02* +X167865000Y-124780000D01* +X167865000Y-126680000D02* +X171225000Y-126680000D01* +X171225000Y-126680000D02* +X171225000Y-124780000D01* +X167865000Y-124780000D02* +X167865000Y-126680000D01* +%TO.C,R19*% +X167865000Y-130495000D02* +X167865000Y-132395000D01* +X167865000Y-132395000D02* +X171225000Y-132395000D01* +X171225000Y-130495000D02* +X167865000Y-130495000D01* +X171225000Y-132395000D02* +X171225000Y-130495000D01* +%TO.C,C13*% +X120125000Y-113320000D02* +X116725000Y-113320000D01* +X116725000Y-113320000D02* +X116725000Y-115280000D01* +X120125000Y-115280000D02* +X120125000Y-113320000D01* +X116725000Y-115280000D02* +X120125000Y-115280000D01* +%TO.C,U4*% +X178206400Y-113778600D02* +X178511200Y-113778600D01* +X182168800Y-116091400D02* +X182473600Y-116091400D01* +X179183600Y-116763800D02* +X179183600Y-117068600D01* +X179183600Y-116763800D02* +X178511200Y-116763800D01* +X182168800Y-113778600D02* +X182168800Y-113106200D01* +X178511200Y-116763800D02* +X178511200Y-116091400D01* +X179183600Y-113106200D02* +X178511200Y-113106200D01* +X182168800Y-116763800D02* +X182168800Y-116091400D01* +X181496400Y-116763800D02* +X182168800Y-116763800D01* +X178511200Y-116091400D02* +X178511200Y-116763800D01* +X181496400Y-112801400D02* +X179183600Y-112801400D01* +X182473600Y-113778600D02* +X182168800Y-113778600D01* +X178206400Y-116091400D02* +X178511200Y-116091400D01* +X179183600Y-117068600D02* +X181496400Y-117068600D01* +X182473600Y-116091400D02* +X182473600Y-113778600D01* +X178511200Y-116091400D02* +X178206400Y-116091400D01* +X182168800Y-113106200D02* +X181496400Y-113106200D01* +X181496400Y-117068600D02* +X181496400Y-116763800D01* +X179183600Y-112801400D02* +X179183600Y-113106200D01* +X182168800Y-116763800D02* +X181496400Y-116763800D01* +X178206400Y-116091400D02* +X178206400Y-113778600D01* +X181496400Y-116763800D02* +X181496400Y-117068600D01* +X182168800Y-116763800D02* +X182168800Y-116091400D01* +X179183600Y-117068600D02* +X179183600Y-116763800D01* +X181496400Y-117068600D02* +X179183600Y-117068600D01* +X181496400Y-112801400D02* +X179183600Y-112801400D01* +X181496400Y-113106200D02* +X181496400Y-112801400D01* +X178511200Y-113106200D02* +X178511200Y-113778600D01* +X179183600Y-113106200D02* +X178511200Y-113106200D01* +X181496400Y-113106200D02* +X181496400Y-112801400D01* +X182168800Y-113106200D02* +X181496400Y-113106200D01* +X178511200Y-116763800D02* +X179183600Y-116763800D01* +X178511200Y-113778600D02* +X178206400Y-113778600D01* +X178206400Y-113778600D02* +X178206400Y-116091400D01* +X179183600Y-112801400D02* +X179183600Y-113106200D01* +X182168800Y-113778600D02* +X182168800Y-113106200D01* +X182473600Y-116091400D02* +X182473600Y-113778600D01* +X182168800Y-116091400D02* +X182473600Y-116091400D01* +X182473600Y-113778600D02* +X182168800Y-113778600D01* +X178511200Y-113778600D02* +X178511200Y-113106200D01* +%TO.C,R9*% +X182020000Y-119446000D02* +X178660000Y-119446000D01* +X182020000Y-121346000D02* +X182020000Y-119446000D01* +X178660000Y-121346000D02* +X182020000Y-121346000D01* +X178660000Y-119446000D02* +X178660000Y-121346000D01* +%TO.C,R14*% +X184465000Y-108175000D02* +X182565000Y-108175000D01* +X184465000Y-111535000D02* +X184465000Y-108175000D01* +X182565000Y-108175000D02* +X182565000Y-111535000D01* +X182565000Y-111535000D02* +X184465000Y-111535000D01* +%TO.C,R29*% +X160975000Y-112977500D02* +X160975000Y-116337500D01* +X160975000Y-116337500D02* +X162875000Y-116337500D01* +X162875000Y-112977500D02* +X160975000Y-112977500D01* +X162875000Y-116337500D02* +X162875000Y-112977500D01* +%TO.C,C10*% +X166025000Y-88192500D02* +X167985000Y-88192500D01* +X166025000Y-84792500D02* +X166025000Y-88192500D01* +X167985000Y-88192500D02* +X167985000Y-84792500D01* +X167985000Y-84792500D02* +X166025000Y-84792500D01* +%TO.C,R26*% +X148910000Y-120240000D02* +X148910000Y-123600000D01* +X150810000Y-123600000D02* +X150810000Y-120240000D01* +X150810000Y-120240000D02* +X148910000Y-120240000D01* +X148910000Y-123600000D02* +X150810000Y-123600000D01* +%TO.C,R28*% +X165415000Y-112977500D02* +X163515000Y-112977500D01* +X163515000Y-116337500D02* +X165415000Y-116337500D01* +X165415000Y-116337500D02* +X165415000Y-112977500D01* +X163515000Y-112977500D02* +X163515000Y-116337500D01* +%TO.C,R8*% +X185862000Y-90072000D02* +X185862000Y-86712000D01* +X183962000Y-90072000D02* +X185862000Y-90072000D01* +X183962000Y-86712000D02* +X183962000Y-90072000D01* +X185862000Y-86712000D02* +X183962000Y-86712000D01* +%TO.C,R6*% +X124235000Y-98745000D02* +X120875000Y-98745000D01* +X124235000Y-100645000D02* +X124235000Y-98745000D01* +X120875000Y-100645000D02* +X124235000Y-100645000D01* +X120875000Y-98745000D02* +X120875000Y-100645000D01* +%TO.C,R25*% +X136205000Y-110900000D02* +X136205000Y-107540000D01* +X134305000Y-107540000D02* +X134305000Y-110900000D01* +X134305000Y-110900000D02* +X136205000Y-110900000D01* +X136205000Y-107540000D02* +X134305000Y-107540000D01* +%TO.C,R27*% +X167955000Y-112977500D02* +X166055000Y-112977500D01* +X166055000Y-116337500D02* +X167955000Y-116337500D01* +X166055000Y-112977500D02* +X166055000Y-116337500D01* +X167955000Y-116337500D02* +X167955000Y-112977500D01* +%TO.C,C14*% +X127840000Y-91150000D02* +X131240000Y-91150000D01* +X131240000Y-89190000D02* +X127840000Y-89190000D01* +X131240000Y-91150000D02* +X131240000Y-89190000D01* +X127840000Y-89190000D02* +X127840000Y-91150000D01* +%TO.C,R23*% +X119954000Y-119247500D02* +X119954000Y-122607500D01* +X121854000Y-122607500D02* +X121854000Y-119247500D01* +X119954000Y-122607500D02* +X121854000Y-122607500D01* +X121854000Y-119247500D02* +X119954000Y-119247500D01* +%TO.C,R12*% +X181925000Y-111535000D02* +X181925000Y-108175000D01* +X181925000Y-108175000D02* +X180025000Y-108175000D01* +X180025000Y-108175000D02* +X180025000Y-111535000D01* +X180025000Y-111535000D02* +X181925000Y-111535000D01* +%TO.C,C15*% +X125440000Y-130285000D02* +X125440000Y-126885000D01* +X123480000Y-130285000D02* +X125440000Y-130285000D01* +X123480000Y-126885000D02* +X123480000Y-130285000D01* +X125440000Y-126885000D02* +X123480000Y-126885000D01* +%TO.C,C12*% +X148734000Y-94016000D02* +X148734000Y-95976000D01* +X148734000Y-95976000D02* +X152134000Y-95976000D01* +X152134000Y-94016000D02* +X148734000Y-94016000D01* +X152134000Y-95976000D02* +X152134000Y-94016000D01* +%TO.C,C1*% +X113320000Y-99900000D02* +X113320000Y-103300000D01* +X115280000Y-103300000D02* +X115280000Y-99900000D01* +X113320000Y-103300000D02* +X115280000Y-103300000D01* +X115280000Y-99900000D02* +X113320000Y-99900000D01* +%TO.C,Q1*% +X133205000Y-99185000D02* +X129685000Y-99185000D01* +X129685000Y-102735000D02* +X133205000Y-102735000D01* +X133205000Y-99185000D02* +X133205000Y-102735000D01* +X129685000Y-102735000D02* +X129685000Y-99185000D01* +%TO.C,U6*% +X175690000Y-99972500D02* +X172290000Y-99972500D01* +X172290000Y-99972500D02* +X172290000Y-95872500D01* +X175690000Y-95872500D02* +X175690000Y-99972500D01* +X172290000Y-95872500D02* +X175690000Y-95872500D01* +%TO.C,C9*% +X179500000Y-103215000D02* +X179500000Y-101255000D01* +X179500000Y-101255000D02* +X176100000Y-101255000D01* +X176100000Y-103215000D02* +X179500000Y-103215000D01* +X176100000Y-101255000D02* +X176100000Y-103215000D01* +%TO.C,C11*% +X177455000Y-99490000D02* +X179415000Y-99490000D01* +X179415000Y-99490000D02* +X179415000Y-96090000D01* +X177455000Y-96090000D02* +X177455000Y-99490000D01* +X179415000Y-96090000D02* +X177455000Y-96090000D01* +%TO.C,C18*% +X158405000Y-112915000D02* +X158405000Y-116315000D01* +X160365000Y-112915000D02* +X158405000Y-112915000D01* +X158405000Y-116315000D02* +X160365000Y-116315000D01* +X160365000Y-116315000D02* +X160365000Y-112915000D01* +%TO.C,R22*% +X117922000Y-122607500D02* +X119822000Y-122607500D01* +X119822000Y-119247500D02* +X117922000Y-119247500D01* +X119822000Y-122607500D02* +X119822000Y-119247500D01* +X117922000Y-119247500D02* +X117922000Y-122607500D01* +%TO.C,U5*% +X177055000Y-83792500D02* +X177055000Y-89192500D01* +X169655000Y-89192500D02* +X169655000Y-83792500D01* +X177055000Y-89192500D02* +X169655000Y-89192500D01* +X169655000Y-83792500D02* +X177055000Y-83792500D01* +%TO.C,C16*% +X154420000Y-121575000D02* +X151020000Y-121575000D01* +X151020000Y-123535000D02* +X154420000Y-123535000D01* +X154420000Y-123535000D02* +X154420000Y-121575000D01* +X151020000Y-121575000D02* +X151020000Y-123535000D01* +%TO.C,R4*% +X124235000Y-105725000D02* +X124235000Y-103825000D01* +X124235000Y-103825000D02* +X120875000Y-103825000D01* +X120875000Y-105725000D02* +X124235000Y-105725000D01* +X120875000Y-103825000D02* +X120875000Y-105725000D01* +%TO.C,C2*% +X120125000Y-108295000D02* +X120125000Y-106335000D01* +X116725000Y-106335000D02* +X116725000Y-108295000D01* +X120125000Y-106335000D02* +X116725000Y-106335000D01* +X116725000Y-108295000D02* +X120125000Y-108295000D01* +%TO.C,R15*% +X170495000Y-99602500D02* +X170495000Y-96242500D01* +X170495000Y-96242500D02* +X168595000Y-96242500D01* +X168595000Y-96242500D02* +X168595000Y-99602500D01* +X168595000Y-99602500D02* +X170495000Y-99602500D01* +%TO.C,R20*% +X171225000Y-127955000D02* +X167865000Y-127955000D01* +X171225000Y-129855000D02* +X171225000Y-127955000D01* +X167865000Y-127955000D02* +X167865000Y-129855000D01* +X167865000Y-129855000D02* +X171225000Y-129855000D01* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Cu.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Cu.gbr new file mode 100644 index 0000000..9b1109d --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Cu.gbr @@ -0,0 +1,16455 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L2,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +%AMFreePoly0* +4,1,22,0.550000,-0.750000,0.000000,-0.750000,0.000000,-0.745033,-0.079941,-0.743568,-0.215256,-0.701293,-0.333266,-0.622738,-0.424486,-0.514219,-0.481581,-0.384460,-0.499164,-0.250000,-0.500000,-0.250000,-0.500000,0.250000,-0.499164,0.250000,-0.499963,0.256109,-0.478152,0.396186,-0.417904,0.524511,-0.324060,0.630769,-0.204165,0.706417,-0.067858,0.745374,0.000000,0.744959,0.000000,0.750000, +0.550000,0.750000,0.550000,-0.750000,0.550000,-0.750000,$1*% +%AMFreePoly1* +4,1,20,0.000000,0.744959,0.073905,0.744508,0.209726,0.703889,0.328688,0.626782,0.421226,0.519385,0.479903,0.390333,0.500000,0.250000,0.500000,-0.250000,0.499851,-0.262216,0.476331,-0.402017,0.414519,-0.529596,0.319384,-0.634700,0.198574,-0.708877,0.061801,-0.746166,0.000000,-0.745033,0.000000,-0.750000,-0.550000,-0.750000,-0.550000,0.750000,0.000000,0.750000,0.000000,0.744959, +0.000000,0.744959,$1*% +G04 Aperture macros list end* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD12R,0.300000X0.300000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD13R,0.250000X0.250000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD14R,1.000000X1.500000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD15RoundRect,0.250000X0.600000X0.600000X-0.600000X0.600000X-0.600000X-0.600000X0.600000X-0.600000X0*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD16C,1.700000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD17C,3.500000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD18O,1.700000X1.100000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD19R,1.200000X1.200000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD20C,1.200000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD21RoundRect,0.250000X0.475000X-0.250000X0.475000X0.250000X-0.475000X0.250000X-0.475000X-0.250000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD22RoundRect,0.250000X-0.262500X-0.450000X0.262500X-0.450000X0.262500X0.450000X-0.262500X0.450000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD23RoundRect,0.075000X-0.662500X-0.075000X0.662500X-0.075000X0.662500X0.075000X-0.662500X0.075000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD24RoundRect,0.075000X-0.075000X-0.662500X0.075000X-0.662500X0.075000X0.662500X-0.075000X0.662500X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD25RoundRect,0.250000X0.262500X0.450000X-0.262500X0.450000X-0.262500X-0.450000X0.262500X-0.450000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD26RoundRect,0.250000X-0.475000X0.250000X-0.475000X-0.250000X0.475000X-0.250000X0.475000X0.250000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD27RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD28RoundRect,0.125000X-0.537500X-0.125000X0.537500X-0.125000X0.537500X0.125000X-0.537500X0.125000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD29R,0.700000X0.510000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD30RoundRect,0.250000X-0.450000X0.262500X-0.450000X-0.262500X0.450000X-0.262500X0.450000X0.262500X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD31RoundRect,0.250000X0.450000X-0.262500X0.450000X0.262500X-0.450000X0.262500X-0.450000X-0.262500X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD32R,1.100000X0.510000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD33FreePoly0,180.000000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD34FreePoly1,180.000000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD35RoundRect,0.250000X0.250000X0.475000X-0.250000X0.475000X-0.250000X-0.475000X0.250000X-0.475000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD36R,0.812800X0.254000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD37R,0.254000X0.812800*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD38R,1.752600X1.752600*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD39RoundRect,0.150000X0.150000X-0.512500X0.150000X0.512500X-0.150000X0.512500X-0.150000X-0.512500X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD40RoundRect,0.150000X0.725000X0.150000X-0.725000X0.150000X-0.725000X-0.150000X0.725000X-0.150000X0*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD41C,0.800000*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD42C,0.900000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD43C,0.250000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD44C,0.500000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD45C,0.300000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD46C,0.400000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD47C,0.700000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD48C,0.200000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD49C,1.000000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD50C,0.350000*% +%TD*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.P,D1,1,K*% +%TO.N,VBUS*% +X136945000Y-101615000D03* +%TO.P,D1,2,K*% +%TO.N,/Power_Charge/Sense_BATT*% +X136945000Y-100315000D03* +D13* +%TO.P,D1,3,A*% +%TO.N,Net-(C6-Pad1)*% +X138670000Y-100965000D03* +D14* +X138045000Y-100965000D03* +%TD*% +D15* +%TO.P,J1,1,Pin_1*% +%TO.N,/Cpu/OUTGAUCHE_A*% +X131000000Y-87000000D03* +D16* +%TO.P,J1,2,Pin_2*% +%TO.N,/Cpu/OUTGAUCHE_B*% +X128460000Y-87000000D03* +%TO.P,J1,3,Pin_3*% +%TO.N,Net-(J1-Pad3)*% +X131000000Y-84460000D03* +%TO.P,J1,4,Pin_4*% +%TO.N,/Cpu/ENCGAUCHE_A*% +X128460000Y-84460000D03* +%TO.P,J1,5,Pin_5*% +%TO.N,/Cpu/ENCGAUCHE_B*% +X131000000Y-81920000D03* +%TO.P,J1,6,Pin_6*% +%TO.N,GND*% +X128460000Y-81920000D03* +%TD*% +D17* +%TO.P,BT1,1,+*% +%TO.N,+BATT*% +X180500000Y-124250000D03* +X180500000Y-131850000D03* +%TO.P,BT1,2,-*% +%TO.N,GND*% +X180500000Y-80150000D03* +X180500000Y-87750000D03* +%TD*% +D15* +%TO.P,J2,1,Pin_1*% +%TO.N,/Cpu/OUTDROIT_A*% +X131000000Y-130000000D03* +D16* +%TO.P,J2,2,Pin_2*% +%TO.N,/Cpu/OUTDROIT_B*% +X128460000Y-130000000D03* +%TO.P,J2,3,Pin_3*% +%TO.N,Net-(J1-Pad3)*% +X131000000Y-127460000D03* +%TO.P,J2,4,Pin_4*% +%TO.N,/Cpu/ENCDROIT_A*% +X128460000Y-127460000D03* +%TO.P,J2,5,Pin_5*% +%TO.N,/Cpu/ENCDROIT_B*% +X131000000Y-124920000D03* +%TO.P,J2,6,Pin_6*% +%TO.N,GND*% +X128460000Y-124920000D03* +%TD*% +D18* +%TO.P,P1,S1,SHIELD*% +%TO.N,GND*% +X191835000Y-101710000D03* +X195635000Y-110350000D03* +X195635000Y-101700000D03* +X191835000Y-110350000D03* +%TD*% +D19* +%TO.P,U1,1,VCC*% +%TO.N,+2V5*% +X119435000Y-116800000D03* +D20* +%TO.P,U1,2,DOUT*% +%TO.N,/Cpu/USART_RX*% +X121435000Y-116800000D03* +%TO.P,U1,3,DIN*% +%TO.N,/Cpu/USART_TX*% +X123435000Y-116800000D03* +%TO.P,U1,4,DIO12*% +%TO.N,unconnected-(U1-Pad4)*% +X125435000Y-116800000D03* +%TO.P,U1,5,~{RESET}*% +%TO.N,/Cpu/XBEE_RESET*% +X127435000Y-116800000D03* +%TO.P,U1,6,RSSI*% +%TO.N,unconnected-(U1-Pad6)*% +X129435000Y-116800000D03* +%TO.P,U1,7,DIO11*% +%TO.N,unconnected-(U1-Pad7)*% +X131435000Y-116800000D03* +%TO.P,U1,8*% +%TO.N,N/C*% +X133435000Y-116800000D03* +%TO.P,U1,9,~{DTR}/SLEEP_REQ*% +%TO.N,unconnected-(U1-Pad9)*% +X135435000Y-116800000D03* +%TO.P,U1,10,GND*% +%TO.N,GND*% +X137435000Y-116800000D03* +%TO.P,U1,11,DIO4*% +%TO.N,unconnected-(U1-Pad11)*% +X137435000Y-94800000D03* +%TO.P,U1,12,~{CTS}*% +%TO.N,unconnected-(U1-Pad12)*% +X135435000Y-94800000D03* +%TO.P,U1,13,~{SLEEP}*% +%TO.N,unconnected-(U1-Pad13)*% +X133435000Y-94800000D03* +%TO.P,U1,14*% +%TO.N,N/C*% +X131435000Y-94800000D03* +%TO.P,U1,15,ASSOCIATE*% +%TO.N,unconnected-(U1-Pad15)*% +X129435000Y-94800000D03* +%TO.P,U1,16,~{RTS}*% +%TO.N,unconnected-(U1-Pad16)*% +X127435000Y-94800000D03* +%TO.P,U1,17,DIO3*% +%TO.N,unconnected-(U1-Pad17)*% +X125435000Y-94800000D03* +%TO.P,U1,18,DIO2*% +%TO.N,unconnected-(U1-Pad18)*% +X123435000Y-94800000D03* +%TO.P,U1,19,DIO1*% +%TO.N,unconnected-(U1-Pad19)*% +X121435000Y-94800000D03* +%TO.P,U1,20,DIO0*% +%TO.N,unconnected-(U1-Pad20)*% +X119435000Y-94800000D03* +%TD*% +D21* +%TO.P,C17,1*% +%TO.N,+2V5*% +X156210000Y-106995000D03* +%TO.P,C17,2*% +%TO.N,GND*% +X156210000Y-105095000D03* +%TD*% +D22* +%TO.P,R10,1*% +%TO.N,Net-(R10-Pad1)*% +X173839500Y-81000000D03* +%TO.P,R10,2*% +%TO.N,+5V*% +X175664500Y-81000000D03* +%TD*% +D23* +%TO.P,U2,1,PC0*% +%TO.N,/Cpu/ENCGAUCHE_A*% +X146332500Y-115780000D03* +%TO.P,U2,2,PC13*% +%TO.N,unconnected-(U2-Pad2)*% +X146332500Y-115280000D03* +%TO.P,U2,3,PC14*% +%TO.N,unconnected-(U2-Pad3)*% +X146332500Y-114780000D03* +%TO.P,U2,4,PC15*% +%TO.N,unconnected-(U2-Pad4)*% +X146332500Y-114280000D03* +%TO.P,U2,5,PH0*% +%TO.N,unconnected-(U2-Pad5)*% +X146332500Y-113780000D03* +%TO.P,U2,6,PH1*% +%TO.N,unconnected-(U2-Pad6)*% +X146332500Y-113280000D03* +%TO.P,U2,7,NRST*% +%TO.N,/Cpu/RESET*% +X146332500Y-112780000D03* +%TO.P,U2,8,VSSA*% +%TO.N,GND*% +X146332500Y-112280000D03* +%TO.P,U2,9,VDDA*% +%TO.N,+2V5*% +X146332500Y-111780000D03* +%TO.P,U2,10,PA0*% +%TO.N,/Cpu/BATTERY_SENSE*% +X146332500Y-111280000D03* +%TO.P,U2,11,PA1*% +%TO.N,/Cpu/PWM_GAUCHE_B*% +X146332500Y-110780000D03* +%TO.P,U2,12,PA2*% +%TO.N,/Cpu/ENCDROIT_A*% +X146332500Y-110280000D03* +D24* +%TO.P,U2,13,PA3*% +%TO.N,/Cpu/ENCDROIT_B*% +X147745000Y-108867500D03* +%TO.P,U2,14,PA4*% +%TO.N,unconnected-(U2-Pad14)*% +X148245000Y-108867500D03* +%TO.P,U2,15,PA5*% +%TO.N,/Cpu/ENCGAUCHE_B*% +X148745000Y-108867500D03* +%TO.P,U2,16,PA6*% +%TO.N,unconnected-(U2-Pad16)*% +X149245000Y-108867500D03* +%TO.P,U2,17,PA7*% +%TO.N,unconnected-(U2-Pad17)*% +X149745000Y-108867500D03* +%TO.P,U2,18,PB0*% +%TO.N,/Cpu/PWM_DROIT_A*% +X150245000Y-108867500D03* +%TO.P,U2,19,PB1*% +%TO.N,/Cpu/PWM_DROIT_B*% +X150745000Y-108867500D03* +%TO.P,U2,20,PB2*% +%TO.N,unconnected-(U2-Pad20)*% +X151245000Y-108867500D03* +%TO.P,U2,21,PB10*% +%TO.N,/Cpu/USART_TX*% +X151745000Y-108867500D03* +%TO.P,U2,22,PB11*% +%TO.N,/Cpu/USART_RX*% +X152245000Y-108867500D03* +%TO.P,U2,23,VSS*% +%TO.N,GND*% +X152745000Y-108867500D03* +%TO.P,U2,24,VDD*% +%TO.N,+2V5*% +X153245000Y-108867500D03* +D23* +%TO.P,U2,25,PB12*% +%TO.N,/Cpu/LED_ROUGE*% +X154657500Y-110280000D03* +%TO.P,U2,26,PB13*% +%TO.N,/Cpu/LED_ORANGE*% +X154657500Y-110780000D03* +%TO.P,U2,27,PB14*% +%TO.N,/Cpu/LED_VERTE*% +X154657500Y-111280000D03* +%TO.P,U2,28,PB15*% +%TO.N,/Cpu/SHUTDOWN_ENC*% +X154657500Y-111780000D03* +%TO.P,U2,29,PA8*% +%TO.N,/Cpu/PWM_GAUCHE_A*% +X154657500Y-112280000D03* +%TO.P,U2,30,PA9*% +%TO.N,unconnected-(U2-Pad30)*% +X154657500Y-112780000D03* +%TO.P,U2,31,PA10*% +%TO.N,unconnected-(U2-Pad31)*% +X154657500Y-113280000D03* +%TO.P,U2,32,PA11*% +%TO.N,unconnected-(U2-Pad32)*% +X154657500Y-113780000D03* +%TO.P,U2,33,PA12*% +%TO.N,unconnected-(U2-Pad33)*% +X154657500Y-114280000D03* +%TO.P,U2,34,PA13*% +%TO.N,/Cpu/SWDIO*% +X154657500Y-114780000D03* +%TO.P,U2,35,VSS*% +%TO.N,GND*% +X154657500Y-115280000D03* +%TO.P,U2,36,VDD*% +%TO.N,+2V5*% +X154657500Y-115780000D03* +D24* +%TO.P,U2,37,PA14*% +%TO.N,/Cpu/SWCLK*% +X153245000Y-117192500D03* +%TO.P,U2,38,PA15*% +%TO.N,/Cpu/XBEE_RESET*% +X152745000Y-117192500D03* +%TO.P,U2,39,PB3*% +%TO.N,/Cpu/BUTTON_SENSE*% +X152245000Y-117192500D03* +%TO.P,U2,40,PB4*% +%TO.N,/Cpu/USB_SENSE*% +X151745000Y-117192500D03* +%TO.P,U2,41,PB5*% +%TO.N,unconnected-(U2-Pad41)*% +X151245000Y-117192500D03* +%TO.P,U2,42,PB6*% +%TO.N,/Cpu/CHARGER_ST2*% +X150745000Y-117192500D03* +%TO.P,U2,43,PB7*% +%TO.N,/Cpu/CHARGER_ST1*% +X150245000Y-117192500D03* +%TO.P,U2,44,BOOT0*% +%TO.N,Net-(R26-Pad2)*% +X149745000Y-117192500D03* +%TO.P,U2,45,PB8*% +%TO.N,/Cpu/SHUTDOWN_5V*% +X149245000Y-117192500D03* +%TO.P,U2,46,PB9*% +%TO.N,/Cpu/SHUTDOWN*% +X148745000Y-117192500D03* +%TO.P,U2,47,VSS*% +%TO.N,GND*% +X148245000Y-117192500D03* +%TO.P,U2,48,VDD*% +%TO.N,+2V5*% +X147745000Y-117192500D03* +%TD*% +D21* +%TO.P,C4,1*% +%TO.N,Net-(C4-Pad1)*% +X184785000Y-116520000D03* +%TO.P,C4,2*% +%TO.N,GND*% +X184785000Y-114620000D03* +%TD*% +D25* +%TO.P,R7,1*% +%TO.N,Net-(R7-Pad1)*% +X175537500Y-113030000D03* +%TO.P,R7,2*% +%TO.N,Net-(R7-Pad2)*% +X173712500Y-113030000D03* +%TD*% +D26* +%TO.P,C20,1*% +%TO.N,+2V5*% +X141605000Y-110810000D03* +%TO.P,C20,2*% +%TO.N,GND*% +X141605000Y-112710000D03* +%TD*% +D25* +%TO.P,R17,1*% +%TO.N,VBUS*% +X170457500Y-123190000D03* +%TO.P,R17,2*% +%TO.N,/Cpu/USB_SENSE*% +X168632500Y-123190000D03* +%TD*% +D27* +%TO.P,C6,1*% +%TO.N,Net-(C6-Pad1)*% +X172725000Y-102235000D03* +%TO.P,C6,2*% +%TO.N,GND*% +X174625000Y-102235000D03* +%TD*% +D22* +%TO.P,R3,1*% +%TO.N,+2V5*% +X175340000Y-122555000D03* +%TO.P,R3,2*% +%TO.N,/Cpu/CHARGER_ST1*% +X177165000Y-122555000D03* +%TD*% +D26* +%TO.P,C19,1*% +%TO.N,+2V5*% +X144780000Y-118750000D03* +%TO.P,C19,2*% +%TO.N,GND*% +X144780000Y-120650000D03* +%TD*% +D28* +%TO.P,U3,1,Vin*% +%TO.N,+BATT*% +X116972500Y-102575000D03* +%TO.P,U3,2,~{PB}*% +%TO.N,Net-(SW1-Pad2)*% +X116972500Y-101925000D03* +%TO.P,U3,3,ONT*% +%TO.N,Net-(C1-Pad1)*% +X116972500Y-101275000D03* +%TO.P,U3,4,GND*% +%TO.N,GND*% +X116972500Y-100625000D03* +%TO.P,U3,5,~{INT}*% +%TO.N,/Cpu/BUTTON_SENSE*% +X119247500Y-100625000D03* +%TO.P,U3,6,~{EN}*% +%TO.N,Net-(R1-Pad1)*% +X119247500Y-101275000D03* +%TO.P,U3,7,PDT*% +%TO.N,Net-(C2-Pad1)*% +X119247500Y-101925000D03* +%TO.P,U3,8,~{KILL}*% +%TO.N,/Cpu/SHUTDOWN*% +X119247500Y-102575000D03* +%TD*% +D29* +%TO.P,Q2,1,D*% +%TO.N,Net-(J1-Pad3)*% +X132605000Y-108270000D03* +%TO.P,Q2,2,D*% +X132605000Y-109220000D03* +%TO.P,Q2,3,G*% +%TO.N,Net-(R24-Pad2)*% +X132605000Y-110170000D03* +%TO.P,Q2,4,S*% +%TO.N,+2V5*% +X130285000Y-110170000D03* +%TO.P,Q2,5,D*% +%TO.N,Net-(J1-Pad3)*% +X130285000Y-109220000D03* +%TO.P,Q2,6,D*% +X130285000Y-108270000D03* +%TD*% +D22* +%TO.P,R24,1*% +%TO.N,+2V5*% +X130532500Y-112395000D03* +%TO.P,R24,2*% +%TO.N,Net-(R24-Pad2)*% +X132357500Y-112395000D03* +%TD*% +%TO.P,R1,1*% +%TO.N,Net-(R1-Pad1)*% +X130532500Y-104140000D03* +%TO.P,R1,2*% +%TO.N,+BATT*% +X132357500Y-104140000D03* +%TD*% +D21* +%TO.P,C7,1*% +%TO.N,+BATT*% +X184785000Y-131440000D03* +%TO.P,C7,2*% +%TO.N,GND*% +X184785000Y-129540000D03* +%TD*% +D30* +%TO.P,R16,1*% +%TO.N,/Cpu/LED_ROUGE*% +X116840000Y-120015000D03* +%TO.P,R16,2*% +%TO.N,Net-(D3-Pad2)*% +X116840000Y-121840000D03* +%TD*% +D31* +%TO.P,R13,1*% +%TO.N,Net-(R13-Pad1)*% +X178435000Y-110767500D03* +%TO.P,R13,2*% +%TO.N,GND*% +X178435000Y-108942500D03* +%TD*% +D32* +%TO.P,U7,1,IN1*% +%TO.N,/Cpu/PWM_GAUCHE_A*% +X153045000Y-98330000D03* +%TO.P,U7,2,IN2*% +%TO.N,/Cpu/PWM_GAUCHE_B*% +X153045000Y-99330000D03* +%TO.P,U7,3,VBB*% +%TO.N,+5V*% +X153045000Y-100330000D03* +%TO.P,U7,4,IN3*% +%TO.N,/Cpu/PWM_DROIT_A*% +X153045000Y-101330000D03* +%TO.P,U7,5,IN4*% +%TO.N,/Cpu/PWM_DROIT_B*% +X153045000Y-102330000D03* +%TO.P,U7,6,OUT4*% +%TO.N,/Cpu/OUTDROIT_B*% +X147945000Y-102330000D03* +%TO.P,U7,7,OUT3*% +%TO.N,/Cpu/OUTDROIT_A*% +X147945000Y-101330000D03* +%TO.P,U7,8,GND*% +%TO.N,GND*% +X147945000Y-100330000D03* +%TO.P,U7,9,OUT2*% +%TO.N,/Cpu/OUTGAUCHE_B*% +X147945000Y-99330000D03* +%TO.P,U7,10,OUT1*% +%TO.N,/Cpu/OUTGAUCHE_A*% +X147945000Y-98330000D03* +%TD*% +D25* +%TO.P,R21,1*% +%TO.N,Net-(R21-Pad1)*% +X175537500Y-115570000D03* +%TO.P,R21,2*% +%TO.N,+BATT*% +X173712500Y-115570000D03* +%TD*% +D26* +%TO.P,C3,1*% +%TO.N,VBUS*% +X188595000Y-105095000D03* +%TO.P,C3,2*% +%TO.N,GND*% +X188595000Y-106995000D03* +%TD*% +D25* +%TO.P,R2,1*% +%TO.N,Net-(Q1-Pad3)*% +X123467500Y-102235000D03* +%TO.P,R2,2*% +%TO.N,Net-(R1-Pad1)*% +X121642500Y-102235000D03* +%TD*% +D33* +%TO.P,JP1,1,A*% +%TO.N,GND*% +X151795000Y-126365000D03* +D14* +%TO.P,JP1,2,C*% +%TO.N,Net-(JP1-Pad2)*% +X150495000Y-126365000D03* +D34* +%TO.P,JP1,3,B*% +%TO.N,+2V5*% +X149195000Y-126365000D03* +%TD*% +D27* +%TO.P,C8,1*% +%TO.N,Net-(C6-Pad1)*% +X172405000Y-91572500D03* +%TO.P,C8,2*% +%TO.N,GND*% +X174305000Y-91572500D03* +%TD*% +D22* +%TO.P,R5,1*% +%TO.N,+2V5*% +X175340000Y-120015000D03* +%TO.P,R5,2*% +%TO.N,/Cpu/CHARGER_ST2*% +X177165000Y-120015000D03* +%TD*% +D25* +%TO.P,R11,1*% +%TO.N,GND*% +X181149000Y-84328000D03* +%TO.P,R11,2*% +%TO.N,Net-(R10-Pad1)*% +X179324000Y-84328000D03* +%TD*% +D26* +%TO.P,C5,1*% +%TO.N,Net-(C5-Pad1)*% +X184912000Y-83378000D03* +%TO.P,C5,2*% +%TO.N,Net-(C5-Pad2)*% +X184912000Y-85278000D03* +%TD*% +D22* +%TO.P,R18,1*% +%TO.N,/Cpu/USB_SENSE*% +X168632500Y-125730000D03* +%TO.P,R18,2*% +%TO.N,GND*% +X170457500Y-125730000D03* +%TD*% +D25* +%TO.P,R19,1*% +%TO.N,/Power_Charge/Sense_BATT*% +X170457500Y-131445000D03* +%TO.P,R19,2*% +%TO.N,/Cpu/BATTERY_SENSE*% +X168632500Y-131445000D03* +%TD*% +D35* +%TO.P,C13,1*% +%TO.N,+2V5*% +X119375000Y-114300000D03* +%TO.P,C13,2*% +%TO.N,GND*% +X117475000Y-114300000D03* +%TD*% +D36* +%TO.P,U4,1,Vin*% +%TO.N,VBUS*% +X181813200Y-114184999D03* +%TO.P,U4,2,Vinsns*% +X181813200Y-114685000D03* +%TO.P,U4,3,ST2*% +%TO.N,/Cpu/CHARGER_ST2*% +X181813200Y-115185000D03* +%TO.P,U4,4,ST1*% +%TO.N,/Cpu/CHARGER_ST1*% +X181813200Y-115685001D03* +D37* +%TO.P,U4,5,T_PRG*% +%TO.N,Net-(C4-Pad1)*% +X181090001Y-116408200D03* +%TO.P,U4,6,GND*% +%TO.N,GND*% +X180590000Y-116408200D03* +%TO.P,U4,7,SHDN*% +X180090000Y-116408200D03* +%TO.P,U4,8,TH*% +%TO.N,Net-(R7-Pad2)*% +X179589999Y-116408200D03* +D36* +%TO.P,U4,9,ISEL*% +%TO.N,VBUS*% +X178866800Y-115685001D03* +%TO.P,U4,10,Vosns*% +%TO.N,Net-(R21-Pad1)*% +X178866800Y-115185000D03* +%TO.P,U4,11,Vout*% +%TO.N,+BATT*% +X178866800Y-114685000D03* +%TO.P,U4,12,V_REF*% +%TO.N,Net-(R7-Pad1)*% +X178866800Y-114184999D03* +D37* +%TO.P,U4,13,I_END*% +%TO.N,Net-(R13-Pad1)*% +X179589999Y-113461800D03* +%TO.P,U4,14,MODE*% +%TO.N,VBUS*% +X180090000Y-113461800D03* +%TO.P,U4,15,I_USB*% +%TO.N,Net-(R12-Pad1)*% +X180590000Y-113461800D03* +%TO.P,U4,16,I_AC*% +%TO.N,Net-(R14-Pad1)*% +X181090001Y-113461800D03* +D38* +%TO.P,U4,17,GND*% +%TO.N,GND*% +X180340000Y-114935000D03* +%TD*% +D22* +%TO.P,R9,1*% +%TO.N,Net-(R7-Pad2)*% +X179427500Y-120396000D03* +%TO.P,R9,2*% +%TO.N,GND*% +X181252500Y-120396000D03* +%TD*% +D31* +%TO.P,R14,1*% +%TO.N,Net-(R14-Pad1)*% +X183515000Y-110767500D03* +%TO.P,R14,2*% +%TO.N,GND*% +X183515000Y-108942500D03* +%TD*% +%TO.P,R29,1*% +%TO.N,+2V5*% +X161925000Y-115570000D03* +%TO.P,R29,2*% +%TO.N,/Cpu/RESET*% +X161925000Y-113745000D03* +%TD*% +D26* +%TO.P,C10,1*% +%TO.N,+5V*% +X167005000Y-85542500D03* +%TO.P,C10,2*% +%TO.N,GND*% +X167005000Y-87442500D03* +%TD*% +D31* +%TO.P,R26,1*% +%TO.N,Net-(JP1-Pad2)*% +X149860000Y-122832500D03* +%TO.P,R26,2*% +%TO.N,Net-(R26-Pad2)*% +X149860000Y-121007500D03* +%TD*% +D30* +%TO.P,R28,1*% +%TO.N,/Cpu/SWCLK*% +X164465000Y-113745000D03* +%TO.P,R28,2*% +%TO.N,GND*% +X164465000Y-115570000D03* +%TD*% +D31* +%TO.P,R8,1*% +%TO.N,GND*% +X184912000Y-89304500D03* +%TO.P,R8,2*% +%TO.N,Net-(C5-Pad2)*% +X184912000Y-87479500D03* +%TD*% +D25* +%TO.P,R6,1*% +%TO.N,+2V5*% +X123467500Y-99695000D03* +%TO.P,R6,2*% +%TO.N,/Cpu/BUTTON_SENSE*% +X121642500Y-99695000D03* +%TD*% +D31* +%TO.P,R25,1*% +%TO.N,Net-(R24-Pad2)*% +X135255000Y-110132500D03* +%TO.P,R25,2*% +%TO.N,/Cpu/SHUTDOWN_ENC*% +X135255000Y-108307500D03* +%TD*% +%TO.P,R27,1*% +%TO.N,+2V5*% +X167005000Y-115570000D03* +%TO.P,R27,2*% +%TO.N,/Cpu/SWDIO*% +X167005000Y-113745000D03* +%TD*% +D35* +%TO.P,C14,1*% +%TO.N,/Cpu/OUTGAUCHE_A*% +X130490000Y-90170000D03* +%TO.P,C14,2*% +%TO.N,/Cpu/OUTGAUCHE_B*% +X128590000Y-90170000D03* +%TD*% +D30* +%TO.P,R23,1*% +%TO.N,/Cpu/LED_VERTE*% +X120904000Y-120015000D03* +%TO.P,R23,2*% +%TO.N,Net-(D5-Pad2)*% +X120904000Y-121840000D03* +%TD*% +D31* +%TO.P,R12,1*% +%TO.N,Net-(R12-Pad1)*% +X180975000Y-110767500D03* +%TO.P,R12,2*% +%TO.N,GND*% +X180975000Y-108942500D03* +%TD*% +D21* +%TO.P,C15,1*% +%TO.N,/Cpu/OUTDROIT_A*% +X124460000Y-129535000D03* +%TO.P,C15,2*% +%TO.N,/Cpu/OUTDROIT_B*% +X124460000Y-127635000D03* +%TD*% +D35* +%TO.P,C12,1*% +%TO.N,+5V*% +X151384000Y-94996000D03* +%TO.P,C12,2*% +%TO.N,GND*% +X149484000Y-94996000D03* +%TD*% +D21* +%TO.P,C1,2*% +%TO.N,GND*% +X114300000Y-100650000D03* +%TO.P,C1,1*% +%TO.N,Net-(C1-Pad1)*% +X114300000Y-102550000D03* +%TD*% +D29* +%TO.P,Q1,1,D*% +%TO.N,/Power_Charge/Sense_BATT*% +X132605000Y-100015000D03* +%TO.P,Q1,2,D*% +X132605000Y-100965000D03* +%TO.P,Q1,3,G*% +%TO.N,Net-(Q1-Pad3)*% +X132605000Y-101915000D03* +%TO.P,Q1,4,S*% +%TO.N,+BATT*% +X130285000Y-101915000D03* +%TO.P,Q1,5,D*% +%TO.N,/Power_Charge/Sense_BATT*% +X130285000Y-100965000D03* +%TO.P,Q1,6,D*% +X130285000Y-100015000D03* +%TD*% +D39* +%TO.P,U6,1,Vin*% +%TO.N,Net-(C6-Pad1)*% +X174940000Y-99060000D03* +%TO.P,U6,2,GND*% +%TO.N,GND*% +X173990000Y-99060000D03* +%TO.P,U6,3,~{SHDN}*% +%TO.N,Net-(C6-Pad1)*% +X173040000Y-99060000D03* +%TO.P,U6,4,~{ERROR}*% +%TO.N,Net-(C9-Pad1)*% +X173040000Y-96785000D03* +%TO.P,U6,5,Vout*% +%TO.N,+2V5*% +X174940000Y-96785000D03* +%TD*% +D35* +%TO.P,C9,1*% +%TO.N,Net-(C9-Pad1)*% +X178750000Y-102235000D03* +%TO.P,C9,2*% +%TO.N,GND*% +X176850000Y-102235000D03* +%TD*% +D26* +%TO.P,C11,1*% +%TO.N,+2V5*% +X178435000Y-96840000D03* +%TO.P,C11,2*% +%TO.N,GND*% +X178435000Y-98740000D03* +%TD*% +D21* +%TO.P,C18,1*% +%TO.N,+2V5*% +X159385000Y-115565000D03* +%TO.P,C18,2*% +%TO.N,GND*% +X159385000Y-113665000D03* +%TD*% +D30* +%TO.P,R22,1*% +%TO.N,/Cpu/LED_ORANGE*% +X118872000Y-120015000D03* +%TO.P,R22,2*% +%TO.N,Net-(D4-Pad2)*% +X118872000Y-121840000D03* +%TD*% +D40* +%TO.P,U5,1,VC*% +%TO.N,Net-(C5-Pad1)*% +X175930000Y-84587500D03* +%TO.P,U5,2,FB*% +%TO.N,Net-(R10-Pad1)*% +X175930000Y-85857500D03* +%TO.P,U5,3,Test*% +%TO.N,GND*% +X175930000Y-87127500D03* +%TO.P,U5,4,SS*% +%TO.N,/Cpu/SHUTDOWN_5V*% +X175930000Y-88397500D03* +%TO.P,U5,5,VCC*% +%TO.N,Net-(C6-Pad1)*% +X170780000Y-88397500D03* +%TO.P,U5,6,AGND*% +%TO.N,GND*% +X170780000Y-87127500D03* +%TO.P,U5,7,PGND*% +X170780000Y-85857500D03* +%TO.P,U5,8,Vsw*% +%TO.N,Net-(D2-Pad2)*% +X170780000Y-84587500D03* +%TD*% +D35* +%TO.P,C16,1*% +%TO.N,/Cpu/RESET*% +X153670000Y-122555000D03* +%TO.P,C16,2*% +%TO.N,GND*% +X151770000Y-122555000D03* +%TD*% +D25* +%TO.P,R4,1*% +%TO.N,+2V5*% +X123467500Y-104775000D03* +%TO.P,R4,2*% +%TO.N,/Cpu/SHUTDOWN*% +X121642500Y-104775000D03* +%TD*% +D35* +%TO.P,C2,1*% +%TO.N,Net-(C2-Pad1)*% +X119375000Y-107315000D03* +%TO.P,C2,2*% +%TO.N,GND*% +X117475000Y-107315000D03* +%TD*% +D30* +%TO.P,R15,1*% +%TO.N,Net-(C9-Pad1)*% +X169545000Y-97010000D03* +%TO.P,R15,2*% +%TO.N,Net-(C6-Pad1)*% +X169545000Y-98835000D03* +%TD*% +D22* +%TO.P,R20,1*% +%TO.N,/Cpu/BATTERY_SENSE*% +X168632500Y-128905000D03* +%TO.P,R20,2*% +%TO.N,GND*% +X170457500Y-128905000D03* +%TD*% +D41* +%TO.N,/Cpu/BUTTON_SENSE*% +X114300000Y-110490000D03* +X119380000Y-97040500D03* +X113030000Y-95885000D03* +X119380000Y-99060000D03* +%TO.N,/Power_Charge/Sense_BATT*% +X187960000Y-111125000D03* +X188595000Y-113570500D03* +X167005000Y-133350000D03* +X139065000Y-95250000D03* +%TO.N,+BATT*% +X114935000Y-106045000D03* +X116840000Y-104140000D03* +%TO.N,/Cpu/SHUTDOWN*% +X121285000Y-109220000D03* +X111760000Y-105410000D03* +D42* +%TO.N,+BATT*% +X171704000Y-115570000D03* +D41* +X153035000Y-96520000D03* +X125095000Y-97790000D03* +D42* +%TO.N,GND*% +X117475000Y-116840000D03* +D41* +X162560000Y-109855000D03* +X149860000Y-100330000D03* +X173990000Y-100584000D03* +X153350000Y-105095000D03* +X163195000Y-112395000D03* +D42* +X112776000Y-99060000D03* +D41* +%TO.N,VBUS*% +X142404500Y-94996000D03* +X169164000Y-110236000D03* +D42* +X194310000Y-105410000D03* +X183515000Y-113030000D03* +X177165000Y-116840000D03* +D41* +X164084000Y-97536000D03* +X170561000Y-117729000D03* +D42* +X179705000Y-111760000D03* +D41* +%TO.N,+2V5*% +X159385000Y-103505000D03* +X166370000Y-117475000D03* +X143764000Y-117348000D03* +X151387793Y-114811542D03* +X180225500Y-96520000D03* +X148860122Y-112764776D03* +X151892000Y-112268000D03* +X171704000Y-120015000D03* +D42* +%TO.N,+5V*% +X164465000Y-78105000D03* +D41* +X175260000Y-78232000D03* +%TO.N,Net-(C9-Pad1)*% +X171450000Y-95250000D03* +X180340000Y-95250000D03* +D42* +%TO.N,Net-(D2-Pad2)*% +X170815000Y-82550000D03* +D41* +%TO.N,/Cpu/RESET*% +X139700000Y-121195500D03* +X154940000Y-129629500D03* +X155575000Y-123190000D03* +X144145000Y-113030000D03* +X166370000Y-111125000D03* +%TO.N,Net-(J1-Pad3)*% +X127000000Y-99695000D03* +X127000000Y-109220000D03* +X133350000Y-88900000D03* +X126365000Y-117945500D03* +X127000000Y-104775000D03* +%TO.N,Net-(R7-Pad2)*% +X178308000Y-117856000D03* +X174625000Y-111125000D03* +%TO.N,/Cpu/OUTDROIT_A*% +X145415000Y-101600000D03* +X112776000Y-106680000D03* +%TO.N,/Cpu/OUTDROIT_B*% +X113665000Y-107950000D03* +X146050000Y-102870000D03* +%TO.N,Net-(SW1-Pad2)*% +X118110000Y-99060000D03* +%TO.N,Net-(D3-Pad2)*% +X116840000Y-126365000D03* +%TO.N,Net-(D4-Pad2)*% +X118745000Y-126365000D03* +%TO.N,Net-(D5-Pad2)*% +X120650000Y-126365000D03* +%TO.N,/Cpu/ENCGAUCHE_A*% +X144272000Y-99060000D03* +X141605000Y-104140000D03* +X138430000Y-109855000D03* +X138340500Y-114935000D03* +X144272000Y-104140000D03* +X140208000Y-99060000D03* +%TO.N,/Cpu/ENCDROIT_A*% +X127635000Y-114210500D03* +X139259800Y-108779800D03* +%TO.N,/Cpu/ENCDROIT_B*% +X149860000Y-113792000D03* +%TO.N,/Cpu/LED_ROUGE*% +X156845000Y-109220000D03* +X115570000Y-118110000D03* +%TO.N,/Cpu/LED_ORANGE*% +X156845000Y-110490000D03* +X122555000Y-121285000D03* +%TO.N,/Cpu/LED_VERTE*% +X158115000Y-109855000D03* +X124460000Y-121920000D03* +%TO.N,/Cpu/USART_RX*% +X135255000Y-112395000D03* +X151995500Y-106045000D03* +%TO.N,/Cpu/USART_TX*% +X135979500Y-113101755D03* +X151520500Y-106997462D03* +%TO.N,/Cpu/XBEE_RESET*% +X136525000Y-117945500D03* +X142710500Y-120650000D03* +X152469500Y-118745000D03* +X138340500Y-115934503D03* +%TO.N,/Cpu/CHARGER_ST1*% +X182880000Y-116205000D03* +X176530000Y-124460000D03* +%TO.N,/Cpu/SHUTDOWN*% +X135890000Y-125095000D03* +X146050000Y-121830500D03* +%TO.N,/Cpu/CHARGER_ST2*% +X171704000Y-118745000D03* +X156210000Y-120015000D03* +X151020500Y-118745000D03* +X169545000Y-118745000D03* +X182880000Y-114935000D03* +X178816000Y-118872000D03* +%TO.N,/Cpu/PWM_GAUCHE_B*% +X146812000Y-105955500D03* +X154940000Y-99060000D03* +%TO.N,/Cpu/BUTTON_SENSE*% +X150368000Y-115570000D03* +X115387601Y-121285000D03* +%TO.N,/Cpu/BATTERY_SENSE*% +X148844000Y-111252000D03* +X157983701Y-122423701D03* +X167132000Y-125984000D03* +X168632500Y-130071500D03* +%TO.N,/Cpu/SHUTDOWN_ENC*% +X137160000Y-108204000D03* +X159385000Y-110490000D03* +%TO.N,/Cpu/SWDIO*% +X156395480Y-118295480D03* +X152908000Y-113030000D03* +X171450000Y-104775000D03* +%TO.N,/Cpu/SWCLK*% +X160020000Y-117475000D03* +X167005000Y-112395000D03* +X170180000Y-105410000D03* +%TO.N,/Cpu/SHUTDOWN_5V*% +X173990000Y-88265000D03* +X186690000Y-110490000D03* +X186690000Y-113284000D03* +X147320000Y-121830500D03* +%TO.N,Net-(C6-Pad1)*% +X176530000Y-98425000D03* +D42* +X170180000Y-92710000D03* +D41* +X171225000Y-98835000D03* +X141224000Y-93980000D03* +%TD*% +D43* +%TO.N,/Cpu/ENCGAUCHE_A*% +X132715000Y-82586072D02* +X132116072Y-83185000D01* +X125729282Y-78740000D02* +X132080000Y-78740000D01* +X124460000Y-80009282D02* +X125729282Y-78740000D01* +X124460000Y-92710000D02* +X124460000Y-80009282D01* +X125095000Y-93345000D02* +X124460000Y-92710000D01* +X139700000Y-93345000D02* +X125095000Y-93345000D01* +X140335000Y-93980000D02* +X139700000Y-93345000D01* +X140335000Y-98933000D02* +X140335000Y-93980000D01* +X140208000Y-99060000D02* +X140335000Y-98933000D01* +X132715000Y-79375000D02* +X132715000Y-82586072D01* +X132116072Y-83185000D02* +X129735000Y-83185000D01* +X132080000Y-78740000D02* +X132715000Y-79375000D01* +X129735000Y-83185000D02* +X128460000Y-84460000D01* +D44* +%TO.N,+2V5*% +X146934000Y-118750000D02* +X144780000Y-118750000D01* +D45* +X147315000Y-118750000D02* +X146934000Y-118750000D01* +D46* +%TO.N,GND*% +X112776000Y-100584000D02* +X112776000Y-103886000D01* +X112776000Y-99949000D02* +X112776000Y-100584000D01* +X112776000Y-100584000D02* +X114234000Y-100584000D01* +X114234000Y-100584000D02* +X114300000Y-100650000D01* +D47* +X149484000Y-94996000D02* +X149484000Y-91816000D01* +X149484000Y-91816000D02* +X152400000Y-88900000D01* +X152400000Y-88900000D02* +X152400000Y-76708000D01* +X152400000Y-76708000D02* +X153416000Y-75692000D01* +X153416000Y-75692000D02* +X179832000Y-75692000D01* +X179832000Y-75692000D02* +X180500000Y-76360000D01* +X180500000Y-76360000D02* +X180500000Y-80150000D01* +%TO.N,Net-(C6-Pad1)*% +X138045000Y-100965000D02* +X140589000Y-100965000D01* +X140589000Y-100965000D02* +X141224000Y-100330000D01* +D46* +%TO.N,+BATT*% +X112395000Y-97790000D02* +X125095000Y-97790000D01* +%TO.N,/Power_Charge/Sense_BATT*% +X132605000Y-100015000D02* +X132605000Y-100220000D01* +D47* +X132605000Y-100220000D02* +X132605000Y-100965000D01* +X136945000Y-100315000D02* +X132700000Y-100315000D01* +D46* +X132700000Y-100315000D02* +X132605000Y-100220000D01* +D47* +%TO.N,+BATT*% +X125095000Y-97790000D02* +X127000000Y-97790000D01* +X130285000Y-101915000D02* +X128585000Y-101915000D01* +X128585000Y-101915000D02* +X128270000Y-101600000D01* +X128270000Y-101600000D02* +X128270000Y-99060000D01* +X128270000Y-99060000D02* +X127000000Y-97790000D01* +D46* +X112395000Y-97790000D02* +X111760000Y-98425000D01* +X111760000Y-98425000D02* +X111760000Y-104140000D01* +X111760000Y-104140000D02* +X113665000Y-106045000D01* +X113665000Y-106045000D02* +X114935000Y-106045000D01* +%TO.N,/Power_Charge/Sense_BATT*% +X170457500Y-131445000D02* +X170457500Y-133072500D01* +D43* +%TO.N,/Cpu/BUTTON_SENSE*% +X113665000Y-120650000D02* +X113665000Y-110490000D01* +D45* +X119380000Y-99695000D02* +X119380000Y-99060000D01* +D43* +X113665000Y-110490000D02* +X114300000Y-110490000D01* +X113030000Y-95885000D02* +X118745000Y-95885000D01* +X119380000Y-96520000D02* +X119380000Y-97040500D01* +X118745000Y-95885000D02* +X119380000Y-96520000D01* +D46* +%TO.N,/Power_Charge/Sense_BATT*% +X136945000Y-98640000D02* +X137160000Y-98425000D01* +X139065000Y-98425000D02* +X139065000Y-95250000D01* +X187960000Y-111125000D02* +X187960000Y-113030000D01* +X187960000Y-113030000D02* +X188500500Y-113570500D01* +X137160000Y-98425000D02* +X139065000Y-98425000D01* +X170180000Y-133350000D02* +X167005000Y-133350000D01* +X136945000Y-100315000D02* +X136945000Y-98640000D01* +X188500500Y-113570500D02* +X188595000Y-113570500D01* +X170457500Y-133072500D02* +X170180000Y-133350000D01* +%TO.N,+BATT*% +X116840000Y-104140000D02* +X116840000Y-102707500D01* +X116840000Y-102707500D02* +X116972500Y-102575000D01* +%TO.N,/Cpu/OUTDROIT_A*% +X112395000Y-122132850D02* +X113700480Y-123438330D01* +X112776000Y-106680000D02* +X112395000Y-107061000D01* +X112395000Y-107061000D02* +X112395000Y-122132850D01* +X113700480Y-123438330D02* +X113700480Y-127109010D01* +X113700480Y-127109010D02* +X114861470Y-128270000D01* +X114861470Y-128270000D02* +X121285000Y-128270000D01* +X121285000Y-128270000D02* +X125095000Y-132080000D01* +D45* +%TO.N,Net-(R1-Pad1)*% +X125160000Y-98490000D02* +X123125000Y-98490000D01* +X125730000Y-104775000D02* +X125730000Y-99060000D01* +X130532500Y-104140000D02* +X130175000Y-104140000D01* +X130175000Y-104140000D02* +X128840000Y-105475000D01* +X122555000Y-100965000D02* +X121920000Y-101600000D01* +X122555000Y-99060000D02* +X122555000Y-100965000D01* +X128840000Y-105475000D02* +X126430000Y-105475000D01* +X126430000Y-105475000D02* +X125730000Y-104775000D01* +X125730000Y-99060000D02* +X125160000Y-98490000D01* +X123125000Y-98490000D02* +X122555000Y-99060000D01* +%TO.N,+2V5*% +X123467500Y-104775000D02* +X123467500Y-104417500D01* +X123467500Y-104417500D02* +X122555000Y-103505000D01* +X122555000Y-103505000D02* +X122555000Y-101657183D01* +X122555000Y-101657183D02* +X123467500Y-100744683D01* +X123467500Y-100744683D02* +X123467500Y-99695000D01* +%TO.N,/Cpu/SHUTDOWN*% +X121642500Y-104775000D02* +X121642500Y-108862500D01* +X121642500Y-108862500D02* +X121285000Y-109220000D01* +D43* +X111760000Y-105410000D02* +X111760000Y-122239634D01* +D45* +%TO.N,Net-(C2-Pad1)*% +X119247500Y-101925000D02* +X118421396Y-101925000D01* +X119380000Y-106045000D02* +X119380000Y-107310000D01* +X118421396Y-101925000D02* +X118110000Y-102236396D01* +X119380000Y-107310000D02* +X119375000Y-107315000D01* +X118110000Y-102236396D02* +X118110000Y-104775000D01* +X118110000Y-104775000D02* +X119380000Y-106045000D01* +D46* +%TO.N,GND*% +X113980000Y-105090000D02* +X117155000Y-105090000D01* +X117155000Y-105090000D02* +X117475000Y-105410000D01* +X117475000Y-105410000D02* +X117475000Y-107315000D01* +D45* +%TO.N,Net-(SW1-Pad2)*% +X116972500Y-101925000D02* +X117785000Y-101925000D01* +X117785000Y-101925000D02* +X118110000Y-101600000D01* +X118110000Y-101600000D02* +X118110000Y-99060000D01* +D46* +%TO.N,GND*% +X112776000Y-103886000D02* +X113980000Y-105090000D01* +D45* +%TO.N,Net-(Q1-Pad3)*% +X132605000Y-101915000D02* +X133665000Y-101915000D01* +X133665000Y-101915000D02* +X133985000Y-102235000D01* +X133985000Y-102235000D02* +X133985000Y-105410000D01* +X133985000Y-105410000D02* +X133350000Y-106045000D01* +X133350000Y-106045000D02* +X125730000Y-106045000D01* +X125730000Y-106045000D02* +X125095000Y-105410000D01* +X125095000Y-105410000D02* +X125095000Y-102870000D01* +X125095000Y-102870000D02* +X124460000Y-102235000D01* +X124460000Y-102235000D02* +X123467500Y-102235000D01* +%TO.N,/Cpu/SHUTDOWN*% +X120650000Y-102870000D02* +X120650000Y-104775000D01* +X119247500Y-102575000D02* +X120355000Y-102575000D01* +X120650000Y-104775000D02* +X121642500Y-104775000D01* +X120355000Y-102575000D02* +X120650000Y-102870000D01* +%TO.N,Net-(R1-Pad1)*% +X119247500Y-101275000D02* +X120682500Y-101275000D01* +X120682500Y-101275000D02* +X121642500Y-102235000D01* +%TO.N,/Cpu/BUTTON_SENSE*% +X121642500Y-99695000D02* +X119380000Y-99695000D01* +X119380000Y-99695000D02* +X119247500Y-99827500D01* +X119247500Y-99827500D02* +X119247500Y-100625000D01* +D48* +%TO.N,Net-(C1-Pad1)*% +X114300000Y-102550000D02* +X114620000Y-102550000D01* +X114620000Y-102550000D02* +X115895000Y-101275000D01* +X115895000Y-101275000D02* +X116972500Y-101275000D01* +D46* +%TO.N,GND*% +X114300000Y-100650000D02* +X116947500Y-100650000D01* +X116947500Y-100650000D02* +X116972500Y-100625000D01* +X112776000Y-99060000D02* +X112776000Y-99949000D01* +%TO.N,+BATT*% +X130285000Y-101915000D02* +X131379000Y-101915000D01* +X131572000Y-102108000D02* +X131572000Y-103354500D01* +X131572000Y-103354500D02* +X131968591Y-103751091D01* +X131379000Y-101915000D02* +X131572000Y-102108000D01* +D47* +X171704000Y-115570000D02* +X172399511Y-114874489D01* +D43* +X173712500Y-115212500D02* +X173712500Y-115570000D01* +D47* +X172399511Y-114874489D02* +X172399511Y-103819511D01* +D46* +X184725000Y-131500000D02* +X184785000Y-131440000D01* +D49* +X180500000Y-131850000D02* +X184375000Y-131850000D01* +D47* +X172399511Y-103819511D02* +X170815000Y-102235000D01* +X171704000Y-115570000D02* +X173712500Y-115570000D01* +D46* +X174625000Y-114300000D02* +X176784000Y-114300000D01* +D49* +X184375000Y-131850000D02* +X184785000Y-131440000D01* +D46* +X173712500Y-115212500D02* +X174625000Y-114300000D01* +D47* +X170815000Y-102235000D02* +X166370000Y-102235000D01* +D43* +X177308216Y-114685000D02* +X177238608Y-114754608D01* +D46* +X176784000Y-114300000D02* +X177238608Y-114754608D01* +D43* +X178866800Y-114685000D02* +X177308216Y-114685000D01* +D47* +X166370000Y-102235000D02* +X166370000Y-97155000D01* +X165735000Y-96520000D02* +X153035000Y-96520000D01* +X166370000Y-97155000D02* +X165735000Y-96520000D01* +D45* +%TO.N,GND*% +X148590000Y-121920000D02* +X147955000Y-122555000D01* +X152745000Y-108867500D02* +X152745000Y-105700000D01* +D49* +X191135000Y-129540000D02* +X191835000Y-128840000D01* +D45* +X150840000Y-114300000D02* +X150840000Y-113756000D01* +D44* +X173990000Y-100965000D02* +X173990000Y-101600000D01* +D43* +X180090000Y-115185000D02* +X180340000Y-114935000D01* +D46* +X181252500Y-119657500D02* +X181252500Y-120396000D01* +X184912000Y-89304500D02* +X182054500Y-89304500D01* +X164465000Y-115570000D02* +X163830000Y-115570000D01* +D47* +X170457500Y-127230500D02* +X170735000Y-127508000D01* +D49* +X191835000Y-120715000D02* +X191835000Y-115000000D01* +D46* +X191455000Y-114620000D02* +X191835000Y-115000000D01* +D47* +X191835000Y-110350000D02* +X189090000Y-110350000D01* +X188595000Y-109855000D02* +X188595000Y-109220000D01* +D49* +X184404000Y-127508000D02* +X184785000Y-127889000D01* +D46* +X137435000Y-118470000D02* +X137435000Y-116800000D01* +D44* +X177485000Y-98740000D02* +X178435000Y-98740000D01* +D46* +X180590000Y-118995000D02* +X181252500Y-119657500D01* +D45* +X151384000Y-110236000D02* +X152214361Y-110236000D01* +X152745000Y-105700000D02* +X153350000Y-105095000D01* +D49* +X184785000Y-127889000D02* +X184785000Y-129540000D01* +D47* +X149484000Y-100071000D02* +X149484000Y-94996000D01* +D43* +X180090000Y-116408200D02* +X180590000Y-116408200D01* +D46* +X128460000Y-119190000D02* +X128905000Y-118745000D01* +D45* +X148245000Y-117192500D02* +X148245000Y-118526428D01* +X148245000Y-114590000D02* +X148245000Y-113193000D01* +D49* +X170457500Y-125730000D02* +X170457500Y-127230500D01* +D47* +X176850000Y-102235000D02* +X176850000Y-108270000D01* +D46* +X141605000Y-112710000D02* +X138750000Y-112710000D01* +X177673000Y-87503000D02* +X177920000Y-87750000D01* +D47* +X177390000Y-90580000D02* +X177800000Y-90170000D01* +D45* +X147332000Y-112280000D02* +X146332500Y-112280000D01* +D47* +X175297500Y-90580000D02* +X174305000Y-91572500D01* +D46* +X181149000Y-87101000D02* +X180500000Y-87750000D01* +D47* +X178435000Y-108942500D02* +X177522500Y-108942500D01* +D46* +X163195000Y-114935000D02* +X163195000Y-112395000D01* +D47* +X168777500Y-87127500D02* +X168462500Y-87442500D01* +D45* +X157770000Y-115280000D02* +X159385000Y-113665000D01* +D44* +X176850000Y-102235000D02* +X176850000Y-99375000D01* +D47* +X177522500Y-108942500D02* +X176850000Y-108270000D01* +D44* +X147945000Y-100330000D02* +X149225000Y-100330000D01* +D47* +X177920000Y-87750000D02* +X180500000Y-87750000D01* +X177673000Y-87503000D02* +X177297500Y-87127500D01* +D45* +X142035000Y-112280000D02* +X141605000Y-112710000D01* +X153683922Y-115280000D02* +X152183433Y-113779511D01* +X148245000Y-118526428D02* +X146121428Y-120650000D01* +D49* +X181252500Y-120396000D02* +X191516000Y-120396000D01* +D46* +X137435000Y-114025000D02* +X137435000Y-116800000D01* +D47* +X149743000Y-100330000D02* +X149484000Y-100071000D01* +D45* +X148245000Y-117192500D02* +X148245000Y-114590000D01* +D47* +X188595000Y-109220000D02* +X188595000Y-106995000D01* +D46* +X174625000Y-102235000D02* +X176850000Y-102235000D01* +D49* +X191835000Y-128840000D02* +X191835000Y-120715000D01* +D45* +X151770000Y-122555000D02* +X151135000Y-121920000D01* +D47* +X177297500Y-87127500D02* +X175930000Y-87127500D01* +D49* +X184785000Y-114620000D02* +X191455000Y-114620000D01* +D46* +X188317500Y-108942500D02* +X188595000Y-109220000D01* +X128460000Y-124920000D02* +X128460000Y-119190000D01* +D47* +X177800000Y-90170000D02* +X177800000Y-87630000D01* +D44* +X173990000Y-101600000D02* +X174625000Y-102235000D01* +D47* +X189090000Y-110350000D02* +X188595000Y-109855000D01* +D45* +X151135000Y-121920000D02* +X148590000Y-121920000D01* +X159385000Y-113665000D02* +X159385000Y-113030000D01* +D47* +X195635000Y-101700000D02* +X191845000Y-101700000D01* +D49* +X191835000Y-115000000D02* +X191835000Y-110350000D01* +D46* +X173990000Y-99060000D02* +X173990000Y-100965000D01* +D47* +X195635000Y-110350000D02* +X191835000Y-110350000D01* +D44* +X176850000Y-99375000D02* +X177485000Y-98740000D01* +D45* +X148245000Y-113193000D02* +X147332000Y-112280000D01* +D46* +X180590000Y-117860000D02* +X180590000Y-118995000D01* +D47* +X178435000Y-108942500D02* +X188317500Y-108942500D01* +D46* +X182054500Y-89304500D02* +X180500000Y-87750000D01* +D50* +X151770000Y-126340000D02* +X151795000Y-126365000D01* +D45* +X150550000Y-114590000D02* +X150840000Y-114300000D01* +D49* +X170457500Y-127230500D02* +X170457500Y-128905000D01* +D45* +X152183433Y-113779511D02* +X150863511Y-113779511D01* +D47* +X167005000Y-87442500D02* +X168462500Y-87442500D01* +D46* +X191845000Y-101700000D02* +X191835000Y-101710000D01* +D45* +X151770000Y-122555000D02* +X151770000Y-126340000D01* +D47* +X170780000Y-87127500D02* +X168777500Y-87127500D01* +X175930000Y-87127500D02* +X170780000Y-87127500D01* +D45* +X154657500Y-115280000D02* +X157770000Y-115280000D01* +X159385000Y-113030000D02* +X162560000Y-109855000D01* +D46* +X138750000Y-112710000D02* +X137435000Y-114025000D01* +D47* +X149225000Y-100330000D02* +X149484000Y-100071000D01* +D43* +X180590000Y-116408200D02* +X180590000Y-117860000D01* +D45* +X144780000Y-121920000D02* +X144780000Y-120650000D01* +X154657500Y-115280000D02* +X153683922Y-115280000D01* +D46* +X117475000Y-116840000D02* +X117475000Y-114300000D01* +D47* +X195635000Y-110350000D02* +X195635000Y-101700000D01* +D45* +X150840000Y-113756000D02* +X150840000Y-110780000D01* +D46* +X117475000Y-114300000D02* +X117475000Y-107315000D01* +X177800000Y-87630000D02* +X177673000Y-87503000D01* +X173990000Y-91887500D02* +X174305000Y-91572500D01* +D44* +X173990000Y-99060000D02* +X173990000Y-91887500D01* +D43* +X180090000Y-116408200D02* +X180090000Y-115185000D01* +D47* +X191516000Y-120396000D02* +X191835000Y-120715000D01* +D45* +X147955000Y-122555000D02* +X145415000Y-122555000D01* +X146121428Y-120650000D02* +X144780000Y-120650000D01* +D46* +X163830000Y-115570000D02* +X163195000Y-114935000D01* +D45* +X152214361Y-110236000D02* +X152745000Y-109705361D01* +X150840000Y-110780000D02* +X151384000Y-110236000D01* +D46* +X170780000Y-85857500D02* +X170780000Y-87127500D01* +X137160000Y-118745000D02* +X137435000Y-118470000D01* +D49* +X184785000Y-129540000D02* +X191135000Y-129540000D01* +D45* +X150863511Y-113779511D02* +X150840000Y-113756000D01* +X146332500Y-112280000D02* +X142035000Y-112280000D01* +X148245000Y-114590000D02* +X150550000Y-114590000D01* +D49* +X170735000Y-127508000D02* +X184404000Y-127508000D01* +D45* +X145415000Y-122555000D02* +X144780000Y-121920000D01* +D46* +X128905000Y-118745000D02* +X137160000Y-118745000D01* +D45* +X153350000Y-105095000D02* +X156210000Y-105095000D01* +D46* +X181149000Y-84328000D02* +X181149000Y-87101000D01* +D47* +X175297500Y-90580000D02* +X177390000Y-90580000D01* +D45* +X152745000Y-109705361D02* +X152745000Y-108867500D01* +X149860000Y-100330000D02* +X149743000Y-100330000D01* +D46* +%TO.N,VBUS*% +X137160000Y-102870000D02* +X141605000Y-102870000D01* +X142240000Y-95250000D02* +X142240000Y-95160500D01* +X164084000Y-97536000D02* +X165608000Y-99060000D01* +X166116000Y-110236000D02* +X169164000Y-110236000D01* +X165608000Y-99060000D02* +X165608000Y-109728000D01* +X136945000Y-101615000D02* +X136945000Y-102655000D01* +X142240000Y-95160500D02* +X142404500Y-94996000D01* +X170457500Y-123190000D02* +X170457500Y-117832500D01* +D43* +X178319999Y-115685001D02* +X177165000Y-116840000D01* +D46* +X170561000Y-117729000D02* +X171450000Y-116840000D01* +X142240000Y-102235000D02* +X142240000Y-95250000D01* +D47* +X188595000Y-105095000D02* +X193995000Y-105095000D01* +D43* +X181813200Y-114184999D02* +X181813200Y-114685000D01* +D46* +X183515000Y-113030000D02* +X182880000Y-113665000D01* +X171450000Y-116840000D02* +X177165000Y-116840000D01* +X170457500Y-117832500D02* +X170561000Y-117729000D01* +D43* +X182880000Y-113665000D02* +X182360001Y-114184999D01* +X180090000Y-112145000D02* +X179705000Y-111760000D01* +D46* +X193995000Y-105095000D02* +X194310000Y-105410000D01* +X165608000Y-109728000D02* +X166116000Y-110236000D01* +X136945000Y-102655000D02* +X137160000Y-102870000D01* +D43* +X180090000Y-113461800D02* +X180090000Y-112145000D01* +D46* +X141605000Y-102870000D02* +X142240000Y-102235000D01* +D43* +X178866800Y-115685001D02* +X178319999Y-115685001D01* +X182360001Y-114184999D02* +X181813200Y-114184999D01* +D46* +%TO.N,Net-(C4-Pad1)*% +X184150000Y-117475000D02* +X181610000Y-117475000D01* +X184785000Y-116520000D02* +X184785000Y-116840000D01* +X184785000Y-116840000D02* +X184150000Y-117475000D01* +D43* +X181090001Y-116955001D02* +X181090001Y-116408200D01* +X181610000Y-117475000D02* +X181090001Y-116955001D01* +D46* +%TO.N,Net-(C5-Pad1)*% +X184338000Y-82804000D02* +X184912000Y-83378000D01* +X177546000Y-82804000D02* +X184338000Y-82804000D01* +X175930000Y-84587500D02* +X175930000Y-84420000D01* +X175930000Y-84420000D02* +X177546000Y-82804000D01* +%TO.N,Net-(C5-Pad2)*% +X184912000Y-85278000D02* +X184912000Y-87479500D01* +%TO.N,+2V5*% +X141539000Y-110744000D02* +X141605000Y-110810000D01* +X166370000Y-117475000D02* +X167005000Y-116840000D01* +X175340000Y-120015000D02* +X171704000Y-120015000D01* +D44* +X119700000Y-110170000D02* +X119375000Y-110495000D01* +D46* +X162560000Y-117475000D02* +X166370000Y-117475000D01* +X143505000Y-117607000D02* +X143505000Y-118750000D01* +D44* +X159070000Y-106995000D02* +X159385000Y-106680000D01* +D45* +X159385000Y-115565000D02* +X161920000Y-115565000D01* +X123467500Y-104775000D02* +X123467500Y-110127500D01* +D46* +X123467500Y-110127500D02* +X123510000Y-110170000D01* +D44* +X136144000Y-111252000D02* +X136652000Y-110744000D01* +X156210000Y-106995000D02* +X159070000Y-106995000D01* +X130285000Y-110170000D02* +X123510000Y-110170000D01* +D45* +X143764000Y-117348000D02* +X143505000Y-117607000D01* +X147745000Y-118320000D02* +X147315000Y-118750000D01* +D44* +X159385000Y-106680000D02* +X159385000Y-103505000D01* +D45* +X144780000Y-123825000D02* +X143510000Y-122555000D01* +D44* +X133985000Y-113665000D02* +X133985000Y-111760000D01* +D46* +X151387793Y-114811542D02* +X152509036Y-114811542D01* +X161925000Y-115570000D02* +X161925000Y-116840000D01* +X161925000Y-116840000D02* +X162560000Y-117475000D01* +X175340000Y-120015000D02* +X175340000Y-122555000D01* +D44* +X123510000Y-110170000D02* +X119700000Y-110170000D01* +X130532500Y-112395000D02* +X130532500Y-114022500D01* +X144338000Y-110810000D02* +X141605000Y-110810000D01* +D45* +X143510000Y-122555000D02* +X143510000Y-118755000D01* +X161920000Y-115565000D02* +X161925000Y-115570000D01* +D44* +X151892000Y-112268000D02* +X153245000Y-110915000D01* +X145308000Y-111780000D02* +X144338000Y-110810000D01* +D45* +X149195000Y-126365000D02* +X144780000Y-126365000D01* +X146332500Y-111780000D02* +X147875346Y-111780000D01* +D44* +X119375000Y-110495000D02* +X119375000Y-114300000D01* +X119375000Y-114300000D02* +X119375000Y-116740000D01* +X180225500Y-96520000D02* +X178755000Y-96520000D01* +X136652000Y-110744000D02* +X141539000Y-110744000D01* +D46* +X143505000Y-118750000D02* +X144780000Y-118750000D01* +D45* +X154657500Y-115780000D02* +X159170000Y-115780000D01* +X153245000Y-110915000D02* +X153245000Y-108867500D01* +D44* +X178755000Y-96520000D02* +X178435000Y-96840000D01* +D46* +X178380000Y-96785000D02* +X178435000Y-96840000D01* +X167005000Y-116840000D02* +X167005000Y-115570000D01* +X119375000Y-116740000D02* +X119435000Y-116800000D01* +D44* +X133627500Y-114022500D02* +X133985000Y-113665000D01* +D46* +X143510000Y-118755000D02* +X143505000Y-118750000D01* +X147875346Y-111780000D02* +X148860122Y-112764776D01* +X153245000Y-107740000D02* +X153990000Y-106995000D01* +D45* +X146332500Y-111780000D02* +X145308000Y-111780000D01* +D44* +X153990000Y-106995000D02* +X156210000Y-106995000D01* +D45* +X159170000Y-115780000D02* +X159385000Y-115565000D01* +X153477494Y-115780000D02* +X154657500Y-115780000D01* +D44* +X130532500Y-114022500D02* +X133627500Y-114022500D01* +X130532500Y-110417500D02* +X130285000Y-110170000D01* +X134493000Y-111252000D02* +X136144000Y-111252000D01* +D45* +X147745000Y-117192500D02* +X147745000Y-118320000D01* +D44* +X174940000Y-96785000D02* +X178380000Y-96785000D01* +D45* +X144780000Y-126365000D02* +X144780000Y-123825000D01* +D44* +X130532500Y-112395000D02* +X130532500Y-110417500D01* +D45* +X153245000Y-108867500D02* +X153245000Y-107740000D01* +X152509036Y-114811542D02* +X153477494Y-115780000D01* +D44* +X133985000Y-111760000D02* +X134493000Y-111252000D01* +%TO.N,+5V*% +X151384000Y-99949000D02* +X151384000Y-94996000D01* +X151765000Y-100330000D02* +X151384000Y-99949000D01* +X151384000Y-94996000D02* +X151765000Y-94615000D01* +D46* +X175260000Y-78232000D02* +X175664500Y-78636500D01* +D47* +X164465000Y-93345000D02* +X164465000Y-85090000D01* +D44* +X153045000Y-100330000D02* +X151765000Y-100330000D01* +D47* +X164465000Y-78105000D02* +X164465000Y-85090000D01* +D46* +X175664500Y-78636500D02* +X175664500Y-81000000D01* +D44* +X164917500Y-85542500D02* +X167005000Y-85542500D01* +D47* +X163195000Y-94615000D02* +X164465000Y-93345000D01* +X151765000Y-94615000D02* +X163195000Y-94615000D01* +D44* +X164465000Y-85090000D02* +X164917500Y-85542500D01* +D47* +%TO.N,/Power_Charge/Sense_BATT*% +X130285000Y-100965000D02* +X130285000Y-100015000D01* +X130285000Y-100965000D02* +X132605000Y-100965000D01* +D46* +%TO.N,Net-(C9-Pad1)*% +X169545000Y-97010000D02* +X171305000Y-97010000D01* +D45* +X180975000Y-95885000D02* +X180340000Y-95250000D01* +D46* +X172815000Y-97010000D02* +X173040000Y-96785000D01* +D45* +X171450000Y-95250000D02* +X171450000Y-96865000D01* +X171450000Y-96865000D02* +X171305000Y-97010000D01* +X178750000Y-102235000D02* +X180340000Y-102235000D01* +X180975000Y-101600000D02* +X180975000Y-95885000D01* +D46* +X171305000Y-97010000D02* +X172815000Y-97010000D01* +D45* +X180340000Y-102235000D02* +X180975000Y-101600000D01* +D46* +%TO.N,Net-(D2-Pad2)*% +X170815000Y-84552500D02* +X170780000Y-84587500D01* +X170815000Y-82550000D02* +X170815000Y-84552500D01* +D43* +%TO.N,/Cpu/RESET*% +X161925000Y-111760000D02* +X161925000Y-113745000D01* +X142768216Y-122555000D02* +X144145000Y-123931784D01* +X153670000Y-122555000D02* +X154940000Y-122555000D01* +X144145000Y-123931784D02* +X144145000Y-128905000D01* +X140335000Y-122555000D02* +X142768216Y-122555000D01* +X140335000Y-122555000D02* +X139700000Y-121920000D01* +X144869500Y-129629500D02* +X154940000Y-129629500D01* +X154940000Y-122555000D02* +X155575000Y-123190000D01* +X144145000Y-128905000D02* +X144869500Y-129629500D01* +X146332500Y-112780000D02* +X144395000Y-112780000D01* +X144395000Y-112780000D02* +X144145000Y-113030000D01* +X162560000Y-111125000D02* +X161925000Y-111760000D01* +X139700000Y-121920000D02* +X139700000Y-121195500D01* +X166370000Y-111125000D02* +X162560000Y-111125000D01* +D45* +%TO.N,Net-(J1-Pad3)*% +X132720000Y-84460000D02* +X133350000Y-85090000D01* +X125730000Y-125730000D02* +X125730000Y-118580500D01* +D46* +X132605000Y-108270000D02* +X132605000Y-109220000D01* +D45* +X133350000Y-85090000D02* +X133350000Y-88900000D01* +D46* +X130285000Y-108270000D02* +X130285000Y-109220000D01* +D45* +X127000000Y-109220000D02* +X130285000Y-109220000D01* +X127000000Y-99695000D02* +X127000000Y-104775000D01* +D46* +X130285000Y-108270000D02* +X132605000Y-108270000D01* +D45* +X131000000Y-127460000D02* +X129800489Y-126260489D01* +X125730000Y-118580500D02* +X126365000Y-117945500D01* +X131000000Y-84460000D02* +X132720000Y-84460000D01* +X126260489Y-126260489D02* +X125730000Y-125730000D01* +X129800489Y-126260489D02* +X126260489Y-126260489D01* +D43* +%TO.N,Net-(R7-Pad1)*% +X177684999Y-114184999D02* +X176530000Y-113030000D01* +X178866800Y-114184999D02* +X177684999Y-114184999D01* +X176530000Y-113030000D02* +X175537500Y-113030000D01* +%TO.N,Net-(R7-Pad2)*% +X178308000Y-117856000D02* +X179589999Y-116574001D01* +X179589999Y-120233501D02* +X179589999Y-116408200D01* +X174625000Y-111125000D02* +X173990000Y-111125000D01* +X173990000Y-111125000D02* +X173712500Y-111402500D01* +X173712500Y-111402500D02* +X173712500Y-113030000D01* +X179589999Y-116574001D02* +X179589999Y-116408200D01* +X179427500Y-120396000D02* +X179589999Y-120233501D01* +D46* +%TO.N,Net-(R10-Pad1)*% +X177032500Y-85857500D02* +X178562000Y-84328000D01* +X174249500Y-85857500D02* +X173839500Y-85447500D01* +X178562000Y-84328000D02* +X179324000Y-84328000D01* +X173839500Y-85447500D02* +X173839500Y-81000000D01* +X175930000Y-85857500D02* +X177032500Y-85857500D01* +X175930000Y-85857500D02* +X174249500Y-85857500D01* +D43* +%TO.N,Net-(R12-Pad1)*% +X180590000Y-113461800D02* +X180590000Y-111152500D01* +X180590000Y-111152500D02* +X180975000Y-110767500D01* +%TO.N,Net-(R13-Pad1)*% +X179589999Y-112914999D02* +X178435000Y-111760000D01* +X179589999Y-113461800D02* +X179589999Y-112914999D01* +X178435000Y-111760000D02* +X178435000Y-110767500D01* +%TO.N,Net-(R14-Pad1)*% +X181090001Y-112914999D02* +X181610000Y-112395000D01* +X181090001Y-113461800D02* +X181090001Y-112914999D01* +X182880000Y-112395000D02* +X183515000Y-111760000D01* +X181610000Y-112395000D02* +X182880000Y-112395000D01* +X183515000Y-111760000D02* +X183515000Y-110767500D01* +%TO.N,Net-(R21-Pad1)*% +X177550000Y-115185000D02* +X177165000Y-115570000D01* +X177165000Y-115570000D02* +X175537500Y-115570000D01* +X178866800Y-115185000D02* +X177550000Y-115185000D01* +D46* +%TO.N,/Cpu/OUTGAUCHE_A*% +X130490000Y-87510000D02* +X131000000Y-87000000D01* +X147945000Y-91430000D02* +X146685000Y-90170000D01* +X146685000Y-90170000D02* +X130490000Y-90170000D01* +X147945000Y-98330000D02* +X147945000Y-91430000D01* +X130490000Y-90170000D02* +X130490000Y-87510000D01* +%TO.N,/Cpu/OUTGAUCHE_B*% +X128590000Y-90170000D02* +X128590000Y-91760000D01* +X146050000Y-92710000D02* +X146050000Y-99060000D01* +X128460000Y-90040000D02* +X128590000Y-90170000D01* +X146320000Y-99330000D02* +X147945000Y-99330000D01* +X128905000Y-92075000D02* +X145415000Y-92075000D01* +X146050000Y-99060000D02* +X146320000Y-99330000D01* +X145415000Y-92075000D02* +X146050000Y-92710000D01* +X128590000Y-91760000D02* +X128905000Y-92075000D01* +X128460000Y-87000000D02* +X128460000Y-90040000D01* +%TO.N,/Cpu/OUTDROIT_A*% +X130175000Y-132080000D02* +X131000000Y-131255000D01* +X145685000Y-101330000D02* +X147945000Y-101330000D01* +X131000000Y-131255000D02* +X131000000Y-130000000D01* +X124460000Y-131445000D02* +X125095000Y-132080000D01* +X125095000Y-132080000D02* +X130175000Y-132080000D01* +X145415000Y-101600000D02* +X145685000Y-101330000D01* +X124460000Y-129535000D02* +X124460000Y-131445000D01* +%TO.N,/Cpu/OUTDROIT_B*% +X126825000Y-130000000D02* +X126365000Y-129540000D01* +X113665000Y-107950000D02* +X113030000Y-108585000D01* +X113030000Y-108585000D02* +X113030000Y-121920000D01* +X115147850Y-127635000D02* +X124460000Y-127635000D01* +X114300000Y-123190000D02* +X114300000Y-126787150D01* +X126365000Y-128270000D02* +X125730000Y-127635000D01* +X114300000Y-126787150D02* +X115147850Y-127635000D01* +X146590000Y-102330000D02* +X146050000Y-102870000D01* +X128460000Y-130000000D02* +X126825000Y-130000000D01* +X113030000Y-121920000D02* +X114300000Y-123190000D01* +X147945000Y-102330000D02* +X146590000Y-102330000D01* +X125730000Y-127635000D02* +X124460000Y-127635000D01* +X126365000Y-129540000D02* +X126365000Y-128270000D01* +D45* +%TO.N,Net-(D3-Pad2)*% +X116840000Y-126365000D02* +X116840000Y-121840000D01* +%TO.N,Net-(D4-Pad2)*% +X118745000Y-121967000D02* +X118872000Y-121840000D01* +X118745000Y-126365000D02* +X118745000Y-121967000D01* +%TO.N,Net-(D5-Pad2)*% +X120650000Y-121840000D02* +X120650000Y-126365000D01* +D43* +%TO.N,/Cpu/ENCGAUCHE_A*% +X141815000Y-115780000D02* +X146332500Y-115780000D01* +X138340500Y-114935000D02* +X140970000Y-114935000D01* +X144272000Y-104140000D02* +X144272000Y-99060000D01* +X141605000Y-104140000D02* +X138747500Y-104140000D01* +X138430000Y-104457500D02* +X138430000Y-109855000D01* +X140970000Y-114935000D02* +X141815000Y-115780000D01* +X138747500Y-104140000D02* +X138430000Y-104457500D01* +%TO.N,/Cpu/ENCGAUCHE_B*% +X148336000Y-105156000D02* +X143256000Y-105156000D01* +X125095000Y-92075000D02* +X125095000Y-80010000D01* +X125095000Y-80010000D02* +X125730000Y-79375000D01* +X148745000Y-108867500D02* +X148745000Y-105565000D01* +X125730000Y-92710000D02* +X125095000Y-92075000D01* +X143256000Y-105156000D02* +X143256000Y-93345000D01* +X142621000Y-92710000D02* +X125730000Y-92710000D01* +X131000000Y-80200000D02* +X131000000Y-81920000D01* +X143256000Y-93345000D02* +X142621000Y-92710000D01* +X148745000Y-105565000D02* +X148336000Y-105156000D01* +X130175000Y-79375000D02* +X131000000Y-80200000D01* +X125730000Y-79375000D02* +X130175000Y-79375000D01* +%TO.N,/Cpu/ENCDROIT_A*% +X142665000Y-110280000D02* +X146332500Y-110280000D01* +X126457494Y-127460000D02* +X128460000Y-127460000D01* +X120510489Y-114439511D02* +X120510489Y-118605489D01* +X125228747Y-126231253D02* +X126457494Y-127460000D01* +X141164800Y-108779800D02* +X142665000Y-110280000D01* +X120510489Y-118605489D02* +X122415489Y-118605489D01* +X125228747Y-121418747D02* +X125228747Y-126231253D01* +X127635000Y-114210500D02* +X120739500Y-114210500D01* +X139259800Y-108779800D02* +X141164800Y-108779800D01* +X122415489Y-118605489D02* +X125228747Y-121418747D01* +X120739500Y-114210500D02* +X120510489Y-114439511D01* +%TO.N,/Cpu/ENCDROIT_B*% +X149860000Y-110236000D02* +X148310994Y-110236000D01* +X148310994Y-110236000D02* +X147745000Y-109670006D01* +X149860000Y-113792000D02* +X149860000Y-110236000D01* +X147745000Y-109670006D02* +X147745000Y-108867500D01* +%TO.N,/Cpu/LED_ROUGE*% +X155785000Y-110280000D02* +X156845000Y-109220000D01* +X154657500Y-110280000D02* +X155785000Y-110280000D01* +X115570000Y-118745000D02* +X116840000Y-120015000D01* +X115570000Y-118110000D02* +X115570000Y-118745000D01* +%TO.N,/Cpu/LED_ORANGE*% +X156845000Y-110490000D02* +X156555000Y-110780000D01* +X118872000Y-120777000D02* +X119097980Y-121002980D01* +X118872000Y-120015000D02* +X118872000Y-120777000D01* +X156555000Y-110780000D02* +X154657500Y-110780000D01* +X119097980Y-121002980D02* +X122272980Y-121002980D01* +X122272980Y-121002980D02* +X122555000Y-121285000D01* +%TO.N,/Cpu/LED_VERTE*% +X157079614Y-111280000D02* +X158115000Y-110244614D01* +X158115000Y-110244614D02* +X158115000Y-109855000D01* +X154657500Y-111280000D02* +X157079614Y-111280000D01* +X122555000Y-120015000D02* +X120650000Y-120015000D01* +X124460000Y-121920000D02* +X122555000Y-120015000D01* +%TO.N,/Cpu/USART_RX*% +X135255000Y-114300000D02* +X135255000Y-112395000D01* +X121920000Y-114935000D02* +X134620000Y-114935000D01* +X152245000Y-108867500D02* +X152245000Y-106294500D01* +X121435000Y-116800000D02* +X121435000Y-115420000D01* +X152245000Y-106294500D02* +X151995500Y-106045000D01* +X121435000Y-115420000D02* +X121920000Y-114935000D01* +X134620000Y-114935000D02* +X135255000Y-114300000D01* +%TO.N,/Cpu/USART_TX*% +X135979500Y-113101755D02* +X135979500Y-114211218D01* +X123190000Y-116555000D02* +X123435000Y-116800000D01* +X135979500Y-114211218D02* +X134620718Y-115570000D01* +X123190000Y-116205000D02* +X123190000Y-116555000D01* +X123825000Y-115570000D02* +X123190000Y-116205000D01* +X134620718Y-115570000D02* +X123825000Y-115570000D01* +X151745000Y-107221962D02* +X151520500Y-106997462D01* +X151745000Y-108867500D02* +X151745000Y-107221962D01* +%TO.N,/Cpu/XBEE_RESET*% +X140970000Y-116205000D02* +X140699503Y-115934503D01* +X141522750Y-120650000D02* +X140970000Y-120097250D01* +X136525000Y-118110000D02* +X136525000Y-117945500D01* +X127635000Y-118110000D02* +X136525000Y-118110000D01* +X127435000Y-117910000D02* +X127635000Y-118110000D01* +X140970000Y-120097250D02* +X140970000Y-116205000D01* +X152469500Y-118745000D02* +X152745000Y-118469500D01* +X152745000Y-118469500D02* +X152745000Y-117192500D01* +X140699503Y-115934503D02* +X138340500Y-115934503D01* +X127435000Y-116800000D02* +X127435000Y-117910000D01* +X142710500Y-120650000D02* +X141522750Y-120650000D01* +D45* +%TO.N,Net-(JP1-Pad2)*% +X150495000Y-123467500D02* +X149860000Y-122832500D01* +X150495000Y-126365000D02* +X150495000Y-123467500D01* +D46* +%TO.N,Net-(R24-Pad2)*% +X132642500Y-110132500D02* +X132605000Y-110170000D01* +X135255000Y-110132500D02* +X132642500Y-110132500D01* +X132357500Y-112395000D02* +X132357500Y-110417500D01* +X132357500Y-110417500D02* +X132605000Y-110170000D01* +D43* +%TO.N,/Cpu/CHARGER_ST1*% +X153670000Y-128270000D02* +X153670000Y-124460000D01* +X177165000Y-122555000D02* +X177165000Y-123825000D01* +X152845480Y-123635480D02* +X152845480Y-121731197D01* +X169545000Y-127000000D02* +X162560000Y-127000000D01* +X154305000Y-128905000D02* +X153670000Y-128270000D01* +X181813200Y-115685001D02* +X182360001Y-115685001D01* +X153670000Y-124460000D02* +X152845480Y-123635480D01* +X162560000Y-127000000D02* +X160655000Y-128905000D01* +X150245000Y-119130717D02* +X150245000Y-117192500D01* +X177165000Y-123825000D02* +X176530000Y-124460000D01* +X170180000Y-124460000D02* +X169545000Y-125095000D01* +X176530000Y-124460000D02* +X170180000Y-124460000D01* +X182360001Y-115685001D02* +X182880000Y-116205000D01* +X152845480Y-121731197D02* +X150245000Y-119130717D01* +X160655000Y-128905000D02* +X154305000Y-128905000D01* +X169545000Y-125095000D02* +X169545000Y-127000000D01* +%TO.N,/Cpu/SHUTDOWN*% +X135255000Y-132715000D02* +X135890000Y-132080000D01* +X148745000Y-117192500D02* +X148745000Y-119135500D01* +X120539520Y-128794520D02* +X124460000Y-132715000D01* +X113175960Y-123655594D02* +X113175960Y-127326274D01* +X114644206Y-128794520D02* +X120539520Y-128794520D01* +X135890000Y-125095000D02* +X135890000Y-132080000D01* +X124460000Y-132715000D02* +X135255000Y-132715000D01* +X113175960Y-127326274D02* +X114644206Y-128794520D01* +X148745000Y-119135500D02* +X146050000Y-121830500D01* +X111760000Y-122239634D02* +X113175960Y-123655594D01* +%TO.N,/Cpu/CHARGER_ST2*% +X175895000Y-118745000D02* +X177165000Y-120015000D01* +X177165000Y-120015000D02* +X178308000Y-118872000D01* +X182630000Y-115185000D02* +X182880000Y-114935000D01* +X171704000Y-118745000D02* +X175895000Y-118745000D01* +X150745000Y-118469500D02* +X151020500Y-118745000D01* +X169545000Y-118745000D02* +X157480000Y-118745000D01* +X157480000Y-118745000D02* +X156210000Y-120015000D01* +X178308000Y-118872000D02* +X178816000Y-118872000D01* +X150745000Y-117192500D02* +X150745000Y-118469500D01* +X181813200Y-115185000D02* +X182630000Y-115185000D01* +%TO.N,/Cpu/PWM_GAUCHE_A*% +X162560000Y-108585000D02* +X162560000Y-99060000D01* +X161830000Y-98330000D02* +X153045000Y-98330000D01* +X158865000Y-112280000D02* +X162560000Y-108585000D01* +X154657500Y-112280000D02* +X158865000Y-112280000D01* +X162560000Y-99060000D02* +X161830000Y-98330000D01* +%TO.N,/Cpu/PWM_GAUCHE_B*% +X154940000Y-99060000D02* +X154670000Y-99330000D01* +X147309480Y-110754520D02* +X147394520Y-110669480D01* +X146812000Y-109372724D02* +X146812000Y-105955500D01* +X154670000Y-99330000D02* +X153045000Y-99330000D01* +X146332500Y-110772500D02* +X146350480Y-110754520D01* +X147394520Y-109955244D02* +X146812000Y-109372724D01* +X146332500Y-110780000D02* +X146332500Y-110772500D01* +X147394520Y-110669480D02* +X147394520Y-109955244D01* +X146350480Y-110754520D02* +X147309480Y-110754520D01* +%TO.N,/Cpu/BUTTON_SENSE*% +X114300000Y-121285000D02* +X113665000Y-120650000D01* +X151425006Y-115570000D02* +X152245000Y-116389994D01* +X115387601Y-121285000D02* +X114300000Y-121285000D01* +X150368000Y-115570000D02* +X151425006Y-115570000D01* +X152245000Y-116389994D02* +X152245000Y-117192500D01* +%TO.N,/Cpu/USB_SENSE*% +X152654000Y-120904000D02* +X151745000Y-119995000D01* +X151745000Y-119995000D02* +X151745000Y-117192500D01* +X168632500Y-123190000D02* +X168632500Y-121388500D01* +D46* +X168632500Y-123190000D02* +X168632500Y-125730000D01* +D43* +X168632500Y-121388500D02* +X168148000Y-120904000D01* +X168148000Y-120904000D02* +X152654000Y-120904000D01* +%TO.N,/Cpu/BATTERY_SENSE*% +X148816000Y-111280000D02* +X148844000Y-111252000D01* +X166619701Y-122423701D02* +X167132000Y-122936000D01* +X146332500Y-111280000D02* +X148816000Y-111280000D01* +D46* +X168632500Y-130071500D02* +X168632500Y-131445000D01* +X168632500Y-128905000D02* +X168632500Y-130071500D01* +D43* +X167132000Y-122936000D02* +X167132000Y-125984000D01* +X157983701Y-122423701D02* +X166619701Y-122423701D01* +%TO.N,/Cpu/SHUTDOWN_ENC*% +X135255000Y-108307500D02* +X137056500Y-108307500D01* +X154657500Y-111780000D02* +X158095000Y-111780000D01* +X137056500Y-108307500D02* +X137160000Y-108204000D01* +X158095000Y-111780000D02* +X159385000Y-110490000D01* +D48* +%TO.N,Net-(R26-Pad2)*% +X149745000Y-117192500D02* +X149745000Y-120892500D01* +X149745000Y-120892500D02* +X149860000Y-121007500D01* +D43* +%TO.N,/Cpu/SWDIO*% +X152908000Y-113833006D02* +X153854994Y-114780000D01* +X168910000Y-113825000D02* +X168910000Y-118110000D01* +X168830000Y-113745000D02* +X168910000Y-113825000D01* +X170735000Y-113745000D02* +X171450000Y-113030000D01* +X167005000Y-113745000D02* +X168830000Y-113745000D01* +X152908000Y-113030000D02* +X152908000Y-113833006D01* +X168830000Y-113745000D02* +X170735000Y-113745000D01* +X153854994Y-114780000D02* +X154657500Y-114780000D01* +X171450000Y-113030000D02* +X171450000Y-104775000D01* +X168724520Y-118295480D02* +X156395480Y-118295480D01* +X168910000Y-118110000D02* +X168724520Y-118295480D01* +%TO.N,/Cpu/PWM_DROIT_A*% +X150765000Y-101330000D02* +X150245000Y-101850000D01* +X150245000Y-101850000D02* +X150245000Y-108867500D01* +X153045000Y-101330000D02* +X150765000Y-101330000D01* +%TO.N,/Cpu/PWM_DROIT_B*% +X150745000Y-108867500D02* +X150745000Y-102620000D01* +X151035000Y-102330000D02* +X153045000Y-102330000D01* +X150745000Y-102620000D02* +X151035000Y-102330000D01* +%TO.N,/Cpu/SWCLK*% +X169545000Y-112395000D02* +X167005000Y-112395000D01* +X165100000Y-112395000D02* +X164465000Y-113030000D01* +X170180000Y-111760000D02* +X169545000Y-112395000D01* +X164465000Y-113030000D02* +X164465000Y-113745000D01* +X153245000Y-117192500D02* +X159737500Y-117192500D01* +X159737500Y-117192500D02* +X160020000Y-117475000D01* +X167005000Y-112395000D02* +X165100000Y-112395000D01* +X170180000Y-105410000D02* +X170180000Y-111760000D01* +%TO.N,/Cpu/SHUTDOWN_5V*% +X147512007Y-121830500D02* +X147320000Y-121830500D01* +X149245000Y-117192500D02* +X149245000Y-120097507D01* +X175797500Y-88265000D02* +X175930000Y-88397500D01* +X173990000Y-88265000D02* +X175797500Y-88265000D01* +X149245000Y-120097507D02* +X147512007Y-121830500D01* +X186690000Y-113284000D02* +X186690000Y-110490000D01* +D47* +%TO.N,Net-(C6-Pad1)*% +X176530000Y-98425000D02* +X175575000Y-98425000D01* +X141224000Y-100330000D02* +X141224000Y-93980000D01* +D44* +X172725000Y-99375000D02* +X173040000Y-99060000D01* +X170180000Y-92710000D02* +X171267500Y-92710000D01* +D47* +X168050000Y-93570000D02* +X168910000Y-92710000D01* +X169545000Y-98835000D02* +X172185000Y-98835000D01* +X168910000Y-92710000D02* +X170180000Y-92710000D01* +D44* +X172725000Y-102235000D02* +X172725000Y-99375000D01* +D47* +X169545000Y-98835000D02* +X168050000Y-98835000D01* +D44* +X172185000Y-98835000D02* +X172725000Y-99375000D01* +X175575000Y-98425000D02* +X174940000Y-99060000D01* +X170780000Y-92110000D02* +X170180000Y-92710000D01* +X171267500Y-92710000D02* +X172405000Y-91572500D01* +X170780000Y-88397500D02* +X170780000Y-92110000D01* +D47* +X168050000Y-98835000D02* +X168050000Y-93570000D01* +%TD*% +%TA.AperFunction,Conductor*% +%TO.N,GND*% +G36* +X132183621Y-63528502D02* +G01* +X132230114Y-63582158D01* +X132241500Y-63634500D01* +X132241500Y-71491377D01* +X132241498Y-71492147D01* +X132241024Y-71569721D01* +X132243491Y-71578352D01* +X132249150Y-71598153D01* +X132252728Y-71614915D01* +X132256920Y-71644187D01* +X132260634Y-71652355D01* +X132260634Y-71652356D01* +X132267548Y-71667562D01* +X132273996Y-71685086D01* +X132281051Y-71709771D01* +X132285843Y-71717365D01* +X132285844Y-71717368D01* +X132296830Y-71734780D01* +X132304969Y-71749863D01* +X132317208Y-71776782D01* +X132323069Y-71783584D01* +X132333970Y-71796235D01* +X132345073Y-71811239D01* +X132358776Y-71832958D01* +X132365501Y-71838897D01* +X132365504Y-71838901D01* +X132380938Y-71852532D01* +X132392982Y-71864724D01* +X132406427Y-71880327D01* +X132406430Y-71880329D01* +X132412287Y-71887127D01* +X132419816Y-71892007D01* +X132419817Y-71892008D01* +X132433835Y-71901094D01* +X132448709Y-71912385D01* +X132461217Y-71923431D01* +X132467951Y-71929378D01* +X132494711Y-71941942D01* +X132509691Y-71950263D01* +X132526983Y-71961471D01* +X132526988Y-71961473D01* +X132534515Y-71966352D01* +X132543108Y-71968922D01* +X132543113Y-71968924D01* +X132559120Y-71973711D01* +X132576564Y-71980372D01* +X132591676Y-71987467D01* +X132591678Y-71987468D01* +X132599800Y-71991281D01* +X132608667Y-71992662D01* +X132608668Y-71992662D01* +X132611353Y-71993080D01* +X132629017Y-71995830D01* +X132645732Y-71999613D01* +X132665466Y-72005515D01* +X132665472Y-72005516D01* +X132674066Y-72008086D01* +X132683037Y-72008141D01* +X132683038Y-72008141D01* +X132693097Y-72008202D01* +X132708506Y-72008296D01* +X132709289Y-72008329D01* +X132710386Y-72008500D01* +X132741377Y-72008500D01* +X132742147Y-72008502D01* +X132815785Y-72008952D01* +X132815786Y-72008952D01* +X132819721Y-72008976D01* +X132821065Y-72008592D01* +X132822410Y-72008500D01* +X167741377Y-72008500D01* +X167742148Y-72008502D01* +X167819721Y-72008976D01* +X167848152Y-72000850D01* +X167864915Y-71997272D01* +X167865753Y-71997152D01* +X167894187Y-71993080D01* +X167917564Y-71982451D01* +X167935087Y-71976004D01* +X167959771Y-71968949D01* +X167967365Y-71964157D01* +X167967368Y-71964156D01* +X167984780Y-71953170D01* +X167999865Y-71945030D01* +X168026782Y-71932792D01* +X168046235Y-71916030D01* +X168061239Y-71904927D01* +X168082958Y-71891224D01* +X168088897Y-71884499D01* +X168088901Y-71884496D01* +X168102532Y-71869062D01* +X168114724Y-71857018D01* +X168130327Y-71843573D01* +X168130329Y-71843570D01* +X168137127Y-71837713D01* +X168151094Y-71816165D01* +X168162385Y-71801291D01* +X168173431Y-71788783D01* +X168173432Y-71788782D01* +X168179378Y-71782049D01* +X168191943Y-71755287D01* +X168200263Y-71740309D01* +X168211471Y-71723017D01* +X168211473Y-71723012D01* +X168216352Y-71715485D01* +X168218922Y-71706892D01* +X168218924Y-71706887D01* +X168223711Y-71690880D01* +X168230372Y-71673436D01* +X168237467Y-71658324D01* +X168237468Y-71658322D01* +X168241281Y-71650200D01* +X168245830Y-71620983D01* +X168249613Y-71604268D01* +X168255515Y-71584534D01* +X168255516Y-71584528D01* +X168258086Y-71575934D01* +X168258296Y-71541494D01* +X168258329Y-71540711D01* +X168258500Y-71539614D01* +X168258500Y-71508623D01* +X168258502Y-71507853D01* +X168258952Y-71434215D01* +X168258952Y-71434214D01* +X168258976Y-71430279D01* +X168258592Y-71428935D01* +X168258500Y-71427590D01* +X168258500Y-69977869D01* +X171636689Y-69977869D01* +X171653238Y-70264883D01* +X171654063Y-70269088D01* +X171654064Y-70269096D01* +X171673821Y-70369798D01* +X171708586Y-70546995D01* +X171709973Y-70551045D01* +X171709974Y-70551050D01* +X171785557Y-70771807D01* +X171801710Y-70818986D01* +X171803637Y-70822817D01* +X171891310Y-70997135D01* +X171930885Y-71075822D01* +X172093721Y-71312750D01* +X172096608Y-71315923D01* +X172096609Y-71315924D01* +X172137329Y-71360675D01* +X172287206Y-71525388D01* +X172290501Y-71528143D01* +X172290502Y-71528144D01* +X172497402Y-71701138D01* +X172507759Y-71709798D01* +X172751298Y-71862571D01* +X173013318Y-71980877D01* +X173072778Y-71998490D01* +X173284857Y-72061311D01* +X173284862Y-72061312D01* +X173288970Y-72062529D01* +X173293204Y-72063177D01* +X173293209Y-72063178D01* +X173541811Y-72101219D01* +X173573153Y-72106015D01* +X173719485Y-72108314D01* +X173856317Y-72110464D01* +X173856323Y-72110464D01* +X173860608Y-72110531D01* +X173864860Y-72110016D01* +X173864868Y-72110016D01* +X174141756Y-72076508D01* +X174141761Y-72076507D01* +X174146017Y-72075992D01* +X174401558Y-72008952D01* +X174419954Y-72004126D01* +X174419955Y-72004126D01* +X174424097Y-72003039D01* +X174689704Y-71893021D01* +X174834671Y-71808309D01* +X174934219Y-71750138D01* +X174934220Y-71750137D01* +X174937922Y-71747974D01* +X175164159Y-71570582D01* +X175205285Y-71528144D01* +X175361244Y-71367206D01* +X175364227Y-71364128D01* +X175366760Y-71360680D01* +X175366764Y-71360675D01* +X175531887Y-71135886D01* +X175534425Y-71132431D01* +X175607885Y-70997135D01* +X175669554Y-70883555D01* +X175669555Y-70883553D01* +X175671604Y-70879779D01* +X175773225Y-70610848D01* +X175811449Y-70443953D01* +X175836449Y-70334797D01* +X175836450Y-70334793D01* +X175837407Y-70330613D01* +X175843577Y-70261487D01* +X175862743Y-70046726D01* +X175862743Y-70046724D01* +X175862963Y-70044260D01* +X175863427Y-70000000D01* +X175847956Y-69773064D01* +X175844165Y-69717452D01* +X175844164Y-69717446D01* +X175843873Y-69713175D01* +X175839336Y-69691264D01* +X175809479Y-69547091D01* +X175785574Y-69431658D01* +X175689607Y-69160657D01* +X175557750Y-68905188D01* +X175544488Y-68886317D01* +X175394904Y-68673482D01* +X175392441Y-68669977D01* +X175196740Y-68459378D01* +X174974268Y-68277287D01* +X174729142Y-68127073D01* +X174711048Y-68119130D01* +X174469830Y-68013243D01* +X174465898Y-68011517D01* +X174439963Y-68004129D01* +X174193534Y-67933932D01* +X174193535Y-67933932D01* +X174189406Y-67932756D01* +X173961467Y-67900316D01* +X173909036Y-67892854D01* +X173909034Y-67892854D01* +X173904784Y-67892249D01* +X173900495Y-67892227D01* +X173900488Y-67892226D01* +X173621583Y-67890765D01* +X173621576Y-67890765D01* +X173617297Y-67890743D01* +X173613053Y-67891302D01* +X173613049Y-67891302D01* +X173487660Y-67907810D01* +X173332266Y-67928268D01* +X173328126Y-67929401D01* +X173328124Y-67929401D01* +X173251311Y-67950415D01* +X173054964Y-68004129D01* +X173051016Y-68005813D01* +X172794476Y-68115237D01* +X172794472Y-68115239D01* +X172790524Y-68116923D01* +X172711107Y-68164453D01* +X172547521Y-68262357D01* +X172547517Y-68262360D01* +X172543839Y-68264561D01* +X172319472Y-68444313D01* +X172121577Y-68652851D01* +X171953814Y-68886317D01* +X171819288Y-69140392D01* +X171720489Y-69410373D01* +X171659245Y-69691264D01* +X171652807Y-69773064D01* +X171637196Y-69971428D01* +X171637195Y-69971428D01* +X171637196Y-69971430D01* +X171636689Y-69977869D01* +X168258500Y-69977869D01* +X168258500Y-63634500D01* +X168278502Y-63566379D01* +X168332158Y-63519886D01* +X168384500Y-63508500D01* +X172700633Y-63508500D01* +X172720018Y-63510000D01* +X172734851Y-63512310D01* +X172734855Y-63512310D01* +X172743724Y-63513691D01* +X172752625Y-63512527D01* +X172752629Y-63512527D01* +X172769723Y-63510291D01* +X172788517Y-63509251D01* +X173710672Y-63527239D01* +X173715560Y-63527431D01* +X174672307Y-63583476D01* +X174677187Y-63583857D01* +X175631031Y-63677174D01* +X175635903Y-63677747D01* +X175978249Y-63724779D01* +X176585342Y-63808184D01* +X176590197Y-63808947D01* +X176792161Y-63844768D01* +X177533902Y-63976325D01* +X177538669Y-63977267D01* +X178475106Y-64181316D01* +X178479862Y-64182450D01* +X179407611Y-64422859D01* +X179412321Y-64424178D01* +X180324655Y-64698978D01* +X180329987Y-64700584D01* +X180334662Y-64702092D01* +X180617060Y-64799316D01* +X181240839Y-65014071D01* +X181245454Y-65015761D01* +X182138786Y-65362847D01* +X182143331Y-65364716D01* +X182475798Y-65509053D01* +X183022457Y-65746379D01* +X183026884Y-65748405D01* +X183890463Y-66164067D01* +X183894805Y-66166262D01* +X184741536Y-66615295D01* +X184745793Y-66617660D01* +X185544053Y-67081749D01* +X185574366Y-67099372D01* +X185578564Y-67101925D01* +X186387658Y-67615542D01* +X186391730Y-67618240D01* +X186842066Y-67929401D01* +X187180229Y-68163056D01* +X187184217Y-68165928D01* +X187950869Y-68741080D01* +X187954704Y-68744076D01* +X188287713Y-69014828D01* +X188698323Y-69348673D01* +X188702075Y-69351847D01* +X189006888Y-69620082D01* +X189413466Y-69977869D01* +X189421535Y-69984970D01* +X189425150Y-69988278D01* +X189616878Y-70170748D01* +X190119401Y-70649006D01* +X190122894Y-70652463D01* +X190790827Y-71339739D01* +X190794183Y-71343330D01* +X191434810Y-72056137D01* +X191438023Y-72059856D01* +X192050349Y-72797086D01* +X192053415Y-72800927D01* +X192636538Y-73561492D01* +X192639452Y-73565450D01* +X193192467Y-74348175D01* +X193195224Y-74352243D01* +X193717302Y-75155952D01* +X193719898Y-75160125D01* +X194210220Y-75983555D01* +X194212652Y-75987826D01* +X194670505Y-76829782D01* +X194672765Y-76834138D01* +X194824877Y-77141885D01* +X195097415Y-77693273D01* +X195099507Y-77697720D01* +X195490353Y-78572812D01* +X195492269Y-78577338D01* +X195671934Y-79025802D01* +X195844068Y-79455468D01* +X195848678Y-79466976D01* +X195850412Y-79471562D01* +X195944101Y-79734712D01* +X196171854Y-80374419D01* +X196173412Y-80379080D01* +X196459403Y-81293797D01* +X196460778Y-81298516D01* +X196710877Y-82223681D01* +X196712064Y-82228436D01* +X196925901Y-83162692D01* +X196926895Y-83167462D01* +X196953060Y-83306507D01* +X197104133Y-84109338D01* +X197104947Y-84114184D01* +X197184239Y-84649715D01* +X197238337Y-85015089D01* +X197238868Y-85018678D01* +X197240181Y-85040528D01* +X197239680Y-85059088D01* +X197241129Y-85064592D01* +X197241500Y-85071014D01* +X197241500Y-126927194D01* +X197241454Y-126927849D01* +X197241276Y-126928464D01* +X197241312Y-126942696D01* +X197241343Y-126954682D01* +X197239984Y-126973458D01* +X197184492Y-127348254D01* +X197104902Y-127885807D01* +X197104088Y-127890654D01* +X196928038Y-128826233D01* +X196926855Y-128832518D01* +X196925855Y-128837313D01* +X196712025Y-129771545D01* +X196710839Y-129776300D01* +X196627891Y-130083143D01* +X196460736Y-130701486D01* +X196459361Y-130706204D01* +X196308591Y-131188434D01* +X196179654Y-131600835D01* +X196173378Y-131620907D01* +X196171823Y-131625560D01* +X195850371Y-132528450D01* +X195848653Y-132532993D01* +X195670387Y-132977969D01* +X195492236Y-133422657D01* +X195490320Y-133427183D01* +X195099476Y-134302274D01* +X195097384Y-134306721D01* +X194672738Y-135165850D01* +X194670475Y-135170213D01* +X194212624Y-136012170D01* +X194210192Y-136016441D01* +X193719872Y-136839872D01* +X193717276Y-136844045D01* +X193195200Y-137647753D01* +X193192443Y-137651821D01* +X192639429Y-138434547D01* +X192636515Y-138438505D01* +X192053394Y-139199070D01* +X192050328Y-139202911D01* +X191437988Y-139940159D01* +X191434805Y-139943844D01* +X191145973Y-140265220D01* +X190794165Y-140656668D01* +X190790809Y-140660259D01* +X190122877Y-141347535D01* +X190119384Y-141350992D01* +X189968232Y-141494846D01* +X189456201Y-141982154D01* +X189425145Y-142011710D01* +X189421529Y-142015019D01* +X188702040Y-142648171D01* +X188698330Y-142651309D01* +X187954691Y-143255923D01* +X187950856Y-143258919D01* +X187806515Y-143367206D01* +X187184204Y-143834071D01* +X187180216Y-143836943D01* +X186391743Y-144381744D01* +X186387646Y-144384458D01* +X185578520Y-144898098D01* +X185574369Y-144900621D01* +X184745783Y-145382341D01* +X184741526Y-145384706D01* +X183894796Y-145833740D01* +X183890454Y-145835935D01* +X183026877Y-146251596D01* +X183022450Y-146253622D01* +X182590108Y-146441319D01* +X182143324Y-146635286D01* +X182138779Y-146637155D01* +X181245448Y-146984242D01* +X181240841Y-146985929D01* +X180617063Y-147200684D01* +X180334660Y-147297910D01* +X180329985Y-147299418D01* +X179412317Y-147575825D01* +X179407607Y-147577144D01* +X178479858Y-147817553D01* +X178475102Y-147818687D01* +X177538675Y-148022734D01* +X177533890Y-148023680D01* +X176859936Y-148143215D01* +X176590194Y-148191057D01* +X176585339Y-148191820D01* +X175978669Y-148275167D01* +X175635901Y-148322257D01* +X175631029Y-148322830D01* +X174677186Y-148416146D01* +X174672306Y-148416527D01* +X173715559Y-148472573D01* +X173710671Y-148472765D01* +X172796210Y-148490603D01* +X172774368Y-148489126D01* +X172765150Y-148487690D01* +X172765145Y-148487690D01* +X172756276Y-148486309D01* +X172747374Y-148487473D01* +X172747372Y-148487473D01* +X172732323Y-148489441D01* +X172724714Y-148490436D01* +X172708379Y-148491500D01* +X168384500Y-148491500D01* +X168316379Y-148471498D01* +X168269886Y-148417842D01* +X168258500Y-148365500D01* +X168258500Y-141977869D01* +X171636689Y-141977869D01* +X171636936Y-141982153D01* +X171636936Y-141982154D01* +X171638832Y-142015028D01* +X171653238Y-142264883D01* +X171654063Y-142269088D01* +X171654064Y-142269096D01* +X171673821Y-142369798D01* +X171708586Y-142546995D01* +X171709973Y-142551045D01* +X171709974Y-142551050D01* +X171785557Y-142771807D01* +X171801710Y-142818986D01* +X171803637Y-142822817D01* +X171891310Y-142997135D01* +X171930885Y-143075822D01* +X172093721Y-143312750D01* +X172287206Y-143525388D01* +X172290501Y-143528143D01* +X172290502Y-143528144D01* +X172341258Y-143570582D01* +X172507759Y-143709798D01* +X172751298Y-143862571D01* +X173013318Y-143980877D01* +X173017437Y-143982097D01* +X173284857Y-144061311D01* +X173284862Y-144061312D01* +X173288970Y-144062529D01* +X173293204Y-144063177D01* +X173293209Y-144063178D01* +X173514089Y-144096977D01* +X173573153Y-144106015D01* +X173719485Y-144108314D01* +X173856317Y-144110464D01* +X173856323Y-144110464D01* +X173860608Y-144110531D01* +X173864860Y-144110016D01* +X173864868Y-144110016D01* +X174141756Y-144076508D01* +X174141761Y-144076507D01* +X174146017Y-144075992D01* +X174424097Y-144003039D01* +X174689704Y-143893021D01* +X174937922Y-143747974D01* +X175164159Y-143570582D01* +X175205285Y-143528144D01* +X175361244Y-143367206D01* +X175364227Y-143364128D01* +X175366760Y-143360680D01* +X175366764Y-143360675D01* +X175531887Y-143135886D01* +X175534425Y-143132431D01* +X175536471Y-143128663D01* +X175669554Y-142883555D01* +X175669555Y-142883553D01* +X175671604Y-142879779D01* +X175773225Y-142610848D01* +X175811664Y-142443012D01* +X175836449Y-142334797D01* +X175836450Y-142334793D01* +X175837407Y-142330613D01* +X175843577Y-142261487D01* +X175862743Y-142046726D01* +X175862743Y-142046724D01* +X175862963Y-142044260D01* +X175863427Y-142000000D01* +X175847956Y-141773064D01* +X175844165Y-141717452D01* +X175844164Y-141717446D01* +X175843873Y-141713175D01* +X175839336Y-141691264D01* +X175809479Y-141547091D01* +X175785574Y-141431658D01* +X175689607Y-141160657D01* +X175557750Y-140905188D01* +X175544488Y-140886317D01* +X175394904Y-140673482D01* +X175392441Y-140669977D01* +X175287620Y-140557176D01* +X175199661Y-140462521D01* +X175199658Y-140462519D01* +X175196740Y-140459378D01* +X174974268Y-140277287D01* +X174729142Y-140127073D01* +X174712285Y-140119673D01* +X174469830Y-140013243D01* +X174465898Y-140011517D01* +X174440107Y-140004170D01* +X174228390Y-139943861D01* +X174189406Y-139932756D01* +X173976704Y-139902485D01* +X173909036Y-139892854D01* +X173909034Y-139892854D01* +X173904784Y-139892249D01* +X173900495Y-139892227D01* +X173900488Y-139892226D01* +X173621583Y-139890765D01* +X173621576Y-139890765D01* +X173617297Y-139890743D01* +X173613053Y-139891302D01* +X173613049Y-139891302D01* +X173487660Y-139907810D01* +X173332266Y-139928268D01* +X173328126Y-139929401D01* +X173328124Y-139929401D01* +X173288862Y-139940142D01* +X173054964Y-140004129D01* +X173051016Y-140005813D01* +X172794476Y-140115237D01* +X172794472Y-140115239D01* +X172790524Y-140116923D01* +X172702145Y-140169817D01* +X172547521Y-140262357D01* +X172547517Y-140262360D01* +X172543839Y-140264561D01* +X172319472Y-140444313D01* +X172121577Y-140652851D01* +X171953814Y-140886317D01* +X171819288Y-141140392D01* +X171720489Y-141410373D01* +X171659245Y-141691264D01* +X171654068Y-141757040D01* +X171637196Y-141971428D01* +X171637195Y-141971428D01* +X171637196Y-141971430D01* +X171636689Y-141977869D01* +X168258500Y-141977869D01* +X168258500Y-140508623D01* +X168258502Y-140507853D01* +X168258800Y-140459102D01* +X168258976Y-140430279D01* +X168250850Y-140401847D01* +X168247272Y-140385085D01* +X168244352Y-140364698D01* +X168243080Y-140355813D01* +X168232451Y-140332436D01* +X168226004Y-140314913D01* +X168221416Y-140298862D01* +X168218949Y-140290229D01* +X168212497Y-140280003D01* +X168203170Y-140265220D01* +X168195030Y-140250135D01* +X168192564Y-140244711D01* +X168182792Y-140223218D01* +X168166030Y-140203765D01* +X168154927Y-140188761D01* +X168141224Y-140167042D01* +X168134499Y-140161103D01* +X168134496Y-140161099D01* +X168119062Y-140147468D01* +X168107018Y-140135276D01* +X168093573Y-140119673D01* +X168093570Y-140119671D01* +X168087713Y-140112873D01* +X168074009Y-140103990D01* +X168066165Y-140098906D01* +X168051291Y-140087615D01* +X168038783Y-140076569D01* +X168038782Y-140076568D01* +X168032049Y-140070622D01* +X168005287Y-140058057D01* +X167990309Y-140049737D01* +X167973017Y-140038529D01* +X167973012Y-140038527D01* +X167965485Y-140033648D01* +X167956892Y-140031078D01* +X167956887Y-140031076D01* +X167940880Y-140026289D01* +X167923436Y-140019628D01* +X167908324Y-140012533D01* +X167908322Y-140012532D01* +X167900200Y-140008719D01* +X167891333Y-140007338D01* +X167891332Y-140007338D01* +X167880478Y-140005648D01* +X167870983Y-140004170D01* +X167854268Y-140000387D01* +X167834534Y-139994485D01* +X167834528Y-139994484D01* +X167825934Y-139991914D01* +X167816963Y-139991859D01* +X167816962Y-139991859D01* +X167806903Y-139991798D01* +X167791494Y-139991704D01* +X167790711Y-139991671D01* +X167789614Y-139991500D01* +X167758623Y-139991500D01* +X167757853Y-139991498D01* +X167684215Y-139991048D01* +X167684214Y-139991048D01* +X167680279Y-139991024D01* +X167678935Y-139991408D01* +X167677590Y-139991500D01* +X132758623Y-139991500D01* +X132757853Y-139991498D01* +X132757037Y-139991493D01* +X132680279Y-139991024D01* +X132657918Y-139997415D01* +X132651847Y-139999150D01* +X132635085Y-140002728D01* +X132605813Y-140006920D01* +X132597645Y-140010634D01* +X132597644Y-140010634D01* +X132582438Y-140017548D01* +X132564914Y-140023996D01* +X132540229Y-140031051D01* +X132532635Y-140035843D01* +X132532632Y-140035844D01* +X132515220Y-140046830D01* +X132500137Y-140054969D01* +X132473218Y-140067208D01* +X132466416Y-140073069D01* +X132453765Y-140083970D01* +X132438761Y-140095073D01* +X132417042Y-140108776D01* +X132411103Y-140115501D01* +X132411099Y-140115504D01* +X132397468Y-140130938D01* +X132385276Y-140142982D01* +X132369673Y-140156427D01* +X132369671Y-140156430D01* +X132362873Y-140162287D01* +X132357993Y-140169816D01* +X132357992Y-140169817D01* +X132348906Y-140183835D01* +X132337615Y-140198709D01* +X132326569Y-140211217D01* +X132320622Y-140217951D01* +X132314312Y-140231391D01* +X132308058Y-140244711D01* +X132299737Y-140259691D01* +X132288529Y-140276983D01* +X132288527Y-140276988D01* +X132283648Y-140284515D01* +X132281078Y-140293108D01* +X132281076Y-140293113D01* +X132276289Y-140309120D01* +X132269628Y-140326564D01* +X132262533Y-140341676D01* +X132258719Y-140349800D01* +X132257338Y-140358667D01* +X132257338Y-140358668D01* +X132254170Y-140379015D01* +X132250387Y-140395732D01* +X132244485Y-140415466D01* +X132244484Y-140415472D01* +X132241914Y-140424066D01* +X132241859Y-140433037D01* +X132241859Y-140433038D01* +X132241704Y-140458497D01* +X132241671Y-140459289D01* +X132241500Y-140460386D01* +X132241500Y-140491377D01* +X132241498Y-140492147D01* +X132241024Y-140569721D01* +X132241408Y-140571065D01* +X132241500Y-140572410D01* +X132241500Y-148365500D01* +X132221498Y-148433621D01* +X132167842Y-148480114D01* +X132115500Y-148491500D01* +X127941898Y-148491500D01* +X127872037Y-148470359D01* +X127020759Y-147903203D01* +X127017521Y-147900972D01* +X126035953Y-147201826D01* +X126032786Y-147199495D01* +X125293256Y-146637155D01* +X125073501Y-146470052D01* +X125070416Y-146467630D01* +X124291398Y-145835946D01* +X124134362Y-145708611D01* +X124131349Y-145706088D01* +X123219461Y-144918251D01* +X123216526Y-144915634D01* +X122329620Y-144099684D01* +X122326768Y-144096977D01* +X121465807Y-143253800D01* +X121463041Y-143251006D01* +X120942976Y-142708873D01* +X120628738Y-142381301D01* +X120626107Y-142378470D01* +X120265130Y-141977869D01* +X125636689Y-141977869D01* +X125636936Y-141982153D01* +X125636936Y-141982154D01* +X125638832Y-142015028D01* +X125653238Y-142264883D01* +X125654063Y-142269088D01* +X125654064Y-142269096D01* +X125673821Y-142369798D01* +X125708586Y-142546995D01* +X125709973Y-142551045D01* +X125709974Y-142551050D01* +X125785557Y-142771807D01* +X125801710Y-142818986D01* +X125803637Y-142822817D01* +X125891310Y-142997135D01* +X125930885Y-143075822D01* +X126093721Y-143312750D01* +X126287206Y-143525388D01* +X126290501Y-143528143D01* +X126290502Y-143528144D01* +X126341258Y-143570582D01* +X126507759Y-143709798D01* +X126751298Y-143862571D01* +X127013318Y-143980877D01* +X127017437Y-143982097D01* +X127284857Y-144061311D01* +X127284862Y-144061312D01* +X127288970Y-144062529D01* +X127293204Y-144063177D01* +X127293209Y-144063178D01* +X127514089Y-144096977D01* +X127573153Y-144106015D01* +X127719485Y-144108314D01* +X127856317Y-144110464D01* +X127856323Y-144110464D01* +X127860608Y-144110531D01* +X127864860Y-144110016D01* +X127864868Y-144110016D01* +X128141756Y-144076508D01* +X128141761Y-144076507D01* +X128146017Y-144075992D01* +X128424097Y-144003039D01* +X128689704Y-143893021D01* +X128937922Y-143747974D01* +X129164159Y-143570582D01* +X129205285Y-143528144D01* +X129361244Y-143367206D01* +X129364227Y-143364128D01* +X129366760Y-143360680D01* +X129366764Y-143360675D01* +X129531887Y-143135886D01* +X129534425Y-143132431D01* +X129536471Y-143128663D01* +X129669554Y-142883555D01* +X129669555Y-142883553D01* +X129671604Y-142879779D01* +X129773225Y-142610848D01* +X129811664Y-142443012D01* +X129836449Y-142334797D01* +X129836450Y-142334793D01* +X129837407Y-142330613D01* +X129843577Y-142261487D01* +X129862743Y-142046726D01* +X129862743Y-142046724D01* +X129862963Y-142044260D01* +X129863427Y-142000000D01* +X129847956Y-141773064D01* +X129844165Y-141717452D01* +X129844164Y-141717446D01* +X129843873Y-141713175D01* +X129839336Y-141691264D01* +X129809479Y-141547091D01* +X129785574Y-141431658D01* +X129689607Y-141160657D01* +X129557750Y-140905188D01* +X129544488Y-140886317D01* +X129394904Y-140673482D01* +X129392441Y-140669977D01* +X129287620Y-140557176D01* +X129199661Y-140462521D01* +X129199658Y-140462519D01* +X129196740Y-140459378D01* +X128974268Y-140277287D01* +X128729142Y-140127073D01* +X128712285Y-140119673D01* +X128469830Y-140013243D01* +X128465898Y-140011517D01* +X128440107Y-140004170D01* +X128228390Y-139943861D01* +X128189406Y-139932756D01* +X127976704Y-139902485D01* +X127909036Y-139892854D01* +X127909034Y-139892854D01* +X127904784Y-139892249D01* +X127900495Y-139892227D01* +X127900488Y-139892226D01* +X127621583Y-139890765D01* +X127621576Y-139890765D01* +X127617297Y-139890743D01* +X127613053Y-139891302D01* +X127613049Y-139891302D01* +X127487660Y-139907810D01* +X127332266Y-139928268D01* +X127328126Y-139929401D01* +X127328124Y-139929401D01* +X127288862Y-139940142D01* +X127054964Y-140004129D01* +X127051016Y-140005813D01* +X126794476Y-140115237D01* +X126794472Y-140115239D01* +X126790524Y-140116923D01* +X126702145Y-140169817D01* +X126547521Y-140262357D01* +X126547517Y-140262360D01* +X126543839Y-140264561D01* +X126319472Y-140444313D01* +X126121577Y-140652851D01* +X125953814Y-140886317D01* +X125819288Y-141140392D01* +X125720489Y-141410373D01* +X125659245Y-141691264D01* +X125654068Y-141757040D01* +X125637196Y-141971428D01* +X125637195Y-141971428D01* +X125637196Y-141971430D01* +X125636689Y-141977869D01* +X120265130Y-141977869D01* +X120105837Y-141801090D01* +X119819393Y-141483202D01* +X119816806Y-141480240D01* +X119038405Y-140560217D01* +X119035913Y-140557176D01* +X118588415Y-139993491D01* +X118286613Y-139613328D01* +X118284227Y-139610225D01* +X117978240Y-139199070D01* +X117564737Y-138643447D01* +X117562444Y-138640263D01* +X117270269Y-138220956D01* +X116873501Y-137651547D01* +X116871305Y-137648290D01* +X116567021Y-137181178D01* +X116213500Y-136638481D01* +X116211409Y-136635158D01* +X115585474Y-135605379D01* +X115583484Y-135601987D01* +X114989979Y-134553164D01* +X114988096Y-134549712D01* +X114771391Y-134137237D01* +X114427588Y-133482841D01* +X114425840Y-133479385D01* +X113898899Y-132395553D01* +X113897237Y-132391995D01* +X113404387Y-131292278D01* +X113402835Y-131288665D01* +X113097498Y-130546095D01* +X112944533Y-130174087D01* +X112943104Y-130170453D01* +X112939632Y-130161196D01* +X112519797Y-129042096D01* +X112518480Y-129038410D01* +X112507085Y-129004889D01* +X112157240Y-127975792D01* +X112130597Y-127897420D01* +X112129390Y-127893677D01* +X111777309Y-126741168D01* +X111776219Y-126737390D01* +X111591010Y-126055675D01* +X111460263Y-125574424D01* +X111459298Y-125570641D01* +X111457355Y-125562490D01* +X111179783Y-124398372D01* +X111178931Y-124394533D01* +X111146832Y-124238478D01* +X110936131Y-123214112D01* +X110935413Y-123210318D01* +X110776139Y-122291556D01* +X110729562Y-122022876D01* +X110728951Y-122018991D01* +X110631387Y-121328866D01* +X110560261Y-120825754D01* +X110559773Y-120821868D01* +X110556249Y-120789730D01* +X110506320Y-120334467D01* +X110428398Y-119623939D01* +X110428030Y-119620024D01* +X110334098Y-118418561D01* +X110333853Y-118414636D01* +X110304187Y-117781399D01* +X110277457Y-117210837D01* +X110277335Y-117206938D01* +X110277292Y-117204125D01* +X110264063Y-116356446D01* +X110259290Y-116050612D01* +X110261021Y-116027743D01* +X110262769Y-116017351D01* +X110262769Y-116017346D01* +X110263576Y-116012552D01* +X110263729Y-116000000D01* +X110259773Y-115972376D01* +X110258500Y-115954514D01* +X110258500Y-105410000D01* +X110846496Y-105410000D01* +X110847186Y-105416565D01* +X110863172Y-105568659D01* +X110866458Y-105599928D01* +X110925473Y-105781556D01* +X110928776Y-105787278D01* +X110928777Y-105787279D01* +X110945825Y-105816807D01* +X111020960Y-105946944D01* +X111094137Y-106028215D01* +X111124853Y-106092221D01* +X111126500Y-106112524D01* +X111126500Y-122160867D01* +X111125973Y-122172050D01* +X111124298Y-122179543D01* +X111124547Y-122187469D01* +X111124547Y-122187470D01* +X111126438Y-122247620D01* +X111126500Y-122251579D01* +X111126500Y-122279490D01* +X111126997Y-122283424D01* +X111126997Y-122283425D01* +X111127005Y-122283490D01* +X111127938Y-122295327D01* +X111129327Y-122339523D01* +X111134978Y-122358973D01* +X111138987Y-122378334D01* +X111141526Y-122398431D01* +X111144445Y-122405802D01* +X111144445Y-122405804D01* +X111157804Y-122439546D01* +X111161649Y-122450776D01* +X111171771Y-122485617D01* +X111173982Y-122493227D01* +X111178015Y-122500046D01* +X111178017Y-122500051D01* +X111184293Y-122510662D01* +X111192988Y-122528410D01* +X111200448Y-122547251D01* +X111205110Y-122553667D01* +X111205110Y-122553668D01* +X111226436Y-122583021D01* +X111232952Y-122592941D01* +X111249912Y-122621618D01* +X111255458Y-122630996D01* +X111269779Y-122645317D01* +X111282619Y-122660350D01* +X111294528Y-122676741D01* +X111324825Y-122701805D01* +X111328605Y-122704932D01* +X111337384Y-122712922D01* +X112505555Y-123881094D01* +X112539581Y-123943406D01* +X112542460Y-123970189D01* +X112542460Y-127247507D01* +X112541933Y-127258690D01* +X112540258Y-127266183D01* +X112540507Y-127274109D01* +X112540507Y-127274110D01* +X112542398Y-127334260D01* +X112542460Y-127338219D01* +X112542460Y-127366130D01* +X112542957Y-127370064D01* +X112542957Y-127370065D01* +X112542965Y-127370130D01* +X112543898Y-127381967D01* +X112545287Y-127426163D01* +X112550938Y-127445613D01* +X112554947Y-127464974D01* +X112555719Y-127471081D01* +X112557486Y-127485071D01* +X112560405Y-127492442D01* +X112560405Y-127492444D01* +X112573764Y-127526186D01* +X112577609Y-127537416D01* +X112585840Y-127565748D01* +X112589942Y-127579867D01* +X112593975Y-127586686D01* +X112593977Y-127586691D01* +X112600253Y-127597302D01* +X112608948Y-127615050D01* +X112616408Y-127633891D01* +X112621070Y-127640307D01* +X112621070Y-127640308D01* +X112642396Y-127669661D01* +X112648912Y-127679581D01* +X112665248Y-127707203D01* +X112671418Y-127717636D01* +X112685739Y-127731957D01* +X112698579Y-127746990D01* +X112710488Y-127763381D01* +X112716594Y-127768432D01* +X112744565Y-127791572D01* +X112753344Y-127799562D01* +X114140549Y-129186767D01* +X114148093Y-129195057D01* +X114152206Y-129201538D01* +X114157983Y-129206963D01* +X114201873Y-129248178D01* +X114204715Y-129250933D01* +X114224436Y-129270654D01* +X114227631Y-129273132D01* +X114236653Y-129280838D01* +X114268885Y-129311106D01* +X114275834Y-129314926D01* +X114286638Y-129320866D01* +X114303162Y-129331719D01* +X114319165Y-129344133D01* +X114359749Y-129361696D01* +X114370379Y-129366903D01* +X114409146Y-129388215D01* +X114416823Y-129390186D01* +X114416828Y-129390188D01* +X114428764Y-129393252D01* +X114447472Y-129399657D01* +X114466061Y-129407701D01* +X114473886Y-129408940D01* +X114473888Y-129408941D01* +X114509725Y-129414617D01* +X114521346Y-129417024D01* +X114556495Y-129426048D01* +X114564176Y-129428020D01* +X114584437Y-129428020D01* +X114604146Y-129429571D01* +X114624149Y-129432739D01* +X114632041Y-129431993D01* +X114637268Y-129431499D01* +X114668160Y-129428579D01* +X114680017Y-129428020D01* +X120224926Y-129428020D01* +X120293047Y-129448022D01* +X120314021Y-129464925D01* +X123956348Y-133107253D01* +X123963888Y-133115539D01* +X123968000Y-133122018D01* +X123973777Y-133127443D01* +X124017651Y-133168643D01* +X124020493Y-133171398D01* +X124040230Y-133191135D01* +X124043427Y-133193615D01* +X124052447Y-133201318D01* +X124084679Y-133231586D01* +X124091625Y-133235405D01* +X124091628Y-133235407D01* +X124102434Y-133241348D01* +X124118953Y-133252199D01* +X124134959Y-133264614D01* +X124142228Y-133267759D01* +X124142232Y-133267762D01* +X124175537Y-133282174D01* +X124186187Y-133287391D01* +X124224940Y-133308695D01* +X124232615Y-133310666D01* +X124232616Y-133310666D01* +X124244562Y-133313733D01* +X124263267Y-133320137D01* +X124281855Y-133328181D01* +X124289678Y-133329420D01* +X124289688Y-133329423D01* +X124325524Y-133335099D01* +X124337144Y-133337505D01* +X124368959Y-133345673D01* +X124379970Y-133348500D01* +X124400224Y-133348500D01* +X124419934Y-133350051D01* +X124439943Y-133353220D01* +X124447835Y-133352474D01* +X124466580Y-133350702D01* +X124483962Y-133349059D01* +X124495819Y-133348500D01* +X135176233Y-133348500D01* +X135187416Y-133349027D01* +X135194909Y-133350702D01* +X135202835Y-133350453D01* +X135202836Y-133350453D01* +X135262986Y-133348562D01* +X135266945Y-133348500D01* +X135294856Y-133348500D01* +X135298791Y-133348003D01* +X135298856Y-133347995D01* +X135310693Y-133347062D01* +X135342951Y-133346048D01* +X135346970Y-133345922D01* +X135354889Y-133345673D01* +X135374343Y-133340021D01* +X135393700Y-133336013D01* +X135405930Y-133334468D01* +X135405931Y-133334468D01* +X135413797Y-133333474D01* +X135421168Y-133330555D01* +X135421170Y-133330555D01* +X135454912Y-133317196D01* +X135466142Y-133313351D01* +X135500983Y-133303229D01* +X135500984Y-133303229D01* +X135508593Y-133301018D01* +X135515412Y-133296985D01* +X135515417Y-133296983D01* +X135526028Y-133290707D01* +X135543776Y-133282012D01* +X135562617Y-133274552D01* +X135598387Y-133248564D01* +X135608307Y-133242048D01* +X135639535Y-133223580D01* +X135639538Y-133223578D01* +X135646362Y-133219542D01* +X135660683Y-133205221D01* +X135675717Y-133192380D01* +X135681290Y-133188331D01* +X135692107Y-133180472D01* +X135720298Y-133146395D01* +X135728288Y-133137616D01* +X136282247Y-132583657D01* +X136290537Y-132576113D01* +X136297018Y-132572000D01* +X136343659Y-132522332D01* +X136346413Y-132519491D01* +X136366135Y-132499769D01* +X136368612Y-132496576D01* +X136376317Y-132487555D01* +X136401159Y-132461100D01* +X136406586Y-132455321D01* +X136415168Y-132439710D01* +X136416346Y-132437568D01* +X136427202Y-132421041D01* +X136434757Y-132411302D01* +X136434758Y-132411300D01* +X136439614Y-132405040D01* +X136457174Y-132364460D01* +X136462391Y-132353812D01* +X136479875Y-132322009D01* +X136479876Y-132322007D01* +X136483695Y-132315060D01* +X136488733Y-132295437D01* +X136495137Y-132276734D01* +X136500033Y-132265420D01* +X136500033Y-132265419D01* +X136503181Y-132258145D01* +X136504420Y-132250322D01* +X136504423Y-132250312D01* +X136510099Y-132214476D01* +X136512505Y-132202856D01* +X136521528Y-132167711D01* +X136521528Y-132167710D01* +X136523500Y-132160030D01* +X136523500Y-132139776D01* +X136525051Y-132120065D01* +X136526980Y-132107886D01* +X136528220Y-132100057D01* +X136524059Y-132056038D01* +X136523500Y-132044181D01* +X136523500Y-125797524D01* +X136543502Y-125729403D01* +X136555858Y-125713221D01* +X136629040Y-125631944D01* +X136705218Y-125500000D01* +X139936681Y-125500000D01* +X139955928Y-125744557D01* +X139957082Y-125749364D01* +X139957083Y-125749370D01* +X139969391Y-125800635D01* +X140013195Y-125983092D01* +X140015088Y-125987663D01* +X140015089Y-125987665D01* +X140040050Y-126047926D01* +X140107073Y-126209732D01* +X140144685Y-126271109D01* +X140232237Y-126413982D01* +X140235248Y-126418896D01* +X140238463Y-126422660D01* +X140238465Y-126422663D01* +X140323837Y-126522620D01* +X140394567Y-126605433D01* +X140398323Y-126608641D01* +X140562619Y-126748964D01* +X140581104Y-126764752D01* +X140585327Y-126767340D01* +X140585330Y-126767342D01* +X140625086Y-126791704D01* +X140790268Y-126892927D01* +X140893724Y-126935780D01* +X141012335Y-126984911D01* +X141012337Y-126984912D01* +X141016908Y-126986805D01* +X141099563Y-127006649D01* +X141250630Y-127042917D01* +X141250636Y-127042918D01* +X141255443Y-127044072D01* +X141500000Y-127063319D01* +X141744557Y-127044072D01* +X141749364Y-127042918D01* +X141749370Y-127042917D01* +X141900437Y-127006649D01* +X141983092Y-126986805D01* +X141987663Y-126984912D01* +X141987665Y-126984911D01* +X142106276Y-126935780D01* +X142209732Y-126892927D01* +X142374914Y-126791704D01* +X142414670Y-126767342D01* +X142414673Y-126767340D01* +X142418896Y-126764752D01* +X142437382Y-126748964D01* +X142601677Y-126608641D01* +X142605433Y-126605433D01* +X142676163Y-126522620D01* +X142761535Y-126422663D01* +X142761537Y-126422660D01* +X142764752Y-126418896D01* +X142767764Y-126413982D01* +X142855315Y-126271109D01* +X142892927Y-126209732D01* +X142959950Y-126047926D01* +X142984911Y-125987665D01* +X142984912Y-125987663D01* +X142986805Y-125983092D01* +X143030609Y-125800635D01* +X143042917Y-125749370D01* +X143042918Y-125749364D01* +X143044072Y-125744557D01* +X143063319Y-125500000D01* +X143044072Y-125255443D01* +X143040008Y-125238513D01* +X142987960Y-125021720D01* +X142986805Y-125016908D01* +X142962612Y-124958500D01* +X142930747Y-124881574D01* +X142892927Y-124790268D01* +X142764752Y-124581104D01* +X142736460Y-124547978D01* +X142608641Y-124398323D01* +X142605433Y-124394567D01* +X142574371Y-124368037D01* +X142422663Y-124238465D01* +X142422660Y-124238463D01* +X142418896Y-124235248D01* +X142414673Y-124232660D01* +X142414670Y-124232658D01* +X142314408Y-124171218D01* +X142209732Y-124107073D01* +X141994306Y-124017840D01* +X141987665Y-124015089D01* +X141987663Y-124015088D01* +X141983092Y-124013195D01* +X141872824Y-123986722D01* +X141749370Y-123957083D01* +X141749364Y-123957082D01* +X141744557Y-123955928D01* +X141500000Y-123936681D01* +X141255443Y-123955928D01* +X141250636Y-123957082D01* +X141250630Y-123957083D01* +X141127176Y-123986722D01* +X141016908Y-124013195D01* +X141012337Y-124015088D01* +X141012335Y-124015089D01* +X141005694Y-124017840D01* +X140790268Y-124107073D01* +X140685592Y-124171218D01* +X140585330Y-124232658D01* +X140585327Y-124232660D01* +X140581104Y-124235248D01* +X140577340Y-124238463D01* +X140577337Y-124238465D01* +X140425629Y-124368037D01* +X140394567Y-124394567D01* +X140391359Y-124398323D01* +X140263541Y-124547978D01* +X140235248Y-124581104D01* +X140107073Y-124790268D01* +X140069253Y-124881574D01* +X140037389Y-124958500D01* +X140013195Y-125016908D01* +X140012040Y-125021720D01* +X139959993Y-125238513D01* +X139955928Y-125255443D01* +X139936681Y-125500000D01* +X136705218Y-125500000D01* +X136706786Y-125497285D01* +X136721223Y-125472279D01* +X136721224Y-125472278D01* +X136724527Y-125466556D01* +X136783542Y-125284928D01* +X136786123Y-125260377D01* +X136802814Y-125101565D01* +X136803504Y-125095000D01* +X136790920Y-124975271D01* +X136784232Y-124911635D01* +X136784232Y-124911633D01* +X136783542Y-124905072D01* +X136724527Y-124723444D01* +X136629040Y-124558056D01* +X136613966Y-124541314D01* +X136505675Y-124421045D01* +X136505674Y-124421044D01* +X136501253Y-124416134D01* +X136369856Y-124320668D01* +X136352094Y-124307763D01* +X136352093Y-124307762D01* +X136346752Y-124303882D01* +X136340724Y-124301198D01* +X136340722Y-124301197D01* +X136178319Y-124228891D01* +X136178318Y-124228891D01* +X136172288Y-124226206D01* +X136077697Y-124206100D01* +X135991944Y-124187872D01* +X135991939Y-124187872D01* +X135985487Y-124186500D01* +X135794513Y-124186500D01* +X135788061Y-124187872D01* +X135788056Y-124187872D01* +X135702303Y-124206100D01* +X135607712Y-124226206D01* +X135601682Y-124228891D01* +X135601681Y-124228891D01* +X135439278Y-124301197D01* +X135439276Y-124301198D01* +X135433248Y-124303882D01* +X135427907Y-124307762D01* +X135427906Y-124307763D01* +X135410144Y-124320668D01* +X135278747Y-124416134D01* +X135274326Y-124421044D01* +X135274325Y-124421045D01* +X135166035Y-124541314D01* +X135150960Y-124558056D01* +X135055473Y-124723444D01* +X134996458Y-124905072D01* +X134995768Y-124911633D01* +X134995768Y-124911635D01* +X134989080Y-124975271D01* +X134976496Y-125095000D01* +X134977186Y-125101565D01* +X134993878Y-125260377D01* +X134996458Y-125284928D01* +X135055473Y-125466556D01* +X135058776Y-125472278D01* +X135058777Y-125472279D01* +X135073214Y-125497285D01* +X135150960Y-125631944D01* +X135224137Y-125713215D01* +X135254853Y-125777221D01* +X135256500Y-125797524D01* +X135256500Y-131765405D01* +X135236498Y-131833526D01* +X135219595Y-131854501D01* +X135029499Y-132044596D01* +X134967187Y-132078621D01* +X134940404Y-132081500D01* +X131479661Y-132081500D01* +X131411540Y-132061498D01* +X131365047Y-132007842D01* +X131354943Y-131937568D01* +X131384437Y-131872988D01* +X131390566Y-131866405D01* +X131480528Y-131776443D01* +X131486793Y-131770589D01* +X131524664Y-131737552D01* +X131524665Y-131737551D01* +X131530385Y-131732561D01* +X131567136Y-131680271D01* +X131571028Y-131675029D01* +X131610476Y-131624718D01* +X131613600Y-131617799D01* +X131614988Y-131615507D01* +X131623357Y-131600835D01* +X131624622Y-131598475D01* +X131628990Y-131592261D01* +X131652203Y-131532723D01* +X131654759Y-131526642D01* +X131677918Y-131475352D01* +X131681045Y-131468427D01* +X131682430Y-131460954D01* +X131683234Y-131458388D01* +X131687862Y-131442142D01* +X131688523Y-131439566D01* +X131691282Y-131432491D01* +X131691783Y-131428682D01* +X131727277Y-131369051D01* +X131773129Y-131341867D01* +X131923946Y-131291550D01* +X132074348Y-131198478D01* +X132199305Y-131073303D01* +X132256721Y-130980157D01* +X132288275Y-130928968D01* +X132288276Y-130928966D01* +X132292115Y-130922738D01* +X132342368Y-130771229D01* +X132345632Y-130761389D01* +X132345632Y-130761387D01* +X132347797Y-130754861D01* +X132358500Y-130650400D01* +X132358500Y-129349600D01* +X132357723Y-129342107D01* +X132348238Y-129250692D01* +X132348237Y-129250688D01* +X132347526Y-129243834D01* +X132345059Y-129236438D01* +X132293868Y-129083002D01* +X132291550Y-129076054D01* +X132198478Y-128925652D01* +X132073303Y-128800695D01* +X132058166Y-128791364D01* +X131976293Y-128740897D01* +X131922738Y-128707885D01* +X131915785Y-128705579D01* +X131914904Y-128705168D01* +X131861618Y-128658252D01* +X131842156Y-128589975D01* +X131862696Y-128522015D01* +X131880529Y-128501844D01* +X131879860Y-128501173D01* +X131944017Y-128437240D01* +X132038096Y-128343489D01* +X132065183Y-128305794D01* +X132165435Y-128166277D01* +X132168453Y-128162077D01* +X132183189Y-128132262D01* +X132265136Y-127966453D01* +X132265137Y-127966451D01* +X132267430Y-127961811D01* +X132326183Y-127768432D01* +X132330865Y-127753023D01* +X132330865Y-127753021D01* +X132332370Y-127748069D01* +X132361529Y-127526590D01* +X132362363Y-127492444D01* +X132363074Y-127463365D01* +X132363074Y-127463361D01* +X132363156Y-127460000D01* +X132344852Y-127237361D01* +X132290431Y-127020702D01* +X132201354Y-126815840D01* +X132157665Y-126748307D01* +X132082822Y-126632617D01* +X132082820Y-126632614D01* +X132080014Y-126628277D01* +X131929670Y-126463051D01* +X131925619Y-126459852D01* +X131925615Y-126459848D01* +X131758414Y-126327800D01* +X131758410Y-126327798D01* +X131754359Y-126324598D01* +X131713053Y-126301796D01* +X131663084Y-126251364D01* +X131648312Y-126181921D01* +X131673428Y-126115516D01* +X131700780Y-126088909D01* +X131767245Y-126041500D01* +X131879860Y-125961173D01* +X132038096Y-125803489D01* +X132056972Y-125777221D01* +X132165435Y-125626277D01* +X132168453Y-125622077D01* +X132175146Y-125608536D01* +X132265136Y-125426453D01* +X132265137Y-125426451D01* +X132267430Y-125421811D01* +X132323120Y-125238513D01* +X132330865Y-125213023D01* +X132330865Y-125213021D01* +X132332370Y-125208069D01* +X132361529Y-124986590D01* +X132361806Y-124975271D01* +X132363074Y-124923365D01* +X132363074Y-124923361D01* +X132363156Y-124920000D01* +X132344852Y-124697361D01* +X132290431Y-124480702D01* +X132201354Y-124275840D01* +X132139634Y-124180436D01* +X132082822Y-124092617D01* +X132082820Y-124092614D01* +X132080014Y-124088277D01* +X131929670Y-123923051D01* +X131925619Y-123919852D01* +X131925615Y-123919848D01* +X131758414Y-123787800D01* +X131758410Y-123787798D01* +X131754359Y-123784598D01* +X131745840Y-123779895D01* +X131696260Y-123752526D01* +X131558789Y-123676638D01* +X131553920Y-123674914D01* +X131553916Y-123674912D01* +X131353087Y-123603795D01* +X131353083Y-123603794D01* +X131348212Y-123602069D01* +X131343119Y-123601162D01* +X131343116Y-123601161D01* +X131133373Y-123563800D01* +X131133367Y-123563799D01* +X131128284Y-123562894D01* +X131054452Y-123561992D01* +X130910081Y-123560228D01* +X130910079Y-123560228D01* +X130904911Y-123560165D01* +X130684091Y-123593955D01* +X130471756Y-123663357D01* +X130437449Y-123681216D01* +X130282223Y-123762022D01* +X130273607Y-123766507D01* +X130269474Y-123769610D01* +X130269471Y-123769612D01* +X130099100Y-123897530D01* +X130094965Y-123900635D01* +X130091393Y-123904373D01* +X129962475Y-124039278D01* +X129940629Y-124062138D01* +X129937715Y-124066410D01* +X129937714Y-124066411D01* +X129912063Y-124104014D01* +X129842216Y-124206407D01* +X129832898Y-124220066D01* +X129777987Y-124265069D01* +X129707462Y-124273240D01* +X129643715Y-124241986D01* +X129623017Y-124217501D01* +X129593062Y-124171197D01* +X129582377Y-124161995D01* +X129572812Y-124166398D01* +X128549095Y-125190115D01* +X128486783Y-125224141D01* +X128415968Y-125219076D01* +X128370905Y-125190115D01* +X127349849Y-124169059D01* +X127338313Y-124162759D01* +X127326031Y-124172382D01* +X127278089Y-124242662D01* +X127273004Y-124251613D01* +X127183338Y-124444783D01* +X127179775Y-124454470D01* +X127122864Y-124659681D01* +X127120933Y-124669800D01* +X127098302Y-124881574D01* +X127098050Y-124891863D01* +X127110309Y-125104477D01* +X127111745Y-125114697D01* +X127158565Y-125322446D01* +X127161646Y-125332280D01* +X127200751Y-125428586D01* +X127207847Y-125499227D01* +X127175624Y-125562490D01* +X127114315Y-125598290D01* +X127084008Y-125601989D01* +X126585439Y-125601989D01* +X126517318Y-125581987D01* +X126496344Y-125565084D01* +X126425405Y-125494145D01* +X126391379Y-125431833D01* +X126388500Y-125405050D01* +X126388500Y-123796427D01* +X127701223Y-123796427D01* +X127707968Y-123808758D01* +X128447188Y-124547978D01* +X128461132Y-124555592D01* +X128462965Y-124555461D01* +X128469580Y-124551210D01* +X129213389Y-123807401D01* +X129220410Y-123794544D01* +X129213611Y-123785213D01* +X129209554Y-123782518D01* +X129023117Y-123679599D01* +X129013705Y-123675369D01* +X128812959Y-123604280D01* +X128802989Y-123601646D01* +X128593327Y-123564301D01* +X128583073Y-123563331D01* +X128370116Y-123560728D01* +X128359832Y-123561448D01* +X128149321Y-123593661D01* +X128139293Y-123596050D01* +X127936868Y-123662212D01* +X127927359Y-123666209D01* +X127738466Y-123764540D01* +X127729734Y-123770039D01* +X127709677Y-123785099D01* +X127701223Y-123796427D01* +X126388500Y-123796427D01* +X126388500Y-118971334D01* +X126408502Y-118903213D01* +X126462158Y-118856720D01* +X126488299Y-118848088D01* +X126647288Y-118814294D01* +X126655641Y-118810575D01* +X126815722Y-118739303D01* +X126815724Y-118739302D01* +X126821752Y-118736618D01* +X126829448Y-118731027D01* +X126925551Y-118661203D01* +X126976253Y-118624366D01* +X127018751Y-118577167D01* +X127079194Y-118539929D01* +X127150178Y-118541280D01* +X127201480Y-118572384D01* +X127215231Y-118586135D01* +X127218373Y-118588572D01* +X127218433Y-118588619D01* +X127227445Y-118596317D01* +X127248836Y-118616404D01* +X127259679Y-118626586D01* +X127266622Y-118630403D01* +X127277431Y-118636345D01* +X127293953Y-118647198D01* +X127309959Y-118659614D01* +X127317237Y-118662764D01* +X127317238Y-118662764D01* +X127350537Y-118677174D01* +X127361187Y-118682391D01* +X127399940Y-118703695D01* +X127407615Y-118705666D01* +X127407616Y-118705666D01* +X127419562Y-118708733D01* +X127438266Y-118715137D01* +X127443094Y-118717226D01* +X127456855Y-118723181D01* +X127464678Y-118724420D01* +X127464688Y-118724423D01* +X127500524Y-118730099D01* +X127512144Y-118732505D01* +X127535242Y-118738435D01* +X127554970Y-118743500D01* +X127575224Y-118743500D01* +X127594934Y-118745051D01* +X127614943Y-118748220D01* +X127622835Y-118747474D01* +X127649007Y-118745000D01* +X127658962Y-118744059D01* +X127670819Y-118743500D01* +X136056922Y-118743500D01* +X136108170Y-118754393D01* +X136236677Y-118811608D01* +X136236685Y-118811611D01* +X136242712Y-118814294D01* +X136336113Y-118834147D01* +X136423056Y-118852628D01* +X136423061Y-118852628D01* +X136429513Y-118854000D01* +X136620487Y-118854000D01* +X136626939Y-118852628D01* +X136626944Y-118852628D01* +X136713887Y-118834147D01* +X136807288Y-118814294D01* +X136815641Y-118810575D01* +X136975722Y-118739303D01* +X136975724Y-118739302D01* +X136981752Y-118736618D01* +X136989448Y-118731027D01* +X137085551Y-118661203D01* +X137136253Y-118624366D01* +X137147790Y-118611553D01* +X137259621Y-118487352D01* +X137259622Y-118487351D01* +X137264040Y-118482444D01* +X137348496Y-118336163D01* +X137356223Y-118322779D01* +X137356224Y-118322778D01* +X137359527Y-118317056D01* +X137418542Y-118135428D01* +X137419441Y-118126881D01* +X137431072Y-118016213D01* +X137458085Y-117950557D01* +X137516307Y-117909927D01* +X137538302Y-117904688D01* +X137689044Y-117882832D01* +X137700240Y-117880144D01* +X137882131Y-117818400D01* +X137892628Y-117813726D01* +X138003032Y-117751898D01* +X138012895Y-117741821D01* +X138009940Y-117734151D01* +X137075790Y-116800000D01* +X136503541Y-116227752D01* +X136489599Y-116220139D01* +X136459550Y-116222288D01* +X136390176Y-116207196D01* +X136349604Y-116171998D01* +X136265758Y-116059715D01* +X136265758Y-116059714D01* +X136262305Y-116055091D01* +X136162681Y-115962999D01* +X136116943Y-115920719D01* +X136116940Y-115920717D01* +X136112703Y-115916800D01* +X136060853Y-115884085D01* +X135945288Y-115811169D01* +X135945283Y-115811167D01* +X135940404Y-115808088D01* +X135819690Y-115759928D01* +X135756549Y-115734737D01* +X135751180Y-115732595D01* +X135652671Y-115713000D01* +X135651118Y-115712691D01* +X135588209Y-115679783D01* +X135553077Y-115618088D01* +X135556877Y-115547193D01* +X135586603Y-115500019D01* +X136371764Y-114714859D01* +X136380038Y-114707330D01* +X136386518Y-114703218D01* +X136433144Y-114653566D01* +X136435898Y-114650725D01* +X136455635Y-114630988D01* +X136458115Y-114627791D01* +X136465820Y-114618769D01* +X136496086Y-114586539D01* +X136499905Y-114579593D01* +X136499907Y-114579590D01* +X136505848Y-114568784D01* +X136516699Y-114552265D01* +X136517059Y-114551801D01* +X136529114Y-114536259D01* +X136532259Y-114528990D01* +X136532262Y-114528986D01* +X136546674Y-114495681D01* +X136551891Y-114485031D01* +X136573195Y-114446278D01* +X136578233Y-114426655D01* +X136584637Y-114407952D01* +X136589533Y-114396638D01* +X136589533Y-114396637D01* +X136592681Y-114389363D01* +X136593920Y-114381540D01* +X136593923Y-114381530D01* +X136599599Y-114345694D01* +X136602005Y-114334074D01* +X136611028Y-114298929D01* +X136611028Y-114298928D01* +X136613000Y-114291248D01* +X136613000Y-114270994D01* +X136614551Y-114251283D01* +X136615276Y-114246709D01* +X136617720Y-114231275D01* +X136613559Y-114187256D01* +X136613000Y-114175399D01* +X136613000Y-113804279D01* +X136633002Y-113736158D01* +X136645358Y-113719976D01* +X136718540Y-113638699D01* +X136800787Y-113496243D01* +X136810723Y-113479034D01* +X136810724Y-113479033D01* +X136814027Y-113473311D01* +X136873042Y-113291683D01* +X136875266Y-113270528D01* +X136892314Y-113108320D01* +X136893004Y-113101755D01* +X136889968Y-113072865D01* +X136883055Y-113007095D01* +X140372001Y-113007095D01* +X140372338Y-113013614D01* +X140382257Y-113109206D01* +X140385149Y-113122600D01* +X140436588Y-113276784D01* +X140442761Y-113289962D01* +X140528063Y-113427807D01* +X140537099Y-113439208D01* +X140651829Y-113553739D01* +X140663240Y-113562751D01* +X140801243Y-113647816D01* +X140814424Y-113653963D01* +X140968710Y-113705138D01* +X140982086Y-113708005D01* +X141076438Y-113717672D01* +X141082854Y-113718000D01* +X141332885Y-113718000D01* +X141348124Y-113713525D01* +X141349329Y-113712135D01* +X141351000Y-113704452D01* +X141351000Y-113699884D01* +X141859000Y-113699884D01* +X141863475Y-113715123D01* +X141864865Y-113716328D01* +X141872548Y-113717999D01* +X142127095Y-113717999D01* +X142133614Y-113717662D01* +X142229206Y-113707743D01* +X142242600Y-113704851D01* +X142396784Y-113653412D01* +X142409962Y-113647239D01* +X142547807Y-113561937D01* +X142559208Y-113552901D01* +X142673739Y-113438171D01* +X142682751Y-113426760D01* +X142767816Y-113288757D01* +X142773963Y-113275576D01* +X142825138Y-113121290D01* +X142828005Y-113107914D01* +X142837672Y-113013562D01* +X142838000Y-113007146D01* +X142838000Y-112982115D01* +X142833525Y-112966876D01* +X142832135Y-112965671D01* +X142824452Y-112964000D01* +X141877115Y-112964000D01* +X141861876Y-112968475D01* +X141860671Y-112969865D01* +X141859000Y-112977548D01* +X141859000Y-113699884D01* +X141351000Y-113699884D01* +X141351000Y-112982115D01* +X141346525Y-112966876D01* +X141345135Y-112965671D01* +X141337452Y-112964000D01* +X140390116Y-112964000D01* +X140374877Y-112968475D01* +X140373672Y-112969865D01* +X140372001Y-112977548D01* +X140372001Y-113007095D01* +X136883055Y-113007095D01* +X136873732Y-112918390D01* +X136873732Y-112918388D01* +X136873042Y-112911827D01* +X136814027Y-112730199D01* +X136808828Y-112721193D01* +X136746604Y-112613419D01* +X136718540Y-112564811D01* +X136706458Y-112551392D01* +X136595175Y-112427800D01* +X136595174Y-112427799D01* +X136590753Y-112422889D01* +X136436252Y-112310637D01* +X136430224Y-112307953D01* +X136430222Y-112307952D01* +X136272262Y-112237624D01* +X136218166Y-112191644D01* +X136197517Y-112123717D01* +X136216869Y-112055408D01* +X136270080Y-112008407D01* +X136292844Y-112000924D01* +X136293637Y-112000860D01* +X136300601Y-111998604D01* +X136306560Y-111997413D01* +X136312415Y-111996029D01* +X136319681Y-111995182D01* +X136388327Y-111970265D01* +X136392455Y-111968848D01* +X136454936Y-111948607D01* +X136454938Y-111948606D01* +X136461899Y-111946351D01* +X136468154Y-111942555D01* +X136473628Y-111940049D01* +X136479058Y-111937330D01* +X136485937Y-111934833D01* +X136492833Y-111930312D01* +X136546976Y-111894814D01* +X136550680Y-111892477D01* +X136613107Y-111854595D01* +X136621484Y-111847197D01* +X136621508Y-111847224D01* +X136624500Y-111844571D01* +X136627733Y-111841868D01* +X136633852Y-111837856D01* +X136687128Y-111781617D01* +X136689506Y-111779175D01* +X136929276Y-111539405D01* +X136991588Y-111505379D01* +X137018371Y-111502500D01* +X140447492Y-111502500D01* +X140515613Y-111522502D01* +X140536508Y-111539326D01* +X140656697Y-111659305D01* +X140661235Y-111662102D01* +X140701824Y-111719353D01* +X140705054Y-111790276D01* +X140669428Y-111851687D01* +X140660932Y-111859062D01* +X140650793Y-111867098D01* +X140536261Y-111981829D01* +X140527249Y-111993240D01* +X140442184Y-112131243D01* +X140436037Y-112144424D01* +X140384862Y-112298710D01* +X140381995Y-112312086D01* +X140372328Y-112406438D01* +X140372000Y-112412855D01* +X140372000Y-112437885D01* +X140376475Y-112453124D01* +X140377865Y-112454329D01* +X140385548Y-112456000D01* +X142819884Y-112456000D01* +X142835123Y-112451525D01* +X142836328Y-112450135D01* +X142837999Y-112442452D01* +X142837999Y-112412905D01* +X142837662Y-112406386D01* +X142827743Y-112310794D01* +X142824851Y-112297400D01* +X142773412Y-112143216D01* +X142767239Y-112130038D01* +X142681937Y-111992193D01* +X142672901Y-111980792D01* +X142558172Y-111866262D01* +X142549238Y-111859206D01* +X142508177Y-111801288D01* +X142504947Y-111730365D01* +X142540574Y-111668954D01* +X142548407Y-111662154D01* +X142554348Y-111658478D01* +X142580281Y-111632500D01* +X142607252Y-111605482D01* +X142669535Y-111571403D01* +X142696425Y-111568500D01* +X143971629Y-111568500D01* +X144039750Y-111588502D01* +X144060724Y-111605405D01* +X144366825Y-111911506D01* +X144400851Y-111973818D01* +X144395786Y-112044633D01* +X144353239Y-112101469D01* +X144286719Y-112126280D01* +X144251532Y-112123847D01* +X144246951Y-112122873D01* +X144246942Y-112122872D01* +X144240487Y-112121500D01* +X144049513Y-112121500D01* +X144043061Y-112122872D01* +X144043056Y-112122872D01* +X143960699Y-112140378D01* +X143862712Y-112161206D01* +X143856682Y-112163891D01* +X143856681Y-112163891D01* +X143694278Y-112236197D01* +X143694276Y-112236198D01* +X143688248Y-112238882D01* +X143682907Y-112242762D01* +X143682906Y-112242763D01* +X143655047Y-112263004D01* +X143533747Y-112351134D01* +X143529326Y-112356044D01* +X143529325Y-112356045D01* +X143420203Y-112477238D01* +X143405960Y-112493056D01* +X143310473Y-112658444D01* +X143251458Y-112840072D01* +X143250768Y-112846633D01* +X143250768Y-112846635D01* +X143238058Y-112967568D01* +X143231496Y-113030000D01* +X143232186Y-113036565D01* +X143249449Y-113200810D01* +X143251458Y-113219928D01* +X143310473Y-113401556D01* +X143313776Y-113407278D01* +X143313777Y-113407279D01* +X143328771Y-113433249D01* +X143405960Y-113566944D01* +X143410375Y-113571847D01* +X143410379Y-113571852D01* +X143525819Y-113700061D01* +X143533747Y-113708866D01* +X143688248Y-113821118D01* +X143694276Y-113823802D01* +X143694278Y-113823803D01* +X143840988Y-113889122D01* +X143862712Y-113898794D01* +X143956112Y-113918647D01* +X144043056Y-113937128D01* +X144043061Y-113937128D01* +X144049513Y-113938500D01* +X144240487Y-113938500D01* +X144246939Y-113937128D01* +X144246944Y-113937128D01* +X144333887Y-113918647D01* +X144427288Y-113898794D01* +X144449012Y-113889122D01* +X144595722Y-113823803D01* +X144595724Y-113823802D01* +X144601752Y-113821118D01* +X144756253Y-113708866D01* +X144764341Y-113699884D01* +X144866864Y-113586020D01* +X144927310Y-113548780D01* +X144998294Y-113550132D01* +X145057278Y-113589645D01* +X145085536Y-113654776D01* +X145086500Y-113670330D01* +X145086500Y-113893244D01* +X145087038Y-113897330D01* +X145087038Y-113897331D01* +X145101519Y-114007324D01* +X145099974Y-114007527D01* +X145099974Y-114052473D01* +X145101519Y-114052676D01* +X145087270Y-114160911D01* +X145086500Y-114166756D01* +X145086500Y-114393244D01* +X145087038Y-114397330D01* +X145087038Y-114397331D01* +X145101519Y-114507324D01* +X145099974Y-114507527D01* +X145099974Y-114552473D01* +X145101519Y-114552676D01* +X145087963Y-114655647D01* +X145086500Y-114666756D01* +X145086500Y-114893244D01* +X145087038Y-114897330D01* +X145087038Y-114897331D01* +X145101088Y-115004054D01* +X145090148Y-115074203D01* +X145043020Y-115127301D01* +X144976166Y-115146500D01* +X142129595Y-115146500D01* +X142061474Y-115126498D01* +X142040500Y-115109595D01* +X141473652Y-114542747D01* +X141466112Y-114534461D01* +X141462000Y-114527982D01* +X141440218Y-114507527D01* +X141412349Y-114481357D01* +X141409507Y-114478602D01* +X141389770Y-114458865D01* +X141386573Y-114456385D01* +X141377551Y-114448680D01* +X141345321Y-114418414D01* +X141338375Y-114414595D01* +X141338372Y-114414593D01* +X141327566Y-114408652D01* +X141311047Y-114397801D01* +X141309548Y-114396638D01* +X141295041Y-114385386D01* +X141287772Y-114382241D01* +X141287768Y-114382238D01* +X141254463Y-114367826D01* +X141243813Y-114362609D01* +X141205060Y-114341305D01* +X141185437Y-114336267D01* +X141166734Y-114329863D01* +X141155420Y-114324967D01* +X141155419Y-114324967D01* +X141148145Y-114321819D01* +X141140322Y-114320580D01* +X141140312Y-114320577D01* +X141104476Y-114314901D01* +X141092856Y-114312495D01* +X141057711Y-114303472D01* +X141057710Y-114303472D01* +X141050030Y-114301500D01* +X141029776Y-114301500D01* +X141010065Y-114299949D01* +X141009693Y-114299890D01* +X140990057Y-114296780D01* +X140982165Y-114297526D01* +X140946039Y-114300941D01* +X140934181Y-114301500D01* +X139048700Y-114301500D01* +X138980579Y-114281498D01* +X138961353Y-114265157D01* +X138961080Y-114265460D01* +X138956168Y-114261037D01* +X138951753Y-114256134D01* +X138895801Y-114215482D01* +X138802594Y-114147763D01* +X138802593Y-114147762D01* +X138797252Y-114143882D01* +X138791224Y-114141198D01* +X138791222Y-114141197D01* +X138628819Y-114068891D01* +X138628818Y-114068891D01* +X138622788Y-114066206D01* +X138521997Y-114044782D01* +X138442444Y-114027872D01* +X138442439Y-114027872D01* +X138435987Y-114026500D01* +X138245013Y-114026500D01* +X138238561Y-114027872D01* +X138238556Y-114027872D01* +X138159003Y-114044782D01* +X138058212Y-114066206D01* +X138052182Y-114068891D01* +X138052181Y-114068891D01* +X137889778Y-114141197D01* +X137889776Y-114141198D01* +X137883748Y-114143882D01* +X137878407Y-114147762D01* +X137878406Y-114147763D01* +X137860310Y-114160911D01* +X137729247Y-114256134D01* +X137724826Y-114261044D01* +X137724825Y-114261045D01* +X137615703Y-114382238D01* +X137601460Y-114398056D01* +X137557283Y-114474572D01* +X137511426Y-114554000D01* +X137505973Y-114563444D01* +X137446958Y-114745072D01* +X137446268Y-114751633D01* +X137446268Y-114751635D01* +X137428329Y-114922316D01* +X137426996Y-114935000D01* +X137427686Y-114941565D01* +X137444860Y-115104962D01* +X137446958Y-115124928D01* +X137505973Y-115306556D01* +X137543615Y-115371753D01* +X137560352Y-115440745D01* +X137543614Y-115497751D01* +X137505973Y-115562947D01* +X137503933Y-115569227D01* +X137503932Y-115569228D01* +X137492654Y-115603938D01* +X137452580Y-115662543D01* +X137387183Y-115690180D01* +X137371173Y-115690990D01* +X137353478Y-115690759D01* +X137341997Y-115691662D01* +X137152697Y-115724190D01* +X137141577Y-115727170D01* +X136961365Y-115793653D01* +X136950991Y-115798601D01* +X136867385Y-115848342D01* +X136857788Y-115858675D01* +X136861275Y-115867064D01* +X137435000Y-116440790D01* +X138365236Y-117371025D01* +X138377615Y-117377784D01* +X138384195Y-117372858D01* +X138448726Y-117257628D01* +X138453400Y-117247131D01* +X138515144Y-117065240D01* +X138517832Y-117054044D01* +X138539664Y-116903468D01* +X138569234Y-116838922D01* +X138622845Y-116803424D01* +X138622788Y-116803297D01* +X138623546Y-116802960D01* +X138623548Y-116802959D01* +X138710020Y-116764459D01* +X138791222Y-116728306D01* +X138791224Y-116728305D01* +X138797252Y-116725621D01* +X138951753Y-116613369D01* +X138956168Y-116608466D01* +X138961080Y-116604043D01* +X138962205Y-116605292D01* +X139015514Y-116572452D01* +X139048700Y-116568003D01* +X140210500Y-116568003D01* +X140278621Y-116588005D01* +X140325114Y-116641661D01* +X140336500Y-116694003D01* +X140336500Y-120018483D01* +X140335973Y-120029666D01* +X140334298Y-120037159D01* +X140334547Y-120045085D01* +X140334547Y-120045086D01* +X140336438Y-120105236D01* +X140336500Y-120109195D01* +X140336500Y-120137106D01* +X140336997Y-120141040D01* +X140336997Y-120141041D01* +X140337005Y-120141106D01* +X140337938Y-120152943D01* +X140339327Y-120197139D01* +X140344978Y-120216589D01* +X140348987Y-120235950D01* +X140351526Y-120256047D01* +X140354444Y-120263417D01* +X140356416Y-120271098D01* +X140354073Y-120271700D01* +X140359449Y-120330410D01* +X140326672Y-120393388D01* +X140265050Y-120428647D01* +X140194147Y-120424993D01* +X140167976Y-120411278D01* +X140167811Y-120411564D01* +X140162093Y-120408263D01* +X140156752Y-120404382D01* +X140150724Y-120401698D01* +X140150722Y-120401697D01* +X139988319Y-120329391D01* +X139988318Y-120329391D01* +X139982288Y-120326706D01* +X139881426Y-120305267D01* +X139801944Y-120288372D01* +X139801939Y-120288372D01* +X139795487Y-120287000D01* +X139604513Y-120287000D01* +X139598061Y-120288372D01* +X139598056Y-120288372D01* +X139518574Y-120305267D01* +X139417712Y-120326706D01* +X139411682Y-120329391D01* +X139411681Y-120329391D01* +X139249278Y-120401697D01* +X139249276Y-120401698D01* +X139243248Y-120404382D01* +X139237907Y-120408262D01* +X139237906Y-120408263D01* +X139209850Y-120428647D01* +X139088747Y-120516634D01* +X139084326Y-120521544D01* +X139084325Y-120521545D01* +X139000543Y-120614595D01* +X138960960Y-120658556D01* +X138923346Y-120723706D01* +X138878006Y-120802237D01* +X138865473Y-120823944D01* +X138806458Y-121005572D01* +X138805768Y-121012133D01* +X138805768Y-121012135D01* +X138789912Y-121162998D01* +X138786496Y-121195500D01* +X138787186Y-121202065D01* +X138805528Y-121376575D01* +X138806458Y-121385428D01* +X138865473Y-121567056D01* +X138868776Y-121572778D01* +X138868777Y-121572779D01* +X138886613Y-121603672D01* +X138960960Y-121732444D01* +X138965378Y-121737351D01* +X138965379Y-121737352D01* +X139033031Y-121812487D01* +X139063749Y-121876494D01* +X139065333Y-121892838D01* +X139066438Y-121927986D01* +X139066500Y-121931945D01* +X139066500Y-121959856D01* +X139066997Y-121963790D01* +X139066997Y-121963791D01* +X139067005Y-121963856D01* +X139067938Y-121975693D01* +X139069327Y-122019889D01* +X139073599Y-122034593D01* +X139074978Y-122039339D01* +X139078987Y-122058700D01* +X139081526Y-122078797D01* +X139084445Y-122086168D01* +X139084445Y-122086170D01* +X139097804Y-122119912D01* +X139101649Y-122131142D01* +X139109017Y-122156502D01* +X139113982Y-122173593D01* +X139118015Y-122180412D01* +X139118017Y-122180417D01* +X139124293Y-122191028D01* +X139132988Y-122208776D01* +X139140448Y-122227617D01* +X139145110Y-122234033D01* +X139145110Y-122234034D01* +X139166436Y-122263387D01* +X139172952Y-122273307D01* +X139189330Y-122301000D01* +X139195458Y-122311362D01* +X139209779Y-122325683D01* +X139222619Y-122340716D01* +X139234528Y-122357107D01* +X139260187Y-122378334D01* +X139268605Y-122385298D01* +X139277384Y-122393288D01* +X139831343Y-122947247D01* +X139838887Y-122955537D01* +X139843000Y-122962018D01* +X139848777Y-122967443D01* +X139892667Y-123008658D01* +X139895509Y-123011413D01* +X139915231Y-123031135D01* +X139918355Y-123033558D01* +X139918359Y-123033562D01* +X139918424Y-123033612D01* +X139927445Y-123041317D01* +X139959679Y-123071586D01* +X139966627Y-123075405D01* +X139966629Y-123075407D01* +X139977432Y-123081346D01* +X139993959Y-123092202D01* +X140003698Y-123099757D01* +X140003700Y-123099758D01* +X140009960Y-123104614D01* +X140050540Y-123122174D01* +X140061188Y-123127391D01* +X140088006Y-123142134D01* +X140099940Y-123148695D01* +X140107616Y-123150666D01* +X140107619Y-123150667D01* +X140119562Y-123153733D01* +X140138266Y-123160137D01* +X140141414Y-123161499D01* +X140156855Y-123168181D01* +X140164678Y-123169420D01* +X140164688Y-123169423D01* +X140200524Y-123175099D01* +X140212144Y-123177505D01* +X140235242Y-123183435D01* +X140254970Y-123188500D01* +X140275224Y-123188500D01* +X140294934Y-123190051D01* +X140314943Y-123193220D01* +X140322835Y-123192474D01* +X140358961Y-123189059D01* +X140370819Y-123188500D01* +X142453622Y-123188500D01* +X142521743Y-123208502D01* +X142542717Y-123225405D01* +X143474595Y-124157283D01* +X143508621Y-124219595D01* +X143511500Y-124246378D01* +X143511500Y-128826233D01* +X143510973Y-128837416D01* +X143509298Y-128844909D01* +X143509547Y-128852835D01* +X143509547Y-128852836D01* +X143511438Y-128912986D01* +X143511500Y-128916945D01* +X143511500Y-128944856D01* +X143511997Y-128948790D01* +X143511997Y-128948791D01* +X143512005Y-128948856D01* +X143512938Y-128960693D01* +X143514327Y-129004889D01* +X143519978Y-129024339D01* +X143523987Y-129043700D01* +X143526526Y-129063797D01* +X143529445Y-129071168D01* +X143529445Y-129071170D01* +X143542804Y-129104912D01* +X143546649Y-129116142D01* +X143555443Y-129146411D01* +X143558982Y-129158593D01* +X143563015Y-129165412D01* +X143563017Y-129165417D01* +X143569293Y-129176028D01* +X143577988Y-129193776D01* +X143585448Y-129212617D01* +X143590110Y-129219033D01* +X143590110Y-129219034D01* +X143611436Y-129248387D01* +X143617952Y-129258307D01* +X143634330Y-129286000D01* +X143640458Y-129296362D01* +X143654779Y-129310683D01* +X143667619Y-129325716D01* +X143679528Y-129342107D01* +X143706053Y-129364050D01* +X143713593Y-129370288D01* +X143722374Y-129378278D01* +X144365853Y-130021758D01* +X144373387Y-130030037D01* +X144377500Y-130036518D01* +X144427151Y-130083143D01* +X144429993Y-130085898D01* +X144449730Y-130105635D01* +X144452927Y-130108115D01* +X144461947Y-130115818D01* +X144494179Y-130146086D01* +X144501125Y-130149905D01* +X144501128Y-130149907D01* +X144511934Y-130155848D01* +X144528453Y-130166699D01* +X144544459Y-130179114D01* +X144551728Y-130182259D01* +X144551732Y-130182262D01* +X144585037Y-130196674D01* +X144595687Y-130201891D01* +X144634440Y-130223195D01* +X144642115Y-130225166D01* +X144642116Y-130225166D01* +X144654062Y-130228233D01* +X144672767Y-130234637D01* +X144691355Y-130242681D01* +X144699178Y-130243920D01* +X144699188Y-130243923D01* +X144735024Y-130249599D01* +X144746644Y-130252005D01* +X144781789Y-130261028D01* +X144789470Y-130263000D01* +X144809724Y-130263000D01* +X144829434Y-130264551D01* +X144849443Y-130267720D01* +X144857335Y-130266974D01* +X144893461Y-130263559D01* +X144905319Y-130263000D01* +X154231800Y-130263000D01* +X154299921Y-130283002D01* +X154319147Y-130299343D01* +X154319420Y-130299040D01* +X154324332Y-130303463D01* +X154328747Y-130308366D01* +X154350329Y-130324046D01* +X154448945Y-130395695D01* +X154483248Y-130420618D01* +X154489276Y-130423302D01* +X154489278Y-130423303D01* +X154624648Y-130483573D01* +X154657712Y-130498294D01* +X154738561Y-130515479D01* +X154838056Y-130536628D01* +X154838061Y-130536628D01* +X154844513Y-130538000D01* +X155035487Y-130538000D01* +X155041939Y-130536628D01* +X155041944Y-130536628D01* +X155141439Y-130515479D01* +X155222288Y-130498294D01* +X155255352Y-130483573D01* +X155390722Y-130423303D01* +X155390724Y-130423302D01* +X155396752Y-130420618D01* +X155431056Y-130395695D01* +X155482050Y-130358645D01* +X155551253Y-130308366D01* +X155555675Y-130303455D01* +X155674621Y-130171352D01* +X155674622Y-130171351D01* +X155679040Y-130166444D01* +X155762575Y-130021758D01* +X155771223Y-130006779D01* +X155771224Y-130006778D01* +X155774527Y-130001056D01* +X155833542Y-129819428D01* +X155834311Y-129812115D01* +X155851210Y-129651329D01* +X155878223Y-129585673D01* +X155936445Y-129545043D01* +X155976520Y-129538500D01* +X160576233Y-129538500D01* +X160587416Y-129539027D01* +X160594909Y-129540702D01* +X160602835Y-129540453D01* +X160602836Y-129540453D01* +X160662986Y-129538562D01* +X160666945Y-129538500D01* +X160694856Y-129538500D01* +X160698791Y-129538003D01* +X160698856Y-129537995D01* +X160710693Y-129537062D01* +X160742951Y-129536048D01* +X160746970Y-129535922D01* +X160754889Y-129535673D01* +X160774343Y-129530021D01* +X160793700Y-129526013D01* +X160805930Y-129524468D01* +X160805931Y-129524468D01* +X160813797Y-129523474D01* +X160821168Y-129520555D01* +X160821170Y-129520555D01* +X160854912Y-129507196D01* +X160866142Y-129503351D01* +X160900983Y-129493229D01* +X160900984Y-129493229D01* +X160908593Y-129491018D01* +X160915412Y-129486985D01* +X160915417Y-129486983D01* +X160926028Y-129480707D01* +X160943776Y-129472012D01* +X160962617Y-129464552D01* +X160998387Y-129438564D01* +X161008307Y-129432048D01* +X161039535Y-129413580D01* +X161039538Y-129413578D01* +X161046362Y-129409542D01* +X161060683Y-129395221D01* +X161075717Y-129382380D01* +X161085694Y-129375131D01* +X161092107Y-129370472D01* +X161120298Y-129336395D01* +X161128288Y-129327616D01* +X162785500Y-127670405D01* +X162847812Y-127636379D01* +X162874595Y-127633500D01* +X167816578Y-127633500D01* +X167884699Y-127653502D01* +X167931192Y-127707158D01* +X167941296Y-127777432D01* +X167911802Y-127842012D01* +X167898454Y-127854788D01* +X167895652Y-127856522D01* +X167770695Y-127981697D01* +X167766855Y-127987927D01* +X167766854Y-127987928D01* +X167685532Y-128119857D01* +X167677885Y-128132262D01* +X167666365Y-128166994D01* +X167628238Y-128281945D01* +X167622203Y-128300139D01* +X167621503Y-128306975D01* +X167621502Y-128306978D01* +X167619584Y-128325699D01* +X167611500Y-128404600D01* +X167611500Y-129405400D01* +X167611837Y-129408646D01* +X167611837Y-129408650D01* +X167621618Y-129502914D01* +X167622474Y-129511166D01* +X167624655Y-129517702D01* +X167624655Y-129517704D01* +X167647659Y-129586654D01* +X167678450Y-129678946D01* +X167682306Y-129685177D01* +X167730554Y-129763145D01* +X167749392Y-129831597D01* +X167743243Y-129868384D01* +X167738958Y-129881572D01* +X167738268Y-129888133D01* +X167738268Y-129888135D01* +X167724224Y-130021758D01* +X167718996Y-130071500D01* +X167719686Y-130078065D01* +X167738037Y-130252662D01* +X167738958Y-130261428D01* +X167787607Y-130411153D01* +X167789635Y-130482119D01* +X167770078Y-130521316D01* +X167770695Y-130521697D01* +X167689390Y-130653598D01* +X167677885Y-130672262D01* +X167661080Y-130722928D01* +X167632535Y-130808990D01* +X167622203Y-130840139D01* +X167611500Y-130944600D01* +X167611500Y-131945400D01* +X167611837Y-131948646D01* +X167611837Y-131948650D01* +X167618487Y-132012738D01* +X167622474Y-132051166D01* +X167624655Y-132057702D01* +X167624655Y-132057704D01* +X167648728Y-132129858D01* +X167678450Y-132218946D01* +X167771522Y-132369348D01* +X167776704Y-132374521D01* +X167828600Y-132426327D01* +X167862679Y-132488610D01* +X167857676Y-132559430D01* +X167815179Y-132616303D01* +X167748680Y-132641171D01* +X167739582Y-132641500D01* +X167616405Y-132641500D01* +X167548284Y-132621498D01* +X167542344Y-132617436D01* +X167467094Y-132562763D01* +X167467093Y-132562762D01* +X167461752Y-132558882D01* +X167455724Y-132556198D01* +X167455722Y-132556197D01* +X167293319Y-132483891D01* +X167293318Y-132483891D01* +X167287288Y-132481206D01* +X167192697Y-132461100D01* +X167106944Y-132442872D01* +X167106939Y-132442872D01* +X167100487Y-132441500D01* +X166909513Y-132441500D01* +X166903061Y-132442872D01* +X166903056Y-132442872D01* +X166817303Y-132461100D01* +X166722712Y-132481206D01* +X166716682Y-132483891D01* +X166716681Y-132483891D01* +X166554278Y-132556197D01* +X166554276Y-132556198D01* +X166548248Y-132558882D01* +X166542907Y-132562762D01* +X166542906Y-132562763D01* +X166528874Y-132572958D01* +X166393747Y-132671134D01* +X166389326Y-132676044D01* +X166389325Y-132676045D01* +X166284352Y-132792630D01* +X166265960Y-132813056D01* +X166170473Y-132978444D01* +X166111458Y-133160072D01* +X166110768Y-133166633D01* +X166110768Y-133166635D01* +X166104010Y-133230938D01* +X166091496Y-133350000D01* +X166092186Y-133356565D01* +X166101727Y-133447338D01* +X166111458Y-133539928D01* +X166170473Y-133721556D01* +X166265960Y-133886944D01* +X166270378Y-133891851D01* +X166270379Y-133891852D01* +X166373367Y-134006232D01* +X166393747Y-134028866D01* +X166548248Y-134141118D01* +X166554276Y-134143802D01* +X166554278Y-134143803D01* +X166716681Y-134216109D01* +X166722712Y-134218794D01* +X166816112Y-134238647D01* +X166903056Y-134257128D01* +X166903061Y-134257128D01* +X166909513Y-134258500D01* +X167100487Y-134258500D01* +X167106939Y-134257128D01* +X167106944Y-134257128D01* +X167193888Y-134238647D01* +X167287288Y-134218794D01* +X167293319Y-134216109D01* +X167455722Y-134143803D01* +X167455724Y-134143802D01* +X167461752Y-134141118D01* +X167527733Y-134093180D01* +X167542344Y-134082564D01* +X167609211Y-134058706D01* +X167616405Y-134058500D01* +X170151088Y-134058500D01* +X170159658Y-134058792D01* +X170209776Y-134062209D01* +X170209780Y-134062209D01* +X170217352Y-134062725D01* +X170224829Y-134061420D01* +X170224830Y-134061420D01* +X170251308Y-134056799D01* +X170280303Y-134051738D01* +X170286821Y-134050777D01* +X170350242Y-134043102D01* +X170357343Y-134040419D01* +X170359952Y-134039778D01* +X170376262Y-134035315D01* +X170378798Y-134034550D01* +X170386284Y-134033243D01* +X170444800Y-134007556D01* +X170450904Y-134005065D01* +X170503548Y-133985173D01* +X170503549Y-133985172D01* +X170510656Y-133982487D01* +X170516919Y-133978183D01* +X170519285Y-133976946D01* +X170534097Y-133968701D01* +X170536351Y-133967368D01* +X170543305Y-133964315D01* +X170594002Y-133925413D01* +X170599332Y-133921541D01* +X170645720Y-133889661D01* +X170645725Y-133889656D01* +X170651981Y-133885357D01* +X170693435Y-133838830D01* +X170698416Y-133833554D01* +X170938035Y-133593936D01* +X170944300Y-133588083D01* +X170982164Y-133555052D01* +X170982165Y-133555051D01* +X170987885Y-133550061D01* +X171024636Y-133497771D01* +X171028528Y-133492529D01* +X171067976Y-133442218D01* +X171071100Y-133435299D01* +X171072488Y-133433007D01* +X171080857Y-133418335D01* +X171082122Y-133415975D01* +X171086490Y-133409761D01* +X171109703Y-133350223D01* +X171112259Y-133344142D01* +X171112579Y-133343435D01* +X171138545Y-133285927D01* +X171139930Y-133278454D01* +X171140734Y-133275888D01* +X171145355Y-133259665D01* +X171146020Y-133257073D01* +X171148782Y-133249991D01* +X171152791Y-133219542D01* +X171157122Y-133186639D01* +X171158154Y-133180123D01* +X171168411Y-133124781D01* +X171169795Y-133117314D01* +X171166209Y-133055120D01* +X171166000Y-133047867D01* +X171166000Y-132574002D01* +X171186002Y-132505881D01* +X171202827Y-132484984D01* +X171206599Y-132481206D01* +X171319305Y-132368303D01* +X171325031Y-132359014D01* +X171408275Y-132223968D01* +X171408276Y-132223966D01* +X171412115Y-132217738D01* +X171451148Y-132100057D01* +X171465632Y-132056389D01* +X171465632Y-132056387D01* +X171467797Y-132049861D01* +X171478500Y-131945400D01* +X171478500Y-131850000D01* +X178236654Y-131850000D01* +X178236924Y-131854119D01* +X178255647Y-132139776D01* +X178256017Y-132145426D01* +X178256819Y-132149459D01* +X178256820Y-132149465D01* +X178311892Y-132426327D01* +X178313776Y-132435797D01* +X178315103Y-132439706D01* +X178315104Y-132439710D01* +X178403244Y-132699362D01* +X178408941Y-132716145D01* +X178458800Y-132817248D01* +X178513797Y-132928771D01* +X178539885Y-132981673D01* +X178542179Y-132985106D01* +X178701522Y-133223580D01* +X178704367Y-133227838D01* +X178707081Y-133230932D01* +X178707085Y-133230938D01* +X178811545Y-133350051D01* +X178899573Y-133450427D01* +X178902662Y-133453136D01* +X179119062Y-133642915D01* +X179119068Y-133642919D01* +X179122162Y-133645633D01* +X179125588Y-133647922D01* +X179125593Y-133647926D01* +X179235789Y-133721556D01* +X179368327Y-133810115D01* +X179372026Y-133811939D01* +X179372031Y-133811942D01* +X179421070Y-133836125D01* +X179633855Y-133941059D01* +X179637760Y-133942384D01* +X179637761Y-133942385D01* +X179910290Y-134034896D01* +X179910294Y-134034897D01* +X179914203Y-134036224D01* +X179918247Y-134037028D01* +X179918253Y-134037030D01* +X180200535Y-134093180D01* +X180200541Y-134093181D01* +X180204574Y-134093983D01* +X180208679Y-134094252D01* +X180208686Y-134094253D01* +X180495881Y-134113076D01* +X180500000Y-134113346D01* +X180504119Y-134113076D01* +X180791314Y-134094253D01* +X180791321Y-134094252D01* +X180795426Y-134093983D01* +X180799459Y-134093181D01* +X180799465Y-134093180D01* +X181081747Y-134037030D01* +X181081753Y-134037028D01* +X181085797Y-134036224D01* +X181089706Y-134034897D01* +X181089710Y-134034896D01* +X181362239Y-133942385D01* +X181362240Y-133942384D01* +X181366145Y-133941059D01* +X181578930Y-133836125D01* +X181627969Y-133811942D01* +X181627974Y-133811939D01* +X181631673Y-133810115D01* +X181764211Y-133721556D01* +X181874407Y-133647926D01* +X181874412Y-133647922D01* +X181877838Y-133645633D01* +X181880932Y-133642919D01* +X181880938Y-133642915D01* +X182097338Y-133453136D01* +X182100427Y-133450427D01* +X182188455Y-133350051D01* +X182292915Y-133230938D01* +X182292919Y-133230932D01* +X182295633Y-133227838D01* +X182298479Y-133223580D01* +X182457821Y-132985106D01* +X182460115Y-132981673D01* +X182486204Y-132928770D01* +X182534272Y-132876523D01* +X182599209Y-132858500D01* +X184313157Y-132858500D01* +X184326764Y-132859237D01* +X184358262Y-132862659D01* +X184358267Y-132862659D01* +X184364388Y-132863324D01* +X184390638Y-132861027D01* +X184414388Y-132858950D01* +X184419214Y-132858621D01* +X184421686Y-132858500D01* +X184424769Y-132858500D01* +X184436738Y-132857326D01* +X184467506Y-132854310D01* +X184468819Y-132854188D01* +X184513084Y-132850315D01* +X184561413Y-132846087D01* +X184566532Y-132844600D01* +X184571833Y-132844080D01* +X184660834Y-132817209D01* +X184661967Y-132816874D01* +X184745414Y-132792630D01* +X184745418Y-132792628D01* +X184751336Y-132790909D01* +X184756068Y-132788456D01* +X184761169Y-132786916D01* +X184766612Y-132784022D01* +X184843260Y-132743269D01* +X184844426Y-132742657D01* +X184921453Y-132702729D01* +X184926926Y-132699892D01* +X184931089Y-132696569D01* +X184935796Y-132694066D01* +X185007918Y-132635245D01* +X185008774Y-132634554D01* +X185047973Y-132603262D01* +X185050477Y-132600758D01* +X185051195Y-132600116D01* +X185055528Y-132596415D01* +X185089062Y-132569065D01* +X185094276Y-132562763D01* +X185118288Y-132533737D01* +X185126277Y-132524958D01* +X185165830Y-132485405D01* +X185228142Y-132451379D01* +X185254925Y-132448500D01* +X185310400Y-132448500D01* +X185313646Y-132448163D01* +X185313650Y-132448163D01* +X185409308Y-132438238D01* +X185409312Y-132438237D01* +X185416166Y-132437526D01* +X185422702Y-132435345D01* +X185422704Y-132435345D01* +X185576998Y-132383868D01* +X185583946Y-132381550D01* +X185734348Y-132288478D01* +X185859305Y-132163303D01* +X185879921Y-132129858D01* +X185948275Y-132018968D01* +X185948276Y-132018966D01* +X185952115Y-132012738D01* +X186007797Y-131844861D01* +X186008959Y-131833526D01* +X186018172Y-131743598D01* +X186018500Y-131740400D01* +X186018500Y-131139600D01* +X186014323Y-131099339D01* +X186008238Y-131040692D01* +X186008237Y-131040688D01* +X186007526Y-131033834D01* +X185951550Y-130866054D01* +X185858478Y-130715652D01* +X185834066Y-130691282D01* +X185757638Y-130614988D01* +X185733303Y-130590695D01* +X185728765Y-130587898D01* +X185688176Y-130530647D01* +X185684946Y-130459724D01* +X185720572Y-130398313D01* +X185729068Y-130390938D01* +X185739207Y-130382902D01* +X185853739Y-130268171D01* +X185862751Y-130256760D01* +X185947816Y-130118757D01* +X185953963Y-130105576D01* +X186005138Y-129951290D01* +X186008005Y-129937914D01* +X186017672Y-129843562D01* +X186018000Y-129837146D01* +X186018000Y-129812115D01* +X186013525Y-129796876D01* +X186012135Y-129795671D01* +X186004452Y-129794000D01* +X183570116Y-129794000D01* +X183554877Y-129798475D01* +X183553672Y-129799865D01* +X183552001Y-129807548D01* +X183552001Y-129837095D01* +X183552338Y-129843614D01* +X183562257Y-129939206D01* +X183565149Y-129952600D01* +X183616588Y-130106784D01* +X183622761Y-130119962D01* +X183708063Y-130257807D01* +X183717099Y-130269208D01* +X183831828Y-130383738D01* +X183840762Y-130390794D01* +X183881823Y-130448712D01* +X183885053Y-130519635D01* +X183849426Y-130581046D01* +X183841593Y-130587846D01* +X183835652Y-130591522D01* +X183710695Y-130716697D01* +X183706855Y-130722927D01* +X183706854Y-130722928D01* +X183670678Y-130781616D01* +X183617905Y-130829110D01* +X183563418Y-130841500D01* +X182599209Y-130841500D01* +X182531088Y-130821498D01* +X182486203Y-130771229D01* +X182484939Y-130768665D01* +X182460115Y-130718327D01* +X182361705Y-130571046D01* +X182297926Y-130475593D01* +X182297922Y-130475588D01* +X182295633Y-130472162D01* +X182292919Y-130469068D01* +X182292915Y-130469062D01* +X182103136Y-130252662D01* +X182100427Y-130249573D01* +X182078905Y-130230699D01* +X181880938Y-130057085D01* +X181880932Y-130057081D01* +X181877838Y-130054367D01* +X181874412Y-130052078D01* +X181874407Y-130052074D01* +X181635106Y-129892179D01* +X181631673Y-129889885D01* +X181627974Y-129888061D01* +X181627969Y-129888058D01* +X181473971Y-129812115D01* +X181366145Y-129758941D01* +X181148843Y-129685177D01* +X181089710Y-129665104D01* +X181089706Y-129665103D01* +X181085797Y-129663776D01* +X181081753Y-129662972D01* +X181081747Y-129662970D01* +X180799465Y-129606820D01* +X180799459Y-129606819D01* +X180795426Y-129606017D01* +X180791321Y-129605748D01* +X180791314Y-129605747D01* +X180504119Y-129586924D01* +X180500000Y-129586654D01* +X180495881Y-129586924D01* +X180208686Y-129605747D01* +X180208679Y-129605748D01* +X180204574Y-129606017D01* +X180200541Y-129606819D01* +X180200535Y-129606820D01* +X179918253Y-129662970D01* +X179918247Y-129662972D01* +X179914203Y-129663776D01* +X179910294Y-129665103D01* +X179910290Y-129665104D01* +X179851157Y-129685177D01* +X179633855Y-129758941D01* +X179526029Y-129812115D01* +X179372031Y-129888058D01* +X179372026Y-129888061D01* +X179368327Y-129889885D01* +X179364894Y-129892179D01* +X179125593Y-130052074D01* +X179125588Y-130052078D01* +X179122162Y-130054367D01* +X179119068Y-130057081D01* +X179119062Y-130057085D01* +X178921095Y-130230699D01* +X178899573Y-130249573D01* +X178896864Y-130252662D01* +X178707085Y-130469062D01* +X178707081Y-130469068D01* +X178704367Y-130472162D01* +X178702078Y-130475588D01* +X178702074Y-130475593D01* +X178638295Y-130571046D01* +X178539885Y-130718327D01* +X178538061Y-130722025D01* +X178538058Y-130722031D01* +X178508674Y-130781616D01* +X178408941Y-130983855D01* +X178407616Y-130987760D01* +X178407615Y-130987761D01* +X178336087Y-131198478D01* +X178313776Y-131264203D01* +X178312972Y-131268247D01* +X178312970Y-131268253D01* +X178260974Y-131529655D01* +X178256017Y-131554574D01* +X178255748Y-131558679D01* +X178255747Y-131558686D01* +X178241859Y-131770589D01* +X178236654Y-131850000D01* +X171478500Y-131850000D01* +X171478500Y-130944600D01* +X171475397Y-130914691D01* +X171468238Y-130845692D01* +X171468237Y-130845688D01* +X171467526Y-130838834D01* +X171456268Y-130805088D01* +X171413868Y-130678002D01* +X171411550Y-130671054D01* +X171318478Y-130520652D01* +X171193303Y-130395695D01* +X171173905Y-130383738D01* +X171048968Y-130306725D01* +X171048966Y-130306724D01* +X171042738Y-130302885D01* +X171025519Y-130297174D01* +X171016777Y-130294274D01* +X170958416Y-130253844D01* +X170931179Y-130188280D01* +X170943712Y-130118398D01* +X170992036Y-130066386D01* +X171016567Y-130055157D01* +X171036784Y-130048412D01* +X171049962Y-130042239D01* +X171187807Y-129956937D01* +X171199208Y-129947901D01* +X171313739Y-129833171D01* +X171322751Y-129821760D01* +X171407816Y-129683757D01* +X171413963Y-129670576D01* +X171465138Y-129516290D01* +X171468005Y-129502914D01* +X171477672Y-129408562D01* +X171478000Y-129402146D01* +X171478000Y-129267885D01* +X183552000Y-129267885D01* +X183556475Y-129283124D01* +X183557865Y-129284329D01* +X183565548Y-129286000D01* +X184512885Y-129286000D01* +X184528124Y-129281525D01* +X184529329Y-129280135D01* +X184531000Y-129272452D01* +X184531000Y-129267885D01* +X185039000Y-129267885D01* +X185043475Y-129283124D01* +X185044865Y-129284329D01* +X185052548Y-129286000D01* +X185999884Y-129286000D01* +X186015123Y-129281525D01* +X186016328Y-129280135D01* +X186017999Y-129272452D01* +X186017999Y-129242905D01* +X186017662Y-129236386D01* +X186007743Y-129140794D01* +X186004851Y-129127400D01* +X185953412Y-128973216D01* +X185947239Y-128960038D01* +X185861937Y-128822193D01* +X185852901Y-128810792D01* +X185738171Y-128696261D01* +X185726760Y-128687249D01* +X185588757Y-128602184D01* +X185575576Y-128596037D01* +X185421290Y-128544862D01* +X185407914Y-128541995D01* +X185313562Y-128532328D01* +X185307145Y-128532000D01* +X185057115Y-128532000D01* +X185041876Y-128536475D01* +X185040671Y-128537865D01* +X185039000Y-128545548D01* +X185039000Y-129267885D01* +X184531000Y-129267885D01* +X184531000Y-128550116D01* +X184526525Y-128534877D01* +X184525135Y-128533672D01* +X184517452Y-128532001D01* +X184262905Y-128532001D01* +X184256386Y-128532338D01* +X184160794Y-128542257D01* +X184147400Y-128545149D01* +X183993216Y-128596588D01* +X183980038Y-128602761D01* +X183842193Y-128688063D01* +X183830792Y-128697099D01* +X183716261Y-128811829D01* +X183707249Y-128823240D01* +X183622184Y-128961243D01* +X183616037Y-128974424D01* +X183564862Y-129128710D01* +X183561995Y-129142086D01* +X183552328Y-129236438D01* +X183552000Y-129242855D01* +X183552000Y-129267885D01* +X171478000Y-129267885D01* +X171478000Y-129177115D01* +X171473525Y-129161876D01* +X171472135Y-129160671D01* +X171464452Y-129159000D01* +X170329500Y-129159000D01* +X170261379Y-129138998D01* +X170214886Y-129085342D01* +X170203500Y-129033000D01* +X170203500Y-128632885D01* +X170711500Y-128632885D01* +X170715975Y-128648124D01* +X170717365Y-128649329D01* +X170725048Y-128651000D01* +X171459884Y-128651000D01* +X171475123Y-128646525D01* +X171476328Y-128645135D01* +X171477999Y-128637452D01* +X171477999Y-128407905D01* +X171477662Y-128401386D01* +X171467743Y-128305794D01* +X171464851Y-128292400D01* +X171413412Y-128138216D01* +X171407239Y-128125038D01* +X171321937Y-127987193D01* +X171312901Y-127975792D01* +X171198171Y-127861261D01* +X171186760Y-127852249D01* +X171048757Y-127767184D01* +X171035576Y-127761037D01* +X170881290Y-127709862D01* +X170867914Y-127706995D01* +X170773562Y-127697328D01* +X170767145Y-127697000D01* +X170729615Y-127697000D01* +X170714376Y-127701475D01* +X170713171Y-127702865D01* +X170711500Y-127710548D01* +X170711500Y-128632885D01* +X170203500Y-128632885D01* +X170203500Y-127715116D01* +X170199025Y-127699877D01* +X170197635Y-127698672D01* +X170189952Y-127697001D01* +X170147905Y-127697001D01* +X170141388Y-127697338D01* +X170053379Y-127706470D01* +X169983557Y-127693605D01* +X169931775Y-127645034D01* +X169914473Y-127576178D01* +X169937143Y-127508899D01* +X169952401Y-127492359D01* +X169952018Y-127492000D01* +X169957659Y-127485993D01* +X169975446Y-127470312D01* +X169975691Y-127470134D01* +X169975693Y-127470132D01* +X169982107Y-127465472D01* +X169990659Y-127455135D01* +X170017903Y-127422204D01* +X170023134Y-127416270D01* +X170056158Y-127381102D01* +X170056160Y-127381099D01* +X170061586Y-127375321D01* +X170065558Y-127368097D01* +X170078881Y-127348494D01* +X170079080Y-127348254D01* +X170079084Y-127348247D01* +X170084133Y-127342144D01* +X170108047Y-127291324D01* +X170111629Y-127284292D01* +X170138695Y-127235060D01* +X170140665Y-127227385D01* +X170140668Y-127227379D01* +X170140744Y-127227081D01* +X170148776Y-127204772D01* +X170148906Y-127204497D01* +X170148909Y-127204489D01* +X170152283Y-127197318D01* +X170162806Y-127142151D01* +X170164532Y-127134429D01* +X170176529Y-127087707D01* +X170176529Y-127087706D01* +X170178500Y-127080030D01* +X170178500Y-127071793D01* +X170180732Y-127048184D01* +X170180790Y-127047881D01* +X170180790Y-127047877D01* +X170182275Y-127040094D01* +X170181055Y-127020702D01* +X170180504Y-127011938D01* +X170196190Y-126942696D01* +X170201036Y-126935780D01* +X170203500Y-126924452D01* +X170203500Y-126919884D01* +X170711500Y-126919884D01* +X170715975Y-126935123D01* +X170717365Y-126936328D01* +X170725048Y-126937999D01* +X170767095Y-126937999D01* +X170773614Y-126937662D01* +X170869206Y-126927743D01* +X170882600Y-126924851D01* +X171036784Y-126873412D01* +X171049962Y-126867239D01* +X171187807Y-126781937D01* +X171199208Y-126772901D01* +X171313739Y-126658171D01* +X171322751Y-126646760D01* +X171407816Y-126508757D01* +X171413963Y-126495576D01* +X171465138Y-126341290D01* +X171468005Y-126327914D01* +X171477672Y-126233562D01* +X171478000Y-126227146D01* +X171478000Y-126002115D01* +X171473525Y-125986876D01* +X171472135Y-125985671D01* +X171464452Y-125984000D01* +X170729615Y-125984000D01* +X170714376Y-125988475D01* +X170713171Y-125989865D01* +X170711500Y-125997548D01* +X170711500Y-126919884D01* +X170203500Y-126919884D01* +X170203500Y-125602000D01* +X170223502Y-125533879D01* +X170277158Y-125487386D01* +X170329500Y-125476000D01* +X171459884Y-125476000D01* +X171475123Y-125471525D01* +X171476328Y-125470135D01* +X171477999Y-125462452D01* +X171477999Y-125232891D01* +X171477643Y-125226016D01* +X171494095Y-125156952D01* +X171545274Y-125107747D01* +X171603474Y-125093500D01* +X175821800Y-125093500D01* +X175889921Y-125113502D01* +X175909147Y-125129843D01* +X175909420Y-125129540D01* +X175914332Y-125133963D01* +X175918747Y-125138866D01* +X175940329Y-125154546D01* +X176021626Y-125213612D01* +X176073248Y-125251118D01* +X176079276Y-125253802D01* +X176079278Y-125253803D01* +X176163759Y-125291416D01* +X176247712Y-125328794D01* +X176341113Y-125348647D01* +X176428056Y-125367128D01* +X176428061Y-125367128D01* +X176434513Y-125368500D01* +X176625487Y-125368500D01* +X176631939Y-125367128D01* +X176631944Y-125367128D01* +X176718887Y-125348647D01* +X176812288Y-125328794D01* +X176896241Y-125291416D01* +X176980722Y-125253803D01* +X176980724Y-125253802D01* +X176986752Y-125251118D01* +X177141253Y-125138866D01* +X177218769Y-125052776D01* +X177264621Y-125001852D01* +X177264622Y-125001851D01* +X177269040Y-124996944D01* +X177364527Y-124831556D01* +X177423542Y-124649928D01* +X177440907Y-124484706D01* +X177467920Y-124419050D01* +X177477122Y-124408782D01* +X177557247Y-124328657D01* +X177565537Y-124321113D01* +X177572018Y-124317000D01* +X177618659Y-124267332D01* +X177621413Y-124264491D01* +X177635904Y-124250000D01* +X178236654Y-124250000D01* +X178236924Y-124254119D01* +X178255002Y-124529938D01* +X178256017Y-124545426D01* +X178256819Y-124549459D01* +X178256820Y-124549465D01* +X178309664Y-124815125D01* +X178313776Y-124835797D01* +X178315103Y-124839706D01* +X178315104Y-124839710D01* +X178363826Y-124983240D01* +X178408941Y-125116145D01* +X178458166Y-125215964D01* +X178533389Y-125368500D01* +X178539885Y-125381673D01* +X178542179Y-125385106D01* +X178700518Y-125622077D01* +X178704367Y-125627838D01* +X178707081Y-125630932D01* +X178707085Y-125630938D01* +X178875650Y-125823148D01* +X178899573Y-125850427D01* +X178902662Y-125853136D01* +X179119062Y-126042915D01* +X179119068Y-126042919D01* +X179122162Y-126045633D01* +X179125588Y-126047922D01* +X179125593Y-126047926D01* +X179226749Y-126115516D01* +X179368327Y-126210115D01* +X179372026Y-126211939D01* +X179372031Y-126211942D01* +X179494890Y-126272529D01* +X179633855Y-126341059D01* +X179637760Y-126342384D01* +X179637761Y-126342385D01* +X179910290Y-126434896D01* +X179910294Y-126434897D01* +X179914203Y-126436224D01* +X179918247Y-126437028D01* +X179918253Y-126437030D01* +X180200535Y-126493180D01* +X180200541Y-126493181D01* +X180204574Y-126493983D01* +X180208679Y-126494252D01* +X180208686Y-126494253D01* +X180495881Y-126513076D01* +X180500000Y-126513346D01* +X180504119Y-126513076D01* +X180791314Y-126494253D01* +X180791321Y-126494252D01* +X180795426Y-126493983D01* +X180799459Y-126493181D01* +X180799465Y-126493180D01* +X181081747Y-126437030D01* +X181081753Y-126437028D01* +X181085797Y-126436224D01* +X181089706Y-126434897D01* +X181089710Y-126434896D01* +X181362239Y-126342385D01* +X181362240Y-126342384D01* +X181366145Y-126341059D01* +X181505110Y-126272529D01* +X181627969Y-126211942D01* +X181627974Y-126211939D01* +X181631673Y-126210115D01* +X181773251Y-126115516D01* +X181874407Y-126047926D01* +X181874412Y-126047922D01* +X181877838Y-126045633D01* +X181880932Y-126042919D01* +X181880938Y-126042915D01* +X182097338Y-125853136D01* +X182100427Y-125850427D01* +X182124350Y-125823148D01* +X182292915Y-125630938D01* +X182292919Y-125630932D01* +X182295633Y-125627838D01* +X182299483Y-125622077D01* +X182457821Y-125385106D01* +X182460115Y-125381673D01* +X182466612Y-125368500D01* +X182541834Y-125215964D01* +X182591059Y-125116145D01* +X182636174Y-124983240D01* +X182684896Y-124839710D01* +X182684897Y-124839706D01* +X182686224Y-124835797D01* +X182690336Y-124815125D01* +X182743180Y-124549465D01* +X182743181Y-124549459D01* +X182743983Y-124545426D01* +X182744999Y-124529938D01* +X182763076Y-124254119D01* +X182763346Y-124250000D01* +X182758259Y-124172382D01* +X182744253Y-123958686D01* +X182744252Y-123958679D01* +X182743983Y-123954574D01* +X182742977Y-123949514D01* +X182687030Y-123668253D01* +X182687028Y-123668247D01* +X182686224Y-123664203D01* +X182684641Y-123659538D01* +X182592385Y-123387761D01* +X182592384Y-123387760D01* +X182591059Y-123383855D01* +X182507368Y-123214147D01* +X182461942Y-123122031D01* +X182461939Y-123122026D01* +X182460115Y-123118327D01* +X182399982Y-123028332D01* +X182297926Y-122875593D01* +X182297922Y-122875588D01* +X182295633Y-122872162D01* +X182292919Y-122869068D01* +X182292915Y-122869062D01* +X182103136Y-122652662D01* +X182100427Y-122649573D01* +X182035851Y-122592941D01* +X181880938Y-122457085D01* +X181880932Y-122457081D01* +X181877838Y-122454367D01* +X181874412Y-122452078D01* +X181874407Y-122452074D01* +X181642739Y-122297279D01* +X181631673Y-122289885D01* +X181627974Y-122288061D01* +X181627969Y-122288058D01* +X181490459Y-122220246D01* +X181366145Y-122158941D01* +X181351495Y-122153968D01* +X181089710Y-122065104D01* +X181089706Y-122065103D01* +X181085797Y-122063776D01* +X181081753Y-122062972D01* +X181081747Y-122062970D01* +X180799465Y-122006820D01* +X180799459Y-122006819D01* +X180795426Y-122006017D01* +X180791321Y-122005748D01* +X180791314Y-122005747D01* +X180504119Y-121986924D01* +X180500000Y-121986654D01* +X180495881Y-121986924D01* +X180208686Y-122005747D01* +X180208679Y-122005748D01* +X180204574Y-122006017D01* +X180200541Y-122006819D01* +X180200535Y-122006820D01* +X179918253Y-122062970D01* +X179918247Y-122062972D01* +X179914203Y-122063776D01* +X179910294Y-122065103D01* +X179910290Y-122065104D01* +X179648505Y-122153968D01* +X179633855Y-122158941D01* +X179509541Y-122220246D01* +X179372031Y-122288058D01* +X179372026Y-122288061D01* +X179368327Y-122289885D01* +X179357261Y-122297279D01* +X179125593Y-122452074D01* +X179125588Y-122452078D01* +X179122162Y-122454367D01* +X179119068Y-122457081D01* +X179119062Y-122457085D01* +X178964149Y-122592941D01* +X178899573Y-122649573D01* +X178896864Y-122652662D01* +X178707085Y-122869062D01* +X178707081Y-122869068D01* +X178704367Y-122872162D01* +X178702078Y-122875588D01* +X178702074Y-122875593D01* +X178600018Y-123028332D01* +X178539885Y-123118327D01* +X178538061Y-123122026D01* +X178538058Y-123122031D01* +X178492632Y-123214147D01* +X178408941Y-123383855D01* +X178407616Y-123387760D01* +X178407615Y-123387761D01* +X178315360Y-123659538D01* +X178313776Y-123664203D01* +X178312972Y-123668247D01* +X178312970Y-123668253D01* +X178257024Y-123949514D01* +X178256017Y-123954574D01* +X178255748Y-123958679D01* +X178255747Y-123958686D01* +X178241741Y-124172382D01* +X178236654Y-124250000D01* +X177635904Y-124250000D01* +X177641135Y-124244769D01* +X177643612Y-124241576D01* +X177651317Y-124232555D01* +X177676159Y-124206100D01* +X177681586Y-124200321D01* +X177685407Y-124193371D01* +X177691346Y-124182568D01* +X177702202Y-124166041D01* +X177709757Y-124156302D01* +X177709758Y-124156300D01* +X177714614Y-124150040D01* +X177732174Y-124109460D01* +X177737391Y-124098812D01* +X177754875Y-124067009D01* +X177754876Y-124067007D01* +X177758695Y-124060060D01* +X177761972Y-124047299D01* +X177763733Y-124040438D01* +X177770137Y-124021734D01* +X177775033Y-124010420D01* +X177775033Y-124010419D01* +X177778181Y-124003145D01* +X177779420Y-123995322D01* +X177779423Y-123995312D01* +X177785100Y-123959470D01* +X177787503Y-123947861D01* +X177798500Y-123905030D01* +X177798500Y-123884776D01* +X177800051Y-123865065D01* +X177801980Y-123852886D01* +X177803220Y-123845057D01* +X177799059Y-123801038D01* +X177798500Y-123789181D01* +X177798500Y-123737634D01* +X177818502Y-123669513D01* +X177858197Y-123630490D01* +X177861449Y-123628478D01* +X177901848Y-123603478D01* +X178026805Y-123478303D01* +X178062353Y-123420634D01* +X178115775Y-123333968D01* +X178115776Y-123333966D01* +X178119615Y-123327738D01* +X178163123Y-123196565D01* +X178173132Y-123166389D01* +X178173132Y-123166387D01* +X178175297Y-123159861D01* +X178176539Y-123147744D01* +X178182485Y-123089708D01* +X178186000Y-123055400D01* +X178186000Y-122054600D01* +X178185405Y-122048861D01* +X178175738Y-121955692D01* +X178175737Y-121955688D01* +X178175026Y-121948834D01* +X178169392Y-121931945D01* +X178123443Y-121794221D01* +X178119050Y-121781054D01* +X178025978Y-121630652D01* +X177900803Y-121505695D01* +X177894572Y-121501854D01* +X177756468Y-121416725D01* +X177756466Y-121416724D01* +X177750238Y-121412885D01* +X177734069Y-121407522D01* +X177725070Y-121404537D01* +X177666709Y-121364107D01* +X177639472Y-121298543D01* +X177652005Y-121228661D01* +X177700329Y-121176649D01* +X177724859Y-121165421D01* +X177744493Y-121158871D01* +X177744503Y-121158867D01* +X177751446Y-121156550D01* +X177901848Y-121063478D01* +X178026805Y-120938303D01* +X178036107Y-120923212D01* +X178115775Y-120793968D01* +X178115776Y-120793966D01* +X178119615Y-120787738D01* +X178160907Y-120663246D01* +X178201338Y-120604886D01* +X178266902Y-120577649D01* +X178336783Y-120590182D01* +X178388795Y-120638507D01* +X178406500Y-120702913D01* +X178406500Y-120896400D01* +X178406837Y-120899646D01* +X178406837Y-120899650D01* +X178416618Y-120993914D01* +X178417474Y-121002166D01* +X178419655Y-121008702D01* +X178419655Y-121008704D01* +X178451782Y-121104999D01* +X178473450Y-121169946D01* +X178566522Y-121320348D01* +X178691697Y-121445305D01* +X178697927Y-121449145D01* +X178697928Y-121449146D01* +X178835288Y-121533816D01* +X178842262Y-121538115D01* +X178903721Y-121558500D01* +X179003611Y-121591632D01* +X179003613Y-121591632D01* +X179010139Y-121593797D01* +X179016975Y-121594497D01* +X179016978Y-121594498D01* +X179060031Y-121598909D01* +X179114600Y-121604500D01* +X179740400Y-121604500D01* +X179743646Y-121604163D01* +X179743650Y-121604163D01* +X179839308Y-121594238D01* +X179839312Y-121594237D01* +X179846166Y-121593526D01* +X179852702Y-121591345D01* +X179852704Y-121591345D01* +X179984806Y-121547272D01* +X180013946Y-121537550D01* +X180164348Y-121444478D01* +X180204178Y-121404579D01* +X180251138Y-121357537D01* +X180313421Y-121323458D01* +X180384241Y-121328461D01* +X180429329Y-121357382D01* +X180511829Y-121439739D01* +X180523240Y-121448751D01* +X180661243Y-121533816D01* +X180674424Y-121539963D01* +X180828710Y-121591138D01* +X180842086Y-121594005D01* +X180936438Y-121603672D01* +X180942854Y-121604000D01* +X180980385Y-121604000D01* +X180995624Y-121599525D01* +X180996829Y-121598135D01* +X180998500Y-121590452D01* +X180998500Y-121585884D01* +X181506500Y-121585884D01* +X181510975Y-121601123D01* +X181512365Y-121602328D01* +X181520048Y-121603999D01* +X181562095Y-121603999D01* +X181568614Y-121603662D01* +X181664206Y-121593743D01* +X181677600Y-121590851D01* +X181831784Y-121539412D01* +X181844962Y-121533239D01* +X181982807Y-121447937D01* +X181994208Y-121438901D01* +X182108739Y-121324171D01* +X182117751Y-121312760D01* +X182202816Y-121174757D01* +X182208963Y-121161576D01* +X182260138Y-121007290D01* +X182263005Y-120993914D01* +X182272672Y-120899562D01* +X182273000Y-120893146D01* +X182273000Y-120668115D01* +X182268525Y-120652876D01* +X182267135Y-120651671D01* +X182259452Y-120650000D01* +X181524615Y-120650000D01* +X181509376Y-120654475D01* +X181508171Y-120655865D01* +X181506500Y-120663548D01* +X181506500Y-121585884D01* +X180998500Y-121585884D01* +X180998500Y-120123885D01* +X181506500Y-120123885D01* +X181510975Y-120139124D01* +X181512365Y-120140329D01* +X181520048Y-120142000D01* +X182254884Y-120142000D01* +X182270123Y-120137525D01* +X182271328Y-120136135D01* +X182272999Y-120128452D01* +X182272999Y-119898905D01* +X182272662Y-119892386D01* +X182262743Y-119796794D01* +X182259851Y-119783400D01* +X182208412Y-119629216D01* +X182202239Y-119616038D01* +X182116937Y-119478193D01* +X182107901Y-119466792D01* +X181993171Y-119352261D01* +X181981760Y-119343249D01* +X181843757Y-119258184D01* +X181830576Y-119252037D01* +X181676290Y-119200862D01* +X181662914Y-119197995D01* +X181568562Y-119188328D01* +X181562145Y-119188000D01* +X181524615Y-119188000D01* +X181509376Y-119192475D01* +X181508171Y-119193865D01* +X181506500Y-119201548D01* +X181506500Y-120123885D01* +X180998500Y-120123885D01* +X180998500Y-119206116D01* +X180994025Y-119190877D01* +X180992635Y-119189672D01* +X180984952Y-119188001D01* +X180942905Y-119188001D01* +X180936386Y-119188338D01* +X180840794Y-119198257D01* +X180827400Y-119201149D01* +X180673216Y-119252588D01* +X180660038Y-119258761D01* +X180522193Y-119344063D01* +X180510792Y-119353099D01* +X180438672Y-119425344D01* +X180376389Y-119459423D01* +X180305569Y-119454420D01* +X180248696Y-119411922D01* +X180223828Y-119345424D01* +X180223499Y-119336326D01* +X180223499Y-117442235D01* +X180243501Y-117374114D01* +X180297157Y-117327621D01* +X180363108Y-117316972D01* +X180411517Y-117322231D01* +X180418328Y-117322600D01* +X180444883Y-117322600D01* +X180463451Y-117317148D01* +X180534448Y-117317148D01* +X180588045Y-117348949D01* +X180599780Y-117360684D01* +X180612620Y-117375717D01* +X180624529Y-117392108D01* +X180644411Y-117408556D01* +X180658606Y-117420299D01* +X180667385Y-117428289D01* +X180910264Y-117671168D01* +X180939266Y-117716342D01* +X180939286Y-117716395D01* +X180941058Y-117723777D01* +X180944539Y-117730521D01* +X180944540Y-117730524D01* +X180970799Y-117781399D01* +X181019709Y-117876161D01* +X181024698Y-117881880D01* +X181025952Y-117883318D01* +X181132439Y-118005385D01* +X181272739Y-118103990D01* +X181337794Y-118129354D01* +X181425429Y-118163522D01* +X181425432Y-118163523D01* +X181432509Y-118166282D01* +X181440042Y-118167274D01* +X181440043Y-118167274D01* +X181520195Y-118177826D01* +X181563294Y-118183500D01* +X184121088Y-118183500D01* +X184129658Y-118183792D01* +X184179776Y-118187209D01* +X184179780Y-118187209D01* +X184187352Y-118187725D01* +X184194829Y-118186420D01* +X184194830Y-118186420D01* +X184244071Y-118177826D01* +X184250303Y-118176738D01* +X184256821Y-118175777D01* +X184320242Y-118168102D01* +X184327343Y-118165419D01* +X184329952Y-118164778D01* +X184346262Y-118160315D01* +X184348798Y-118159550D01* +X184356284Y-118158243D01* +X184414800Y-118132556D01* +X184420904Y-118130065D01* +X184424078Y-118128866D01* +X184464817Y-118113472D01* +X184473548Y-118110173D01* +X184473549Y-118110172D01* +X184480656Y-118107487D01* +X184486919Y-118103183D01* +X184489285Y-118101946D01* +X184504097Y-118093701D01* +X184506351Y-118092368D01* +X184513305Y-118089315D01* +X184564002Y-118050413D01* +X184569332Y-118046541D01* +X184615720Y-118014661D01* +X184615725Y-118014656D01* +X184621981Y-118010357D01* +X184627387Y-118004290D01* +X184663435Y-117963830D01* +X184668416Y-117958554D01* +X185061565Y-117565405D01* +X185123877Y-117531379D01* +X185150660Y-117528500D01* +X185310400Y-117528500D01* +X185313646Y-117528163D01* +X185313650Y-117528163D01* +X185409308Y-117518238D01* +X185409312Y-117518237D01* +X185416166Y-117517526D01* +X185422702Y-117515345D01* +X185422704Y-117515345D01* +X185576998Y-117463868D01* +X185583946Y-117461550D01* +X185734348Y-117368478D01* +X185756425Y-117346363D01* +X185854134Y-117248483D01* +X185859305Y-117243303D01* +X185894741Y-117185815D01* +X185948275Y-117098968D01* +X185948276Y-117098966D01* +X185952115Y-117092738D01* +X185981978Y-117002702D01* +X186005632Y-116931389D01* +X186005632Y-116931387D01* +X186007797Y-116924861D01* +X186018500Y-116820400D01* +X186018500Y-116219600D01* +X186013561Y-116171998D01* +X186008238Y-116120692D01* +X186008237Y-116120688D01* +X186007526Y-116113834D01* +X186004426Y-116104540D01* +X185954513Y-115954935D01* +X185951550Y-115946054D01* +X185858478Y-115795652D01* +X185733303Y-115670695D01* +X185728765Y-115667898D01* +X185688176Y-115610647D01* +X185684946Y-115539724D01* +X185720572Y-115478313D01* +X185729068Y-115470938D01* +X185739207Y-115462902D01* +X185853739Y-115348171D01* +X185862751Y-115336760D01* +X185947816Y-115198757D01* +X185953963Y-115185576D01* +X186005138Y-115031290D01* +X186008005Y-115017914D01* +X186017672Y-114923562D01* +X186018000Y-114917146D01* +X186018000Y-114892115D01* +X186013525Y-114876876D01* +X186012135Y-114875671D01* +X186004452Y-114874000D01* +X184657000Y-114874000D01* +X184588879Y-114853998D01* +X184542386Y-114800342D01* +X184531000Y-114748000D01* +X184531000Y-114347885D01* +X185039000Y-114347885D01* +X185043475Y-114363124D01* +X185044865Y-114364329D01* +X185052548Y-114366000D01* +X185999884Y-114366000D01* +X186015123Y-114361525D01* +X186016328Y-114360135D01* +X186017999Y-114352452D01* +X186017999Y-114322905D01* +X186017662Y-114316386D01* +X186007743Y-114220794D01* +X186004851Y-114207400D01* +X185997910Y-114186595D01* +X185995326Y-114115646D01* +X186031509Y-114054562D01* +X186094974Y-114022737D01* +X186165569Y-114030276D01* +X186191494Y-114044782D01* +X186198660Y-114049988D01* +X186233248Y-114075118D01* +X186239276Y-114077802D01* +X186239278Y-114077803D01* +X186387695Y-114143882D01* +X186407712Y-114152794D01* +X186492790Y-114170878D01* +X186588056Y-114191128D01* +X186588061Y-114191128D01* +X186594513Y-114192500D01* +X186785487Y-114192500D01* +X186791939Y-114191128D01* +X186791944Y-114191128D01* +X186887210Y-114170878D01* +X186972288Y-114152794D01* +X186992305Y-114143882D01* +X187140722Y-114077803D01* +X187140724Y-114077802D01* +X187146752Y-114075118D01* +X187152400Y-114071015D01* +X187218848Y-114022737D01* +X187301253Y-113962866D01* +X187314338Y-113948334D01* +X187424621Y-113825852D01* +X187424622Y-113825851D01* +X187429040Y-113820944D01* +X187432339Y-113815231D01* +X187432342Y-113815226D01* +X187464041Y-113760321D01* +X187515424Y-113711328D01* +X187585138Y-113697892D01* +X187651048Y-113724279D01* +X187662255Y-113734226D01* +X187686325Y-113758296D01* +X187717062Y-113808454D01* +X187727635Y-113840992D01* +X187757384Y-113932548D01* +X187760473Y-113942056D01* +X187855960Y-114107444D01* +X187860378Y-114112351D01* +X187860379Y-114112352D01* +X187917147Y-114175399D01* +X187983747Y-114249366D01* +X188053287Y-114299890D01* +X188116331Y-114345694D01* +X188138248Y-114361618D01* +X188144276Y-114364302D01* +X188144278Y-114364303D01* +X188306681Y-114436609D01* +X188312712Y-114439294D01* +X188393382Y-114456441D01* +X188493056Y-114477628D01* +X188493061Y-114477628D01* +X188499513Y-114479000D01* +X188690487Y-114479000D01* +X188696939Y-114477628D01* +X188696944Y-114477628D01* +X188796618Y-114456441D01* +X188877288Y-114439294D01* +X188883319Y-114436609D01* +X189045722Y-114364303D01* +X189045724Y-114364302D01* +X189051752Y-114361618D01* +X189073670Y-114345694D01* +X189136713Y-114299890D01* +X189206253Y-114249366D01* +X189272853Y-114175399D01* +X189329621Y-114112352D01* +X189329622Y-114112351D01* +X189334040Y-114107444D01* +X189399153Y-113994665D01* +X189426223Y-113947779D01* +X189426224Y-113947777D01* +X189429527Y-113942056D01* +X189488542Y-113760428D01* +X189492342Y-113724279D01* +X189507814Y-113577065D01* +X189508504Y-113570500D01* +X189500550Y-113494824D01* +X189489232Y-113387135D01* +X189489232Y-113387133D01* +X189488542Y-113380572D01* +X189429527Y-113198944D01* +X189334040Y-113033556D01* +X189319364Y-113017256D01* +X189210675Y-112896545D01* +X189210674Y-112896544D01* +X189206253Y-112891634D01* +X189064485Y-112788633D01* +X189057094Y-112783263D01* +X189057093Y-112783262D01* +X189051752Y-112779382D01* +X189045724Y-112776698D01* +X189045722Y-112776697D01* +X188883319Y-112704391D01* +X188883318Y-112704391D01* +X188877288Y-112701706D01* +X188870827Y-112700333D01* +X188870822Y-112700331D01* +X188768303Y-112678539D01* +X188705829Y-112644811D01* +X188671508Y-112582661D01* +X188668500Y-112555293D01* +X188668500Y-111743744D01* +X188688502Y-111675623D01* +X188692564Y-111669683D01* +X188694621Y-111666852D01* +X188699040Y-111661944D01* +X188720870Y-111624134D01* +X188791223Y-111502279D01* +X188791224Y-111502278D01* +X188794527Y-111496556D01* +X188853542Y-111314928D01* +X188856814Y-111283803D01* +X188872814Y-111131565D01* +X188873504Y-111125000D01* +X188871740Y-111108213D01* +X188854232Y-110941635D01* +X188854232Y-110941633D01* +X188853542Y-110935072D01* +X188794527Y-110753444D01* +X188715040Y-110615768D01* +X190510302Y-110615768D01* +X190547554Y-110742342D01* +X190552147Y-110753710D01* +X190642566Y-110926666D01* +X190649282Y-110936928D01* +X190771568Y-111089020D01* +X190780152Y-111097786D01* +X190929656Y-111223236D01* +X190939767Y-111230160D01* +X191110798Y-111324184D01* +X191122062Y-111329012D01* +X191308095Y-111388025D01* +X191320084Y-111390573D01* +X191471947Y-111407607D01* +X191478971Y-111408000D01* +X191562885Y-111408000D01* +X191578124Y-111403525D01* +X191579329Y-111402135D01* +X191581000Y-111394452D01* +X191581000Y-111389885D01* +X192089000Y-111389885D01* +X192093475Y-111405124D01* +X192094865Y-111406329D01* +X192102548Y-111408000D01* +X192184124Y-111408000D01* +X192190272Y-111407699D01* +X192335361Y-111393473D01* +X192347396Y-111391090D01* +X192534223Y-111334683D01* +X192545565Y-111330008D01* +X192717879Y-111238388D01* +X192728095Y-111231601D01* +X192879335Y-111108253D01* +X192888039Y-111099609D01* +X193012438Y-110949237D01* +X193019297Y-110939069D01* +X193112121Y-110767393D01* +X193116871Y-110756093D01* +X193158595Y-110621307D01* +X193158676Y-110615768D01* +X194310302Y-110615768D01* +X194347554Y-110742342D01* +X194352147Y-110753710D01* +X194442566Y-110926666D01* +X194449282Y-110936928D01* +X194571568Y-111089020D01* +X194580152Y-111097786D01* +X194729656Y-111223236D01* +X194739767Y-111230160D01* +X194910798Y-111324184D01* +X194922062Y-111329012D01* +X195108095Y-111388025D01* +X195120084Y-111390573D01* +X195271947Y-111407607D01* +X195278971Y-111408000D01* +X195362885Y-111408000D01* +X195378124Y-111403525D01* +X195379329Y-111402135D01* +X195381000Y-111394452D01* +X195381000Y-111389885D01* +X195889000Y-111389885D01* +X195893475Y-111405124D01* +X195894865Y-111406329D01* +X195902548Y-111408000D01* +X195984124Y-111408000D01* +X195990272Y-111407699D01* +X196135361Y-111393473D01* +X196147396Y-111391090D01* +X196334223Y-111334683D01* +X196345565Y-111330008D01* +X196517879Y-111238388D01* +X196528095Y-111231601D01* +X196679335Y-111108253D01* +X196688039Y-111099609D01* +X196812438Y-110949237D01* +X196819297Y-110939069D01* +X196912121Y-110767393D01* +X196916871Y-110756093D01* +X196958595Y-110621307D01* +X196958801Y-110607205D01* +X196952045Y-110604000D01* +X195907115Y-110604000D01* +X195891876Y-110608475D01* +X195890671Y-110609865D01* +X195889000Y-110617548D01* +X195889000Y-111389885D01* +X195381000Y-111389885D01* +X195381000Y-110622115D01* +X195376525Y-110606876D01* +X195375135Y-110605671D01* +X195367452Y-110604000D01* +X194324953Y-110604000D01* +X194311422Y-110607973D01* +X194310302Y-110615768D01* +X193158676Y-110615768D01* +X193158801Y-110607205D01* +X193152045Y-110604000D01* +X192107115Y-110604000D01* +X192091876Y-110608475D01* +X192090671Y-110609865D01* +X192089000Y-110617548D01* +X192089000Y-111389885D01* +X191581000Y-111389885D01* +X191581000Y-110622115D01* +X191576525Y-110606876D01* +X191575135Y-110605671D01* +X191567452Y-110604000D01* +X190524953Y-110604000D01* +X190511422Y-110607973D01* +X190510302Y-110615768D01* +X188715040Y-110615768D01* +X188699040Y-110588056D01* +X188682881Y-110570109D01* +X188575675Y-110451045D01* +X188575674Y-110451044D01* +X188571253Y-110446134D01* +X188437332Y-110348834D01* +X188422094Y-110337763D01* +X188422093Y-110337762D01* +X188416752Y-110333882D01* +X188410724Y-110331198D01* +X188410722Y-110331197D01* +X188248319Y-110258891D01* +X188248318Y-110258891D01* +X188242288Y-110256206D01* +X188129213Y-110232171D01* +X188061944Y-110217872D01* +X188061939Y-110217872D01* +X188055487Y-110216500D01* +X187864513Y-110216500D01* +X187858061Y-110217872D01* +X187858056Y-110217872D01* +X187687265Y-110254175D01* +X187616474Y-110248773D01* +X187559841Y-110205956D01* +X187541235Y-110169865D01* +X187526568Y-110124725D01* +X187526567Y-110124724D01* +X187524527Y-110118444D01* +X187509719Y-110092795D01* +X190511199Y-110092795D01* +X190517955Y-110096000D01* +X191562885Y-110096000D01* +X191578124Y-110091525D01* +X191579329Y-110090135D01* +X191581000Y-110082452D01* +X191581000Y-110077885D01* +X192089000Y-110077885D01* +X192093475Y-110093124D01* +X192094865Y-110094329D01* +X192102548Y-110096000D01* +X193145047Y-110096000D01* +X193155962Y-110092795D01* +X194311199Y-110092795D01* +X194317955Y-110096000D01* +X195362885Y-110096000D01* +X195378124Y-110091525D01* +X195379329Y-110090135D01* +X195381000Y-110082452D01* +X195381000Y-110077885D01* +X195889000Y-110077885D01* +X195893475Y-110093124D01* +X195894865Y-110094329D01* +X195902548Y-110096000D01* +X196945047Y-110096000D01* +X196958578Y-110092027D01* +X196959698Y-110084232D01* +X196922446Y-109957658D01* +X196917853Y-109946290D01* +X196827434Y-109773334D01* +X196820718Y-109763072D01* +X196698432Y-109610980D01* +X196689848Y-109602214D01* +X196540344Y-109476764D01* +X196530233Y-109469840D01* +X196359202Y-109375816D01* +X196347938Y-109370988D01* +X196161905Y-109311975D01* +X196149916Y-109309427D01* +X195998053Y-109292393D01* +X195991029Y-109292000D01* +X195907115Y-109292000D01* +X195891876Y-109296475D01* +X195890671Y-109297865D01* +X195889000Y-109305548D01* +X195889000Y-110077885D01* +X195381000Y-110077885D01* +X195381000Y-109310115D01* +X195376525Y-109294876D01* +X195375135Y-109293671D01* +X195367452Y-109292000D01* +X195285876Y-109292000D01* +X195279728Y-109292301D01* +X195134639Y-109306527D01* +X195122604Y-109308910D01* +X194935777Y-109365317D01* +X194924435Y-109369992D01* +X194752121Y-109461612D01* +X194741905Y-109468399D01* +X194590665Y-109591747D01* +X194581961Y-109600391D01* +X194457562Y-109750763D01* +X194450703Y-109760931D01* +X194357879Y-109932607D01* +X194353129Y-109943907D01* +X194311405Y-110078693D01* +X194311199Y-110092795D01* +X193155962Y-110092795D01* +X193158578Y-110092027D01* +X193159698Y-110084232D01* +X193122446Y-109957658D01* +X193117853Y-109946290D01* +X193027434Y-109773334D01* +X193020718Y-109763072D01* +X192898432Y-109610980D01* +X192889848Y-109602214D01* +X192740344Y-109476764D01* +X192730233Y-109469840D01* +X192559202Y-109375816D01* +X192547938Y-109370988D01* +X192361905Y-109311975D01* +X192349916Y-109309427D01* +X192198053Y-109292393D01* +X192191029Y-109292000D01* +X192107115Y-109292000D01* +X192091876Y-109296475D01* +X192090671Y-109297865D01* +X192089000Y-109305548D01* +X192089000Y-110077885D01* +X191581000Y-110077885D01* +X191581000Y-109310115D01* +X191576525Y-109294876D01* +X191575135Y-109293671D01* +X191567452Y-109292000D01* +X191485876Y-109292000D01* +X191479728Y-109292301D01* +X191334639Y-109306527D01* +X191322604Y-109308910D01* +X191135777Y-109365317D01* +X191124435Y-109369992D01* +X190952121Y-109461612D01* +X190941905Y-109468399D01* +X190790665Y-109591747D01* +X190781961Y-109600391D01* +X190657562Y-109750763D01* +X190650703Y-109760931D01* +X190557879Y-109932607D01* +X190553129Y-109943907D01* +X190511405Y-110078693D01* +X190511199Y-110092795D01* +X187509719Y-110092795D01* +X187429040Y-109953056D01* +X187356333Y-109872306D01* +X187305675Y-109816045D01* +X187305674Y-109816044D01* +X187301253Y-109811134D01* +X187146752Y-109698882D01* +X187140724Y-109696198D01* +X187140722Y-109696197D01* +X186978319Y-109623891D01* +X186978318Y-109623891D01* +X186972288Y-109621206D01* +X186870598Y-109599591D01* +X186791944Y-109582872D01* +X186791939Y-109582872D01* +X186785487Y-109581500D01* +X186594513Y-109581500D01* +X186588061Y-109582872D01* +X186588056Y-109582872D01* +X186509402Y-109599591D01* +X186407712Y-109621206D01* +X186401682Y-109623891D01* +X186401681Y-109623891D01* +X186239278Y-109696197D01* +X186239276Y-109696198D01* +X186233248Y-109698882D01* +X186078747Y-109811134D01* +X186074326Y-109816044D01* +X186074325Y-109816045D01* +X186023668Y-109872306D01* +X185950960Y-109953056D01* +X185908550Y-110026512D01* +X185870092Y-110093124D01* +X185855473Y-110118444D01* +X185796458Y-110300072D01* +X185795768Y-110306633D01* +X185795768Y-110306635D01* +X185779873Y-110457866D01* +X185776496Y-110490000D01* +X185777186Y-110496565D01* +X185790208Y-110620458D01* +X185796458Y-110679928D01* +X185855473Y-110861556D01* +X185858776Y-110867278D01* +X185858777Y-110867279D01* +X185892686Y-110926010D01* +X185950960Y-111026944D01* +X186024137Y-111108215D01* +X186054853Y-111172221D01* +X186056500Y-111192524D01* +X186056500Y-112581476D01* +X186036498Y-112649597D01* +X186024142Y-112665779D01* +X185950960Y-112747056D01* +X185920840Y-112799226D01* +X185863539Y-112898474D01* +X185855473Y-112912444D01* +X185796458Y-113094072D01* +X185795768Y-113100633D01* +X185795768Y-113100635D01* +X185782039Y-113231261D01* +X185776496Y-113284000D01* +X185777186Y-113290565D01* +X185795733Y-113467026D01* +X185796458Y-113473928D01* +X185802207Y-113491620D01* +X185827120Y-113568296D01* +X185829147Y-113639264D01* +X185792485Y-113700061D01* +X185728773Y-113731387D01* +X185658239Y-113723294D01* +X185641171Y-113714492D01* +X185588757Y-113682184D01* +X185575576Y-113676037D01* +X185421290Y-113624862D01* +X185407914Y-113621995D01* +X185313562Y-113612328D01* +X185307145Y-113612000D01* +X185057115Y-113612000D01* +X185041876Y-113616475D01* +X185040671Y-113617865D01* +X185039000Y-113625548D01* +X185039000Y-114347885D01* +X184531000Y-114347885D01* +X184531000Y-113630116D01* +X184526525Y-113614877D01* +X184525135Y-113613672D01* +X184517452Y-113612001D01* +X184503278Y-113612001D01* +X184435157Y-113591999D01* +X184388664Y-113538343D01* +X184378560Y-113468069D01* +X184390480Y-113433249D01* +X184389319Y-113432732D01* +X184391823Y-113427107D01* +X184394870Y-113421744D01* +X184454203Y-113243382D01* +X184477762Y-113056892D01* +X184478008Y-113039274D01* +X184478089Y-113033522D01* +X184478089Y-113033518D01* +X184478138Y-113030000D01* +X184459795Y-112842926D01* +X184452154Y-112817616D01* +X184425773Y-112730241D01* +X184405465Y-112662977D01* +X184317218Y-112497008D01* +X184198415Y-112351340D01* +X184084961Y-112257483D01* +X184045224Y-112198650D01* +X184043601Y-112127672D01* +X184056824Y-112096259D01* +X184059753Y-112091307D01* +X184064614Y-112085040D01* +X184082174Y-112044460D01* +X184087391Y-112033812D01* +X184104875Y-112002009D01* +X184104876Y-112002007D01* +X184108695Y-111995060D01* +X184112359Y-111980792D01* +X184113067Y-111978031D01* +X184113733Y-111975437D01* +X184120137Y-111956734D01* +X184125033Y-111945420D01* +X184125033Y-111945419D01* +X184128181Y-111938145D01* +X184129420Y-111930322D01* +X184129423Y-111930312D01* +X184135099Y-111894476D01* +X184137505Y-111882856D01* +X184146529Y-111847709D01* +X184146530Y-111847705D01* +X184148500Y-111840031D01* +X184148776Y-111840102D01* +X184175344Y-111779176D01* +X184232096Y-111740517D01* +X184263244Y-111730125D01* +X184281996Y-111723869D01* +X184281998Y-111723868D01* +X184288946Y-111721550D01* +X184439348Y-111628478D01* +X184466584Y-111601195D01* +X184559134Y-111508483D01* +X184564305Y-111503303D01* +X184578199Y-111480763D01* +X184653275Y-111358968D01* +X184653276Y-111358966D01* +X184657115Y-111352738D01* +X184710196Y-111192704D01* +X184710632Y-111191389D01* +X184710632Y-111191387D01* +X184712797Y-111184861D01* +X184713682Y-111176230D01* +X184720860Y-111106166D01* +X184723500Y-111080400D01* +X184723500Y-110454600D01* +X184723131Y-110451045D01* +X184713238Y-110355692D01* +X184713237Y-110355688D01* +X184712526Y-110348834D01* +X184708833Y-110337763D01* +X184658868Y-110188002D01* +X184656550Y-110181054D01* +X184563478Y-110030652D01* +X184522734Y-109989979D01* +X184476537Y-109943862D01* +X184442458Y-109881579D01* +X184447461Y-109810759D01* +X184476382Y-109765671D01* +X184558739Y-109683171D01* +X184567751Y-109671760D01* +X184652816Y-109533757D01* +X184658963Y-109520576D01* +X184710138Y-109366290D01* +X184713005Y-109352914D01* +X184722672Y-109258562D01* +X184723000Y-109252146D01* +X184723000Y-109214615D01* +X184718525Y-109199376D01* +X184717135Y-109198171D01* +X184709452Y-109196500D01* +X183387000Y-109196500D01* +X183318879Y-109176498D01* +X183272386Y-109122842D01* +X183261000Y-109070500D01* +X183261000Y-108670385D01* +X183769000Y-108670385D01* +X183773475Y-108685624D01* +X183774865Y-108686829D01* +X183782548Y-108688500D01* +X184704884Y-108688500D01* +X184720123Y-108684025D01* +X184721328Y-108682635D01* +X184722999Y-108674952D01* +X184722999Y-108632905D01* +X184722662Y-108626386D01* +X184712743Y-108530794D01* +X184709851Y-108517400D01* +X184658412Y-108363216D01* +X184652239Y-108350038D01* +X184566937Y-108212193D01* +X184557901Y-108200792D01* +X184443171Y-108086261D01* +X184431760Y-108077249D01* +X184293757Y-107992184D01* +X184280576Y-107986037D01* +X184126290Y-107934862D01* +X184112914Y-107931995D01* +X184018562Y-107922328D01* +X184012145Y-107922000D01* +X183787115Y-107922000D01* +X183771876Y-107926475D01* +X183770671Y-107927865D01* +X183769000Y-107935548D01* +X183769000Y-108670385D01* +X183261000Y-108670385D01* +X183261000Y-107940116D01* +X183256525Y-107924877D01* +X183255135Y-107923672D01* +X183247452Y-107922001D01* +X183017905Y-107922001D01* +X183011386Y-107922338D01* +X182915794Y-107932257D01* +X182902400Y-107935149D01* +X182748216Y-107986588D01* +X182735038Y-107992761D01* +X182597193Y-108078063D01* +X182585792Y-108087099D01* +X182471261Y-108201829D01* +X182462249Y-108213240D01* +X182377184Y-108351243D01* +X182371038Y-108364422D01* +X182364538Y-108384018D01* +X182324106Y-108442377D01* +X182258541Y-108469613D01* +X182188660Y-108457079D01* +X182136649Y-108408753D01* +X182125421Y-108384224D01* +X182118413Y-108363218D01* +X182112239Y-108350038D01* +X182026937Y-108212193D01* +X182017901Y-108200792D01* +X181903171Y-108086261D01* +X181891760Y-108077249D01* +X181753757Y-107992184D01* +X181740576Y-107986037D01* +X181586290Y-107934862D01* +X181572914Y-107931995D01* +X181478562Y-107922328D01* +X181472145Y-107922000D01* +X181247115Y-107922000D01* +X181231876Y-107926475D01* +X181230671Y-107927865D01* +X181229000Y-107935548D01* +X181229000Y-109070500D01* +X181208998Y-109138621D01* +X181155342Y-109185114D01* +X181103000Y-109196500D01* +X180847000Y-109196500D01* +X180778879Y-109176498D01* +X180732386Y-109122842D01* +X180721000Y-109070500D01* +X180721000Y-107940116D01* +X180716525Y-107924877D01* +X180715135Y-107923672D01* +X180707452Y-107922001D01* +X180477905Y-107922001D01* +X180471386Y-107922338D01* +X180375794Y-107932257D01* +X180362400Y-107935149D01* +X180208216Y-107986588D01* +X180195038Y-107992761D01* +X180057193Y-108078063D01* +X180045792Y-108087099D01* +X179931261Y-108201829D01* +X179922249Y-108213240D01* +X179837184Y-108351243D01* +X179831038Y-108364422D01* +X179824538Y-108384018D01* +X179784106Y-108442377D01* +X179718541Y-108469613D01* +X179648660Y-108457079D01* +X179596649Y-108408753D01* +X179585421Y-108384224D01* +X179578413Y-108363218D01* +X179572239Y-108350038D01* +X179486937Y-108212193D01* +X179477901Y-108200792D01* +X179363171Y-108086261D01* +X179351760Y-108077249D01* +X179213757Y-107992184D01* +X179200576Y-107986037D01* +X179046290Y-107934862D01* +X179032914Y-107931995D01* +X178938562Y-107922328D01* +X178932145Y-107922000D01* +X178707115Y-107922000D01* +X178691876Y-107926475D01* +X178690671Y-107927865D01* +X178689000Y-107935548D01* +X178689000Y-109070500D01* +X178668998Y-109138621D01* +X178615342Y-109185114D01* +X178563000Y-109196500D01* +X177245116Y-109196500D01* +X177229877Y-109200975D01* +X177228672Y-109202365D01* +X177227001Y-109210048D01* +X177227001Y-109252095D01* +X177227338Y-109258614D01* +X177237257Y-109354206D01* +X177240149Y-109367600D01* +X177291588Y-109521784D01* +X177297761Y-109534962D01* +X177383063Y-109672807D01* +X177392099Y-109684208D01* +X177473462Y-109765430D01* +X177507541Y-109827713D01* +X177502538Y-109898533D01* +X177473617Y-109943620D01* +X177390870Y-110026512D01* +X177390866Y-110026517D01* +X177385695Y-110031697D01* +X177381855Y-110037927D01* +X177381854Y-110037928D01* +X177300527Y-110169865D01* +X177292885Y-110182262D01* +X177276936Y-110230348D01* +X177245405Y-110325412D01* +X177237203Y-110350139D01* +X177226500Y-110454600D01* +X177226500Y-111080400D01* +X177226837Y-111083646D01* +X177226837Y-111083650D01* +X177236082Y-111172749D01* +X177237474Y-111186166D01* +X177239655Y-111192702D01* +X177239655Y-111192704D01* +X177252332Y-111230701D01* +X177293450Y-111353946D01* +X177386522Y-111504348D01* +X177391704Y-111509521D01* +X177435247Y-111552988D01* +X177511697Y-111629305D01* +X177517927Y-111633145D01* +X177517928Y-111633146D01* +X177655090Y-111717694D01* +X177662262Y-111722115D01* +X177698589Y-111734164D01* +X177717941Y-111740583D01* +X177776301Y-111781014D01* +X177802542Y-111844182D01* +X177802837Y-111844135D01* +X177803030Y-111845356D01* +X177803538Y-111846578D01* +X177803785Y-111850123D01* +X177804078Y-111851973D01* +X177804327Y-111859889D01* +X177809978Y-111879339D01* +X177813987Y-111898700D01* +X177814459Y-111902432D01* +X177816526Y-111918797D01* +X177819445Y-111926168D01* +X177819445Y-111926170D01* +X177832804Y-111959912D01* +X177836649Y-111971142D01* +X177846771Y-112005983D01* +X177848982Y-112013593D01* +X177853015Y-112020412D01* +X177853017Y-112020417D01* +X177859293Y-112031028D01* +X177867988Y-112048776D01* +X177875448Y-112067617D01* +X177880110Y-112074033D01* +X177880110Y-112074034D01* +X177901436Y-112103387D01* +X177907952Y-112113307D01* +X177926355Y-112144424D01* +X177930458Y-112151362D01* +X177944779Y-112165683D01* +X177957619Y-112180716D01* +X177969528Y-112197107D01* +X178003605Y-112225298D01* +X178012384Y-112233288D01* +X178917594Y-113138498D01* +X178951620Y-113200810D01* +X178954499Y-113227593D01* +X178954499Y-113423499D01* +X178934497Y-113491620D01* +X178880841Y-113538113D01* +X178828499Y-113549499D01* +X178412266Y-113549499D01* +X178408871Y-113549868D01* +X178408867Y-113549868D01* +X178400639Y-113550762D01* +X178387032Y-113551499D01* +X177999594Y-113551499D01* +X177931473Y-113531497D01* +X177910499Y-113514594D01* +X177033652Y-112637747D01* +X177026112Y-112629461D01* +X177022000Y-112622982D01* +X176972348Y-112576356D01* +X176969507Y-112573602D01* +X176949770Y-112553865D01* +X176946573Y-112551385D01* +X176937551Y-112543680D01* +X176905321Y-112513414D01* +X176898375Y-112509595D01* +X176898372Y-112509593D01* +X176887566Y-112503652D01* +X176871047Y-112492801D01* +X176865048Y-112488148D01* +X176855041Y-112480386D01* +X176847772Y-112477241D01* +X176847768Y-112477238D01* +X176814463Y-112462826D01* +X176803813Y-112457609D01* +X176765060Y-112436305D01* +X176745437Y-112431267D01* +X176726734Y-112424863D01* +X176715420Y-112419967D01* +X176715419Y-112419967D01* +X176708145Y-112416819D01* +X176700322Y-112415580D01* +X176700312Y-112415577D01* +X176664476Y-112409901D01* +X176652856Y-112407495D01* +X176617709Y-112398471D01* +X176617705Y-112398470D01* +X176611740Y-112396939D01* +X176610031Y-112396500D01* +X176610102Y-112396224D01* +X176549176Y-112369656D01* +X176510516Y-112312903D01* +X176510244Y-112312086D01* +X176497153Y-112272847D01* +X176493869Y-112263004D01* +X176493868Y-112263002D01* +X176491550Y-112256054D01* +X176398478Y-112105652D01* +X176273303Y-111980695D01* +X176264775Y-111975438D01* +X176128968Y-111891725D01* +X176128966Y-111891724D01* +X176122738Y-111887885D01* +X176011165Y-111850878D01* +X175961389Y-111834368D01* +X175961387Y-111834368D01* +X175954861Y-111832203D01* +X175948025Y-111831503D01* +X175948022Y-111831502D01* +X175904969Y-111827091D01* +X175850400Y-111821500D01* +X175490159Y-111821500D01* +X175422038Y-111801498D01* +X175375545Y-111747842D01* +X175365441Y-111677568D01* +X175381040Y-111632500D01* +X175456223Y-111502279D01* +X175456224Y-111502278D01* +X175459527Y-111496556D01* +X175518542Y-111314928D01* +X175521814Y-111283803D01* +X175537814Y-111131565D01* +X175538504Y-111125000D01* +X175536740Y-111108213D01* +X175519232Y-110941635D01* +X175519232Y-110941633D01* +X175518542Y-110935072D01* +X175459527Y-110753444D01* +X175364040Y-110588056D01* +X175347881Y-110570109D01* +X175240675Y-110451045D01* +X175240674Y-110451044D01* +X175236253Y-110446134D01* +X175102332Y-110348834D01* +X175087094Y-110337763D01* +X175087093Y-110337762D01* +X175081752Y-110333882D01* +X175075724Y-110331198D01* +X175075722Y-110331197D01* +X174913319Y-110258891D01* +X174913318Y-110258891D01* +X174907288Y-110256206D01* +X174794213Y-110232171D01* +X174726944Y-110217872D01* +X174726939Y-110217872D01* +X174720487Y-110216500D01* +X174529513Y-110216500D01* +X174523061Y-110217872D01* +X174523056Y-110217872D01* +X174455787Y-110232171D01* +X174342712Y-110256206D01* +X174336682Y-110258891D01* +X174336681Y-110258891D01* +X174174278Y-110331197D01* +X174174276Y-110331198D01* +X174168248Y-110333882D01* +X174162907Y-110337762D01* +X174162906Y-110337763D01* +X174064125Y-110409532D01* +X174013747Y-110446134D01* +X174009333Y-110451036D01* +X174009331Y-110451038D01* +X174008655Y-110451789D01* +X174008155Y-110452097D01* +X174004420Y-110455460D01* +X174003805Y-110454777D01* +X173948211Y-110489031D01* +X173918976Y-110493419D01* +X173899940Y-110494018D01* +X173898029Y-110494078D01* +X173890110Y-110494327D01* +X173872454Y-110499456D01* +X173870658Y-110499978D01* +X173851306Y-110503986D01* +X173847072Y-110504521D01* +X173831203Y-110506526D01* +X173823834Y-110509443D01* +X173823832Y-110509444D01* +X173790097Y-110522800D01* +X173778869Y-110526645D01* +X173736407Y-110538982D01* +X173729585Y-110543016D01* +X173729579Y-110543019D01* +X173718968Y-110549294D01* +X173701218Y-110557990D01* +X173689756Y-110562528D01* +X173689751Y-110562531D01* +X173682383Y-110565448D01* +X173675968Y-110570109D01* +X173646625Y-110591427D01* +X173636707Y-110597943D01* +X173619748Y-110607973D01* +X173598637Y-110620458D01* +X173584313Y-110634782D01* +X173569283Y-110647620D01* +X173552893Y-110659528D01* +X173536017Y-110679928D01* +X173524712Y-110693593D01* +X173516722Y-110702373D01* +X173473106Y-110745989D01* +X173410794Y-110780015D01* +X173339979Y-110774950D01* +X173283143Y-110732403D01* +X173258332Y-110665883D01* +X173258011Y-110656894D01* +X173258011Y-108670385D01* +X177227000Y-108670385D01* +X177231475Y-108685624D01* +X177232865Y-108686829D01* +X177240548Y-108688500D01* +X178162885Y-108688500D01* +X178178124Y-108684025D01* +X178179329Y-108682635D01* +X178181000Y-108674952D01* +X178181000Y-107940116D01* +X178176525Y-107924877D01* +X178175135Y-107923672D01* +X178167452Y-107922001D01* +X177937905Y-107922001D01* +X177931386Y-107922338D01* +X177835794Y-107932257D01* +X177822400Y-107935149D01* +X177668216Y-107986588D01* +X177655038Y-107992761D01* +X177517193Y-108078063D01* +X177505792Y-108087099D01* +X177391261Y-108201829D01* +X177382249Y-108213240D01* +X177297184Y-108351243D01* +X177291037Y-108364424D01* +X177239862Y-108518710D01* +X177236995Y-108532086D01* +X177227328Y-108626438D01* +X177227000Y-108632855D01* +X177227000Y-108670385D01* +X173258011Y-108670385D01* +X173258011Y-107292095D01* +X187362001Y-107292095D01* +X187362338Y-107298614D01* +X187372257Y-107394206D01* +X187375149Y-107407600D01* +X187426588Y-107561784D01* +X187432761Y-107574962D01* +X187518063Y-107712807D01* +X187527099Y-107724208D01* +X187641829Y-107838739D01* +X187653240Y-107847751D01* +X187791243Y-107932816D01* +X187804424Y-107938963D01* +X187958710Y-107990138D01* +X187972086Y-107993005D01* +X188066438Y-108002672D01* +X188072854Y-108003000D01* +X188322885Y-108003000D01* +X188338124Y-107998525D01* +X188339329Y-107997135D01* +X188341000Y-107989452D01* +X188341000Y-107984884D01* +X188849000Y-107984884D01* +X188853475Y-108000123D01* +X188854865Y-108001328D01* +X188862548Y-108002999D01* +X189117095Y-108002999D01* +X189123614Y-108002662D01* +X189219206Y-107992743D01* +X189232600Y-107989851D01* +X189386784Y-107938412D01* +X189399962Y-107932239D01* +X189537807Y-107846937D01* +X189549208Y-107837901D01* +X189663739Y-107723171D01* +X189672751Y-107711760D01* +X189757816Y-107573757D01* +X189763963Y-107560576D01* +X189815138Y-107406290D01* +X189818005Y-107392914D01* +X189827672Y-107298562D01* +X189828000Y-107292146D01* +X189828000Y-107267115D01* +X189823525Y-107251876D01* +X189822135Y-107250671D01* +X189814452Y-107249000D01* +X188867115Y-107249000D01* +X188851876Y-107253475D01* +X188850671Y-107254865D01* +X188849000Y-107262548D01* +X188849000Y-107984884D01* +X188341000Y-107984884D01* +X188341000Y-107267115D01* +X188336525Y-107251876D01* +X188335135Y-107250671D01* +X188327452Y-107249000D01* +X187380116Y-107249000D01* +X187364877Y-107253475D01* +X187363672Y-107254865D01* +X187362001Y-107262548D01* +X187362001Y-107292095D01* +X173258011Y-107292095D01* +X173258011Y-105395400D01* +X187361500Y-105395400D01* +X187361837Y-105398646D01* +X187361837Y-105398650D01* +X187371752Y-105494206D01* +X187372474Y-105501166D01* +X187374655Y-105507702D01* +X187374655Y-105507704D01* +X187405424Y-105599928D01* +X187428450Y-105668946D01* +X187521522Y-105819348D01* +X187646697Y-105944305D01* +X187651235Y-105947102D01* +X187691824Y-106004353D01* +X187695054Y-106075276D01* +X187659428Y-106136687D01* +X187650932Y-106144062D01* +X187640793Y-106152098D01* +X187526261Y-106266829D01* +X187517249Y-106278240D01* +X187432184Y-106416243D01* +X187426037Y-106429424D01* +X187374862Y-106583710D01* +X187371995Y-106597086D01* +X187362328Y-106691438D01* +X187362000Y-106697855D01* +X187362000Y-106722885D01* +X187366475Y-106738124D01* +X187367865Y-106739329D01* +X187375548Y-106741000D01* +X189809884Y-106741000D01* +X189825123Y-106736525D01* +X189826328Y-106735135D01* +X189827999Y-106727452D01* +X189827999Y-106697905D01* +X189827662Y-106691386D01* +X189817743Y-106595794D01* +X189814851Y-106582400D01* +X189763412Y-106428216D01* +X189757239Y-106415038D01* +X189671937Y-106277193D01* +X189662901Y-106265792D01* +X189565613Y-106168673D01* +X189531534Y-106106390D01* +X189536537Y-106035570D01* +X189579034Y-105978697D01* +X189645533Y-105953829D01* +X189654631Y-105953500D01* +X193456755Y-105953500D01* +X193524876Y-105973502D01* +X193555498Y-106001234D01* +X193617177Y-106079052D01* +X193621871Y-106083047D01* +X193706652Y-106155201D01* +X193760324Y-106200880D01* +X193765702Y-106203886D01* +X193765704Y-106203887D01* +X193816688Y-106232381D01* +X193924409Y-106292584D01* +X194103180Y-106350670D01* +X194289830Y-106372927D01* +X194295965Y-106372455D01* +X194295967Y-106372455D01* +X194471105Y-106358979D01* +X194471109Y-106358978D01* +X194477247Y-106358506D01* +X194612397Y-106320771D01* +X194652350Y-106309616D01* +X194652353Y-106309615D01* +X194658294Y-106307956D01* +X194663798Y-106305176D01* +X194663800Y-106305175D01* +X194820574Y-106225983D01* +X194820576Y-106225982D01* +X194826075Y-106223204D01* +X194974199Y-106107477D01* +X194985088Y-106094862D01* +X195092994Y-105969852D01* +X195092995Y-105969850D01* +X195097023Y-105965184D01* +X195103661Y-105953500D01* +X195140976Y-105887813D01* +X195189870Y-105801744D01* +X195249203Y-105623382D01* +X195272762Y-105436892D01* +X195272957Y-105422957D01* +X195273089Y-105413522D01* +X195273089Y-105413518D01* +X195273138Y-105410000D01* +X195254795Y-105222926D01* +X195252597Y-105215644D01* +X195210078Y-105074817D01* +X195200465Y-105042977D01* +X195112218Y-104877008D01* +X194993415Y-104731340D01* +X194933594Y-104681852D01* +X194853329Y-104615450D01* +X194853324Y-104615447D01* +X194848580Y-104611522D01* +X194843161Y-104608592D01* +X194843158Y-104608590D01* +X194747023Y-104556611D01* +X194683231Y-104522119D01* +X194652951Y-104512746D01* +X194601007Y-104478366D01* +X194599877Y-104479553D01* +X194594935Y-104474847D01* +X194590529Y-104469633D01* +X194585104Y-104465485D01* +X194447769Y-104360484D01* +X194447765Y-104360481D01* +X194442348Y-104356340D01* +X194273296Y-104277510D01* +X194091260Y-104236820D01* +X194085537Y-104236500D01* +X189564100Y-104236500D01* +X189497984Y-104217760D01* +X189398968Y-104156725D01* +X189398966Y-104156724D01* +X189392738Y-104152885D01* +X189292561Y-104119658D01* +X189231389Y-104099368D01* +X189231387Y-104099368D01* +X189224861Y-104097203D01* +X189218025Y-104096503D01* +X189218022Y-104096502D01* +X189174969Y-104092091D01* +X189120400Y-104086500D01* +X188069600Y-104086500D01* +X188066354Y-104086837D01* +X188066350Y-104086837D01* +X187970692Y-104096762D01* +X187970688Y-104096763D01* +X187963834Y-104097474D01* +X187957298Y-104099655D01* +X187957296Y-104099655D01* +X187856046Y-104133435D01* +X187796054Y-104153450D01* +X187645652Y-104246522D01* +X187640479Y-104251704D01* +X187616204Y-104276021D01* +X187520695Y-104371697D01* +X187516855Y-104377927D01* +X187516854Y-104377928D01* +X187440467Y-104501851D01* +X187427885Y-104522262D01* +X187413434Y-104565832D01* +X187374681Y-104682669D01* +X187372203Y-104690139D01* +X187371503Y-104696975D01* +X187371502Y-104696978D01* +X187367492Y-104736114D01* +X187361500Y-104794600D01* +X187361500Y-105395400D01* +X173258011Y-105395400D01* +X173258011Y-103860901D01* +X173258453Y-103850358D01* +X173262244Y-103805210D01* +X173262815Y-103798412D01* +X173259655Y-103774729D01* +X173252074Y-103717909D01* +X173251704Y-103714854D01* +X173248202Y-103682622D01* +X173242928Y-103634074D01* +X173240753Y-103627610D01* +X173240033Y-103624335D01* +X173239963Y-103623939D01* +X173239840Y-103623515D01* +X173239049Y-103620294D01* +X173238145Y-103613522D01* +X173220207Y-103564237D01* +X173215705Y-103493385D01* +X173250224Y-103431345D01* +X173286405Y-103409182D01* +X173285370Y-103406973D01* +X173291998Y-103403868D01* +X173298946Y-103401550D01* +X173449348Y-103308478D01* +X173574305Y-103183303D01* +X173577102Y-103178765D01* +X173634353Y-103138176D01* +X173705276Y-103134946D01* +X173766687Y-103170572D01* +X173774062Y-103179068D01* +X173782098Y-103189207D01* +X173896829Y-103303739D01* +X173908240Y-103312751D01* +X174046243Y-103397816D01* +X174059424Y-103403963D01* +X174213710Y-103455138D01* +X174227086Y-103458005D01* +X174321438Y-103467672D01* +X174327854Y-103468000D01* +X174352885Y-103468000D01* +X174368124Y-103463525D01* +X174369329Y-103462135D01* +X174371000Y-103454452D01* +X174371000Y-103449884D01* +X174879000Y-103449884D01* +X174883475Y-103465123D01* +X174884865Y-103466328D01* +X174892548Y-103467999D01* +X174922095Y-103467999D01* +X174928614Y-103467662D01* +X175024206Y-103457743D01* +X175037600Y-103454851D01* +X175191784Y-103403412D01* +X175204962Y-103397239D01* +X175342807Y-103311937D01* +X175354208Y-103302901D01* +X175468739Y-103188171D01* +X175477751Y-103176760D01* +X175562816Y-103038757D01* +X175568964Y-103025574D01* +X175617838Y-102878224D01* +X175658269Y-102819864D01* +X175723833Y-102792627D01* +X175793715Y-102805161D01* +X175845726Y-102853485D01* +X175856955Y-102878015D01* +X175906588Y-103026784D01* +X175912761Y-103039962D01* +X175998063Y-103177807D01* +X176007099Y-103189208D01* +X176121829Y-103303739D01* +X176133240Y-103312751D01* +X176271243Y-103397816D01* +X176284424Y-103403963D01* +X176438710Y-103455138D01* +X176452086Y-103458005D01* +X176546438Y-103467672D01* +X176552854Y-103468000D01* +X176577885Y-103468000D01* +X176593124Y-103463525D01* +X176594329Y-103462135D01* +X176596000Y-103454452D01* +X176596000Y-101020116D01* +X176591525Y-101004877D01* +X176590135Y-101003672D01* +X176582452Y-101002001D01* +X176552905Y-101002001D01* +X176546386Y-101002338D01* +X176450794Y-101012257D01* +X176437400Y-101015149D01* +X176283216Y-101066588D01* +X176270038Y-101072761D01* +X176132193Y-101158063D01* +X176120792Y-101167099D01* +X176006261Y-101281829D01* +X175997249Y-101293240D01* +X175912184Y-101431243D01* +X175906036Y-101444426D01* +X175857162Y-101591776D01* +X175816731Y-101650136D01* +X175751167Y-101677373D01* +X175681285Y-101664839D01* +X175629274Y-101616515D01* +X175618045Y-101591985D01* +X175568412Y-101443216D01* +X175562239Y-101430038D01* +X175476937Y-101292193D01* +X175467901Y-101280792D01* +X175353171Y-101166261D01* +X175341760Y-101157249D01* +X175203757Y-101072184D01* +X175190576Y-101066037D01* +X175036290Y-101014862D01* +X175022914Y-101011995D01* +X174928562Y-101002328D01* +X174922145Y-101002000D01* +X174897115Y-101002000D01* +X174881876Y-101006475D01* +X174880671Y-101007865D01* +X174879000Y-101015548D01* +X174879000Y-103449884D01* +X174371000Y-103449884D01* +X174371000Y-101020116D01* +X174366525Y-101004877D01* +X174365135Y-101003672D01* +X174357452Y-101002001D01* +X174327905Y-101002001D01* +X174321386Y-101002338D01* +X174225794Y-101012257D01* +X174212400Y-101015149D01* +X174058216Y-101066588D01* +X174045038Y-101072761D01* +X173907193Y-101158063D01* +X173895792Y-101167099D01* +X173781262Y-101281828D01* +X173774206Y-101290762D01* +X173716288Y-101331823D01* +X173645365Y-101335053D01* +X173583954Y-101299426D01* +X173577154Y-101291593D01* +X173573478Y-101285652D01* +X173565432Y-101277620D01* +X173520482Y-101232748D01* +X173486403Y-101170465D01* +X173483500Y-101143575D01* +X173483500Y-100321951D01* +X173503502Y-100253830D01* +X173557158Y-100207337D01* +X173627432Y-100197233D01* +X173644654Y-100200954D01* +X173718605Y-100222439D01* +X173732706Y-100222399D01* +X173736000Y-100215130D01* +X173736000Y-99977342D01* +X173753547Y-99913203D01* +X173779500Y-99869319D01* +X173799145Y-99836101D01* +X173810433Y-99797249D01* +X173825576Y-99745123D01* +X173845562Y-99676331D01* +X173846229Y-99667867D01* +X173848307Y-99641458D01* +X173848307Y-99641450D01* +X173848500Y-99639002D01* +X174131500Y-99639002D01* +X174131693Y-99641450D01* +X174131693Y-99641458D01* +X174133772Y-99667867D01* +X174134438Y-99676331D01* +X174154424Y-99745123D01* +X174169568Y-99797249D01* +X174180855Y-99836101D01* +X174200500Y-99869319D01* +X174226453Y-99913203D01* +X174244000Y-99977342D01* +X174244000Y-100209378D01* +X174247973Y-100222909D01* +X174255871Y-100224044D01* +X174395790Y-100183393D01* +X174414326Y-100175372D01* +X174484788Y-100166676D01* +X174514404Y-100175372D01* +X174519577Y-100177611D01* +X174526399Y-100181645D01* +X174534010Y-100183856D01* +X174534012Y-100183857D01* +X174580054Y-100197233D01* +X174686169Y-100228062D01* +X174692574Y-100228566D01* +X174692579Y-100228567D01* +X174721042Y-100230807D01* +X174721050Y-100230807D01* +X174723498Y-100231000D01* +X175156502Y-100231000D01* +X175158950Y-100230807D01* +X175158958Y-100230807D01* +X175187421Y-100228567D01* +X175187426Y-100228566D01* +X175193831Y-100228062D01* +X175299946Y-100197233D01* +X175345988Y-100183857D01* +X175345990Y-100183856D01* +X175353601Y-100181645D01* +X175449922Y-100124681D01* +X175489980Y-100100991D01* +X175489983Y-100100989D01* +X175496807Y-100096953D01* +X175614453Y-99979307D01* +X175618489Y-99972483D01* +X175618491Y-99972480D01* +X175695108Y-99842927D01* +X175699145Y-99836101D01* +X175710433Y-99797249D01* +X175725576Y-99745123D01* +X175745562Y-99676331D01* +X175746229Y-99667867D01* +X175748307Y-99641458D01* +X175748307Y-99641450D01* +X175748500Y-99639002D01* +X175748500Y-99409500D01* +X175768502Y-99341379D01* +X175822158Y-99294886D01* +X175874500Y-99283500D01* +X176198307Y-99283500D01* +X176237244Y-99289667D01* +X176241681Y-99291109D01* +X176247712Y-99293794D01* +X176254164Y-99295166D01* +X176254169Y-99295167D01* +X176428056Y-99332128D01* +X176428061Y-99332128D01* +X176434513Y-99333500D01* +X176625487Y-99333500D01* +X176631939Y-99332128D01* +X176631944Y-99332128D01* +X176733448Y-99310552D01* +X176812288Y-99293794D01* +X176818319Y-99291109D01* +X176980722Y-99218803D01* +X176980724Y-99218802D01* +X176986752Y-99216118D01* +X177016369Y-99194600D01* +X177048494Y-99171260D01* +X177115362Y-99147401D01* +X177184514Y-99163482D01* +X177233994Y-99214396D01* +X177242079Y-99233321D01* +X177266587Y-99306782D01* +X177272761Y-99319962D01* +X177358063Y-99457807D01* +X177367099Y-99469208D01* +X177481829Y-99583739D01* +X177493240Y-99592751D01* +X177631243Y-99677816D01* +X177644424Y-99683963D01* +X177798710Y-99735138D01* +X177812086Y-99738005D01* +X177906438Y-99747672D01* +X177912854Y-99748000D01* +X178162885Y-99748000D01* +X178178124Y-99743525D01* +X178179329Y-99742135D01* +X178181000Y-99734452D01* +X178181000Y-99729884D01* +X178689000Y-99729884D01* +X178693475Y-99745123D01* +X178694865Y-99746328D01* +X178702548Y-99747999D01* +X178957095Y-99747999D01* +X178963614Y-99747662D01* +X179059206Y-99737743D01* +X179072600Y-99734851D01* +X179226784Y-99683412D01* +X179239962Y-99677239D01* +X179377807Y-99591937D01* +X179389208Y-99582901D01* +X179503739Y-99468171D01* +X179512751Y-99456760D01* +X179597816Y-99318757D01* +X179603963Y-99305576D01* +X179655138Y-99151290D01* +X179658005Y-99137914D01* +X179667672Y-99043562D01* +X179668000Y-99037146D01* +X179668000Y-99012115D01* +X179663525Y-98996876D01* +X179662135Y-98995671D01* +X179654452Y-98994000D01* +X178707115Y-98994000D01* +X178691876Y-98998475D01* +X178690671Y-98999865D01* +X178689000Y-99007548D01* +X178689000Y-99729884D01* +X178181000Y-99729884D01* +X178181000Y-98612000D01* +X178201002Y-98543879D01* +X178254658Y-98497386D01* +X178307000Y-98486000D01* +X179649884Y-98486000D01* +X179665123Y-98481525D01* +X179666328Y-98480135D01* +X179667999Y-98472452D01* +X179667999Y-98442905D01* +X179667662Y-98436386D01* +X179657743Y-98340794D01* +X179654851Y-98327400D01* +X179603412Y-98173216D01* +X179597239Y-98160038D01* +X179511937Y-98022193D01* +X179502901Y-98010792D01* +X179388172Y-97896262D01* +X179379238Y-97889206D01* +X179338177Y-97831288D01* +X179334947Y-97760365D01* +X179370574Y-97698954D01* +X179378407Y-97692154D01* +X179384348Y-97688478D01* +X179509305Y-97563303D01* +X179513680Y-97556206D01* +X179598275Y-97418968D01* +X179598276Y-97418966D01* +X179602115Y-97412738D01* +X179604420Y-97405789D01* +X179609141Y-97391557D01* +X179649573Y-97333198D01* +X179715138Y-97305963D01* +X179779981Y-97316120D01* +X179937177Y-97386108D01* +X179937185Y-97386111D01* +X179943212Y-97388794D01* +X180023167Y-97405789D01* +X180123556Y-97427128D01* +X180123561Y-97427128D01* +X180130013Y-97428500D01* +X180190500Y-97428500D01* +X180258621Y-97448502D01* +X180305114Y-97502158D01* +X180316500Y-97554500D01* +X180316500Y-101275050D01* +X180296498Y-101343171D01* +X180279595Y-101364145D01* +X180104145Y-101539595D01* +X180041833Y-101573621D01* +X180015050Y-101576500D01* +X179829197Y-101576500D01* +X179761076Y-101556498D01* +X179714583Y-101502842D01* +X179709674Y-101490377D01* +X179693867Y-101442998D01* +X179693866Y-101442996D01* +X179691550Y-101436054D01* +X179680158Y-101417644D01* +X179602332Y-101291880D01* +X179598478Y-101285652D01* +X179473303Y-101160695D01* +X179467072Y-101156854D01* +X179328968Y-101071725D01* +X179328966Y-101071724D01* +X179322738Y-101067885D01* +X179199069Y-101026866D01* +X179161389Y-101014368D01* +X179161387Y-101014368D01* +X179154861Y-101012203D01* +X179148025Y-101011503D01* +X179148022Y-101011502D01* +X179104969Y-101007091D01* +X179050400Y-101001500D01* +X178449600Y-101001500D01* +X178446354Y-101001837D01* +X178446350Y-101001837D01* +X178350692Y-101011762D01* +X178350688Y-101011763D01* +X178343834Y-101012474D01* +X178337298Y-101014655D01* +X178337296Y-101014655D01* +X178233735Y-101049206D01* +X178176054Y-101068450D01* +X178025652Y-101161522D01* +X177900695Y-101286697D01* +X177897898Y-101291235D01* +X177840647Y-101331824D01* +X177769724Y-101335054D01* +X177708313Y-101299428D01* +X177700938Y-101290932D01* +X177692902Y-101280793D01* +X177578171Y-101166261D01* +X177566760Y-101157249D01* +X177428757Y-101072184D01* +X177415576Y-101066037D01* +X177261290Y-101014862D01* +X177247914Y-101011995D01* +X177153562Y-101002328D01* +X177147145Y-101002000D01* +X177122115Y-101002000D01* +X177106876Y-101006475D01* +X177105671Y-101007865D01* +X177104000Y-101015548D01* +X177104000Y-103449884D01* +X177108475Y-103465123D01* +X177109865Y-103466328D01* +X177117548Y-103467999D01* +X177147095Y-103467999D01* +X177153614Y-103467662D01* +X177249206Y-103457743D01* +X177262600Y-103454851D01* +X177416784Y-103403412D01* +X177429962Y-103397239D01* +X177567807Y-103311937D01* +X177579208Y-103302901D01* +X177693738Y-103188172D01* +X177700794Y-103179238D01* +X177758712Y-103138177D01* +X177829635Y-103134947D01* +X177891046Y-103170574D01* +X177897846Y-103178407D01* +X177901522Y-103184348D01* +X178026697Y-103309305D01* +X178032927Y-103313145D01* +X178032928Y-103313146D01* +X178170288Y-103397816D01* +X178177262Y-103402115D01* +X178257005Y-103428564D01* +X178338611Y-103455632D01* +X178338613Y-103455632D01* +X178345139Y-103457797D01* +X178351975Y-103458497D01* +X178351978Y-103458498D01* +X178395031Y-103462909D01* +X178449600Y-103468500D01* +X179050400Y-103468500D01* +X179053646Y-103468163D01* +X179053650Y-103468163D01* +X179149308Y-103458238D01* +X179149312Y-103458237D01* +X179156166Y-103457526D01* +X179162702Y-103455345D01* +X179162704Y-103455345D01* +X179314348Y-103404752D01* +X179323946Y-103401550D01* +X179474348Y-103308478D01* +X179599305Y-103183303D01* +X179603338Y-103176760D01* +X179688275Y-103038968D01* +X179688276Y-103038966D01* +X179692115Y-103032738D01* +X179709663Y-102979832D01* +X179750094Y-102921473D01* +X179815658Y-102894236D01* +X179829256Y-102893500D01* +X180257944Y-102893500D01* +X180269800Y-102894059D01* +X180269803Y-102894059D01* +X180277537Y-102895788D01* +X180348369Y-102893562D01* +X180352327Y-102893500D01* +X180381432Y-102893500D01* +X180385832Y-102892944D01* +X180397664Y-102892012D01* +X180443831Y-102890562D01* +X180464421Y-102884580D01* +X180483782Y-102880570D01* +X180490770Y-102879688D01* +X180497204Y-102878875D01* +X180497205Y-102878875D01* +X180505064Y-102877882D01* +X180512429Y-102874966D01* +X180512433Y-102874965D01* +X180548021Y-102860874D01* +X180559231Y-102857035D01* +X180603600Y-102844145D01* +X180622065Y-102833225D01* +X180639805Y-102824534D01* +X180659756Y-102816635D01* +X180697129Y-102789482D01* +X180707048Y-102782967D01* +X180739977Y-102763493D01* +X180739981Y-102763490D01* +X180746807Y-102759453D01* +X180761971Y-102744289D01* +X180777005Y-102731448D01* +X180794357Y-102718841D01* +X180823803Y-102683247D01* +X180831792Y-102674468D01* +X181382605Y-102123655D01* +X181391385Y-102115665D01* +X181391387Y-102115663D01* +X181398080Y-102111416D01* +X181405317Y-102103710D01* +X181446604Y-102059743D01* +X181449359Y-102056901D01* +X181469927Y-102036333D01* +X181472647Y-102032826D01* +X181480353Y-102023804D01* +X181506544Y-101995913D01* +X181511972Y-101990133D01* +X181518404Y-101978433D01* +X181519869Y-101975768D01* +X190510302Y-101975768D01* +X190547554Y-102102342D01* +X190552147Y-102113710D01* +X190642566Y-102286666D01* +X190649282Y-102296928D01* +X190771568Y-102449020D01* +X190780152Y-102457786D01* +X190929656Y-102583236D01* +X190939767Y-102590160D01* +X191110798Y-102684184D01* +X191122062Y-102689012D01* +X191308095Y-102748025D01* +X191320084Y-102750573D01* +X191471947Y-102767607D01* +X191478971Y-102768000D01* +X191562885Y-102768000D01* +X191578124Y-102763525D01* +X191579329Y-102762135D01* +X191581000Y-102754452D01* +X191581000Y-102749885D01* +X192089000Y-102749885D01* +X192093475Y-102765124D01* +X192094865Y-102766329D01* +X192102548Y-102768000D01* +X192184124Y-102768000D01* +X192190272Y-102767699D01* +X192335361Y-102753473D01* +X192347396Y-102751090D01* +X192534223Y-102694683D01* +X192545565Y-102690008D01* +X192717879Y-102598388D01* +X192728095Y-102591601D01* +X192879335Y-102468253D01* +X192888039Y-102459609D01* +X193012438Y-102309237D01* +X193019297Y-102299069D01* +X193112121Y-102127393D01* +X193116871Y-102116093D01* +X193158595Y-101981307D01* +X193158801Y-101967205D01* +X193155772Y-101965768D01* +X194310302Y-101965768D01* +X194347554Y-102092342D01* +X194352147Y-102103710D01* +X194442566Y-102276666D01* +X194449282Y-102286928D01* +X194571568Y-102439020D01* +X194580152Y-102447786D01* +X194729656Y-102573236D01* +X194739767Y-102580160D01* +X194910798Y-102674184D01* +X194922062Y-102679012D01* +X195108095Y-102738025D01* +X195120084Y-102740573D01* +X195271947Y-102757607D01* +X195278971Y-102758000D01* +X195362885Y-102758000D01* +X195378124Y-102753525D01* +X195379329Y-102752135D01* +X195381000Y-102744452D01* +X195381000Y-102739885D01* +X195889000Y-102739885D01* +X195893475Y-102755124D01* +X195894865Y-102756329D01* +X195902548Y-102758000D01* +X195984124Y-102758000D01* +X195990272Y-102757699D01* +X196135361Y-102743473D01* +X196147396Y-102741090D01* +X196334223Y-102684683D01* +X196345565Y-102680008D01* +X196517879Y-102588388D01* +X196528095Y-102581601D01* +X196679335Y-102458253D01* +X196688039Y-102449609D01* +X196812438Y-102299237D01* +X196819297Y-102289069D01* +X196912121Y-102117393D01* +X196916871Y-102106093D01* +X196958595Y-101971307D01* +X196958801Y-101957205D01* +X196952045Y-101954000D01* +X195907115Y-101954000D01* +X195891876Y-101958475D01* +X195890671Y-101959865D01* +X195889000Y-101967548D01* +X195889000Y-102739885D01* +X195381000Y-102739885D01* +X195381000Y-101972115D01* +X195376525Y-101956876D01* +X195375135Y-101955671D01* +X195367452Y-101954000D01* +X194324953Y-101954000D01* +X194311422Y-101957973D01* +X194310302Y-101965768D01* +X193155772Y-101965768D01* +X193152045Y-101964000D01* +X192107115Y-101964000D01* +X192091876Y-101968475D01* +X192090671Y-101969865D01* +X192089000Y-101977548D01* +X192089000Y-102749885D01* +X191581000Y-102749885D01* +X191581000Y-101982115D01* +X191576525Y-101966876D01* +X191575135Y-101965671D01* +X191567452Y-101964000D01* +X190524953Y-101964000D01* +X190511422Y-101967973D01* +X190510302Y-101975768D01* +X181519869Y-101975768D01* +X181522303Y-101971342D01* +X181533157Y-101954818D01* +X181541445Y-101944132D01* +X181546304Y-101937868D01* +X181552999Y-101922397D01* +X181564654Y-101895465D01* +X181569876Y-101884805D01* +X181588305Y-101851284D01* +X181588306Y-101851282D01* +X181592124Y-101844337D01* +X181597459Y-101823559D01* +X181603858Y-101804869D01* +X181612380Y-101785176D01* +X181619606Y-101739552D01* +X181622013Y-101727929D01* +X181630386Y-101695316D01* +X181633500Y-101683188D01* +X181633500Y-101661741D01* +X181635051Y-101642031D01* +X181637166Y-101628677D01* +X181638406Y-101620848D01* +X181634059Y-101574859D01* +X181633500Y-101563004D01* +X181633500Y-101452795D01* +X190511199Y-101452795D01* +X190517955Y-101456000D01* +X191562885Y-101456000D01* +X191578124Y-101451525D01* +X191579329Y-101450135D01* +X191581000Y-101442452D01* +X191581000Y-101437885D01* +X192089000Y-101437885D01* +X192093475Y-101453124D01* +X192094865Y-101454329D01* +X192102548Y-101456000D01* +X193145047Y-101456000D01* +X193158578Y-101452027D01* +X193159698Y-101444232D01* +X193159275Y-101442795D01* +X194311199Y-101442795D01* +X194317955Y-101446000D01* +X195362885Y-101446000D01* +X195378124Y-101441525D01* +X195379329Y-101440135D01* +X195381000Y-101432452D01* +X195381000Y-101427885D01* +X195889000Y-101427885D01* +X195893475Y-101443124D01* +X195894865Y-101444329D01* +X195902548Y-101446000D01* +X196945047Y-101446000D01* +X196958578Y-101442027D01* +X196959698Y-101434232D01* +X196922446Y-101307658D01* +X196917853Y-101296290D01* +X196827434Y-101123334D01* +X196820718Y-101113072D01* +X196698432Y-100960980D01* +X196689848Y-100952214D01* +X196540344Y-100826764D01* +X196530233Y-100819840D01* +X196359202Y-100725816D01* +X196347938Y-100720988D01* +X196161905Y-100661975D01* +X196149916Y-100659427D01* +X195998053Y-100642393D01* +X195991029Y-100642000D01* +X195907115Y-100642000D01* +X195891876Y-100646475D01* +X195890671Y-100647865D01* +X195889000Y-100655548D01* +X195889000Y-101427885D01* +X195381000Y-101427885D01* +X195381000Y-100660115D01* +X195376525Y-100644876D01* +X195375135Y-100643671D01* +X195367452Y-100642000D01* +X195285876Y-100642000D01* +X195279728Y-100642301D01* +X195134639Y-100656527D01* +X195122604Y-100658910D01* +X194935777Y-100715317D01* +X194924435Y-100719992D01* +X194752121Y-100811612D01* +X194741905Y-100818399D01* +X194590665Y-100941747D01* +X194581961Y-100950391D01* +X194457562Y-101100763D01* +X194450703Y-101110931D01* +X194357879Y-101282607D01* +X194353129Y-101293907D01* +X194311405Y-101428693D01* +X194311199Y-101442795D01* +X193159275Y-101442795D01* +X193122446Y-101317658D01* +X193117853Y-101306290D01* +X193027434Y-101133334D01* +X193020718Y-101123072D01* +X192898432Y-100970980D01* +X192889848Y-100962214D01* +X192740344Y-100836764D01* +X192730233Y-100829840D01* +X192559202Y-100735816D01* +X192547938Y-100730988D01* +X192361905Y-100671975D01* +X192349916Y-100669427D01* +X192198053Y-100652393D01* +X192191029Y-100652000D01* +X192107115Y-100652000D01* +X192091876Y-100656475D01* +X192090671Y-100657865D01* +X192089000Y-100665548D01* +X192089000Y-101437885D01* +X191581000Y-101437885D01* +X191581000Y-100670115D01* +X191576525Y-100654876D01* +X191575135Y-100653671D01* +X191567452Y-100652000D01* +X191485876Y-100652000D01* +X191479728Y-100652301D01* +X191334639Y-100666527D01* +X191322604Y-100668910D01* +X191135777Y-100725317D01* +X191124435Y-100729992D01* +X190952121Y-100821612D01* +X190941905Y-100828399D01* +X190790665Y-100951747D01* +X190781961Y-100960391D01* +X190657562Y-101110763D01* +X190650703Y-101120931D01* +X190557879Y-101292607D01* +X190553129Y-101303907D01* +X190511405Y-101438693D01* +X190511199Y-101452795D01* +X181633500Y-101452795D01* +X181633500Y-95967060D01* +X181634059Y-95955203D01* +X181635789Y-95947463D01* +X181635076Y-95924759D01* +X181633562Y-95876599D01* +X181633500Y-95872641D01* +X181633500Y-95843568D01* +X181632947Y-95839189D01* +X181632014Y-95827346D01* +X181631811Y-95820862D01* +X181630563Y-95781169D01* +X181624579Y-95760571D01* +X181620571Y-95741218D01* +X181620132Y-95737743D01* +X181617882Y-95719936D01* +X181612756Y-95706988D01* +X181600875Y-95676982D01* +X181597029Y-95665747D01* +X181586358Y-95629016D01* +X181586357Y-95629013D01* +X181584145Y-95621400D01* +X181573225Y-95602935D01* +X181564534Y-95585195D01* +X181556635Y-95565244D01* +X181529482Y-95527871D01* +X181522967Y-95517952D01* +X181503493Y-95485023D01* +X181503490Y-95485019D01* +X181499453Y-95478193D01* +X181484289Y-95463029D01* +X181471448Y-95447995D01* +X181463501Y-95437057D01* +X181458841Y-95430643D01* +X181423247Y-95401197D01* +X181414468Y-95393208D01* +X181282970Y-95261710D01* +X181248944Y-95199398D01* +X181246755Y-95185786D01* +X181234232Y-95066636D01* +X181234232Y-95066635D01* +X181233542Y-95060072D01* +X181174527Y-94878444D01* +X181079040Y-94713056D01* +X180951253Y-94571134D01* +X180852157Y-94499136D01* +X180802094Y-94462763D01* +X180802093Y-94462762D01* +X180796752Y-94458882D01* +X180790724Y-94456198D01* +X180790722Y-94456197D01* +X180628319Y-94383891D01* +X180628318Y-94383891D01* +X180622288Y-94381206D01* +X180528888Y-94361353D01* +X180441944Y-94342872D01* +X180441939Y-94342872D01* +X180435487Y-94341500D01* +X180244513Y-94341500D01* +X180238061Y-94342872D01* +X180238056Y-94342872D01* +X180151112Y-94361353D01* +X180057712Y-94381206D01* +X180051682Y-94383891D01* +X180051681Y-94383891D01* +X179889278Y-94456197D01* +X179889276Y-94456198D01* +X179883248Y-94458882D01* +X179877907Y-94462762D01* +X179877906Y-94462763D01* +X179827843Y-94499136D01* +X179728747Y-94571134D01* +X179600960Y-94713056D01* +X179505473Y-94878444D01* +X179446458Y-95060072D01* +X179445768Y-95066633D01* +X179445768Y-95066635D01* +X179436355Y-95156198D01* +X179426496Y-95250000D01* +X179427186Y-95256565D01* +X179443952Y-95416081D01* +X179446458Y-95439928D01* +X179497353Y-95596566D01* +X179499381Y-95667531D01* +X179462719Y-95728329D01* +X179399006Y-95759654D01* +X179377520Y-95761500D01* +X178822063Y-95761500D01* +X178803114Y-95760067D01* +X178800399Y-95759654D01* +X178781651Y-95756802D01* +X178774359Y-95757395D01* +X178774356Y-95757395D01* +X178728991Y-95761085D01* +X178718777Y-95761500D01* +X178710707Y-95761500D01* +X178707087Y-95761922D01* +X178707069Y-95761923D01* +X178682461Y-95764792D01* +X178678100Y-95765224D01* +X178652981Y-95767267D01* +X178612661Y-95770546D01* +X178612658Y-95770547D01* +X178605363Y-95771140D01* +X178598399Y-95773396D01* +X178592440Y-95774587D01* +X178586585Y-95775971D01* +X178579319Y-95776818D01* +X178510673Y-95801735D01* +X178506545Y-95803152D01* +X178437970Y-95825367D01* +X178399139Y-95831500D01* +X177909600Y-95831500D01* +X177906354Y-95831837D01* +X177906350Y-95831837D01* +X177810692Y-95841762D01* +X177810688Y-95841763D01* +X177803834Y-95842474D01* +X177797298Y-95844655D01* +X177797296Y-95844655D01* +X177701549Y-95876599D01* +X177636054Y-95898450D01* +X177485652Y-95991522D01* +X177480484Y-95996699D01* +X177477269Y-95999247D01* +X177411458Y-96025883D01* +X177399007Y-96026500D01* +X175781423Y-96026500D01* +X175713302Y-96006498D01* +X175672970Y-95964640D01* +X175614453Y-95865693D01* +X175496807Y-95748047D01* +X175489983Y-95744011D01* +X175489980Y-95744009D01* +X175360427Y-95667392D01* +X175360428Y-95667392D01* +X175353601Y-95663355D01* +X175345990Y-95661144D01* +X175345988Y-95661143D01* +X175239486Y-95630202D01* +X175193831Y-95616938D01* +X175187426Y-95616434D01* +X175187421Y-95616433D01* +X175158958Y-95614193D01* +X175158950Y-95614193D01* +X175156502Y-95614000D01* +X174723498Y-95614000D01* +X174721050Y-95614193D01* +X174721042Y-95614193D01* +X174692579Y-95616433D01* +X174692574Y-95616434D01* +X174686169Y-95616938D01* +X174640514Y-95630202D01* +X174534012Y-95661143D01* +X174534010Y-95661144D01* +X174526399Y-95663355D01* +X174519572Y-95667392D01* +X174519573Y-95667392D01* +X174390020Y-95744009D01* +X174390017Y-95744011D01* +X174383193Y-95748047D01* +X174265547Y-95865693D01* +X174261511Y-95872517D01* +X174261509Y-95872520D01* +X174211482Y-95957111D01* +X174180855Y-96008899D01* +X174178644Y-96016510D01* +X174178643Y-96016512D01* +X174164876Y-96063901D01* +X174134438Y-96168669D01* +X174133934Y-96175074D01* +X174133933Y-96175079D01* +X174131693Y-96203542D01* +X174131500Y-96205998D01* +X174131500Y-97364002D01* +X174131693Y-97366450D01* +X174131693Y-97366458D01* +X174133669Y-97391557D01* +X174134438Y-97401331D01* +X174151619Y-97460468D01* +X174173563Y-97536000D01* +X174180855Y-97561101D01* +X174265547Y-97704307D01* +X174271156Y-97709916D01* +X174275399Y-97715386D01* +X174301346Y-97781471D01* +X174287445Y-97851094D01* +X174249554Y-97892616D01* +X174244000Y-97904870D01* +X174244000Y-98142658D01* +X174226453Y-98206797D01* +X174221768Y-98214719D01* +X174180855Y-98283899D01* +X174178644Y-98291510D01* +X174178643Y-98291512D01* +X174172074Y-98314124D01* +X174134438Y-98443669D01* +X174133934Y-98450074D01* +X174133933Y-98450079D01* +X174131693Y-98478542D01* +X174131500Y-98480998D01* +X174131500Y-99639002D01* +X173848500Y-99639002D01* +X173848500Y-98480998D01* +X173848307Y-98478542D01* +X173846067Y-98450079D01* +X173846066Y-98450074D01* +X173845562Y-98443669D01* +X173807926Y-98314124D01* +X173801357Y-98291512D01* +X173801356Y-98291510D01* +X173799145Y-98283899D01* +X173758232Y-98214719D01* +X173753547Y-98206797D01* +X173736000Y-98142658D01* +X173736000Y-97910622D01* +X173731526Y-97895384D01* +X173722118Y-97887232D01* +X173683734Y-97827506D01* +X173683734Y-97756510D01* +X173705071Y-97714780D01* +X173708845Y-97709915D01* +X173714453Y-97704307D01* +X173718489Y-97697483D01* +X173718491Y-97697480D01* +X173795108Y-97567927D01* +X173799145Y-97561101D01* +X173806438Y-97536000D01* +X173828381Y-97460468D01* +X173845562Y-97401331D01* +X173846332Y-97391557D01* +X173848307Y-97366458D01* +X173848307Y-97366450D01* +X173848500Y-97364002D01* +X173848500Y-96205998D01* +X173848307Y-96203542D01* +X173846067Y-96175079D01* +X173846066Y-96175074D01* +X173845562Y-96168669D01* +X173815124Y-96063901D01* +X173801357Y-96016512D01* +X173801356Y-96016510D01* +X173799145Y-96008899D01* +X173768518Y-95957111D01* +X173718491Y-95872520D01* +X173718489Y-95872517D01* +X173714453Y-95865693D01* +X173596807Y-95748047D01* +X173589983Y-95744011D01* +X173589980Y-95744009D01* +X173460427Y-95667392D01* +X173460428Y-95667392D01* +X173453601Y-95663355D01* +X173445990Y-95661144D01* +X173445988Y-95661143D01* +X173339486Y-95630202D01* +X173293831Y-95616938D01* +X173287426Y-95616434D01* +X173287421Y-95616433D01* +X173258958Y-95614193D01* +X173258950Y-95614193D01* +X173256502Y-95614000D01* +X172823498Y-95614000D01* +X172821050Y-95614193D01* +X172821042Y-95614193D01* +X172792579Y-95616433D01* +X172792574Y-95616434D01* +X172786169Y-95616938D01* +X172740514Y-95630202D01* +X172634012Y-95661143D01* +X172634010Y-95661144D01* +X172626399Y-95663355D01* +X172619572Y-95667392D01* +X172619573Y-95667392D01* +X172530138Y-95720284D01* +X172483193Y-95748047D01* +X172482711Y-95748529D01* +X172419631Y-95773297D01* +X172350008Y-95759398D01* +X172298952Y-95710065D01* +X172282672Y-95640960D01* +X172288654Y-95608855D01* +X172336762Y-95460794D01* +X172343542Y-95439928D01* +X172346049Y-95416081D01* +X172362814Y-95256565D01* +X172363504Y-95250000D01* +X172353645Y-95156198D01* +X172344232Y-95066635D01* +X172344232Y-95066633D01* +X172343542Y-95060072D01* +X172284527Y-94878444D01* +X172189040Y-94713056D01* +X172061253Y-94571134D01* +X171962157Y-94499136D01* +X171912094Y-94462763D01* +X171912093Y-94462762D01* +X171906752Y-94458882D01* +X171900724Y-94456198D01* +X171900722Y-94456197D01* +X171738319Y-94383891D01* +X171738318Y-94383891D01* +X171732288Y-94381206D01* +X171638888Y-94361353D01* +X171551944Y-94342872D01* +X171551939Y-94342872D01* +X171545487Y-94341500D01* +X171354513Y-94341500D01* +X171348061Y-94342872D01* +X171348056Y-94342872D01* +X171261112Y-94361353D01* +X171167712Y-94381206D01* +X171161682Y-94383891D01* +X171161681Y-94383891D01* +X170999278Y-94456197D01* +X170999276Y-94456198D01* +X170993248Y-94458882D01* +X170987907Y-94462762D01* +X170987906Y-94462763D01* +X170937843Y-94499136D01* +X170838747Y-94571134D01* +X170710960Y-94713056D01* +X170615473Y-94878444D01* +X170556458Y-95060072D01* +X170555768Y-95066633D01* +X170555768Y-95066635D01* +X170546355Y-95156198D01* +X170536496Y-95250000D01* +X170537186Y-95256565D01* +X170553952Y-95416081D01* +X170556458Y-95439928D01* +X170615473Y-95621556D01* +X170618776Y-95627278D01* +X170618777Y-95627279D01* +X170632591Y-95651206D01* +X170710960Y-95786944D01* +X170715378Y-95791851D01* +X170715379Y-95791852D01* +X170759136Y-95840449D01* +X170789854Y-95904456D01* +X170791500Y-95924759D01* +X170791500Y-96167013D01* +X170771498Y-96235134D01* +X170717842Y-96281627D01* +X170647568Y-96291731D01* +X170582988Y-96262237D01* +X170576482Y-96256186D01* +X170569250Y-96248966D01* +X170468303Y-96148195D01* +X170447648Y-96135463D01* +X170323968Y-96059225D01* +X170323966Y-96059224D01* +X170317738Y-96055385D01* +X170228792Y-96025883D01* +X170156389Y-96001868D01* +X170156387Y-96001868D01* +X170149861Y-95999703D01* +X170143025Y-95999003D01* +X170143022Y-95999002D01* +X170091506Y-95993724D01* +X170045400Y-95989000D01* +X169044600Y-95989000D01* +X169041360Y-95989336D01* +X169041016Y-95989354D01* +X168971952Y-95972902D01* +X168922746Y-95921722D01* +X168908500Y-95863523D01* +X168908500Y-93977793D01* +X168928502Y-93909672D01* +X168945405Y-93888697D01* +X169228699Y-93605404D01* +X169291011Y-93571379D01* +X169317794Y-93568500D01* +X169718495Y-93568500D01* +X169779966Y-93584512D01* +X169794409Y-93592584D01* +X169973180Y-93650670D01* +X170159830Y-93672927D01* +X170165965Y-93672455D01* +X170165967Y-93672455D01* +X170341105Y-93658979D01* +X170341109Y-93658978D01* +X170347247Y-93658506D01* +X170440614Y-93632437D01* +X170522350Y-93609616D01* +X170522353Y-93609615D01* +X170528294Y-93607956D01* +X170533798Y-93605176D01* +X170533800Y-93605175D01* +X170690574Y-93525983D01* +X170690576Y-93525982D01* +X170696075Y-93523204D01* +X170731906Y-93495210D01* +X170797897Y-93469033D01* +X170809477Y-93468500D01* +X171200430Y-93468500D01* +X171219380Y-93469933D01* +X171233615Y-93472099D01* +X171233619Y-93472099D01* +X171240849Y-93473199D01* +X171248141Y-93472606D01* +X171248144Y-93472606D01* +X171293518Y-93468915D01* +X171303733Y-93468500D01* +X171311793Y-93468500D01* +X171325083Y-93466951D01* +X171340007Y-93465211D01* +X171344382Y-93464778D01* +X171409839Y-93459454D01* +X171409842Y-93459453D01* +X171417137Y-93458860D01* +X171424101Y-93456604D01* +X171430060Y-93455413D01* +X171435915Y-93454029D01* +X171443181Y-93453182D01* +X171511827Y-93428265D01* +X171515955Y-93426848D01* +X171578436Y-93406607D01* +X171578438Y-93406606D01* +X171585399Y-93404351D01* +X171591654Y-93400555D01* +X171597128Y-93398049D01* +X171602558Y-93395330D01* +X171609437Y-93392833D01* +X171628393Y-93380405D01* +X171670476Y-93352814D01* +X171674180Y-93350477D01* +X171736607Y-93312595D01* +X171744984Y-93305197D01* +X171745008Y-93305224D01* +X171748000Y-93302571D01* +X171751233Y-93299868D01* +X171757352Y-93295856D01* +X171810628Y-93239617D01* +X171813006Y-93237175D01* +X172207276Y-92842905D01* +X172269588Y-92808879D01* +X172296371Y-92806000D01* +X172705400Y-92806000D01* +X172708646Y-92805663D01* +X172708650Y-92805663D01* +X172804308Y-92795738D01* +X172804312Y-92795737D01* +X172811166Y-92795026D01* +X172817702Y-92792845D01* +X172817704Y-92792845D01* +X172971998Y-92741368D01* +X172978946Y-92739050D01* +X173129348Y-92645978D01* +X173254305Y-92520803D01* +X173257102Y-92516265D01* +X173314353Y-92475676D01* +X173385276Y-92472446D01* +X173446687Y-92508072D01* +X173454062Y-92516568D01* +X173462098Y-92526707D01* +X173576829Y-92641239D01* +X173588240Y-92650251D01* +X173726243Y-92735316D01* +X173739424Y-92741463D01* +X173893710Y-92792638D01* +X173907086Y-92795505D01* +X174001438Y-92805172D01* +X174007854Y-92805500D01* +X174032885Y-92805500D01* +X174048124Y-92801025D01* +X174049329Y-92799635D01* +X174051000Y-92791952D01* +X174051000Y-92787384D01* +X174559000Y-92787384D01* +X174563475Y-92802623D01* +X174564865Y-92803828D01* +X174572548Y-92805499D01* +X174602095Y-92805499D01* +X174608614Y-92805162D01* +X174704206Y-92795243D01* +X174717600Y-92792351D01* +X174871784Y-92740912D01* +X174884962Y-92734739D01* +X175022807Y-92649437D01* +X175034208Y-92640401D01* +X175148739Y-92525671D01* +X175157751Y-92514260D01* +X175242816Y-92376257D01* +X175248963Y-92363076D01* +X175300138Y-92208790D01* +X175303005Y-92195414D01* +X175312672Y-92101062D01* +X175313000Y-92094646D01* +X175313000Y-91844615D01* +X175308525Y-91829376D01* +X175307135Y-91828171D01* +X175299452Y-91826500D01* +X174577115Y-91826500D01* +X174561876Y-91830975D01* +X174560671Y-91832365D01* +X174559000Y-91840048D01* +X174559000Y-92787384D01* +X174051000Y-92787384D01* +X174051000Y-91300385D01* +X174559000Y-91300385D01* +X174563475Y-91315624D01* +X174564865Y-91316829D01* +X174572548Y-91318500D01* +X175294884Y-91318500D01* +X175310123Y-91314025D01* +X175311328Y-91312635D01* +X175312999Y-91304952D01* +X175312999Y-91050405D01* +X175312662Y-91043886D01* +X175302743Y-90948294D01* +X175299851Y-90934900D01* +X175248412Y-90780716D01* +X175242239Y-90767538D01* +X175156937Y-90629693D01* +X175147901Y-90618292D01* +X175033171Y-90503761D01* +X175021760Y-90494749D01* +X174883757Y-90409684D01* +X174870576Y-90403537D01* +X174716290Y-90352362D01* +X174702914Y-90349495D01* +X174608562Y-90339828D01* +X174602145Y-90339500D01* +X174577115Y-90339500D01* +X174561876Y-90343975D01* +X174560671Y-90345365D01* +X174559000Y-90353048D01* +X174559000Y-91300385D01* +X174051000Y-91300385D01* +X174051000Y-90357616D01* +X174046525Y-90342377D01* +X174045135Y-90341172D01* +X174037452Y-90339501D01* +X174007905Y-90339501D01* +X174001386Y-90339838D01* +X173905794Y-90349757D01* +X173892400Y-90352649D01* +X173738216Y-90404088D01* +X173725038Y-90410261D01* +X173587193Y-90495563D01* +X173575792Y-90504599D01* +X173461262Y-90619328D01* +X173454206Y-90628262D01* +X173396288Y-90669323D01* +X173325365Y-90672553D01* +X173263954Y-90636926D01* +X173257154Y-90629093D01* +X173253478Y-90623152D01* +X173128303Y-90498195D01* +X172987209Y-90411223D01* +X172983968Y-90409225D01* +X172983966Y-90409224D01* +X172977738Y-90405385D01* +X172897995Y-90378936D01* +X172816389Y-90351868D01* +X172816387Y-90351868D01* +X172809861Y-90349703D01* +X172803025Y-90349003D01* +X172803022Y-90349002D01* +X172759969Y-90344591D01* +X172705400Y-90339000D01* +X172104600Y-90339000D01* +X172101354Y-90339337D01* +X172101350Y-90339337D01* +X172005692Y-90349262D01* +X172005688Y-90349263D01* +X171998834Y-90349974D01* +X171992298Y-90352155D01* +X171992296Y-90352155D01* +X171860194Y-90396228D01* +X171831054Y-90405950D01* +X171824822Y-90409806D01* +X171824823Y-90409806D01* +X171730803Y-90467987D01* +X171662351Y-90486825D01* +X171594581Y-90465664D01* +X171549010Y-90411223D01* +X171538500Y-90360843D01* +X171538500Y-89518856D01* +X179096601Y-89518856D01* +X179103059Y-89528216D01* +X179119361Y-89542512D01* +X179125901Y-89547530D01* +X179365144Y-89707387D01* +X179372281Y-89711508D01* +X179630349Y-89838772D01* +X179637953Y-89841922D01* +X179910420Y-89934412D01* +X179918383Y-89936546D01* +X180200600Y-89992683D01* +X180208751Y-89993756D01* +X180495881Y-90012575D01* +X180504119Y-90012575D01* +X180791249Y-89993756D01* +X180799400Y-89992683D01* +X181081617Y-89936546D01* +X181089580Y-89934412D01* +X181362047Y-89841922D01* +X181369651Y-89838772D01* +X181627719Y-89711508D01* +X181634856Y-89707387D01* +X181774477Y-89614095D01* +X183704001Y-89614095D01* +X183704338Y-89620614D01* +X183714257Y-89716206D01* +X183717149Y-89729600D01* +X183768588Y-89883784D01* +X183774761Y-89896962D01* +X183860063Y-90034807D01* +X183869099Y-90046208D01* +X183983829Y-90160739D01* +X183995240Y-90169751D01* +X184133243Y-90254816D01* +X184146424Y-90260963D01* +X184300710Y-90312138D01* +X184314086Y-90315005D01* +X184408438Y-90324672D01* +X184414854Y-90325000D01* +X184639885Y-90325000D01* +X184655124Y-90320525D01* +X184656329Y-90319135D01* +X184658000Y-90311452D01* +X184658000Y-90306884D01* +X185166000Y-90306884D01* +X185170475Y-90322123D01* +X185171865Y-90323328D01* +X185179548Y-90324999D01* +X185409095Y-90324999D01* +X185415614Y-90324662D01* +X185511206Y-90314743D01* +X185524600Y-90311851D01* +X185678784Y-90260412D01* +X185691962Y-90254239D01* +X185829807Y-90168937D01* +X185841208Y-90159901D01* +X185955739Y-90045171D01* +X185964751Y-90033760D01* +X186049816Y-89895757D01* +X186055963Y-89882576D01* +X186107138Y-89728290D01* +X186110005Y-89714914D01* +X186119672Y-89620562D01* +X186120000Y-89614146D01* +X186120000Y-89576615D01* +X186115525Y-89561376D01* +X186114135Y-89560171D01* +X186106452Y-89558500D01* +X185184115Y-89558500D01* +X185168876Y-89562975D01* +X185167671Y-89564365D01* +X185166000Y-89572048D01* +X185166000Y-90306884D01* +X184658000Y-90306884D01* +X184658000Y-89576615D01* +X184653525Y-89561376D01* +X184652135Y-89560171D01* +X184644452Y-89558500D01* +X183722116Y-89558500D01* +X183706877Y-89562975D01* +X183705672Y-89564365D01* +X183704001Y-89572048D01* +X183704001Y-89614095D01* +X181774477Y-89614095D01* +X181874099Y-89547530D01* +X181880639Y-89542512D01* +X181895074Y-89529853D01* +X181903472Y-89516614D01* +X181897638Y-89506849D01* +X180512810Y-88122020D01* +X180498869Y-88114408D01* +X180497034Y-88114539D01* +X180490420Y-88118790D01* +X179104116Y-89505095D01* +X179096601Y-89518856D01* +X171538500Y-89518856D01* +X171538500Y-89318099D01* +X171558502Y-89249978D01* +X171612158Y-89203485D01* +X171629347Y-89197102D01* +X171760988Y-89158857D01* +X171760990Y-89158856D01* +X171768601Y-89156645D01* +X171862918Y-89100866D01* +X171904980Y-89075991D01* +X171904983Y-89075989D01* +X171911807Y-89071953D01* +X172029453Y-88954307D01* +X172033489Y-88947483D01* +X172033491Y-88947480D01* +X172110108Y-88817927D01* +X172114145Y-88811101D01* +X172116806Y-88801944D01* +X172131528Y-88751269D01* +X172160562Y-88651331D01* +X172161067Y-88644919D01* +X172162225Y-88638578D01* +X172164105Y-88638921D01* +X172186157Y-88581063D01* +X172243295Y-88538924D01* +X172314145Y-88534365D01* +X172375417Y-88568107D01* +X172380202Y-88574343D01* +X172386748Y-88579366D01* +X172481338Y-88651948D01* +X172488513Y-88657454D01* +X172496139Y-88660613D01* +X172496141Y-88660614D01* +X172607014Y-88706539D01* +X172607017Y-88706540D01* +X172614644Y-88709699D01* +X172750000Y-88727519D01* +X172758188Y-88726441D01* +X172877168Y-88710777D01* +X172885356Y-88709699D01* +X172892983Y-88706540D01* +X172892986Y-88706539D01* +X172961879Y-88678002D01* +X173011487Y-88657454D01* +X173018041Y-88652425D01* +X173018867Y-88651948D01* +X173087863Y-88635210D01* +X173154955Y-88658430D01* +X173190986Y-88698065D01* +X173250960Y-88801944D01* +X173255378Y-88806851D01* +X173255379Y-88806852D01* +X173333339Y-88893435D01* +X173378747Y-88943866D01* +X173393092Y-88954288D01* +X173525516Y-89050500D01* +X173533248Y-89056118D01* +X173539276Y-89058802D01* +X173539278Y-89058803D01* +X173701681Y-89131109D01* +X173707712Y-89133794D01* +X173799946Y-89153399D01* +X173888056Y-89172128D01* +X173888061Y-89172128D01* +X173894513Y-89173500D01* +X174085487Y-89173500D01* +X174091939Y-89172128D01* +X174091944Y-89172128D01* +X174180054Y-89153399D01* +X174272288Y-89133794D01* +X174278319Y-89131109D01* +X174440722Y-89058803D01* +X174440724Y-89058802D01* +X174446752Y-89056118D01* +X174454485Y-89050500D01* +X174554071Y-88978146D01* +X174620939Y-88954288D01* +X174690090Y-88970368D01* +X174717227Y-88990987D01* +X174798193Y-89071953D01* +X174805017Y-89075989D01* +X174805020Y-89075991D01* +X174847082Y-89100866D01* +X174941399Y-89156645D01* +X174949010Y-89158856D01* +X174949012Y-89158857D01* +X174982046Y-89168454D01* +X175101169Y-89203062D01* +X175107574Y-89203566D01* +X175107579Y-89203567D01* +X175136042Y-89205807D01* +X175136050Y-89205807D01* +X175138498Y-89206000D01* +X176721502Y-89206000D01* +X176723950Y-89205807D01* +X176723958Y-89205807D01* +X176752421Y-89203567D01* +X176752426Y-89203566D01* +X176758831Y-89203062D01* +X176877954Y-89168454D01* +X176910988Y-89158857D01* +X176910990Y-89158856D01* +X176918601Y-89156645D01* +X177012918Y-89100866D01* +X177054980Y-89075991D01* +X177054983Y-89075989D01* +X177061807Y-89071953D01* +X177179453Y-88954307D01* +X177183489Y-88947483D01* +X177183491Y-88947480D01* +X177260108Y-88817927D01* +X177264145Y-88811101D01* +X177266806Y-88801944D01* +X177281528Y-88751269D01* +X177310562Y-88651331D01* +X177313056Y-88619651D01* +X177313307Y-88616458D01* +X177313307Y-88616450D01* +X177313500Y-88614002D01* +X177313500Y-88180998D01* +X177313307Y-88178542D01* +X177311067Y-88150079D01* +X177311066Y-88150074D01* +X177310562Y-88143669D01* +X177279726Y-88037529D01* +X177266357Y-87991512D01* +X177266356Y-87991510D01* +X177264145Y-87983899D01* +X177179453Y-87840693D01* +X177176513Y-87837753D01* +X177151180Y-87773234D01* +X177154996Y-87754119D01* +X178237425Y-87754119D01* +X178256244Y-88041249D01* +X178257317Y-88049400D01* +X178313454Y-88331617D01* +X178315588Y-88339580D01* +X178408078Y-88612047D01* +X178411228Y-88619651D01* +X178538492Y-88877718D01* +X178542613Y-88884855D01* +X178702470Y-89124099D01* +X178707488Y-89130639D01* +X178720147Y-89145074D01* +X178733386Y-89153472D01* +X178743151Y-89147638D01* +X180127980Y-87762810D01* +X180134357Y-87751131D01* +X180864408Y-87751131D01* +X180864539Y-87752966D01* +X180868790Y-87759580D01* +X182255095Y-89145884D01* +X182268856Y-89153399D01* +X182278216Y-89146941D01* +X182292512Y-89130639D01* +X182297530Y-89124099D01* +X182457387Y-88884855D01* +X182461508Y-88877718D01* +X182588772Y-88619651D01* +X182591922Y-88612047D01* +X182684412Y-88339580D01* +X182686546Y-88331617D01* +X182742683Y-88049400D01* +X182743756Y-88041249D01* +X182762575Y-87754119D01* +X182762575Y-87745881D01* +X182743756Y-87458751D01* +X182742683Y-87450600D01* +X182686546Y-87168383D01* +X182684412Y-87160420D01* +X182591922Y-86887953D01* +X182588772Y-86880349D01* +X182461508Y-86622282D01* +X182457387Y-86615145D01* +X182297530Y-86375901D01* +X182292512Y-86369361D01* +X182279853Y-86354926D01* +X182266614Y-86346528D01* +X182256849Y-86352362D01* +X180872020Y-87737190D01* +X180864408Y-87751131D01* +X180134357Y-87751131D01* +X180135592Y-87748869D01* +X180135461Y-87747034D01* +X180131210Y-87740420D01* +X178744905Y-86354116D01* +X178731144Y-86346601D01* +X178721784Y-86353059D01* +X178707488Y-86369361D01* +X178702470Y-86375901D01* +X178542613Y-86615145D01* +X178538492Y-86622282D01* +X178411228Y-86880349D01* +X178408078Y-86887953D01* +X178315588Y-87160420D01* +X178313454Y-87168383D01* +X178257317Y-87450600D01* +X178256244Y-87458751D01* +X178237425Y-87745881D01* +X178237425Y-87754119D01* +X177154996Y-87754119D01* +X177165079Y-87703611D01* +X177177126Y-87684864D01* +X177183090Y-87677176D01* +X177259648Y-87547721D01* +X177265893Y-87533290D01* +X177304939Y-87398895D01* +X177304899Y-87384794D01* +X177297630Y-87381500D01* +X174568122Y-87381500D01* +X174552883Y-87385975D01* +X174531717Y-87410402D01* +X174530400Y-87413287D01* +X174470683Y-87451683D01* +X174399686Y-87451699D01* +X174383910Y-87445902D01* +X174278323Y-87398892D01* +X174278315Y-87398889D01* +X174272288Y-87396206D01* +X174178887Y-87376353D01* +X174091944Y-87357872D01* +X174091939Y-87357872D01* +X174085487Y-87356500D01* +X173894513Y-87356500D01* +X173888061Y-87357872D01* +X173888056Y-87357872D01* +X173801113Y-87376353D01* +X173707712Y-87396206D01* +X173701682Y-87398891D01* +X173701681Y-87398891D01* +X173539278Y-87471197D01* +X173539276Y-87471198D01* +X173533248Y-87473882D01* +X173378747Y-87586134D01* +X173374326Y-87591044D01* +X173374325Y-87591045D01* +X173274352Y-87702077D01* +X173250960Y-87728056D01* +X173239842Y-87747313D01* +X173188460Y-87796305D01* +X173118746Y-87809740D01* +X173054019Y-87784272D01* +X173018042Y-87756665D01* +X173018037Y-87756662D01* +X173011487Y-87751636D01* +X173003861Y-87748477D01* +X173003859Y-87748476D01* +X172892986Y-87702551D01* +X172892983Y-87702550D01* +X172885356Y-87699391D01* +X172750000Y-87681571D01* +X172614644Y-87699391D01* +X172607017Y-87702550D01* +X172607014Y-87702551D01* +X172496141Y-87748476D01* +X172496139Y-87748477D01* +X172488513Y-87751636D01* +X172481963Y-87756662D01* +X172386748Y-87829724D01* +X172380202Y-87834747D01* +X172297091Y-87943058D01* +X172295567Y-87941889D01* +X172251849Y-87983577D01* +X172182136Y-87997016D01* +X172116224Y-87970632D01* +X172085655Y-87935725D01* +X172033493Y-87847524D01* +X172033492Y-87847523D01* +X172029453Y-87840693D01* +X172026513Y-87837753D01* +X172001180Y-87773234D01* +X172015079Y-87703611D01* +X172027126Y-87684864D01* +X172033090Y-87677176D01* +X172109648Y-87547721D01* +X172115893Y-87533290D01* +X172154939Y-87398895D01* +X172154899Y-87384794D01* +X172147630Y-87381500D01* +X169418122Y-87381500D01* +X169404591Y-87385473D01* +X169403456Y-87393371D01* +X169444107Y-87533290D01* +X169450352Y-87547721D01* +X169526911Y-87677177D01* +X169532871Y-87684860D01* +X169558820Y-87750944D01* +X169544922Y-87820567D01* +X169534579Y-87836661D01* +X169530547Y-87840693D01* +X169445855Y-87983899D01* +X169443644Y-87991510D01* +X169443643Y-87991512D01* +X169430274Y-88037529D01* +X169399438Y-88143669D01* +X169398934Y-88150074D01* +X169398933Y-88150079D01* +X169396693Y-88178542D01* +X169396500Y-88180998D01* +X169396500Y-88614002D01* +X169396693Y-88616450D01* +X169396693Y-88616458D01* +X169396945Y-88619651D01* +X169399438Y-88651331D01* +X169428472Y-88751269D01* +X169443195Y-88801944D01* +X169445855Y-88811101D01* +X169449892Y-88817927D01* +X169526509Y-88947480D01* +X169526511Y-88947483D01* +X169530547Y-88954307D01* +X169648193Y-89071953D01* +X169655017Y-89075989D01* +X169655020Y-89075991D01* +X169697082Y-89100866D01* +X169791399Y-89156645D01* +X169799010Y-89158856D01* +X169799012Y-89158857D01* +X169930653Y-89197102D01* +X169990488Y-89235315D01* +X170020166Y-89299811D01* +X170021500Y-89318099D01* +X170021500Y-91663194D01* +X170001498Y-91731315D01* +X169947842Y-91777808D01* +X169931075Y-91784068D01* +X169819202Y-91816994D01* +X169813742Y-91819848D01* +X169813743Y-91819848D01* +X169780624Y-91837162D01* +X169722249Y-91851500D01* +X168951391Y-91851500D01* +X168940848Y-91851058D01* +X168888902Y-91846696D01* +X168882142Y-91847598D01* +X168882139Y-91847598D01* +X168808395Y-91857437D01* +X168805341Y-91857807D01* +X168765980Y-91862083D01* +X168724563Y-91866583D01* +X168718092Y-91868761D01* +X168714852Y-91869473D01* +X168714417Y-91869550D01* +X168714017Y-91869666D01* +X168710774Y-91870463D01* +X168704012Y-91871365D01* +X168627644Y-91899161D01* +X168624823Y-91900149D01* +X168547777Y-91926078D01* +X168541930Y-91929591D01* +X168538896Y-91930993D01* +X168538508Y-91931153D01* +X168538121Y-91931364D01* +X168535147Y-91932828D01* +X168528733Y-91935162D01* +X168460090Y-91978724D01* +X168457621Y-91980249D01* +X168387891Y-92022147D01* +X168382932Y-92026837D01* +X168380277Y-92028852D01* +X168379546Y-92029360D01* +X168375608Y-92032338D01* +X168371241Y-92035109D01* +X168366968Y-92038929D01* +X168312972Y-92092925D01* +X168310450Y-92095379D01* +X168252364Y-92150308D01* +X168248526Y-92155956D01* +X168244107Y-92161148D01* +X168243707Y-92160808D01* +X168237100Y-92168797D01* +X167472217Y-92933680D01* +X167464451Y-92940822D01* +X167424633Y-92974471D01* +X167420486Y-92979895D01* +X167420485Y-92979896D01* +X167401041Y-93005328D01* +X167383037Y-93028877D01* +X167375326Y-93038962D01* +X167373432Y-93041379D01* +X167322490Y-93104738D01* +X167319453Y-93110857D01* +X167317665Y-93113652D01* +X167317412Y-93114013D01* +X167317210Y-93114380D01* +X167315479Y-93117238D01* +X167311340Y-93122652D01* +X167283065Y-93183288D01* +X167277015Y-93196262D01* +X167275681Y-93199033D01* +X167239553Y-93271814D01* +X167237902Y-93278435D01* +X167236751Y-93281563D01* +X167236587Y-93281956D01* +X167236468Y-93282361D01* +X167235391Y-93285526D01* +X167232510Y-93291704D01* +X167231023Y-93298355D01* +X167231022Y-93298359D01* +X167222826Y-93335029D01* +X167216462Y-93363502D01* +X167214789Y-93370985D01* +X167214080Y-93373982D01* +X167197306Y-93441260D01* +X167194428Y-93452801D01* +X167194237Y-93459622D01* +X167193785Y-93462925D01* +X167193626Y-93463809D01* +X167192948Y-93468692D01* +X167191820Y-93473740D01* +X167191500Y-93479463D01* +X167191500Y-93555844D01* +X167191451Y-93559363D01* +X167189219Y-93639257D01* +X167190498Y-93645961D01* +X167191045Y-93652762D01* +X167190525Y-93652804D01* +X167191500Y-93663125D01* +X167191500Y-96457594D01* +X167171498Y-96525715D01* +X167117842Y-96572208D01* +X167047568Y-96582312D01* +X166982988Y-96552818D01* +X166973951Y-96544167D01* +X166953886Y-96522949D01* +X166929692Y-96497364D01* +X166924044Y-96493526D01* +X166918852Y-96489107D01* +X166919192Y-96488707D01* +X166911203Y-96482100D01* +X166371320Y-95942217D01* +X166364177Y-95934450D01* +X166361747Y-95931574D01* +X166330529Y-95894633D01* +X166324003Y-95889643D01* +X166266038Y-95845326D01* +X166263615Y-95843427D01* +X166250999Y-95833283D01* +X166200262Y-95792490D01* +X166194143Y-95789453D01* +X166191348Y-95787665D01* +X166190987Y-95787412D01* +X166190620Y-95787210D01* +X166187762Y-95785479D01* +X166182348Y-95781340D01* +X166108736Y-95747014D01* +X166105964Y-95745680D01* +X166039296Y-95712586D01* +X166033186Y-95709553D01* +X166026565Y-95707902D01* +X166023437Y-95706751D01* +X166023044Y-95706587D01* +X166022639Y-95706468D01* +X166019475Y-95705391D01* +X166013296Y-95702510D01* +X165934000Y-95684785D01* +X165931002Y-95684076D01* +X165858821Y-95666079D01* +X165858820Y-95666079D01* +X165852199Y-95664428D01* +X165845378Y-95664237D01* +X165842075Y-95663785D01* +X165841191Y-95663626D01* +X165836308Y-95662948D01* +X165831260Y-95661820D01* +X165825537Y-95661500D01* +X165749156Y-95661500D01* +X165745637Y-95661451D01* +X165665743Y-95659219D01* +X165659039Y-95660498D01* +X165652238Y-95661045D01* +X165652196Y-95660525D01* +X165641875Y-95661500D01* +X163546425Y-95661500D01* +X163478304Y-95641498D01* +X163431811Y-95587842D01* +X163421707Y-95517568D01* +X163451201Y-95452988D01* +X163506236Y-95416081D01* +X163550753Y-95401100D01* +X163550758Y-95401098D01* +X163557223Y-95398922D01* +X163563076Y-95395405D01* +X163566084Y-95394015D01* +X163566489Y-95393848D01* +X163566865Y-95393643D01* +X163569852Y-95392173D01* +X163576268Y-95389838D01* +X163644920Y-95346270D01* +X163647389Y-95344745D01* +X163717109Y-95302853D01* +X163722066Y-95298166D01* +X163724723Y-95296149D01* +X163725469Y-95295631D01* +X163729402Y-95292656D01* +X163733759Y-95289891D01* +X163738032Y-95286070D01* +X163792010Y-95232092D01* +X163794532Y-95229638D01* +X163847680Y-95179379D01* +X163847682Y-95179377D01* +X163852636Y-95174692D01* +X163856471Y-95169050D01* +X163860894Y-95163852D01* +X163861290Y-95164189D01* +X163867904Y-95156198D01* +X165042776Y-93981326D01* +X165050543Y-93974183D01* +X165085154Y-93944934D01* +X165090367Y-93940529D01* +X165094512Y-93935108D01* +X165139710Y-93875992D01* +X165141609Y-93873571D01* +X165188232Y-93815582D01* +X165188233Y-93815580D01* +X165192509Y-93810262D01* +X165195543Y-93804150D01* +X165197330Y-93801356D01* +X165197582Y-93800996D01* +X165197785Y-93800627D01* +X165199517Y-93797766D01* +X165203660Y-93792348D01* +X165237993Y-93718721D01* +X165239327Y-93715949D01* +X165272414Y-93649296D01* +X165275447Y-93643186D01* +X165277098Y-93636565D01* +X165278249Y-93633437D01* +X165278413Y-93633044D01* +X165278532Y-93632639D01* +X165279609Y-93629475D01* +X165282490Y-93623296D01* +X165300215Y-93543998D01* +X165300924Y-93541002D01* +X165318921Y-93468821D01* +X165318921Y-93468820D01* +X165320572Y-93462199D01* +X165320763Y-93455378D01* +X165321215Y-93452075D01* +X165321374Y-93451191D01* +X165322052Y-93446308D01* +X165323180Y-93441260D01* +X165323500Y-93435537D01* +X165323500Y-93359156D01* +X165323549Y-93355637D01* +X165323636Y-93352526D01* +X165325781Y-93275743D01* +X165324502Y-93269039D01* +X165323955Y-93262238D01* +X165324475Y-93262196D01* +X165323500Y-93251875D01* +X165323500Y-87739595D01* +X165772001Y-87739595D01* +X165772338Y-87746114D01* +X165782257Y-87841706D01* +X165785149Y-87855100D01* +X165836588Y-88009284D01* +X165842761Y-88022462D01* +X165928063Y-88160307D01* +X165937099Y-88171708D01* +X166051829Y-88286239D01* +X166063240Y-88295251D01* +X166201243Y-88380316D01* +X166214424Y-88386463D01* +X166368710Y-88437638D01* +X166382086Y-88440505D01* +X166476438Y-88450172D01* +X166482854Y-88450500D01* +X166732885Y-88450500D01* +X166748124Y-88446025D01* +X166749329Y-88444635D01* +X166751000Y-88436952D01* +X166751000Y-88432384D01* +X167259000Y-88432384D01* +X167263475Y-88447623D01* +X167264865Y-88448828D01* +X167272548Y-88450499D01* +X167527095Y-88450499D01* +X167533614Y-88450162D01* +X167629206Y-88440243D01* +X167642600Y-88437351D01* +X167796784Y-88385912D01* +X167809962Y-88379739D01* +X167947807Y-88294437D01* +X167959208Y-88285401D01* +X168073739Y-88170671D01* +X168082751Y-88159260D01* +X168167816Y-88021257D01* +X168173963Y-88008076D01* +X168225138Y-87853790D01* +X168228005Y-87840414D01* +X168237672Y-87746062D01* +X168238000Y-87739646D01* +X168238000Y-87714615D01* +X168233525Y-87699376D01* +X168232135Y-87698171D01* +X168224452Y-87696500D01* +X167277115Y-87696500D01* +X167261876Y-87700975D01* +X167260671Y-87702365D01* +X167259000Y-87710048D01* +X167259000Y-88432384D01* +X166751000Y-88432384D01* +X166751000Y-87714615D01* +X166746525Y-87699376D01* +X166745135Y-87698171D01* +X166737452Y-87696500D01* +X165790116Y-87696500D01* +X165774877Y-87700975D01* +X165773672Y-87702365D01* +X165772001Y-87710048D01* +X165772001Y-87739595D01* +X165323500Y-87739595D01* +X165323500Y-86427000D01* +X165343502Y-86358879D01* +X165397158Y-86312386D01* +X165449500Y-86301000D01* +X165913607Y-86301000D01* +X165981728Y-86321002D01* +X166002625Y-86337827D01* +X166056697Y-86391805D01* +X166061235Y-86394602D01* +X166101824Y-86451853D01* +X166105054Y-86522776D01* +X166069428Y-86584187D01* +X166060932Y-86591562D01* +X166050793Y-86599598D01* +X165936261Y-86714329D01* +X165927249Y-86725740D01* +X165842184Y-86863743D01* +X165836037Y-86876924D01* +X165784862Y-87031210D01* +X165781995Y-87044586D01* +X165772328Y-87138938D01* +X165772000Y-87145355D01* +X165772000Y-87170385D01* +X165776475Y-87185624D01* +X165777865Y-87186829D01* +X165785548Y-87188500D01* +X168219884Y-87188500D01* +X168235123Y-87184025D01* +X168236328Y-87182635D01* +X168237999Y-87174952D01* +X168237999Y-87145405D01* +X168237662Y-87138886D01* +X168227743Y-87043294D01* +X168224851Y-87029900D01* +X168173412Y-86875716D01* +X168167239Y-86862538D01* +X168081937Y-86724693D01* +X168072901Y-86713292D01* +X167958172Y-86598762D01* +X167949238Y-86591706D01* +X167908177Y-86533788D01* +X167904947Y-86462865D01* +X167940574Y-86401454D01* +X167948407Y-86394654D01* +X167954348Y-86390978D01* +X168079305Y-86265803D01* +X168089216Y-86249725D01* +X168167102Y-86123371D01* +X169403456Y-86123371D01* +X169444107Y-86263290D01* +X169450352Y-86277721D01* +X169526912Y-86407178D01* +X169533189Y-86415270D01* +X169559139Y-86481354D01* +X169545241Y-86550977D01* +X169533189Y-86569730D01* +X169526912Y-86577822D01* +X169450352Y-86707279D01* +X169444107Y-86721710D01* +X169405061Y-86856105D01* +X169405101Y-86870206D01* +X169412370Y-86873500D01* +X170507885Y-86873500D01* +X170523124Y-86869025D01* +X170524329Y-86867635D01* +X170526000Y-86859952D01* +X170526000Y-86855385D01* +X171034000Y-86855385D01* +X171038475Y-86870624D01* +X171039865Y-86871829D01* +X171047548Y-86873500D01* +X172141878Y-86873500D01* +X172155409Y-86869527D01* +X172156544Y-86861629D01* +X172115893Y-86721710D01* +X172109648Y-86707279D01* +X172033088Y-86577822D01* +X172026811Y-86569730D01* +X172000861Y-86503646D01* +X172014759Y-86434023D01* +X172026811Y-86415270D01* +X172033088Y-86407178D01* +X172109648Y-86277721D01* +X172115893Y-86263290D01* +X172154939Y-86128895D01* +X172154899Y-86114794D01* +X172147630Y-86111500D01* +X171052115Y-86111500D01* +X171036876Y-86115975D01* +X171035671Y-86117365D01* +X171034000Y-86125048D01* +X171034000Y-86855385D01* +X170526000Y-86855385D01* +X170526000Y-86129615D01* +X170521525Y-86114376D01* +X170520135Y-86113171D01* +X170512452Y-86111500D01* +X169418122Y-86111500D01* +X169404591Y-86115473D01* +X169403456Y-86123371D01* +X168167102Y-86123371D01* +X168168275Y-86121468D01* +X168168276Y-86121466D01* +X168172115Y-86115238D01* +X168210388Y-85999848D01* +X168225632Y-85953889D01* +X168225632Y-85953887D01* +X168227797Y-85947361D01* +X168238500Y-85842900D01* +X168238500Y-85242100D01* +X168237789Y-85235248D01* +X168228238Y-85143192D01* +X168228237Y-85143188D01* +X168227526Y-85136334D01* +X168218627Y-85109659D01* +X168173868Y-84975502D01* +X168171550Y-84968554D01* +X168078478Y-84818152D01* +X168064303Y-84804002D01* +X169396500Y-84804002D01* +X169396693Y-84806450D01* +X169396693Y-84806458D01* +X169398263Y-84826400D01* +X169399438Y-84841331D01* +X169445855Y-85001101D01* +X169449892Y-85007927D01* +X169493462Y-85081599D01* +X169530547Y-85144307D01* +X169533487Y-85147247D01* +X169558820Y-85211766D01* +X169544921Y-85281389D01* +X169532874Y-85300136D01* +X169526910Y-85307824D01* +X169450352Y-85437279D01* +X169444107Y-85451710D01* +X169405061Y-85586105D01* +X169405101Y-85600206D01* +X169412370Y-85603500D01* +X172141878Y-85603500D01* +X172155409Y-85599527D01* +X172156544Y-85591629D01* +X172115893Y-85451710D01* +X172109648Y-85437279D01* +X172033089Y-85307823D01* +X172027129Y-85300140D01* +X172001180Y-85234056D01* +X172015078Y-85164433D01* +X172025421Y-85148339D01* +X172029453Y-85144307D01* +X172114145Y-85001101D01* +X172160562Y-84841331D01* +X172161738Y-84826400D01* +X172163307Y-84806458D01* +X172163307Y-84806450D01* +X172163500Y-84804002D01* +X172163500Y-84370998D01* +X172163307Y-84368542D01* +X172161067Y-84340079D01* +X172161066Y-84340074D01* +X172160562Y-84333669D01* +X172114145Y-84173899D01* +X172074181Y-84106323D01* +X172033491Y-84037520D01* +X172033489Y-84037517D01* +X172029453Y-84030693D01* +X171911807Y-83913047D01* +X171904983Y-83909011D01* +X171904980Y-83909009D01* +X171775427Y-83832392D01* +X171775428Y-83832392D01* +X171768601Y-83828355D01* +X171614347Y-83783541D01* +X171554512Y-83745329D01* +X171524834Y-83680832D01* +X171523500Y-83662544D01* +X171523500Y-83243012D01* +X171543502Y-83174891D01* +X171554119Y-83160681D01* +X171597994Y-83109852D01* +X171597995Y-83109850D01* +X171602023Y-83105184D01* +X171694870Y-82941744D01* +X171754203Y-82763382D01* +X171777762Y-82576892D01* +X171777969Y-82562111D01* +X171778089Y-82553522D01* +X171778089Y-82553518D01* +X171778138Y-82550000D01* +X171759795Y-82362926D01* +X171750638Y-82332595D01* +X171720549Y-82232939D01* +X171705465Y-82182977D01* +X171617218Y-82017008D01* +X171498415Y-81871340D01* +X171388217Y-81780176D01* +X171358329Y-81755450D01* +X171358324Y-81755447D01* +X171353580Y-81751522D01* +X171348161Y-81748592D01* +X171348158Y-81748590D01* +X171278671Y-81711019D01* +X171188231Y-81662119D01* +X171008666Y-81606534D01* +X171002541Y-81605890D01* +X171002540Y-81605890D01* +X170827852Y-81587529D01* +X170827851Y-81587529D01* +X170821724Y-81586885D01* +X170744673Y-81593897D01* +X170640665Y-81603363D01* +X170640662Y-81603364D01* +X170634526Y-81603922D01* +X170628620Y-81605660D01* +X170628616Y-81605661D01* +X170495278Y-81644905D01* +X170454202Y-81656994D01* +X170287621Y-81744080D01* +X170141128Y-81861864D01* +X170137170Y-81866582D01* +X170137167Y-81866584D01* +X170057326Y-81961736D01* +X170020302Y-82005859D01* +X170017338Y-82011251D01* +X170017335Y-82011255D01* +X169966377Y-82103948D01* +X169929746Y-82170580D01* +X169927885Y-82176447D01* +X169927884Y-82176449D01* +X169910710Y-82230589D01* +X169872909Y-82349752D01* +X169851956Y-82536552D01* +X169853211Y-82551500D01* +X169866431Y-82708928D01* +X169867685Y-82723865D01* +X169888892Y-82797824D01* +X169908179Y-82865083D01* +X169919497Y-82904555D01* +X169922312Y-82910032D01* +X169922313Y-82910035D01* +X169991600Y-83044853D01* +X170005418Y-83071740D01* +X170009241Y-83076564D01* +X170009244Y-83076568D01* +X170079245Y-83164886D01* +X170105883Y-83230696D01* +X170106500Y-83243151D01* +X170106500Y-83653314D01* +X170086498Y-83721435D01* +X170032842Y-83767928D01* +X169988458Y-83778497D01* +X169988498Y-83779000D01* +X169957579Y-83781433D01* +X169957574Y-83781434D01* +X169951169Y-83781938D01* +X169877048Y-83803472D01* +X169799012Y-83826143D01* +X169799010Y-83826144D01* +X169791399Y-83828355D01* +X169784572Y-83832392D01* +X169784573Y-83832392D01* +X169655020Y-83909009D01* +X169655017Y-83909011D01* +X169648193Y-83913047D01* +X169530547Y-84030693D01* +X169526511Y-84037517D01* +X169526509Y-84037520D01* +X169485819Y-84106323D01* +X169445855Y-84173899D01* +X169399438Y-84333669D01* +X169398934Y-84340074D01* +X169398933Y-84340079D01* +X169396693Y-84368542D01* +X169396500Y-84370998D01* +X169396500Y-84804002D01* +X168064303Y-84804002D01* +X167953303Y-84693195D01* +X167927974Y-84677582D01* +X167808968Y-84604225D01* +X167808966Y-84604224D01* +X167802738Y-84600385D01* +X167680619Y-84559880D01* +X167641389Y-84546868D01* +X167641387Y-84546868D01* +X167634861Y-84544703D01* +X167628025Y-84544003D01* +X167628022Y-84544002D01* +X167584969Y-84539591D01* +X167530400Y-84534000D01* +X166479600Y-84534000D01* +X166476354Y-84534337D01* +X166476350Y-84534337D01* +X166380692Y-84544262D01* +X166380688Y-84544263D01* +X166373834Y-84544974D01* +X166367298Y-84547155D01* +X166367296Y-84547155D01* +X166235194Y-84591228D01* +X166206054Y-84600950D01* +X166055652Y-84694022D01* +X166050479Y-84699204D01* +X166002748Y-84747018D01* +X165940465Y-84781097D01* +X165913575Y-84784000D01* +X165449500Y-84784000D01* +X165381379Y-84763998D01* +X165334886Y-84710342D01* +X165323500Y-84658000D01* +X165323500Y-81500400D01* +X172818500Y-81500400D01* +X172818837Y-81503646D01* +X172818837Y-81503650D01* +X172824227Y-81555592D01* +X172829474Y-81606166D01* +X172831655Y-81612702D01* +X172831655Y-81612704D01* +X172848141Y-81662119D01* +X172885450Y-81773946D01* +X172978522Y-81924348D01* +X172983704Y-81929521D01* +X173094018Y-82039643D01* +X173128097Y-82101926D01* +X173131000Y-82128816D01* +X173131000Y-85418588D01* +X173130708Y-85427158D01* +X173127623Y-85472419D01* +X173126775Y-85484852D01* +X173128080Y-85492329D01* +X173128080Y-85492330D01* +X173137761Y-85547799D01* +X173138723Y-85554321D01* +X173146398Y-85617742D01* +X173149081Y-85624843D01* +X173149722Y-85627452D01* +X173154185Y-85643762D01* +X173154950Y-85646298D01* +X173156257Y-85653784D01* +X173177939Y-85703175D01* +X173181942Y-85712295D01* +X173184433Y-85718399D01* +X173207013Y-85778156D01* +X173211317Y-85784419D01* +X173212554Y-85786785D01* +X173220799Y-85801597D01* +X173222132Y-85803851D01* +X173225185Y-85810805D01* +X173256755Y-85851946D01* +X173264079Y-85861491D01* +X173267959Y-85866832D01* +X173299839Y-85913220D01* +X173299844Y-85913225D01* +X173304143Y-85919481D01* +X173309813Y-85924532D01* +X173309814Y-85924534D01* +X173350670Y-85960935D01* +X173355946Y-85965916D01* +X173728050Y-86338020D01* +X173733904Y-86344285D01* +X173771939Y-86387885D01* +X173811393Y-86415613D01* +X173824197Y-86424612D01* +X173829493Y-86428545D01* +X173879782Y-86467977D01* +X173886704Y-86471102D01* +X173888952Y-86472464D01* +X173903685Y-86480868D01* +X173906024Y-86482122D01* +X173912239Y-86486490D01* +X173919315Y-86489249D01* +X173919319Y-86489251D01* +X173971774Y-86509702D01* +X173977852Y-86512257D01* +X174036074Y-86538545D01* +X174043545Y-86539929D01* +X174046099Y-86540730D01* +X174062378Y-86545367D01* +X174064933Y-86546023D01* +X174072009Y-86548782D01* +X174100462Y-86552528D01* +X174135351Y-86557121D01* +X174141867Y-86558153D01* +X174184206Y-86566000D01* +X174204687Y-86569796D01* +X174212267Y-86569359D01* +X174212268Y-86569359D01* +X174266898Y-86566209D01* +X174274151Y-86566000D01* +X174471528Y-86566000D01* +X174539649Y-86586002D01* +X174586142Y-86639658D01* +X174596246Y-86709932D01* +X174592525Y-86727153D01* +X174555061Y-86856104D01* +X174555101Y-86870206D01* +X174562370Y-86873500D01* +X177291878Y-86873500D01* +X177305409Y-86869527D01* +X177306544Y-86861629D01* +X177265893Y-86721710D01* +X177259646Y-86707274D01* +X177249823Y-86690664D01* +X177232364Y-86621847D01* +X177254882Y-86554516D01* +X177313739Y-86508660D01* +X177356050Y-86492672D01* +X177356049Y-86492672D01* +X177363156Y-86489987D01* +X177369419Y-86485683D01* +X177371785Y-86484446D01* +X177386597Y-86476201D01* +X177388851Y-86474868D01* +X177395805Y-86471815D01* +X177446502Y-86432913D01* +X177451832Y-86429041D01* +X177498220Y-86397161D01* +X177498225Y-86397156D01* +X177504481Y-86392857D01* +X177510028Y-86386632D01* +X177545935Y-86346330D01* +X177550916Y-86341054D01* +X178472279Y-85419691D01* +X178534591Y-85385665D01* +X178605406Y-85390730D01* +X178627490Y-85401526D01* +X178732532Y-85466275D01* +X178738762Y-85470115D01* +X178760352Y-85477276D01* +X178900111Y-85523632D01* +X178900113Y-85523632D01* +X178906639Y-85525797D01* +X178913475Y-85526497D01* +X178913478Y-85526498D01* +X178956531Y-85530909D01* +X179011100Y-85536500D01* +X179342888Y-85536500D01* +X179411009Y-85556502D01* +X179457502Y-85610158D01* +X179467606Y-85680432D01* +X179438112Y-85745012D01* +X179398616Y-85775506D01* +X179372282Y-85788493D01* +X179365145Y-85792613D01* +X179125901Y-85952470D01* +X179119361Y-85957488D01* +X179104926Y-85970147D01* +X179096528Y-85983386D01* +X179102362Y-85993151D01* +X180487190Y-87377980D01* +X180501131Y-87385592D01* +X180502966Y-87385461D01* +X180509580Y-87381210D01* +X181895884Y-85994905D01* +X181903399Y-85981144D01* +X181896941Y-85971784D01* +X181880639Y-85957488D01* +X181874099Y-85952470D01* +X181634856Y-85792613D01* +X181627719Y-85788493D01* +X181559636Y-85754918D01* +X181507387Y-85706850D01* +X181489420Y-85638165D01* +X181511439Y-85570669D01* +X181566454Y-85525792D01* +X181575488Y-85522388D01* +X181728284Y-85471412D01* +X181741462Y-85465239D01* +X181879307Y-85379937D01* +X181890708Y-85370901D01* +X182005239Y-85256171D01* +X182014251Y-85244760D01* +X182099316Y-85106757D01* +X182105463Y-85093576D01* +X182156638Y-84939290D01* +X182159505Y-84925914D01* +X182169172Y-84831562D01* +X182169500Y-84825146D01* +X182169500Y-84600115D01* +X182165025Y-84584876D01* +X182163635Y-84583671D01* +X182155952Y-84582000D01* +X181021000Y-84582000D01* +X180952879Y-84561998D01* +X180906386Y-84508342D01* +X180895000Y-84456000D01* +X180895000Y-84200000D01* +X180915002Y-84131879D01* +X180968658Y-84085386D01* +X181021000Y-84074000D01* +X182151384Y-84074000D01* +X182166623Y-84069525D01* +X182167828Y-84068135D01* +X182169499Y-84060452D01* +X182169499Y-83830905D01* +X182169162Y-83824386D01* +X182159243Y-83728794D01* +X182156351Y-83715400D01* +X182143999Y-83678376D01* +X182141415Y-83607426D01* +X182177599Y-83546343D01* +X182241063Y-83514518D01* +X182263523Y-83512500D01* +X183552500Y-83512500D01* +X183620621Y-83532502D01* +X183667114Y-83586158D01* +X183678500Y-83638500D01* +X183678500Y-83678400D01* +X183678837Y-83681646D01* +X183678837Y-83681650D01* +X183688110Y-83771018D01* +X183689474Y-83784166D01* +X183691655Y-83790702D01* +X183691655Y-83790704D01* +X183709061Y-83842876D01* +X183745450Y-83951946D01* +X183838522Y-84102348D01* +X183963697Y-84227305D01* +X183967916Y-84229906D01* +X184008417Y-84287030D01* +X184011649Y-84357953D01* +X183976024Y-84419365D01* +X183968470Y-84425922D01* +X183962652Y-84429522D01* +X183837695Y-84554697D01* +X183833855Y-84560927D01* +X183833854Y-84560928D01* +X183758489Y-84683193D01* +X183744885Y-84705262D01* +X183742581Y-84712209D01* +X183704706Y-84826400D01* +X183689203Y-84873139D01* +X183678500Y-84977600D01* +X183678500Y-85578400D01* +X183678837Y-85581646D01* +X183678837Y-85581650D01* +X183688120Y-85671114D01* +X183689474Y-85684166D01* +X183691655Y-85690702D01* +X183691655Y-85690704D01* +X183727070Y-85796854D01* +X183745450Y-85851946D01* +X183838522Y-86002348D01* +X183963697Y-86127305D01* +X183969927Y-86131145D01* +X183969928Y-86131146D01* +X184107090Y-86215694D01* +X184114262Y-86220115D01* +X184121209Y-86222419D01* +X184127844Y-86225513D01* +X184126801Y-86227749D01* +X184175538Y-86261523D01* +X184202766Y-86327091D01* +X184203500Y-86340672D01* +X184203500Y-86415613D01* +X184183498Y-86483734D01* +X184137270Y-86524184D01* +X184138054Y-86525450D01* +X183987652Y-86618522D01* +X183862695Y-86743697D01* +X183769885Y-86894262D01* +X183767581Y-86901209D01* +X183720454Y-87043294D01* +X183714203Y-87062139D01* +X183703500Y-87166600D01* +X183703500Y-87792400D01* +X183703837Y-87795646D01* +X183703837Y-87795650D01* +X183713330Y-87887136D01* +X183714474Y-87898166D01* +X183716655Y-87904702D01* +X183716655Y-87904704D01* +X183755943Y-88022462D01* +X183770450Y-88065946D01* +X183863522Y-88216348D01* +X183868704Y-88221521D01* +X183950463Y-88303138D01* +X183984542Y-88365421D01* +X183979539Y-88436241D01* +X183950618Y-88481329D01* +X183868261Y-88563829D01* +X183859249Y-88575240D01* +X183774184Y-88713243D01* +X183768037Y-88726424D01* +X183716862Y-88880710D01* +X183713995Y-88894086D01* +X183704328Y-88988435D01* +X183704000Y-88994855D01* +X183704000Y-89032385D01* +X183708475Y-89047624D01* +X183709865Y-89048829D01* +X183717548Y-89050500D01* +X186101884Y-89050500D01* +X186117123Y-89046025D01* +X186118328Y-89044635D01* +X186119999Y-89036952D01* +X186119999Y-88994905D01* +X186119662Y-88988386D01* +X186109743Y-88892794D01* +X186106851Y-88879400D01* +X186055412Y-88725216D01* +X186049239Y-88712038D01* +X185963937Y-88574193D01* +X185954901Y-88562792D01* +X185873538Y-88481570D01* +X185839459Y-88419287D01* +X185844462Y-88348467D01* +X185873383Y-88303380D01* +X185956130Y-88220488D01* +X185956134Y-88220483D01* +X185961305Y-88215303D01* +X185967936Y-88204545D01* +X186050275Y-88070968D01* +X186050276Y-88070966D01* +X186054115Y-88064738D01* +X186094862Y-87941889D01* +X186107632Y-87903389D01* +X186107632Y-87903387D01* +X186109797Y-87896861D01* +X186110794Y-87887136D01* +X186115552Y-87840693D01* +X186120500Y-87792400D01* +X186120500Y-87166600D01* +X186117630Y-87138938D01* +X186110238Y-87067692D01* +X186110237Y-87067688D01* +X186109526Y-87060834D01* +X186053550Y-86893054D01* +X185960478Y-86742652D01* +X185943537Y-86725740D01* +X185840483Y-86622866D01* +X185835303Y-86617695D01* +X185805945Y-86599598D01* +X185684738Y-86524885D01* +X185685774Y-86523205D01* +X185639969Y-86482879D01* +X185620500Y-86415595D01* +X185620500Y-86340516D01* +X185640502Y-86272395D01* +X185694158Y-86225902D01* +X185701874Y-86222863D01* +X185703997Y-86221868D01* +X185710946Y-86219550D01* +X185861348Y-86126478D01* +X185986305Y-86001303D01* +X186016406Y-85952470D01* +X186075275Y-85856968D01* +X186075276Y-85856966D01* +X186079115Y-85850738D01* +X186114183Y-85745012D01* +X186132632Y-85689389D01* +X186132632Y-85689387D01* +X186134797Y-85682861D01* +X186137064Y-85660741D01* +X186141469Y-85617742D01* +X186145500Y-85578400D01* +X186145500Y-84977600D01* +X186145163Y-84974350D01* +X186135238Y-84878692D01* +X186135237Y-84878688D01* +X186134526Y-84871834D01* +X186124350Y-84841331D01* +X186080868Y-84711002D01* +X186078550Y-84704054D01* +X185985478Y-84553652D01* +X185860303Y-84428695D01* +X185856084Y-84426094D01* +X185815583Y-84368970D01* +X185812351Y-84298047D01* +X185847976Y-84236635D01* +X185855530Y-84230078D01* +X185861348Y-84226478D01* +X185986305Y-84101303D01* +X185990146Y-84095072D01* +X186075275Y-83956968D01* +X186075276Y-83956966D01* +X186079115Y-83950738D01* +X186117478Y-83835077D01* +X186132632Y-83789389D01* +X186132632Y-83789387D01* +X186134797Y-83782861D01* +X186136011Y-83771018D01* +X186141709Y-83715400D01* +X186145500Y-83678400D01* +X186145500Y-83077600D01* +X186142834Y-83051907D01* +X186135238Y-82978692D01* +X186135237Y-82978688D01* +X186134526Y-82971834D01* +X186131109Y-82961590D01* +X186080868Y-82811002D01* +X186078550Y-82804054D01* +X185985478Y-82653652D01* +X185860303Y-82528695D01* +X185709738Y-82435885D01* +X185629995Y-82409436D01* +X185548389Y-82382368D01* +X185548387Y-82382368D01* +X185541861Y-82380203D01* +X185535025Y-82379503D01* +X185535022Y-82379502D01* +X185491969Y-82375091D01* +X185437400Y-82369500D01* +X184957660Y-82369500D01* +X184889539Y-82349498D01* +X184868565Y-82332595D01* +X184859442Y-82323472D01* +X184853588Y-82317206D01* +X184820556Y-82279340D01* +X184820553Y-82279337D01* +X184815561Y-82273615D01* +X184763280Y-82236871D01* +X184757986Y-82232939D01* +X184713693Y-82198209D01* +X184707718Y-82193524D01* +X184700802Y-82190401D01* +X184698516Y-82189017D01* +X184683835Y-82180643D01* +X184681475Y-82179378D01* +X184675261Y-82175010D01* +X184668182Y-82172250D01* +X184668180Y-82172249D01* +X184615725Y-82151798D01* +X184609656Y-82149247D01* +X184551427Y-82122955D01* +X184543960Y-82121571D01* +X184541405Y-82120770D01* +X184525152Y-82116141D01* +X184522572Y-82115478D01* +X184515491Y-82112718D01* +X184507960Y-82111727D01* +X184507958Y-82111726D01* +X184478339Y-82107827D01* +X184452139Y-82104378D01* +X184445641Y-82103348D01* +X184382814Y-82091704D01* +X184375234Y-82092141D01* +X184375233Y-82092141D01* +X184320608Y-82095291D01* +X184313354Y-82095500D01* +X182019136Y-82095500D01* +X181951015Y-82075498D01* +X181904522Y-82021842D01* +X181894418Y-81951568D01* +X181903644Y-81926608D01* +X181903585Y-81916804D01* +X181897638Y-81906849D01* +X180512810Y-80522020D01* +X180498869Y-80514408D01* +X180497034Y-80514539D01* +X180490420Y-80518790D01* +X179104116Y-81905095D01* +X179096502Y-81919039D01* +X179098546Y-81947622D01* +X179104396Y-81965374D01* +X179086636Y-82034114D01* +X179034531Y-82082338D01* +X178978464Y-82095500D01* +X177574912Y-82095500D01* +X177566342Y-82095208D01* +X177516224Y-82091791D01* +X177516220Y-82091791D01* +X177508648Y-82091275D01* +X177501171Y-82092580D01* +X177501170Y-82092580D01* +X177474692Y-82097201D01* +X177445697Y-82102262D01* +X177439179Y-82103223D01* +X177375758Y-82110898D01* +X177368657Y-82113581D01* +X177366048Y-82114222D01* +X177349738Y-82118685D01* +X177347202Y-82119450D01* +X177339716Y-82120757D01* +X177287069Y-82143868D01* +X177281205Y-82146442D01* +X177275101Y-82148933D01* +X177215344Y-82171513D01* +X177209081Y-82175817D01* +X177206715Y-82177054D01* +X177191903Y-82185299D01* +X177189649Y-82186632D01* +X177182695Y-82189685D01* +X177131998Y-82228587D01* +X177126668Y-82232459D01* +X177080280Y-82264339D01* +X177080275Y-82264344D01* +X177074019Y-82268643D01* +X177068968Y-82274313D01* +X177068966Y-82274314D01* +X177032565Y-82315170D01* +X177027584Y-82320446D01* +X175605935Y-83742095D01* +X175543623Y-83776121D01* +X175516840Y-83779000D01* +X175138498Y-83779000D01* +X175136050Y-83779193D01* +X175136042Y-83779193D01* +X175107579Y-83781433D01* +X175107574Y-83781434D01* +X175101169Y-83781938D01* +X175027048Y-83803472D01* +X174949012Y-83826143D01* +X174949010Y-83826144D01* +X174941399Y-83828355D01* +X174934572Y-83832392D01* +X174934573Y-83832392D01* +X174805020Y-83909009D01* +X174805017Y-83909011D01* +X174798193Y-83913047D01* +X174763095Y-83948145D01* +X174700783Y-83982171D01* +X174629968Y-83977106D01* +X174573132Y-83934559D01* +X174548321Y-83868039D01* +X174548000Y-83859050D01* +X174548000Y-82129002D01* +X174568002Y-82060881D01* +X174584827Y-82039984D01* +X174585168Y-82039643D01* +X174662784Y-81961891D01* +X174725066Y-81927812D01* +X174795887Y-81932815D01* +X174840975Y-81961736D01* +X174880449Y-82001141D01* +X174928697Y-82049305D01* +X174934927Y-82053145D01* +X174934928Y-82053146D01* +X175072090Y-82137694D01* +X175079262Y-82142115D01* +X175104847Y-82150601D01* +X175240611Y-82195632D01* +X175240613Y-82195632D01* +X175247139Y-82197797D01* +X175253975Y-82198497D01* +X175253978Y-82198498D01* +X175297031Y-82202909D01* +X175351600Y-82208500D01* +X175977400Y-82208500D01* +X175980646Y-82208163D01* +X175980650Y-82208163D01* +X176076308Y-82198238D01* +X176076312Y-82198237D01* +X176083166Y-82197526D01* +X176089702Y-82195345D01* +X176089704Y-82195345D01* +X176227893Y-82149241D01* +X176250946Y-82141550D01* +X176401348Y-82048478D01* +X176526305Y-81923303D01* +X176534246Y-81910420D01* +X176615275Y-81778968D01* +X176615276Y-81778966D01* +X176619115Y-81772738D01* +X176654993Y-81664570D01* +X176672632Y-81611389D01* +X176672632Y-81611387D01* +X176674797Y-81604861D01* +X176685500Y-81500400D01* +X176685500Y-80499600D01* +X176681641Y-80462404D01* +X176675238Y-80400692D01* +X176675237Y-80400688D01* +X176674526Y-80393834D01* +X176668824Y-80376741D01* +X176620868Y-80233002D01* +X176618550Y-80226054D01* +X176574035Y-80154119D01* +X178237425Y-80154119D01* +X178256244Y-80441249D01* +X178257317Y-80449400D01* +X178313454Y-80731617D01* +X178315588Y-80739580D01* +X178408078Y-81012047D01* +X178411228Y-81019651D01* +X178538492Y-81277718D01* +X178542613Y-81284855D01* +X178702470Y-81524099D01* +X178707488Y-81530639D01* +X178720147Y-81545074D01* +X178733386Y-81553472D01* +X178743151Y-81547638D01* +X180127980Y-80162810D01* +X180134357Y-80151131D01* +X180864408Y-80151131D01* +X180864539Y-80152966D01* +X180868790Y-80159580D01* +X182255095Y-81545884D01* +X182268856Y-81553399D01* +X182278216Y-81546941D01* +X182292512Y-81530639D01* +X182297530Y-81524099D01* +X182457387Y-81284855D01* +X182461508Y-81277718D01* +X182588772Y-81019651D01* +X182591922Y-81012047D01* +X182684412Y-80739580D01* +X182686546Y-80731617D01* +X182742683Y-80449400D01* +X182743756Y-80441249D01* +X182762575Y-80154119D01* +X182762575Y-80145881D01* +X182743756Y-79858751D01* +X182742683Y-79850600D01* +X182686546Y-79568383D01* +X182684412Y-79560420D01* +X182591922Y-79287953D01* +X182588772Y-79280349D01* +X182461508Y-79022282D01* +X182457387Y-79015145D01* +X182297530Y-78775901D01* +X182292512Y-78769361D01* +X182279853Y-78754926D01* +X182266614Y-78746528D01* +X182256849Y-78752362D01* +X180872020Y-80137190D01* +X180864408Y-80151131D01* +X180134357Y-80151131D01* +X180135592Y-80148869D01* +X180135461Y-80147034D01* +X180131210Y-80140420D01* +X178744905Y-78754116D01* +X178731144Y-78746601D01* +X178721784Y-78753059D01* +X178707488Y-78769361D01* +X178702470Y-78775901D01* +X178542613Y-79015145D01* +X178538492Y-79022282D01* +X178411228Y-79280349D01* +X178408078Y-79287953D01* +X178315588Y-79560420D01* +X178313454Y-79568383D01* +X178257317Y-79850600D01* +X178256244Y-79858751D01* +X178237425Y-80145881D01* +X178237425Y-80154119D01* +X176574035Y-80154119D01* +X176525478Y-80075652D01* +X176409982Y-79960357D01* +X176375903Y-79898074D01* +X176373000Y-79871184D01* +X176373000Y-78665412D01* +X176373292Y-78656842D01* +X176376709Y-78606724D01* +X176376709Y-78606720D01* +X176377225Y-78599148D01* +X176373019Y-78575046D01* +X176366240Y-78536208D01* +X176365277Y-78529682D01* +X176362340Y-78505414D01* +X176357602Y-78466258D01* +X176354916Y-78459150D01* +X176354279Y-78456556D01* +X176349818Y-78440250D01* +X176349048Y-78437699D01* +X176347742Y-78430216D01* +X176327185Y-78383386D01* +X179096528Y-78383386D01* +X179102362Y-78393151D01* +X180487190Y-79777980D01* +X180501131Y-79785592D01* +X180502966Y-79785461D01* +X180509580Y-79781210D01* +X181895884Y-78394905D01* +X181903399Y-78381144D01* +X181896941Y-78371784D01* +X181880639Y-78357488D01* +X181874099Y-78352470D01* +X181634856Y-78192613D01* +X181627719Y-78188492D01* +X181369651Y-78061228D01* +X181362047Y-78058078D01* +X181089580Y-77965588D01* +X181081617Y-77963454D01* +X180799400Y-77907317D01* +X180791249Y-77906244D01* +X180504119Y-77887425D01* +X180495881Y-77887425D01* +X180208751Y-77906244D01* +X180200600Y-77907317D01* +X179918383Y-77963454D01* +X179910420Y-77965588D01* +X179637953Y-78058078D01* +X179630349Y-78061228D01* +X179372282Y-78188492D01* +X179365145Y-78192613D01* +X179125901Y-78352470D01* +X179119361Y-78357488D01* +X179104926Y-78370147D01* +X179096528Y-78383386D01* +X176327185Y-78383386D01* +X176326201Y-78381144D01* +X176322061Y-78371712D01* +X176319569Y-78365605D01* +X176299673Y-78312952D01* +X176299673Y-78312951D01* +X176296987Y-78305844D01* +X176292684Y-78299583D01* +X176291447Y-78297217D01* +X176283220Y-78282437D01* +X176281869Y-78280152D01* +X176278815Y-78273195D01* +X176274195Y-78267175D01* +X176274192Y-78267169D01* +X176244780Y-78228841D01* +X176239913Y-78222498D01* +X176236041Y-78217168D01* +X176204161Y-78170780D01* +X176204156Y-78170775D01* +X176199857Y-78164519D01* +X176194189Y-78159469D01* +X176189162Y-78153767D01* +X176191591Y-78151626D01* +X176161790Y-78103795D01* +X176157861Y-78083163D01* +X176154232Y-78048635D01* +X176154232Y-78048633D01* +X176153542Y-78042072D01* +X176094527Y-77860444D01* +X175999040Y-77695056D01* +X175871253Y-77553134D01* +X175772157Y-77481136D01* +X175722094Y-77444763D01* +X175722093Y-77444762D01* +X175716752Y-77440882D01* +X175710724Y-77438198D01* +X175710722Y-77438197D01* +X175548319Y-77365891D01* +X175548318Y-77365891D01* +X175542288Y-77363206D01* +X175448888Y-77343353D01* +X175361944Y-77324872D01* +X175361939Y-77324872D01* +X175355487Y-77323500D01* +X175164513Y-77323500D01* +X175158061Y-77324872D01* +X175158056Y-77324872D01* +X175071112Y-77343353D01* +X174977712Y-77363206D01* +X174971682Y-77365891D01* +X174971681Y-77365891D01* +X174809278Y-77438197D01* +X174809276Y-77438198D01* +X174803248Y-77440882D01* +X174797907Y-77444762D01* +X174797906Y-77444763D01* +X174747843Y-77481136D01* +X174648747Y-77553134D01* +X174520960Y-77695056D01* +X174425473Y-77860444D01* +X174366458Y-78042072D01* +X174365768Y-78048633D01* +X174365768Y-78048635D01* +X174354696Y-78153982D01* +X174346496Y-78232000D01* +X174347186Y-78238565D01* +X174357110Y-78332982D01* +X174366458Y-78421928D01* +X174425473Y-78603556D01* +X174520960Y-78768944D01* +X174648747Y-78910866D01* +X174803248Y-79023118D01* +X174822326Y-79031612D01* +X174881249Y-79057846D01* +X174935345Y-79103826D01* +X174956000Y-79172953D01* +X174956000Y-79870998D01* +X174935998Y-79939119D01* +X174919174Y-79960015D01* +X174841216Y-80038109D01* +X174778934Y-80072188D01* +X174708113Y-80067185D01* +X174663025Y-80038264D01* +X174580483Y-79955866D01* +X174575303Y-79950695D01* +X174557270Y-79939579D01* +X174430968Y-79861725D01* +X174430966Y-79861724D01* +X174424738Y-79857885D01* +X174296821Y-79815457D01* +X174263389Y-79804368D01* +X174263387Y-79804368D01* +X174256861Y-79802203D01* +X174250025Y-79801503D01* +X174250022Y-79801502D01* +X174206969Y-79797091D01* +X174152400Y-79791500D01* +X173526600Y-79791500D01* +X173523354Y-79791837D01* +X173523350Y-79791837D01* +X173427692Y-79801762D01* +X173427688Y-79801763D01* +X173420834Y-79802474D01* +X173414298Y-79804655D01* +X173414296Y-79804655D01* +X173311442Y-79838970D01* +X173253054Y-79858450D01* +X173102652Y-79951522D01* +X172977695Y-80076697D01* +X172973855Y-80082927D01* +X172973854Y-80082928D01* +X172909053Y-80188055D01* +X172884885Y-80227262D01* +X172870729Y-80269942D01* +X172834530Y-80379080D01* +X172829203Y-80395139D01* +X172818500Y-80499600D01* +X172818500Y-81500400D01* +X165323500Y-81500400D01* +X165323500Y-78567652D01* +X165339331Y-78507737D01* +X165339319Y-78507732D01* +X165339352Y-78507657D01* +X165339945Y-78505414D01* +X165341822Y-78502110D01* +X165341823Y-78502107D01* +X165344870Y-78496744D01* +X165404203Y-78318382D01* +X165427762Y-78131892D01* +X165427930Y-78119901D01* +X165428089Y-78108522D01* +X165428089Y-78108518D01* +X165428138Y-78105000D01* +X165409795Y-77917926D01* +X165355465Y-77737977D01* +X165267218Y-77572008D01* +X165148415Y-77426340D01* +X165070441Y-77361834D01* +X165008329Y-77310450D01* +X165008324Y-77310447D01* +X165003580Y-77306522D01* +X164998161Y-77303592D01* +X164998158Y-77303590D01* +X164928671Y-77266019D01* +X164838231Y-77217119D01* +X164658666Y-77161534D01* +X164652541Y-77160890D01* +X164652540Y-77160890D01* +X164477852Y-77142529D01* +X164477851Y-77142529D01* +X164471724Y-77141885D01* +X164394673Y-77148897D01* +X164290665Y-77158363D01* +X164290662Y-77158364D01* +X164284526Y-77158922D01* +X164278620Y-77160660D01* +X164278616Y-77160661D01* +X164145278Y-77199905D01* +X164104202Y-77211994D01* +X163937621Y-77299080D01* +X163791128Y-77416864D01* +X163787170Y-77421582D01* +X163787167Y-77421584D01* +X163699797Y-77525708D01* +X163670302Y-77560859D01* +X163667338Y-77566251D01* +X163667335Y-77566255D01* +X163661176Y-77577459D01* +X163579746Y-77725580D01* +X163522909Y-77904752D01* +X163501956Y-78091552D01* +X163504259Y-78118973D01* +X163516930Y-78269869D01* +X163517685Y-78278865D01* +X163569497Y-78459555D01* +X163592567Y-78504444D01* +X163606500Y-78562036D01* +X163606500Y-92937207D01* +X163586498Y-93005328D01* +X163569595Y-93026303D01* +X162876301Y-93719596D01* +X162813989Y-93753621D01* +X162787206Y-93756500D01* +X151718404Y-93756500D01* +X151715008Y-93756869D01* +X151715007Y-93756869D01* +X151669957Y-93761763D01* +X151656349Y-93762500D01* +X151083600Y-93762500D01* +X151080354Y-93762837D01* +X151080350Y-93762837D01* +X150984692Y-93772762D01* +X150984688Y-93772763D01* +X150977834Y-93773474D01* +X150971298Y-93775655D01* +X150971296Y-93775655D01* +X150851621Y-93815582D01* +X150810054Y-93829450D01* +X150659652Y-93922522D01* +X150534695Y-94047697D01* +X150531898Y-94052235D01* +X150474647Y-94092824D01* +X150403724Y-94096054D01* +X150342313Y-94060428D01* +X150334938Y-94051932D01* +X150326902Y-94041793D01* +X150212171Y-93927261D01* +X150200760Y-93918249D01* +X150062757Y-93833184D01* +X150049576Y-93827037D01* +X149895290Y-93775862D01* +X149881914Y-93772995D01* +X149787562Y-93763328D01* +X149781145Y-93763000D01* +X149756115Y-93763000D01* +X149740876Y-93767475D01* +X149739671Y-93768865D01* +X149738000Y-93776548D01* +X149738000Y-95793339D01* +X149717998Y-95861460D01* +X149664342Y-95907953D01* +X149594068Y-95918057D01* +X149529488Y-95888563D01* +X149495591Y-95841557D01* +X149456069Y-95746141D01* +X149456068Y-95746139D01* +X149452909Y-95738513D01* +X149411138Y-95684076D01* +X149374821Y-95636748D01* +X149369798Y-95630202D01* +X149363252Y-95625179D01* +X149363249Y-95625176D01* +X149279296Y-95560756D01* +X149237429Y-95503418D01* +X149230000Y-95460794D01* +X149230000Y-93781116D01* +X149225525Y-93765877D01* +X149224135Y-93764672D01* +X149216452Y-93763001D01* +X149186905Y-93763001D01* +X149180386Y-93763338D01* +X149084794Y-93773257D01* +X149071400Y-93776149D01* +X148917216Y-93827588D01* +X148904037Y-93833762D01* +X148845803Y-93869798D01* +X148777351Y-93888636D01* +X148709581Y-93867475D01* +X148664010Y-93813034D01* +X148653500Y-93762654D01* +X148653500Y-91458912D01* +X148653792Y-91450342D01* +X148657209Y-91400224D01* +X148657209Y-91400220D01* +X148657725Y-91392648D01* +X148656167Y-91383718D01* +X148646739Y-91329701D01* +X148645776Y-91323175D01* +X148644669Y-91314025D01* +X148638102Y-91259758D01* +X148635419Y-91252657D01* +X148634778Y-91250048D01* +X148630315Y-91233738D01* +X148629550Y-91231202D01* +X148628243Y-91223716D01* +X148602556Y-91165200D01* +X148600065Y-91159096D01* +X148580173Y-91106452D01* +X148580172Y-91106451D01* +X148577487Y-91099344D01* +X148573183Y-91093081D01* +X148571946Y-91090715D01* +X148563701Y-91075903D01* +X148562368Y-91073649D01* +X148559315Y-91066695D01* +X148520413Y-91015998D01* +X148516541Y-91010668D01* +X148484661Y-90964280D01* +X148484656Y-90964275D01* +X148480357Y-90958019D01* +X148433829Y-90916564D01* +X148428554Y-90911584D01* +X147206450Y-89689480D01* +X147200596Y-89683215D01* +X147169716Y-89647817D01* +X147162561Y-89639615D01* +X147110280Y-89602871D01* +X147104986Y-89598939D01* +X147076515Y-89576615D01* +X147054718Y-89559524D01* +X147047802Y-89556401D01* +X147045516Y-89555017D01* +X147030835Y-89546643D01* +X147028475Y-89545378D01* +X147022261Y-89541010D01* +X147015182Y-89538250D01* +X147015180Y-89538249D01* +X146962725Y-89517798D01* +X146956656Y-89515247D01* +X146898427Y-89488955D01* +X146890960Y-89487571D01* +X146888405Y-89486770D01* +X146872152Y-89482141D01* +X146869572Y-89481478D01* +X146862491Y-89478718D01* +X146854960Y-89477727D01* +X146854958Y-89477726D01* +X146825339Y-89473827D01* +X146799139Y-89470378D01* +X146792641Y-89469348D01* +X146729814Y-89457704D01* +X146722234Y-89458141D01* +X146722233Y-89458141D01* +X146667608Y-89461291D01* +X146660354Y-89461500D01* +X134293101Y-89461500D01* +X134224980Y-89441498D01* +X134178487Y-89387842D01* +X134168383Y-89317568D01* +X134180014Y-89283964D01* +X134178539Y-89283307D01* +X134181223Y-89277279D01* +X134184527Y-89271556D01* +X134243542Y-89089928D01* +X134246814Y-89058803D01* +X134262814Y-88906565D01* +X134263504Y-88900000D01* +X134254878Y-88817927D01* +X134244232Y-88716635D01* +X134244232Y-88716633D01* +X134243542Y-88710072D01* +X134184527Y-88528444D01* +X134168394Y-88500500D01* +X134092341Y-88368774D01* +X134089040Y-88363056D01* +X134040864Y-88309551D01* +X134010146Y-88245544D01* +X134008500Y-88225241D01* +X134008500Y-86500000D01* +X139936681Y-86500000D01* +X139955928Y-86744557D01* +X139957082Y-86749364D01* +X139957083Y-86749370D01* +X139986194Y-86870624D01* +X140013195Y-86983092D01* +X140015088Y-86987663D01* +X140015089Y-86987665D01* +X140038132Y-87043294D01* +X140107073Y-87209732D01* +X140190262Y-87345485D01* +X140231283Y-87412425D01* +X140235248Y-87418896D01* +X140238463Y-87422660D01* +X140238465Y-87422663D01* +X140378084Y-87586134D01* +X140394567Y-87605433D01* +X140398323Y-87608641D01* +X140562508Y-87748869D01* +X140581104Y-87764752D01* +X140585327Y-87767340D01* +X140585330Y-87767342D01* +X140594945Y-87773234D01* +X140790268Y-87892927D01* +X140862238Y-87922738D01* +X141012335Y-87984911D01* +X141012337Y-87984912D01* +X141016908Y-87986805D01* +X141099563Y-88006649D01* +X141250630Y-88042917D01* +X141250636Y-88042918D01* +X141255443Y-88044072D01* +X141500000Y-88063319D01* +X141744557Y-88044072D01* +X141749364Y-88042918D01* +X141749370Y-88042917D01* +X141900437Y-88006649D01* +X141983092Y-87986805D01* +X141987663Y-87984912D01* +X141987665Y-87984911D01* +X142137762Y-87922738D01* +X142209732Y-87892927D01* +X142405055Y-87773234D01* +X142414670Y-87767342D01* +X142414673Y-87767340D01* +X142418896Y-87764752D01* +X142437493Y-87748869D01* +X142601677Y-87608641D01* +X142605433Y-87605433D01* +X142621916Y-87586134D01* +X142761535Y-87422663D01* +X142761537Y-87422660D01* +X142764752Y-87418896D01* +X142768718Y-87412425D01* +X142809738Y-87345485D01* +X142892927Y-87209732D01* +X142961868Y-87043294D01* +X142984911Y-86987665D01* +X142984912Y-86987663D01* +X142986805Y-86983092D01* +X143013806Y-86870624D01* +X143042917Y-86749370D01* +X143042918Y-86749364D01* +X143044072Y-86744557D01* +X143063319Y-86500000D01* +X157436681Y-86500000D01* +X157455928Y-86744557D01* +X157457082Y-86749364D01* +X157457083Y-86749370D01* +X157486194Y-86870624D01* +X157513195Y-86983092D01* +X157515088Y-86987663D01* +X157515089Y-86987665D01* +X157538132Y-87043294D01* +X157607073Y-87209732D01* +X157690262Y-87345485D01* +X157731283Y-87412425D01* +X157735248Y-87418896D01* +X157738463Y-87422660D01* +X157738465Y-87422663D01* +X157878084Y-87586134D01* +X157894567Y-87605433D01* +X157898323Y-87608641D01* +X158062508Y-87748869D01* +X158081104Y-87764752D01* +X158085327Y-87767340D01* +X158085330Y-87767342D01* +X158094945Y-87773234D01* +X158290268Y-87892927D01* +X158362238Y-87922738D01* +X158512335Y-87984911D01* +X158512337Y-87984912D01* +X158516908Y-87986805D01* +X158599563Y-88006649D01* +X158750630Y-88042917D01* +X158750636Y-88042918D01* +X158755443Y-88044072D01* +X159000000Y-88063319D01* +X159244557Y-88044072D01* +X159249364Y-88042918D01* +X159249370Y-88042917D01* +X159400437Y-88006649D01* +X159483092Y-87986805D01* +X159487663Y-87984912D01* +X159487665Y-87984911D01* +X159637762Y-87922738D01* +X159709732Y-87892927D01* +X159905055Y-87773234D01* +X159914670Y-87767342D01* +X159914673Y-87767340D01* +X159918896Y-87764752D01* +X159937493Y-87748869D01* +X160101677Y-87608641D01* +X160105433Y-87605433D01* +X160121916Y-87586134D01* +X160261535Y-87422663D01* +X160261537Y-87422660D01* +X160264752Y-87418896D01* +X160268718Y-87412425D01* +X160309738Y-87345485D01* +X160392927Y-87209732D01* +X160461868Y-87043294D01* +X160484911Y-86987665D01* +X160484912Y-86987663D01* +X160486805Y-86983092D01* +X160513806Y-86870624D01* +X160542917Y-86749370D01* +X160542918Y-86749364D01* +X160544072Y-86744557D01* +X160563319Y-86500000D01* +X160544072Y-86255443D01* +X160542700Y-86249725D01* +X160487960Y-86021720D01* +X160486805Y-86016908D01* +X160479739Y-85999848D01* +X160447292Y-85921517D01* +X160392927Y-85790268D01* +X160264752Y-85581104D01* +X160241881Y-85554325D01* +X160108641Y-85398323D01* +X160105433Y-85394567D01* +X160101677Y-85391359D01* +X159922663Y-85238465D01* +X159922660Y-85238463D01* +X159918896Y-85235248D01* +X159914673Y-85232660D01* +X159914670Y-85232658D01* +X159815782Y-85172060D01* +X159709732Y-85107073D01* +X159549091Y-85040533D01* +X159487665Y-85015089D01* +X159487663Y-85015088D01* +X159483092Y-85013195D01* +X159400437Y-84993351D01* +X159249370Y-84957083D01* +X159249364Y-84957082D01* +X159244557Y-84955928D01* +X159000000Y-84936681D01* +X158755443Y-84955928D01* +X158750636Y-84957082D01* +X158750630Y-84957083D01* +X158599563Y-84993351D01* +X158516908Y-85013195D01* +X158512337Y-85015088D01* +X158512335Y-85015089D01* +X158450909Y-85040533D01* +X158290268Y-85107073D01* +X158184218Y-85172060D01* +X158085330Y-85232658D01* +X158085327Y-85232660D01* +X158081104Y-85235248D01* +X158077340Y-85238463D01* +X158077337Y-85238465D01* +X157898323Y-85391359D01* +X157894567Y-85394567D01* +X157891359Y-85398323D01* +X157758120Y-85554325D01* +X157735248Y-85581104D01* +X157607073Y-85790268D01* +X157552708Y-85921517D01* +X157520262Y-85999848D01* +X157513195Y-86016908D01* +X157512040Y-86021720D01* +X157457301Y-86249725D01* +X157455928Y-86255443D01* +X157436681Y-86500000D01* +X143063319Y-86500000D01* +X143044072Y-86255443D01* +X143042700Y-86249725D01* +X142987960Y-86021720D01* +X142986805Y-86016908D01* +X142979739Y-85999848D01* +X142947292Y-85921517D01* +X142892927Y-85790268D01* +X142764752Y-85581104D01* +X142741881Y-85554325D01* +X142608641Y-85398323D01* +X142605433Y-85394567D01* +X142601677Y-85391359D01* +X142422663Y-85238465D01* +X142422660Y-85238463D01* +X142418896Y-85235248D01* +X142414673Y-85232660D01* +X142414670Y-85232658D01* +X142315782Y-85172060D01* +X142209732Y-85107073D01* +X142049091Y-85040533D01* +X141987665Y-85015089D01* +X141987663Y-85015088D01* +X141983092Y-85013195D01* +X141900437Y-84993351D01* +X141749370Y-84957083D01* +X141749364Y-84957082D01* +X141744557Y-84955928D01* +X141500000Y-84936681D01* +X141255443Y-84955928D01* +X141250636Y-84957082D01* +X141250630Y-84957083D01* +X141099563Y-84993351D01* +X141016908Y-85013195D01* +X141012337Y-85015088D01* +X141012335Y-85015089D01* +X140950909Y-85040533D01* +X140790268Y-85107073D01* +X140684218Y-85172060D01* +X140585330Y-85232658D01* +X140585327Y-85232660D01* +X140581104Y-85235248D01* +X140577340Y-85238463D01* +X140577337Y-85238465D01* +X140398323Y-85391359D01* +X140394567Y-85394567D01* +X140391359Y-85398323D01* +X140258120Y-85554325D01* +X140235248Y-85581104D01* +X140107073Y-85790268D01* +X140052708Y-85921517D01* +X140020262Y-85999848D01* +X140013195Y-86016908D01* +X140012040Y-86021720D01* +X139957301Y-86249725D01* +X139955928Y-86255443D01* +X139936681Y-86500000D01* +X134008500Y-86500000D01* +X134008500Y-85172060D01* +X134009059Y-85160203D01* +X134010789Y-85152463D01* +X134008562Y-85081599D01* +X134008500Y-85077641D01* +X134008500Y-85048568D01* +X134007947Y-85044189D01* +X134007014Y-85032346D01* +X134005812Y-84994089D01* +X134005812Y-84994088D01* +X134005563Y-84986169D01* +X133999579Y-84965571D01* +X133995571Y-84946218D01* +X133995132Y-84942743D01* +X133992882Y-84924936D01* +X133975875Y-84881982D01* +X133972029Y-84870747D01* +X133961358Y-84834016D01* +X133961357Y-84834013D01* +X133959145Y-84826400D01* +X133948225Y-84807935D01* +X133939534Y-84790195D01* +X133931635Y-84770244D01* +X133904482Y-84732871D01* +X133897967Y-84722952D01* +X133878493Y-84690023D01* +X133878490Y-84690019D01* +X133874453Y-84683193D01* +X133859289Y-84668029D01* +X133846448Y-84652995D01* +X133838501Y-84642057D01* +X133833841Y-84635643D01* +X133798247Y-84606197D01* +X133789468Y-84598208D01* +X133243655Y-84052395D01* +X133235665Y-84043615D01* +X133235663Y-84043613D01* +X133231416Y-84036920D01* +X133179742Y-83988395D01* +X133176901Y-83985641D01* +X133156333Y-83965073D01* +X133152826Y-83962353D01* +X133143804Y-83954647D01* +X133133529Y-83944998D01* +X133110133Y-83923028D01* +X133103181Y-83919206D01* +X133091342Y-83912697D01* +X133074818Y-83901843D01* +X133064132Y-83893555D01* +X133057868Y-83888696D01* +X133050596Y-83885549D01* +X133050594Y-83885548D01* +X133015465Y-83870346D01* +X133004805Y-83865124D01* +X132971284Y-83846695D01* +X132971282Y-83846694D01* +X132964337Y-83842876D01* +X132943559Y-83837541D01* +X132924869Y-83831142D01* +X132905176Y-83822620D01* +X132859552Y-83815394D01* +X132847929Y-83812987D01* +X132819928Y-83805798D01* +X132803188Y-83801500D01* +X132781741Y-83801500D01* +X132762031Y-83799949D01* +X132748677Y-83797834D01* +X132740848Y-83796594D01* +X132732956Y-83797340D01* +X132732954Y-83797340D01* +X132713263Y-83799201D01* +X132643562Y-83785697D01* +X132592227Y-83736654D01* +X132575556Y-83667643D01* +X132598841Y-83600573D01* +X132612312Y-83584664D01* +X133107258Y-83089719D01* +X133115537Y-83082185D01* +X133122018Y-83078072D01* +X133168644Y-83028420D01* +X133171398Y-83025579D01* +X133191135Y-83005842D01* +X133193615Y-83002645D01* +X133201320Y-82993623D01* +X133226159Y-82967172D01* +X133231586Y-82961393D01* +X133235405Y-82954447D01* +X133235407Y-82954444D01* +X133241348Y-82943638D01* +X133252199Y-82927119D01* +X133259758Y-82917373D01* +X133264614Y-82911113D01* +X133267759Y-82903844D01* +X133267762Y-82903840D01* +X133282174Y-82870535D01* +X133287391Y-82859885D01* +X133308695Y-82821132D01* +X133313733Y-82801509D01* +X133320137Y-82782806D01* +X133325033Y-82771492D01* +X133325033Y-82771491D01* +X133328181Y-82764217D01* +X133329420Y-82756394D01* +X133329423Y-82756384D01* +X133335099Y-82720548D01* +X133337505Y-82708928D01* +X133346528Y-82673783D01* +X133346528Y-82673782D01* +X133348500Y-82666102D01* +X133348500Y-82645848D01* +X133350051Y-82626137D01* +X133351980Y-82613958D01* +X133353220Y-82606129D01* +X133349059Y-82562110D01* +X133348500Y-82550253D01* +X133348500Y-79453768D01* +X133349027Y-79442585D01* +X133350702Y-79435092D01* +X133348562Y-79367001D01* +X133348500Y-79363044D01* +X133348500Y-79335144D01* +X133347996Y-79331153D01* +X133347063Y-79319311D01* +X133345923Y-79283036D01* +X133345674Y-79275111D01* +X133343461Y-79267493D01* +X133340021Y-79255652D01* +X133336012Y-79236293D01* +X133335846Y-79234983D01* +X133333474Y-79216203D01* +X133330558Y-79208837D01* +X133330556Y-79208831D01* +X133317200Y-79175098D01* +X133313355Y-79163868D01* +X133303230Y-79129017D01* +X133303230Y-79129016D01* +X133301019Y-79121407D01* +X133290705Y-79103966D01* +X133282008Y-79086213D01* +X133277472Y-79074758D01* +X133274552Y-79067383D01* +X133248563Y-79031612D01* +X133242047Y-79021692D01* +X133223578Y-78990463D01* +X133219542Y-78983638D01* +X133205221Y-78969317D01* +X133192380Y-78954283D01* +X133185132Y-78944307D01* +X133180472Y-78937893D01* +X133146407Y-78909712D01* +X133137626Y-78901722D01* +X132583647Y-78347742D01* +X132576113Y-78339463D01* +X132572000Y-78332982D01* +X132522348Y-78286356D01* +X132519507Y-78283602D01* +X132499770Y-78263865D01* +X132496573Y-78261385D01* +X132487551Y-78253680D01* +X132471455Y-78238565D01* +X132455321Y-78223414D01* +X132448375Y-78219595D01* +X132448372Y-78219593D01* +X132437566Y-78213652D01* +X132421047Y-78202801D01* +X132420583Y-78202441D01* +X132405041Y-78190386D01* +X132397772Y-78187241D01* +X132397768Y-78187238D01* +X132364463Y-78172826D01* +X132353813Y-78167609D01* +X132315060Y-78146305D01* +X132295437Y-78141267D01* +X132276734Y-78134863D01* +X132265420Y-78129967D01* +X132265419Y-78129967D01* +X132258145Y-78126819D01* +X132250322Y-78125580D01* +X132250312Y-78125577D01* +X132214476Y-78119901D01* +X132202856Y-78117495D01* +X132167711Y-78108472D01* +X132167710Y-78108472D01* +X132160030Y-78106500D01* +X132139776Y-78106500D01* +X132120065Y-78104949D01* +X132107886Y-78103020D01* +X132100057Y-78101780D01* +X132070786Y-78104547D01* +X132056039Y-78105941D01* +X132044181Y-78106500D01* +X125808049Y-78106500D01* +X125796866Y-78105973D01* +X125789373Y-78104298D01* +X125781447Y-78104547D01* +X125781446Y-78104547D01* +X125721283Y-78106438D01* +X125717325Y-78106500D01* +X125689426Y-78106500D01* +X125685436Y-78107004D01* +X125673602Y-78107936D01* +X125629393Y-78109326D01* +X125621779Y-78111538D01* +X125621774Y-78111539D01* +X125609941Y-78114977D01* +X125590578Y-78118988D01* +X125570485Y-78121526D01* +X125563118Y-78124443D01* +X125563113Y-78124444D01* +X125529374Y-78137802D01* +X125518147Y-78141646D01* +X125475689Y-78153982D01* +X125468863Y-78158019D01* +X125458254Y-78164293D01* +X125440506Y-78172988D01* +X125421665Y-78180448D01* +X125415249Y-78185110D01* +X125415248Y-78185110D01* +X125385895Y-78206436D01* +X125375975Y-78212952D01* +X125344747Y-78231420D01* +X125344744Y-78231422D01* +X125337920Y-78235458D01* +X125323599Y-78249779D01* +X125308566Y-78262619D01* +X125292175Y-78274528D01* +X125283499Y-78285016D01* +X125263984Y-78308605D01* +X125255994Y-78317384D01* +X124067747Y-79505630D01* +X124059461Y-79513170D01* +X124052982Y-79517282D01* +X124047557Y-79523059D01* +X124006357Y-79566933D01* +X124003602Y-79569775D01* +X123983865Y-79589512D01* +X123981385Y-79592709D01* +X123973682Y-79601729D01* +X123943414Y-79633961D01* +X123939595Y-79640907D01* +X123939593Y-79640910D01* +X123933652Y-79651716D01* +X123922801Y-79668235D01* +X123910386Y-79684241D01* +X123907241Y-79691510D01* +X123907238Y-79691514D01* +X123892826Y-79724819D01* +X123887609Y-79735469D01* +X123866305Y-79774222D01* +X123864334Y-79781897D01* +X123864334Y-79781898D01* +X123861267Y-79793844D01* +X123854863Y-79812548D01* +X123846819Y-79831137D01* +X123845580Y-79838960D01* +X123845577Y-79838970D01* +X123839901Y-79874806D01* +X123837495Y-79886426D01* +X123826500Y-79929252D01* +X123826500Y-79949506D01* +X123824949Y-79969216D01* +X123821780Y-79989225D01* +X123822526Y-79997117D01* +X123825941Y-80033243D01* +X123826500Y-80045101D01* +X123826500Y-92631233D01* +X123825973Y-92642416D01* +X123824298Y-92649909D01* +X123824547Y-92657835D01* +X123824547Y-92657836D01* +X123826438Y-92717986D01* +X123826500Y-92721945D01* +X123826500Y-92749856D01* +X123826997Y-92753790D01* +X123826997Y-92753791D01* +X123827005Y-92753856D01* +X123827938Y-92765693D01* +X123829327Y-92809889D01* +X123834978Y-92829339D01* +X123838987Y-92848700D01* +X123841526Y-92868797D01* +X123844445Y-92876168D01* +X123844445Y-92876170D01* +X123857804Y-92909912D01* +X123861649Y-92921142D01* +X123865292Y-92933680D01* +X123873982Y-92963593D01* +X123878015Y-92970412D01* +X123878017Y-92970417D01* +X123884293Y-92981028D01* +X123892988Y-92998776D01* +X123900448Y-93017617D01* +X123905110Y-93024033D01* +X123905110Y-93024034D01* +X123926436Y-93053387D01* +X123932952Y-93063307D01* +X123949571Y-93091407D01* +X123955458Y-93101362D01* +X123969779Y-93115683D01* +X123982619Y-93130716D01* +X123994528Y-93147107D01* +X124000634Y-93152158D01* +X124028605Y-93175298D01* +X124037384Y-93183288D01* +X124591343Y-93737247D01* +X124598887Y-93745537D01* +X124603000Y-93752018D01* +X124608777Y-93757443D01* +X124652667Y-93798658D01* +X124655509Y-93801413D01* +X124671037Y-93816941D01* +X124705063Y-93879253D01* +X124699998Y-93950068D01* +X124665022Y-94000765D01* +X124627478Y-94033690D01* +X124533395Y-94153034D01* +X124475515Y-94194146D01* +X124404595Y-94197440D01* +X124343152Y-94161869D01* +X124333488Y-94150416D01* +X124265758Y-94059715D01* +X124265758Y-94059714D01* +X124262305Y-94055091D01* +X124138373Y-93940529D01* +X124116943Y-93920719D01* +X124116940Y-93920717D01* +X124112703Y-93916800D01* +X124048026Y-93875992D01* +X123945288Y-93811169D01* +X123945283Y-93811167D01* +X123940404Y-93808088D01* +X123751180Y-93732595D01* +X123551366Y-93692849D01* +X123545592Y-93692773D01* +X123545588Y-93692773D01* +X123442452Y-93691424D01* +X123347655Y-93690183D01* +X123341958Y-93691162D01* +X123341957Y-93691162D01* +X123152567Y-93723705D01* +X123146870Y-93724684D01* +X122955734Y-93795198D01* +X122950773Y-93798150D01* +X122950772Y-93798150D01* +X122891886Y-93833184D01* +X122780649Y-93899363D01* +X122627478Y-94033690D01* +X122533395Y-94153034D01* +X122475515Y-94194146D01* +X122404595Y-94197440D01* +X122343152Y-94161869D01* +X122333488Y-94150416D01* +X122265758Y-94059715D01* +X122265758Y-94059714D01* +X122262305Y-94055091D01* +X122138373Y-93940529D01* +X122116943Y-93920719D01* +X122116940Y-93920717D01* +X122112703Y-93916800D01* +X122048026Y-93875992D01* +X121945288Y-93811169D01* +X121945283Y-93811167D01* +X121940404Y-93808088D01* +X121751180Y-93732595D01* +X121551366Y-93692849D01* +X121545592Y-93692773D01* +X121545588Y-93692773D01* +X121442452Y-93691424D01* +X121347655Y-93690183D01* +X121341958Y-93691162D01* +X121341957Y-93691162D01* +X121152567Y-93723705D01* +X121146870Y-93724684D01* +X120955734Y-93795198D01* +X120950773Y-93798150D01* +X120950772Y-93798150D01* +X120891886Y-93833184D01* +X120780649Y-93899363D01* +X120627478Y-94033690D01* +X120533395Y-94153034D01* +X120475515Y-94194146D01* +X120404595Y-94197440D01* +X120343152Y-94161869D01* +X120333488Y-94150416D01* +X120265758Y-94059715D01* +X120265758Y-94059714D01* +X120262305Y-94055091D01* +X120138373Y-93940529D01* +X120116943Y-93920719D01* +X120116940Y-93920717D01* +X120112703Y-93916800D01* +X120048026Y-93875992D01* +X119945288Y-93811169D01* +X119945283Y-93811167D01* +X119940404Y-93808088D01* +X119751180Y-93732595D01* +X119551366Y-93692849D01* +X119545592Y-93692773D01* +X119545588Y-93692773D01* +X119442452Y-93691424D01* +X119347655Y-93690183D01* +X119341958Y-93691162D01* +X119341957Y-93691162D01* +X119152567Y-93723705D01* +X119146870Y-93724684D01* +X118955734Y-93795198D01* +X118950773Y-93798150D01* +X118950772Y-93798150D01* +X118891886Y-93833184D01* +X118780649Y-93899363D01* +X118627478Y-94033690D01* +X118623911Y-94038215D01* +X118623906Y-94038220D01* +X118537331Y-94148040D01* +X118501351Y-94193681D01* +X118498662Y-94198792D01* +X118498660Y-94198795D01* +X118462349Y-94267811D01* +X118406492Y-94373978D01* +X118346078Y-94568543D01* +X118322132Y-94770859D01* +X118335457Y-94974151D01* +X118355684Y-95053794D01* +X118366018Y-95094485D01* +X118363400Y-95165433D01* +X118322839Y-95223703D01* +X118257215Y-95250794D01* +X118243895Y-95251500D01* +X113738200Y-95251500D01* +X113670079Y-95231498D01* +X113650853Y-95215157D01* +X113650580Y-95215460D01* +X113645668Y-95211037D01* +X113641253Y-95206134D01* +X113619671Y-95190454D01* +X113492094Y-95097763D01* +X113492093Y-95097762D01* +X113486752Y-95093882D01* +X113480724Y-95091198D01* +X113480722Y-95091197D01* +X113318319Y-95018891D01* +X113318318Y-95018891D01* +X113312288Y-95016206D01* +X113218887Y-94996353D01* +X113131944Y-94977872D01* +X113131939Y-94977872D01* +X113125487Y-94976500D01* +X112934513Y-94976500D01* +X112928061Y-94977872D01* +X112928056Y-94977872D01* +X112841113Y-94996353D01* +X112747712Y-95016206D01* +X112741682Y-95018891D01* +X112741681Y-95018891D01* +X112579278Y-95091197D01* +X112579276Y-95091198D01* +X112573248Y-95093882D01* +X112418747Y-95206134D01* +X112414326Y-95211044D01* +X112414325Y-95211045D01* +X112338164Y-95295631D01* +X112290960Y-95348056D01* +X112258181Y-95404831D01* +X112201262Y-95503418D01* +X112195473Y-95513444D01* +X112136458Y-95695072D01* +X112135768Y-95701633D01* +X112135768Y-95701635D01* +X112125170Y-95802474D01* +X112116496Y-95885000D01* +X112117186Y-95891565D01* +X112134808Y-96059225D01* +X112136458Y-96074928D01* +X112195473Y-96256556D01* +X112198776Y-96262278D01* +X112198777Y-96262279D01* +X112205055Y-96273152D01* +X112290960Y-96421944D01* +X112295378Y-96426851D01* +X112295379Y-96426852D01* +X112414325Y-96558955D01* +X112418747Y-96563866D01* +X112573248Y-96676118D01* +X112579276Y-96678802D01* +X112579278Y-96678803D01* +X112741681Y-96751109D01* +X112747712Y-96753794D01* +X112841112Y-96773647D01* +X112928056Y-96792128D01* +X112928061Y-96792128D01* +X112934513Y-96793500D01* +X113125487Y-96793500D01* +X113131939Y-96792128D01* +X113131944Y-96792128D01* +X113218888Y-96773647D01* +X113312288Y-96753794D01* +X113318319Y-96751109D01* +X113480722Y-96678803D01* +X113480724Y-96678802D01* +X113486752Y-96676118D01* +X113556850Y-96625189D01* +X113629771Y-96572208D01* +X113641253Y-96563866D01* +X113645668Y-96558963D01* +X113650580Y-96554540D01* +X113651705Y-96555789D01* +X113705014Y-96522949D01* +X113738200Y-96518500D01* +X118420931Y-96518500D01* +X118489052Y-96538502D01* +X118535545Y-96592158D01* +X118545649Y-96662432D01* +X118540764Y-96683436D01* +X118511425Y-96773733D01* +X118486458Y-96850572D01* +X118475540Y-96954456D01* +X118474046Y-96968670D01* +X118447033Y-97034327D01* +X118388812Y-97074957D01* +X118348736Y-97081500D01* +X112423927Y-97081500D01* +X112415358Y-97081208D01* +X112365225Y-97077790D01* +X112365221Y-97077790D01* +X112357648Y-97077274D01* +X112294681Y-97088264D01* +X112288169Y-97089224D01* +X112224758Y-97096898D01* +X112217657Y-97099581D01* +X112215048Y-97100222D01* +X112198728Y-97104687D01* +X112196195Y-97105452D01* +X112188717Y-97106757D01* +X112130190Y-97132448D01* +X112124108Y-97134930D01* +X112103753Y-97142622D01* +X112071449Y-97154828D01* +X112071447Y-97154829D01* +X112064344Y-97157513D01* +X112058085Y-97161814D01* +X112055720Y-97163051D01* +X112040948Y-97171273D01* +X112038656Y-97172628D01* +X112031695Y-97175684D01* +X112025668Y-97180309D01* +X112025664Y-97180311D01* +X111980987Y-97214593D01* +X111975662Y-97218462D01* +X111923019Y-97254643D01* +X111917967Y-97260313D01* +X111917966Y-97260314D01* +X111881580Y-97301153D01* +X111876600Y-97306429D01* +X111279465Y-97903565D01* +X111273198Y-97909419D01* +X111235340Y-97942444D01* +X111235337Y-97942447D01* +X111229615Y-97947439D01* +X111209191Y-97976500D01* +X111192872Y-97999719D01* +X111188939Y-98005014D01* +X111149524Y-98055282D01* +X111146401Y-98062198D01* +X111145017Y-98064484D01* +X111136643Y-98079165D01* +X111135378Y-98081525D01* +X111131010Y-98087739D01* +X111128250Y-98094818D01* +X111128249Y-98094820D01* +X111107798Y-98147275D01* +X111105247Y-98153344D01* +X111078955Y-98211573D01* +X111077571Y-98219040D01* +X111076770Y-98221595D01* +X111072141Y-98237848D01* +X111071478Y-98240428D01* +X111068718Y-98247509D01* +X111067727Y-98255040D01* +X111067726Y-98255042D01* +X111060379Y-98310852D01* +X111059348Y-98317359D01* +X111047704Y-98380186D01* +X111048141Y-98387766D01* +X111048141Y-98387767D01* +X111051291Y-98442392D01* +X111051500Y-98449646D01* +X111051500Y-104111088D01* +X111051208Y-104119658D01* +X111048611Y-104157761D01* +X111047275Y-104177352D01* +X111057870Y-104238056D01* +X111058261Y-104240299D01* +X111059223Y-104246821D01* +X111066898Y-104310242D01* +X111069581Y-104317343D01* +X111070222Y-104319952D01* +X111074685Y-104336262D01* +X111075450Y-104338798D01* +X111076757Y-104346284D01* +X111099338Y-104397723D01* +X111102442Y-104404795D01* +X111104933Y-104410899D01* +X111127513Y-104470656D01* +X111131817Y-104476919D01* +X111133054Y-104479285D01* +X111141299Y-104494097D01* +X111142632Y-104496352D01* +X111145685Y-104503305D01* +X111153485Y-104513470D01* +X111180286Y-104548397D01* +X111205887Y-104614617D01* +X111191623Y-104684166D01* +X111158508Y-104722289D01* +X111158998Y-104722833D01* +X111154584Y-104726808D01* +X111154382Y-104727040D01* +X111148747Y-104731134D01* +X111144326Y-104736044D01* +X111144325Y-104736045D01* +X111053853Y-104836525D01* +X111020960Y-104873056D01* +X110925473Y-105038444D01* +X110866458Y-105220072D01* +X110865768Y-105226633D01* +X110865768Y-105226635D01* +X110847828Y-105397331D01* +X110846496Y-105410000D01* +X110258500Y-105410000D01* +X110258500Y-96053250D01* +X110260246Y-96032345D01* +X110262770Y-96017344D01* +X110262770Y-96017341D01* +X110263576Y-96012552D01* +X110263729Y-96000000D01* +X110263039Y-95995185D01* +X110263039Y-95995178D01* +X110260427Y-95976936D01* +X110259170Y-95957111D01* +X110270192Y-95250794D01* +X110277336Y-94793032D01* +X110277458Y-94789132D01* +X110278315Y-94770859D01* +X110310264Y-94088873D01* +X110333853Y-93585364D01* +X110334098Y-93581439D01* +X110428030Y-92379976D01* +X110428398Y-92376061D01* +X110529212Y-91456803D01* +X110559775Y-91178117D01* +X110560263Y-91174231D01* +X110562560Y-91157988D01* +X110668956Y-90405385D01* +X110728951Y-89981009D01* +X110729562Y-89977124D01* +X110804188Y-89546643D01* +X110935413Y-88789682D01* +X110936131Y-88785888D01* +X111178931Y-87605467D01* +X111179783Y-87601628D01* +X111210883Y-87471197D01* +X111459305Y-86429333D01* +X111460270Y-86425549D01* +X111462970Y-86415613D01* +X111654202Y-85711728D01* +X111776219Y-85262610D01* +X111777309Y-85258832D01* +X112129390Y-84106323D01* +X112130597Y-84102580D01* +X112283438Y-83652985D01* +X112518486Y-82961574D01* +X112519803Y-82957888D01* +X112525149Y-82943638D01* +X112943114Y-81829521D01* +X112944543Y-81825887D01* +X112966398Y-81772738D01* +X113213257Y-81172382D01* +X113402835Y-80711335D01* +X113404387Y-80707722D01* +X113873756Y-79660399D01* +X113897240Y-79608000D01* +X113898901Y-79604442D01* +X113993239Y-79410405D01* +X114425840Y-78520615D01* +X114427588Y-78517159D01* +X114988096Y-77450288D01* +X114989979Y-77446836D01* +X115583484Y-76398013D01* +X115585474Y-76394621D01* +X116211409Y-75364842D01* +X116213503Y-75361514D01* +X116871305Y-74351710D01* +X116873503Y-74348450D01* +X117088167Y-74040381D01* +X117562449Y-73359730D01* +X117564742Y-73356546D01* +X118284239Y-72389760D01* +X118286624Y-72386657D01* +X118506244Y-72110016D01* +X118616275Y-71971416D01* +X119035913Y-71442824D01* +X119038405Y-71439783D01* +X119816806Y-70519760D01* +X119819393Y-70516798D01* +X120242968Y-70046726D01* +X120305014Y-69977869D01* +X125636689Y-69977869D01* +X125653238Y-70264883D01* +X125654063Y-70269088D01* +X125654064Y-70269096D01* +X125673821Y-70369798D01* +X125708586Y-70546995D01* +X125709973Y-70551045D01* +X125709974Y-70551050D01* +X125785557Y-70771807D01* +X125801710Y-70818986D01* +X125803637Y-70822817D01* +X125891310Y-70997135D01* +X125930885Y-71075822D01* +X126093721Y-71312750D01* +X126096608Y-71315923D01* +X126096609Y-71315924D01* +X126137329Y-71360675D01* +X126287206Y-71525388D01* +X126290501Y-71528143D01* +X126290502Y-71528144D01* +X126497402Y-71701138D01* +X126507759Y-71709798D01* +X126751298Y-71862571D01* +X127013318Y-71980877D01* +X127072778Y-71998490D01* +X127284857Y-72061311D01* +X127284862Y-72061312D01* +X127288970Y-72062529D01* +X127293204Y-72063177D01* +X127293209Y-72063178D01* +X127541811Y-72101219D01* +X127573153Y-72106015D01* +X127719485Y-72108314D01* +X127856317Y-72110464D01* +X127856323Y-72110464D01* +X127860608Y-72110531D01* +X127864860Y-72110016D01* +X127864868Y-72110016D01* +X128141756Y-72076508D01* +X128141761Y-72076507D01* +X128146017Y-72075992D01* +X128401558Y-72008952D01* +X128419954Y-72004126D01* +X128419955Y-72004126D01* +X128424097Y-72003039D01* +X128689704Y-71893021D01* +X128834671Y-71808309D01* +X128934219Y-71750138D01* +X128934220Y-71750137D01* +X128937922Y-71747974D01* +X129164159Y-71570582D01* +X129205285Y-71528144D01* +X129361244Y-71367206D01* +X129364227Y-71364128D01* +X129366760Y-71360680D01* +X129366764Y-71360675D01* +X129531887Y-71135886D01* +X129534425Y-71132431D01* +X129607885Y-70997135D01* +X129669554Y-70883555D01* +X129669555Y-70883553D01* +X129671604Y-70879779D01* +X129773225Y-70610848D01* +X129811449Y-70443953D01* +X129836449Y-70334797D01* +X129836450Y-70334793D01* +X129837407Y-70330613D01* +X129843577Y-70261487D01* +X129862743Y-70046726D01* +X129862743Y-70046724D01* +X129862963Y-70044260D01* +X129863427Y-70000000D01* +X129847956Y-69773064D01* +X129844165Y-69717452D01* +X129844164Y-69717446D01* +X129843873Y-69713175D01* +X129839336Y-69691264D01* +X129809479Y-69547091D01* +X129785574Y-69431658D01* +X129689607Y-69160657D01* +X129557750Y-68905188D01* +X129544488Y-68886317D01* +X129394904Y-68673482D01* +X129392441Y-68669977D01* +X129196740Y-68459378D01* +X128974268Y-68277287D01* +X128729142Y-68127073D01* +X128711048Y-68119130D01* +X128469830Y-68013243D01* +X128465898Y-68011517D01* +X128439963Y-68004129D01* +X128193534Y-67933932D01* +X128193535Y-67933932D01* +X128189406Y-67932756D01* +X127961467Y-67900316D01* +X127909036Y-67892854D01* +X127909034Y-67892854D01* +X127904784Y-67892249D01* +X127900495Y-67892227D01* +X127900488Y-67892226D01* +X127621583Y-67890765D01* +X127621576Y-67890765D01* +X127617297Y-67890743D01* +X127613053Y-67891302D01* +X127613049Y-67891302D01* +X127487660Y-67907810D01* +X127332266Y-67928268D01* +X127328126Y-67929401D01* +X127328124Y-67929401D01* +X127251311Y-67950415D01* +X127054964Y-68004129D01* +X127051016Y-68005813D01* +X126794476Y-68115237D01* +X126794472Y-68115239D01* +X126790524Y-68116923D01* +X126711107Y-68164453D01* +X126547521Y-68262357D01* +X126547517Y-68262360D01* +X126543839Y-68264561D01* +X126319472Y-68444313D01* +X126121577Y-68652851D01* +X125953814Y-68886317D01* +X125819288Y-69140392D01* +X125720489Y-69410373D01* +X125659245Y-69691264D01* +X125652807Y-69773064D01* +X125637196Y-69971428D01* +X125637195Y-69971428D01* +X125637196Y-69971430D01* +X125636689Y-69977869D01* +X120305014Y-69977869D01* +X120626107Y-69621530D01* +X120628738Y-69618699D01* +X121266909Y-68953448D01* +X121463041Y-68748994D01* +X121465807Y-68746200D01* +X122326768Y-67903023D01* +X122329620Y-67900316D01* +X123216526Y-67084366D01* +X123219461Y-67081749D01* +X124131349Y-66293912D01* +X124134364Y-66291388D01* +X124447034Y-66037853D01* +X125070424Y-65532364D01* +X125073509Y-65529941D01* +X126032786Y-64800505D01* +X126035953Y-64798174D01* +X127017521Y-64099028D01* +X127020759Y-64096797D01* +X127736749Y-63619775D01* +X127872037Y-63529641D01* +X127941898Y-63508500D01* +X132115500Y-63508500D01* +X132183621Y-63528502D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X151966121Y-122321002D02* +G01* +X152012614Y-122374658D01* +X152024000Y-122427000D01* +X152024000Y-123769884D01* +X152028475Y-123785123D01* +X152029865Y-123786328D01* +X152037548Y-123787999D01* +X152067095Y-123787999D01* +X152073612Y-123787662D01* +X152120775Y-123782768D01* +X152190596Y-123795633D01* +X152242379Y-123844203D01* +X152254776Y-123872942D01* +X152259462Y-123889073D01* +X152263495Y-123895892D01* +X152263497Y-123895897D01* +X152269773Y-123906508D01* +X152278468Y-123924256D01* +X152285928Y-123943097D01* +X152290590Y-123949513D01* +X152290590Y-123949514D01* +X152311916Y-123978867D01* +X152318432Y-123988787D01* +X152340938Y-124026842D01* +X152355259Y-124041163D01* +X152368099Y-124056196D01* +X152380008Y-124072587D01* +X152398974Y-124088277D01* +X152414085Y-124100778D01* +X152422864Y-124108768D01* +X152999595Y-124685499D01* +X153033621Y-124747811D01* +X153036500Y-124774594D01* +X153036500Y-128191233D01* +X153035973Y-128202416D01* +X153034298Y-128209909D01* +X153034547Y-128217835D01* +X153034547Y-128217836D01* +X153036438Y-128277986D01* +X153036500Y-128281945D01* +X153036500Y-128309856D01* +X153036997Y-128313790D01* +X153036997Y-128313791D01* +X153037005Y-128313856D01* +X153037938Y-128325693D01* +X153039327Y-128369889D01* +X153044978Y-128389339D01* +X153048987Y-128408700D01* +X153051526Y-128428797D01* +X153054445Y-128436168D01* +X153054445Y-128436170D01* +X153067804Y-128469912D01* +X153071649Y-128481142D01* +X153081771Y-128515983D01* +X153083982Y-128523593D01* +X153088015Y-128530412D01* +X153088017Y-128530417D01* +X153094293Y-128541028D01* +X153102988Y-128558776D01* +X153110448Y-128577617D01* +X153115110Y-128584033D01* +X153115110Y-128584034D01* +X153136436Y-128613387D01* +X153142952Y-128623307D01* +X153160202Y-128652474D01* +X153165458Y-128661362D01* +X153179779Y-128675683D01* +X153192619Y-128690716D01* +X153204528Y-128707107D01* +X153210634Y-128712158D01* +X153238605Y-128735298D01* +X153247384Y-128743288D01* +X153285001Y-128780905D01* +X153319027Y-128843217D01* +X153313962Y-128914032D01* +X153271415Y-128970868D01* +X153204895Y-128995679D01* +X153195906Y-128996000D01* +X145184095Y-128996000D01* +X145115974Y-128975998D01* +X145094999Y-128959095D01* +X144815404Y-128679499D01* +X144781379Y-128617187D01* +X144778500Y-128590404D01* +X144778500Y-127149500D01* +X144798502Y-127081379D01* +X144852158Y-127034886D01* +X144904500Y-127023500D01* +X148185973Y-127023500D01* +X148254094Y-127043502D01* +X148296471Y-127092488D01* +X148297788Y-127091772D01* +X148299928Y-127095710D01* +X148301783Y-127099789D01* +X148304196Y-127103562D01* +X148368747Y-127204497D01* +X148380258Y-127222497D01* +X148473748Y-127330998D01* +X148583511Y-127426750D01* +X148703696Y-127504650D01* +X148707757Y-127506526D01* +X148707758Y-127506527D01* +X148822515Y-127559552D01* +X148835924Y-127565748D01* +X148876104Y-127577764D01* +X148968844Y-127605499D01* +X148968849Y-127605500D01* +X148973142Y-127606784D01* +X148977574Y-127607446D01* +X148977577Y-127607447D01* +X149112765Y-127627650D01* +X149112768Y-127627650D01* +X149117196Y-127628312D01* +X149191855Y-127628768D01* +X149255945Y-127629160D01* +X149255950Y-127629160D01* +X149260417Y-127629187D01* +X149262861Y-127628852D01* +X149266656Y-127628729D01* +X149745000Y-127628729D01* +X149766029Y-127627225D01* +X149811375Y-127623982D01* +X149811377Y-127623982D01* +X149818111Y-127623500D01* +X149827989Y-127620600D01* +X149830423Y-127619885D01* +X149884496Y-127618474D01* +X149884684Y-127616745D01* +X149946866Y-127623500D01* +X151043134Y-127623500D01* +X151105316Y-127616745D01* +X151241705Y-127565615D01* +X151358261Y-127478261D01* +X151445615Y-127361705D01* +X151496745Y-127225316D01* +X151503500Y-127163134D01* +X151503500Y-125566866D01* +X151496745Y-125504684D01* +X151445615Y-125368295D01* +X151358261Y-125251739D01* +X151241705Y-125164385D01* +X151233296Y-125161233D01* +X151225425Y-125156923D01* +X151226336Y-125155259D01* +X151178510Y-125119337D01* +X151153807Y-125052776D01* +X151153500Y-125043991D01* +X151153500Y-123881615D01* +X151173502Y-123813494D01* +X151227158Y-123767001D01* +X151297432Y-123756897D01* +X151319168Y-123762022D01* +X151358710Y-123775138D01* +X151372086Y-123778005D01* +X151466438Y-123787672D01* +X151472854Y-123788000D01* +X151497885Y-123788000D01* +X151513124Y-123783525D01* +X151514329Y-123782135D01* +X151516000Y-123774452D01* +X151516000Y-122427000D01* +X151536002Y-122358879D01* +X151589658Y-122312386D01* +X151642000Y-122301000D01* +X151898000Y-122301000D01* +X151966121Y-122321002D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X147308656Y-119499317D02* +G01* +X147342131Y-119561926D01* +X147336444Y-119632695D01* +X147307875Y-119676720D01* +X146114748Y-120869847D01* +X146052436Y-120903873D01* +X146013000Y-120903873D01* +X146013000Y-120904000D01* +X145052115Y-120904000D01* +X145036876Y-120908475D01* +X145035671Y-120909865D01* +X145034000Y-120917548D01* +X145034000Y-121639884D01* +X145038475Y-121655123D01* +X145039865Y-121656328D01* +X145041903Y-121656771D01* +X145104215Y-121690795D01* +X145138241Y-121753107D01* +X145140431Y-121793061D01* +X145136496Y-121830500D01* +X145137186Y-121837065D01* +X145154371Y-122000568D01* +X145156458Y-122020428D01* +X145215473Y-122202056D01* +X145218776Y-122207778D01* +X145218777Y-122207779D01* +X145236110Y-122237800D01* +X145310960Y-122367444D01* +X145315378Y-122372351D01* +X145315379Y-122372352D01* +X145387161Y-122452074D01* +X145438747Y-122509366D01* +X145593248Y-122621618D01* +X145599276Y-122624302D01* +X145599278Y-122624303D01* +X145753690Y-122693051D01* +X145767712Y-122699294D01* +X145855806Y-122718019D01* +X145948056Y-122737628D01* +X145948061Y-122737628D01* +X145954513Y-122739000D01* +X146145487Y-122739000D01* +X146151939Y-122737628D01* +X146151944Y-122737628D01* +X146244194Y-122718019D01* +X146332288Y-122699294D01* +X146346310Y-122693051D01* +X146500722Y-122624303D01* +X146500724Y-122624302D01* +X146506752Y-122621618D01* +X146610940Y-122545921D01* +X146677806Y-122522063D01* +X146746958Y-122538143D01* +X146759056Y-122545918D01* +X146863248Y-122621618D01* +X146869276Y-122624302D01* +X146869278Y-122624303D01* +X147023690Y-122693051D01* +X147037712Y-122699294D01* +X147125806Y-122718019D01* +X147218056Y-122737628D01* +X147218061Y-122737628D01* +X147224513Y-122739000D01* +X147415487Y-122739000D01* +X147421939Y-122737628D01* +X147421944Y-122737628D01* +X147514194Y-122718019D01* +X147602288Y-122699294D01* +X147616310Y-122693051D01* +X147770722Y-122624303D01* +X147770724Y-122624302D01* +X147776752Y-122621618D01* +X147931253Y-122509366D01* +X147982839Y-122452074D01* +X148054621Y-122372352D01* +X148054622Y-122372351D01* +X148059040Y-122367444D01* +X148133890Y-122237800D01* +X148151223Y-122207779D01* +X148151224Y-122207778D01* +X148154527Y-122202056D01* +X148179424Y-122125431D01* +X148202057Y-122055775D01* +X148232795Y-122005616D01* +X148577657Y-121660754D01* +X148639969Y-121626728D01* +X148710784Y-121631793D01* +X148767620Y-121674340D01* +X148773894Y-121683542D01* +X148811522Y-121744348D01* +X148897825Y-121830500D01* +X148898109Y-121830784D01* +X148932188Y-121893066D01* +X148927185Y-121963886D01* +X148898264Y-122008975D01* +X148879774Y-122027497D01* +X148810695Y-122096697D01* +X148806855Y-122102927D01* +X148806854Y-122102928D01* +X148728495Y-122230050D01* +X148717885Y-122247262D01* +X148702987Y-122292179D01* +X148669451Y-122393288D01* +X148662203Y-122415139D01* +X148661503Y-122421975D01* +X148661502Y-122421978D01* +X148658419Y-122452074D01* +X148651500Y-122519600D01* +X148651500Y-123145400D01* +X148651837Y-123148646D01* +X148651837Y-123148650D01* +X148659636Y-123223811D01* +X148662474Y-123251166D01* +X148664655Y-123257702D01* +X148664655Y-123257704D01* +X148690099Y-123333968D01* +X148718450Y-123418946D01* +X148811522Y-123569348D01* +X148816704Y-123574521D01* +X148843850Y-123601620D01* +X148936697Y-123694305D01* +X148942927Y-123698145D01* +X148942928Y-123698146D01* +X149080210Y-123782768D01* +X149087262Y-123787115D01* +X149115337Y-123796427D01* +X149248611Y-123840632D01* +X149248613Y-123840632D01* +X149255139Y-123842797D01* +X149261975Y-123843497D01* +X149261978Y-123843498D01* +X149305031Y-123847909D01* +X149359600Y-123853500D01* +X149710500Y-123853500D01* +X149778621Y-123873502D01* +X149825114Y-123927158D01* +X149836500Y-123979500D01* +X149836500Y-124975271D01* +X149816498Y-125043392D01* +X149762842Y-125089885D01* +X149710500Y-125101271D01* +X149207678Y-125101271D01* +X149205369Y-125101250D01* +X149146453Y-125100170D01* +X149141980Y-125100088D01* +X149132483Y-125101271D01* +X149001872Y-125117540D01* +X149001868Y-125117541D01* +X148997435Y-125118093D01* +X148859255Y-125155766D01* +X148855138Y-125157548D01* +X148855134Y-125157549D01* +X148729704Y-125211827D01* +X148729699Y-125211829D01* +X148725580Y-125213612D01* +X148603528Y-125288552D01* +X148600080Y-125291415D01* +X148600078Y-125291416D01* +X148517650Y-125359849D01* +X148491460Y-125381592D01* +X148395346Y-125487776D01* +X148392839Y-125491492D01* +X148392838Y-125491494D01* +X148318302Y-125602000D01* +X148313893Y-125608536D01* +X148311937Y-125612574D01* +X148311936Y-125612575D01* +X148300859Y-125635438D01* +X148253157Y-125688022D01* +X148187467Y-125706500D01* +X145564500Y-125706500D01* +X145496379Y-125686498D01* +X145449886Y-125632842D01* +X145438500Y-125580500D01* +X145438500Y-123907056D01* +X145439059Y-123895200D01* +X145439059Y-123895197D01* +X145440788Y-123887463D01* +X145438562Y-123816631D01* +X145438500Y-123812673D01* +X145438500Y-123783568D01* +X145437944Y-123779168D01* +X145437012Y-123767330D01* +X145436925Y-123764540D01* +X145435562Y-123721169D01* +X145429580Y-123700579D01* +X145425570Y-123681216D01* +X145423875Y-123667796D01* +X145423875Y-123667795D01* +X145422882Y-123659936D01* +X145419966Y-123652571D01* +X145419965Y-123652567D01* +X145405874Y-123616979D01* +X145402035Y-123605769D01* +X145389145Y-123561400D01* +X145378229Y-123542943D01* +X145369534Y-123525193D01* +X145361635Y-123505244D01* +X145345825Y-123483483D01* +X145334477Y-123467864D01* +X145327960Y-123457943D01* +X145327477Y-123457126D01* +X145304452Y-123418193D01* +X145289291Y-123403032D01* +X145276449Y-123387997D01* +X145270753Y-123380157D01* +X145263841Y-123370643D01* +X145228242Y-123341193D01* +X145219463Y-123333204D01* +X144205405Y-122319145D01* +X144171379Y-122256833D01* +X144168500Y-122230050D01* +X144168500Y-121784000D01* +X144188502Y-121715879D01* +X144242158Y-121669386D01* +X144294500Y-121658000D01* +X144507885Y-121658000D01* +X144523124Y-121653525D01* +X144524329Y-121652135D01* +X144526000Y-121644452D01* +X144526000Y-120522000D01* +X144546002Y-120453879D01* +X144599658Y-120407386D01* +X144652000Y-120396000D01* +X145994884Y-120396000D01* +X146010123Y-120391525D01* +X146011328Y-120390135D01* +X146012999Y-120382452D01* +X146012999Y-120352905D01* +X146012662Y-120346386D01* +X146002743Y-120250794D01* +X145999851Y-120237400D01* +X145948412Y-120083216D01* +X145942239Y-120070038D01* +X145856937Y-119932193D01* +X145847901Y-119920792D01* +X145733172Y-119806262D01* +X145724238Y-119799206D01* +X145683177Y-119741288D01* +X145679947Y-119670365D01* +X145715574Y-119608954D01* +X145723407Y-119602154D01* +X145729348Y-119598478D01* +X145734521Y-119593296D01* +X145782252Y-119545482D01* +X145844535Y-119511403D01* +X145871425Y-119508500D01* +X146978293Y-119508500D01* +X147057059Y-119499317D01* +X147102411Y-119494030D01* +X147102415Y-119494029D01* +X147109681Y-119493182D01* +X147116556Y-119490687D01* +X147116558Y-119490686D01* +X147175788Y-119469186D01* +X147246646Y-119464745D01* +X147308656Y-119499317D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X117235020Y-98518502D02* +G01* +X117281513Y-98572158D01* +X117291617Y-98642432D01* +X117279986Y-98676036D01* +X117281461Y-98676693D01* +X117278777Y-98682721D01* +X117275473Y-98688444D01* +X117216458Y-98870072D01* +X117215768Y-98876633D01* +X117215768Y-98876635D01* +X117200268Y-99024110D01* +X117196496Y-99060000D01* +X117197186Y-99066565D01* +X117214713Y-99233321D01* +X117216458Y-99249928D01* +X117275473Y-99431556D01* +X117278776Y-99437278D01* +X117278777Y-99437279D01* +X117304841Y-99482422D01* +X117370960Y-99596944D01* +X117375375Y-99601847D01* +X117375379Y-99601852D01* +X117419136Y-99650449D01* +X117449854Y-99714456D01* +X117451500Y-99734759D01* +X117451500Y-99741000D01* +X117431498Y-99809121D01* +X117377842Y-99855614D01* +X117325500Y-99867000D01* +X117240615Y-99867000D01* +X117225376Y-99871475D01* +X117224171Y-99872865D01* +X117222500Y-99880548D01* +X117222500Y-100390500D01* +X117202498Y-100458621D01* +X117148842Y-100505114D01* +X117096500Y-100516500D01* +X116845128Y-100516500D01* +X116777007Y-100496498D01* +X116730514Y-100442842D01* +X116720410Y-100372568D01* +X116722008Y-100363715D01* +X116722500Y-100361453D01* +X116722500Y-99885116D01* +X116718025Y-99869877D01* +X116716635Y-99868672D01* +X116708952Y-99867001D01* +X116373547Y-99867001D01* +X116368611Y-99867195D01* +X116341608Y-99869319D01* +X116329007Y-99871620D01* +X116189220Y-99912232D01* +X116174783Y-99918480D01* +X116050773Y-99991819D01* +X116038335Y-100001468D01* +X115936468Y-100103335D01* +X115926819Y-100115773D01* +X115853480Y-100239783D01* +X115847232Y-100254220D01* +X115817196Y-100357605D01* +X115817236Y-100371705D01* +X115824506Y-100375000D01* +X116040378Y-100375000D01* +X116108499Y-100395002D01* +X116154992Y-100448658D01* +X116165096Y-100518932D01* +X116135602Y-100583512D01* +X116104517Y-100609454D01* +X116089554Y-100618303D01* +X116043637Y-100645458D01* +X116042663Y-100643810D01* +X115986132Y-100666006D01* +X115974991Y-100666500D01* +X115943136Y-100666500D01* +X115926690Y-100665422D01* +X115903188Y-100662328D01* +X115895000Y-100661250D01* +X115886812Y-100662328D01* +X115855129Y-100666499D01* +X115855120Y-100666500D01* +X115855115Y-100666500D01* +X115736150Y-100682162D01* +X115728521Y-100685322D01* +X115713606Y-100691500D01* +X115588125Y-100743476D01* +X115568787Y-100758315D01* +X115492928Y-100816523D01* +X115492925Y-100816526D01* +X115492921Y-100816529D01* +X115467566Y-100835984D01* +X115467563Y-100835987D01* +X115461013Y-100841013D01* +X115455987Y-100847563D01* +X115455984Y-100847566D01* +X115450508Y-100854703D01* +X115393171Y-100896571D01* +X115350545Y-100904000D01* +X113085116Y-100904000D01* +X113069877Y-100908475D01* +X113068672Y-100909865D01* +X113067001Y-100917548D01* +X113067001Y-100947095D01* +X113067338Y-100953614D01* +X113077257Y-101049206D01* +X113080149Y-101062600D01* +X113131588Y-101216784D01* +X113137761Y-101229962D01* +X113223063Y-101367807D01* +X113232099Y-101379208D01* +X113346828Y-101493738D01* +X113355762Y-101500794D01* +X113396823Y-101558712D01* +X113400053Y-101629635D01* +X113364426Y-101691046D01* +X113356593Y-101697846D01* +X113350652Y-101701522D01* +X113225695Y-101826697D01* +X113221855Y-101832927D01* +X113221854Y-101832928D01* +X113137445Y-101969865D01* +X113132885Y-101977262D01* +X113130581Y-101984209D01* +X113081837Y-102131169D01* +X113077203Y-102145139D01* +X113076503Y-102151975D01* +X113076502Y-102151978D01* +X113073905Y-102177330D01* +X113066500Y-102249600D01* +X113066500Y-102850400D01* +X113066837Y-102853646D01* +X113066837Y-102853650D01* +X113076654Y-102948261D01* +X113077474Y-102956166D01* +X113079655Y-102962702D01* +X113079655Y-102962704D01* +X113115307Y-103069565D01* +X113133450Y-103123946D01* +X113226522Y-103274348D01* +X113231704Y-103279521D01* +X113255964Y-103303739D01* +X113351697Y-103399305D01* +X113357927Y-103403145D01* +X113357928Y-103403146D01* +X113495906Y-103488197D01* +X113502262Y-103492115D01* +X113560902Y-103511565D01* +X113663611Y-103545632D01* +X113663613Y-103545632D01* +X113670139Y-103547797D01* +X113676975Y-103548497D01* +X113676978Y-103548498D01* +X113718470Y-103552749D01* +X113774600Y-103558500D01* +X114825400Y-103558500D01* +X114828646Y-103558163D01* +X114828650Y-103558163D01* +X114924308Y-103548238D01* +X114924312Y-103548237D01* +X114931166Y-103547526D01* +X114937702Y-103545345D01* +X114937704Y-103545345D01* +X115078309Y-103498435D01* +X115098946Y-103491550D01* +X115249348Y-103398478D01* +X115374305Y-103273303D01* +X115384661Y-103256503D01* +X115463275Y-103128968D01* +X115463276Y-103128966D01* +X115467115Y-103122738D01* +X115496566Y-103033946D01* +X115520632Y-102961389D01* +X115520632Y-102961387D01* +X115522797Y-102954861D01* +X115525001Y-102933355D01* +X115529236Y-102892012D01* +X115533500Y-102850400D01* +X115533500Y-102549239D01* +X115553502Y-102481118D01* +X115570405Y-102460144D01* +X115586405Y-102444144D01* +X115648717Y-102410118D01* +X115719532Y-102415183D01* +X115776368Y-102457730D01* +X115801179Y-102524250D01* +X115801500Y-102533238D01* +X115801501Y-102647582D01* +X115801501Y-102763978D01* +X115801794Y-102767699D01* +X115803755Y-102792627D01* +X115804326Y-102799889D01* +X115848982Y-102953593D01* +X115863544Y-102978216D01* +X115926424Y-103084543D01* +X115926427Y-103084547D01* +X115930458Y-103091363D01* +X116043637Y-103204542D01* +X116050464Y-103208579D01* +X116050466Y-103208581D01* +X116069639Y-103219920D01* +X116118092Y-103271813D01* +X116131500Y-103328373D01* +X116131500Y-103521256D01* +X116111498Y-103589377D01* +X116107436Y-103595317D01* +X116105379Y-103598148D01* +X116100960Y-103603056D01* +X116097659Y-103608774D01* +X116097658Y-103608775D01* +X116024142Y-103736109D01* +X116005473Y-103768444D01* +X115946458Y-103950072D01* +X115945768Y-103956633D01* +X115945768Y-103956635D01* +X115930590Y-104101045D01* +X115926496Y-104140000D01* +X115927186Y-104146565D01* +X115941143Y-104279355D01* +X115946458Y-104329928D01* +X116005473Y-104511556D01* +X116008776Y-104517278D01* +X116008777Y-104517279D01* +X116031486Y-104556611D01* +X116100960Y-104676944D01* +X116105378Y-104681851D01* +X116105379Y-104681852D01* +X116165823Y-104748982D01* +X116228747Y-104818866D01* +X116316275Y-104882459D01* +X116366959Y-104919283D01* +X116383248Y-104931118D01* +X116389276Y-104933802D01* +X116389278Y-104933803D01* +X116551681Y-105006109D01* +X116557712Y-105008794D01* +X116651113Y-105028647D01* +X116738056Y-105047128D01* +X116738061Y-105047128D01* +X116744513Y-105048500D01* +X116935487Y-105048500D01* +X116941939Y-105047128D01* +X116941944Y-105047128D01* +X117028888Y-105028647D01* +X117122288Y-105008794D01* +X117128319Y-105006109D01* +X117290722Y-104933803D01* +X117290724Y-104933802D01* +X117296752Y-104931118D01* +X117302094Y-104927237D01* +X117305431Y-104925310D01* +X117374426Y-104908571D01* +X117441518Y-104931790D01* +X117485406Y-104987596D01* +X117489429Y-104999272D01* +X117500855Y-105038600D01* +X117511775Y-105057065D01* +X117520466Y-105074805D01* +X117528365Y-105094756D01* +X117555516Y-105132126D01* +X117562033Y-105142048D01* +X117581507Y-105174977D01* +X117581510Y-105174981D01* +X117585547Y-105181807D01* +X117600711Y-105196971D01* +X117613551Y-105212004D01* +X117626159Y-105229357D01* +X117652559Y-105251197D01* +X117661752Y-105258802D01* +X117670532Y-105266792D01* +X118558941Y-106155201D01* +X118592967Y-106217513D01* +X118587902Y-106288328D01* +X118559020Y-106333313D01* +X118541694Y-106350670D01* +X118525695Y-106366697D01* +X118522898Y-106371235D01* +X118465647Y-106411824D01* +X118394724Y-106415054D01* +X118333313Y-106379428D01* +X118325938Y-106370932D01* +X118317902Y-106360793D01* +X118203171Y-106246261D01* +X118191760Y-106237249D01* +X118053757Y-106152184D01* +X118040576Y-106146037D01* +X117886290Y-106094862D01* +X117872914Y-106091995D01* +X117778562Y-106082328D01* +X117772145Y-106082000D01* +X117747115Y-106082000D01* +X117731876Y-106086475D01* +X117730671Y-106087865D01* +X117729000Y-106095548D01* +X117729000Y-108529884D01* +X117733475Y-108545123D01* +X117734865Y-108546328D01* +X117742548Y-108547999D01* +X117772095Y-108547999D01* +X117778614Y-108547662D01* +X117874206Y-108537743D01* +X117887600Y-108534851D01* +X118041784Y-108483412D01* +X118054962Y-108477239D01* +X118192807Y-108391937D01* +X118204208Y-108382901D01* +X118318738Y-108268172D01* +X118325794Y-108259238D01* +X118383712Y-108218177D01* +X118454635Y-108214947D01* +X118516046Y-108250574D01* +X118522846Y-108258407D01* +X118526522Y-108264348D01* +X118651697Y-108389305D01* +X118657927Y-108393145D01* +X118657928Y-108393146D01* +X118795288Y-108477816D01* +X118802262Y-108482115D01* +X118867101Y-108503621D01* +X118963611Y-108535632D01* +X118963613Y-108535632D01* +X118970139Y-108537797D01* +X118976975Y-108538497D01* +X118976978Y-108538498D01* +X119020031Y-108542909D01* +X119074600Y-108548500D01* +X119675400Y-108548500D01* +X119678646Y-108548163D01* +X119678650Y-108548163D01* +X119774308Y-108538238D01* +X119774312Y-108538237D01* +X119781166Y-108537526D01* +X119787702Y-108535345D01* +X119787704Y-108535345D01* +X119932778Y-108486944D01* +X119948946Y-108481550D01* +X120099348Y-108388478D01* +X120224305Y-108263303D01* +X120232151Y-108250574D01* +X120313275Y-108118968D01* +X120313276Y-108118966D01* +X120317115Y-108112738D01* +X120343564Y-108032995D01* +X120370632Y-107951389D01* +X120370632Y-107951387D01* +X120372797Y-107944861D01* +X120373822Y-107934862D01* +X120382747Y-107847751D01* +X120383500Y-107840400D01* +X120383500Y-106789600D01* +X120381830Y-106773502D01* +X120373238Y-106690692D01* +X120373237Y-106690688D01* +X120372526Y-106683834D01* +X120368071Y-106670479D01* +X120318868Y-106523002D01* +X120316550Y-106516054D01* +X120223478Y-106365652D01* +X120098303Y-106240695D01* +X120092072Y-106236854D01* +X120086408Y-106232381D01* +X120045345Y-106174464D01* +X120038500Y-106133499D01* +X120038500Y-106127056D01* +X120039059Y-106115200D01* +X120039059Y-106115197D01* +X120040788Y-106107463D01* +X120038562Y-106036631D01* +X120038500Y-106032673D01* +X120038500Y-106003568D01* +X120037944Y-105999168D01* +X120037012Y-105987330D01* +X120036317Y-105965184D01* +X120035562Y-105941169D01* +X120029580Y-105920579D01* +X120025570Y-105901216D01* +X120023875Y-105887796D01* +X120023875Y-105887795D01* +X120022882Y-105879936D01* +X120019966Y-105872571D01* +X120019965Y-105872567D01* +X120005874Y-105836979D01* +X120002035Y-105825769D01* +X119989145Y-105781400D01* +X119978229Y-105762943D01* +X119969534Y-105745193D01* +X119961635Y-105725244D01* +X119943307Y-105700018D01* +X119934477Y-105687864D01* +X119927960Y-105677943D01* +X119926004Y-105674636D01* +X119904452Y-105638193D01* +X119889291Y-105623032D01* +X119876449Y-105607997D01* +X119875148Y-105606206D01* +X119863841Y-105590643D01* +X119828242Y-105561193D01* +X119819463Y-105553204D01* +X118805405Y-104539145D01* +X118771379Y-104476833D01* +X118768500Y-104450050D01* +X118768500Y-103459500D01* +X118788502Y-103391379D01* +X118842158Y-103344886D01* +X118894500Y-103333500D01* +X119828171Y-103333499D01* +X119848978Y-103333499D01* +X119855197Y-103333010D01* +X119855627Y-103332976D01* +X119925105Y-103347579D01* +X119975660Y-103397426D01* +X119991500Y-103458589D01* +X119991500Y-104700845D01* +X119989268Y-104724454D01* +X119987576Y-104733324D01* +X119988074Y-104741235D01* +X119991251Y-104791735D01* +X119991500Y-104799647D01* +X119991500Y-104816432D01* +X119992298Y-104822749D01* +X119993604Y-104833090D01* +X119994348Y-104840966D01* +X119996731Y-104878831D01* +X119998023Y-104899371D01* +X120000471Y-104906904D01* +X120000810Y-104907947D01* +X120005986Y-104931105D01* +X120007118Y-104940064D01* +X120010034Y-104947429D01* +X120010035Y-104947433D01* +X120028673Y-104994506D01* +X120031355Y-105001956D01* +X120045477Y-105045418D01* +X120049436Y-105057604D01* +X120053684Y-105064298D01* +X120053687Y-105064304D01* +X120054276Y-105065232D01* +X120065039Y-105086355D01* +X120068365Y-105094756D01* +X120095516Y-105132126D01* +X120102774Y-105142116D01* +X120107223Y-105148663D01* +X120138584Y-105198080D01* +X120144364Y-105203508D01* +X120144365Y-105203509D01* +X120145173Y-105204268D01* +X120160849Y-105222049D01* +X120166159Y-105229357D01* +X120172267Y-105234410D01* +X120172269Y-105234412D01* +X120211255Y-105266665D01* +X120217189Y-105271896D01* +X120232550Y-105286320D01* +X120259867Y-105311972D01* +X120266809Y-105315788D01* +X120266814Y-105315792D01* +X120267784Y-105316325D01* +X120287395Y-105329652D01* +X120294354Y-105335409D01* +X120345698Y-105359570D01* +X120347315Y-105360331D01* +X120354367Y-105363924D01* +X120370884Y-105373004D01* +X120405663Y-105392124D01* +X120413341Y-105394095D01* +X120413343Y-105394096D01* +X120413876Y-105394233D01* +X120414410Y-105394370D01* +X120436722Y-105402403D01* +X120437720Y-105402873D01* +X120437723Y-105402874D01* +X120444895Y-105406249D01* +X120452682Y-105407734D01* +X120452684Y-105407735D01* +X120465282Y-105410138D01* +X120502404Y-105417219D01* +X120510120Y-105418944D01* +X120515554Y-105420339D01* +X120559127Y-105431527D01* +X120559128Y-105431527D01* +X120566812Y-105433500D01* +X120574641Y-105433500D01* +X120639674Y-105461863D01* +X120678330Y-105518613D01* +X120688450Y-105548946D01* +X120781522Y-105699348D01* +X120906697Y-105824305D01* +X120924116Y-105835042D01* +X120971609Y-105887813D01* +X120984000Y-105942302D01* +X120984000Y-108277711D01* +X120963998Y-108345832D01* +X120909249Y-108392818D01* +X120834278Y-108426197D01* +X120834276Y-108426198D01* +X120828248Y-108428882D01* +X120673747Y-108541134D01* +X120669326Y-108546044D01* +X120669325Y-108546045D01* +X120555275Y-108672711D01* +X120545960Y-108683056D01* +X120517296Y-108732704D01* +X120466798Y-108820169D01* +X120450473Y-108848444D01* +X120391458Y-109030072D01* +X120390768Y-109036633D01* +X120390768Y-109036635D01* +X120380049Y-109138621D01* +X120371496Y-109220000D01* +X120372186Y-109226565D01* +X120376996Y-109272330D01* +X120364224Y-109342168D01* +X120315722Y-109394015D01* +X120251686Y-109411500D01* +X119767063Y-109411500D01* +X119748114Y-109410067D01* +X119747200Y-109409928D01* +X119726651Y-109406802D01* +X119719359Y-109407395D01* +X119719356Y-109407395D01* +X119673991Y-109411085D01* +X119663777Y-109411500D01* +X119655707Y-109411500D01* +X119652087Y-109411922D01* +X119652069Y-109411923D01* +X119627461Y-109414792D01* +X119623100Y-109415224D01* +X119597981Y-109417267D01* +X119557661Y-109420546D01* +X119557658Y-109420547D01* +X119550363Y-109421140D01* +X119543399Y-109423396D01* +X119537440Y-109424587D01* +X119531585Y-109425971D01* +X119524319Y-109426818D01* +X119455673Y-109451735D01* +X119451545Y-109453152D01* +X119389064Y-109473393D01* +X119389062Y-109473394D01* +X119382101Y-109475649D01* +X119375846Y-109479445D01* +X119370372Y-109481951D01* +X119364942Y-109484670D01* +X119358063Y-109487167D01* +X119297016Y-109527191D01* +X119293327Y-109529518D01* +X119276344Y-109539824D01* +X119235693Y-109564491D01* +X119235688Y-109564495D01* +X119230892Y-109567405D01* +X119226685Y-109571121D01* +X119226682Y-109571123D01* +X119222545Y-109574777D01* +X119222516Y-109574803D01* +X119222493Y-109574777D01* +X119219503Y-109577426D01* +X119216264Y-109580134D01* +X119210148Y-109584144D01* +X119205121Y-109589451D01* +X119205117Y-109589454D01* +X119156872Y-109640383D01* +X119154494Y-109642825D01* +X118886089Y-109911230D01* +X118871677Y-109923616D01* +X118860082Y-109932149D01* +X118860077Y-109932154D01* +X118854182Y-109936492D01* +X118849443Y-109942070D01* +X118849440Y-109942073D01* +X118819965Y-109976768D01* +X118813035Y-109984284D01* +X118807340Y-109989979D01* +X118805060Y-109992861D01* +X118789719Y-110012251D01* +X118786928Y-110015655D01* +X118756435Y-110051548D01* +X118739667Y-110071285D01* +X118736339Y-110077801D01* +X118732972Y-110082850D01* +X118729805Y-110087979D01* +X118725266Y-110093716D01* +X118694345Y-110159875D01* +X118692442Y-110163769D01* +X118659231Y-110228808D01* +X118657492Y-110235916D01* +X118655393Y-110241559D01* +X118653476Y-110247322D01* +X118650378Y-110253950D01* +X118648888Y-110261112D01* +X118648888Y-110261113D01* +X118635514Y-110325412D01* +X118634544Y-110329696D01* +X118617192Y-110400610D01* +X118616500Y-110411764D01* +X118616464Y-110411762D01* +X118616225Y-110415755D01* +X118615851Y-110419947D01* +X118614360Y-110427115D01* +X118615884Y-110483435D01* +X118616454Y-110504521D01* +X118616500Y-110507928D01* +X118616500Y-113208607D01* +X118596498Y-113276728D01* +X118579673Y-113297625D01* +X118525695Y-113351697D01* +X118522898Y-113356235D01* +X118465647Y-113396824D01* +X118394724Y-113400054D01* +X118333313Y-113364428D01* +X118325938Y-113355932D01* +X118317902Y-113345793D01* +X118203171Y-113231261D01* +X118191760Y-113222249D01* +X118053757Y-113137184D01* +X118040576Y-113131037D01* +X117886290Y-113079862D01* +X117872914Y-113076995D01* +X117778562Y-113067328D01* +X117772145Y-113067000D01* +X117747115Y-113067000D01* +X117731876Y-113071475D01* +X117730671Y-113072865D01* +X117729000Y-113080548D01* +X117729000Y-115514884D01* +X117733475Y-115530123D01* +X117734865Y-115531328D01* +X117742548Y-115532999D01* +X117772095Y-115532999D01* +X117778614Y-115532662D01* +X117874206Y-115522743D01* +X117887600Y-115519851D01* +X118041784Y-115468412D01* +X118054962Y-115462239D01* +X118192807Y-115376937D01* +X118204208Y-115367901D01* +X118318738Y-115253172D01* +X118325794Y-115244238D01* +X118383712Y-115203177D01* +X118454635Y-115199947D01* +X118516046Y-115235574D01* +X118522846Y-115243407D01* +X118526522Y-115249348D01* +X118531704Y-115254521D01* +X118579518Y-115302252D01* +X118613597Y-115364535D01* +X118616500Y-115391425D01* +X118616500Y-115665219D01* +X118596498Y-115733340D01* +X118566065Y-115766045D01* +X118492191Y-115821411D01* +X118471739Y-115836739D01* +X118384385Y-115953295D01* +X118333255Y-116089684D01* +X118326500Y-116151866D01* +X118326500Y-117448134D01* +X118333255Y-117510316D01* +X118384385Y-117646705D01* +X118471739Y-117763261D01* +X118588295Y-117850615D01* +X118724684Y-117901745D01* +X118786866Y-117908500D01* +X119750989Y-117908500D01* +X119819110Y-117928502D01* +X119865603Y-117982158D01* +X119876989Y-118034500D01* +X119876989Y-118533696D01* +X119874757Y-118557305D01* +X119873214Y-118565395D01* +X119875746Y-118605638D01* +X119876740Y-118621440D01* +X119876989Y-118629351D01* +X119876989Y-118645345D01* +X119878995Y-118661219D01* +X119879737Y-118669079D01* +X119883264Y-118725139D01* +X119885714Y-118732680D01* +X119885810Y-118732976D01* +X119890983Y-118756120D01* +X119891021Y-118756424D01* +X119891022Y-118756429D01* +X119892015Y-118764286D01* +X119894931Y-118771651D01* +X119894932Y-118771655D01* +X119912688Y-118816500D01* +X119915360Y-118823919D01* +X119932725Y-118877364D01* +X119936975Y-118884060D01* +X119936975Y-118884061D01* +X119937139Y-118884320D01* +X119947904Y-118905447D01* +X119948018Y-118905735D01* +X119948021Y-118905740D01* +X119950937Y-118913106D01* +X119955593Y-118919514D01* +X119955596Y-118919520D01* +X119983947Y-118958541D01* +X119988397Y-118965089D01* +X120004912Y-118991113D01* +X120024524Y-119059347D01* +X120004132Y-119127352D01* +X119980086Y-119153754D01* +X119979652Y-119154022D01* +X119974482Y-119159201D01* +X119968744Y-119163749D01* +X119967316Y-119161947D01* +X119914774Y-119190691D01* +X119843955Y-119185681D01* +X119806976Y-119161958D01* +X119806229Y-119162904D01* +X119800483Y-119158366D01* +X119795303Y-119153195D01* +X119697961Y-119093192D01* +X119650968Y-119064225D01* +X119650966Y-119064224D01* +X119644738Y-119060385D01* +X119549195Y-119028695D01* +X119483389Y-119006868D01* +X119483387Y-119006868D01* +X119476861Y-119004703D01* +X119470025Y-119004003D01* +X119470022Y-119004002D01* +X119419023Y-118998777D01* +X119372400Y-118994000D01* +X118371600Y-118994000D01* +X118368354Y-118994337D01* +X118368350Y-118994337D01* +X118272692Y-119004262D01* +X118272688Y-119004263D01* +X118265834Y-119004974D01* +X118259298Y-119007155D01* +X118259296Y-119007155D01* +X118179471Y-119033787D01* +X118098054Y-119060950D01* +X117947652Y-119154022D01* +X117942479Y-119159204D01* +X117936742Y-119163751D01* +X117935314Y-119161949D01* +X117882774Y-119190691D01* +X117811955Y-119185681D01* +X117774976Y-119161958D01* +X117774229Y-119162904D01* +X117768483Y-119158366D01* +X117763303Y-119153195D01* +X117665961Y-119093192D01* +X117618968Y-119064225D01* +X117618966Y-119064224D01* +X117612738Y-119060385D01* +X117517195Y-119028695D01* +X117451389Y-119006868D01* +X117451387Y-119006868D01* +X117444861Y-119004703D01* +X117438025Y-119004003D01* +X117438022Y-119004002D01* +X117387023Y-118998777D01* +X117340400Y-118994000D01* +X116767095Y-118994000D01* +X116698974Y-118973998D01* +X116678000Y-118957095D01* +X116398931Y-118678026D01* +X116364905Y-118615714D01* +X116369970Y-118544899D01* +X116378907Y-118525931D01* +X116401223Y-118487279D01* +X116401224Y-118487278D01* +X116404527Y-118481556D01* +X116463542Y-118299928D01* +X116464700Y-118288915D01* +X116482814Y-118116565D01* +X116483504Y-118110000D01* +X116472968Y-118009752D01* +X116464232Y-117926635D01* +X116464232Y-117926633D01* +X116463542Y-117920072D01* +X116404527Y-117738444D01* +X116399955Y-117730524D01* +X116317198Y-117587186D01* +X116309040Y-117573056D01* +X116263799Y-117522810D01* +X116185675Y-117436045D01* +X116185674Y-117436044D01* +X116181253Y-117431134D01* +X116064374Y-117346216D01* +X116032094Y-117322763D01* +X116032093Y-117322762D01* +X116026752Y-117318882D01* +X116020724Y-117316198D01* +X116020722Y-117316197D01* +X115858319Y-117243891D01* +X115858318Y-117243891D01* +X115852288Y-117241206D01* +X115758887Y-117221353D01* +X115671944Y-117202872D01* +X115671939Y-117202872D01* +X115665487Y-117201500D01* +X115474513Y-117201500D01* +X115468061Y-117202872D01* +X115468056Y-117202872D01* +X115381113Y-117221353D01* +X115287712Y-117241206D01* +X115281682Y-117243891D01* +X115281681Y-117243891D01* +X115119278Y-117316197D01* +X115119276Y-117316198D01* +X115113248Y-117318882D01* +X115107907Y-117322762D01* +X115107906Y-117322763D01* +X115075626Y-117346216D01* +X114958747Y-117431134D01* +X114954326Y-117436044D01* +X114954325Y-117436045D01* +X114876202Y-117522810D01* +X114830960Y-117573056D01* +X114822802Y-117587186D01* +X114740046Y-117730524D01* +X114735473Y-117738444D01* +X114676458Y-117920072D01* +X114675768Y-117926633D01* +X114675768Y-117926635D01* +X114667032Y-118009752D01* +X114656496Y-118110000D01* +X114657186Y-118116565D01* +X114675301Y-118288915D01* +X114676458Y-118299928D01* +X114735473Y-118481556D01* +X114738776Y-118487278D01* +X114738777Y-118487279D01* +X114765748Y-118533993D01* +X114830960Y-118646944D01* +X114905947Y-118730225D01* +X114936664Y-118794233D01* +X114938248Y-118810575D01* +X114938669Y-118823950D01* +X114939327Y-118844889D01* +X114944978Y-118864339D01* +X114948987Y-118883700D01* +X114951526Y-118903797D01* +X114954445Y-118911168D01* +X114954445Y-118911170D01* +X114967804Y-118944912D01* +X114971649Y-118956142D01* +X114981771Y-118990983D01* +X114983982Y-118998593D01* +X114988015Y-119005412D01* +X114988017Y-119005417D01* +X114994293Y-119016028D01* +X115002988Y-119033776D01* +X115010448Y-119052617D01* +X115015110Y-119059033D01* +X115015110Y-119059034D01* +X115036436Y-119088387D01* +X115042952Y-119098307D01* +X115058951Y-119125359D01* +X115065458Y-119136362D01* +X115079779Y-119150683D01* +X115092619Y-119165716D01* +X115104528Y-119182107D01* +X115115129Y-119190877D01* +X115138605Y-119210298D01* +X115147384Y-119218288D01* +X115594595Y-119665499D01* +X115628621Y-119727811D01* +X115631500Y-119754594D01* +X115631500Y-120252856D01* +X115611498Y-120320977D01* +X115557842Y-120367470D01* +X115492327Y-120378166D01* +X115489555Y-120377875D01* +X115483088Y-120376500D01* +X115292114Y-120376500D01* +X115285662Y-120377872D01* +X115285657Y-120377872D01* +X115200374Y-120396000D01* +X115105313Y-120416206D01* +X115099283Y-120418891D01* +X115099282Y-120418891D01* +X114936879Y-120491197D01* +X114936877Y-120491198D01* +X114930849Y-120493882D01* +X114925508Y-120497762D01* +X114925507Y-120497763D01* +X114892774Y-120521545D01* +X114776348Y-120606134D01* +X114771933Y-120611037D01* +X114767021Y-120615460D01* +X114765896Y-120614211D01* +X114712587Y-120647051D01* +X114679401Y-120651500D01* +X114614595Y-120651500D01* +X114546474Y-120631498D01* +X114525499Y-120614595D01* +X114335404Y-120424499D01* +X114301379Y-120362187D01* +X114298500Y-120335404D01* +X114298500Y-114822095D01* +X116467001Y-114822095D01* +X116467338Y-114828614D01* +X116477257Y-114924206D01* +X116480149Y-114937600D01* +X116531588Y-115091784D01* +X116537761Y-115104962D01* +X116623063Y-115242807D01* +X116632099Y-115254208D01* +X116746829Y-115368739D01* +X116758240Y-115377751D01* +X116896243Y-115462816D01* +X116909424Y-115468963D01* +X117063710Y-115520138D01* +X117077086Y-115523005D01* +X117171438Y-115532672D01* +X117177854Y-115533000D01* +X117202885Y-115533000D01* +X117218124Y-115528525D01* +X117219329Y-115527135D01* +X117221000Y-115519452D01* +X117221000Y-114572115D01* +X117216525Y-114556876D01* +X117215135Y-114555671D01* +X117207452Y-114554000D01* +X116485116Y-114554000D01* +X116469877Y-114558475D01* +X116468672Y-114559865D01* +X116467001Y-114567548D01* +X116467001Y-114822095D01* +X114298500Y-114822095D01* +X114298500Y-114027885D01* +X116467000Y-114027885D01* +X116471475Y-114043124D01* +X116472865Y-114044329D01* +X116480548Y-114046000D01* +X117202885Y-114046000D01* +X117218124Y-114041525D01* +X117219329Y-114040135D01* +X117221000Y-114032452D01* +X117221000Y-113085116D01* +X117216525Y-113069877D01* +X117215135Y-113068672D01* +X117207452Y-113067001D01* +X117177905Y-113067001D01* +X117171386Y-113067338D01* +X117075794Y-113077257D01* +X117062400Y-113080149D01* +X116908216Y-113131588D01* +X116895038Y-113137761D01* +X116757193Y-113223063D01* +X116745792Y-113232099D01* +X116631261Y-113346829D01* +X116622249Y-113358240D01* +X116537184Y-113496243D01* +X116531037Y-113509424D01* +X116479862Y-113663710D01* +X116476995Y-113677086D01* +X116467328Y-113771438D01* +X116467000Y-113777855D01* +X116467000Y-114027885D01* +X114298500Y-114027885D01* +X114298500Y-111521148D01* +X114318502Y-111453027D01* +X114372158Y-111406534D01* +X114398299Y-111397902D01* +X114582288Y-111358794D01* +X114595890Y-111352738D01* +X114750722Y-111283803D01* +X114750724Y-111283802D01* +X114756752Y-111281118D01* +X114766851Y-111273781D01* +X114878443Y-111192704D01* +X114911253Y-111168866D01* +X115009117Y-111060177D01* +X115034621Y-111031852D01* +X115034625Y-111031847D01* +X115039040Y-111026944D01* +X115097314Y-110926010D01* +X115131223Y-110867279D01* +X115131224Y-110867278D01* +X115134527Y-110861556D01* +X115193542Y-110679928D01* +X115199793Y-110620458D01* +X115212814Y-110496565D01* +X115213504Y-110490000D01* +X115210127Y-110457866D01* +X115194232Y-110306635D01* +X115194232Y-110306633D01* +X115193542Y-110300072D01* +X115134527Y-110118444D01* +X115119909Y-110093124D01* +X115081450Y-110026512D01* +X115039040Y-109953056D01* +X114966333Y-109872306D01* +X114915675Y-109816045D01* +X114915674Y-109816044D01* +X114911253Y-109811134D01* +X114756752Y-109698882D01* +X114750724Y-109696198D01* +X114750722Y-109696197D01* +X114588319Y-109623891D01* +X114588318Y-109623891D01* +X114582288Y-109621206D01* +X114480598Y-109599591D01* +X114401944Y-109582872D01* +X114401939Y-109582872D01* +X114395487Y-109581500D01* +X114204513Y-109581500D01* +X114198061Y-109582872D01* +X114198056Y-109582872D01* +X114119402Y-109599591D01* +X114017712Y-109621206D01* +X114011682Y-109623891D01* +X114011681Y-109623891D01* +X113983318Y-109636519D01* +X113915748Y-109666603D01* +X113845382Y-109676037D01* +X113781085Y-109645931D01* +X113743271Y-109585842D01* +X113738500Y-109551496D01* +X113738500Y-108965207D01* +X113758502Y-108897086D01* +X113812158Y-108850593D01* +X113838303Y-108841961D01* +X113940822Y-108820169D01* +X113940827Y-108820167D01* +X113947288Y-108818794D01* +X113953319Y-108816109D01* +X114115722Y-108743803D01* +X114115724Y-108743802D01* +X114121752Y-108741118D01* +X114276253Y-108628866D01* +X114286817Y-108617134D01* +X114399621Y-108491852D01* +X114399622Y-108491851D01* +X114404040Y-108486944D01* +X114499527Y-108321556D01* +X114558542Y-108139928D01* +X114560641Y-108119962D01* +X114577814Y-107956565D01* +X114578504Y-107950000D01* +X114576031Y-107926475D01* +X114566637Y-107837095D01* +X116467001Y-107837095D01* +X116467338Y-107843614D01* +X116477257Y-107939206D01* +X116480149Y-107952600D01* +X116531588Y-108106784D01* +X116537761Y-108119962D01* +X116623063Y-108257807D01* +X116632099Y-108269208D01* +X116746829Y-108383739D01* +X116758240Y-108392751D01* +X116896243Y-108477816D01* +X116909424Y-108483963D01* +X117063710Y-108535138D01* +X117077086Y-108538005D01* +X117171438Y-108547672D01* +X117177854Y-108548000D01* +X117202885Y-108548000D01* +X117218124Y-108543525D01* +X117219329Y-108542135D01* +X117221000Y-108534452D01* +X117221000Y-107587115D01* +X117216525Y-107571876D01* +X117215135Y-107570671D01* +X117207452Y-107569000D01* +X116485116Y-107569000D01* +X116469877Y-107573475D01* +X116468672Y-107574865D01* +X116467001Y-107582548D01* +X116467001Y-107837095D01* +X114566637Y-107837095D01* +X114559232Y-107766635D01* +X114559232Y-107766633D01* +X114558542Y-107760072D01* +X114499527Y-107578444D01* +X114494075Y-107569000D01* +X114426353Y-107451704D01* +X114404040Y-107413056D01* +X114399128Y-107407600D01* +X114280675Y-107276045D01* +X114280674Y-107276044D01* +X114276253Y-107271134D01* +X114157729Y-107185021D01* +X114127094Y-107162763D01* +X114127093Y-107162762D01* +X114121752Y-107158882D01* +X114115724Y-107156198D01* +X114115722Y-107156197D01* +X113953319Y-107083891D01* +X113953318Y-107083891D01* +X113947288Y-107081206D01* +X113767003Y-107042885D01* +X116467000Y-107042885D01* +X116471475Y-107058124D01* +X116472865Y-107059329D01* +X116480548Y-107061000D01* +X117202885Y-107061000D01* +X117218124Y-107056525D01* +X117219329Y-107055135D01* +X117221000Y-107047452D01* +X117221000Y-106100116D01* +X117216525Y-106084877D01* +X117215135Y-106083672D01* +X117207452Y-106082001D01* +X117177905Y-106082001D01* +X117171386Y-106082338D01* +X117075794Y-106092257D01* +X117062400Y-106095149D01* +X116908216Y-106146588D01* +X116895038Y-106152761D01* +X116757193Y-106238063D01* +X116745792Y-106247099D01* +X116631261Y-106361829D01* +X116622249Y-106373240D01* +X116537184Y-106511243D01* +X116531037Y-106524424D01* +X116479862Y-106678710D01* +X116476995Y-106692086D01* +X116467328Y-106786438D01* +X116467000Y-106792855D01* +X116467000Y-107042885D01* +X113767003Y-107042885D01* +X113760487Y-107041500D01* +X113761105Y-107038593D01* +X113707390Y-107016418D01* +X113666831Y-106958147D01* +X113664213Y-106887199D01* +X113666498Y-106879297D01* +X113669542Y-106869928D01* +X113670232Y-106863359D01* +X113671605Y-106856901D01* +X113673624Y-106857330D01* +X113696930Y-106800677D01* +X113755149Y-106760045D01* +X113795230Y-106753500D01* +X114323595Y-106753500D01* +X114391716Y-106773502D01* +X114397656Y-106777564D01* +X114478248Y-106836118D01* +X114484276Y-106838802D01* +X114484278Y-106838803D01* +X114646681Y-106911109D01* +X114652712Y-106913794D01* +X114743911Y-106933179D01* +X114833056Y-106952128D01* +X114833061Y-106952128D01* +X114839513Y-106953500D01* +X115030487Y-106953500D01* +X115036939Y-106952128D01* +X115036944Y-106952128D01* +X115126089Y-106933179D01* +X115217288Y-106913794D01* +X115223319Y-106911109D01* +X115385722Y-106838803D01* +X115385724Y-106838802D01* +X115391752Y-106836118D01* +X115546253Y-106723866D01* +X115550675Y-106718955D01* +X115669621Y-106586852D01* +X115669622Y-106586851D01* +X115674040Y-106581944D01* +X115769527Y-106416556D01* +X115828542Y-106234928D01* +X115829574Y-106225114D01* +X115847814Y-106051565D01* +X115848504Y-106045000D01* +X115842443Y-105987330D01* +X115829232Y-105861635D01* +X115829232Y-105861633D01* +X115828542Y-105855072D01* +X115769527Y-105673444D01* +X115762507Y-105661284D01* +X115704719Y-105561194D01* +X115674040Y-105508056D01* +X115661570Y-105494206D01* +X115550675Y-105371045D01* +X115550674Y-105371044D01* +X115546253Y-105366134D01* +X115391752Y-105253882D01* +X115385724Y-105251198D01* +X115385722Y-105251197D01* +X115223319Y-105178891D01* +X115223318Y-105178891D01* +X115217288Y-105176206D01* +X115123887Y-105156353D01* +X115036944Y-105137872D01* +X115036939Y-105137872D01* +X115030487Y-105136500D01* +X114839513Y-105136500D01* +X114833061Y-105137872D01* +X114833056Y-105137872D01* +X114746113Y-105156353D01* +X114652712Y-105176206D01* +X114646682Y-105178891D01* +X114646681Y-105178891D01* +X114484278Y-105251197D01* +X114484276Y-105251198D01* +X114478248Y-105253882D01* +X114472907Y-105257762D01* +X114472906Y-105257763D01* +X114397656Y-105312436D01* +X114330789Y-105336294D01* +X114323595Y-105336500D01* +X114010660Y-105336500D01* +X113942539Y-105316498D01* +X113921565Y-105299595D01* +X112505405Y-103883435D01* +X112471379Y-103821123D01* +X112468500Y-103794340D01* +X112468500Y-100377885D01* +X113067000Y-100377885D01* +X113071475Y-100393124D01* +X113072865Y-100394329D01* +X113080548Y-100396000D01* +X114027885Y-100396000D01* +X114043124Y-100391525D01* +X114044329Y-100390135D01* +X114046000Y-100382452D01* +X114046000Y-100377885D01* +X114554000Y-100377885D01* +X114558475Y-100393124D01* +X114559865Y-100394329D01* +X114567548Y-100396000D01* +X115514884Y-100396000D01* +X115530123Y-100391525D01* +X115531328Y-100390135D01* +X115532999Y-100382452D01* +X115532999Y-100352905D01* +X115532662Y-100346386D01* +X115522743Y-100250794D01* +X115519851Y-100237400D01* +X115468412Y-100083216D01* +X115462239Y-100070038D01* +X115376937Y-99932193D01* +X115367901Y-99920792D01* +X115253171Y-99806261D01* +X115241760Y-99797249D01* +X115103757Y-99712184D01* +X115090576Y-99706037D01* +X114936290Y-99654862D01* +X114922914Y-99651995D01* +X114828562Y-99642328D01* +X114822145Y-99642000D01* +X114572115Y-99642000D01* +X114556876Y-99646475D01* +X114555671Y-99647865D01* +X114554000Y-99655548D01* +X114554000Y-100377885D01* +X114046000Y-100377885D01* +X114046000Y-99660116D01* +X114041525Y-99644877D01* +X114040135Y-99643672D01* +X114032452Y-99642001D01* +X113777905Y-99642001D01* +X113771386Y-99642338D01* +X113675794Y-99652257D01* +X113662400Y-99655149D01* +X113508216Y-99706588D01* +X113495038Y-99712761D01* +X113357193Y-99798063D01* +X113345792Y-99807099D01* +X113231261Y-99921829D01* +X113222249Y-99933240D01* +X113137184Y-100071243D01* +X113131037Y-100084424D01* +X113079862Y-100238710D01* +X113076995Y-100252086D01* +X113067328Y-100346438D01* +X113067000Y-100352855D01* +X113067000Y-100377885D01* +X112468500Y-100377885D01* +X112468500Y-98770660D01* +X112488502Y-98702539D01* +X112505405Y-98681565D01* +X112651565Y-98535405D01* +X112713877Y-98501379D01* +X112740660Y-98498500D01* +X117166899Y-98498500D01* +X117235020Y-98518502D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X147787012Y-112694090D02* +G01* +X147793595Y-112700219D01* +X147925457Y-112832081D01* +X147959483Y-112894393D01* +X147961672Y-112908004D01* +X147966580Y-112954704D01* +X147968620Y-112960981D01* +X147968620Y-112960983D01* +X147990151Y-113027249D01* +X148025595Y-113136332D01* +X148121082Y-113301720D01* +X148125500Y-113306627D01* +X148125501Y-113306628D01* +X148239511Y-113433249D01* +X148248869Y-113443642D01* +X148314905Y-113491620D01* +X148378897Y-113538113D01* +X148403370Y-113555894D01* +X148409398Y-113558578D01* +X148409400Y-113558579D01* +X148570076Y-113630116D01* +X148577834Y-113633570D01* +X148644856Y-113647816D01* +X148758178Y-113671904D01* +X148758183Y-113671904D01* +X148764635Y-113673276D01* +X148821186Y-113673276D01* +X148889307Y-113693278D01* +X148935800Y-113746934D01* +X148945623Y-113792092D01* +X148946496Y-113792000D01* +X148965059Y-113968614D01* +X148966458Y-113981928D01* +X149025473Y-114163556D01* +X149028776Y-114169278D01* +X149028777Y-114169279D01* +X149039157Y-114187257D01* +X149120960Y-114328944D01* +X149125378Y-114333851D01* +X149125379Y-114333852D01* +X149235759Y-114456441D01* +X149248747Y-114470866D01* +X149300873Y-114508738D01* +X149384820Y-114569729D01* +X149403248Y-114583118D01* +X149409276Y-114585802D01* +X149409278Y-114585803D01* +X149571681Y-114658109D01* +X149577712Y-114660794D01* +X149653927Y-114676994D01* +X149688599Y-114684364D01* +X149751073Y-114718093D01* +X149785394Y-114780242D01* +X149780666Y-114851081D01* +X149756038Y-114891921D01* +X149642594Y-115017914D01* +X149628960Y-115033056D01* +X149533473Y-115198444D01* +X149474458Y-115380072D01* +X149473768Y-115386633D01* +X149473768Y-115386635D01* +X149472644Y-115397331D01* +X149466996Y-115451075D01* +X149465838Y-115462091D01* +X149438825Y-115527748D01* +X149380604Y-115568378D01* +X149309659Y-115571081D01* +X149276030Y-115554797D01* +X149275192Y-115556248D01* +X149268036Y-115552117D01* +X149261487Y-115547091D01* +X149253861Y-115543932D01* +X149253859Y-115543931D01* +X149142986Y-115498006D01* +X149142983Y-115498005D01* +X149135356Y-115494846D01* +X149000000Y-115477026D01* +X148864644Y-115494846D01* +X148857017Y-115498005D01* +X148857014Y-115498006D01* +X148746141Y-115543931D01* +X148746139Y-115543932D01* +X148738513Y-115547091D01* +X148731963Y-115552117D01* +X148726183Y-115556552D01* +X148630202Y-115630202D01* +X148547091Y-115738513D01* +X148543932Y-115746139D01* +X148543931Y-115746141D01* +X148536740Y-115763503D01* +X148494846Y-115864644D01* +X148494471Y-115867491D01* +X148458820Y-115925984D01* +X148400253Y-115954004D01* +X148399204Y-115954935D01* +X148393217Y-115975784D01* +X148355189Y-116035737D01* +X148348816Y-116040967D01* +X148321704Y-116061771D01* +X148255484Y-116087372D01* +X148185935Y-116073108D01* +X148168295Y-116061771D01* +X148141092Y-116040897D01* +X148099225Y-115983558D01* +X148096901Y-115976433D01* +X148090956Y-115956187D01* +X148077417Y-115954158D01* +X148017806Y-115962006D01* +X148017573Y-115960235D01* +X147972493Y-115960234D01* +X147972324Y-115961519D01* +X147862331Y-115947038D01* +X147862330Y-115947038D01* +X147858244Y-115946500D01* +X147704500Y-115946500D01* +X147636379Y-115926498D01* +X147589886Y-115872842D01* +X147578500Y-115820500D01* +X147578500Y-115666756D01* +X147575702Y-115645499D01* +X147563481Y-115552676D01* +X147565026Y-115552473D01* +X147565026Y-115507527D01* +X147563481Y-115507324D01* +X147577962Y-115397331D01* +X147577962Y-115397330D01* +X147578500Y-115393244D01* +X147578500Y-115166756D01* +X147576642Y-115152639D01* +X147563481Y-115052676D01* +X147565026Y-115052473D01* +X147565026Y-115007527D01* +X147563481Y-115007324D01* +X147577962Y-114897331D01* +X147577962Y-114897330D01* +X147578500Y-114893244D01* +X147578500Y-114666756D01* +X147577038Y-114655647D01* +X147563481Y-114552676D01* +X147565026Y-114552473D01* +X147565026Y-114507527D01* +X147563481Y-114507324D01* +X147577962Y-114397331D01* +X147577962Y-114397330D01* +X147578500Y-114393244D01* +X147578500Y-114166756D01* +X147577731Y-114160911D01* +X147563481Y-114052676D01* +X147565026Y-114052473D01* +X147565026Y-114007527D01* +X147563481Y-114007324D01* +X147577962Y-113897331D01* +X147577962Y-113897330D01* +X147578500Y-113893244D01* +X147578500Y-113666756D01* +X147577026Y-113655556D01* +X147563481Y-113552676D01* +X147565026Y-113552473D01* +X147565026Y-113507527D01* +X147563481Y-113507324D01* +X147577962Y-113397331D01* +X147577962Y-113397330D01* +X147578500Y-113393244D01* +X147578500Y-113166756D01* +X147573798Y-113131037D01* +X147563481Y-113052676D01* +X147565026Y-113052473D01* +X147565026Y-113007527D01* +X147563481Y-113007324D01* +X147577962Y-112897331D01* +X147577962Y-112897330D01* +X147578500Y-112893244D01* +X147578500Y-112789314D01* +X147598502Y-112721193D01* +X147652158Y-112674700D01* +X147722432Y-112664596D01* +X147787012Y-112694090D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X180536121Y-114701002D02* +G01* +X180582614Y-114754658D01* +X180594000Y-114807000D01* +X180594000Y-115435685D01* +X180598519Y-115451075D01* +X180636739Y-115510546D01* +X180636739Y-115581542D01* +X180605469Y-115634246D01* +X180599740Y-115638539D01* +X180512386Y-115755095D01* +X180461256Y-115891484D01* +X180461121Y-115892730D01* +X180427366Y-115951816D01* +X180364411Y-115984637D01* +X180293706Y-115978211D01* +X180237699Y-115934580D01* +X180218971Y-115893572D01* +X180218744Y-115891484D01* +X180167614Y-115755095D01* +X180080260Y-115638539D01* +X180075377Y-115634880D01* +X180042044Y-115573836D01* +X180047109Y-115503021D01* +X180069940Y-115464541D01* +X180084329Y-115447935D01* +X180086000Y-115440252D01* +X180086000Y-114807000D01* +X180106002Y-114738879D01* +X180159658Y-114692386D01* +X180212000Y-114681000D01* +X180468000Y-114681000D01* +X180536121Y-114701002D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X158173075Y-112933502D02* +G01* +X158219568Y-112987158D01* +X158229672Y-113057432D01* +X158219149Y-113092749D01* +X158216039Y-113099419D01* +X158164862Y-113253710D01* +X158161995Y-113267086D01* +X158152328Y-113361438D01* +X158152000Y-113367855D01* +X158152000Y-113392885D01* +X158156475Y-113408124D01* +X158157865Y-113409329D01* +X158165548Y-113411000D01* +X159513000Y-113411000D01* +X159581121Y-113431002D01* +X159627614Y-113484658D01* +X159639000Y-113537000D01* +X159639000Y-113793000D01* +X159618998Y-113861121D01* +X159565342Y-113907614D01* +X159513000Y-113919000D01* +X158170116Y-113919000D01* +X158154877Y-113923475D01* +X158153672Y-113924865D01* +X158152001Y-113932548D01* +X158152001Y-113962095D01* +X158152338Y-113968614D01* +X158162257Y-114064206D01* +X158165149Y-114077600D01* +X158216588Y-114231784D01* +X158222761Y-114244962D01* +X158308063Y-114382807D01* +X158317099Y-114394208D01* +X158431828Y-114508738D01* +X158440762Y-114515794D01* +X158481823Y-114573712D01* +X158485053Y-114644635D01* +X158449426Y-114706046D01* +X158441593Y-114712846D01* +X158435652Y-114716522D01* +X158310695Y-114841697D01* +X158306855Y-114847927D01* +X158306854Y-114847928D01* +X158223253Y-114983554D01* +X158217885Y-114992262D01* +X158211692Y-115010933D01* +X158203654Y-115035167D01* +X158163223Y-115093527D01* +X158097659Y-115120764D01* +X158084061Y-115121500D01* +X156017125Y-115121500D01* +X155949004Y-115101498D01* +X155902511Y-115047842D01* +X155892203Y-114979054D01* +X155902962Y-114897331D01* +X155902962Y-114897330D01* +X155903500Y-114893244D01* +X155903500Y-114666756D01* +X155902038Y-114655647D01* +X155888481Y-114552676D01* +X155890026Y-114552473D01* +X155890026Y-114507527D01* +X155888481Y-114507324D01* +X155902962Y-114397331D01* +X155902962Y-114397330D01* +X155903500Y-114393244D01* +X155903500Y-114166756D01* +X155902731Y-114160911D01* +X155888481Y-114052676D01* +X155890026Y-114052473D01* +X155890026Y-114007527D01* +X155888481Y-114007324D01* +X155902962Y-113897331D01* +X155902962Y-113897330D01* +X155903500Y-113893244D01* +X155903500Y-113666756D01* +X155902026Y-113655556D01* +X155888481Y-113552676D01* +X155890026Y-113552473D01* +X155890026Y-113507527D01* +X155888481Y-113507324D01* +X155902962Y-113397331D01* +X155902962Y-113397330D01* +X155903500Y-113393244D01* +X155903500Y-113166756D01* +X155899736Y-113138166D01* +X155888912Y-113055946D01* +X155899852Y-112985797D01* +X155946980Y-112932699D01* +X156013834Y-112913500D01* +X158104954Y-112913500D01* +X158173075Y-112933502D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X163251339Y-114232005D02* +G01* +X163303351Y-114280329D01* +X163314579Y-114304859D01* +X163321129Y-114324493D01* +X163321133Y-114324503D01* +X163323450Y-114331446D01* +X163416522Y-114481848D01* +X163421704Y-114487021D01* +X163503463Y-114568638D01* +X163537542Y-114630921D01* +X163532539Y-114701741D01* +X163503618Y-114746829D01* +X163421261Y-114829329D01* +X163412249Y-114840740D01* +X163327184Y-114978743D01* +X163321035Y-114991929D01* +X163314800Y-115010725D01* +X163274369Y-115069084D01* +X163208804Y-115096320D01* +X163138923Y-115083786D01* +X163086912Y-115035460D01* +X163075684Y-115010932D01* +X163068868Y-114990502D01* +X163066550Y-114983554D01* +X162973478Y-114833152D01* +X162886891Y-114746716D01* +X162852812Y-114684434D01* +X162857815Y-114613614D01* +X162886736Y-114568525D01* +X162969134Y-114485983D01* +X162969136Y-114485981D01* +X162974305Y-114480803D01* +X162983001Y-114466696D01* +X163063275Y-114336468D01* +X163063276Y-114336466D01* +X163067115Y-114330238D01* +X163075463Y-114305070D01* +X163115893Y-114246709D01* +X163181457Y-114219472D01* +X163251339Y-114232005D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X152127669Y-110112962D02* +G01* +X152127670Y-110112962D01* +X152131756Y-110113500D01* +X152358244Y-110113500D01* +X152362330Y-110112962D01* +X152362331Y-110112962D01* +X152444054Y-110102203D01* +X152514203Y-110113142D01* +X152567301Y-110160271D01* +X152586500Y-110227125D01* +X152586500Y-110448629D01* +X152566498Y-110516750D01* +X152549595Y-110537724D01* +X151735669Y-111351650D01* +X151672772Y-111385801D01* +X151616176Y-111397831D01* +X151616167Y-111397834D01* +X151609712Y-111399206D01* +X151603682Y-111401891D01* +X151603681Y-111401891D01* +X151441278Y-111474197D01* +X151441276Y-111474198D01* +X151435248Y-111476882D01* +X151429907Y-111480762D01* +X151429906Y-111480763D01* +X151400292Y-111502279D01* +X151280747Y-111589134D01* +X151276326Y-111594044D01* +X151276325Y-111594045D01* +X151157999Y-111725460D01* +X151152960Y-111731056D01* +X151107970Y-111808981D01* +X151062415Y-111887885D01* +X151057473Y-111896444D01* +X150998458Y-112078072D01* +X150997768Y-112084633D01* +X150997768Y-112084635D01* +X150980406Y-112249824D01* +X150978496Y-112268000D01* +X150979186Y-112274565D01* +X150995397Y-112428801D01* +X150998458Y-112457928D01* +X151057473Y-112639556D01* +X151060776Y-112645278D01* +X151060777Y-112645279D01* +X151088958Y-112694090D01* +X151152960Y-112804944D01* +X151157378Y-112809851D01* +X151157379Y-112809852D01* +X151267991Y-112932699D01* +X151280747Y-112946866D01* +X151322977Y-112977548D01* +X151404207Y-113036565D01* +X151435248Y-113059118D01* +X151441276Y-113061802D01* +X151441278Y-113061803D01* +X151598019Y-113131588D01* +X151609712Y-113136794D01* +X151688458Y-113153532D01* +X151790056Y-113175128D01* +X151790061Y-113175128D01* +X151796513Y-113176500D01* +X151908803Y-113176500D01* +X151976924Y-113196502D01* +X152023417Y-113250158D01* +X152028636Y-113263563D01* +X152073473Y-113401556D01* +X152076776Y-113407278D01* +X152076777Y-113407279D01* +X152091771Y-113433249D01* +X152168960Y-113566944D01* +X152242137Y-113648215D01* +X152272853Y-113712221D01* +X152274500Y-113732524D01* +X152274500Y-113754239D01* +X152273973Y-113765422D01* +X152272298Y-113772915D01* +X152272547Y-113780841D01* +X152272547Y-113780842D01* +X152274438Y-113840992D01* +X152274500Y-113844951D01* +X152274500Y-113872862D01* +X152274997Y-113876796D01* +X152274997Y-113876797D01* +X152275005Y-113876862D01* +X152275938Y-113888699D01* +X152277327Y-113932895D01* +X152279538Y-113940505D01* +X152279538Y-113940506D01* +X152279941Y-113941893D01* +X152279938Y-113943029D01* +X152280778Y-113948334D01* +X152279922Y-113948470D01* +X152279736Y-114012889D01* +X152241180Y-114072504D01* +X152176515Y-114101811D01* +X152158943Y-114103042D01* +X151999198Y-114103042D01* +X151931077Y-114083040D01* +X151925137Y-114078978D01* +X151849887Y-114024305D01* +X151849886Y-114024304D01* +X151844545Y-114020424D01* +X151838517Y-114017740D01* +X151838515Y-114017739D01* +X151676112Y-113945433D01* +X151676111Y-113945433D01* +X151670081Y-113942748D01* +X151576680Y-113922895D01* +X151489737Y-113904414D01* +X151489732Y-113904414D01* +X151483280Y-113903042D01* +X151292306Y-113903042D01* +X151285854Y-113904414D01* +X151285849Y-113904414D01* +X151198905Y-113922895D01* +X151105505Y-113942748D01* +X151099475Y-113945433D01* +X151099474Y-113945433D01* +X151092653Y-113948470D01* +X150939953Y-114016456D01* +X150869587Y-114025890D01* +X150805290Y-113995784D01* +X150767476Y-113935695D01* +X150763395Y-113888178D01* +X150764585Y-113876862D01* +X150773504Y-113792000D01* +X150767133Y-113731387D01* +X150754232Y-113608635D01* +X150754232Y-113608633D01* +X150753542Y-113602072D01* +X150694527Y-113420444D01* +X150689075Y-113411000D01* +X150650618Y-113344391D01* +X150599040Y-113255056D01* +X150525863Y-113173785D01* +X150495147Y-113109779D01* +X150493500Y-113089476D01* +X150493500Y-110307793D01* +X150495732Y-110284184D01* +X150495790Y-110283881D01* +X150495790Y-110283877D01* +X150497275Y-110276094D01* +X150495427Y-110246718D01* +X150511112Y-110177476D01* +X150561743Y-110127706D01* +X150629085Y-110113148D01* +X150631756Y-110113500D01* +X150858244Y-110113500D01* +X150862330Y-110112962D01* +X150862331Y-110112962D01* +X150972324Y-110098481D01* +X150972527Y-110100026D01* +X151017473Y-110100026D01* +X151017676Y-110098481D01* +X151127669Y-110112962D01* +X151127670Y-110112962D01* +X151131756Y-110113500D01* +X151358244Y-110113500D01* +X151362330Y-110112962D01* +X151362331Y-110112962D01* +X151472324Y-110098481D01* +X151472527Y-110100026D01* +X151517473Y-110100026D01* +X151517676Y-110098481D01* +X151627669Y-110112962D01* +X151627670Y-110112962D01* +X151631756Y-110113500D01* +X151858244Y-110113500D01* +X151862330Y-110112962D01* +X151862331Y-110112962D01* +X151972324Y-110098481D01* +X151972527Y-110100026D01* +X152017473Y-110100026D01* +X152017676Y-110098481D01* +X152127669Y-110112962D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X164604526Y-111778502D02* +G01* +X164651019Y-111832158D01* +X164661123Y-111902432D01* +X164631629Y-111967012D01* +X164625500Y-111973596D01* +X164072742Y-112526353D01* +X164064463Y-112533887D01* +X164057982Y-112538000D01* +X164024550Y-112573602D01* +X164011357Y-112587651D01* +X164008602Y-112590493D01* +X163988865Y-112610230D01* +X163986385Y-112613427D01* +X163978682Y-112622447D01* +X163948414Y-112654679D01* +X163944595Y-112661625D01* +X163944593Y-112661628D01* +X163938652Y-112672434D01* +X163927814Y-112688936D01* +X163926216Y-112690997D01* +X163868668Y-112732575D01* +X163861003Y-112734749D01* +X163858834Y-112734974D01* +X163691054Y-112790950D01* +X163540652Y-112884022D01* +X163415695Y-113009197D01* +X163411855Y-113015427D01* +X163411854Y-113015428D01* +X163336447Y-113137761D01* +X163322885Y-113159762D01* +X163320580Y-113166712D01* +X163314537Y-113184930D01* +X163274107Y-113243291D01* +X163208543Y-113270528D01* +X163138661Y-113257995D01* +X163086649Y-113209671D01* +X163075421Y-113185141D01* +X163068871Y-113165507D01* +X163068867Y-113165497D01* +X163066550Y-113158554D01* +X162973478Y-113008152D01* +X162848303Y-112883195D01* +X162778345Y-112840072D01* +X162703968Y-112794225D01* +X162703966Y-112794224D01* +X162697738Y-112790385D01* +X162644832Y-112772837D01* +X162586473Y-112732406D01* +X162559236Y-112666842D01* +X162558500Y-112653244D01* +X162558500Y-112074594D01* +X162578502Y-112006473D01* +X162595405Y-111985499D01* +X162785499Y-111795405D01* +X162847811Y-111761379D01* +X162874594Y-111758500D01* +X164536405Y-111758500D01* +X164604526Y-111778502D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X163115233Y-97398502D02* +G01* +X163161726Y-97452158D01* +X163172422Y-97517668D01* +X163171186Y-97529431D01* +X163170496Y-97536000D01* +X163171186Y-97542565D01* +X163189501Y-97716819D01* +X163190458Y-97725928D01* +X163249473Y-97907556D01* +X163252776Y-97913278D01* +X163252777Y-97913279D01* +X163276087Y-97953653D01* +X163344960Y-98072944D01* +X163349378Y-98077851D01* +X163349379Y-98077852D01* +X163431137Y-98168653D01* +X163472747Y-98214866D01* +X163627248Y-98327118D01* +X163633276Y-98329802D01* +X163633278Y-98329803D01* +X163795681Y-98402109D01* +X163801712Y-98404794D01* +X163896773Y-98425000D01* +X163954568Y-98437285D01* +X164017467Y-98471437D01* +X164862596Y-99316567D01* +X164896621Y-99378879D01* +X164899500Y-99405662D01* +X164899500Y-109699088D01* +X164899208Y-109707658D01* +X164895831Y-109757203D01* +X164895275Y-109765352D01* +X164904176Y-109816350D01* +X164906261Y-109828299D01* +X164907223Y-109834821D01* +X164914898Y-109898242D01* +X164917581Y-109905343D01* +X164918222Y-109907952D01* +X164922685Y-109924262D01* +X164923450Y-109926798D01* +X164924757Y-109934284D01* +X164946611Y-109984067D01* +X164950442Y-109992795D01* +X164952933Y-109998899D01* +X164975513Y-110058656D01* +X164979817Y-110064919D01* +X164981054Y-110067285D01* +X164989299Y-110082097D01* +X164990632Y-110084351D01* +X164993685Y-110091305D01* +X165030879Y-110139775D01* +X165032579Y-110141991D01* +X165036459Y-110147332D01* +X165068339Y-110193720D01* +X165068344Y-110193725D01* +X165072643Y-110199981D01* +X165078313Y-110205032D01* +X165078314Y-110205034D01* +X165119161Y-110241427D01* +X165124437Y-110246408D01* +X165154434Y-110276405D01* +X165188460Y-110338717D01* +X165183395Y-110409532D01* +X165140848Y-110466368D01* +X165074328Y-110491179D01* +X165065339Y-110491500D01* +X162638768Y-110491500D01* +X162627585Y-110490973D01* +X162620092Y-110489298D01* +X162612166Y-110489547D01* +X162612165Y-110489547D01* +X162552002Y-110491438D01* +X162548044Y-110491500D01* +X162520144Y-110491500D01* +X162516154Y-110492004D01* +X162504320Y-110492936D01* +X162460111Y-110494326D01* +X162452495Y-110496539D01* +X162452493Y-110496539D01* +X162440652Y-110499979D01* +X162421293Y-110503988D01* +X162419983Y-110504154D01* +X162401203Y-110506526D01* +X162393837Y-110509442D01* +X162393831Y-110509444D01* +X162360098Y-110522800D01* +X162348868Y-110526645D01* +X162314017Y-110536770D01* +X162306407Y-110538981D01* +X162299584Y-110543016D01* +X162288966Y-110549295D01* +X162271213Y-110557992D01* +X162263568Y-110561019D01* +X162252383Y-110565448D01* +X162245968Y-110570109D01* +X162216612Y-110591437D01* +X162206695Y-110597951D01* +X162168638Y-110620458D01* +X162154317Y-110634779D01* +X162139284Y-110647619D01* +X162122893Y-110659528D01* +X162106017Y-110679928D01* +X162094712Y-110693593D01* +X162086722Y-110702374D01* +X161532742Y-111256353D01* +X161524463Y-111263887D01* +X161517982Y-111268000D01* +X161485276Y-111302829D01* +X161471357Y-111317651D01* +X161468602Y-111320493D01* +X161448865Y-111340230D01* +X161446385Y-111343427D01* +X161438682Y-111352447D01* +X161408414Y-111384679D01* +X161404595Y-111391625D01* +X161404593Y-111391628D01* +X161398652Y-111402434D01* +X161387801Y-111418953D01* +X161375386Y-111434959D01* +X161372241Y-111442228D01* +X161372238Y-111442232D01* +X161357826Y-111475537D01* +X161352609Y-111486187D01* +X161331305Y-111524940D01* +X161329334Y-111532615D01* +X161329334Y-111532616D01* +X161326267Y-111544562D01* +X161319863Y-111563266D01* +X161311819Y-111581855D01* +X161310580Y-111589678D01* +X161310577Y-111589688D01* +X161304901Y-111625524D01* +X161302495Y-111637144D01* +X161296259Y-111661435D01* +X161291500Y-111679970D01* +X161291500Y-111700224D01* +X161289949Y-111719934D01* +X161286780Y-111739943D01* +X161287526Y-111747835D01* +X161290941Y-111783961D01* +X161291500Y-111795819D01* +X161291500Y-112653303D01* +X161271498Y-112721424D01* +X161217842Y-112767917D01* +X161205377Y-112772826D01* +X161157998Y-112788633D01* +X161157996Y-112788634D01* +X161151054Y-112790950D01* +X161144830Y-112794801D01* +X161144829Y-112794802D01* +X161093776Y-112826395D01* +X161000652Y-112884022D01* +X160875695Y-113009197D01* +X160871855Y-113015427D01* +X160871854Y-113015428D01* +X160863796Y-113028500D01* +X160795993Y-113138498D01* +X160788783Y-113150194D01* +X160736011Y-113197687D01* +X160665939Y-113209111D01* +X160600815Y-113180837D01* +X160562000Y-113123955D01* +X160553414Y-113098221D01* +X160547239Y-113085038D01* +X160461937Y-112947193D01* +X160452901Y-112935792D01* +X160338171Y-112821261D01* +X160326760Y-112812249D01* +X160188757Y-112727184D01* +X160175576Y-112721037D01* +X160021290Y-112669862D01* +X160007914Y-112666995D01* +X159913562Y-112657328D01* +X159907145Y-112657000D01* +X159688095Y-112657000D01* +X159619974Y-112636998D01* +X159573481Y-112583342D01* +X159563377Y-112513068D01* +X159592871Y-112448488D01* +X159599000Y-112441905D01* +X162952253Y-109088652D01* +X162960539Y-109081112D01* +X162967018Y-109077000D01* +X162981156Y-109061945D01* +X163013643Y-109027349D01* +X163016398Y-109024507D01* +X163036135Y-109004770D01* +X163038615Y-109001573D01* +X163046320Y-108992551D01* +X163047554Y-108991237D01* +X163076586Y-108960321D01* +X163080405Y-108953375D01* +X163080407Y-108953372D01* +X163086348Y-108942566D01* +X163097199Y-108926047D01* +X163104758Y-108916301D01* +X163109614Y-108910041D01* +X163112759Y-108902772D01* +X163112762Y-108902768D01* +X163127174Y-108869463D01* +X163132391Y-108858813D01* +X163153695Y-108820060D01* +X163158733Y-108800437D01* +X163165137Y-108781734D01* +X163170033Y-108770420D01* +X163170033Y-108770419D01* +X163173181Y-108763145D01* +X163174420Y-108755322D01* +X163174423Y-108755312D01* +X163180099Y-108719476D01* +X163182505Y-108707856D01* +X163191528Y-108672711D01* +X163191528Y-108672710D01* +X163193500Y-108665030D01* +X163193500Y-108644776D01* +X163195051Y-108625065D01* +X163196980Y-108612886D01* +X163198220Y-108605057D01* +X163194059Y-108561038D01* +X163193500Y-108549181D01* +X163193500Y-99138767D01* +X163194027Y-99127584D01* +X163195702Y-99120091D01* +X163193562Y-99052000D01* +X163193500Y-99048043D01* +X163193500Y-99020144D01* +X163192994Y-99016134D01* +X163192063Y-99004311D01* +X163191941Y-99000405D01* +X163190674Y-98960111D01* +X163188462Y-98952497D01* +X163188461Y-98952492D01* +X163185023Y-98940659D01* +X163181012Y-98921295D01* +X163179467Y-98909064D01* +X163178474Y-98901203D01* +X163175557Y-98893836D01* +X163175556Y-98893831D01* +X163162198Y-98860092D01* +X163158354Y-98848865D01* +X163148230Y-98814022D01* +X163146018Y-98806407D01* +X163135707Y-98788972D01* +X163127012Y-98771224D01* +X163119552Y-98752383D01* +X163093564Y-98716613D01* +X163087048Y-98706693D01* +X163068580Y-98675465D01* +X163068578Y-98675462D01* +X163064542Y-98668638D01* +X163050221Y-98654317D01* +X163037380Y-98639283D01* +X163032913Y-98633134D01* +X163025472Y-98622893D01* +X162991407Y-98594712D01* +X162982626Y-98586722D01* +X162333647Y-97937742D01* +X162326113Y-97929463D01* +X162322000Y-97922982D01* +X162272348Y-97876356D01* +X162269507Y-97873602D01* +X162249770Y-97853865D01* +X162246573Y-97851385D01* +X162237551Y-97843680D01* +X162221168Y-97828295D01* +X162205321Y-97813414D01* +X162198375Y-97809595D01* +X162198372Y-97809593D01* +X162187566Y-97803652D01* +X162171047Y-97792801D01* +X162163760Y-97787149D01* +X162155041Y-97780386D01* +X162147772Y-97777241D01* +X162147768Y-97777238D01* +X162114463Y-97762826D01* +X162103813Y-97757609D01* +X162065060Y-97736305D01* +X162045437Y-97731267D01* +X162026734Y-97724863D01* +X162015420Y-97719967D01* +X162015419Y-97719967D01* +X162008145Y-97716819D01* +X162000322Y-97715580D01* +X162000312Y-97715577D01* +X161964476Y-97709901D01* +X161952856Y-97707495D01* +X161917711Y-97698472D01* +X161917710Y-97698472D01* +X161910030Y-97696500D01* +X161889776Y-97696500D01* +X161870065Y-97694949D01* +X161857886Y-97693020D01* +X161850057Y-97691780D01* +X161842165Y-97692526D01* +X161806039Y-97695941D01* +X161794181Y-97696500D01* +X153979903Y-97696500D01* +X153911782Y-97676498D01* +X153904338Y-97671326D01* +X153887386Y-97658621D01* +X153841705Y-97624385D01* +X153833297Y-97621233D01* +X153825425Y-97616923D01* +X153826534Y-97614898D01* +X153779864Y-97579839D01* +X153755165Y-97513277D01* +X153770373Y-97443928D01* +X153820660Y-97393811D01* +X153880859Y-97378500D01* +X163047112Y-97378500D01* +X163115233Y-97398502D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X161583526Y-98983502D02* +G01* +X161604501Y-99000405D01* +X161889596Y-99285501D01* +X161923621Y-99347813D01* +X161926500Y-99374596D01* +X161926500Y-108270406D01* +X161906498Y-108338527D01* +X161889595Y-108359501D01* +X160299419Y-109949676D01* +X160237107Y-109983702D01* +X160166291Y-109978637D01* +X160116688Y-109944891D01* +X160115762Y-109943862D01* +X160029839Y-109848435D01* +X160000675Y-109816045D01* +X160000674Y-109816044D01* +X159996253Y-109811134D01* +X159841752Y-109698882D01* +X159835724Y-109696198D01* +X159835722Y-109696197D01* +X159673319Y-109623891D01* +X159673318Y-109623891D01* +X159667288Y-109621206D01* +X159565598Y-109599591D01* +X159486944Y-109582872D01* +X159486939Y-109582872D01* +X159480487Y-109581500D01* +X159289513Y-109581500D01* +X159283061Y-109582872D01* +X159283056Y-109582872D01* +X159112265Y-109619175D01* +X159041474Y-109613773D01* +X158984841Y-109570956D01* +X158966235Y-109534865D01* +X158951568Y-109489725D01* +X158951567Y-109489724D01* +X158949527Y-109483444D01* +X158854040Y-109318056D01* +X158846271Y-109309427D01* +X158730675Y-109181045D01* +X158730674Y-109181044D01* +X158726253Y-109176134D01* +X158602286Y-109086066D01* +X158577094Y-109067763D01* +X158577093Y-109067762D01* +X158571752Y-109063882D01* +X158565724Y-109061198D01* +X158565722Y-109061197D01* +X158403319Y-108988891D01* +X158403318Y-108988891D01* +X158397288Y-108986206D01* +X158297823Y-108965064D01* +X158216944Y-108947872D01* +X158216939Y-108947872D01* +X158210487Y-108946500D01* +X158019513Y-108946500D01* +X158013061Y-108947872D01* +X158013056Y-108947872D01* +X157842265Y-108984175D01* +X157771474Y-108978773D01* +X157714841Y-108935956D01* +X157696235Y-108899865D01* +X157681568Y-108854725D01* +X157681567Y-108854724D01* +X157679527Y-108848444D01* +X157584040Y-108683056D01* +X157574726Y-108672711D01* +X157460675Y-108546045D01* +X157460674Y-108546044D01* +X157456253Y-108541134D01* +X157301752Y-108428882D01* +X157295724Y-108426198D01* +X157295722Y-108426197D01* +X157133319Y-108353891D01* +X157133318Y-108353891D01* +X157127288Y-108351206D01* +X157014721Y-108327279D01* +X156946944Y-108312872D01* +X156946939Y-108312872D01* +X156940487Y-108311500D01* +X156749513Y-108311500D01* +X156743061Y-108312872D01* +X156743056Y-108312872D01* +X156675279Y-108327279D01* +X156562712Y-108351206D01* +X156556682Y-108353891D01* +X156556681Y-108353891D01* +X156394278Y-108426197D01* +X156394276Y-108426198D01* +X156388248Y-108428882D01* +X156233747Y-108541134D01* +X156229326Y-108546044D01* +X156229325Y-108546045D01* +X156115275Y-108672711D01* +X156105960Y-108683056D01* +X156077296Y-108732704D01* +X156026798Y-108820169D01* +X156010473Y-108848444D01* +X155951458Y-109030072D01* +X155950768Y-109036633D01* +X155950768Y-109036635D01* +X155946582Y-109076461D01* +X155936107Y-109176134D01* +X155934093Y-109195292D01* +X155907080Y-109260949D01* +X155897878Y-109271217D01* +X155569504Y-109599591D01* +X155507192Y-109633617D01* +X155463963Y-109635418D01* +X155362331Y-109622038D01* +X155362330Y-109622038D01* +X155358244Y-109621500D01* +X154029500Y-109621500D01* +X153961379Y-109601498D01* +X153914886Y-109547842D01* +X153903500Y-109495500D01* +X153903500Y-108135661D01* +X153923502Y-108067540D01* +X153940405Y-108046565D01* +X154196567Y-107790404D01* +X154258879Y-107756379D01* +X154285662Y-107753500D01* +X155118607Y-107753500D01* +X155186728Y-107773502D01* +X155207625Y-107790327D01* +X155261697Y-107844305D01* +X155267927Y-107848145D01* +X155267928Y-107848146D01* +X155405288Y-107932816D01* +X155412262Y-107937115D01* +X155455297Y-107951389D01* +X155573611Y-107990632D01* +X155573613Y-107990632D01* +X155580139Y-107992797D01* +X155586975Y-107993497D01* +X155586978Y-107993498D01* +X155629134Y-107997817D01* +X155684600Y-108003500D01* +X156735400Y-108003500D01* +X156738646Y-108003163D01* +X156738650Y-108003163D01* +X156834308Y-107993238D01* +X156834312Y-107993237D01* +X156841166Y-107992526D01* +X156847702Y-107990345D01* +X156847704Y-107990345D01* +X156998257Y-107940116D01* +X157008946Y-107936550D01* +X157159348Y-107843478D01* +X157212252Y-107790482D01* +X157274535Y-107756403D01* +X157301425Y-107753500D01* +X159002930Y-107753500D01* +X159021880Y-107754933D01* +X159036115Y-107757099D01* +X159036119Y-107757099D01* +X159043349Y-107758199D01* +X159050641Y-107757606D01* +X159050644Y-107757606D01* +X159096018Y-107753915D01* +X159106233Y-107753500D01* +X159114293Y-107753500D01* +X159127583Y-107751951D01* +X159142507Y-107750211D01* +X159146882Y-107749778D01* +X159212339Y-107744454D01* +X159212342Y-107744453D01* +X159219637Y-107743860D01* +X159226601Y-107741604D01* +X159232560Y-107740413D01* +X159238415Y-107739029D01* +X159245681Y-107738182D01* +X159314327Y-107713265D01* +X159318455Y-107711848D01* +X159380936Y-107691607D01* +X159380938Y-107691606D01* +X159387899Y-107689351D01* +X159394154Y-107685555D01* +X159399628Y-107683049D01* +X159405058Y-107680330D01* +X159411937Y-107677833D01* +X159429352Y-107666415D01* +X159472976Y-107637814D01* +X159476680Y-107635477D01* +X159539107Y-107597595D01* +X159547484Y-107590197D01* +X159547508Y-107590224D01* +X159550500Y-107587571D01* +X159553733Y-107584868D01* +X159559852Y-107580856D01* +X159613128Y-107524617D01* +X159615506Y-107522175D01* +X159873911Y-107263770D01* +X159888323Y-107251384D01* +X159899918Y-107242851D01* +X159899923Y-107242846D01* +X159905818Y-107238508D01* +X159910557Y-107232930D01* +X159910560Y-107232927D01* +X159940035Y-107198232D01* +X159946965Y-107190716D01* +X159952660Y-107185021D01* +X159957518Y-107178880D01* +X159970281Y-107162749D01* +X159973072Y-107159345D01* +X160015591Y-107109297D01* +X160015592Y-107109295D01* +X160020333Y-107103715D01* +X160023661Y-107097199D01* +X160027028Y-107092150D01* +X160030195Y-107087021D01* +X160034734Y-107081284D01* +X160065655Y-107015125D01* +X160067561Y-107011225D01* +X160097037Y-106953500D01* +X160100769Y-106946192D01* +X160102508Y-106939084D01* +X160104607Y-106933441D01* +X160106524Y-106927678D01* +X160109622Y-106921050D01* +X160124487Y-106849583D01* +X160125457Y-106845299D01* +X160141473Y-106779845D01* +X160142808Y-106774390D01* +X160143500Y-106763236D01* +X160143536Y-106763238D01* +X160143775Y-106759245D01* +X160144149Y-106755053D01* +X160145640Y-106747885D01* +X160143546Y-106670479D01* +X160143500Y-106667072D01* +X160143500Y-104041999D01* +X160160381Y-103978999D01* +X160216223Y-103882279D01* +X160216224Y-103882278D01* +X160219527Y-103876556D01* +X160278542Y-103694928D01* +X160281814Y-103663803D01* +X160297814Y-103511565D01* +X160298504Y-103505000D01* +X160292583Y-103448661D01* +X160279232Y-103321635D01* +X160279232Y-103321633D01* +X160278542Y-103315072D01* +X160219527Y-103133444D01* +X160214978Y-103125564D01* +X160157947Y-103026784D01* +X160124040Y-102968056D01* +X160116913Y-102960140D01* +X160000675Y-102831045D01* +X160000674Y-102831044D01* +X159996253Y-102826134D01* +X159883828Y-102744452D01* +X159847094Y-102717763D01* +X159847093Y-102717762D01* +X159841752Y-102713882D01* +X159835724Y-102711198D01* +X159835722Y-102711197D01* +X159673319Y-102638891D01* +X159673318Y-102638891D01* +X159667288Y-102636206D01* +X159573887Y-102616353D01* +X159486944Y-102597872D01* +X159486939Y-102597872D01* +X159480487Y-102596500D01* +X159289513Y-102596500D01* +X159283061Y-102597872D01* +X159283056Y-102597872D01* +X159196113Y-102616353D01* +X159102712Y-102636206D01* +X159096682Y-102638891D01* +X159096681Y-102638891D01* +X158934278Y-102711197D01* +X158934276Y-102711198D01* +X158928248Y-102713882D01* +X158922907Y-102717762D01* +X158922906Y-102717763D01* +X158886172Y-102744452D01* +X158773747Y-102826134D01* +X158769326Y-102831044D01* +X158769325Y-102831045D01* +X158653088Y-102960140D01* +X158645960Y-102968056D01* +X158612053Y-103026784D01* +X158555023Y-103125564D01* +X158550473Y-103133444D01* +X158491458Y-103315072D01* +X158490768Y-103321633D01* +X158490768Y-103321635D01* +X158477417Y-103448661D01* +X158471496Y-103505000D01* +X158472186Y-103511565D01* +X158488187Y-103663803D01* +X158491458Y-103694928D01* +X158550473Y-103876556D01* +X158553776Y-103882278D01* +X158553777Y-103882279D01* +X158609619Y-103978999D01* +X158626500Y-104041999D01* +X158626500Y-106110500D01* +X158606498Y-106178621D01* +X158552842Y-106225114D01* +X158500500Y-106236500D01* +X157301393Y-106236500D01* +X157233272Y-106216498D01* +X157212375Y-106199673D01* +X157163485Y-106150868D01* +X157158303Y-106145695D01* +X157153765Y-106142898D01* +X157113176Y-106085647D01* +X157109946Y-106014724D01* +X157145572Y-105953313D01* +X157154068Y-105945938D01* +X157164207Y-105937902D01* +X157278739Y-105823171D01* +X157287751Y-105811760D01* +X157372816Y-105673757D01* +X157378963Y-105660576D01* +X157430138Y-105506290D01* +X157433005Y-105492914D01* +X157442672Y-105398562D01* +X157443000Y-105392146D01* +X157443000Y-105367115D01* +X157438525Y-105351876D01* +X157437135Y-105350671D01* +X157429452Y-105349000D01* +X154995116Y-105349000D01* +X154979877Y-105353475D01* +X154978672Y-105354865D01* +X154977001Y-105362548D01* +X154977001Y-105392095D01* +X154977338Y-105398614D01* +X154987257Y-105494206D01* +X154990149Y-105507600D01* +X155041588Y-105661784D01* +X155047761Y-105674962D01* +X155133063Y-105812807D01* +X155142099Y-105824208D01* +X155256828Y-105938738D01* +X155265762Y-105945794D01* +X155306823Y-106003712D01* +X155310053Y-106074635D01* +X155274426Y-106136046D01* +X155266593Y-106142846D01* +X155260652Y-106146522D01* +X155255479Y-106151704D01* +X155207748Y-106199518D01* +X155145465Y-106233597D01* +X155118575Y-106236500D01* +X153945707Y-106236500D01* +X153875964Y-106244631D01* +X153821589Y-106250970D01* +X153821585Y-106250971D01* +X153814319Y-106251818D01* +X153807444Y-106254313D01* +X153807442Y-106254314D01* +X153702012Y-106292584D01* +X153648063Y-106312167D01* +X153641946Y-106316178D01* +X153641943Y-106316179D01* +X153506267Y-106405132D01* +X153500148Y-106409144D01* +X153378510Y-106537547D01* +X153306150Y-106662124D01* +X153293949Y-106683130D01* +X153274090Y-106708940D01* +X153093595Y-106889435D01* +X153031283Y-106923461D01* +X152960468Y-106918396D01* +X152903632Y-106875849D01* +X152878821Y-106809329D01* +X152878500Y-106800340D01* +X152878500Y-106373267D01* +X152879027Y-106362084D01* +X152880702Y-106354591D01* +X152880017Y-106332779D01* +X152878699Y-106290867D01* +X152884803Y-106247974D01* +X152887003Y-106241204D01* +X152887003Y-106241202D01* +X152889042Y-106234928D01* +X152890074Y-106225114D01* +X152908314Y-106051565D01* +X152909004Y-106045000D01* +X152902943Y-105987330D01* +X152889732Y-105861635D01* +X152889732Y-105861633D01* +X152889042Y-105855072D01* +X152830027Y-105673444D01* +X152823007Y-105661284D01* +X152765219Y-105561194D01* +X152734540Y-105508056D01* +X152722070Y-105494206D01* +X152611175Y-105371045D01* +X152611174Y-105371044D01* +X152606753Y-105366134D01* +X152452252Y-105253882D01* +X152446224Y-105251198D01* +X152446222Y-105251197D01* +X152283819Y-105178891D01* +X152283818Y-105178891D01* +X152277788Y-105176206D01* +X152184387Y-105156353D01* +X152097444Y-105137872D01* +X152097439Y-105137872D01* +X152090987Y-105136500D01* +X151900013Y-105136500D01* +X151893561Y-105137872D01* +X151893556Y-105137872D01* +X151806613Y-105156353D01* +X151713212Y-105176206D01* +X151707182Y-105178891D01* +X151707181Y-105178891D01* +X151683791Y-105189305D01* +X151555748Y-105246313D01* +X151485382Y-105255747D01* +X151421085Y-105225641D01* +X151383271Y-105165552D01* +X151378500Y-105131206D01* +X151378500Y-104822885D01* +X154977000Y-104822885D01* +X154981475Y-104838124D01* +X154982865Y-104839329D01* +X154990548Y-104841000D01* +X155937885Y-104841000D01* +X155953124Y-104836525D01* +X155954329Y-104835135D01* +X155956000Y-104827452D01* +X155956000Y-104822885D01* +X156464000Y-104822885D01* +X156468475Y-104838124D01* +X156469865Y-104839329D01* +X156477548Y-104841000D01* +X157424884Y-104841000D01* +X157440123Y-104836525D01* +X157441328Y-104835135D01* +X157442999Y-104827452D01* +X157442999Y-104797905D01* +X157442662Y-104791386D01* +X157432743Y-104695794D01* +X157429851Y-104682400D01* +X157378412Y-104528216D01* +X157372239Y-104515038D01* +X157286937Y-104377193D01* +X157277901Y-104365792D01* +X157163171Y-104251261D01* +X157151760Y-104242249D01* +X157013757Y-104157184D01* +X157000576Y-104151037D01* +X156846290Y-104099862D01* +X156832914Y-104096995D01* +X156738562Y-104087328D01* +X156732145Y-104087000D01* +X156482115Y-104087000D01* +X156466876Y-104091475D01* +X156465671Y-104092865D01* +X156464000Y-104100548D01* +X156464000Y-104822885D01* +X155956000Y-104822885D01* +X155956000Y-104105116D01* +X155951525Y-104089877D01* +X155950135Y-104088672D01* +X155942452Y-104087001D01* +X155687905Y-104087001D01* +X155681386Y-104087338D01* +X155585794Y-104097257D01* +X155572400Y-104100149D01* +X155418216Y-104151588D01* +X155405038Y-104157761D01* +X155267193Y-104243063D01* +X155255792Y-104252099D01* +X155141261Y-104366829D01* +X155132249Y-104378240D01* +X155047184Y-104516243D01* +X155041037Y-104529424D01* +X154989862Y-104683710D01* +X154986995Y-104697086D01* +X154977328Y-104791438D01* +X154977000Y-104797855D01* +X154977000Y-104822885D01* +X151378500Y-104822885D01* +X151378500Y-103089500D01* +X151398502Y-103021379D01* +X151452158Y-102974886D01* +X151504500Y-102963500D01* +X152110097Y-102963500D01* +X152178218Y-102983502D01* +X152185657Y-102988671D01* +X152248295Y-103035615D01* +X152384684Y-103086745D01* +X152446866Y-103093500D01* +X153643134Y-103093500D01* +X153705316Y-103086745D01* +X153841705Y-103035615D01* +X153958261Y-102948261D01* +X154045615Y-102831705D01* +X154096745Y-102695316D01* +X154103500Y-102633134D01* +X154103500Y-102026866D01* +X154096745Y-101964684D01* +X154062835Y-101874229D01* +X154057652Y-101803423D01* +X154062835Y-101785770D01* +X154065786Y-101777899D01* +X154096745Y-101695316D01* +X154103500Y-101633134D01* +X154103500Y-101026866D01* +X154096745Y-100964684D01* +X154062835Y-100874229D01* +X154057652Y-100803423D01* +X154062835Y-100785770D01* +X154069673Y-100767531D01* +X154096745Y-100695316D01* +X154103500Y-100633134D01* +X154103500Y-100089500D01* +X154123502Y-100021379D01* +X154177158Y-99974886D01* +X154229500Y-99963500D01* +X154591233Y-99963500D01* +X154602416Y-99964027D01* +X154609909Y-99965702D01* +X154617835Y-99965453D01* +X154617836Y-99965453D01* +X154677986Y-99963562D01* +X154681945Y-99963500D01* +X154709856Y-99963500D01* +X154713791Y-99963003D01* +X154713856Y-99962995D01* +X154725693Y-99962062D01* +X154757951Y-99961048D01* +X154761970Y-99960922D01* +X154769889Y-99960673D01* +X154770663Y-99960448D01* +X154811680Y-99961522D01* +X154838047Y-99967127D01* +X154838060Y-99967128D01* +X154844513Y-99968500D01* +X155035487Y-99968500D01* +X155041939Y-99967128D01* +X155041944Y-99967128D01* +X155130990Y-99948200D01* +X155222288Y-99928794D01* +X155253012Y-99915115D01* +X155390722Y-99853803D01* +X155390724Y-99853802D01* +X155396752Y-99851118D01* +X155427900Y-99828488D01* +X155485715Y-99786482D01* +X155551253Y-99738866D01* +X155555675Y-99733955D01* +X155674621Y-99601852D01* +X155674625Y-99601847D01* +X155679040Y-99596944D01* +X155745159Y-99482422D01* +X155771223Y-99437279D01* +X155771224Y-99437278D01* +X155774527Y-99431556D01* +X155833542Y-99249928D01* +X155834904Y-99236976D01* +X155851788Y-99076329D01* +X155878801Y-99010673D01* +X155937023Y-98970043D01* +X155977098Y-98963500D01* +X161515405Y-98963500D01* +X161583526Y-98983502D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X150525046Y-95931574D02* +G01* +X150531846Y-95939407D01* +X150535522Y-95945348D01* +X150540704Y-95950521D01* +X150588518Y-95998252D01* +X150622597Y-96060535D01* +X150625500Y-96087425D01* +X150625500Y-99881930D01* +X150624067Y-99900880D01* +X150622471Y-99911373D01* +X150620801Y-99922349D01* +X150621394Y-99929641D01* +X150621394Y-99929644D01* +X150625085Y-99975018D01* +X150625500Y-99985233D01* +X150625500Y-99993293D01* +X150625925Y-99996937D01* +X150628789Y-100021507D01* +X150629222Y-100025882D01* +X150634397Y-100089500D01* +X150635140Y-100098637D01* +X150637396Y-100105601D01* +X150638587Y-100111560D01* +X150639971Y-100117415D01* +X150640818Y-100124681D01* +X150665735Y-100193327D01* +X150667152Y-100197455D01* +X150685542Y-100254220D01* +X150689649Y-100266899D01* +X150693445Y-100273154D01* +X150695951Y-100278628D01* +X150698670Y-100284058D01* +X150701167Y-100290937D01* +X150705180Y-100297057D01* +X150705180Y-100297058D01* +X150741186Y-100351976D01* +X150743523Y-100355680D01* +X150781405Y-100418107D01* +X150785121Y-100422315D01* +X150785122Y-100422316D01* +X150788803Y-100426484D01* +X150788776Y-100426508D01* +X150791429Y-100429500D01* +X150794132Y-100432733D01* +X150798144Y-100438852D01* +X150821303Y-100460791D01* +X150840526Y-100479001D01* +X150876224Y-100540371D01* +X150873076Y-100611297D01* +X150832083Y-100669263D01* +X150766258Y-100695864D01* +X150757876Y-100696410D01* +X150757058Y-100696436D01* +X150753055Y-100696500D01* +X150725144Y-100696500D01* +X150721210Y-100696997D01* +X150721209Y-100696997D01* +X150721144Y-100697005D01* +X150709307Y-100697938D01* +X150677049Y-100698952D01* +X150673030Y-100699078D01* +X150665111Y-100699327D01* +X150645657Y-100704979D01* +X150626300Y-100708987D01* +X150614070Y-100710532D01* +X150614069Y-100710532D01* +X150606203Y-100711526D01* +X150598832Y-100714445D01* +X150598830Y-100714445D01* +X150565088Y-100727804D01* +X150553858Y-100731649D01* +X150519017Y-100741771D01* +X150519016Y-100741771D01* +X150511407Y-100743982D01* +X150504588Y-100748015D01* +X150504583Y-100748017D01* +X150493972Y-100754293D01* +X150476224Y-100762988D01* +X150457383Y-100770448D01* +X150450967Y-100775110D01* +X150450966Y-100775110D01* +X150421613Y-100796436D01* +X150411693Y-100802952D01* +X150380465Y-100821420D01* +X150380462Y-100821422D01* +X150373638Y-100825458D01* +X150359317Y-100839779D01* +X150344284Y-100852619D01* +X150327893Y-100864528D01* +X150316448Y-100878363D01* +X150299712Y-100898593D01* +X150291722Y-100907374D01* +X149852742Y-101346353D01* +X149844463Y-101353887D01* +X149837982Y-101358000D01* +X149799053Y-101399456D01* +X149791357Y-101407651D01* +X149788602Y-101410493D01* +X149768865Y-101430230D01* +X149766385Y-101433427D01* +X149758682Y-101442447D01* +X149728414Y-101474679D01* +X149724595Y-101481625D01* +X149724593Y-101481628D01* +X149718652Y-101492434D01* +X149707801Y-101508953D01* +X149695386Y-101524959D01* +X149692241Y-101532228D01* +X149692238Y-101532232D01* +X149677826Y-101565537D01* +X149672609Y-101576187D01* +X149651305Y-101614940D01* +X149649334Y-101622615D01* +X149649334Y-101622616D01* +X149646267Y-101634562D01* +X149639863Y-101653266D01* +X149631819Y-101671855D01* +X149630580Y-101679678D01* +X149630577Y-101679688D01* +X149624901Y-101715524D01* +X149622495Y-101727144D01* +X149613532Y-101762055D01* +X149611500Y-101769970D01* +X149611500Y-101790224D01* +X149609949Y-101809934D01* +X149606780Y-101829943D01* +X149607526Y-101837835D01* +X149610941Y-101873961D01* +X149611500Y-101885819D01* +X149611500Y-105378803D01* +X149591498Y-105446924D01* +X149537842Y-105493417D01* +X149467568Y-105503521D01* +X149402988Y-105474027D01* +X149364103Y-105411178D01* +X149363474Y-105406203D01* +X149360484Y-105398650D01* +X149347200Y-105365097D01* +X149343355Y-105353870D01* +X149338308Y-105336500D01* +X149331018Y-105311407D01* +X149326984Y-105304585D01* +X149326981Y-105304579D01* +X149320706Y-105293968D01* +X149312010Y-105276218D01* +X149307472Y-105264756D01* +X149307469Y-105264751D01* +X149304552Y-105257383D01* +X149287861Y-105234410D01* +X149278573Y-105221625D01* +X149272057Y-105211707D01* +X149260341Y-105191897D01* +X149249542Y-105173637D01* +X149235218Y-105159313D01* +X149222376Y-105144278D01* +X149210472Y-105127893D01* +X149176406Y-105099711D01* +X149167627Y-105091722D01* +X148839652Y-104763747D01* +X148832112Y-104755461D01* +X148828000Y-104748982D01* +X148803035Y-104725538D01* +X148778349Y-104702357D01* +X148775507Y-104699602D01* +X148755770Y-104679865D01* +X148752573Y-104677385D01* +X148743551Y-104669680D01* +X148717100Y-104644841D01* +X148711321Y-104639414D01* +X148704375Y-104635595D01* +X148704372Y-104635593D01* +X148693566Y-104629652D01* +X148677047Y-104618801D01* +X148673690Y-104616197D01* +X148661041Y-104606386D01* +X148653772Y-104603241D01* +X148653768Y-104603238D01* +X148620463Y-104588826D01* +X148609813Y-104583609D01* +X148571060Y-104562305D01* +X148551437Y-104557267D01* +X148532734Y-104550863D01* +X148521420Y-104545967D01* +X148521419Y-104545967D01* +X148514145Y-104542819D01* +X148506322Y-104541580D01* +X148506312Y-104541577D01* +X148470476Y-104535901D01* +X148458856Y-104533495D01* +X148423711Y-104524472D01* +X148423710Y-104524472D01* +X148416030Y-104522500D01* +X148395776Y-104522500D01* +X148376065Y-104520949D01* +X148363886Y-104519020D01* +X148356057Y-104517780D01* +X148348165Y-104518526D01* +X148312039Y-104521941D01* +X148300181Y-104522500D01* +X145276395Y-104522500D01* +X145208274Y-104502498D01* +X145161781Y-104448842D01* +X145151677Y-104378568D01* +X145156563Y-104357562D01* +X145163502Y-104336208D01* +X145163503Y-104336203D01* +X145165542Y-104329928D01* +X145170858Y-104279355D01* +X145184814Y-104146565D01* +X145185504Y-104140000D01* +X145181410Y-104101045D01* +X145166232Y-103956635D01* +X145166232Y-103956633D01* +X145165542Y-103950072D01* +X145106527Y-103768444D01* +X145076466Y-103716376D01* +X145018008Y-103615125D01* +X145011040Y-103603056D01* +X144937863Y-103521785D01* +X144907147Y-103457779D01* +X144905500Y-103437476D01* +X144905500Y-103074754D01* +X144925502Y-103006633D01* +X144979158Y-102960140D01* +X145049432Y-102950036D01* +X145114012Y-102979530D01* +X145152396Y-103039256D01* +X145154746Y-103048556D01* +X145155768Y-103053364D01* +X145156458Y-103059928D01* +X145215473Y-103241556D01* +X145218776Y-103247278D01* +X145218777Y-103247279D01* +X145236685Y-103278296D01* +X145310960Y-103406944D01* +X145315378Y-103411851D01* +X145315379Y-103411852D01* +X145399250Y-103505000D01* +X145438747Y-103548866D01* +X145507065Y-103598502D01* +X145584372Y-103654669D01* +X145593248Y-103661118D01* +X145599276Y-103663802D01* +X145599278Y-103663803D01* +X145761681Y-103736109D01* +X145767712Y-103738794D01* +X145861112Y-103758647D01* +X145948056Y-103777128D01* +X145948061Y-103777128D01* +X145954513Y-103778500D01* +X146145487Y-103778500D01* +X146151939Y-103777128D01* +X146151944Y-103777128D01* +X146238887Y-103758647D01* +X146332288Y-103738794D01* +X146338319Y-103736109D01* +X146500722Y-103663803D01* +X146500724Y-103663802D01* +X146506752Y-103661118D01* +X146515629Y-103654669D01* +X146592935Y-103598502D01* +X146661253Y-103548866D01* +X146700750Y-103505000D01* +X146784621Y-103411852D01* +X146784622Y-103411851D01* +X146789040Y-103406944D01* +X146863315Y-103278296D01* +X146881223Y-103247279D01* +X146881224Y-103247278D01* +X146884527Y-103241556D01* +X146922216Y-103125563D01* +X146962288Y-103066958D01* +X147027685Y-103039321D01* +X147042048Y-103038500D01* +X147133149Y-103038500D01* +X147177379Y-103046518D01* +X147284684Y-103086745D01* +X147346866Y-103093500D01* +X148543134Y-103093500D01* +X148605316Y-103086745D01* +X148741705Y-103035615D01* +X148858261Y-102948261D01* +X148945615Y-102831705D01* +X148996745Y-102695316D01* +X149003500Y-102633134D01* +X149003500Y-102026866D01* +X148996745Y-101964684D01* +X148962835Y-101874229D01* +X148957652Y-101803423D01* +X148962835Y-101785770D01* +X148965786Y-101777899D01* +X148996745Y-101695316D01* +X149003500Y-101633134D01* +X149003500Y-101026866D01* +X148996745Y-100964684D01* +X148962568Y-100873517D01* +X148957385Y-100802711D01* +X148962568Y-100785058D01* +X148993478Y-100702606D01* +X148997105Y-100687351D01* +X149002631Y-100636486D01* +X149003000Y-100629672D01* +X149003000Y-100602115D01* +X148998525Y-100586876D01* +X148997135Y-100585671D01* +X148989452Y-100584000D01* +X148656820Y-100584000D01* +X148620505Y-100577416D01* +X148620400Y-100577856D01* +X148612716Y-100576029D01* +X148605316Y-100573255D01* +X148543134Y-100566500D01* +X147346866Y-100566500D01* +X147284684Y-100573255D01* +X147277284Y-100576029D01* +X147269600Y-100577856D01* +X147269495Y-100577416D01* +X147233180Y-100584000D01* +X146905116Y-100584000D01* +X146876594Y-100592375D01* +X146839217Y-100616396D01* +X146803718Y-100621500D01* +X145713927Y-100621500D01* +X145705358Y-100621208D01* +X145655225Y-100617790D01* +X145655221Y-100617790D01* +X145647648Y-100617274D01* +X145584681Y-100628264D01* +X145578169Y-100629224D01* +X145514758Y-100636898D01* +X145507657Y-100639581D01* +X145505048Y-100640222D01* +X145488728Y-100644687D01* +X145486195Y-100645452D01* +X145478717Y-100646757D01* +X145420190Y-100672448D01* +X145414109Y-100674930D01* +X145397823Y-100681084D01* +X145391784Y-100683366D01* +X145347247Y-100691500D01* +X145319513Y-100691500D01* +X145313061Y-100692872D01* +X145313056Y-100692872D01* +X145229975Y-100710532D01* +X145132712Y-100731206D01* +X145126682Y-100733891D01* +X145126681Y-100733891D01* +X145082749Y-100753451D01* +X145012382Y-100762885D01* +X144948085Y-100732779D01* +X144910271Y-100672690D01* +X144905500Y-100638344D01* +X144905500Y-99762524D01* +X144925502Y-99694403D01* +X144937858Y-99678221D01* +X145011040Y-99596944D01* +X145077159Y-99482422D01* +X145103223Y-99437279D01* +X145103224Y-99437278D01* +X145106527Y-99431556D01* +X145139362Y-99330500D01* +X145145844Y-99310552D01* +X145185918Y-99251947D01* +X145251315Y-99224310D01* +X145321271Y-99236417D01* +X145373577Y-99284424D01* +X145381045Y-99298832D01* +X145392452Y-99324819D01* +X145394933Y-99330899D01* +X145417513Y-99390656D01* +X145421817Y-99396919D01* +X145423054Y-99399285D01* +X145431299Y-99414097D01* +X145432632Y-99416351D01* +X145435685Y-99423305D01* +X145470909Y-99469208D01* +X145474579Y-99473991D01* +X145478459Y-99479332D01* +X145510339Y-99525720D01* +X145510344Y-99525725D01* +X145514643Y-99531981D01* +X145520313Y-99537032D01* +X145520314Y-99537034D01* +X145561170Y-99573435D01* +X145566446Y-99578416D01* +X145798550Y-99810520D01* +X145804404Y-99816785D01* +X145842439Y-99860385D01* +X145860197Y-99872865D01* +X145894697Y-99897112D01* +X145899993Y-99901045D01* +X145950282Y-99940477D01* +X145957204Y-99943602D01* +X145959452Y-99944964D01* +X145974185Y-99953368D01* +X145976524Y-99954622D01* +X145982739Y-99958990D01* +X145989815Y-99961749D01* +X145989819Y-99961751D01* +X146042269Y-99982200D01* +X146048334Y-99984749D01* +X146106573Y-100011045D01* +X146114038Y-100012429D01* +X146116582Y-100013226D01* +X146132848Y-100017859D01* +X146135428Y-100018521D01* +X146142509Y-100021282D01* +X146150042Y-100022274D01* +X146150043Y-100022274D01* +X146182699Y-100026573D01* +X146205857Y-100029622D01* +X146212355Y-100030650D01* +X146275187Y-100042296D01* +X146282767Y-100041859D01* +X146282768Y-100041859D01* +X146337398Y-100038709D01* +X146344651Y-100038500D01* +X146804521Y-100038500D01* +X146872642Y-100058502D01* +X146887034Y-100069276D01* +X146892865Y-100074329D01* +X146900548Y-100076000D01* +X147233180Y-100076000D01* +X147269495Y-100082584D01* +X147269600Y-100082144D01* +X147277284Y-100083971D01* +X147284684Y-100086745D01* +X147346866Y-100093500D01* +X148543134Y-100093500D01* +X148605316Y-100086745D01* +X148612716Y-100083971D01* +X148620400Y-100082144D01* +X148620505Y-100082584D01* +X148656820Y-100076000D01* +X148984884Y-100076000D01* +X149000123Y-100071525D01* +X149001328Y-100070135D01* +X149002999Y-100062452D01* +X149002999Y-100030331D01* +X149002629Y-100023510D01* +X148997105Y-99972648D01* +X148993479Y-99957397D01* +X148962568Y-99874942D01* +X148957385Y-99804135D01* +X148962568Y-99786482D01* +X148969813Y-99767158D01* +X148996745Y-99695316D01* +X149003500Y-99633134D01* +X149003500Y-99026866D01* +X148996745Y-98964684D01* +X148962835Y-98874229D01* +X148957652Y-98803423D01* +X148962835Y-98785770D01* +X148968292Y-98771213D01* +X148996745Y-98695316D01* +X149003500Y-98633134D01* +X149003500Y-98026866D01* +X148996745Y-97964684D01* +X148945615Y-97828295D01* +X148858261Y-97711739D01* +X148741705Y-97624385D01* +X148733296Y-97621233D01* +X148725425Y-97616923D01* +X148726336Y-97615259D01* +X148678510Y-97579337D01* +X148653807Y-97512776D01* +X148653500Y-97503991D01* +X148653500Y-96606268D01* +X148673502Y-96538147D01* +X148727158Y-96491654D01* +X148797432Y-96481550D01* +X148827717Y-96489859D01* +X148857011Y-96501993D01* +X148857016Y-96501994D01* +X148864644Y-96505154D01* +X149000000Y-96522974D01* +X149008188Y-96521896D01* +X149127168Y-96506232D01* +X149135356Y-96505154D01* +X149142983Y-96501995D01* +X149142986Y-96501994D01* +X149253859Y-96456069D01* +X149253861Y-96456068D01* +X149261487Y-96452909D01* +X149369798Y-96369798D01* +X149452909Y-96261487D01* +X149458096Y-96248966D01* +X149495591Y-96158443D01* +X149540139Y-96103162D01* +X149607503Y-96080741D01* +X149676294Y-96098299D01* +X149724672Y-96150261D01* +X149738000Y-96206661D01* +X149738000Y-96210884D01* +X149742475Y-96226123D01* +X149743865Y-96227328D01* +X149751548Y-96228999D01* +X149781095Y-96228999D01* +X149787614Y-96228662D01* +X149883206Y-96218743D01* +X149896600Y-96215851D01* +X150050784Y-96164412D01* +X150063962Y-96158239D01* +X150201807Y-96072937D01* +X150213208Y-96063901D01* +X150327738Y-95949172D01* +X150334794Y-95940238D01* +X150392712Y-95899177D01* +X150463635Y-95895947D01* +X150525046Y-95931574D01* +G37* +%TD.AperFunction*% +%TA.AperFunction,Conductor*% +G36* +X129928527Y-80028502D02* +G01* +X129949501Y-80045405D01* +X130329595Y-80425499D01* +X130363621Y-80487811D01* +X130366500Y-80514594D01* +X130366500Y-80641692D01* +X130346498Y-80709813D01* +X130298683Y-80753453D01* +X130273607Y-80766507D01* +X130269474Y-80769610D01* +X130269471Y-80769612D01* +X130099128Y-80897509D01* +X130094965Y-80900635D01* +X130091393Y-80904373D01* +X129981231Y-81019651D01* +X129940629Y-81062138D01* +X129867693Y-81169059D01* +X129832898Y-81220066D01* +X129777987Y-81265069D01* +X129707462Y-81273240D01* +X129643715Y-81241986D01* +X129623017Y-81217501D01* +X129593062Y-81171197D01* +X129582377Y-81161995D01* +X129572812Y-81166398D01* +X127706737Y-83032473D01* +X127699977Y-83044853D01* +X127705258Y-83051907D01* +X127751969Y-83079203D01* +X127800693Y-83130841D01* +X127813764Y-83200624D01* +X127787033Y-83266396D01* +X127746584Y-83299752D01* +X127733607Y-83306507D01* +X127729474Y-83309610D01* +X127729471Y-83309612D01* +X127559100Y-83437530D01* +X127554965Y-83440635D01* +X127551393Y-83444373D01* +X127417328Y-83584664D01* +X127400629Y-83602138D01* +X127397715Y-83606410D01* +X127397714Y-83606411D01* +X127350801Y-83675183D01* +X127274743Y-83786680D01* +X127257241Y-83824386D01* +X127186351Y-83977106D01* +X127180688Y-83989305D01* +X127120989Y-84204570D01* +X127097251Y-84426695D01* +X127097548Y-84431848D01* +X127097548Y-84431851D01* +X127104273Y-84548479D01* +X127110110Y-84649715D01* +X127111247Y-84654761D01* +X127111248Y-84654767D01* +X127120095Y-84694022D01* +X127159222Y-84867639D01* +X127207352Y-84986169D01* +X127235920Y-85056524D01* +X127243266Y-85074616D01* +X127281087Y-85136334D01* +X127357291Y-85260688D01* +X127359987Y-85265088D01* +X127506250Y-85433938D01* +X127616889Y-85525792D01* +X127670944Y-85570669D01* +X127678126Y-85576632D01* +X127748478Y-85617742D01* +X127751445Y-85619476D01* +X127800169Y-85671114D01* +X127813240Y-85740897D01* +X127786509Y-85806669D01* +X127746055Y-85840027D01* +X127733607Y-85846507D01* +X127729474Y-85849610D01* +X127729471Y-85849612D01* +X127559100Y-85977530D01* +X127554965Y-85980635D01* +X127529272Y-86007521D01* +X127416961Y-86125048D01* +X127400629Y-86142138D01* +X127397715Y-86146410D01* +X127397714Y-86146411D01* +X127350056Y-86216275D01* +X127274743Y-86326680D01* +X127243458Y-86394079D01* +X127183520Y-86523205D01* +X127180688Y-86529305D01* +X127120989Y-86744570D01* +X127097251Y-86966695D01* +X127097548Y-86971848D01* +X127097548Y-86971851D01* +X127108995Y-87170385D01* +X127110110Y-87189715D01* +X127111247Y-87194761D01* +X127111248Y-87194767D01* +X127135304Y-87301508D01* +X127159222Y-87407639D01* +X127210243Y-87533290D01* +X127232865Y-87589000D01* +X127243266Y-87614616D01* +X127267154Y-87653598D01* +X127354172Y-87795598D01* +X127359987Y-87805088D01* +X127506250Y-87973938D01* +X127678126Y-88116632D01* +X127689070Y-88123027D01* +X127737793Y-88174664D01* +X127751500Y-88231815D01* +X127751500Y-89168454D01* +X127732760Y-89234570D01* +X127647885Y-89372262D01* +X127639942Y-89396209D01* +X127595615Y-89529853D01* +X127592203Y-89540139D01* +X127591503Y-89546975D01* +X127591502Y-89546978D01* +X127590027Y-89561376D01* +X127581500Y-89644600D01* +X127581500Y-90695400D01* +X127581837Y-90698646D01* +X127581837Y-90698650D01* +X127588985Y-90767538D01* +X127592474Y-90801166D01* +X127648450Y-90968946D01* +X127741522Y-91119348D01* +X127746704Y-91124521D01* +X127844518Y-91222165D01* +X127878597Y-91284448D01* +X127881500Y-91311338D01* +X127881500Y-91731088D01* +X127881208Y-91739658D01* +X127878181Y-91784068D01* +X127877275Y-91797352D01* +X127878580Y-91804829D01* +X127878580Y-91804830D01* +X127880703Y-91816994D01* +X127885987Y-91847267D01* +X127888261Y-91860299D01* +X127889223Y-91866821D01* +X127893199Y-91899676D01* +X127896898Y-91930242D01* +X127894982Y-91930474D01* +X127892258Y-91991367D01* +X127851243Y-92049318D01* +X127785408Y-92075894D01* +X127773069Y-92076500D01* +X126044595Y-92076500D01* +X125976474Y-92056498D01* +X125955499Y-92039595D01* +X125765404Y-91849499D01* +X125731379Y-91787187D01* +X125728500Y-91760404D01* +X125728500Y-81891863D01* +X127098050Y-81891863D01* +X127110309Y-82104477D01* +X127111745Y-82114697D01* +X127158565Y-82322446D01* +X127161645Y-82332275D01* +X127241770Y-82529603D01* +X127246413Y-82538794D01* +X127326460Y-82669420D01* +X127336916Y-82678880D01* +X127345694Y-82675096D01* +X128087978Y-81932812D01* +X128095592Y-81918868D01* +X128095461Y-81917035D01* +X128091210Y-81910420D01* +X127349849Y-81169059D01* +X127338313Y-81162759D01* +X127326031Y-81172382D01* +X127278089Y-81242662D01* +X127273004Y-81251613D01* +X127183338Y-81444783D01* +X127179775Y-81454470D01* +X127122864Y-81659681D01* +X127120933Y-81669800D01* +X127098302Y-81881574D01* +X127098050Y-81891863D01* +X125728500Y-81891863D01* +X125728500Y-80796427D01* +X127701223Y-80796427D01* +X127707968Y-80808758D01* +X128447188Y-81547978D01* +X128461132Y-81555592D01* +X128462965Y-81555461D01* +X128469580Y-81551210D01* +X129213389Y-80807401D01* +X129220410Y-80794544D01* +X129213611Y-80785213D01* +X129209554Y-80782518D01* +X129023117Y-80679599D01* +X129013705Y-80675369D01* +X128812959Y-80604280D01* +X128802989Y-80601646D01* +X128593327Y-80564301D01* +X128583073Y-80563331D01* +X128370116Y-80560728D01* +X128359832Y-80561448D01* +X128149321Y-80593661D01* +X128139293Y-80596050D01* +X127936868Y-80662212D01* +X127927359Y-80666209D01* +X127738466Y-80764540D01* +X127729734Y-80770039D01* +X127709677Y-80785099D01* +X127701223Y-80796427D01* +X125728500Y-80796427D01* +X125728500Y-80324594D01* +X125748502Y-80256473D01* +X125765405Y-80235499D01* +X125955499Y-80045405D01* +X126017811Y-80011379D01* +X126044594Y-80008500D01* +X129860406Y-80008500D01* +X129928527Y-80028502D01* +G37* +%TD.AperFunction*% +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Fab.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Fab.gbr new file mode 100644 index 0000000..2ee5494 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Fab.gbr @@ -0,0 +1,5758 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,AssemblyDrawing,Bot*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12C,0.150000*% +%ADD13C,0.080000*% +%ADD14C,0.060000*% +%ADD15C,0.075000*% +%ADD16C,0.100000*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.C,D1*% +X140647380Y-95945952D02* +X139647380Y-95945952D01* +X139647380Y-96326904D01* +X139695000Y-96422142D01* +X139742619Y-96469761D01* +X139837857Y-96517380D01* +X139980714Y-96517380D01* +X140075952Y-96469761D01* +X140123571Y-96422142D01* +X140171190Y-96326904D01* +X140171190Y-95945952D01* +X140647380Y-96945952D02* +X139647380Y-96945952D01* +X140361666Y-97279285D01* +X139647380Y-97612619D01* +X140647380Y-97612619D01* +X140123571Y-98088809D02* +X140123571Y-98422142D01* +X140647380Y-98565000D02* +X140647380Y-98088809D01* +X139647380Y-98088809D01* +X139647380Y-98565000D01* +X139695000Y-99517380D02* +X139647380Y-99422142D01* +X139647380Y-99279285D01* +X139695000Y-99136428D01* +X139790238Y-99041190D01* +X139885476Y-98993571D01* +X140075952Y-98945952D01* +X140218809Y-98945952D01* +X140409285Y-98993571D01* +X140504523Y-99041190D01* +X140599761Y-99136428D01* +X140647380Y-99279285D01* +X140647380Y-99374523D01* +X140599761Y-99517380D01* +X140552142Y-99565000D01* +X140218809Y-99565000D01* +X140218809Y-99374523D01* +X139742619Y-99945952D02* +X139695000Y-99993571D01* +X139647380Y-100088809D01* +X139647380Y-100326904D01* +X139695000Y-100422142D01* +X139742619Y-100469761D01* +X139837857Y-100517380D01* +X139933095Y-100517380D01* +X140075952Y-100469761D01* +X140647380Y-99898333D01* +X140647380Y-100517380D01* +X139647380Y-101136428D02* +X139647380Y-101231666D01* +X139695000Y-101326904D01* +X139742619Y-101374523D01* +X139837857Y-101422142D01* +X140028333Y-101469761D01* +X140266428Y-101469761D01* +X140456904Y-101422142D01* +X140552142Y-101374523D01* +X140599761Y-101326904D01* +X140647380Y-101231666D01* +X140647380Y-101136428D01* +X140599761Y-101041190D01* +X140552142Y-100993571D01* +X140456904Y-100945952D01* +X140266428Y-100898333D01* +X140028333Y-100898333D01* +X139837857Y-100945952D01* +X139742619Y-100993571D01* +X139695000Y-101041190D01* +X139647380Y-101136428D01* +X139742619Y-101850714D02* +X139695000Y-101898333D01* +X139647380Y-101993571D01* +X139647380Y-102231666D01* +X139695000Y-102326904D01* +X139742619Y-102374523D01* +X139837857Y-102422142D01* +X139933095Y-102422142D01* +X140075952Y-102374523D01* +X140647380Y-101803095D01* +X140647380Y-102422142D01* +X139647380Y-103041190D02* +X139647380Y-103136428D01* +X139695000Y-103231666D01* +X139742619Y-103279285D01* +X139837857Y-103326904D01* +X140028333Y-103374523D01* +X140266428Y-103374523D01* +X140456904Y-103326904D01* +X140552142Y-103279285D01* +X140599761Y-103231666D01* +X140647380Y-103136428D01* +X140647380Y-103041190D01* +X140599761Y-102945952D01* +X140552142Y-102898333D01* +X140456904Y-102850714D01* +X140266428Y-102803095D01* +X140028333Y-102803095D01* +X139837857Y-102850714D01* +X139742619Y-102898333D01* +X139695000Y-102945952D01* +X139647380Y-103041190D01* +X140552142Y-104374523D02* +X140599761Y-104326904D01* +X140647380Y-104184047D01* +X140647380Y-104088809D01* +X140599761Y-103945952D01* +X140504523Y-103850714D01* +X140409285Y-103803095D01* +X140218809Y-103755476D01* +X140075952Y-103755476D01* +X139885476Y-103803095D01* +X139790238Y-103850714D01* +X139695000Y-103945952D01* +X139647380Y-104088809D01* +X139647380Y-104184047D01* +X139695000Y-104326904D01* +X139742619Y-104374523D01* +X140647380Y-104803095D02* +X139647380Y-104803095D01* +X139647380Y-105184047D01* +X139695000Y-105279285D01* +X139742619Y-105326904D01* +X139837857Y-105374523D01* +X139980714Y-105374523D01* +X140075952Y-105326904D01* +X140123571Y-105279285D01* +X140171190Y-105184047D01* +X140171190Y-104803095D01* +X140361666Y-105755476D02* +X140361666Y-106231666D01* +X140647380Y-105660238D02* +X139647380Y-105993571D01* +X140647380Y-106326904D01* +X135947380Y-100826904D02* +X134947380Y-100826904D01* +X134947380Y-101065000D01* +X134995000Y-101207857D01* +X135090238Y-101303095D01* +X135185476Y-101350714D01* +X135375952Y-101398333D01* +X135518809Y-101398333D01* +X135709285Y-101350714D01* +X135804523Y-101303095D01* +X135899761Y-101207857D01* +X135947380Y-101065000D01* +X135947380Y-100826904D01* +X135947380Y-102350714D02* +X135947380Y-101779285D01* +X135947380Y-102065000D02* +X134947380Y-102065000D01* +X135090238Y-101969761D01* +X135185476Y-101874523D01* +X135233095Y-101779285D01* +%TO.C,C17*% +X154982380Y-104497380D02* +X154982380Y-103925952D01* +X154982380Y-104211666D02* +X153982380Y-104211666D01* +X154125238Y-104116428D01* +X154220476Y-104021190D01* +X154268095Y-103925952D01* +X153982380Y-105116428D02* +X153982380Y-105211666D01* +X154030000Y-105306904D01* +X154077619Y-105354523D01* +X154172857Y-105402142D01* +X154363333Y-105449761D01* +X154601428Y-105449761D01* +X154791904Y-105402142D01* +X154887142Y-105354523D01* +X154934761Y-105306904D01* +X154982380Y-105211666D01* +X154982380Y-105116428D01* +X154934761Y-105021190D01* +X154887142Y-104973571D01* +X154791904Y-104925952D01* +X154601428Y-104878333D01* +X154363333Y-104878333D01* +X154172857Y-104925952D01* +X154077619Y-104973571D01* +X154030000Y-105021190D01* +X153982380Y-105116428D01* +X153982380Y-106068809D02* +X153982380Y-106164047D01* +X154030000Y-106259285D01* +X154077619Y-106306904D01* +X154172857Y-106354523D01* +X154363333Y-106402142D01* +X154601428Y-106402142D01* +X154791904Y-106354523D01* +X154887142Y-106306904D01* +X154934761Y-106259285D01* +X154982380Y-106164047D01* +X154982380Y-106068809D01* +X154934761Y-105973571D01* +X154887142Y-105925952D01* +X154791904Y-105878333D01* +X154601428Y-105830714D01* +X154363333Y-105830714D01* +X154172857Y-105878333D01* +X154077619Y-105925952D01* +X154030000Y-105973571D01* +X153982380Y-106068809D01* +X154315714Y-106830714D02* +X154982380Y-106830714D01* +X154410952Y-106830714D02* +X154363333Y-106878333D01* +X154315714Y-106973571D01* +X154315714Y-107116428D01* +X154363333Y-107211666D01* +X154458571Y-107259285D01* +X154982380Y-107259285D01* +X154458571Y-108068809D02* +X154458571Y-107735476D01* +X154982380Y-107735476D02* +X153982380Y-107735476D01* +X153982380Y-108211666D01* +D13* +X156388571Y-105723571D02* +X156412380Y-105699761D01* +X156436190Y-105628333D01* +X156436190Y-105580714D01* +X156412380Y-105509285D01* +X156364761Y-105461666D01* +X156317142Y-105437857D01* +X156221904Y-105414047D01* +X156150476Y-105414047D01* +X156055238Y-105437857D01* +X156007619Y-105461666D01* +X155960000Y-105509285D01* +X155936190Y-105580714D01* +X155936190Y-105628333D01* +X155960000Y-105699761D01* +X155983809Y-105723571D01* +X156436190Y-106199761D02* +X156436190Y-105914047D01* +X156436190Y-106056904D02* +X155936190Y-106056904D01* +X156007619Y-106009285D01* +X156055238Y-105961666D01* +X156079047Y-105914047D01* +X155936190Y-106366428D02* +X155936190Y-106699761D01* +X156436190Y-106485476D01* +D12* +%TO.C,R10*% +X176775809Y-78802380D02* +X176156761Y-78802380D01* +X176490095Y-79183333D01* +X176347238Y-79183333D01* +X176252000Y-79230952D01* +X176204380Y-79278571D01* +X176156761Y-79373809D01* +X176156761Y-79611904D01* +X176204380Y-79707142D01* +X176252000Y-79754761D01* +X176347238Y-79802380D01* +X176632952Y-79802380D01* +X176728190Y-79754761D01* +X176775809Y-79707142D01* +X175728190Y-79707142D02* +X175680571Y-79754761D01* +X175728190Y-79802380D01* +X175775809Y-79754761D01* +X175728190Y-79707142D01* +X175728190Y-79802380D01* +X175347238Y-78802380D02* +X174680571Y-78802380D01* +X175109142Y-79802380D01* +X174347238Y-78897619D02* +X174299619Y-78850000D01* +X174204380Y-78802380D01* +X173966285Y-78802380D01* +X173871047Y-78850000D01* +X173823428Y-78897619D01* +X173775809Y-78992857D01* +X173775809Y-79088095D01* +X173823428Y-79230952D01* +X174394857Y-79802380D01* +X173775809Y-79802380D01* +X173347238Y-79802380D02* +X173347238Y-78802380D01* +X172775809Y-79802380D02* +X173204380Y-79230952D01* +X172775809Y-78802380D02* +X173347238Y-79373809D01* +D13* +X175073428Y-81226190D02* +X175240095Y-80988095D01* +X175359142Y-81226190D02* +X175359142Y-80726190D01* +X175168666Y-80726190D01* +X175121047Y-80750000D01* +X175097238Y-80773809D01* +X175073428Y-80821428D01* +X175073428Y-80892857D01* +X175097238Y-80940476D01* +X175121047Y-80964285D01* +X175168666Y-80988095D01* +X175359142Y-80988095D01* +X174597238Y-81226190D02* +X174882952Y-81226190D01* +X174740095Y-81226190D02* +X174740095Y-80726190D01* +X174787714Y-80797619D01* +X174835333Y-80845238D01* +X174882952Y-80869047D01* +X174287714Y-80726190D02* +X174240095Y-80726190D01* +X174192476Y-80750000D01* +X174168666Y-80773809D01* +X174144857Y-80821428D01* +X174121047Y-80916666D01* +X174121047Y-81035714D01* +X174144857Y-81130952D01* +X174168666Y-81178571D01* +X174192476Y-81202380D01* +X174240095Y-81226190D01* +X174287714Y-81226190D01* +X174335333Y-81202380D01* +X174359142Y-81178571D01* +X174382952Y-81130952D01* +X174406761Y-81035714D01* +X174406761Y-80916666D01* +X174382952Y-80821428D01* +X174359142Y-80773809D01* +X174335333Y-80750000D01* +X174287714Y-80726190D01* +D12* +%TO.C,U2*% +X156280714Y-107584761D02* +X156137857Y-107632380D01* +X155899761Y-107632380D01* +X155804523Y-107584761D01* +X155756904Y-107537142D01* +X155709285Y-107441904D01* +X155709285Y-107346666D01* +X155756904Y-107251428D01* +X155804523Y-107203809D01* +X155899761Y-107156190D01* +X156090238Y-107108571D01* +X156185476Y-107060952D01* +X156233095Y-107013333D01* +X156280714Y-106918095D01* +X156280714Y-106822857D01* +X156233095Y-106727619D01* +X156185476Y-106680000D01* +X156090238Y-106632380D01* +X155852142Y-106632380D01* +X155709285Y-106680000D01* +X155423571Y-106632380D02* +X154852142Y-106632380D01* +X155137857Y-107632380D02* +X155137857Y-106632380D01* +X154518809Y-107632380D02* +X154518809Y-106632380D01* +X154185476Y-107346666D01* +X153852142Y-106632380D01* +X153852142Y-107632380D01* +X153471190Y-106632380D02* +X152852142Y-106632380D01* +X153185476Y-107013333D01* +X153042619Y-107013333D01* +X152947380Y-107060952D01* +X152899761Y-107108571D01* +X152852142Y-107203809D01* +X152852142Y-107441904D01* +X152899761Y-107537142D01* +X152947380Y-107584761D01* +X153042619Y-107632380D01* +X153328333Y-107632380D01* +X153423571Y-107584761D01* +X153471190Y-107537142D01* +X152471190Y-106727619D02* +X152423571Y-106680000D01* +X152328333Y-106632380D01* +X152090238Y-106632380D01* +X151995000Y-106680000D01* +X151947380Y-106727619D01* +X151899761Y-106822857D01* +X151899761Y-106918095D01* +X151947380Y-107060952D01* +X152518809Y-107632380D01* +X151899761Y-107632380D01* +X150995000Y-107632380D02* +X151471190Y-107632380D01* +X151471190Y-106632380D01* +X150471190Y-106632380D02* +X150375952Y-106632380D01* +X150280714Y-106680000D01* +X150233095Y-106727619D01* +X150185476Y-106822857D01* +X150137857Y-107013333D01* +X150137857Y-107251428D01* +X150185476Y-107441904D01* +X150233095Y-107537142D01* +X150280714Y-107584761D01* +X150375952Y-107632380D01* +X150471190Y-107632380D01* +X150566428Y-107584761D01* +X150614047Y-107537142D01* +X150661666Y-107441904D01* +X150709285Y-107251428D01* +X150709285Y-107013333D01* +X150661666Y-106822857D01* +X150614047Y-106727619D01* +X150566428Y-106680000D01* +X150471190Y-106632380D01* +X149185476Y-107632380D02* +X149756904Y-107632380D01* +X149471190Y-107632380D02* +X149471190Y-106632380D01* +X149566428Y-106775238D01* +X149661666Y-106870476D01* +X149756904Y-106918095D01* +X148566428Y-106632380D02* +X148471190Y-106632380D01* +X148375952Y-106680000D01* +X148328333Y-106727619D01* +X148280714Y-106822857D01* +X148233095Y-107013333D01* +X148233095Y-107251428D01* +X148280714Y-107441904D01* +X148328333Y-107537142D01* +X148375952Y-107584761D01* +X148471190Y-107632380D01* +X148566428Y-107632380D01* +X148661666Y-107584761D01* +X148709285Y-107537142D01* +X148756904Y-107441904D01* +X148804523Y-107251428D01* +X148804523Y-107013333D01* +X148756904Y-106822857D01* +X148709285Y-106727619D01* +X148661666Y-106680000D01* +X148566428Y-106632380D01* +X147233095Y-107537142D02* +X147280714Y-107584761D01* +X147423571Y-107632380D01* +X147518809Y-107632380D01* +X147661666Y-107584761D01* +X147756904Y-107489523D01* +X147804523Y-107394285D01* +X147852142Y-107203809D01* +X147852142Y-107060952D01* +X147804523Y-106870476D01* +X147756904Y-106775238D01* +X147661666Y-106680000D01* +X147518809Y-106632380D01* +X147423571Y-106632380D01* +X147280714Y-106680000D01* +X147233095Y-106727619D01* +X146375952Y-106632380D02* +X146566428Y-106632380D01* +X146661666Y-106680000D01* +X146709285Y-106727619D01* +X146804523Y-106870476D01* +X146852142Y-107060952D01* +X146852142Y-107441904D01* +X146804523Y-107537142D01* +X146756904Y-107584761D01* +X146661666Y-107632380D01* +X146471190Y-107632380D01* +X146375952Y-107584761D01* +X146328333Y-107537142D01* +X146280714Y-107441904D01* +X146280714Y-107203809D01* +X146328333Y-107108571D01* +X146375952Y-107060952D01* +X146471190Y-107013333D01* +X146661666Y-107013333D01* +X146756904Y-107060952D01* +X146804523Y-107108571D01* +X146852142Y-107203809D01* +X145995000Y-106632380D02* +X145423571Y-106632380D01* +X145709285Y-107632380D02* +X145709285Y-106632380D01* +X145185476Y-107632380D02* +X144661666Y-106965714D01* +X145185476Y-106965714D02* +X144661666Y-107632380D01* +X151256904Y-112482380D02* +X151256904Y-113291904D01* +X151209285Y-113387142D01* +X151161666Y-113434761D01* +X151066428Y-113482380D01* +X150875952Y-113482380D01* +X150780714Y-113434761D01* +X150733095Y-113387142D01* +X150685476Y-113291904D01* +X150685476Y-112482380D01* +X150256904Y-112577619D02* +X150209285Y-112530000D01* +X150114047Y-112482380D01* +X149875952Y-112482380D01* +X149780714Y-112530000D01* +X149733095Y-112577619D01* +X149685476Y-112672857D01* +X149685476Y-112768095D01* +X149733095Y-112910952D01* +X150304523Y-113482380D01* +X149685476Y-113482380D01* +%TO.C,C4*% +X183557380Y-114498571D02* +X183557380Y-113927142D01* +X183557380Y-114212857D02* +X182557380Y-114212857D01* +X182700238Y-114117619D01* +X182795476Y-114022380D01* +X182843095Y-113927142D01* +X182557380Y-115117619D02* +X182557380Y-115212857D01* +X182605000Y-115308095D01* +X182652619Y-115355714D01* +X182747857Y-115403333D01* +X182938333Y-115450952D01* +X183176428Y-115450952D01* +X183366904Y-115403333D01* +X183462142Y-115355714D01* +X183509761Y-115308095D01* +X183557380Y-115212857D01* +X183557380Y-115117619D01* +X183509761Y-115022380D01* +X183462142Y-114974761D01* +X183366904Y-114927142D01* +X183176428Y-114879523D01* +X182938333Y-114879523D01* +X182747857Y-114927142D01* +X182652619Y-114974761D01* +X182605000Y-115022380D01* +X182557380Y-115117619D01* +X182890714Y-115879523D02* +X183557380Y-115879523D01* +X182985952Y-115879523D02* +X182938333Y-115927142D01* +X182890714Y-116022380D01* +X182890714Y-116165238D01* +X182938333Y-116260476D01* +X183033571Y-116308095D01* +X183557380Y-116308095D01* +X183033571Y-117117619D02* +X183033571Y-116784285D01* +X183557380Y-116784285D02* +X182557380Y-116784285D01* +X182557380Y-117260476D01* +D13* +X184963571Y-115486666D02* +X184987380Y-115462857D01* +X185011190Y-115391428D01* +X185011190Y-115343809D01* +X184987380Y-115272380D01* +X184939761Y-115224761D01* +X184892142Y-115200952D01* +X184796904Y-115177142D01* +X184725476Y-115177142D01* +X184630238Y-115200952D01* +X184582619Y-115224761D01* +X184535000Y-115272380D01* +X184511190Y-115343809D01* +X184511190Y-115391428D01* +X184535000Y-115462857D01* +X184558809Y-115486666D01* +X184677857Y-115915238D02* +X185011190Y-115915238D01* +X184487380Y-115796190D02* +X184844523Y-115677142D01* +X184844523Y-115986666D01* +D12* +%TO.C,R7*% +X174839285Y-115132380D02* +X175410714Y-115132380D01* +X175125000Y-115132380D02* +X175125000Y-114132380D01* +X175220238Y-114275238D01* +X175315476Y-114370476D01* +X175410714Y-114418095D01* +X174410714Y-115132380D02* +X174410714Y-114132380D01* +X173839285Y-115132380D02* +X174267857Y-114560952D01* +X173839285Y-114132380D02* +X174410714Y-114703809D01* +D13* +X174708333Y-113256190D02* +X174875000Y-113018095D01* +X174994047Y-113256190D02* +X174994047Y-112756190D01* +X174803571Y-112756190D01* +X174755952Y-112780000D01* +X174732142Y-112803809D01* +X174708333Y-112851428D01* +X174708333Y-112922857D01* +X174732142Y-112970476D01* +X174755952Y-112994285D01* +X174803571Y-113018095D01* +X174994047Y-113018095D01* +X174541666Y-112756190D02* +X174208333Y-112756190D01* +X174422619Y-113256190D01* +D12* +%TO.C,C20*% +X143737380Y-110212380D02* +X143737380Y-109640952D01* +X143737380Y-109926666D02* +X142737380Y-109926666D01* +X142880238Y-109831428D01* +X142975476Y-109736190D01* +X143023095Y-109640952D01* +X142737380Y-110831428D02* +X142737380Y-110926666D01* +X142785000Y-111021904D01* +X142832619Y-111069523D01* +X142927857Y-111117142D01* +X143118333Y-111164761D01* +X143356428Y-111164761D01* +X143546904Y-111117142D01* +X143642142Y-111069523D01* +X143689761Y-111021904D01* +X143737380Y-110926666D01* +X143737380Y-110831428D01* +X143689761Y-110736190D01* +X143642142Y-110688571D01* +X143546904Y-110640952D01* +X143356428Y-110593333D01* +X143118333Y-110593333D01* +X142927857Y-110640952D01* +X142832619Y-110688571D01* +X142785000Y-110736190D01* +X142737380Y-110831428D01* +X142737380Y-111783809D02* +X142737380Y-111879047D01* +X142785000Y-111974285D01* +X142832619Y-112021904D01* +X142927857Y-112069523D01* +X143118333Y-112117142D01* +X143356428Y-112117142D01* +X143546904Y-112069523D01* +X143642142Y-112021904D01* +X143689761Y-111974285D01* +X143737380Y-111879047D01* +X143737380Y-111783809D01* +X143689761Y-111688571D01* +X143642142Y-111640952D01* +X143546904Y-111593333D01* +X143356428Y-111545714D01* +X143118333Y-111545714D01* +X142927857Y-111593333D01* +X142832619Y-111640952D01* +X142785000Y-111688571D01* +X142737380Y-111783809D01* +X143070714Y-112545714D02* +X143737380Y-112545714D01* +X143165952Y-112545714D02* +X143118333Y-112593333D01* +X143070714Y-112688571D01* +X143070714Y-112831428D01* +X143118333Y-112926666D01* +X143213571Y-112974285D01* +X143737380Y-112974285D01* +X143213571Y-113783809D02* +X143213571Y-113450476D01* +X143737380Y-113450476D02* +X142737380Y-113450476D01* +X142737380Y-113926666D01* +D13* +X141783571Y-111438571D02* +X141807380Y-111414761D01* +X141831190Y-111343333D01* +X141831190Y-111295714D01* +X141807380Y-111224285D01* +X141759761Y-111176666D01* +X141712142Y-111152857D01* +X141616904Y-111129047D01* +X141545476Y-111129047D01* +X141450238Y-111152857D01* +X141402619Y-111176666D01* +X141355000Y-111224285D01* +X141331190Y-111295714D01* +X141331190Y-111343333D01* +X141355000Y-111414761D01* +X141378809Y-111438571D01* +X141378809Y-111629047D02* +X141355000Y-111652857D01* +X141331190Y-111700476D01* +X141331190Y-111819523D01* +X141355000Y-111867142D01* +X141378809Y-111890952D01* +X141426428Y-111914761D01* +X141474047Y-111914761D01* +X141545476Y-111890952D01* +X141831190Y-111605238D01* +X141831190Y-111914761D01* +X141331190Y-112224285D02* +X141331190Y-112271904D01* +X141355000Y-112319523D01* +X141378809Y-112343333D01* +X141426428Y-112367142D01* +X141521666Y-112390952D01* +X141640714Y-112390952D01* +X141735952Y-112367142D01* +X141783571Y-112343333D01* +X141807380Y-112319523D01* +X141831190Y-112271904D01* +X141831190Y-112224285D01* +X141807380Y-112176666D01* +X141783571Y-112152857D01* +X141735952Y-112129047D01* +X141640714Y-112105238D01* +X141521666Y-112105238D01* +X141426428Y-112129047D01* +X141378809Y-112152857D01* +X141355000Y-112176666D01* +X141331190Y-112224285D01* +D12* +%TO.C,R17*% +X170711666Y-125292380D02* +X171283095Y-125292380D01* +X170997380Y-125292380D02* +X170997380Y-124292380D01* +X171092619Y-124435238D01* +X171187857Y-124530476D01* +X171283095Y-124578095D01* +X169806904Y-124292380D02* +X170283095Y-124292380D01* +X170330714Y-124768571D01* +X170283095Y-124720952D01* +X170187857Y-124673333D01* +X169949761Y-124673333D01* +X169854523Y-124720952D01* +X169806904Y-124768571D01* +X169759285Y-124863809D01* +X169759285Y-125101904D01* +X169806904Y-125197142D01* +X169854523Y-125244761D01* +X169949761Y-125292380D01* +X170187857Y-125292380D01* +X170283095Y-125244761D01* +X170330714Y-125197142D01* +X169140238Y-124292380D02* +X169045000Y-124292380D01* +X168949761Y-124340000D01* +X168902142Y-124387619D01* +X168854523Y-124482857D01* +X168806904Y-124673333D01* +X168806904Y-124911428D01* +X168854523Y-125101904D01* +X168902142Y-125197142D01* +X168949761Y-125244761D01* +X169045000Y-125292380D01* +X169140238Y-125292380D01* +X169235476Y-125244761D01* +X169283095Y-125197142D01* +X169330714Y-125101904D01* +X169378333Y-124911428D01* +X169378333Y-124673333D01* +X169330714Y-124482857D01* +X169283095Y-124387619D01* +X169235476Y-124340000D01* +X169140238Y-124292380D01* +X168378333Y-125292380D02* +X168378333Y-124292380D01* +X167806904Y-125292380D02* +X168235476Y-124720952D01* +X167806904Y-124292380D02* +X168378333Y-124863809D01* +D13* +X169866428Y-123416190D02* +X170033095Y-123178095D01* +X170152142Y-123416190D02* +X170152142Y-122916190D01* +X169961666Y-122916190D01* +X169914047Y-122940000D01* +X169890238Y-122963809D01* +X169866428Y-123011428D01* +X169866428Y-123082857D01* +X169890238Y-123130476D01* +X169914047Y-123154285D01* +X169961666Y-123178095D01* +X170152142Y-123178095D01* +X169390238Y-123416190D02* +X169675952Y-123416190D01* +X169533095Y-123416190D02* +X169533095Y-122916190D01* +X169580714Y-122987619D01* +X169628333Y-123035238D01* +X169675952Y-123059047D01* +X169223571Y-122916190D02* +X168890238Y-122916190D01* +X169104523Y-123416190D01* +D12* +%TO.C,C6*% +X174341666Y-101007380D02* +X174913095Y-101007380D01* +X174627380Y-101007380D02* +X174627380Y-100007380D01* +X174722619Y-100150238D01* +X174817857Y-100245476D01* +X174913095Y-100293095D01* +X173913095Y-100340714D02* +X173913095Y-101340714D01* +X173436904Y-100864523D02* +X173389285Y-100959761D01* +X173294047Y-101007380D01* +X173913095Y-100864523D02* +X173865476Y-100959761D01* +X173770238Y-101007380D01* +X173579761Y-101007380D01* +X173484523Y-100959761D01* +X173436904Y-100864523D01* +X173436904Y-100340714D01* +X172532142Y-100483571D02* +X172865476Y-100483571D01* +X172865476Y-101007380D02* +X172865476Y-100007380D01* +X172389285Y-100007380D01* +D13* +X173758333Y-102413571D02* +X173782142Y-102437380D01* +X173853571Y-102461190D01* +X173901190Y-102461190D01* +X173972619Y-102437380D01* +X174020238Y-102389761D01* +X174044047Y-102342142D01* +X174067857Y-102246904D01* +X174067857Y-102175476D01* +X174044047Y-102080238D01* +X174020238Y-102032619D01* +X173972619Y-101985000D01* +X173901190Y-101961190D01* +X173853571Y-101961190D01* +X173782142Y-101985000D01* +X173758333Y-102008809D01* +X173329761Y-101961190D02* +X173425000Y-101961190D01* +X173472619Y-101985000D01* +X173496428Y-102008809D01* +X173544047Y-102080238D01* +X173567857Y-102175476D01* +X173567857Y-102365952D01* +X173544047Y-102413571D01* +X173520238Y-102437380D01* +X173472619Y-102461190D01* +X173377380Y-102461190D01* +X173329761Y-102437380D01* +X173305952Y-102413571D01* +X173282142Y-102365952D01* +X173282142Y-102246904D01* +X173305952Y-102199285D01* +X173329761Y-102175476D01* +X173377380Y-102151666D01* +X173472619Y-102151666D01* +X173520238Y-102175476D01* +X173544047Y-102199285D01* +X173567857Y-102246904D01* +D12* +%TO.C,R3*% +X176466785Y-121357380D02* +X177038214Y-121357380D01* +X176752500Y-121357380D02* +X176752500Y-120357380D01* +X176847738Y-120500238D01* +X176942976Y-120595476D01* +X177038214Y-120643095D01* +X176038214Y-121357380D02* +X176038214Y-120357380D01* +X175466785Y-121357380D02* +X175895357Y-120785952D01* +X175466785Y-120357380D02* +X176038214Y-120928809D01* +D13* +X176335833Y-122781190D02* +X176502500Y-122543095D01* +X176621547Y-122781190D02* +X176621547Y-122281190D01* +X176431071Y-122281190D01* +X176383452Y-122305000D01* +X176359642Y-122328809D01* +X176335833Y-122376428D01* +X176335833Y-122447857D01* +X176359642Y-122495476D01* +X176383452Y-122519285D01* +X176431071Y-122543095D01* +X176621547Y-122543095D01* +X176169166Y-122281190D02* +X175859642Y-122281190D01* +X176026309Y-122471666D01* +X175954880Y-122471666D01* +X175907261Y-122495476D01* +X175883452Y-122519285D01* +X175859642Y-122566904D01* +X175859642Y-122685952D01* +X175883452Y-122733571D01* +X175907261Y-122757380D01* +X175954880Y-122781190D01* +X176097738Y-122781190D01* +X176145357Y-122757380D01* +X176169166Y-122733571D01* +D12* +%TO.C,C19*% +X146912380Y-118152380D02* +X146912380Y-117580952D01* +X146912380Y-117866666D02* +X145912380Y-117866666D01* +X146055238Y-117771428D01* +X146150476Y-117676190D01* +X146198095Y-117580952D01* +X145912380Y-118771428D02* +X145912380Y-118866666D01* +X145960000Y-118961904D01* +X146007619Y-119009523D01* +X146102857Y-119057142D01* +X146293333Y-119104761D01* +X146531428Y-119104761D01* +X146721904Y-119057142D01* +X146817142Y-119009523D01* +X146864761Y-118961904D01* +X146912380Y-118866666D01* +X146912380Y-118771428D01* +X146864761Y-118676190D01* +X146817142Y-118628571D01* +X146721904Y-118580952D01* +X146531428Y-118533333D01* +X146293333Y-118533333D01* +X146102857Y-118580952D01* +X146007619Y-118628571D01* +X145960000Y-118676190D01* +X145912380Y-118771428D01* +X145912380Y-119723809D02* +X145912380Y-119819047D01* +X145960000Y-119914285D01* +X146007619Y-119961904D01* +X146102857Y-120009523D01* +X146293333Y-120057142D01* +X146531428Y-120057142D01* +X146721904Y-120009523D01* +X146817142Y-119961904D01* +X146864761Y-119914285D01* +X146912380Y-119819047D01* +X146912380Y-119723809D01* +X146864761Y-119628571D01* +X146817142Y-119580952D01* +X146721904Y-119533333D01* +X146531428Y-119485714D01* +X146293333Y-119485714D01* +X146102857Y-119533333D01* +X146007619Y-119580952D01* +X145960000Y-119628571D01* +X145912380Y-119723809D01* +X146245714Y-120485714D02* +X146912380Y-120485714D01* +X146340952Y-120485714D02* +X146293333Y-120533333D01* +X146245714Y-120628571D01* +X146245714Y-120771428D01* +X146293333Y-120866666D01* +X146388571Y-120914285D01* +X146912380Y-120914285D01* +X146388571Y-121723809D02* +X146388571Y-121390476D01* +X146912380Y-121390476D02* +X145912380Y-121390476D01* +X145912380Y-121866666D01* +D13* +X144958571Y-119378571D02* +X144982380Y-119354761D01* +X145006190Y-119283333D01* +X145006190Y-119235714D01* +X144982380Y-119164285D01* +X144934761Y-119116666D01* +X144887142Y-119092857D01* +X144791904Y-119069047D01* +X144720476Y-119069047D01* +X144625238Y-119092857D01* +X144577619Y-119116666D01* +X144530000Y-119164285D01* +X144506190Y-119235714D01* +X144506190Y-119283333D01* +X144530000Y-119354761D01* +X144553809Y-119378571D01* +X145006190Y-119854761D02* +X145006190Y-119569047D01* +X145006190Y-119711904D02* +X144506190Y-119711904D01* +X144577619Y-119664285D01* +X144625238Y-119616666D01* +X144649047Y-119569047D01* +X145006190Y-120092857D02* +X145006190Y-120188095D01* +X144982380Y-120235714D01* +X144958571Y-120259523D01* +X144887142Y-120307142D01* +X144791904Y-120330952D01* +X144601428Y-120330952D01* +X144553809Y-120307142D01* +X144530000Y-120283333D01* +X144506190Y-120235714D01* +X144506190Y-120140476D01* +X144530000Y-120092857D01* +X144553809Y-120069047D01* +X144601428Y-120045238D01* +X144720476Y-120045238D01* +X144768095Y-120069047D01* +X144791904Y-120092857D01* +X144815714Y-120140476D01* +X144815714Y-120235714D01* +X144791904Y-120283333D01* +X144768095Y-120307142D01* +X144720476Y-120330952D01* +D12* +%TO.C,U3*% +X121681428Y-99652380D02* +X122157619Y-99652380D01* +X122157619Y-98652380D01* +X121490952Y-98652380D02* +X120919523Y-98652380D01* +X121205238Y-99652380D02* +X121205238Y-98652380D01* +X120014761Y-99557142D02* +X120062380Y-99604761D01* +X120205238Y-99652380D01* +X120300476Y-99652380D01* +X120443333Y-99604761D01* +X120538571Y-99509523D01* +X120586190Y-99414285D01* +X120633809Y-99223809D01* +X120633809Y-99080952D01* +X120586190Y-98890476D01* +X120538571Y-98795238D01* +X120443333Y-98700000D01* +X120300476Y-98652380D01* +X120205238Y-98652380D01* +X120062380Y-98700000D01* +X120014761Y-98747619D01* +X119633809Y-98747619D02* +X119586190Y-98700000D01* +X119490952Y-98652380D01* +X119252857Y-98652380D01* +X119157619Y-98700000D01* +X119110000Y-98747619D01* +X119062380Y-98842857D01* +X119062380Y-98938095D01* +X119110000Y-99080952D01* +X119681428Y-99652380D01* +X119062380Y-99652380D01* +X118586190Y-99652380D02* +X118395714Y-99652380D01* +X118300476Y-99604761D01* +X118252857Y-99557142D01* +X118157619Y-99414285D01* +X118110000Y-99223809D01* +X118110000Y-98842857D01* +X118157619Y-98747619D01* +X118205238Y-98700000D01* +X118300476Y-98652380D01* +X118490952Y-98652380D01* +X118586190Y-98700000D01* +X118633809Y-98747619D01* +X118681428Y-98842857D01* +X118681428Y-99080952D01* +X118633809Y-99176190D01* +X118586190Y-99223809D01* +X118490952Y-99271428D01* +X118300476Y-99271428D01* +X118205238Y-99223809D01* +X118157619Y-99176190D01* +X118110000Y-99080952D01* +X117205238Y-98652380D02* +X117681428Y-98652380D01* +X117729047Y-99128571D01* +X117681428Y-99080952D01* +X117586190Y-99033333D01* +X117348095Y-99033333D01* +X117252857Y-99080952D01* +X117205238Y-99128571D01* +X117157619Y-99223809D01* +X117157619Y-99461904D01* +X117205238Y-99557142D01* +X117252857Y-99604761D01* +X117348095Y-99652380D01* +X117586190Y-99652380D01* +X117681428Y-99604761D01* +X117729047Y-99557142D01* +X116300476Y-98985714D02* +X116300476Y-99652380D01* +X116538571Y-98604761D02* +X116776666Y-99319047D01* +X116157619Y-99319047D01* +X115776666Y-99271428D02* +X115014761Y-99271428D01* +X114586190Y-98747619D02* +X114538571Y-98700000D01* +X114443333Y-98652380D01* +X114205238Y-98652380D01* +X114110000Y-98700000D01* +X114062380Y-98747619D01* +X114014761Y-98842857D01* +X114014761Y-98938095D01* +X114062380Y-99080952D01* +X114633809Y-99652380D01* +X114014761Y-99652380D01* +D14* +X118414761Y-101380952D02* +X118414761Y-101704761D01* +X118395714Y-101742857D01* +X118376666Y-101761904D01* +X118338571Y-101780952D01* +X118262380Y-101780952D01* +X118224285Y-101761904D01* +X118205238Y-101742857D01* +X118186190Y-101704761D01* +X118186190Y-101380952D01* +X118033809Y-101380952D02* +X117786190Y-101380952D01* +X117919523Y-101533333D01* +X117862380Y-101533333D01* +X117824285Y-101552380D01* +X117805238Y-101571428D01* +X117786190Y-101609523D01* +X117786190Y-101704761D01* +X117805238Y-101742857D01* +X117824285Y-101761904D01* +X117862380Y-101780952D01* +X117976666Y-101780952D01* +X118014761Y-101761904D01* +X118033809Y-101742857D01* +D12* +%TO.C,Q2*% +X134730714Y-112172380D02* +X134730714Y-111172380D01* +X134349761Y-111172380D01* +X134254523Y-111220000D01* +X134206904Y-111267619D01* +X134159285Y-111362857D01* +X134159285Y-111505714D01* +X134206904Y-111600952D01* +X134254523Y-111648571D01* +X134349761Y-111696190D01* +X134730714Y-111696190D01* +X133730714Y-112172380D02* +X133730714Y-111172380D01* +X133397380Y-111886666D01* +X133064047Y-111172380D01* +X133064047Y-112172380D01* +X132587857Y-112172380D02* +X132587857Y-111172380D01* +X132016428Y-112172380D01* +X132016428Y-111172380D01* +X131064047Y-111172380D02* +X131540238Y-111172380D01* +X131587857Y-111648571D01* +X131540238Y-111600952D01* +X131445000Y-111553333D01* +X131206904Y-111553333D01* +X131111666Y-111600952D01* +X131064047Y-111648571D01* +X131016428Y-111743809D01* +X131016428Y-111981904D01* +X131064047Y-112077142D01* +X131111666Y-112124761D01* +X131206904Y-112172380D01* +X131445000Y-112172380D01* +X131540238Y-112124761D01* +X131587857Y-112077142D01* +X130635476Y-111267619D02* +X130587857Y-111220000D01* +X130492619Y-111172380D01* +X130254523Y-111172380D01* +X130159285Y-111220000D01* +X130111666Y-111267619D01* +X130064047Y-111362857D01* +X130064047Y-111458095D01* +X130111666Y-111600952D01* +X130683095Y-112172380D01* +X130064047Y-112172380D01* +X129730714Y-111172380D02* +X129064047Y-112172380D01* +X129064047Y-111172380D02* +X129730714Y-112172380D01* +X128683095Y-112172380D02* +X128683095Y-111172380D01* +X128302142Y-111172380D01* +X128206904Y-111220000D01* +X128159285Y-111267619D01* +X128111666Y-111362857D01* +X128111666Y-111505714D01* +X128159285Y-111600952D01* +X128206904Y-111648571D01* +X128302142Y-111696190D01* +X128683095Y-111696190D01* +D15* +X131718809Y-109172380D02* +X131695000Y-109124761D01* +X131647380Y-109077142D01* +X131575952Y-109005714D01* +X131552142Y-108958095D01* +X131552142Y-108910476D01* +X131671190Y-108934285D02* +X131647380Y-108886666D01* +X131599761Y-108839047D01* +X131504523Y-108815238D01* +X131337857Y-108815238D01* +X131242619Y-108839047D01* +X131195000Y-108886666D01* +X131171190Y-108934285D01* +X131171190Y-109029523D01* +X131195000Y-109077142D01* +X131242619Y-109124761D01* +X131337857Y-109148571D01* +X131504523Y-109148571D01* +X131599761Y-109124761D01* +X131647380Y-109077142D01* +X131671190Y-109029523D01* +X131671190Y-108934285D01* +X131218809Y-109339047D02* +X131195000Y-109362857D01* +X131171190Y-109410476D01* +X131171190Y-109529523D01* +X131195000Y-109577142D01* +X131218809Y-109600952D01* +X131266428Y-109624761D01* +X131314047Y-109624761D01* +X131385476Y-109600952D01* +X131671190Y-109315238D01* +X131671190Y-109624761D01* +D12* +%TO.C,R24*% +X132611666Y-111197380D02* +X133183095Y-111197380D01* +X132897380Y-111197380D02* +X132897380Y-110197380D01* +X132992619Y-110340238D01* +X133087857Y-110435476D01* +X133183095Y-110483095D01* +X131992619Y-110197380D02* +X131897380Y-110197380D01* +X131802142Y-110245000D01* +X131754523Y-110292619D01* +X131706904Y-110387857D01* +X131659285Y-110578333D01* +X131659285Y-110816428D01* +X131706904Y-111006904D01* +X131754523Y-111102142D01* +X131802142Y-111149761D01* +X131897380Y-111197380D01* +X131992619Y-111197380D01* +X132087857Y-111149761D01* +X132135476Y-111102142D01* +X132183095Y-111006904D01* +X132230714Y-110816428D01* +X132230714Y-110578333D01* +X132183095Y-110387857D01* +X132135476Y-110292619D01* +X132087857Y-110245000D01* +X131992619Y-110197380D01* +X131040238Y-110197380D02* +X130945000Y-110197380D01* +X130849761Y-110245000D01* +X130802142Y-110292619D01* +X130754523Y-110387857D01* +X130706904Y-110578333D01* +X130706904Y-110816428D01* +X130754523Y-111006904D01* +X130802142Y-111102142D01* +X130849761Y-111149761D01* +X130945000Y-111197380D01* +X131040238Y-111197380D01* +X131135476Y-111149761D01* +X131183095Y-111102142D01* +X131230714Y-111006904D01* +X131278333Y-110816428D01* +X131278333Y-110578333D01* +X131230714Y-110387857D01* +X131183095Y-110292619D01* +X131135476Y-110245000D01* +X131040238Y-110197380D01* +X130278333Y-111197380D02* +X130278333Y-110197380D01* +X129706904Y-111197380D02* +X130135476Y-110625952D01* +X129706904Y-110197380D02* +X130278333Y-110768809D01* +D13* +X131766428Y-112621190D02* +X131933095Y-112383095D01* +X132052142Y-112621190D02* +X132052142Y-112121190D01* +X131861666Y-112121190D01* +X131814047Y-112145000D01* +X131790238Y-112168809D01* +X131766428Y-112216428D01* +X131766428Y-112287857D01* +X131790238Y-112335476D01* +X131814047Y-112359285D01* +X131861666Y-112383095D01* +X132052142Y-112383095D01* +X131575952Y-112168809D02* +X131552142Y-112145000D01* +X131504523Y-112121190D01* +X131385476Y-112121190D01* +X131337857Y-112145000D01* +X131314047Y-112168809D01* +X131290238Y-112216428D01* +X131290238Y-112264047D01* +X131314047Y-112335476D01* +X131599761Y-112621190D01* +X131290238Y-112621190D01* +X130861666Y-112287857D02* +X130861666Y-112621190D01* +X130980714Y-112097380D02* +X131099761Y-112454523D01* +X130790238Y-112454523D01* +D12* +%TO.C,R1*% +X132611666Y-102942380D02* +X133183095Y-102942380D01* +X132897380Y-102942380D02* +X132897380Y-101942380D01* +X132992619Y-102085238D01* +X133087857Y-102180476D01* +X133183095Y-102228095D01* +X131992619Y-101942380D02* +X131897380Y-101942380D01* +X131802142Y-101990000D01* +X131754523Y-102037619D01* +X131706904Y-102132857D01* +X131659285Y-102323333D01* +X131659285Y-102561428D01* +X131706904Y-102751904D01* +X131754523Y-102847142D01* +X131802142Y-102894761D01* +X131897380Y-102942380D01* +X131992619Y-102942380D01* +X132087857Y-102894761D01* +X132135476Y-102847142D01* +X132183095Y-102751904D01* +X132230714Y-102561428D01* +X132230714Y-102323333D01* +X132183095Y-102132857D01* +X132135476Y-102037619D01* +X132087857Y-101990000D01* +X131992619Y-101942380D01* +X131040238Y-101942380D02* +X130945000Y-101942380D01* +X130849761Y-101990000D01* +X130802142Y-102037619D01* +X130754523Y-102132857D01* +X130706904Y-102323333D01* +X130706904Y-102561428D01* +X130754523Y-102751904D01* +X130802142Y-102847142D01* +X130849761Y-102894761D01* +X130945000Y-102942380D01* +X131040238Y-102942380D01* +X131135476Y-102894761D01* +X131183095Y-102847142D01* +X131230714Y-102751904D01* +X131278333Y-102561428D01* +X131278333Y-102323333D01* +X131230714Y-102132857D01* +X131183095Y-102037619D01* +X131135476Y-101990000D01* +X131040238Y-101942380D01* +X130278333Y-102942380D02* +X130278333Y-101942380D01* +X129706904Y-102942380D02* +X130135476Y-102370952D01* +X129706904Y-101942380D02* +X130278333Y-102513809D01* +D13* +X131528333Y-104366190D02* +X131695000Y-104128095D01* +X131814047Y-104366190D02* +X131814047Y-103866190D01* +X131623571Y-103866190D01* +X131575952Y-103890000D01* +X131552142Y-103913809D01* +X131528333Y-103961428D01* +X131528333Y-104032857D01* +X131552142Y-104080476D01* +X131575952Y-104104285D01* +X131623571Y-104128095D01* +X131814047Y-104128095D01* +X131052142Y-104366190D02* +X131337857Y-104366190D01* +X131195000Y-104366190D02* +X131195000Y-103866190D01* +X131242619Y-103937619D01* +X131290238Y-103985238D01* +X131337857Y-104009047D01* +D12* +%TO.C,C7*% +X183557380Y-129823333D02* +X183557380Y-129251904D01* +X183557380Y-129537619D02* +X182557380Y-129537619D01* +X182700238Y-129442380D01* +X182795476Y-129347142D01* +X182843095Y-129251904D01* +X182890714Y-130251904D02* +X183890714Y-130251904D01* +X183414523Y-130728095D02* +X183509761Y-130775714D01* +X183557380Y-130870952D01* +X183414523Y-130251904D02* +X183509761Y-130299523D01* +X183557380Y-130394761D01* +X183557380Y-130585238D01* +X183509761Y-130680476D01* +X183414523Y-130728095D01* +X182890714Y-130728095D01* +X183033571Y-131632857D02* +X183033571Y-131299523D01* +X183557380Y-131299523D02* +X182557380Y-131299523D01* +X182557380Y-131775714D01* +D13* +X184963571Y-130406666D02* +X184987380Y-130382857D01* +X185011190Y-130311428D01* +X185011190Y-130263809D01* +X184987380Y-130192380D01* +X184939761Y-130144761D01* +X184892142Y-130120952D01* +X184796904Y-130097142D01* +X184725476Y-130097142D01* +X184630238Y-130120952D01* +X184582619Y-130144761D01* +X184535000Y-130192380D01* +X184511190Y-130263809D01* +X184511190Y-130311428D01* +X184535000Y-130382857D01* +X184558809Y-130406666D01* +X184511190Y-130573333D02* +X184511190Y-130906666D01* +X185011190Y-130692380D01* +D12* +%TO.C,R16*% +X118942380Y-119998928D02* +X118942380Y-119427500D01* +X118942380Y-119713214D02* +X117942380Y-119713214D01* +X118085238Y-119617976D01* +X118180476Y-119522738D01* +X118228095Y-119427500D01* +X118847142Y-120427500D02* +X118894761Y-120475119D01* +X118942380Y-120427500D01* +X118894761Y-120379880D01* +X118847142Y-120427500D01* +X118942380Y-120427500D01* +X117942380Y-121379880D02* +X117942380Y-120903690D01* +X118418571Y-120856071D01* +X118370952Y-120903690D01* +X118323333Y-120998928D01* +X118323333Y-121237023D01* +X118370952Y-121332261D01* +X118418571Y-121379880D01* +X118513809Y-121427500D01* +X118751904Y-121427500D01* +X118847142Y-121379880D01* +X118894761Y-121332261D01* +X118942380Y-121237023D01* +X118942380Y-120998928D01* +X118894761Y-120903690D01* +X118847142Y-120856071D01* +X118942380Y-121856071D02* +X117942380Y-121856071D01* +X118942380Y-122427500D02* +X118370952Y-121998928D01* +X117942380Y-122427500D02* +X118513809Y-121856071D01* +D13* +X117066190Y-120606071D02* +X116828095Y-120439404D01* +X117066190Y-120320357D02* +X116566190Y-120320357D01* +X116566190Y-120510833D01* +X116590000Y-120558452D01* +X116613809Y-120582261D01* +X116661428Y-120606071D01* +X116732857Y-120606071D01* +X116780476Y-120582261D01* +X116804285Y-120558452D01* +X116828095Y-120510833D01* +X116828095Y-120320357D01* +X117066190Y-121082261D02* +X117066190Y-120796547D01* +X117066190Y-120939404D02* +X116566190Y-120939404D01* +X116637619Y-120891785D01* +X116685238Y-120844166D01* +X116709047Y-120796547D01* +X116566190Y-121510833D02* +X116566190Y-121415595D01* +X116590000Y-121367976D01* +X116613809Y-121344166D01* +X116685238Y-121296547D01* +X116780476Y-121272738D01* +X116970952Y-121272738D01* +X117018571Y-121296547D01* +X117042380Y-121320357D01* +X117066190Y-121367976D01* +X117066190Y-121463214D01* +X117042380Y-121510833D01* +X117018571Y-121534642D01* +X116970952Y-121558452D01* +X116851904Y-121558452D01* +X116804285Y-121534642D01* +X116780476Y-121510833D01* +X116756666Y-121463214D01* +X116756666Y-121367976D01* +X116780476Y-121320357D01* +X116804285Y-121296547D01* +X116851904Y-121272738D01* +D12* +%TO.C,R13*% +X176332619Y-108355000D02* +X176285000Y-108402619D01* +X176237380Y-108497857D01* +X176237380Y-108735952D01* +X176285000Y-108831190D01* +X176332619Y-108878809D01* +X176427857Y-108926428D01* +X176523095Y-108926428D01* +X176665952Y-108878809D01* +X177237380Y-108307380D01* +X177237380Y-108926428D01* +X177142142Y-109355000D02* +X177189761Y-109402619D01* +X177237380Y-109355000D01* +X177189761Y-109307380D01* +X177142142Y-109355000D01* +X177237380Y-109355000D01* +X176332619Y-109783571D02* +X176285000Y-109831190D01* +X176237380Y-109926428D01* +X176237380Y-110164523D01* +X176285000Y-110259761D01* +X176332619Y-110307380D01* +X176427857Y-110355000D01* +X176523095Y-110355000D01* +X176665952Y-110307380D01* +X177237380Y-109735952D01* +X177237380Y-110355000D01* +X177237380Y-110783571D02* +X176237380Y-110783571D01* +X177237380Y-111355000D02* +X176665952Y-110926428D01* +X176237380Y-111355000D02* +X176808809Y-110783571D01* +D13* +X178661190Y-109533571D02* +X178423095Y-109366904D01* +X178661190Y-109247857D02* +X178161190Y-109247857D01* +X178161190Y-109438333D01* +X178185000Y-109485952D01* +X178208809Y-109509761D01* +X178256428Y-109533571D01* +X178327857Y-109533571D01* +X178375476Y-109509761D01* +X178399285Y-109485952D01* +X178423095Y-109438333D01* +X178423095Y-109247857D01* +X178661190Y-110009761D02* +X178661190Y-109724047D01* +X178661190Y-109866904D02* +X178161190Y-109866904D01* +X178232619Y-109819285D01* +X178280238Y-109771666D01* +X178304047Y-109724047D01* +X178161190Y-110176428D02* +X178161190Y-110485952D01* +X178351666Y-110319285D01* +X178351666Y-110390714D01* +X178375476Y-110438333D01* +X178399285Y-110462142D01* +X178446904Y-110485952D01* +X178565952Y-110485952D01* +X178613571Y-110462142D01* +X178637380Y-110438333D01* +X178661190Y-110390714D01* +X178661190Y-110247857D01* +X178637380Y-110200238D01* +X178613571Y-110176428D01* +D12* +%TO.C,U7*% +X152637857Y-103996666D02* +X152161666Y-103996666D01* +X152733095Y-104282380D02* +X152399761Y-103282380D01* +X152066428Y-104282380D01* +X151828333Y-103282380D02* +X151209285Y-103282380D01* +X151542619Y-103663333D01* +X151399761Y-103663333D01* +X151304523Y-103710952D01* +X151256904Y-103758571D01* +X151209285Y-103853809D01* +X151209285Y-104091904D01* +X151256904Y-104187142D01* +X151304523Y-104234761D01* +X151399761Y-104282380D01* +X151685476Y-104282380D01* +X151780714Y-104234761D01* +X151828333Y-104187142D01* +X150733095Y-104282380D02* +X150542619Y-104282380D01* +X150447380Y-104234761D01* +X150399761Y-104187142D01* +X150304523Y-104044285D01* +X150256904Y-103853809D01* +X150256904Y-103472857D01* +X150304523Y-103377619D01* +X150352142Y-103330000D01* +X150447380Y-103282380D01* +X150637857Y-103282380D01* +X150733095Y-103330000D01* +X150780714Y-103377619D01* +X150828333Y-103472857D01* +X150828333Y-103710952D01* +X150780714Y-103806190D01* +X150733095Y-103853809D01* +X150637857Y-103901428D01* +X150447380Y-103901428D01* +X150352142Y-103853809D01* +X150304523Y-103806190D01* +X150256904Y-103710952D01* +X149637857Y-103282380D02* +X149542619Y-103282380D01* +X149447380Y-103330000D01* +X149399761Y-103377619D01* +X149352142Y-103472857D01* +X149304523Y-103663333D01* +X149304523Y-103901428D01* +X149352142Y-104091904D01* +X149399761Y-104187142D01* +X149447380Y-104234761D01* +X149542619Y-104282380D01* +X149637857Y-104282380D01* +X149733095Y-104234761D01* +X149780714Y-104187142D01* +X149828333Y-104091904D01* +X149875952Y-103901428D01* +X149875952Y-103663333D01* +X149828333Y-103472857D01* +X149780714Y-103377619D01* +X149733095Y-103330000D01* +X149637857Y-103282380D01* +X148828333Y-104282380D02* +X148637857Y-104282380D01* +X148542619Y-104234761D01* +X148495000Y-104187142D01* +X148399761Y-104044285D01* +X148352142Y-103853809D01* +X148352142Y-103472857D01* +X148399761Y-103377619D01* +X148447380Y-103330000D01* +X148542619Y-103282380D01* +X148733095Y-103282380D01* +X148828333Y-103330000D01* +X148875952Y-103377619D01* +X148923571Y-103472857D01* +X148923571Y-103710952D01* +X148875952Y-103806190D01* +X148828333Y-103853809D01* +X148733095Y-103901428D01* +X148542619Y-103901428D01* +X148447380Y-103853809D01* +X148399761Y-103806190D01* +X148352142Y-103710952D01* +X151256904Y-99782380D02* +X151256904Y-100591904D01* +X151209285Y-100687142D01* +X151161666Y-100734761D01* +X151066428Y-100782380D01* +X150875952Y-100782380D01* +X150780714Y-100734761D01* +X150733095Y-100687142D01* +X150685476Y-100591904D01* +X150685476Y-99782380D01* +X150304523Y-99782380D02* +X149637857Y-99782380D01* +X150066428Y-100782380D01* +%TO.C,R21*% +X176172619Y-116672380D02* +X175505952Y-116672380D01* +X175934523Y-117672380D01* +X175077380Y-117624761D02* +X175077380Y-117672380D01* +X175125000Y-117767619D01* +X175172619Y-117815238D01* +X174172619Y-116672380D02* +X174648809Y-116672380D01* +X174696428Y-117148571D01* +X174648809Y-117100952D01* +X174553571Y-117053333D01* +X174315476Y-117053333D01* +X174220238Y-117100952D01* +X174172619Y-117148571D01* +X174125000Y-117243809D01* +X174125000Y-117481904D01* +X174172619Y-117577142D01* +X174220238Y-117624761D01* +X174315476Y-117672380D01* +X174553571Y-117672380D01* +X174648809Y-117624761D01* +X174696428Y-117577142D01* +X173696428Y-117672380D02* +X173696428Y-116672380D01* +X173125000Y-117672380D02* +X173553571Y-117100952D01* +X173125000Y-116672380D02* +X173696428Y-117243809D01* +D13* +X174946428Y-115796190D02* +X175113095Y-115558095D01* +X175232142Y-115796190D02* +X175232142Y-115296190D01* +X175041666Y-115296190D01* +X174994047Y-115320000D01* +X174970238Y-115343809D01* +X174946428Y-115391428D01* +X174946428Y-115462857D01* +X174970238Y-115510476D01* +X174994047Y-115534285D01* +X175041666Y-115558095D01* +X175232142Y-115558095D01* +X174755952Y-115343809D02* +X174732142Y-115320000D01* +X174684523Y-115296190D01* +X174565476Y-115296190D01* +X174517857Y-115320000D01* +X174494047Y-115343809D01* +X174470238Y-115391428D01* +X174470238Y-115439047D01* +X174494047Y-115510476D01* +X174779761Y-115796190D01* +X174470238Y-115796190D01* +X173994047Y-115796190D02* +X174279761Y-115796190D01* +X174136904Y-115796190D02* +X174136904Y-115296190D01* +X174184523Y-115367619D01* +X174232142Y-115415238D01* +X174279761Y-115439047D01* +D12* +%TO.C,C3*% +X190727380Y-105378333D02* +X190727380Y-104806904D01* +X190727380Y-105092619D02* +X189727380Y-105092619D01* +X189870238Y-104997380D01* +X189965476Y-104902142D01* +X190013095Y-104806904D01* +X190060714Y-105806904D02* +X191060714Y-105806904D01* +X190584523Y-106283095D02* +X190679761Y-106330714D01* +X190727380Y-106425952D01* +X190584523Y-105806904D02* +X190679761Y-105854523D01* +X190727380Y-105949761D01* +X190727380Y-106140238D01* +X190679761Y-106235476D01* +X190584523Y-106283095D01* +X190060714Y-106283095D01* +X190203571Y-107187857D02* +X190203571Y-106854523D01* +X190727380Y-106854523D02* +X189727380Y-106854523D01* +X189727380Y-107330714D01* +D13* +X188773571Y-105961666D02* +X188797380Y-105937857D01* +X188821190Y-105866428D01* +X188821190Y-105818809D01* +X188797380Y-105747380D01* +X188749761Y-105699761D01* +X188702142Y-105675952D01* +X188606904Y-105652142D01* +X188535476Y-105652142D01* +X188440238Y-105675952D01* +X188392619Y-105699761D01* +X188345000Y-105747380D01* +X188321190Y-105818809D01* +X188321190Y-105866428D01* +X188345000Y-105937857D01* +X188368809Y-105961666D01* +X188321190Y-106128333D02* +X188321190Y-106437857D01* +X188511666Y-106271190D01* +X188511666Y-106342619D01* +X188535476Y-106390238D01* +X188559285Y-106414047D01* +X188606904Y-106437857D01* +X188725952Y-106437857D01* +X188773571Y-106414047D01* +X188797380Y-106390238D01* +X188821190Y-106342619D01* +X188821190Y-106199761D01* +X188797380Y-106152142D01* +X188773571Y-106128333D01* +D12* +%TO.C,R2*% +X123721666Y-104337380D02* +X124293095Y-104337380D01* +X124007380Y-104337380D02* +X124007380Y-103337380D01* +X124102619Y-103480238D01* +X124197857Y-103575476D01* +X124293095Y-103623095D01* +X123102619Y-103337380D02* +X123007380Y-103337380D01* +X122912142Y-103385000D01* +X122864523Y-103432619D01* +X122816904Y-103527857D01* +X122769285Y-103718333D01* +X122769285Y-103956428D01* +X122816904Y-104146904D01* +X122864523Y-104242142D01* +X122912142Y-104289761D01* +X123007380Y-104337380D01* +X123102619Y-104337380D01* +X123197857Y-104289761D01* +X123245476Y-104242142D01* +X123293095Y-104146904D01* +X123340714Y-103956428D01* +X123340714Y-103718333D01* +X123293095Y-103527857D01* +X123245476Y-103432619D01* +X123197857Y-103385000D01* +X123102619Y-103337380D01* +X122150238Y-103337380D02* +X122055000Y-103337380D01* +X121959761Y-103385000D01* +X121912142Y-103432619D01* +X121864523Y-103527857D01* +X121816904Y-103718333D01* +X121816904Y-103956428D01* +X121864523Y-104146904D01* +X121912142Y-104242142D01* +X121959761Y-104289761D01* +X122055000Y-104337380D01* +X122150238Y-104337380D01* +X122245476Y-104289761D01* +X122293095Y-104242142D01* +X122340714Y-104146904D01* +X122388333Y-103956428D01* +X122388333Y-103718333D01* +X122340714Y-103527857D01* +X122293095Y-103432619D01* +X122245476Y-103385000D01* +X122150238Y-103337380D01* +X121388333Y-104337380D02* +X121388333Y-103337380D01* +X120816904Y-104337380D02* +X121245476Y-103765952D01* +X120816904Y-103337380D02* +X121388333Y-103908809D01* +D13* +X122638333Y-102461190D02* +X122805000Y-102223095D01* +X122924047Y-102461190D02* +X122924047Y-101961190D01* +X122733571Y-101961190D01* +X122685952Y-101985000D01* +X122662142Y-102008809D01* +X122638333Y-102056428D01* +X122638333Y-102127857D01* +X122662142Y-102175476D01* +X122685952Y-102199285D01* +X122733571Y-102223095D01* +X122924047Y-102223095D01* +X122447857Y-102008809D02* +X122424047Y-101985000D01* +X122376428Y-101961190D01* +X122257380Y-101961190D01* +X122209761Y-101985000D01* +X122185952Y-102008809D01* +X122162142Y-102056428D01* +X122162142Y-102104047D01* +X122185952Y-102175476D01* +X122471666Y-102461190D01* +X122162142Y-102461190D01* +D12* +%TO.C,JP1*% +X157685476Y-127717380D02* +X157685476Y-128431666D01* +X157733095Y-128574523D01* +X157828333Y-128669761D01* +X157971190Y-128717380D01* +X158066428Y-128717380D01* +X156780714Y-128050714D02* +X156780714Y-128717380D01* +X157209285Y-128050714D02* +X157209285Y-128574523D01* +X157161666Y-128669761D01* +X157066428Y-128717380D01* +X156923571Y-128717380D01* +X156828333Y-128669761D01* +X156780714Y-128622142D01* +X156304523Y-128717380D02* +X156304523Y-128050714D01* +X156304523Y-128145952D02* +X156256904Y-128098333D01* +X156161666Y-128050714D01* +X156018809Y-128050714D01* +X155923571Y-128098333D01* +X155875952Y-128193571D01* +X155875952Y-128717380D01* +X155875952Y-128193571D02* +X155828333Y-128098333D01* +X155733095Y-128050714D01* +X155590238Y-128050714D01* +X155495000Y-128098333D01* +X155447380Y-128193571D01* +X155447380Y-128717380D01* +X154971190Y-128050714D02* +X154971190Y-129050714D01* +X154971190Y-128098333D02* +X154875952Y-128050714D01* +X154685476Y-128050714D01* +X154590238Y-128098333D01* +X154542619Y-128145952D01* +X154495000Y-128241190D01* +X154495000Y-128526904D01* +X154542619Y-128622142D01* +X154590238Y-128669761D01* +X154685476Y-128717380D01* +X154875952Y-128717380D01* +X154971190Y-128669761D01* +X153685476Y-128669761D02* +X153780714Y-128717380D01* +X153971190Y-128717380D01* +X154066428Y-128669761D01* +X154114047Y-128574523D01* +X154114047Y-128193571D01* +X154066428Y-128098333D01* +X153971190Y-128050714D01* +X153780714Y-128050714D01* +X153685476Y-128098333D01* +X153637857Y-128193571D01* +X153637857Y-128288809D01* +X154114047Y-128384047D01* +X153209285Y-128717380D02* +X153209285Y-128050714D01* +X153209285Y-128241190D02* +X153161666Y-128145952D01* +X153114047Y-128098333D01* +X153018809Y-128050714D01* +X152923571Y-128050714D01* +X152828333Y-128812619D02* +X152066428Y-128812619D01* +X151923571Y-127717380D02* +X151304523Y-127717380D01* +X151637857Y-128098333D01* +X151495000Y-128098333D01* +X151399761Y-128145952D01* +X151352142Y-128193571D01* +X151304523Y-128288809D01* +X151304523Y-128526904D01* +X151352142Y-128622142D01* +X151399761Y-128669761D01* +X151495000Y-128717380D01* +X151780714Y-128717380D01* +X151875952Y-128669761D01* +X151923571Y-128622142D01* +X151114047Y-128812619D02* +X150352142Y-128812619D01* +X149780714Y-128193571D02* +X149637857Y-128241190D01* +X149590238Y-128288809D01* +X149542619Y-128384047D01* +X149542619Y-128526904D01* +X149590238Y-128622142D01* +X149637857Y-128669761D01* +X149733095Y-128717380D01* +X150114047Y-128717380D01* +X150114047Y-127717380D01* +X149780714Y-127717380D01* +X149685476Y-127765000D01* +X149637857Y-127812619D01* +X149590238Y-127907857D01* +X149590238Y-128003095D01* +X149637857Y-128098333D01* +X149685476Y-128145952D01* +X149780714Y-128193571D01* +X150114047Y-128193571D01* +X149114047Y-128717380D02* +X149114047Y-128050714D01* +X149114047Y-128241190D02* +X149066428Y-128145952D01* +X149018809Y-128098333D01* +X148923571Y-128050714D01* +X148828333Y-128050714D01* +X148495000Y-128717380D02* +X148495000Y-128050714D01* +X148495000Y-127717380D02* +X148542619Y-127765000D01* +X148495000Y-127812619D01* +X148447380Y-127765000D01* +X148495000Y-127717380D01* +X148495000Y-127812619D01* +X147590238Y-128717380D02* +X147590238Y-127717380D01* +X147590238Y-128669761D02* +X147685476Y-128717380D01* +X147875952Y-128717380D01* +X147971190Y-128669761D01* +X148018809Y-128622142D01* +X148066428Y-128526904D01* +X148066428Y-128241190D01* +X148018809Y-128145952D01* +X147971190Y-128098333D01* +X147875952Y-128050714D01* +X147685476Y-128050714D01* +X147590238Y-128098333D01* +X146685476Y-128050714D02* +X146685476Y-128860238D01* +X146733095Y-128955476D01* +X146780714Y-129003095D01* +X146875952Y-129050714D01* +X147018809Y-129050714D01* +X147114047Y-129003095D01* +X146685476Y-128669761D02* +X146780714Y-128717380D01* +X146971190Y-128717380D01* +X147066428Y-128669761D01* +X147114047Y-128622142D01* +X147161666Y-128526904D01* +X147161666Y-128241190D01* +X147114047Y-128145952D01* +X147066428Y-128098333D01* +X146971190Y-128050714D01* +X146780714Y-128050714D01* +X146685476Y-128098333D01* +X145828333Y-128669761D02* +X145923571Y-128717380D01* +X146114047Y-128717380D01* +X146209285Y-128669761D01* +X146256904Y-128574523D01* +X146256904Y-128193571D01* +X146209285Y-128098333D01* +X146114047Y-128050714D01* +X145923571Y-128050714D01* +X145828333Y-128098333D01* +X145780714Y-128193571D01* +X145780714Y-128288809D01* +X146256904Y-128384047D01* +X144923571Y-128717380D02* +X144923571Y-127717380D01* +X144923571Y-128669761D02* +X145018809Y-128717380D01* +X145209285Y-128717380D01* +X145304523Y-128669761D01* +X145352142Y-128622142D01* +X145399761Y-128526904D01* +X145399761Y-128241190D01* +X145352142Y-128145952D01* +X145304523Y-128098333D01* +X145209285Y-128050714D01* +X145018809Y-128050714D01* +X144923571Y-128098333D01* +X143923571Y-128717380D02* +X144495000Y-128717380D01* +X144209285Y-128717380D02* +X144209285Y-127717380D01* +X144304523Y-127860238D01* +X144399761Y-127955476D01* +X144495000Y-128003095D01* +X143542619Y-127812619D02* +X143495000Y-127765000D01* +X143399761Y-127717380D01* +X143161666Y-127717380D01* +X143066428Y-127765000D01* +X143018809Y-127812619D01* +X142971190Y-127907857D01* +X142971190Y-128003095D01* +X143018809Y-128145952D01* +X143590238Y-128717380D01* +X142971190Y-128717380D01* +%TO.C,C8*% +X175069285Y-89440119D02* +X175021666Y-89392500D01* +X174926428Y-89344880D01* +X174688333Y-89344880D01* +X174593095Y-89392500D01* +X174545476Y-89440119D01* +X174497857Y-89535357D01* +X174497857Y-89630595D01* +X174545476Y-89773452D01* +X175116904Y-90344880D01* +X174497857Y-90344880D01* +X174116904Y-89440119D02* +X174069285Y-89392500D01* +X173974047Y-89344880D01* +X173735952Y-89344880D01* +X173640714Y-89392500D01* +X173593095Y-89440119D01* +X173545476Y-89535357D01* +X173545476Y-89630595D01* +X173593095Y-89773452D01* +X174164523Y-90344880D01* +X173545476Y-90344880D01* +X173116904Y-89678214D02* +X173116904Y-90678214D01* +X172640714Y-90202023D02* +X172593095Y-90297261D01* +X172497857Y-90344880D01* +X173116904Y-90202023D02* +X173069285Y-90297261D01* +X172974047Y-90344880D01* +X172783571Y-90344880D01* +X172688333Y-90297261D01* +X172640714Y-90202023D01* +X172640714Y-89678214D01* +X171735952Y-89821071D02* +X172069285Y-89821071D01* +X172069285Y-90344880D02* +X172069285Y-89344880D01* +X171593095Y-89344880D01* +D13* +X173438333Y-91751071D02* +X173462142Y-91774880D01* +X173533571Y-91798690D01* +X173581190Y-91798690D01* +X173652619Y-91774880D01* +X173700238Y-91727261D01* +X173724047Y-91679642D01* +X173747857Y-91584404D01* +X173747857Y-91512976D01* +X173724047Y-91417738D01* +X173700238Y-91370119D01* +X173652619Y-91322500D01* +X173581190Y-91298690D01* +X173533571Y-91298690D01* +X173462142Y-91322500D01* +X173438333Y-91346309D01* +X173152619Y-91512976D02* +X173200238Y-91489166D01* +X173224047Y-91465357D01* +X173247857Y-91417738D01* +X173247857Y-91393928D01* +X173224047Y-91346309D01* +X173200238Y-91322500D01* +X173152619Y-91298690D01* +X173057380Y-91298690D01* +X173009761Y-91322500D01* +X172985952Y-91346309D01* +X172962142Y-91393928D01* +X172962142Y-91417738D01* +X172985952Y-91465357D01* +X173009761Y-91489166D01* +X173057380Y-91512976D01* +X173152619Y-91512976D01* +X173200238Y-91536785D01* +X173224047Y-91560595D01* +X173247857Y-91608214D01* +X173247857Y-91703452D01* +X173224047Y-91751071D01* +X173200238Y-91774880D01* +X173152619Y-91798690D01* +X173057380Y-91798690D01* +X173009761Y-91774880D01* +X172985952Y-91751071D01* +X172962142Y-91703452D01* +X172962142Y-91608214D01* +X172985952Y-91560595D01* +X173009761Y-91536785D01* +X173057380Y-91512976D01* +D12* +%TO.C,R5*% +X176466785Y-118817380D02* +X177038214Y-118817380D01* +X176752500Y-118817380D02* +X176752500Y-117817380D01* +X176847738Y-117960238D01* +X176942976Y-118055476D01* +X177038214Y-118103095D01* +X176038214Y-118817380D02* +X176038214Y-117817380D01* +X175466785Y-118817380D02* +X175895357Y-118245952D01* +X175466785Y-117817380D02* +X176038214Y-118388809D01* +D13* +X176335833Y-120241190D02* +X176502500Y-120003095D01* +X176621547Y-120241190D02* +X176621547Y-119741190D01* +X176431071Y-119741190D01* +X176383452Y-119765000D01* +X176359642Y-119788809D01* +X176335833Y-119836428D01* +X176335833Y-119907857D01* +X176359642Y-119955476D01* +X176383452Y-119979285D01* +X176431071Y-120003095D01* +X176621547Y-120003095D01* +X175883452Y-119741190D02* +X176121547Y-119741190D01* +X176145357Y-119979285D01* +X176121547Y-119955476D01* +X176073928Y-119931666D01* +X175954880Y-119931666D01* +X175907261Y-119955476D01* +X175883452Y-119979285D01* +X175859642Y-120026904D01* +X175859642Y-120145952D01* +X175883452Y-120193571D01* +X175907261Y-120217380D01* +X175954880Y-120241190D01* +X176073928Y-120241190D01* +X176121547Y-120217380D01* +X176145357Y-120193571D01* +D12* +%TO.C,R11*% +X181641261Y-86430380D02* +X182212690Y-86430380D01* +X181926976Y-86430380D02* +X181926976Y-85430380D01* +X182022214Y-85573238D01* +X182117452Y-85668476D01* +X182212690Y-85716095D01* +X181212690Y-86335142D02* +X181165071Y-86382761D01* +X181212690Y-86430380D01* +X181260309Y-86382761D01* +X181212690Y-86335142D01* +X181212690Y-86430380D01* +X180784119Y-85525619D02* +X180736500Y-85478000D01* +X180641261Y-85430380D01* +X180403166Y-85430380D01* +X180307928Y-85478000D01* +X180260309Y-85525619D01* +X180212690Y-85620857D01* +X180212690Y-85716095D01* +X180260309Y-85858952D01* +X180831738Y-86430380D01* +X180212690Y-86430380D01* +X179641261Y-85858952D02* +X179736500Y-85811333D01* +X179784119Y-85763714D01* +X179831738Y-85668476D01* +X179831738Y-85620857D01* +X179784119Y-85525619D01* +X179736500Y-85478000D01* +X179641261Y-85430380D01* +X179450785Y-85430380D01* +X179355547Y-85478000D01* +X179307928Y-85525619D01* +X179260309Y-85620857D01* +X179260309Y-85668476D01* +X179307928Y-85763714D01* +X179355547Y-85811333D01* +X179450785Y-85858952D01* +X179641261Y-85858952D01* +X179736500Y-85906571D01* +X179784119Y-85954190D01* +X179831738Y-86049428D01* +X179831738Y-86239904D01* +X179784119Y-86335142D01* +X179736500Y-86382761D01* +X179641261Y-86430380D01* +X179450785Y-86430380D01* +X179355547Y-86382761D01* +X179307928Y-86335142D01* +X179260309Y-86239904D01* +X179260309Y-86049428D01* +X179307928Y-85954190D01* +X179355547Y-85906571D01* +X179450785Y-85858952D01* +X178831738Y-86430380D02* +X178831738Y-85430380D01* +X178260309Y-86430380D02* +X178688880Y-85858952D01* +X178260309Y-85430380D02* +X178831738Y-86001809D01* +D13* +X180557928Y-84554190D02* +X180724595Y-84316095D01* +X180843642Y-84554190D02* +X180843642Y-84054190D01* +X180653166Y-84054190D01* +X180605547Y-84078000D01* +X180581738Y-84101809D01* +X180557928Y-84149428D01* +X180557928Y-84220857D01* +X180581738Y-84268476D01* +X180605547Y-84292285D01* +X180653166Y-84316095D01* +X180843642Y-84316095D01* +X180081738Y-84554190D02* +X180367452Y-84554190D01* +X180224595Y-84554190D02* +X180224595Y-84054190D01* +X180272214Y-84125619D01* +X180319833Y-84173238D01* +X180367452Y-84197047D01* +X179605547Y-84554190D02* +X179891261Y-84554190D01* +X179748404Y-84554190D02* +X179748404Y-84054190D01* +X179796023Y-84125619D01* +X179843642Y-84173238D01* +X179891261Y-84197047D01* +D12* +%TO.C,C5*% +X187044380Y-82780380D02* +X187044380Y-82208952D01* +X187044380Y-82494666D02* +X186044380Y-82494666D01* +X186187238Y-82399428D01* +X186282476Y-82304190D01* +X186330095Y-82208952D01* +X186044380Y-83399428D02* +X186044380Y-83494666D01* +X186092000Y-83589904D01* +X186139619Y-83637523D01* +X186234857Y-83685142D01* +X186425333Y-83732761D01* +X186663428Y-83732761D01* +X186853904Y-83685142D01* +X186949142Y-83637523D01* +X186996761Y-83589904D01* +X187044380Y-83494666D01* +X187044380Y-83399428D01* +X186996761Y-83304190D01* +X186949142Y-83256571D01* +X186853904Y-83208952D01* +X186663428Y-83161333D01* +X186425333Y-83161333D01* +X186234857Y-83208952D01* +X186139619Y-83256571D01* +X186092000Y-83304190D01* +X186044380Y-83399428D01* +X186044380Y-84351809D02* +X186044380Y-84447047D01* +X186092000Y-84542285D01* +X186139619Y-84589904D01* +X186234857Y-84637523D01* +X186425333Y-84685142D01* +X186663428Y-84685142D01* +X186853904Y-84637523D01* +X186949142Y-84589904D01* +X186996761Y-84542285D01* +X187044380Y-84447047D01* +X187044380Y-84351809D01* +X186996761Y-84256571D01* +X186949142Y-84208952D01* +X186853904Y-84161333D01* +X186663428Y-84113714D01* +X186425333Y-84113714D01* +X186234857Y-84161333D01* +X186139619Y-84208952D01* +X186092000Y-84256571D01* +X186044380Y-84351809D01* +X186377714Y-85113714D02* +X187044380Y-85113714D01* +X186472952Y-85113714D02* +X186425333Y-85161333D01* +X186377714Y-85256571D01* +X186377714Y-85399428D01* +X186425333Y-85494666D01* +X186520571Y-85542285D01* +X187044380Y-85542285D01* +X186520571Y-86351809D02* +X186520571Y-86018476D01* +X187044380Y-86018476D02* +X186044380Y-86018476D01* +X186044380Y-86494666D01* +D13* +X185090571Y-84244666D02* +X185114380Y-84220857D01* +X185138190Y-84149428D01* +X185138190Y-84101809D01* +X185114380Y-84030380D01* +X185066761Y-83982761D01* +X185019142Y-83958952D01* +X184923904Y-83935142D01* +X184852476Y-83935142D01* +X184757238Y-83958952D01* +X184709619Y-83982761D01* +X184662000Y-84030380D01* +X184638190Y-84101809D01* +X184638190Y-84149428D01* +X184662000Y-84220857D01* +X184685809Y-84244666D01* +X184638190Y-84697047D02* +X184638190Y-84458952D01* +X184876285Y-84435142D01* +X184852476Y-84458952D01* +X184828666Y-84506571D01* +X184828666Y-84625619D01* +X184852476Y-84673238D01* +X184876285Y-84697047D01* +X184923904Y-84720857D01* +X185042952Y-84720857D01* +X185090571Y-84697047D01* +X185114380Y-84673238D01* +X185138190Y-84625619D01* +X185138190Y-84506571D01* +X185114380Y-84458952D01* +X185090571Y-84435142D01* +D12* +%TO.C,R18*% +X170711666Y-124532380D02* +X171283095Y-124532380D01* +X170997380Y-124532380D02* +X170997380Y-123532380D01* +X171092619Y-123675238D01* +X171187857Y-123770476D01* +X171283095Y-123818095D01* +X170092619Y-123532380D02* +X169997380Y-123532380D01* +X169902142Y-123580000D01* +X169854523Y-123627619D01* +X169806904Y-123722857D01* +X169759285Y-123913333D01* +X169759285Y-124151428D01* +X169806904Y-124341904D01* +X169854523Y-124437142D01* +X169902142Y-124484761D01* +X169997380Y-124532380D01* +X170092619Y-124532380D01* +X170187857Y-124484761D01* +X170235476Y-124437142D01* +X170283095Y-124341904D01* +X170330714Y-124151428D01* +X170330714Y-123913333D01* +X170283095Y-123722857D01* +X170235476Y-123627619D01* +X170187857Y-123580000D01* +X170092619Y-123532380D01* +X169140238Y-123532380D02* +X169045000Y-123532380D01* +X168949761Y-123580000D01* +X168902142Y-123627619D01* +X168854523Y-123722857D01* +X168806904Y-123913333D01* +X168806904Y-124151428D01* +X168854523Y-124341904D01* +X168902142Y-124437142D01* +X168949761Y-124484761D01* +X169045000Y-124532380D01* +X169140238Y-124532380D01* +X169235476Y-124484761D01* +X169283095Y-124437142D01* +X169330714Y-124341904D01* +X169378333Y-124151428D01* +X169378333Y-123913333D01* +X169330714Y-123722857D01* +X169283095Y-123627619D01* +X169235476Y-123580000D01* +X169140238Y-123532380D01* +X168378333Y-124532380D02* +X168378333Y-123532380D01* +X167806904Y-124532380D02* +X168235476Y-123960952D01* +X167806904Y-123532380D02* +X168378333Y-124103809D01* +D13* +X169866428Y-125956190D02* +X170033095Y-125718095D01* +X170152142Y-125956190D02* +X170152142Y-125456190D01* +X169961666Y-125456190D01* +X169914047Y-125480000D01* +X169890238Y-125503809D01* +X169866428Y-125551428D01* +X169866428Y-125622857D01* +X169890238Y-125670476D01* +X169914047Y-125694285D01* +X169961666Y-125718095D01* +X170152142Y-125718095D01* +X169390238Y-125956190D02* +X169675952Y-125956190D01* +X169533095Y-125956190D02* +X169533095Y-125456190D01* +X169580714Y-125527619D01* +X169628333Y-125575238D01* +X169675952Y-125599047D01* +X169104523Y-125670476D02* +X169152142Y-125646666D01* +X169175952Y-125622857D01* +X169199761Y-125575238D01* +X169199761Y-125551428D01* +X169175952Y-125503809D01* +X169152142Y-125480000D01* +X169104523Y-125456190D01* +X169009285Y-125456190D01* +X168961666Y-125480000D01* +X168937857Y-125503809D01* +X168914047Y-125551428D01* +X168914047Y-125575238D01* +X168937857Y-125622857D01* +X168961666Y-125646666D01* +X169009285Y-125670476D01* +X169104523Y-125670476D01* +X169152142Y-125694285D01* +X169175952Y-125718095D01* +X169199761Y-125765714D01* +X169199761Y-125860952D01* +X169175952Y-125908571D01* +X169152142Y-125932380D01* +X169104523Y-125956190D01* +X169009285Y-125956190D01* +X168961666Y-125932380D01* +X168937857Y-125908571D01* +X168914047Y-125860952D01* +X168914047Y-125765714D01* +X168937857Y-125718095D01* +X168961666Y-125694285D01* +X169009285Y-125670476D01* +D12* +%TO.C,R19*% +X170711666Y-133547380D02* +X171283095Y-133547380D01* +X170997380Y-133547380D02* +X170997380Y-132547380D01* +X171092619Y-132690238D01* +X171187857Y-132785476D01* +X171283095Y-132833095D01* +X169806904Y-132547380D02* +X170283095Y-132547380D01* +X170330714Y-133023571D01* +X170283095Y-132975952D01* +X170187857Y-132928333D01* +X169949761Y-132928333D01* +X169854523Y-132975952D01* +X169806904Y-133023571D01* +X169759285Y-133118809D01* +X169759285Y-133356904D01* +X169806904Y-133452142D01* +X169854523Y-133499761D01* +X169949761Y-133547380D01* +X170187857Y-133547380D01* +X170283095Y-133499761D01* +X170330714Y-133452142D01* +X169140238Y-132547380D02* +X169045000Y-132547380D01* +X168949761Y-132595000D01* +X168902142Y-132642619D01* +X168854523Y-132737857D01* +X168806904Y-132928333D01* +X168806904Y-133166428D01* +X168854523Y-133356904D01* +X168902142Y-133452142D01* +X168949761Y-133499761D01* +X169045000Y-133547380D01* +X169140238Y-133547380D01* +X169235476Y-133499761D01* +X169283095Y-133452142D01* +X169330714Y-133356904D01* +X169378333Y-133166428D01* +X169378333Y-132928333D01* +X169330714Y-132737857D01* +X169283095Y-132642619D01* +X169235476Y-132595000D01* +X169140238Y-132547380D01* +X168378333Y-133547380D02* +X168378333Y-132547380D01* +X167806904Y-133547380D02* +X168235476Y-132975952D01* +X167806904Y-132547380D02* +X168378333Y-133118809D01* +D13* +X169866428Y-131671190D02* +X170033095Y-131433095D01* +X170152142Y-131671190D02* +X170152142Y-131171190D01* +X169961666Y-131171190D01* +X169914047Y-131195000D01* +X169890238Y-131218809D01* +X169866428Y-131266428D01* +X169866428Y-131337857D01* +X169890238Y-131385476D01* +X169914047Y-131409285D01* +X169961666Y-131433095D01* +X170152142Y-131433095D01* +X169390238Y-131671190D02* +X169675952Y-131671190D01* +X169533095Y-131671190D02* +X169533095Y-131171190D01* +X169580714Y-131242619D01* +X169628333Y-131290238D01* +X169675952Y-131314047D01* +X169152142Y-131671190D02* +X169056904Y-131671190D01* +X169009285Y-131647380D01* +X168985476Y-131623571D01* +X168937857Y-131552142D01* +X168914047Y-131456904D01* +X168914047Y-131266428D01* +X168937857Y-131218809D01* +X168961666Y-131195000D01* +X169009285Y-131171190D01* +X169104523Y-131171190D01* +X169152142Y-131195000D01* +X169175952Y-131218809D01* +X169199761Y-131266428D01* +X169199761Y-131385476D01* +X169175952Y-131433095D01* +X169152142Y-131456904D01* +X169104523Y-131480714D01* +X169009285Y-131480714D01* +X168961666Y-131456904D01* +X168937857Y-131433095D01* +X168914047Y-131385476D01* +D12* +%TO.C,C13*% +X119091666Y-116432380D02* +X119663095Y-116432380D01* +X119377380Y-116432380D02* +X119377380Y-115432380D01* +X119472619Y-115575238D01* +X119567857Y-115670476D01* +X119663095Y-115718095D01* +X118663095Y-115765714D02* +X118663095Y-116765714D01* +X118186904Y-116289523D02* +X118139285Y-116384761D01* +X118044047Y-116432380D01* +X118663095Y-116289523D02* +X118615476Y-116384761D01* +X118520238Y-116432380D01* +X118329761Y-116432380D01* +X118234523Y-116384761D01* +X118186904Y-116289523D01* +X118186904Y-115765714D01* +X117282142Y-115908571D02* +X117615476Y-115908571D01* +X117615476Y-116432380D02* +X117615476Y-115432380D01* +X117139285Y-115432380D01* +D13* +X118746428Y-114478571D02* +X118770238Y-114502380D01* +X118841666Y-114526190D01* +X118889285Y-114526190D01* +X118960714Y-114502380D01* +X119008333Y-114454761D01* +X119032142Y-114407142D01* +X119055952Y-114311904D01* +X119055952Y-114240476D01* +X119032142Y-114145238D01* +X119008333Y-114097619D01* +X118960714Y-114050000D01* +X118889285Y-114026190D01* +X118841666Y-114026190D01* +X118770238Y-114050000D01* +X118746428Y-114073809D01* +X118270238Y-114526190D02* +X118555952Y-114526190D01* +X118413095Y-114526190D02* +X118413095Y-114026190D01* +X118460714Y-114097619D01* +X118508333Y-114145238D01* +X118555952Y-114169047D01* +X118103571Y-114026190D02* +X117794047Y-114026190D01* +X117960714Y-114216666D01* +X117889285Y-114216666D01* +X117841666Y-114240476D01* +X117817857Y-114264285D01* +X117794047Y-114311904D01* +X117794047Y-114430952D01* +X117817857Y-114478571D01* +X117841666Y-114502380D01* +X117889285Y-114526190D01* +X118032142Y-114526190D01* +X118079761Y-114502380D01* +X118103571Y-114478571D01* +D12* +%TO.C,R9*% +X181601904Y-118531714D02* +X181601904Y-119198380D01* +X181840000Y-118150761D02* +X182078095Y-118865047D01* +X181459047Y-118865047D01* +X181173333Y-118198380D02* +X180506666Y-118198380D01* +X180935238Y-119198380D01* +X179935238Y-118198380D02* +X179840000Y-118198380D01* +X179744761Y-118246000D01* +X179697142Y-118293619D01* +X179649523Y-118388857D01* +X179601904Y-118579333D01* +X179601904Y-118817428D01* +X179649523Y-119007904D01* +X179697142Y-119103142D01* +X179744761Y-119150761D01* +X179840000Y-119198380D01* +X179935238Y-119198380D01* +X180030476Y-119150761D01* +X180078095Y-119103142D01* +X180125714Y-119007904D01* +X180173333Y-118817428D01* +X180173333Y-118579333D01* +X180125714Y-118388857D01* +X180078095Y-118293619D01* +X180030476Y-118246000D01* +X179935238Y-118198380D01* +X178601904Y-119198380D02* +X178935238Y-118722190D01* +X179173333Y-119198380D02* +X179173333Y-118198380D01* +X178792380Y-118198380D01* +X178697142Y-118246000D01* +X178649523Y-118293619D01* +X178601904Y-118388857D01* +X178601904Y-118531714D01* +X178649523Y-118626952D01* +X178697142Y-118674571D01* +X178792380Y-118722190D01* +X179173333Y-118722190D01* +D13* +X180423333Y-120622190D02* +X180590000Y-120384095D01* +X180709047Y-120622190D02* +X180709047Y-120122190D01* +X180518571Y-120122190D01* +X180470952Y-120146000D01* +X180447142Y-120169809D01* +X180423333Y-120217428D01* +X180423333Y-120288857D01* +X180447142Y-120336476D01* +X180470952Y-120360285D01* +X180518571Y-120384095D01* +X180709047Y-120384095D01* +X180185238Y-120622190D02* +X180090000Y-120622190D01* +X180042380Y-120598380D01* +X180018571Y-120574571D01* +X179970952Y-120503142D01* +X179947142Y-120407904D01* +X179947142Y-120217428D01* +X179970952Y-120169809D01* +X179994761Y-120146000D01* +X180042380Y-120122190D01* +X180137619Y-120122190D01* +X180185238Y-120146000D01* +X180209047Y-120169809D01* +X180232857Y-120217428D01* +X180232857Y-120336476D01* +X180209047Y-120384095D01* +X180185238Y-120407904D01* +X180137619Y-120431714D01* +X180042380Y-120431714D01* +X179994761Y-120407904D01* +X179970952Y-120384095D01* +X179947142Y-120336476D01* +D12* +%TO.C,R14*% +X181412619Y-107878809D02* +X181365000Y-107926428D01* +X181317380Y-108021666D01* +X181317380Y-108259761D01* +X181365000Y-108355000D01* +X181412619Y-108402619D01* +X181507857Y-108450238D01* +X181603095Y-108450238D01* +X181745952Y-108402619D01* +X182317380Y-107831190D01* +X182317380Y-108450238D01* +X181317380Y-109355000D02* +X181317380Y-108878809D01* +X181793571Y-108831190D01* +X181745952Y-108878809D01* +X181698333Y-108974047D01* +X181698333Y-109212142D01* +X181745952Y-109307380D01* +X181793571Y-109355000D01* +X181888809Y-109402619D01* +X182126904Y-109402619D01* +X182222142Y-109355000D01* +X182269761Y-109307380D01* +X182317380Y-109212142D01* +X182317380Y-108974047D01* +X182269761Y-108878809D01* +X182222142Y-108831190D01* +X182222142Y-109831190D02* +X182269761Y-109878809D01* +X182317380Y-109831190D01* +X182269761Y-109783571D01* +X182222142Y-109831190D01* +X182317380Y-109831190D01* +X181317380Y-110783571D02* +X181317380Y-110307380D01* +X181793571Y-110259761D01* +X181745952Y-110307380D01* +X181698333Y-110402619D01* +X181698333Y-110640714D01* +X181745952Y-110735952D01* +X181793571Y-110783571D01* +X181888809Y-110831190D01* +X182126904Y-110831190D01* +X182222142Y-110783571D01* +X182269761Y-110735952D01* +X182317380Y-110640714D01* +X182317380Y-110402619D01* +X182269761Y-110307380D01* +X182222142Y-110259761D01* +X182317380Y-111259761D02* +X181317380Y-111259761D01* +X182317380Y-111831190D02* +X181745952Y-111402619D01* +X181317380Y-111831190D02* +X181888809Y-111259761D01* +D13* +X183741190Y-109533571D02* +X183503095Y-109366904D01* +X183741190Y-109247857D02* +X183241190Y-109247857D01* +X183241190Y-109438333D01* +X183265000Y-109485952D01* +X183288809Y-109509761D01* +X183336428Y-109533571D01* +X183407857Y-109533571D01* +X183455476Y-109509761D01* +X183479285Y-109485952D01* +X183503095Y-109438333D01* +X183503095Y-109247857D01* +X183741190Y-110009761D02* +X183741190Y-109724047D01* +X183741190Y-109866904D02* +X183241190Y-109866904D01* +X183312619Y-109819285D01* +X183360238Y-109771666D01* +X183384047Y-109724047D01* +X183407857Y-110438333D02* +X183741190Y-110438333D01* +X183217380Y-110319285D02* +X183574523Y-110200238D01* +X183574523Y-110509761D01* +D12* +%TO.C,R29*% +X160727380Y-113490833D02* +X160727380Y-112919404D01* +X160727380Y-113205119D02* +X159727380Y-113205119D01* +X159870238Y-113109880D01* +X159965476Y-113014642D01* +X160013095Y-112919404D01* +X159727380Y-114109880D02* +X159727380Y-114205119D01* +X159775000Y-114300357D01* +X159822619Y-114347976D01* +X159917857Y-114395595D01* +X160108333Y-114443214D01* +X160346428Y-114443214D01* +X160536904Y-114395595D01* +X160632142Y-114347976D01* +X160679761Y-114300357D01* +X160727380Y-114205119D01* +X160727380Y-114109880D01* +X160679761Y-114014642D01* +X160632142Y-113967023D01* +X160536904Y-113919404D01* +X160346428Y-113871785D01* +X160108333Y-113871785D01* +X159917857Y-113919404D01* +X159822619Y-113967023D01* +X159775000Y-114014642D01* +X159727380Y-114109880D01* +X159727380Y-115062261D02* +X159727380Y-115157500D01* +X159775000Y-115252738D01* +X159822619Y-115300357D01* +X159917857Y-115347976D01* +X160108333Y-115395595D01* +X160346428Y-115395595D01* +X160536904Y-115347976D01* +X160632142Y-115300357D01* +X160679761Y-115252738D01* +X160727380Y-115157500D01* +X160727380Y-115062261D01* +X160679761Y-114967023D01* +X160632142Y-114919404D01* +X160536904Y-114871785D01* +X160346428Y-114824166D01* +X160108333Y-114824166D01* +X159917857Y-114871785D01* +X159822619Y-114919404D01* +X159775000Y-114967023D01* +X159727380Y-115062261D01* +X160727380Y-115824166D02* +X159727380Y-115824166D01* +X160727380Y-116395595D02* +X160155952Y-115967023D01* +X159727380Y-116395595D02* +X160298809Y-115824166D01* +D13* +X162151190Y-114336071D02* +X161913095Y-114169404D01* +X162151190Y-114050357D02* +X161651190Y-114050357D01* +X161651190Y-114240833D01* +X161675000Y-114288452D01* +X161698809Y-114312261D01* +X161746428Y-114336071D01* +X161817857Y-114336071D01* +X161865476Y-114312261D01* +X161889285Y-114288452D01* +X161913095Y-114240833D01* +X161913095Y-114050357D01* +X161698809Y-114526547D02* +X161675000Y-114550357D01* +X161651190Y-114597976D01* +X161651190Y-114717023D01* +X161675000Y-114764642D01* +X161698809Y-114788452D01* +X161746428Y-114812261D01* +X161794047Y-114812261D01* +X161865476Y-114788452D01* +X162151190Y-114502738D01* +X162151190Y-114812261D01* +X162151190Y-115050357D02* +X162151190Y-115145595D01* +X162127380Y-115193214D01* +X162103571Y-115217023D01* +X162032142Y-115264642D01* +X161936904Y-115288452D01* +X161746428Y-115288452D01* +X161698809Y-115264642D01* +X161675000Y-115240833D01* +X161651190Y-115193214D01* +X161651190Y-115097976D01* +X161675000Y-115050357D01* +X161698809Y-115026547D01* +X161746428Y-115002738D01* +X161865476Y-115002738D01* +X161913095Y-115026547D01* +X161936904Y-115050357D01* +X161960714Y-115097976D01* +X161960714Y-115193214D01* +X161936904Y-115240833D01* +X161913095Y-115264642D01* +X161865476Y-115288452D01* +D12* +%TO.C,C10*% +X168232619Y-84778214D02* +X168185000Y-84825833D01* +X168137380Y-84921071D01* +X168137380Y-85159166D01* +X168185000Y-85254404D01* +X168232619Y-85302023D01* +X168327857Y-85349642D01* +X168423095Y-85349642D01* +X168565952Y-85302023D01* +X169137380Y-84730595D01* +X169137380Y-85349642D01* +X168232619Y-85730595D02* +X168185000Y-85778214D01* +X168137380Y-85873452D01* +X168137380Y-86111547D01* +X168185000Y-86206785D01* +X168232619Y-86254404D01* +X168327857Y-86302023D01* +X168423095Y-86302023D01* +X168565952Y-86254404D01* +X169137380Y-85682976D01* +X169137380Y-86302023D01* +X168470714Y-86730595D02* +X169470714Y-86730595D01* +X168994523Y-87206785D02* +X169089761Y-87254404D01* +X169137380Y-87349642D01* +X168994523Y-86730595D02* +X169089761Y-86778214D01* +X169137380Y-86873452D01* +X169137380Y-87063928D01* +X169089761Y-87159166D01* +X168994523Y-87206785D01* +X168470714Y-87206785D01* +X168613571Y-88111547D02* +X168613571Y-87778214D01* +X169137380Y-87778214D02* +X168137380Y-87778214D01* +X168137380Y-88254404D01* +D13* +X167183571Y-86171071D02* +X167207380Y-86147261D01* +X167231190Y-86075833D01* +X167231190Y-86028214D01* +X167207380Y-85956785D01* +X167159761Y-85909166D01* +X167112142Y-85885357D01* +X167016904Y-85861547D01* +X166945476Y-85861547D01* +X166850238Y-85885357D01* +X166802619Y-85909166D01* +X166755000Y-85956785D01* +X166731190Y-86028214D01* +X166731190Y-86075833D01* +X166755000Y-86147261D01* +X166778809Y-86171071D01* +X167231190Y-86647261D02* +X167231190Y-86361547D01* +X167231190Y-86504404D02* +X166731190Y-86504404D01* +X166802619Y-86456785D01* +X166850238Y-86409166D01* +X166874047Y-86361547D01* +X166731190Y-86956785D02* +X166731190Y-87004404D01* +X166755000Y-87052023D01* +X166778809Y-87075833D01* +X166826428Y-87099642D01* +X166921666Y-87123452D01* +X167040714Y-87123452D01* +X167135952Y-87099642D01* +X167183571Y-87075833D01* +X167207380Y-87052023D01* +X167231190Y-87004404D01* +X167231190Y-86956785D01* +X167207380Y-86909166D01* +X167183571Y-86885357D01* +X167135952Y-86861547D01* +X167040714Y-86837738D01* +X166921666Y-86837738D01* +X166826428Y-86861547D01* +X166778809Y-86885357D01* +X166755000Y-86909166D01* +X166731190Y-86956785D01* +D12* +%TO.C,R26*% +X148662380Y-121229523D02* +X148662380Y-120658095D01* +X148662380Y-120943809D02* +X147662380Y-120943809D01* +X147805238Y-120848571D01* +X147900476Y-120753333D01* +X147948095Y-120658095D01* +X147662380Y-121848571D02* +X147662380Y-121943809D01* +X147710000Y-122039047D01* +X147757619Y-122086666D01* +X147852857Y-122134285D01* +X148043333Y-122181904D01* +X148281428Y-122181904D01* +X148471904Y-122134285D01* +X148567142Y-122086666D01* +X148614761Y-122039047D01* +X148662380Y-121943809D01* +X148662380Y-121848571D01* +X148614761Y-121753333D01* +X148567142Y-121705714D01* +X148471904Y-121658095D01* +X148281428Y-121610476D01* +X148043333Y-121610476D01* +X147852857Y-121658095D01* +X147757619Y-121705714D01* +X147710000Y-121753333D01* +X147662380Y-121848571D01* +X148662380Y-122610476D02* +X147662380Y-122610476D01* +X148662380Y-123181904D02* +X148090952Y-122753333D01* +X147662380Y-123181904D02* +X148233809Y-122610476D01* +D13* +X150086190Y-121598571D02* +X149848095Y-121431904D01* +X150086190Y-121312857D02* +X149586190Y-121312857D01* +X149586190Y-121503333D01* +X149610000Y-121550952D01* +X149633809Y-121574761D01* +X149681428Y-121598571D01* +X149752857Y-121598571D01* +X149800476Y-121574761D01* +X149824285Y-121550952D01* +X149848095Y-121503333D01* +X149848095Y-121312857D01* +X149633809Y-121789047D02* +X149610000Y-121812857D01* +X149586190Y-121860476D01* +X149586190Y-121979523D01* +X149610000Y-122027142D01* +X149633809Y-122050952D01* +X149681428Y-122074761D01* +X149729047Y-122074761D01* +X149800476Y-122050952D01* +X150086190Y-121765238D01* +X150086190Y-122074761D01* +X149586190Y-122503333D02* +X149586190Y-122408095D01* +X149610000Y-122360476D01* +X149633809Y-122336666D01* +X149705238Y-122289047D01* +X149800476Y-122265238D01* +X149990952Y-122265238D01* +X150038571Y-122289047D01* +X150062380Y-122312857D01* +X150086190Y-122360476D01* +X150086190Y-122455714D01* +X150062380Y-122503333D01* +X150038571Y-122527142D01* +X149990952Y-122550952D01* +X149871904Y-122550952D01* +X149824285Y-122527142D01* +X149800476Y-122503333D01* +X149776666Y-122455714D01* +X149776666Y-122360476D01* +X149800476Y-122312857D01* +X149824285Y-122289047D01* +X149871904Y-122265238D01* +D12* +%TO.C,R28*% +X166567380Y-113490833D02* +X166567380Y-112919404D01* +X166567380Y-113205119D02* +X165567380Y-113205119D01* +X165710238Y-113109880D01* +X165805476Y-113014642D01* +X165853095Y-112919404D01* +X165567380Y-114109880D02* +X165567380Y-114205119D01* +X165615000Y-114300357D01* +X165662619Y-114347976D01* +X165757857Y-114395595D01* +X165948333Y-114443214D01* +X166186428Y-114443214D01* +X166376904Y-114395595D01* +X166472142Y-114347976D01* +X166519761Y-114300357D01* +X166567380Y-114205119D01* +X166567380Y-114109880D01* +X166519761Y-114014642D01* +X166472142Y-113967023D01* +X166376904Y-113919404D01* +X166186428Y-113871785D01* +X165948333Y-113871785D01* +X165757857Y-113919404D01* +X165662619Y-113967023D01* +X165615000Y-114014642D01* +X165567380Y-114109880D01* +X165567380Y-115062261D02* +X165567380Y-115157500D01* +X165615000Y-115252738D01* +X165662619Y-115300357D01* +X165757857Y-115347976D01* +X165948333Y-115395595D01* +X166186428Y-115395595D01* +X166376904Y-115347976D01* +X166472142Y-115300357D01* +X166519761Y-115252738D01* +X166567380Y-115157500D01* +X166567380Y-115062261D01* +X166519761Y-114967023D01* +X166472142Y-114919404D01* +X166376904Y-114871785D01* +X166186428Y-114824166D01* +X165948333Y-114824166D01* +X165757857Y-114871785D01* +X165662619Y-114919404D01* +X165615000Y-114967023D01* +X165567380Y-115062261D01* +X166567380Y-115824166D02* +X165567380Y-115824166D01* +X166567380Y-116395595D02* +X165995952Y-115967023D01* +X165567380Y-116395595D02* +X166138809Y-115824166D01* +D13* +X164691190Y-114336071D02* +X164453095Y-114169404D01* +X164691190Y-114050357D02* +X164191190Y-114050357D01* +X164191190Y-114240833D01* +X164215000Y-114288452D01* +X164238809Y-114312261D01* +X164286428Y-114336071D01* +X164357857Y-114336071D01* +X164405476Y-114312261D01* +X164429285Y-114288452D01* +X164453095Y-114240833D01* +X164453095Y-114050357D01* +X164238809Y-114526547D02* +X164215000Y-114550357D01* +X164191190Y-114597976D01* +X164191190Y-114717023D01* +X164215000Y-114764642D01* +X164238809Y-114788452D01* +X164286428Y-114812261D01* +X164334047Y-114812261D01* +X164405476Y-114788452D01* +X164691190Y-114502738D01* +X164691190Y-114812261D01* +X164405476Y-115097976D02* +X164381666Y-115050357D01* +X164357857Y-115026547D01* +X164310238Y-115002738D01* +X164286428Y-115002738D01* +X164238809Y-115026547D01* +X164215000Y-115050357D01* +X164191190Y-115097976D01* +X164191190Y-115193214D01* +X164215000Y-115240833D01* +X164238809Y-115264642D01* +X164286428Y-115288452D01* +X164310238Y-115288452D01* +X164357857Y-115264642D01* +X164381666Y-115240833D01* +X164405476Y-115193214D01* +X164405476Y-115097976D01* +X164429285Y-115050357D01* +X164453095Y-115026547D01* +X164500714Y-115002738D01* +X164595952Y-115002738D01* +X164643571Y-115026547D01* +X164667380Y-115050357D01* +X164691190Y-115097976D01* +X164691190Y-115193214D01* +X164667380Y-115240833D01* +X164643571Y-115264642D01* +X164595952Y-115288452D01* +X164500714Y-115288452D01* +X164453095Y-115264642D01* +X164429285Y-115240833D01* +X164405476Y-115193214D01* +D12* +%TO.C,R8*% +X182714380Y-88130095D02* +X182714380Y-87653904D01* +X183190571Y-87606285D01* +X183142952Y-87653904D01* +X183095333Y-87749142D01* +X183095333Y-87987238D01* +X183142952Y-88082476D01* +X183190571Y-88130095D01* +X183285809Y-88177714D01* +X183523904Y-88177714D01* +X183619142Y-88130095D01* +X183666761Y-88082476D01* +X183714380Y-87987238D01* +X183714380Y-87749142D01* +X183666761Y-87653904D01* +X183619142Y-87606285D01* +X183714380Y-88606285D02* +X182714380Y-88606285D01* +X183714380Y-89177714D02* +X183142952Y-88749142D01* +X182714380Y-89177714D02* +X183285809Y-88606285D01* +D13* +X185138190Y-88308666D02* +X184900095Y-88142000D01* +X185138190Y-88022952D02* +X184638190Y-88022952D01* +X184638190Y-88213428D01* +X184662000Y-88261047D01* +X184685809Y-88284857D01* +X184733428Y-88308666D01* +X184804857Y-88308666D01* +X184852476Y-88284857D01* +X184876285Y-88261047D01* +X184900095Y-88213428D01* +X184900095Y-88022952D01* +X184852476Y-88594380D02* +X184828666Y-88546761D01* +X184804857Y-88522952D01* +X184757238Y-88499142D01* +X184733428Y-88499142D01* +X184685809Y-88522952D01* +X184662000Y-88546761D01* +X184638190Y-88594380D01* +X184638190Y-88689619D01* +X184662000Y-88737238D01* +X184685809Y-88761047D01* +X184733428Y-88784857D01* +X184757238Y-88784857D01* +X184804857Y-88761047D01* +X184828666Y-88737238D01* +X184852476Y-88689619D01* +X184852476Y-88594380D01* +X184876285Y-88546761D01* +X184900095Y-88522952D01* +X184947714Y-88499142D01* +X185042952Y-88499142D01* +X185090571Y-88522952D01* +X185114380Y-88546761D01* +X185138190Y-88594380D01* +X185138190Y-88689619D01* +X185114380Y-88737238D01* +X185090571Y-88761047D01* +X185042952Y-88784857D01* +X184947714Y-88784857D01* +X184900095Y-88761047D01* +X184876285Y-88737238D01* +X184852476Y-88689619D01* +D12* +%TO.C,R6*% +X123245476Y-101797380D02* +X123816904Y-101797380D01* +X123531190Y-101797380D02* +X123531190Y-100797380D01* +X123626428Y-100940238D01* +X123721666Y-101035476D01* +X123816904Y-101083095D01* +X122626428Y-100797380D02* +X122531190Y-100797380D01* +X122435952Y-100845000D01* +X122388333Y-100892619D01* +X122340714Y-100987857D01* +X122293095Y-101178333D01* +X122293095Y-101416428D01* +X122340714Y-101606904D01* +X122388333Y-101702142D01* +X122435952Y-101749761D01* +X122531190Y-101797380D01* +X122626428Y-101797380D01* +X122721666Y-101749761D01* +X122769285Y-101702142D01* +X122816904Y-101606904D01* +X122864523Y-101416428D01* +X122864523Y-101178333D01* +X122816904Y-100987857D01* +X122769285Y-100892619D01* +X122721666Y-100845000D01* +X122626428Y-100797380D01* +X121864523Y-101797380D02* +X121864523Y-100797380D01* +X121293095Y-101797380D02* +X121721666Y-101225952D01* +X121293095Y-100797380D02* +X121864523Y-101368809D01* +D13* +X122638333Y-99921190D02* +X122805000Y-99683095D01* +X122924047Y-99921190D02* +X122924047Y-99421190D01* +X122733571Y-99421190D01* +X122685952Y-99445000D01* +X122662142Y-99468809D01* +X122638333Y-99516428D01* +X122638333Y-99587857D01* +X122662142Y-99635476D01* +X122685952Y-99659285D01* +X122733571Y-99683095D01* +X122924047Y-99683095D01* +X122209761Y-99421190D02* +X122305000Y-99421190D01* +X122352619Y-99445000D01* +X122376428Y-99468809D01* +X122424047Y-99540238D01* +X122447857Y-99635476D01* +X122447857Y-99825952D01* +X122424047Y-99873571D01* +X122400238Y-99897380D01* +X122352619Y-99921190D01* +X122257380Y-99921190D01* +X122209761Y-99897380D01* +X122185952Y-99873571D01* +X122162142Y-99825952D01* +X122162142Y-99706904D01* +X122185952Y-99659285D01* +X122209761Y-99635476D01* +X122257380Y-99611666D01* +X122352619Y-99611666D01* +X122400238Y-99635476D01* +X122424047Y-99659285D01* +X122447857Y-99706904D01* +D12* +%TO.C,R25*% +X134057380Y-108529523D02* +X134057380Y-107958095D01* +X134057380Y-108243809D02* +X133057380Y-108243809D01* +X133200238Y-108148571D01* +X133295476Y-108053333D01* +X133343095Y-107958095D01* +X133057380Y-109148571D02* +X133057380Y-109243809D01* +X133105000Y-109339047D01* +X133152619Y-109386666D01* +X133247857Y-109434285D01* +X133438333Y-109481904D01* +X133676428Y-109481904D01* +X133866904Y-109434285D01* +X133962142Y-109386666D01* +X134009761Y-109339047D01* +X134057380Y-109243809D01* +X134057380Y-109148571D01* +X134009761Y-109053333D01* +X133962142Y-109005714D01* +X133866904Y-108958095D01* +X133676428Y-108910476D01* +X133438333Y-108910476D01* +X133247857Y-108958095D01* +X133152619Y-109005714D01* +X133105000Y-109053333D01* +X133057380Y-109148571D01* +X134057380Y-110481904D02* +X133581190Y-110148571D01* +X134057380Y-109910476D02* +X133057380Y-109910476D01* +X133057380Y-110291428D01* +X133105000Y-110386666D01* +X133152619Y-110434285D01* +X133247857Y-110481904D01* +X133390714Y-110481904D01* +X133485952Y-110434285D01* +X133533571Y-110386666D01* +X133581190Y-110291428D01* +X133581190Y-109910476D01* +D13* +X135481190Y-108898571D02* +X135243095Y-108731904D01* +X135481190Y-108612857D02* +X134981190Y-108612857D01* +X134981190Y-108803333D01* +X135005000Y-108850952D01* +X135028809Y-108874761D01* +X135076428Y-108898571D01* +X135147857Y-108898571D01* +X135195476Y-108874761D01* +X135219285Y-108850952D01* +X135243095Y-108803333D01* +X135243095Y-108612857D01* +X135028809Y-109089047D02* +X135005000Y-109112857D01* +X134981190Y-109160476D01* +X134981190Y-109279523D01* +X135005000Y-109327142D01* +X135028809Y-109350952D01* +X135076428Y-109374761D01* +X135124047Y-109374761D01* +X135195476Y-109350952D01* +X135481190Y-109065238D01* +X135481190Y-109374761D01* +X134981190Y-109827142D02* +X134981190Y-109589047D01* +X135219285Y-109565238D01* +X135195476Y-109589047D01* +X135171666Y-109636666D01* +X135171666Y-109755714D01* +X135195476Y-109803333D01* +X135219285Y-109827142D01* +X135266904Y-109850952D01* +X135385952Y-109850952D01* +X135433571Y-109827142D01* +X135457380Y-109803333D01* +X135481190Y-109755714D01* +X135481190Y-109636666D01* +X135457380Y-109589047D01* +X135433571Y-109565238D01* +D12* +%TO.C,R27*% +X165807380Y-113490833D02* +X165807380Y-112919404D01* +X165807380Y-113205119D02* +X164807380Y-113205119D01* +X164950238Y-113109880D01* +X165045476Y-113014642D01* +X165093095Y-112919404D01* +X164807380Y-114109880D02* +X164807380Y-114205119D01* +X164855000Y-114300357D01* +X164902619Y-114347976D01* +X164997857Y-114395595D01* +X165188333Y-114443214D01* +X165426428Y-114443214D01* +X165616904Y-114395595D01* +X165712142Y-114347976D01* +X165759761Y-114300357D01* +X165807380Y-114205119D01* +X165807380Y-114109880D01* +X165759761Y-114014642D01* +X165712142Y-113967023D01* +X165616904Y-113919404D01* +X165426428Y-113871785D01* +X165188333Y-113871785D01* +X164997857Y-113919404D01* +X164902619Y-113967023D01* +X164855000Y-114014642D01* +X164807380Y-114109880D01* +X164807380Y-115062261D02* +X164807380Y-115157500D01* +X164855000Y-115252738D01* +X164902619Y-115300357D01* +X164997857Y-115347976D01* +X165188333Y-115395595D01* +X165426428Y-115395595D01* +X165616904Y-115347976D01* +X165712142Y-115300357D01* +X165759761Y-115252738D01* +X165807380Y-115157500D01* +X165807380Y-115062261D01* +X165759761Y-114967023D01* +X165712142Y-114919404D01* +X165616904Y-114871785D01* +X165426428Y-114824166D01* +X165188333Y-114824166D01* +X164997857Y-114871785D01* +X164902619Y-114919404D01* +X164855000Y-114967023D01* +X164807380Y-115062261D01* +X165807380Y-115824166D02* +X164807380Y-115824166D01* +X165807380Y-116395595D02* +X165235952Y-115967023D01* +X164807380Y-116395595D02* +X165378809Y-115824166D01* +D13* +X167231190Y-114336071D02* +X166993095Y-114169404D01* +X167231190Y-114050357D02* +X166731190Y-114050357D01* +X166731190Y-114240833D01* +X166755000Y-114288452D01* +X166778809Y-114312261D01* +X166826428Y-114336071D01* +X166897857Y-114336071D01* +X166945476Y-114312261D01* +X166969285Y-114288452D01* +X166993095Y-114240833D01* +X166993095Y-114050357D01* +X166778809Y-114526547D02* +X166755000Y-114550357D01* +X166731190Y-114597976D01* +X166731190Y-114717023D01* +X166755000Y-114764642D01* +X166778809Y-114788452D01* +X166826428Y-114812261D01* +X166874047Y-114812261D01* +X166945476Y-114788452D01* +X167231190Y-114502738D01* +X167231190Y-114812261D01* +X166731190Y-114978928D02* +X166731190Y-115312261D01* +X167231190Y-115097976D01* +D12* +%TO.C,C14*% +X131182857Y-91635714D02* +X131182857Y-92302380D01* +X131420952Y-91254761D02* +X131659047Y-91969047D01* +X131040000Y-91969047D01* +X130754285Y-91302380D02* +X130087619Y-91302380D01* +X130516190Y-92302380D01* +X129516190Y-91302380D02* +X129420952Y-91302380D01* +X129325714Y-91350000D01* +X129278095Y-91397619D01* +X129230476Y-91492857D01* +X129182857Y-91683333D01* +X129182857Y-91921428D01* +X129230476Y-92111904D01* +X129278095Y-92207142D01* +X129325714Y-92254761D01* +X129420952Y-92302380D01* +X129516190Y-92302380D01* +X129611428Y-92254761D01* +X129659047Y-92207142D01* +X129706666Y-92111904D01* +X129754285Y-91921428D01* +X129754285Y-91683333D01* +X129706666Y-91492857D01* +X129659047Y-91397619D01* +X129611428Y-91350000D01* +X129516190Y-91302380D01* +X128754285Y-91635714D02* +X128754285Y-92302380D01* +X128754285Y-91730952D02* +X128706666Y-91683333D01* +X128611428Y-91635714D01* +X128468571Y-91635714D01* +X128373333Y-91683333D01* +X128325714Y-91778571D01* +X128325714Y-92302380D01* +X127516190Y-91778571D02* +X127849523Y-91778571D01* +X127849523Y-92302380D02* +X127849523Y-91302380D01* +X127373333Y-91302380D01* +D13* +X129861428Y-90348571D02* +X129885238Y-90372380D01* +X129956666Y-90396190D01* +X130004285Y-90396190D01* +X130075714Y-90372380D01* +X130123333Y-90324761D01* +X130147142Y-90277142D01* +X130170952Y-90181904D01* +X130170952Y-90110476D01* +X130147142Y-90015238D01* +X130123333Y-89967619D01* +X130075714Y-89920000D01* +X130004285Y-89896190D01* +X129956666Y-89896190D01* +X129885238Y-89920000D01* +X129861428Y-89943809D01* +X129385238Y-90396190D02* +X129670952Y-90396190D01* +X129528095Y-90396190D02* +X129528095Y-89896190D01* +X129575714Y-89967619D01* +X129623333Y-90015238D01* +X129670952Y-90039047D01* +X128956666Y-90062857D02* +X128956666Y-90396190D01* +X129075714Y-89872380D02* +X129194761Y-90229523D01* +X128885238Y-90229523D01* +D12* +%TO.C,R23*% +X123006380Y-119998928D02* +X123006380Y-119427500D01* +X123006380Y-119713214D02* +X122006380Y-119713214D01* +X122149238Y-119617976D01* +X122244476Y-119522738D01* +X122292095Y-119427500D01* +X122911142Y-120427500D02* +X122958761Y-120475119D01* +X123006380Y-120427500D01* +X122958761Y-120379880D01* +X122911142Y-120427500D01* +X123006380Y-120427500D01* +X122006380Y-121379880D02* +X122006380Y-120903690D01* +X122482571Y-120856071D01* +X122434952Y-120903690D01* +X122387333Y-120998928D01* +X122387333Y-121237023D01* +X122434952Y-121332261D01* +X122482571Y-121379880D01* +X122577809Y-121427500D01* +X122815904Y-121427500D01* +X122911142Y-121379880D01* +X122958761Y-121332261D01* +X123006380Y-121237023D01* +X123006380Y-120998928D01* +X122958761Y-120903690D01* +X122911142Y-120856071D01* +X123006380Y-121856071D02* +X122006380Y-121856071D01* +X123006380Y-122427500D02* +X122434952Y-121998928D01* +X122006380Y-122427500D02* +X122577809Y-121856071D01* +D13* +X121130190Y-120606071D02* +X120892095Y-120439404D01* +X121130190Y-120320357D02* +X120630190Y-120320357D01* +X120630190Y-120510833D01* +X120654000Y-120558452D01* +X120677809Y-120582261D01* +X120725428Y-120606071D01* +X120796857Y-120606071D01* +X120844476Y-120582261D01* +X120868285Y-120558452D01* +X120892095Y-120510833D01* +X120892095Y-120320357D01* +X120677809Y-120796547D02* +X120654000Y-120820357D01* +X120630190Y-120867976D01* +X120630190Y-120987023D01* +X120654000Y-121034642D01* +X120677809Y-121058452D01* +X120725428Y-121082261D01* +X120773047Y-121082261D01* +X120844476Y-121058452D01* +X121130190Y-120772738D01* +X121130190Y-121082261D01* +X120630190Y-121248928D02* +X120630190Y-121558452D01* +X120820666Y-121391785D01* +X120820666Y-121463214D01* +X120844476Y-121510833D01* +X120868285Y-121534642D01* +X120915904Y-121558452D01* +X121034952Y-121558452D01* +X121082571Y-121534642D01* +X121106380Y-121510833D01* +X121130190Y-121463214D01* +X121130190Y-121320357D01* +X121106380Y-121272738D01* +X121082571Y-121248928D01* +D12* +%TO.C,R12*% +X178872619Y-107878809D02* +X178825000Y-107926428D01* +X178777380Y-108021666D01* +X178777380Y-108259761D01* +X178825000Y-108355000D01* +X178872619Y-108402619D01* +X178967857Y-108450238D01* +X179063095Y-108450238D01* +X179205952Y-108402619D01* +X179777380Y-107831190D01* +X179777380Y-108450238D01* +X178777380Y-109355000D02* +X178777380Y-108878809D01* +X179253571Y-108831190D01* +X179205952Y-108878809D01* +X179158333Y-108974047D01* +X179158333Y-109212142D01* +X179205952Y-109307380D01* +X179253571Y-109355000D01* +X179348809Y-109402619D01* +X179586904Y-109402619D01* +X179682142Y-109355000D01* +X179729761Y-109307380D01* +X179777380Y-109212142D01* +X179777380Y-108974047D01* +X179729761Y-108878809D01* +X179682142Y-108831190D01* +X179682142Y-109831190D02* +X179729761Y-109878809D01* +X179777380Y-109831190D01* +X179729761Y-109783571D01* +X179682142Y-109831190D01* +X179777380Y-109831190D01* +X178777380Y-110783571D02* +X178777380Y-110307380D01* +X179253571Y-110259761D01* +X179205952Y-110307380D01* +X179158333Y-110402619D01* +X179158333Y-110640714D01* +X179205952Y-110735952D01* +X179253571Y-110783571D01* +X179348809Y-110831190D01* +X179586904Y-110831190D01* +X179682142Y-110783571D01* +X179729761Y-110735952D01* +X179777380Y-110640714D01* +X179777380Y-110402619D01* +X179729761Y-110307380D01* +X179682142Y-110259761D01* +X179777380Y-111259761D02* +X178777380Y-111259761D01* +X179777380Y-111831190D02* +X179205952Y-111402619D01* +X178777380Y-111831190D02* +X179348809Y-111259761D01* +D13* +X181201190Y-109533571D02* +X180963095Y-109366904D01* +X181201190Y-109247857D02* +X180701190Y-109247857D01* +X180701190Y-109438333D01* +X180725000Y-109485952D01* +X180748809Y-109509761D01* +X180796428Y-109533571D01* +X180867857Y-109533571D01* +X180915476Y-109509761D01* +X180939285Y-109485952D01* +X180963095Y-109438333D01* +X180963095Y-109247857D01* +X181201190Y-110009761D02* +X181201190Y-109724047D01* +X181201190Y-109866904D02* +X180701190Y-109866904D01* +X180772619Y-109819285D01* +X180820238Y-109771666D01* +X180844047Y-109724047D01* +X180748809Y-110200238D02* +X180725000Y-110224047D01* +X180701190Y-110271666D01* +X180701190Y-110390714D01* +X180725000Y-110438333D01* +X180748809Y-110462142D01* +X180796428Y-110485952D01* +X180844047Y-110485952D01* +X180915476Y-110462142D01* +X181201190Y-110176428D01* +X181201190Y-110485952D01* +D12* +%TO.C,C15*% +X122565714Y-126942142D02* +X123232380Y-126942142D01* +X122184761Y-126704047D02* +X122899047Y-126465952D01* +X122899047Y-127085000D01* +X122232380Y-127370714D02* +X122232380Y-128037380D01* +X123232380Y-127608809D01* +X122232380Y-128608809D02* +X122232380Y-128704047D01* +X122280000Y-128799285D01* +X122327619Y-128846904D01* +X122422857Y-128894523D01* +X122613333Y-128942142D01* +X122851428Y-128942142D01* +X123041904Y-128894523D01* +X123137142Y-128846904D01* +X123184761Y-128799285D01* +X123232380Y-128704047D01* +X123232380Y-128608809D01* +X123184761Y-128513571D01* +X123137142Y-128465952D01* +X123041904Y-128418333D01* +X122851428Y-128370714D01* +X122613333Y-128370714D01* +X122422857Y-128418333D01* +X122327619Y-128465952D01* +X122280000Y-128513571D01* +X122232380Y-128608809D01* +X122565714Y-129370714D02* +X123232380Y-129370714D01* +X122660952Y-129370714D02* +X122613333Y-129418333D01* +X122565714Y-129513571D01* +X122565714Y-129656428D01* +X122613333Y-129751666D01* +X122708571Y-129799285D01* +X123232380Y-129799285D01* +X122708571Y-130608809D02* +X122708571Y-130275476D01* +X123232380Y-130275476D02* +X122232380Y-130275476D01* +X122232380Y-130751666D01* +D13* +X124638571Y-128263571D02* +X124662380Y-128239761D01* +X124686190Y-128168333D01* +X124686190Y-128120714D01* +X124662380Y-128049285D01* +X124614761Y-128001666D01* +X124567142Y-127977857D01* +X124471904Y-127954047D01* +X124400476Y-127954047D01* +X124305238Y-127977857D01* +X124257619Y-128001666D01* +X124210000Y-128049285D01* +X124186190Y-128120714D01* +X124186190Y-128168333D01* +X124210000Y-128239761D01* +X124233809Y-128263571D01* +X124686190Y-128739761D02* +X124686190Y-128454047D01* +X124686190Y-128596904D02* +X124186190Y-128596904D01* +X124257619Y-128549285D01* +X124305238Y-128501666D01* +X124329047Y-128454047D01* +X124186190Y-129192142D02* +X124186190Y-128954047D01* +X124424285Y-128930238D01* +X124400476Y-128954047D01* +X124376666Y-129001666D01* +X124376666Y-129120714D01* +X124400476Y-129168333D01* +X124424285Y-129192142D01* +X124471904Y-129215952D01* +X124590952Y-129215952D01* +X124638571Y-129192142D01* +X124662380Y-129168333D01* +X124686190Y-129120714D01* +X124686190Y-129001666D01* +X124662380Y-128954047D01* +X124638571Y-128930238D01* +D12* +%TO.C,C12*% +X151100666Y-97128380D02* +X151672095Y-97128380D01* +X151386380Y-97128380D02* +X151386380Y-96128380D01* +X151481619Y-96271238D01* +X151576857Y-96366476D01* +X151672095Y-96414095D01* +X150672095Y-96461714D02* +X150672095Y-97461714D01* +X150195904Y-96985523D02* +X150148285Y-97080761D01* +X150053047Y-97128380D01* +X150672095Y-96985523D02* +X150624476Y-97080761D01* +X150529238Y-97128380D01* +X150338761Y-97128380D01* +X150243523Y-97080761D01* +X150195904Y-96985523D01* +X150195904Y-96461714D01* +X149291142Y-96604571D02* +X149624476Y-96604571D01* +X149624476Y-97128380D02* +X149624476Y-96128380D01* +X149148285Y-96128380D01* +D13* +X150755428Y-95174571D02* +X150779238Y-95198380D01* +X150850666Y-95222190D01* +X150898285Y-95222190D01* +X150969714Y-95198380D01* +X151017333Y-95150761D01* +X151041142Y-95103142D01* +X151064952Y-95007904D01* +X151064952Y-94936476D01* +X151041142Y-94841238D01* +X151017333Y-94793619D01* +X150969714Y-94746000D01* +X150898285Y-94722190D01* +X150850666Y-94722190D01* +X150779238Y-94746000D01* +X150755428Y-94769809D01* +X150279238Y-95222190D02* +X150564952Y-95222190D01* +X150422095Y-95222190D02* +X150422095Y-94722190D01* +X150469714Y-94793619D01* +X150517333Y-94841238D01* +X150564952Y-94865047D01* +X150088761Y-94769809D02* +X150064952Y-94746000D01* +X150017333Y-94722190D01* +X149898285Y-94722190D01* +X149850666Y-94746000D01* +X149826857Y-94769809D01* +X149803047Y-94817428D01* +X149803047Y-94865047D01* +X149826857Y-94936476D01* +X150112571Y-95222190D01* +X149803047Y-95222190D01* +D12* +%TO.C,C1*% +X113072380Y-100528571D02* +X113072380Y-99957142D01* +X113072380Y-100242857D02* +X112072380Y-100242857D01* +X112215238Y-100147619D01* +X112310476Y-100052380D01* +X112358095Y-99957142D01* +X112072380Y-101147619D02* +X112072380Y-101242857D01* +X112120000Y-101338095D01* +X112167619Y-101385714D01* +X112262857Y-101433333D01* +X112453333Y-101480952D01* +X112691428Y-101480952D01* +X112881904Y-101433333D01* +X112977142Y-101385714D01* +X113024761Y-101338095D01* +X113072380Y-101242857D01* +X113072380Y-101147619D01* +X113024761Y-101052380D01* +X112977142Y-101004761D01* +X112881904Y-100957142D01* +X112691428Y-100909523D01* +X112453333Y-100909523D01* +X112262857Y-100957142D01* +X112167619Y-101004761D01* +X112120000Y-101052380D01* +X112072380Y-101147619D01* +X112405714Y-101909523D02* +X113072380Y-101909523D01* +X112500952Y-101909523D02* +X112453333Y-101957142D01* +X112405714Y-102052380D01* +X112405714Y-102195238D01* +X112453333Y-102290476D01* +X112548571Y-102338095D01* +X113072380Y-102338095D01* +X112548571Y-103147619D02* +X112548571Y-102814285D01* +X113072380Y-102814285D02* +X112072380Y-102814285D01* +X112072380Y-103290476D01* +D13* +X114478571Y-101516666D02* +X114502380Y-101492857D01* +X114526190Y-101421428D01* +X114526190Y-101373809D01* +X114502380Y-101302380D01* +X114454761Y-101254761D01* +X114407142Y-101230952D01* +X114311904Y-101207142D01* +X114240476Y-101207142D01* +X114145238Y-101230952D01* +X114097619Y-101254761D01* +X114050000Y-101302380D01* +X114026190Y-101373809D01* +X114026190Y-101421428D01* +X114050000Y-101492857D01* +X114073809Y-101516666D01* +X114526190Y-101992857D02* +X114526190Y-101707142D01* +X114526190Y-101850000D02* +X114026190Y-101850000D01* +X114097619Y-101802380D01* +X114145238Y-101754761D01* +X114169047Y-101707142D01* +D12* +%TO.C,Q1*% +X134730714Y-103917380D02* +X134730714Y-102917380D01* +X134349761Y-102917380D01* +X134254523Y-102965000D01* +X134206904Y-103012619D01* +X134159285Y-103107857D01* +X134159285Y-103250714D01* +X134206904Y-103345952D01* +X134254523Y-103393571D01* +X134349761Y-103441190D01* +X134730714Y-103441190D01* +X133730714Y-103917380D02* +X133730714Y-102917380D01* +X133397380Y-103631666D01* +X133064047Y-102917380D01* +X133064047Y-103917380D01* +X132587857Y-103917380D02* +X132587857Y-102917380D01* +X132016428Y-103917380D01* +X132016428Y-102917380D01* +X131064047Y-102917380D02* +X131540238Y-102917380D01* +X131587857Y-103393571D01* +X131540238Y-103345952D01* +X131445000Y-103298333D01* +X131206904Y-103298333D01* +X131111666Y-103345952D01* +X131064047Y-103393571D01* +X131016428Y-103488809D01* +X131016428Y-103726904D01* +X131064047Y-103822142D01* +X131111666Y-103869761D01* +X131206904Y-103917380D01* +X131445000Y-103917380D01* +X131540238Y-103869761D01* +X131587857Y-103822142D01* +X130635476Y-103012619D02* +X130587857Y-102965000D01* +X130492619Y-102917380D01* +X130254523Y-102917380D01* +X130159285Y-102965000D01* +X130111666Y-103012619D01* +X130064047Y-103107857D01* +X130064047Y-103203095D01* +X130111666Y-103345952D01* +X130683095Y-103917380D01* +X130064047Y-103917380D01* +X129730714Y-102917380D02* +X129064047Y-103917380D01* +X129064047Y-102917380D02* +X129730714Y-103917380D01* +X128683095Y-103917380D02* +X128683095Y-102917380D01* +X128302142Y-102917380D01* +X128206904Y-102965000D01* +X128159285Y-103012619D01* +X128111666Y-103107857D01* +X128111666Y-103250714D01* +X128159285Y-103345952D01* +X128206904Y-103393571D01* +X128302142Y-103441190D01* +X128683095Y-103441190D01* +D15* +X131718809Y-100917380D02* +X131695000Y-100869761D01* +X131647380Y-100822142D01* +X131575952Y-100750714D01* +X131552142Y-100703095D01* +X131552142Y-100655476D01* +X131671190Y-100679285D02* +X131647380Y-100631666D01* +X131599761Y-100584047D01* +X131504523Y-100560238D01* +X131337857Y-100560238D01* +X131242619Y-100584047D01* +X131195000Y-100631666D01* +X131171190Y-100679285D01* +X131171190Y-100774523D01* +X131195000Y-100822142D01* +X131242619Y-100869761D01* +X131337857Y-100893571D01* +X131504523Y-100893571D01* +X131599761Y-100869761D01* +X131647380Y-100822142D01* +X131671190Y-100774523D01* +X131671190Y-100679285D01* +X131671190Y-101369761D02* +X131671190Y-101084047D01* +X131671190Y-101226904D02* +X131171190Y-101226904D01* +X131242619Y-101179285D01* +X131290238Y-101131666D01* +X131314047Y-101084047D01* +D12* +%TO.C,U6*% +X171042380Y-95232023D02* +X171042380Y-95803452D01* +X172042380Y-95517738D02* +X171042380Y-95517738D01* +X171947142Y-96708214D02* +X171994761Y-96660595D01* +X172042380Y-96517738D01* +X172042380Y-96422500D01* +X171994761Y-96279642D01* +X171899523Y-96184404D01* +X171804285Y-96136785D01* +X171613809Y-96089166D01* +X171470952Y-96089166D01* +X171280476Y-96136785D01* +X171185238Y-96184404D01* +X171090000Y-96279642D01* +X171042380Y-96422500D01* +X171042380Y-96517738D01* +X171090000Y-96660595D01* +X171137619Y-96708214D01* +X172042380Y-97660595D02* +X172042380Y-97089166D01* +X172042380Y-97374880D02* +X171042380Y-97374880D01* +X171185238Y-97279642D01* +X171280476Y-97184404D01* +X171328095Y-97089166D01* +X172042380Y-98612976D02* +X172042380Y-98041547D01* +X172042380Y-98327261D02* +X171042380Y-98327261D01* +X171185238Y-98232023D01* +X171280476Y-98136785D01* +X171328095Y-98041547D01* +X171470952Y-99184404D02* +X171423333Y-99089166D01* +X171375714Y-99041547D01* +X171280476Y-98993928D01* +X171232857Y-98993928D01* +X171137619Y-99041547D01* +X171090000Y-99089166D01* +X171042380Y-99184404D01* +X171042380Y-99374880D01* +X171090000Y-99470119D01* +X171137619Y-99517738D01* +X171232857Y-99565357D01* +X171280476Y-99565357D01* +X171375714Y-99517738D01* +X171423333Y-99470119D01* +X171470952Y-99374880D01* +X171470952Y-99184404D01* +X171518571Y-99089166D01* +X171566190Y-99041547D01* +X171661428Y-98993928D01* +X171851904Y-98993928D01* +X171947142Y-99041547D01* +X171994761Y-99089166D01* +X172042380Y-99184404D01* +X172042380Y-99374880D01* +X171994761Y-99470119D01* +X171947142Y-99517738D01* +X171851904Y-99565357D01* +X171661428Y-99565357D01* +X171566190Y-99517738D01* +X171518571Y-99470119D01* +X171470952Y-99374880D01* +X171042380Y-100422500D02* +X171042380Y-100232023D01* +X171090000Y-100136785D01* +X171137619Y-100089166D01* +X171280476Y-99993928D01* +X171470952Y-99946309D01* +X171851904Y-99946309D01* +X171947142Y-99993928D01* +X171994761Y-100041547D01* +X172042380Y-100136785D01* +X172042380Y-100327261D01* +X171994761Y-100422500D01* +X171947142Y-100470119D01* +X171851904Y-100517738D01* +X171613809Y-100517738D01* +X171518571Y-100470119D01* +X171470952Y-100422500D01* +X171423333Y-100327261D01* +X171423333Y-100136785D01* +X171470952Y-100041547D01* +X171518571Y-99993928D01* +X171613809Y-99946309D01* +D14* +X173770952Y-97617738D02* +X174094761Y-97617738D01* +X174132857Y-97636785D01* +X174151904Y-97655833D01* +X174170952Y-97693928D01* +X174170952Y-97770119D01* +X174151904Y-97808214D01* +X174132857Y-97827261D01* +X174094761Y-97846309D01* +X173770952Y-97846309D01* +X173770952Y-98208214D02* +X173770952Y-98132023D01* +X173790000Y-98093928D01* +X173809047Y-98074880D01* +X173866190Y-98036785D01* +X173942380Y-98017738D01* +X174094761Y-98017738D01* +X174132857Y-98036785D01* +X174151904Y-98055833D01* +X174170952Y-98093928D01* +X174170952Y-98170119D01* +X174151904Y-98208214D01* +X174132857Y-98227261D01* +X174094761Y-98246309D01* +X173999523Y-98246309D01* +X173961428Y-98227261D01* +X173942380Y-98208214D01* +X173923333Y-98170119D01* +X173923333Y-98093928D01* +X173942380Y-98055833D01* +X173961428Y-98036785D01* +X173999523Y-98017738D01* +D12* +%TO.C,C9*% +X179347619Y-104367380D02* +X179919047Y-104367380D01* +X179633333Y-104367380D02* +X179633333Y-103367380D01* +X179728571Y-103510238D01* +X179823809Y-103605476D01* +X179919047Y-103653095D01* +X178728571Y-103367380D02* +X178633333Y-103367380D01* +X178538095Y-103415000D01* +X178490476Y-103462619D01* +X178442857Y-103557857D01* +X178395238Y-103748333D01* +X178395238Y-103986428D01* +X178442857Y-104176904D01* +X178490476Y-104272142D01* +X178538095Y-104319761D01* +X178633333Y-104367380D01* +X178728571Y-104367380D01* +X178823809Y-104319761D01* +X178871428Y-104272142D01* +X178919047Y-104176904D01* +X178966666Y-103986428D01* +X178966666Y-103748333D01* +X178919047Y-103557857D01* +X178871428Y-103462619D01* +X178823809Y-103415000D01* +X178728571Y-103367380D01* +X177776190Y-103367380D02* +X177680952Y-103367380D01* +X177585714Y-103415000D01* +X177538095Y-103462619D01* +X177490476Y-103557857D01* +X177442857Y-103748333D01* +X177442857Y-103986428D01* +X177490476Y-104176904D01* +X177538095Y-104272142D01* +X177585714Y-104319761D01* +X177680952Y-104367380D01* +X177776190Y-104367380D01* +X177871428Y-104319761D01* +X177919047Y-104272142D01* +X177966666Y-104176904D01* +X178014285Y-103986428D01* +X178014285Y-103748333D01* +X177966666Y-103557857D01* +X177919047Y-103462619D01* +X177871428Y-103415000D01* +X177776190Y-103367380D01* +X177014285Y-103700714D02* +X177014285Y-104700714D01* +X177014285Y-103748333D02* +X176919047Y-103700714D01* +X176728571Y-103700714D01* +X176633333Y-103748333D01* +X176585714Y-103795952D01* +X176538095Y-103891190D01* +X176538095Y-104176904D01* +X176585714Y-104272142D01* +X176633333Y-104319761D01* +X176728571Y-104367380D01* +X176919047Y-104367380D01* +X177014285Y-104319761D01* +X175776190Y-103843571D02* +X176109523Y-103843571D01* +X176109523Y-104367380D02* +X176109523Y-103367380D01* +X175633333Y-103367380D01* +D13* +X177883333Y-102413571D02* +X177907142Y-102437380D01* +X177978571Y-102461190D01* +X178026190Y-102461190D01* +X178097619Y-102437380D01* +X178145238Y-102389761D01* +X178169047Y-102342142D01* +X178192857Y-102246904D01* +X178192857Y-102175476D01* +X178169047Y-102080238D01* +X178145238Y-102032619D01* +X178097619Y-101985000D01* +X178026190Y-101961190D01* +X177978571Y-101961190D01* +X177907142Y-101985000D01* +X177883333Y-102008809D01* +X177645238Y-102461190D02* +X177550000Y-102461190D01* +X177502380Y-102437380D01* +X177478571Y-102413571D01* +X177430952Y-102342142D01* +X177407142Y-102246904D01* +X177407142Y-102056428D01* +X177430952Y-102008809D01* +X177454761Y-101985000D01* +X177502380Y-101961190D01* +X177597619Y-101961190D01* +X177645238Y-101985000D01* +X177669047Y-102008809D01* +X177692857Y-102056428D01* +X177692857Y-102175476D01* +X177669047Y-102223095D01* +X177645238Y-102246904D01* +X177597619Y-102270714D01* +X177502380Y-102270714D01* +X177454761Y-102246904D01* +X177430952Y-102223095D01* +X177407142Y-102175476D01* +D12* +%TO.C,C18*% +X158157380Y-113067380D02* +X158157380Y-112495952D01* +X158157380Y-112781666D02* +X157157380Y-112781666D01* +X157300238Y-112686428D01* +X157395476Y-112591190D01* +X157443095Y-112495952D01* +X157157380Y-113686428D02* +X157157380Y-113781666D01* +X157205000Y-113876904D01* +X157252619Y-113924523D01* +X157347857Y-113972142D01* +X157538333Y-114019761D01* +X157776428Y-114019761D01* +X157966904Y-113972142D01* +X158062142Y-113924523D01* +X158109761Y-113876904D01* +X158157380Y-113781666D01* +X158157380Y-113686428D01* +X158109761Y-113591190D01* +X158062142Y-113543571D01* +X157966904Y-113495952D01* +X157776428Y-113448333D01* +X157538333Y-113448333D01* +X157347857Y-113495952D01* +X157252619Y-113543571D01* +X157205000Y-113591190D01* +X157157380Y-113686428D01* +X157157380Y-114638809D02* +X157157380Y-114734047D01* +X157205000Y-114829285D01* +X157252619Y-114876904D01* +X157347857Y-114924523D01* +X157538333Y-114972142D01* +X157776428Y-114972142D01* +X157966904Y-114924523D01* +X158062142Y-114876904D01* +X158109761Y-114829285D01* +X158157380Y-114734047D01* +X158157380Y-114638809D01* +X158109761Y-114543571D01* +X158062142Y-114495952D01* +X157966904Y-114448333D01* +X157776428Y-114400714D01* +X157538333Y-114400714D01* +X157347857Y-114448333D01* +X157252619Y-114495952D01* +X157205000Y-114543571D01* +X157157380Y-114638809D01* +X157490714Y-115400714D02* +X158157380Y-115400714D01* +X157585952Y-115400714D02* +X157538333Y-115448333D01* +X157490714Y-115543571D01* +X157490714Y-115686428D01* +X157538333Y-115781666D01* +X157633571Y-115829285D01* +X158157380Y-115829285D01* +X157633571Y-116638809D02* +X157633571Y-116305476D01* +X158157380Y-116305476D02* +X157157380Y-116305476D01* +X157157380Y-116781666D01* +D13* +X159563571Y-114293571D02* +X159587380Y-114269761D01* +X159611190Y-114198333D01* +X159611190Y-114150714D01* +X159587380Y-114079285D01* +X159539761Y-114031666D01* +X159492142Y-114007857D01* +X159396904Y-113984047D01* +X159325476Y-113984047D01* +X159230238Y-114007857D01* +X159182619Y-114031666D01* +X159135000Y-114079285D01* +X159111190Y-114150714D01* +X159111190Y-114198333D01* +X159135000Y-114269761D01* +X159158809Y-114293571D01* +X159611190Y-114769761D02* +X159611190Y-114484047D01* +X159611190Y-114626904D02* +X159111190Y-114626904D01* +X159182619Y-114579285D01* +X159230238Y-114531666D01* +X159254047Y-114484047D01* +X159325476Y-115055476D02* +X159301666Y-115007857D01* +X159277857Y-114984047D01* +X159230238Y-114960238D01* +X159206428Y-114960238D01* +X159158809Y-114984047D01* +X159135000Y-115007857D01* +X159111190Y-115055476D01* +X159111190Y-115150714D01* +X159135000Y-115198333D01* +X159158809Y-115222142D01* +X159206428Y-115245952D01* +X159230238Y-115245952D01* +X159277857Y-115222142D01* +X159301666Y-115198333D01* +X159325476Y-115150714D01* +X159325476Y-115055476D01* +X159349285Y-115007857D01* +X159373095Y-114984047D01* +X159420714Y-114960238D01* +X159515952Y-114960238D01* +X159563571Y-114984047D01* +X159587380Y-115007857D01* +X159611190Y-115055476D01* +X159611190Y-115150714D01* +X159587380Y-115198333D01* +X159563571Y-115222142D01* +X159515952Y-115245952D01* +X159420714Y-115245952D01* +X159373095Y-115222142D01* +X159349285Y-115198333D01* +X159325476Y-115150714D01* +D12* +%TO.C,R22*% +X120974380Y-119998928D02* +X120974380Y-119427500D01* +X120974380Y-119713214D02* +X119974380Y-119713214D01* +X120117238Y-119617976D01* +X120212476Y-119522738D01* +X120260095Y-119427500D01* +X120879142Y-120427500D02* +X120926761Y-120475119D01* +X120974380Y-120427500D01* +X120926761Y-120379880D01* +X120879142Y-120427500D01* +X120974380Y-120427500D01* +X119974380Y-121379880D02* +X119974380Y-120903690D01* +X120450571Y-120856071D01* +X120402952Y-120903690D01* +X120355333Y-120998928D01* +X120355333Y-121237023D01* +X120402952Y-121332261D01* +X120450571Y-121379880D01* +X120545809Y-121427500D01* +X120783904Y-121427500D01* +X120879142Y-121379880D01* +X120926761Y-121332261D01* +X120974380Y-121237023D01* +X120974380Y-120998928D01* +X120926761Y-120903690D01* +X120879142Y-120856071D01* +X120974380Y-121856071D02* +X119974380Y-121856071D01* +X120974380Y-122427500D02* +X120402952Y-121998928D01* +X119974380Y-122427500D02* +X120545809Y-121856071D01* +D13* +X119098190Y-120606071D02* +X118860095Y-120439404D01* +X119098190Y-120320357D02* +X118598190Y-120320357D01* +X118598190Y-120510833D01* +X118622000Y-120558452D01* +X118645809Y-120582261D01* +X118693428Y-120606071D01* +X118764857Y-120606071D01* +X118812476Y-120582261D01* +X118836285Y-120558452D01* +X118860095Y-120510833D01* +X118860095Y-120320357D01* +X118645809Y-120796547D02* +X118622000Y-120820357D01* +X118598190Y-120867976D01* +X118598190Y-120987023D01* +X118622000Y-121034642D01* +X118645809Y-121058452D01* +X118693428Y-121082261D01* +X118741047Y-121082261D01* +X118812476Y-121058452D01* +X119098190Y-120772738D01* +X119098190Y-121082261D01* +X118645809Y-121272738D02* +X118622000Y-121296547D01* +X118598190Y-121344166D01* +X118598190Y-121463214D01* +X118622000Y-121510833D01* +X118645809Y-121534642D01* +X118693428Y-121558452D01* +X118741047Y-121558452D01* +X118812476Y-121534642D01* +X119098190Y-121248928D01* +X119098190Y-121558452D01* +D12* +%TO.C,U5*% +X176474047Y-90344880D02* +X176474047Y-89344880D01* +X175902619Y-90344880D01* +X175902619Y-89344880D01* +X174855000Y-90249642D02* +X174902619Y-90297261D01* +X175045476Y-90344880D01* +X175140714Y-90344880D01* +X175283571Y-90297261D01* +X175378809Y-90202023D01* +X175426428Y-90106785D01* +X175474047Y-89916309D01* +X175474047Y-89773452D01* +X175426428Y-89582976D01* +X175378809Y-89487738D01* +X175283571Y-89392500D01* +X175140714Y-89344880D01* +X175045476Y-89344880D01* +X174902619Y-89392500D01* +X174855000Y-89440119D01* +X174569285Y-89344880D02* +X174235952Y-90344880D01* +X173902619Y-89344880D01* +X173093095Y-89344880D02* +X173569285Y-89344880D01* +X173616904Y-89821071D01* +X173569285Y-89773452D01* +X173474047Y-89725833D01* +X173235952Y-89725833D01* +X173140714Y-89773452D01* +X173093095Y-89821071D01* +X173045476Y-89916309D01* +X173045476Y-90154404D01* +X173093095Y-90249642D01* +X173140714Y-90297261D01* +X173235952Y-90344880D01* +X173474047Y-90344880D01* +X173569285Y-90297261D01* +X173616904Y-90249642D01* +X172093095Y-90344880D02* +X172664523Y-90344880D01* +X172378809Y-90344880D02* +X172378809Y-89344880D01* +X172474047Y-89487738D01* +X172569285Y-89582976D01* +X172664523Y-89630595D01* +X171759761Y-89344880D02* +X171093095Y-89344880D01* +X171521666Y-90344880D01* +X170188333Y-90344880D02* +X170759761Y-90344880D01* +X170474047Y-90344880D02* +X170474047Y-89344880D01* +X170569285Y-89487738D01* +X170664523Y-89582976D01* +X170759761Y-89630595D01* +X174101666Y-85955833D02* +X174101666Y-86749166D01* +X174055000Y-86842500D01* +X174008333Y-86889166D01* +X173915000Y-86935833D01* +X173728333Y-86935833D01* +X173635000Y-86889166D01* +X173588333Y-86842500D01* +X173541666Y-86749166D01* +X173541666Y-85955833D01* +X172608333Y-85955833D02* +X173075000Y-85955833D01* +X173121666Y-86422500D01* +X173075000Y-86375833D01* +X172981666Y-86329166D01* +X172748333Y-86329166D01* +X172655000Y-86375833D01* +X172608333Y-86422500D01* +X172561666Y-86515833D01* +X172561666Y-86749166D01* +X172608333Y-86842500D01* +X172655000Y-86889166D01* +X172748333Y-86935833D01* +X172981666Y-86935833D01* +X173075000Y-86889166D01* +X173121666Y-86842500D01* +%TO.C,C16*% +X154267619Y-124687380D02* +X154839047Y-124687380D01* +X154553333Y-124687380D02* +X154553333Y-123687380D01* +X154648571Y-123830238D01* +X154743809Y-123925476D01* +X154839047Y-123973095D01* +X153648571Y-123687380D02* +X153553333Y-123687380D01* +X153458095Y-123735000D01* +X153410476Y-123782619D01* +X153362857Y-123877857D01* +X153315238Y-124068333D01* +X153315238Y-124306428D01* +X153362857Y-124496904D01* +X153410476Y-124592142D01* +X153458095Y-124639761D01* +X153553333Y-124687380D01* +X153648571Y-124687380D01* +X153743809Y-124639761D01* +X153791428Y-124592142D01* +X153839047Y-124496904D01* +X153886666Y-124306428D01* +X153886666Y-124068333D01* +X153839047Y-123877857D01* +X153791428Y-123782619D01* +X153743809Y-123735000D01* +X153648571Y-123687380D01* +X152696190Y-123687380D02* +X152600952Y-123687380D01* +X152505714Y-123735000D01* +X152458095Y-123782619D01* +X152410476Y-123877857D01* +X152362857Y-124068333D01* +X152362857Y-124306428D01* +X152410476Y-124496904D01* +X152458095Y-124592142D01* +X152505714Y-124639761D01* +X152600952Y-124687380D01* +X152696190Y-124687380D01* +X152791428Y-124639761D01* +X152839047Y-124592142D01* +X152886666Y-124496904D01* +X152934285Y-124306428D01* +X152934285Y-124068333D01* +X152886666Y-123877857D01* +X152839047Y-123782619D01* +X152791428Y-123735000D01* +X152696190Y-123687380D01* +X151934285Y-124020714D02* +X151934285Y-124687380D01* +X151934285Y-124115952D02* +X151886666Y-124068333D01* +X151791428Y-124020714D01* +X151648571Y-124020714D01* +X151553333Y-124068333D01* +X151505714Y-124163571D01* +X151505714Y-124687380D01* +X150696190Y-124163571D02* +X151029523Y-124163571D01* +X151029523Y-124687380D02* +X151029523Y-123687380D01* +X150553333Y-123687380D01* +D13* +X153041428Y-122733571D02* +X153065238Y-122757380D01* +X153136666Y-122781190D01* +X153184285Y-122781190D01* +X153255714Y-122757380D01* +X153303333Y-122709761D01* +X153327142Y-122662142D01* +X153350952Y-122566904D01* +X153350952Y-122495476D01* +X153327142Y-122400238D01* +X153303333Y-122352619D01* +X153255714Y-122305000D01* +X153184285Y-122281190D01* +X153136666Y-122281190D01* +X153065238Y-122305000D01* +X153041428Y-122328809D01* +X152565238Y-122781190D02* +X152850952Y-122781190D01* +X152708095Y-122781190D02* +X152708095Y-122281190D01* +X152755714Y-122352619D01* +X152803333Y-122400238D01* +X152850952Y-122424047D01* +X152136666Y-122281190D02* +X152231904Y-122281190D01* +X152279523Y-122305000D01* +X152303333Y-122328809D01* +X152350952Y-122400238D01* +X152374761Y-122495476D01* +X152374761Y-122685952D01* +X152350952Y-122733571D01* +X152327142Y-122757380D01* +X152279523Y-122781190D01* +X152184285Y-122781190D01* +X152136666Y-122757380D01* +X152112857Y-122733571D01* +X152089047Y-122685952D01* +X152089047Y-122566904D01* +X152112857Y-122519285D01* +X152136666Y-122495476D01* +X152184285Y-122471666D01* +X152279523Y-122471666D01* +X152327142Y-122495476D01* +X152350952Y-122519285D01* +X152374761Y-122566904D01* +D12* +%TO.C,R4*% +X123721666Y-106877380D02* +X124293095Y-106877380D01* +X124007380Y-106877380D02* +X124007380Y-105877380D01* +X124102619Y-106020238D01* +X124197857Y-106115476D01* +X124293095Y-106163095D01* +X123102619Y-105877380D02* +X123007380Y-105877380D01* +X122912142Y-105925000D01* +X122864523Y-105972619D01* +X122816904Y-106067857D01* +X122769285Y-106258333D01* +X122769285Y-106496428D01* +X122816904Y-106686904D01* +X122864523Y-106782142D01* +X122912142Y-106829761D01* +X123007380Y-106877380D01* +X123102619Y-106877380D01* +X123197857Y-106829761D01* +X123245476Y-106782142D01* +X123293095Y-106686904D01* +X123340714Y-106496428D01* +X123340714Y-106258333D01* +X123293095Y-106067857D01* +X123245476Y-105972619D01* +X123197857Y-105925000D01* +X123102619Y-105877380D01* +X122150238Y-105877380D02* +X122055000Y-105877380D01* +X121959761Y-105925000D01* +X121912142Y-105972619D01* +X121864523Y-106067857D01* +X121816904Y-106258333D01* +X121816904Y-106496428D01* +X121864523Y-106686904D01* +X121912142Y-106782142D01* +X121959761Y-106829761D01* +X122055000Y-106877380D01* +X122150238Y-106877380D01* +X122245476Y-106829761D01* +X122293095Y-106782142D01* +X122340714Y-106686904D01* +X122388333Y-106496428D01* +X122388333Y-106258333D01* +X122340714Y-106067857D01* +X122293095Y-105972619D01* +X122245476Y-105925000D01* +X122150238Y-105877380D01* +X121388333Y-106877380D02* +X121388333Y-105877380D01* +X120816904Y-106877380D02* +X121245476Y-106305952D01* +X120816904Y-105877380D02* +X121388333Y-106448809D01* +D13* +X122638333Y-105001190D02* +X122805000Y-104763095D01* +X122924047Y-105001190D02* +X122924047Y-104501190D01* +X122733571Y-104501190D01* +X122685952Y-104525000D01* +X122662142Y-104548809D01* +X122638333Y-104596428D01* +X122638333Y-104667857D01* +X122662142Y-104715476D01* +X122685952Y-104739285D01* +X122733571Y-104763095D01* +X122924047Y-104763095D01* +X122209761Y-104667857D02* +X122209761Y-105001190D01* +X122328809Y-104477380D02* +X122447857Y-104834523D01* +X122138333Y-104834523D01* +D12* +%TO.C,C2*% +X119591666Y-108447380D02* +X119782142Y-108447380D01* +X119877380Y-108495000D01* +X119925000Y-108542619D01* +X120020238Y-108685476D01* +X120067857Y-108875952D01* +X120067857Y-109256904D01* +X120020238Y-109352142D01* +X119972619Y-109399761D01* +X119877380Y-109447380D01* +X119686904Y-109447380D01* +X119591666Y-109399761D01* +X119544047Y-109352142D01* +X119496428Y-109256904D01* +X119496428Y-109018809D01* +X119544047Y-108923571D01* +X119591666Y-108875952D01* +X119686904Y-108828333D01* +X119877380Y-108828333D01* +X119972619Y-108875952D01* +X120020238Y-108923571D01* +X120067857Y-109018809D01* +X118925000Y-108875952D02* +X119020238Y-108828333D01* +X119067857Y-108780714D01* +X119115476Y-108685476D01* +X119115476Y-108637857D01* +X119067857Y-108542619D01* +X119020238Y-108495000D01* +X118925000Y-108447380D01* +X118734523Y-108447380D01* +X118639285Y-108495000D01* +X118591666Y-108542619D01* +X118544047Y-108637857D01* +X118544047Y-108685476D01* +X118591666Y-108780714D01* +X118639285Y-108828333D01* +X118734523Y-108875952D01* +X118925000Y-108875952D01* +X119020238Y-108923571D01* +X119067857Y-108971190D01* +X119115476Y-109066428D01* +X119115476Y-109256904D01* +X119067857Y-109352142D01* +X119020238Y-109399761D01* +X118925000Y-109447380D01* +X118734523Y-109447380D01* +X118639285Y-109399761D01* +X118591666Y-109352142D01* +X118544047Y-109256904D01* +X118544047Y-109066428D01* +X118591666Y-108971190D01* +X118639285Y-108923571D01* +X118734523Y-108875952D01* +X118115476Y-108780714D02* +X118115476Y-109447380D01* +X118115476Y-108875952D02* +X118067857Y-108828333D01* +X117972619Y-108780714D01* +X117829761Y-108780714D01* +X117734523Y-108828333D01* +X117686904Y-108923571D01* +X117686904Y-109447380D01* +X116877380Y-108923571D02* +X117210714Y-108923571D01* +X117210714Y-109447380D02* +X117210714Y-108447380D01* +X116734523Y-108447380D01* +D13* +X118508333Y-107493571D02* +X118532142Y-107517380D01* +X118603571Y-107541190D01* +X118651190Y-107541190D01* +X118722619Y-107517380D01* +X118770238Y-107469761D01* +X118794047Y-107422142D01* +X118817857Y-107326904D01* +X118817857Y-107255476D01* +X118794047Y-107160238D01* +X118770238Y-107112619D01* +X118722619Y-107065000D01* +X118651190Y-107041190D01* +X118603571Y-107041190D01* +X118532142Y-107065000D01* +X118508333Y-107088809D01* +X118317857Y-107088809D02* +X118294047Y-107065000D01* +X118246428Y-107041190D01* +X118127380Y-107041190D01* +X118079761Y-107065000D01* +X118055952Y-107088809D01* +X118032142Y-107136428D01* +X118032142Y-107184047D01* +X118055952Y-107255476D01* +X118341666Y-107541190D01* +X118032142Y-107541190D01* +D12* +%TO.C,R15*% +X171647380Y-97636785D02* +X171647380Y-97065357D01* +X171647380Y-97351071D02* +X170647380Y-97351071D01* +X170790238Y-97255833D01* +X170885476Y-97160595D01* +X170933095Y-97065357D01* +X171647380Y-98065357D02* +X170647380Y-98065357D01* +X171361666Y-98398690D01* +X170647380Y-98732023D01* +X171647380Y-98732023D01* +D13* +X169771190Y-97601071D02* +X169533095Y-97434404D01* +X169771190Y-97315357D02* +X169271190Y-97315357D01* +X169271190Y-97505833D01* +X169295000Y-97553452D01* +X169318809Y-97577261D01* +X169366428Y-97601071D01* +X169437857Y-97601071D01* +X169485476Y-97577261D01* +X169509285Y-97553452D01* +X169533095Y-97505833D01* +X169533095Y-97315357D01* +X169771190Y-98077261D02* +X169771190Y-97791547D01* +X169771190Y-97934404D02* +X169271190Y-97934404D01* +X169342619Y-97886785D01* +X169390238Y-97839166D01* +X169414047Y-97791547D01* +X169271190Y-98529642D02* +X169271190Y-98291547D01* +X169509285Y-98267738D01* +X169485476Y-98291547D01* +X169461666Y-98339166D01* +X169461666Y-98458214D01* +X169485476Y-98505833D01* +X169509285Y-98529642D01* +X169556904Y-98553452D01* +X169675952Y-98553452D01* +X169723571Y-98529642D01* +X169747380Y-98505833D01* +X169771190Y-98458214D01* +X169771190Y-98339166D01* +X169747380Y-98291547D01* +X169723571Y-98267738D01* +D12* +%TO.C,R20*% +X170711666Y-127707380D02* +X171283095Y-127707380D01* +X170997380Y-127707380D02* +X170997380Y-126707380D01* +X171092619Y-126850238D01* +X171187857Y-126945476D01* +X171283095Y-126993095D01* +X170092619Y-126707380D02* +X169997380Y-126707380D01* +X169902142Y-126755000D01* +X169854523Y-126802619D01* +X169806904Y-126897857D01* +X169759285Y-127088333D01* +X169759285Y-127326428D01* +X169806904Y-127516904D01* +X169854523Y-127612142D01* +X169902142Y-127659761D01* +X169997380Y-127707380D01* +X170092619Y-127707380D01* +X170187857Y-127659761D01* +X170235476Y-127612142D01* +X170283095Y-127516904D01* +X170330714Y-127326428D01* +X170330714Y-127088333D01* +X170283095Y-126897857D01* +X170235476Y-126802619D01* +X170187857Y-126755000D01* +X170092619Y-126707380D01* +X169140238Y-126707380D02* +X169045000Y-126707380D01* +X168949761Y-126755000D01* +X168902142Y-126802619D01* +X168854523Y-126897857D01* +X168806904Y-127088333D01* +X168806904Y-127326428D01* +X168854523Y-127516904D01* +X168902142Y-127612142D01* +X168949761Y-127659761D01* +X169045000Y-127707380D01* +X169140238Y-127707380D01* +X169235476Y-127659761D01* +X169283095Y-127612142D01* +X169330714Y-127516904D01* +X169378333Y-127326428D01* +X169378333Y-127088333D01* +X169330714Y-126897857D01* +X169283095Y-126802619D01* +X169235476Y-126755000D01* +X169140238Y-126707380D01* +X168378333Y-127707380D02* +X168378333Y-126707380D01* +X167806904Y-127707380D02* +X168235476Y-127135952D01* +X167806904Y-126707380D02* +X168378333Y-127278809D01* +D13* +X169866428Y-129131190D02* +X170033095Y-128893095D01* +X170152142Y-129131190D02* +X170152142Y-128631190D01* +X169961666Y-128631190D01* +X169914047Y-128655000D01* +X169890238Y-128678809D01* +X169866428Y-128726428D01* +X169866428Y-128797857D01* +X169890238Y-128845476D01* +X169914047Y-128869285D01* +X169961666Y-128893095D01* +X170152142Y-128893095D01* +X169675952Y-128678809D02* +X169652142Y-128655000D01* +X169604523Y-128631190D01* +X169485476Y-128631190D01* +X169437857Y-128655000D01* +X169414047Y-128678809D01* +X169390238Y-128726428D01* +X169390238Y-128774047D01* +X169414047Y-128845476D01* +X169699761Y-129131190D01* +X169390238Y-129131190D01* +X169080714Y-128631190D02* +X169033095Y-128631190D01* +X168985476Y-128655000D01* +X168961666Y-128678809D01* +X168937857Y-128726428D01* +X168914047Y-128821666D01* +X168914047Y-128940714D01* +X168937857Y-129035952D01* +X168961666Y-129083571D01* +X168985476Y-129107380D01* +X169033095Y-129131190D01* +X169080714Y-129131190D01* +X169128333Y-129107380D01* +X169152142Y-129083571D01* +X169175952Y-129035952D01* +X169199761Y-128940714D01* +X169199761Y-128821666D01* +X169175952Y-128726428D01* +X169152142Y-128678809D01* +X169128333Y-128655000D01* +X169080714Y-128631190D01* +D16* +%TO.C,D1*% +X138795000Y-99965000D02* +X136795000Y-99965000D01* +X136795000Y-101965000D02* +X138795000Y-101965000D01* +X138795000Y-101965000D02* +X138795000Y-99965000D01* +X136795000Y-99965000D02* +X136795000Y-101965000D01* +%TO.C,C17*% +X155585000Y-107045000D02* +X156835000Y-107045000D01* +X156835000Y-107045000D02* +X156835000Y-105045000D01* +X156835000Y-105045000D02* +X155585000Y-105045000D01* +X155585000Y-105045000D02* +X155585000Y-107045000D01* +%TO.C,R10*% +X175752000Y-81625000D02* +X175752000Y-80375000D01* +X173752000Y-81625000D02* +X175752000Y-81625000D01* +X175752000Y-80375000D02* +X173752000Y-80375000D01* +X173752000Y-80375000D02* +X173752000Y-81625000D01* +%TO.C,U2*% +X153995000Y-109530000D02* +X146995000Y-109530000D01* +X147995000Y-116530000D02* +X153995000Y-116530000D01* +X153995000Y-116530000D02* +X153995000Y-109530000D01* +X146995000Y-109530000D02* +X146995000Y-115530000D01* +X146995000Y-115530000D02* +X147995000Y-116530000D01* +%TO.C,C4*% +X185410000Y-116570000D02* +X185410000Y-114570000D01* +X184160000Y-114570000D02* +X184160000Y-116570000D01* +X184160000Y-116570000D02* +X185410000Y-116570000D01* +X185410000Y-114570000D02* +X184160000Y-114570000D01* +%TO.C,R7*% +X173625000Y-112405000D02* +X173625000Y-113655000D01* +X175625000Y-112405000D02* +X173625000Y-112405000D01* +X175625000Y-113655000D02* +X175625000Y-112405000D01* +X173625000Y-113655000D02* +X175625000Y-113655000D01* +%TO.C,C20*% +X142230000Y-112760000D02* +X142230000Y-110760000D01* +X140980000Y-112760000D02* +X142230000Y-112760000D01* +X140980000Y-110760000D02* +X140980000Y-112760000D01* +X142230000Y-110760000D02* +X140980000Y-110760000D01* +%TO.C,R17*% +X168545000Y-122565000D02* +X168545000Y-123815000D01* +X170545000Y-123815000D02* +X170545000Y-122565000D01* +X170545000Y-122565000D02* +X168545000Y-122565000D01* +X168545000Y-123815000D02* +X170545000Y-123815000D01* +%TO.C,C6*% +X172675000Y-101610000D02* +X172675000Y-102860000D01* +X172675000Y-102860000D02* +X174675000Y-102860000D01* +X174675000Y-101610000D02* +X172675000Y-101610000D01* +X174675000Y-102860000D02* +X174675000Y-101610000D01* +%TO.C,R3*% +X177252500Y-121930000D02* +X175252500Y-121930000D01* +X177252500Y-123180000D02* +X177252500Y-121930000D01* +X175252500Y-121930000D02* +X175252500Y-123180000D01* +X175252500Y-123180000D02* +X177252500Y-123180000D01* +%TO.C,C19*% +X144155000Y-120700000D02* +X145405000Y-120700000D01* +X145405000Y-120700000D02* +X145405000Y-118700000D01* +X144155000Y-118700000D02* +X144155000Y-120700000D01* +X145405000Y-118700000D02* +X144155000Y-118700000D01* +%TO.C,U3*% +X118910000Y-103050000D02* +X118910000Y-100150000D01* +X117310000Y-102650000D02* +X117710000Y-103050000D01* +X117710000Y-103050000D02* +X118910000Y-103050000D01* +X117310000Y-100150000D02* +X117310000Y-102650000D01* +X118910000Y-100150000D02* +X117310000Y-100150000D01* +%TO.C,Q2*% +X132270000Y-108120000D02* +X131870000Y-107695000D01* +X130620000Y-107695000D02* +X131870000Y-107695000D01* +X132270000Y-108120000D02* +X132270000Y-110745000D01* +X130620000Y-107695000D02* +X130620000Y-110745000D01* +X130620000Y-110745000D02* +X132270000Y-110745000D01* +%TO.C,R24*% +X130445000Y-113020000D02* +X132445000Y-113020000D01* +X132445000Y-113020000D02* +X132445000Y-111770000D01* +X132445000Y-111770000D02* +X130445000Y-111770000D01* +X130445000Y-111770000D02* +X130445000Y-113020000D01* +%TO.C,R1*% +X130445000Y-103515000D02* +X130445000Y-104765000D01* +X132445000Y-103515000D02* +X130445000Y-103515000D01* +X132445000Y-104765000D02* +X132445000Y-103515000D01* +X130445000Y-104765000D02* +X132445000Y-104765000D01* +%TO.C,C7*% +X184160000Y-129490000D02* +X184160000Y-131490000D01* +X184160000Y-131490000D02* +X185410000Y-131490000D01* +X185410000Y-131490000D02* +X185410000Y-129490000D01* +X185410000Y-129490000D02* +X184160000Y-129490000D01* +%TO.C,R16*% +X116215000Y-121927500D02* +X117465000Y-121927500D01* +X117465000Y-121927500D02* +X117465000Y-119927500D01* +X116215000Y-119927500D02* +X116215000Y-121927500D01* +X117465000Y-119927500D02* +X116215000Y-119927500D01* +%TO.C,R13*% +X179060000Y-110855000D02* +X179060000Y-108855000D01* +X177810000Y-108855000D02* +X177810000Y-110855000D01* +X177810000Y-110855000D02* +X179060000Y-110855000D01* +X179060000Y-108855000D02* +X177810000Y-108855000D01* +%TO.C,U7*% +X148545000Y-97880000D02* +X148545000Y-102780000D01* +X152445000Y-102780000D02* +X152445000Y-98880000D01* +X152445000Y-98880000D02* +X151445000Y-97880000D01* +X148545000Y-102780000D02* +X152445000Y-102780000D01* +X151445000Y-97880000D02* +X148545000Y-97880000D01* +%TO.C,R21*% +X173625000Y-114945000D02* +X173625000Y-116195000D01* +X173625000Y-116195000D02* +X175625000Y-116195000D01* +X175625000Y-116195000D02* +X175625000Y-114945000D01* +X175625000Y-114945000D02* +X173625000Y-114945000D01* +%TO.C,C3*% +X189220000Y-107045000D02* +X189220000Y-105045000D01* +X187970000Y-107045000D02* +X189220000Y-107045000D01* +X189220000Y-105045000D02* +X187970000Y-105045000D01* +X187970000Y-105045000D02* +X187970000Y-107045000D01* +%TO.C,R2*% +X121555000Y-102860000D02* +X123555000Y-102860000D01* +X123555000Y-102860000D02* +X123555000Y-101610000D01* +X123555000Y-101610000D02* +X121555000Y-101610000D01* +X121555000Y-101610000D02* +X121555000Y-102860000D01* +%TO.C,C8*% +X172355000Y-92197500D02* +X174355000Y-92197500D01* +X174355000Y-92197500D02* +X174355000Y-90947500D01* +X174355000Y-90947500D02* +X172355000Y-90947500D01* +X172355000Y-90947500D02* +X172355000Y-92197500D01* +%TO.C,R5*% +X175252500Y-120640000D02* +X177252500Y-120640000D01* +X175252500Y-119390000D02* +X175252500Y-120640000D01* +X177252500Y-120640000D02* +X177252500Y-119390000D01* +X177252500Y-119390000D02* +X175252500Y-119390000D01* +%TO.C,R11*% +X181236500Y-83703000D02* +X179236500Y-83703000D01* +X179236500Y-84953000D02* +X181236500Y-84953000D01* +X179236500Y-83703000D02* +X179236500Y-84953000D01* +X181236500Y-84953000D02* +X181236500Y-83703000D01* +%TO.C,C5*% +X185537000Y-85328000D02* +X185537000Y-83328000D01* +X184287000Y-85328000D02* +X185537000Y-85328000D01* +X185537000Y-83328000D02* +X184287000Y-83328000D01* +X184287000Y-83328000D02* +X184287000Y-85328000D01* +%TO.C,R18*% +X168545000Y-126355000D02* +X170545000Y-126355000D01* +X170545000Y-126355000D02* +X170545000Y-125105000D01* +X170545000Y-125105000D02* +X168545000Y-125105000D01* +X168545000Y-125105000D02* +X168545000Y-126355000D01* +%TO.C,R19*% +X168545000Y-132070000D02* +X170545000Y-132070000D01* +X170545000Y-132070000D02* +X170545000Y-130820000D01* +X168545000Y-130820000D02* +X168545000Y-132070000D01* +X170545000Y-130820000D02* +X168545000Y-130820000D01* +%TO.C,C13*% +X117425000Y-114925000D02* +X119425000Y-114925000D01* +X117425000Y-113675000D02* +X117425000Y-114925000D01* +X119425000Y-114925000D02* +X119425000Y-113675000D01* +X119425000Y-113675000D02* +X117425000Y-113675000D01* +%TO.C,U4*% +X178765200Y-116509800D02* +X178765200Y-113360200D01* +X178765200Y-113360200D02* +X181914800Y-113360200D01* +X181914800Y-114630200D02* +X180644800Y-113360200D01* +X181914800Y-116509800D02* +X178765200Y-116509800D01* +X181914800Y-113360200D02* +X181914800Y-116509800D01* +%TO.C,R9*% +X179340000Y-121021000D02* +X181340000Y-121021000D01* +X181340000Y-121021000D02* +X181340000Y-119771000D01* +X181340000Y-119771000D02* +X179340000Y-119771000D01* +X179340000Y-119771000D02* +X179340000Y-121021000D01* +%TO.C,R14*% +X182890000Y-110855000D02* +X184140000Y-110855000D01* +X184140000Y-110855000D02* +X184140000Y-108855000D01* +X182890000Y-108855000D02* +X182890000Y-110855000D01* +X184140000Y-108855000D02* +X182890000Y-108855000D01* +%TO.C,R29*% +X161300000Y-115657500D02* +X162550000Y-115657500D01* +X161300000Y-113657500D02* +X161300000Y-115657500D01* +X162550000Y-113657500D02* +X161300000Y-113657500D01* +X162550000Y-115657500D02* +X162550000Y-113657500D01* +%TO.C,C10*% +X166380000Y-87492500D02* +X167630000Y-87492500D01* +X166380000Y-85492500D02* +X166380000Y-87492500D01* +X167630000Y-85492500D02* +X166380000Y-85492500D01* +X167630000Y-87492500D02* +X167630000Y-85492500D01* +%TO.C,R26*% +X149235000Y-120920000D02* +X149235000Y-122920000D01* +X150485000Y-120920000D02* +X149235000Y-120920000D01* +X149235000Y-122920000D02* +X150485000Y-122920000D01* +X150485000Y-122920000D02* +X150485000Y-120920000D01* +%TO.C,R28*% +X165090000Y-115657500D02* +X165090000Y-113657500D01* +X163840000Y-113657500D02* +X163840000Y-115657500D01* +X165090000Y-113657500D02* +X163840000Y-113657500D01* +X163840000Y-115657500D02* +X165090000Y-115657500D01* +%TO.C,R8*% +X185537000Y-87392000D02* +X184287000Y-87392000D01* +X184287000Y-89392000D02* +X185537000Y-89392000D01* +X184287000Y-87392000D02* +X184287000Y-89392000D01* +X185537000Y-89392000D02* +X185537000Y-87392000D01* +%TO.C,R6*% +X123555000Y-99070000D02* +X121555000Y-99070000D01* +X121555000Y-99070000D02* +X121555000Y-100320000D01* +X121555000Y-100320000D02* +X123555000Y-100320000D01* +X123555000Y-100320000D02* +X123555000Y-99070000D01* +%TO.C,R25*% +X134630000Y-108220000D02* +X134630000Y-110220000D01* +X134630000Y-110220000D02* +X135880000Y-110220000D01* +X135880000Y-110220000D02* +X135880000Y-108220000D01* +X135880000Y-108220000D02* +X134630000Y-108220000D01* +%TO.C,R27*% +X166380000Y-113657500D02* +X166380000Y-115657500D01* +X167630000Y-113657500D02* +X166380000Y-113657500D01* +X166380000Y-115657500D02* +X167630000Y-115657500D01* +X167630000Y-115657500D02* +X167630000Y-113657500D01* +%TO.C,C14*% +X128540000Y-90795000D02* +X130540000Y-90795000D01* +X130540000Y-89545000D02* +X128540000Y-89545000D01* +X130540000Y-90795000D02* +X130540000Y-89545000D01* +X128540000Y-89545000D02* +X128540000Y-90795000D01* +%TO.C,R23*% +X120279000Y-121927500D02* +X121529000Y-121927500D01* +X120279000Y-119927500D02* +X120279000Y-121927500D01* +X121529000Y-119927500D02* +X120279000Y-119927500D01* +X121529000Y-121927500D02* +X121529000Y-119927500D01* +%TO.C,R12*% +X181600000Y-108855000D02* +X180350000Y-108855000D01* +X180350000Y-110855000D02* +X181600000Y-110855000D01* +X181600000Y-110855000D02* +X181600000Y-108855000D01* +X180350000Y-108855000D02* +X180350000Y-110855000D01* +%TO.C,C15*% +X125085000Y-129585000D02* +X125085000Y-127585000D01* +X123835000Y-127585000D02* +X123835000Y-129585000D01* +X125085000Y-127585000D02* +X123835000Y-127585000D01* +X123835000Y-129585000D02* +X125085000Y-129585000D01* +%TO.C,C12*% +X151434000Y-94371000D02* +X149434000Y-94371000D01* +X151434000Y-95621000D02* +X151434000Y-94371000D01* +X149434000Y-94371000D02* +X149434000Y-95621000D01* +X149434000Y-95621000D02* +X151434000Y-95621000D01* +%TO.C,C1*% +X113675000Y-100600000D02* +X113675000Y-102600000D01* +X114925000Y-100600000D02* +X113675000Y-100600000D01* +X114925000Y-102600000D02* +X114925000Y-100600000D01* +X113675000Y-102600000D02* +X114925000Y-102600000D01* +%TO.C,Q1*% +X130620000Y-99440000D02* +X130620000Y-102490000D01* +X132270000Y-99865000D02* +X131870000Y-99440000D01* +X130620000Y-102490000D02* +X132270000Y-102490000D01* +X132270000Y-99865000D02* +X132270000Y-102490000D01* +X130620000Y-99440000D02* +X131870000Y-99440000D01* +%TO.C,U6*% +X172540000Y-97122500D02* +X172540000Y-98722500D01* +X175440000Y-98322500D02* +X175440000Y-97122500D01* +X175040000Y-98722500D02* +X175440000Y-98322500D01* +X172540000Y-98722500D02* +X175040000Y-98722500D01* +X175440000Y-97122500D02* +X172540000Y-97122500D01* +%TO.C,C9*% +X178800000Y-101610000D02* +X176800000Y-101610000D01* +X178800000Y-102860000D02* +X178800000Y-101610000D01* +X176800000Y-101610000D02* +X176800000Y-102860000D01* +X176800000Y-102860000D02* +X178800000Y-102860000D01* +%TO.C,C11*% +X179060000Y-98790000D02* +X179060000Y-96790000D01* +X177810000Y-96790000D02* +X177810000Y-98790000D01* +X179060000Y-96790000D02* +X177810000Y-96790000D01* +X177810000Y-98790000D02* +X179060000Y-98790000D01* +%TO.C,C18*% +X160010000Y-115615000D02* +X160010000Y-113615000D01* +X158760000Y-113615000D02* +X158760000Y-115615000D01* +X158760000Y-115615000D02* +X160010000Y-115615000D01* +X160010000Y-113615000D02* +X158760000Y-113615000D01* +%TO.C,R22*% +X119497000Y-119927500D02* +X118247000Y-119927500D01* +X118247000Y-121927500D02* +X119497000Y-121927500D01* +X119497000Y-121927500D02* +X119497000Y-119927500D01* +X118247000Y-119927500D02* +X118247000Y-121927500D01* +%TO.C,U5*% +X171405000Y-88942500D02* +X175305000Y-88942500D01* +X174330000Y-84042500D02* +X171405000Y-84042500D01* +X171405000Y-84042500D02* +X171405000Y-88942500D01* +X175305000Y-85017500D02* +X174330000Y-84042500D01* +X175305000Y-88942500D02* +X175305000Y-85017500D01* +%TO.C,C16*% +X153720000Y-121930000D02* +X151720000Y-121930000D01* +X151720000Y-123180000D02* +X153720000Y-123180000D01* +X151720000Y-121930000D02* +X151720000Y-123180000D01* +X153720000Y-123180000D02* +X153720000Y-121930000D01* +%TO.C,R4*% +X121555000Y-105400000D02* +X123555000Y-105400000D01* +X123555000Y-105400000D02* +X123555000Y-104150000D01* +X123555000Y-104150000D02* +X121555000Y-104150000D01* +X121555000Y-104150000D02* +X121555000Y-105400000D01* +%TO.C,C2*% +X119425000Y-106690000D02* +X117425000Y-106690000D01* +X119425000Y-107940000D02* +X119425000Y-106690000D01* +X117425000Y-107940000D02* +X119425000Y-107940000D01* +X117425000Y-106690000D02* +X117425000Y-107940000D01* +%TO.C,R15*% +X170170000Y-98922500D02* +X170170000Y-96922500D01* +X168920000Y-98922500D02* +X170170000Y-98922500D01* +X168920000Y-96922500D02* +X168920000Y-98922500D01* +X170170000Y-96922500D02* +X168920000Y-96922500D01* +%TO.C,R20*% +X170545000Y-129530000D02* +X170545000Y-128280000D01* +X168545000Y-128280000D02* +X168545000Y-129530000D01* +X168545000Y-129530000D02* +X170545000Y-129530000D01* +X170545000Y-128280000D02* +X168545000Y-128280000D01* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Mask.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Mask.gbr new file mode 100644 index 0000000..ca533b1 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Mask.gbr @@ -0,0 +1,685 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Soldermask,Bot*% +%TF.FilePolarity,Negative*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +%AMFreePoly0* +4,1,22,0.550000,-0.750000,0.000000,-0.750000,0.000000,-0.745033,-0.079941,-0.743568,-0.215256,-0.701293,-0.333266,-0.622738,-0.424486,-0.514219,-0.481581,-0.384460,-0.499164,-0.250000,-0.500000,-0.250000,-0.500000,0.250000,-0.499164,0.250000,-0.499963,0.256109,-0.478152,0.396186,-0.417904,0.524511,-0.324060,0.630769,-0.204165,0.706417,-0.067858,0.745374,0.000000,0.744959,0.000000,0.750000, +0.550000,0.750000,0.550000,-0.750000,0.550000,-0.750000,$1*% +%AMFreePoly1* +4,1,20,0.000000,0.744959,0.073905,0.744508,0.209726,0.703889,0.328688,0.626782,0.421226,0.519385,0.479903,0.390333,0.500000,0.250000,0.500000,-0.250000,0.499851,-0.262216,0.476331,-0.402017,0.414519,-0.529596,0.319384,-0.634700,0.198574,-0.708877,0.061801,-0.746166,0.000000,-0.745033,0.000000,-0.750000,-0.550000,-0.750000,-0.550000,0.750000,0.000000,0.750000,0.000000,0.744959, +0.000000,0.744959,$1*% +G04 Aperture macros list end* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12R,0.300000X0.300000*% +%ADD13R,0.250000X0.250000*% +%ADD14R,1.000000X1.500000*% +%ADD15RoundRect,0.250000X0.600000X0.600000X-0.600000X0.600000X-0.600000X-0.600000X0.600000X-0.600000X0*% +%ADD16C,1.700000*% +%ADD17C,3.500000*% +%ADD18O,1.700000X1.100000*% +%ADD19R,1.200000X1.200000*% +%ADD20C,1.200000*% +%ADD21RoundRect,0.250000X0.475000X-0.250000X0.475000X0.250000X-0.475000X0.250000X-0.475000X-0.250000X0*% +%ADD22RoundRect,0.250000X-0.262500X-0.450000X0.262500X-0.450000X0.262500X0.450000X-0.262500X0.450000X0*% +%ADD23RoundRect,0.075000X-0.662500X-0.075000X0.662500X-0.075000X0.662500X0.075000X-0.662500X0.075000X0*% +%ADD24RoundRect,0.075000X-0.075000X-0.662500X0.075000X-0.662500X0.075000X0.662500X-0.075000X0.662500X0*% +%ADD25RoundRect,0.250000X0.262500X0.450000X-0.262500X0.450000X-0.262500X-0.450000X0.262500X-0.450000X0*% +%ADD26RoundRect,0.250000X-0.475000X0.250000X-0.475000X-0.250000X0.475000X-0.250000X0.475000X0.250000X0*% +%ADD27RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% +%ADD28RoundRect,0.125000X-0.537500X-0.125000X0.537500X-0.125000X0.537500X0.125000X-0.537500X0.125000X0*% +%ADD29R,0.700000X0.510000*% +%ADD30RoundRect,0.250000X-0.450000X0.262500X-0.450000X-0.262500X0.450000X-0.262500X0.450000X0.262500X0*% +%ADD31RoundRect,0.250000X0.450000X-0.262500X0.450000X0.262500X-0.450000X0.262500X-0.450000X-0.262500X0*% +%ADD32R,1.100000X0.510000*% +%ADD33FreePoly0,180.000000*% +%ADD34FreePoly1,180.000000*% +%ADD35RoundRect,0.250000X0.250000X0.475000X-0.250000X0.475000X-0.250000X-0.475000X0.250000X-0.475000X0*% +%ADD36R,0.812800X0.254000*% +%ADD37R,0.254000X0.812800*% +%ADD38R,1.752600X1.752600*% +%ADD39RoundRect,0.150000X0.150000X-0.512500X0.150000X0.512500X-0.150000X0.512500X-0.150000X-0.512500X0*% +%ADD40RoundRect,0.150000X0.725000X0.150000X-0.725000X0.150000X-0.725000X-0.150000X0.725000X-0.150000X0*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.C,D1*% +X136945000Y-101615000D03* +X136945000Y-100315000D03* +D13* +X138670000Y-100965000D03* +D14* +X138045000Y-100965000D03* +%TD*% +D15* +%TO.C,J1*% +X131000000Y-87000000D03* +D16* +X128460000Y-87000000D03* +X131000000Y-84460000D03* +X128460000Y-84460000D03* +X131000000Y-81920000D03* +X128460000Y-81920000D03* +%TD*% +D17* +%TO.C,BT1*% +X180500000Y-124250000D03* +X180500000Y-131850000D03* +X180500000Y-80150000D03* +X180500000Y-87750000D03* +%TD*% +D15* +%TO.C,J2*% +X131000000Y-130000000D03* +D16* +X128460000Y-130000000D03* +X131000000Y-127460000D03* +X128460000Y-127460000D03* +X131000000Y-124920000D03* +X128460000Y-124920000D03* +%TD*% +D18* +%TO.C,P1*% +X191835000Y-101710000D03* +X195635000Y-110350000D03* +X195635000Y-101700000D03* +X191835000Y-110350000D03* +%TD*% +D19* +%TO.C,U1*% +X119435000Y-116800000D03* +D20* +X121435000Y-116800000D03* +X123435000Y-116800000D03* +X125435000Y-116800000D03* +X127435000Y-116800000D03* +X129435000Y-116800000D03* +X131435000Y-116800000D03* +X133435000Y-116800000D03* +X135435000Y-116800000D03* +X137435000Y-116800000D03* +X137435000Y-94800000D03* +X135435000Y-94800000D03* +X133435000Y-94800000D03* +X131435000Y-94800000D03* +X129435000Y-94800000D03* +X127435000Y-94800000D03* +X125435000Y-94800000D03* +X123435000Y-94800000D03* +X121435000Y-94800000D03* +X119435000Y-94800000D03* +%TD*% +D21* +%TO.C,C17*% +X156210000Y-106995000D03* +X156210000Y-105095000D03* +%TD*% +D22* +%TO.C,R10*% +X173839500Y-81000000D03* +X175664500Y-81000000D03* +%TD*% +D23* +%TO.C,U2*% +X146332500Y-115780000D03* +X146332500Y-115280000D03* +X146332500Y-114780000D03* +X146332500Y-114280000D03* +X146332500Y-113780000D03* +X146332500Y-113280000D03* +X146332500Y-112780000D03* +X146332500Y-112280000D03* +X146332500Y-111780000D03* +X146332500Y-111280000D03* +X146332500Y-110780000D03* +X146332500Y-110280000D03* +D24* +X147745000Y-108867500D03* +X148245000Y-108867500D03* +X148745000Y-108867500D03* +X149245000Y-108867500D03* +X149745000Y-108867500D03* +X150245000Y-108867500D03* +X150745000Y-108867500D03* +X151245000Y-108867500D03* +X151745000Y-108867500D03* +X152245000Y-108867500D03* +X152745000Y-108867500D03* +X153245000Y-108867500D03* +D23* +X154657500Y-110280000D03* +X154657500Y-110780000D03* +X154657500Y-111280000D03* +X154657500Y-111780000D03* +X154657500Y-112280000D03* +X154657500Y-112780000D03* +X154657500Y-113280000D03* +X154657500Y-113780000D03* +X154657500Y-114280000D03* +X154657500Y-114780000D03* +X154657500Y-115280000D03* +X154657500Y-115780000D03* +D24* +X153245000Y-117192500D03* +X152745000Y-117192500D03* +X152245000Y-117192500D03* +X151745000Y-117192500D03* +X151245000Y-117192500D03* +X150745000Y-117192500D03* +X150245000Y-117192500D03* +X149745000Y-117192500D03* +X149245000Y-117192500D03* +X148745000Y-117192500D03* +X148245000Y-117192500D03* +X147745000Y-117192500D03* +%TD*% +D21* +%TO.C,C4*% +X184785000Y-116520000D03* +X184785000Y-114620000D03* +%TD*% +D25* +%TO.C,R7*% +X175537500Y-113030000D03* +X173712500Y-113030000D03* +%TD*% +D26* +%TO.C,C20*% +X141605000Y-110810000D03* +X141605000Y-112710000D03* +%TD*% +D25* +%TO.C,R17*% +X170457500Y-123190000D03* +X168632500Y-123190000D03* +%TD*% +D27* +%TO.C,C6*% +X172725000Y-102235000D03* +X174625000Y-102235000D03* +%TD*% +D22* +%TO.C,R3*% +X175340000Y-122555000D03* +X177165000Y-122555000D03* +%TD*% +D26* +%TO.C,C19*% +X144780000Y-118750000D03* +X144780000Y-120650000D03* +%TD*% +D28* +%TO.C,U3*% +X116972500Y-102575000D03* +X116972500Y-101925000D03* +X116972500Y-101275000D03* +X116972500Y-100625000D03* +X119247500Y-100625000D03* +X119247500Y-101275000D03* +X119247500Y-101925000D03* +X119247500Y-102575000D03* +%TD*% +D29* +%TO.C,Q2*% +X132605000Y-108270000D03* +X132605000Y-109220000D03* +X132605000Y-110170000D03* +X130285000Y-110170000D03* +X130285000Y-109220000D03* +X130285000Y-108270000D03* +%TD*% +D22* +%TO.C,R24*% +X130532500Y-112395000D03* +X132357500Y-112395000D03* +%TD*% +%TO.C,R1*% +X130532500Y-104140000D03* +X132357500Y-104140000D03* +%TD*% +D21* +%TO.C,C7*% +X184785000Y-131440000D03* +X184785000Y-129540000D03* +%TD*% +D30* +%TO.C,R16*% +X116840000Y-120015000D03* +X116840000Y-121840000D03* +%TD*% +D31* +%TO.C,R13*% +X178435000Y-110767500D03* +X178435000Y-108942500D03* +%TD*% +D32* +%TO.C,U7*% +X153045000Y-98330000D03* +X153045000Y-99330000D03* +X153045000Y-100330000D03* +X153045000Y-101330000D03* +X153045000Y-102330000D03* +X147945000Y-102330000D03* +X147945000Y-101330000D03* +X147945000Y-100330000D03* +X147945000Y-99330000D03* +X147945000Y-98330000D03* +%TD*% +D25* +%TO.C,R21*% +X175537500Y-115570000D03* +X173712500Y-115570000D03* +%TD*% +D26* +%TO.C,C3*% +X188595000Y-105095000D03* +X188595000Y-106995000D03* +%TD*% +D25* +%TO.C,R2*% +X123467500Y-102235000D03* +X121642500Y-102235000D03* +%TD*% +D33* +%TO.C,JP1*% +X151795000Y-126365000D03* +D14* +X150495000Y-126365000D03* +D34* +X149195000Y-126365000D03* +%TD*% +D27* +%TO.C,C8*% +X172405000Y-91572500D03* +X174305000Y-91572500D03* +%TD*% +D22* +%TO.C,R5*% +X175340000Y-120015000D03* +X177165000Y-120015000D03* +%TD*% +D25* +%TO.C,R11*% +X181149000Y-84328000D03* +X179324000Y-84328000D03* +%TD*% +D26* +%TO.C,C5*% +X184912000Y-83378000D03* +X184912000Y-85278000D03* +%TD*% +D22* +%TO.C,R18*% +X168632500Y-125730000D03* +X170457500Y-125730000D03* +%TD*% +D25* +%TO.C,R19*% +X170457500Y-131445000D03* +X168632500Y-131445000D03* +%TD*% +D35* +%TO.C,C13*% +X119375000Y-114300000D03* +X117475000Y-114300000D03* +%TD*% +D36* +%TO.C,U4*% +X181813200Y-114184999D03* +X181813200Y-114685000D03* +X181813200Y-115185000D03* +X181813200Y-115685001D03* +D37* +X181090001Y-116408200D03* +X180590000Y-116408200D03* +X180090000Y-116408200D03* +X179589999Y-116408200D03* +D36* +X178866800Y-115685001D03* +X178866800Y-115185000D03* +X178866800Y-114685000D03* +X178866800Y-114184999D03* +D37* +X179589999Y-113461800D03* +X180090000Y-113461800D03* +X180590000Y-113461800D03* +X181090001Y-113461800D03* +D38* +X180340000Y-114935000D03* +%TD*% +D22* +%TO.C,R9*% +X179427500Y-120396000D03* +X181252500Y-120396000D03* +%TD*% +D31* +%TO.C,R14*% +X183515000Y-110767500D03* +X183515000Y-108942500D03* +%TD*% +%TO.C,R29*% +X161925000Y-115570000D03* +X161925000Y-113745000D03* +%TD*% +D26* +%TO.C,C10*% +X167005000Y-85542500D03* +X167005000Y-87442500D03* +%TD*% +D31* +%TO.C,R26*% +X149860000Y-122832500D03* +X149860000Y-121007500D03* +%TD*% +D30* +%TO.C,R28*% +X164465000Y-113745000D03* +X164465000Y-115570000D03* +%TD*% +D31* +%TO.C,R8*% +X184912000Y-89304500D03* +X184912000Y-87479500D03* +%TD*% +D25* +%TO.C,R6*% +X123467500Y-99695000D03* +X121642500Y-99695000D03* +%TD*% +D31* +%TO.C,R25*% +X135255000Y-110132500D03* +X135255000Y-108307500D03* +%TD*% +%TO.C,R27*% +X167005000Y-115570000D03* +X167005000Y-113745000D03* +%TD*% +D35* +%TO.C,C14*% +X130490000Y-90170000D03* +X128590000Y-90170000D03* +%TD*% +D30* +%TO.C,R23*% +X120904000Y-120015000D03* +X120904000Y-121840000D03* +%TD*% +D31* +%TO.C,R12*% +X180975000Y-110767500D03* +X180975000Y-108942500D03* +%TD*% +D21* +%TO.C,C15*% +X124460000Y-129535000D03* +X124460000Y-127635000D03* +%TD*% +D35* +%TO.C,C12*% +X151384000Y-94996000D03* +X149484000Y-94996000D03* +%TD*% +D21* +%TO.C,C1*% +X114300000Y-100650000D03* +X114300000Y-102550000D03* +%TD*% +D29* +%TO.C,Q1*% +X132605000Y-100015000D03* +X132605000Y-100965000D03* +X132605000Y-101915000D03* +X130285000Y-101915000D03* +X130285000Y-100965000D03* +X130285000Y-100015000D03* +%TD*% +D39* +%TO.C,U6*% +X174940000Y-99060000D03* +X173990000Y-99060000D03* +X173040000Y-99060000D03* +X173040000Y-96785000D03* +X174940000Y-96785000D03* +%TD*% +D35* +%TO.C,C9*% +X178750000Y-102235000D03* +X176850000Y-102235000D03* +%TD*% +D26* +%TO.C,C11*% +X178435000Y-96840000D03* +X178435000Y-98740000D03* +%TD*% +D21* +%TO.C,C18*% +X159385000Y-115565000D03* +X159385000Y-113665000D03* +%TD*% +D30* +%TO.C,R22*% +X118872000Y-120015000D03* +X118872000Y-121840000D03* +%TD*% +D40* +%TO.C,U5*% +X175930000Y-84587500D03* +X175930000Y-85857500D03* +X175930000Y-87127500D03* +X175930000Y-88397500D03* +X170780000Y-88397500D03* +X170780000Y-87127500D03* +X170780000Y-85857500D03* +X170780000Y-84587500D03* +%TD*% +D35* +%TO.C,C16*% +X153670000Y-122555000D03* +X151770000Y-122555000D03* +%TD*% +D25* +%TO.C,R4*% +X123467500Y-104775000D03* +X121642500Y-104775000D03* +%TD*% +D35* +%TO.C,C2*% +X119375000Y-107315000D03* +X117475000Y-107315000D03* +%TD*% +D30* +%TO.C,R15*% +X169545000Y-97010000D03* +X169545000Y-98835000D03* +%TD*% +D22* +%TO.C,R20*% +X168632500Y-128905000D03* +X170457500Y-128905000D03* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Paste.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Paste.gbr new file mode 100644 index 0000000..39e113d --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Paste.gbr @@ -0,0 +1,605 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Paste,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12R,0.300000X0.300000*% +%ADD13R,0.250000X0.250000*% +%ADD14R,1.000000X1.500000*% +%ADD15RoundRect,0.250000X0.475000X-0.250000X0.475000X0.250000X-0.475000X0.250000X-0.475000X-0.250000X0*% +%ADD16RoundRect,0.250000X-0.262500X-0.450000X0.262500X-0.450000X0.262500X0.450000X-0.262500X0.450000X0*% +%ADD17RoundRect,0.075000X-0.662500X-0.075000X0.662500X-0.075000X0.662500X0.075000X-0.662500X0.075000X0*% +%ADD18RoundRect,0.075000X-0.075000X-0.662500X0.075000X-0.662500X0.075000X0.662500X-0.075000X0.662500X0*% +%ADD19RoundRect,0.250000X0.262500X0.450000X-0.262500X0.450000X-0.262500X-0.450000X0.262500X-0.450000X0*% +%ADD20RoundRect,0.250000X-0.475000X0.250000X-0.475000X-0.250000X0.475000X-0.250000X0.475000X0.250000X0*% +%ADD21RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% +%ADD22RoundRect,0.125000X-0.537500X-0.125000X0.537500X-0.125000X0.537500X0.125000X-0.537500X0.125000X0*% +%ADD23R,0.700000X0.510000*% +%ADD24RoundRect,0.250000X-0.450000X0.262500X-0.450000X-0.262500X0.450000X-0.262500X0.450000X0.262500X0*% +%ADD25RoundRect,0.250000X0.450000X-0.262500X0.450000X0.262500X-0.450000X0.262500X-0.450000X-0.262500X0*% +%ADD26R,1.100000X0.510000*% +%ADD27RoundRect,0.250000X0.250000X0.475000X-0.250000X0.475000X-0.250000X-0.475000X0.250000X-0.475000X0*% +%ADD28R,0.812800X0.254000*% +%ADD29R,0.254000X0.812800*% +%ADD30R,1.752600X1.752600*% +%ADD31RoundRect,0.150000X0.150000X-0.512500X0.150000X0.512500X-0.150000X0.512500X-0.150000X-0.512500X0*% +%ADD32RoundRect,0.150000X0.725000X0.150000X-0.725000X0.150000X-0.725000X-0.150000X0.725000X-0.150000X0*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.C,D1*% +X136945000Y-101615000D03* +X136945000Y-100315000D03* +D13* +X138670000Y-100965000D03* +D14* +X138045000Y-100965000D03* +%TD*% +D15* +%TO.C,C17*% +X156210000Y-106995000D03* +X156210000Y-105095000D03* +%TD*% +D16* +%TO.C,R10*% +X173839500Y-81000000D03* +X175664500Y-81000000D03* +%TD*% +D17* +%TO.C,U2*% +X146332500Y-115780000D03* +X146332500Y-115280000D03* +X146332500Y-114780000D03* +X146332500Y-114280000D03* +X146332500Y-113780000D03* +X146332500Y-113280000D03* +X146332500Y-112780000D03* +X146332500Y-112280000D03* +X146332500Y-111780000D03* +X146332500Y-111280000D03* +X146332500Y-110780000D03* +X146332500Y-110280000D03* +D18* +X147745000Y-108867500D03* +X148245000Y-108867500D03* +X148745000Y-108867500D03* +X149245000Y-108867500D03* +X149745000Y-108867500D03* +X150245000Y-108867500D03* +X150745000Y-108867500D03* +X151245000Y-108867500D03* +X151745000Y-108867500D03* +X152245000Y-108867500D03* +X152745000Y-108867500D03* +X153245000Y-108867500D03* +D17* +X154657500Y-110280000D03* +X154657500Y-110780000D03* +X154657500Y-111280000D03* +X154657500Y-111780000D03* +X154657500Y-112280000D03* +X154657500Y-112780000D03* +X154657500Y-113280000D03* +X154657500Y-113780000D03* +X154657500Y-114280000D03* +X154657500Y-114780000D03* +X154657500Y-115280000D03* +X154657500Y-115780000D03* +D18* +X153245000Y-117192500D03* +X152745000Y-117192500D03* +X152245000Y-117192500D03* +X151745000Y-117192500D03* +X151245000Y-117192500D03* +X150745000Y-117192500D03* +X150245000Y-117192500D03* +X149745000Y-117192500D03* +X149245000Y-117192500D03* +X148745000Y-117192500D03* +X148245000Y-117192500D03* +X147745000Y-117192500D03* +%TD*% +D15* +%TO.C,C4*% +X184785000Y-116520000D03* +X184785000Y-114620000D03* +%TD*% +D19* +%TO.C,R7*% +X175537500Y-113030000D03* +X173712500Y-113030000D03* +%TD*% +D20* +%TO.C,C20*% +X141605000Y-110810000D03* +X141605000Y-112710000D03* +%TD*% +D19* +%TO.C,R17*% +X170457500Y-123190000D03* +X168632500Y-123190000D03* +%TD*% +D21* +%TO.C,C6*% +X172725000Y-102235000D03* +X174625000Y-102235000D03* +%TD*% +D16* +%TO.C,R3*% +X175340000Y-122555000D03* +X177165000Y-122555000D03* +%TD*% +D20* +%TO.C,C19*% +X144780000Y-118750000D03* +X144780000Y-120650000D03* +%TD*% +D22* +%TO.C,U3*% +X116972500Y-102575000D03* +X116972500Y-101925000D03* +X116972500Y-101275000D03* +X116972500Y-100625000D03* +X119247500Y-100625000D03* +X119247500Y-101275000D03* +X119247500Y-101925000D03* +X119247500Y-102575000D03* +%TD*% +D23* +%TO.C,Q2*% +X132605000Y-108270000D03* +X132605000Y-109220000D03* +X132605000Y-110170000D03* +X130285000Y-110170000D03* +X130285000Y-109220000D03* +X130285000Y-108270000D03* +%TD*% +D16* +%TO.C,R24*% +X130532500Y-112395000D03* +X132357500Y-112395000D03* +%TD*% +%TO.C,R1*% +X130532500Y-104140000D03* +X132357500Y-104140000D03* +%TD*% +D15* +%TO.C,C7*% +X184785000Y-131440000D03* +X184785000Y-129540000D03* +%TD*% +D24* +%TO.C,R16*% +X116840000Y-120015000D03* +X116840000Y-121840000D03* +%TD*% +D25* +%TO.C,R13*% +X178435000Y-110767500D03* +X178435000Y-108942500D03* +%TD*% +D26* +%TO.C,U7*% +X153045000Y-98330000D03* +X153045000Y-99330000D03* +X153045000Y-100330000D03* +X153045000Y-101330000D03* +X153045000Y-102330000D03* +X147945000Y-102330000D03* +X147945000Y-101330000D03* +X147945000Y-100330000D03* +X147945000Y-99330000D03* +X147945000Y-98330000D03* +%TD*% +D19* +%TO.C,R21*% +X175537500Y-115570000D03* +X173712500Y-115570000D03* +%TD*% +D20* +%TO.C,C3*% +X188595000Y-105095000D03* +X188595000Y-106995000D03* +%TD*% +D19* +%TO.C,R2*% +X123467500Y-102235000D03* +X121642500Y-102235000D03* +%TD*% +D21* +%TO.C,C8*% +X172405000Y-91572500D03* +X174305000Y-91572500D03* +%TD*% +D16* +%TO.C,R5*% +X175340000Y-120015000D03* +X177165000Y-120015000D03* +%TD*% +D19* +%TO.C,R11*% +X181149000Y-84328000D03* +X179324000Y-84328000D03* +%TD*% +D20* +%TO.C,C5*% +X184912000Y-83378000D03* +X184912000Y-85278000D03* +%TD*% +D16* +%TO.C,R18*% +X168632500Y-125730000D03* +X170457500Y-125730000D03* +%TD*% +D19* +%TO.C,R19*% +X170457500Y-131445000D03* +X168632500Y-131445000D03* +%TD*% +D27* +%TO.C,C13*% +X119375000Y-114300000D03* +X117475000Y-114300000D03* +%TD*% +D28* +%TO.C,U4*% +X181813200Y-114184999D03* +X181813200Y-114685000D03* +X181813200Y-115185000D03* +X181813200Y-115685001D03* +D29* +X181090001Y-116408200D03* +X180590000Y-116408200D03* +X180090000Y-116408200D03* +X179589999Y-116408200D03* +D28* +X178866800Y-115685001D03* +X178866800Y-115185000D03* +X178866800Y-114685000D03* +X178866800Y-114184999D03* +D29* +X179589999Y-113461800D03* +X180090000Y-113461800D03* +X180590000Y-113461800D03* +X181090001Y-113461800D03* +D30* +X180340000Y-114935000D03* +%TD*% +D16* +%TO.C,R9*% +X179427500Y-120396000D03* +X181252500Y-120396000D03* +%TD*% +D25* +%TO.C,R14*% +X183515000Y-110767500D03* +X183515000Y-108942500D03* +%TD*% +%TO.C,R29*% +X161925000Y-115570000D03* +X161925000Y-113745000D03* +%TD*% +D20* +%TO.C,C10*% +X167005000Y-85542500D03* +X167005000Y-87442500D03* +%TD*% +D25* +%TO.C,R26*% +X149860000Y-122832500D03* +X149860000Y-121007500D03* +%TD*% +D24* +%TO.C,R28*% +X164465000Y-113745000D03* +X164465000Y-115570000D03* +%TD*% +D25* +%TO.C,R8*% +X184912000Y-89304500D03* +X184912000Y-87479500D03* +%TD*% +D19* +%TO.C,R6*% +X123467500Y-99695000D03* +X121642500Y-99695000D03* +%TD*% +D25* +%TO.C,R25*% +X135255000Y-110132500D03* +X135255000Y-108307500D03* +%TD*% +%TO.C,R27*% +X167005000Y-115570000D03* +X167005000Y-113745000D03* +%TD*% +D27* +%TO.C,C14*% +X130490000Y-90170000D03* +X128590000Y-90170000D03* +%TD*% +D24* +%TO.C,R23*% +X120904000Y-120015000D03* +X120904000Y-121840000D03* +%TD*% +D25* +%TO.C,R12*% +X180975000Y-110767500D03* +X180975000Y-108942500D03* +%TD*% +D15* +%TO.C,C15*% +X124460000Y-129535000D03* +X124460000Y-127635000D03* +%TD*% +D27* +%TO.C,C12*% +X151384000Y-94996000D03* +X149484000Y-94996000D03* +%TD*% +D15* +%TO.C,C1*% +X114300000Y-100650000D03* +X114300000Y-102550000D03* +%TD*% +D23* +%TO.C,Q1*% +X132605000Y-100015000D03* +X132605000Y-100965000D03* +X132605000Y-101915000D03* +X130285000Y-101915000D03* +X130285000Y-100965000D03* +X130285000Y-100015000D03* +%TD*% +D31* +%TO.C,U6*% +X174940000Y-99060000D03* +X173990000Y-99060000D03* +X173040000Y-99060000D03* +X173040000Y-96785000D03* +X174940000Y-96785000D03* +%TD*% +D27* +%TO.C,C9*% +X178750000Y-102235000D03* +X176850000Y-102235000D03* +%TD*% +D20* +%TO.C,C11*% +X178435000Y-96840000D03* +X178435000Y-98740000D03* +%TD*% +D15* +%TO.C,C18*% +X159385000Y-115565000D03* +X159385000Y-113665000D03* +%TD*% +D24* +%TO.C,R22*% +X118872000Y-120015000D03* +X118872000Y-121840000D03* +%TD*% +D32* +%TO.C,U5*% +X175930000Y-84587500D03* +X175930000Y-85857500D03* +X175930000Y-87127500D03* +X175930000Y-88397500D03* +X170780000Y-88397500D03* +X170780000Y-87127500D03* +X170780000Y-85857500D03* +X170780000Y-84587500D03* +%TD*% +D27* +%TO.C,C16*% +X153670000Y-122555000D03* +X151770000Y-122555000D03* +%TD*% +D19* +%TO.C,R4*% +X123467500Y-104775000D03* +X121642500Y-104775000D03* +%TD*% +D27* +%TO.C,C2*% +X119375000Y-107315000D03* +X117475000Y-107315000D03* +%TD*% +D24* +%TO.C,R15*% +X169545000Y-97010000D03* +X169545000Y-98835000D03* +%TD*% +D16* +%TO.C,R20*% +X168632500Y-128905000D03* +X170457500Y-128905000D03* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Silkscreen.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Silkscreen.gbr new file mode 100644 index 0000000..efee736 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Silkscreen.gbr @@ -0,0 +1,2816 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Legend,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%ADD10C,0.150000*% +%TA.AperFunction,Profile*% +%ADD11C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD12C,0.500000*% +%TD*% +%ADD13C,0.120000*% +%ADD14C,0.100000*% +G04 APERTURE END LIST* +D10* +X183388000Y-81788000D02* +X182372000Y-82804000D01* +X183388000Y-79248000D02* +X183388000Y-81788000D01* +D11* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D12* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D11* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D12* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D11* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D12* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D11* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D12* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D11* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D12* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D11* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D10* +X185592404Y-137526380D02* +X185592404Y-136526380D01* +X185354309Y-136526380D01* +X185211452Y-136574000D01* +X185116214Y-136669238D01* +X185068595Y-136764476D01* +X185020976Y-136954952D01* +X185020976Y-137097809D01* +X185068595Y-137288285D01* +X185116214Y-137383523D01* +X185211452Y-137478761D01* +X185354309Y-137526380D01* +X185592404Y-137526380D01* +X184163833Y-136859714D02* +X184163833Y-137526380D01* +X184592404Y-136859714D02* +X184592404Y-137383523D01* +X184544785Y-137478761D01* +X184449547Y-137526380D01* +X184306690Y-137526380D01* +X184211452Y-137478761D01* +X184163833Y-137431142D01* +X183687642Y-137526380D02* +X183687642Y-136859714D01* +X183687642Y-136954952D02* +X183640023Y-136907333D01* +X183544785Y-136859714D01* +X183401928Y-136859714D01* +X183306690Y-136907333D01* +X183259071Y-137002571D01* +X183259071Y-137526380D01* +X183259071Y-137002571D02* +X183211452Y-136907333D01* +X183116214Y-136859714D01* +X182973357Y-136859714D01* +X182878119Y-136907333D01* +X182830500Y-137002571D01* +X182830500Y-137526380D01* +X182354309Y-137526380D02* +X182354309Y-136526380D01* +X182354309Y-136907333D02* +X182259071Y-136859714D01* +X182068595Y-136859714D01* +X181973357Y-136907333D01* +X181925738Y-136954952D01* +X181878119Y-137050190D01* +X181878119Y-137335904D01* +X181925738Y-137431142D01* +X181973357Y-137478761D01* +X182068595Y-137526380D01* +X182259071Y-137526380D01* +X182354309Y-137478761D01* +X181068595Y-137478761D02* +X181163833Y-137526380D01* +X181354309Y-137526380D01* +X181449547Y-137478761D01* +X181497166Y-137383523D01* +X181497166Y-137002571D01* +X181449547Y-136907333D01* +X181354309Y-136859714D01* +X181163833Y-136859714D01* +X181068595Y-136907333D01* +X181020976Y-137002571D01* +X181020976Y-137097809D01* +X181497166Y-137193047D01* +X180592404Y-137526380D02* +X180592404Y-136859714D01* +X180592404Y-137050190D02* +X180544785Y-136954952D01* +X180497166Y-136907333D01* +X180401928Y-136859714D01* +X180306690Y-136859714D01* +X179306690Y-136526380D02* +X178687642Y-136526380D01* +X179020976Y-136907333D01* +X178878119Y-136907333D01* +X178782880Y-136954952D01* +X178735261Y-137002571D01* +X178687642Y-137097809D01* +X178687642Y-137335904D01* +X178735261Y-137431142D01* +X178782880Y-137478761D01* +X178878119Y-137526380D01* +X179163833Y-137526380D01* +X179259071Y-137478761D01* +X179306690Y-137431142D01* +X177640023Y-136526380D02* +X177306690Y-137526380D01* +X176973357Y-136526380D01* +X176116214Y-137526380D02* +X176687642Y-137526380D01* +X176401928Y-137526380D02* +X176401928Y-136526380D01* +X176497166Y-136669238D01* +X176592404Y-136764476D01* +X176687642Y-136812095D01* +X175687642Y-137431142D02* +X175640023Y-137478761D01* +X175687642Y-137526380D01* +X175735261Y-137478761D01* +X175687642Y-137431142D01* +X175687642Y-137526380D01* +X174687642Y-137526380D02* +X175259071Y-137526380D01* +X174973357Y-137526380D02* +X174973357Y-136526380D01* +X175068595Y-136669238D01* +X175163833Y-136764476D01* +X175259071Y-136812095D01* +X185592404Y-139136380D02* +X185592404Y-138136380D01* +X185116214Y-139136380D02* +X185116214Y-138136380D01* +X184544785Y-139136380D01* +X184544785Y-138136380D01* +X184116214Y-139088761D02* +X183973357Y-139136380D01* +X183735261Y-139136380D01* +X183640023Y-139088761D01* +X183592404Y-139041142D01* +X183544785Y-138945904D01* +X183544785Y-138850666D01* +X183592404Y-138755428D01* +X183640023Y-138707809D01* +X183735261Y-138660190D01* +X183925738Y-138612571D01* +X184020976Y-138564952D01* +X184068595Y-138517333D01* +X184116214Y-138422095D01* +X184116214Y-138326857D01* +X184068595Y-138231619D01* +X184020976Y-138184000D01* +X183925738Y-138136380D01* +X183687642Y-138136380D01* +X183544785Y-138184000D01* +X183163833Y-138850666D02* +X182687642Y-138850666D01* +X183259071Y-139136380D02* +X182925738Y-138136380D01* +X182592404Y-139136380D01* +X182259071Y-138755428D02* +X181497166Y-138755428D01* +X180497166Y-138184000D02* +X180592404Y-138136380D01* +X180735261Y-138136380D01* +X180878119Y-138184000D01* +X180973357Y-138279238D01* +X181020976Y-138374476D01* +X181068595Y-138564952D01* +X181068595Y-138707809D01* +X181020976Y-138898285D01* +X180973357Y-138993523D01* +X180878119Y-139088761D01* +X180735261Y-139136380D01* +X180640023Y-139136380D01* +X180497166Y-139088761D01* +X180449547Y-139041142D01* +X180449547Y-138707809D01* +X180640023Y-138707809D01* +X180020976Y-138612571D02* +X179687642Y-138612571D01* +X179544785Y-139136380D02* +X180020976Y-139136380D01* +X180020976Y-138136380D01* +X179544785Y-138136380D01* +X179116214Y-139136380D02* +X179116214Y-138136380D01* +X185401928Y-139746380D02* +X185306690Y-139746380D01* +X185211452Y-139794000D01* +X185163833Y-139841619D01* +X185116214Y-139936857D01* +X185068595Y-140127333D01* +X185068595Y-140365428D01* +X185116214Y-140555904D01* +X185163833Y-140651142D01* +X185211452Y-140698761D01* +X185306690Y-140746380D01* +X185401928Y-140746380D01* +X185497166Y-140698761D01* +X185544785Y-140651142D01* +X185592404Y-140555904D01* +X185640023Y-140365428D01* +X185640023Y-140127333D01* +X185592404Y-139936857D01* +X185544785Y-139841619D01* +X185497166Y-139794000D01* +X185401928Y-139746380D01* +X184592404Y-140746380D02* +X184401928Y-140746380D01* +X184306690Y-140698761D01* +X184259071Y-140651142D01* +X184163833Y-140508285D01* +X184116214Y-140317809D01* +X184116214Y-139936857D01* +X184163833Y-139841619D01* +X184211452Y-139794000D01* +X184306690Y-139746380D01* +X184497166Y-139746380D01* +X184592404Y-139794000D01* +X184640023Y-139841619D01* +X184687642Y-139936857D01* +X184687642Y-140174952D01* +X184640023Y-140270190D01* +X184592404Y-140317809D01* +X184497166Y-140365428D01* +X184306690Y-140365428D01* +X184211452Y-140317809D01* +X184163833Y-140270190D01* +X184116214Y-140174952D01* +X182973357Y-139698761D02* +X183830500Y-140984476D01* +X182687642Y-139841619D02* +X182640023Y-139794000D01* +X182544785Y-139746380D01* +X182306690Y-139746380D01* +X182211452Y-139794000D01* +X182163833Y-139841619D01* +X182116214Y-139936857D01* +X182116214Y-140032095D01* +X182163833Y-140174952D01* +X182735261Y-140746380D01* +X182116214Y-140746380D01* +X181735261Y-139841619D02* +X181687642Y-139794000D01* +X181592404Y-139746380D01* +X181354309Y-139746380D01* +X181259071Y-139794000D01* +X181211452Y-139841619D01* +X181163833Y-139936857D01* +X181163833Y-140032095D01* +X181211452Y-140174952D01* +X181782880Y-140746380D01* +X181163833Y-140746380D01* +%TO.C,D1*% +X138533095Y-98877380D02* +X138533095Y-97877380D01* +X138295000Y-97877380D01* +X138152142Y-97925000D01* +X138056904Y-98020238D01* +X138009285Y-98115476D01* +X137961666Y-98305952D01* +X137961666Y-98448809D01* +X138009285Y-98639285D01* +X138056904Y-98734523D01* +X138152142Y-98829761D01* +X138295000Y-98877380D01* +X138533095Y-98877380D01* +X137009285Y-98877380D02* +X137580714Y-98877380D01* +X137295000Y-98877380D02* +X137295000Y-97877380D01* +X137390238Y-98020238D01* +X137485476Y-98115476D01* +X137580714Y-98163095D01* +%TO.C,C17*% +X158247142Y-105402142D02* +X158294761Y-105354523D01* +X158342380Y-105211666D01* +X158342380Y-105116428D01* +X158294761Y-104973571D01* +X158199523Y-104878333D01* +X158104285Y-104830714D01* +X157913809Y-104783095D01* +X157770952Y-104783095D01* +X157580476Y-104830714D01* +X157485238Y-104878333D01* +X157390000Y-104973571D01* +X157342380Y-105116428D01* +X157342380Y-105211666D01* +X157390000Y-105354523D01* +X157437619Y-105402142D01* +X158342380Y-106354523D02* +X158342380Y-105783095D01* +X158342380Y-106068809D02* +X157342380Y-106068809D01* +X157485238Y-105973571D01* +X157580476Y-105878333D01* +X157628095Y-105783095D01* +X157342380Y-106687857D02* +X157342380Y-107354523D01* +X158342380Y-106925952D01* +%TO.C,R10*% +X173362857Y-79192380D02* +X173696190Y-78716190D01* +X173934285Y-79192380D02* +X173934285Y-78192380D01* +X173553333Y-78192380D01* +X173458095Y-78240000D01* +X173410476Y-78287619D01* +X173362857Y-78382857D01* +X173362857Y-78525714D01* +X173410476Y-78620952D01* +X173458095Y-78668571D01* +X173553333Y-78716190D01* +X173934285Y-78716190D01* +X172410476Y-79192380D02* +X172981904Y-79192380D01* +X172696190Y-79192380D02* +X172696190Y-78192380D01* +X172791428Y-78335238D01* +X172886666Y-78430476D01* +X172981904Y-78478095D01* +X171791428Y-78192380D02* +X171696190Y-78192380D01* +X171600952Y-78240000D01* +X171553333Y-78287619D01* +X171505714Y-78382857D01* +X171458095Y-78573333D01* +X171458095Y-78811428D01* +X171505714Y-79001904D01* +X171553333Y-79097142D01* +X171600952Y-79144761D01* +X171696190Y-79192380D01* +X171791428Y-79192380D01* +X171886666Y-79144761D01* +X171934285Y-79097142D01* +X171981904Y-79001904D01* +X172029523Y-78811428D01* +X172029523Y-78573333D01* +X171981904Y-78382857D01* +X171934285Y-78287619D01* +X171886666Y-78240000D01* +X171791428Y-78192380D01* +%TO.C,U2*% +X155701904Y-118197380D02* +X155701904Y-119006904D01* +X155654285Y-119102142D01* +X155606666Y-119149761D01* +X155511428Y-119197380D01* +X155320952Y-119197380D01* +X155225714Y-119149761D01* +X155178095Y-119102142D01* +X155130476Y-119006904D01* +X155130476Y-118197380D01* +X154701904Y-118292619D02* +X154654285Y-118245000D01* +X154559047Y-118197380D01* +X154320952Y-118197380D01* +X154225714Y-118245000D01* +X154178095Y-118292619D01* +X154130476Y-118387857D01* +X154130476Y-118483095D01* +X154178095Y-118625952D01* +X154749523Y-119197380D01* +X154130476Y-119197380D01* +%TO.C,C4*% +X186822142Y-115403333D02* +X186869761Y-115355714D01* +X186917380Y-115212857D01* +X186917380Y-115117619D01* +X186869761Y-114974761D01* +X186774523Y-114879523D01* +X186679285Y-114831904D01* +X186488809Y-114784285D01* +X186345952Y-114784285D01* +X186155476Y-114831904D01* +X186060238Y-114879523D01* +X185965000Y-114974761D01* +X185917380Y-115117619D01* +X185917380Y-115212857D01* +X185965000Y-115355714D01* +X186012619Y-115403333D01* +X186250714Y-116260476D02* +X186917380Y-116260476D01* +X185869761Y-116022380D02* +X186584047Y-115784285D01* +X186584047Y-116403333D01* +%TO.C,R7*% +X171616666Y-113482380D02* +X171950000Y-113006190D01* +X172188095Y-113482380D02* +X172188095Y-112482380D01* +X171807142Y-112482380D01* +X171711904Y-112530000D01* +X171664285Y-112577619D01* +X171616666Y-112672857D01* +X171616666Y-112815714D01* +X171664285Y-112910952D01* +X171711904Y-112958571D01* +X171807142Y-113006190D01* +X172188095Y-113006190D01* +X171283333Y-112482380D02* +X170616666Y-112482380D01* +X171045238Y-113482380D01* +%TO.C,C20*% +X141962142Y-107942142D02* +X142009761Y-107894523D01* +X142057380Y-107751666D01* +X142057380Y-107656428D01* +X142009761Y-107513571D01* +X141914523Y-107418333D01* +X141819285Y-107370714D01* +X141628809Y-107323095D01* +X141485952Y-107323095D01* +X141295476Y-107370714D01* +X141200238Y-107418333D01* +X141105000Y-107513571D01* +X141057380Y-107656428D01* +X141057380Y-107751666D01* +X141105000Y-107894523D01* +X141152619Y-107942142D01* +X141152619Y-108323095D02* +X141105000Y-108370714D01* +X141057380Y-108465952D01* +X141057380Y-108704047D01* +X141105000Y-108799285D01* +X141152619Y-108846904D01* +X141247857Y-108894523D01* +X141343095Y-108894523D01* +X141485952Y-108846904D01* +X142057380Y-108275476D01* +X142057380Y-108894523D01* +X141057380Y-109513571D02* +X141057380Y-109608809D01* +X141105000Y-109704047D01* +X141152619Y-109751666D01* +X141247857Y-109799285D01* +X141438333Y-109846904D01* +X141676428Y-109846904D01* +X141866904Y-109799285D01* +X141962142Y-109751666D01* +X142009761Y-109704047D01* +X142057380Y-109608809D01* +X142057380Y-109513571D01* +X142009761Y-109418333D01* +X141962142Y-109370714D01* +X141866904Y-109323095D01* +X141676428Y-109275476D01* +X141438333Y-109275476D01* +X141247857Y-109323095D01* +X141152619Y-109370714D01* +X141105000Y-109418333D01* +X141057380Y-109513571D01* +%TO.C,R17*% +X167012857Y-123642380D02* +X167346190Y-123166190D01* +X167584285Y-123642380D02* +X167584285Y-122642380D01* +X167203333Y-122642380D01* +X167108095Y-122690000D01* +X167060476Y-122737619D01* +X167012857Y-122832857D01* +X167012857Y-122975714D01* +X167060476Y-123070952D01* +X167108095Y-123118571D01* +X167203333Y-123166190D01* +X167584285Y-123166190D01* +X166060476Y-123642380D02* +X166631904Y-123642380D01* +X166346190Y-123642380D02* +X166346190Y-122642380D01* +X166441428Y-122785238D01* +X166536666Y-122880476D01* +X166631904Y-122928095D01* +X165727142Y-122642380D02* +X165060476Y-122642380D01* +X165489047Y-123642380D01* +%TO.C,C6*% +X173841666Y-104272142D02* +X173889285Y-104319761D01* +X174032142Y-104367380D01* +X174127380Y-104367380D01* +X174270238Y-104319761D01* +X174365476Y-104224523D01* +X174413095Y-104129285D01* +X174460714Y-103938809D01* +X174460714Y-103795952D01* +X174413095Y-103605476D01* +X174365476Y-103510238D01* +X174270238Y-103415000D01* +X174127380Y-103367380D01* +X174032142Y-103367380D01* +X173889285Y-103415000D01* +X173841666Y-103462619D01* +X172984523Y-103367380D02* +X173175000Y-103367380D01* +X173270238Y-103415000D01* +X173317857Y-103462619D01* +X173413095Y-103605476D01* +X173460714Y-103795952D01* +X173460714Y-104176904D01* +X173413095Y-104272142D01* +X173365476Y-104319761D01* +X173270238Y-104367380D01* +X173079761Y-104367380D01* +X172984523Y-104319761D01* +X172936904Y-104272142D01* +X172889285Y-104176904D01* +X172889285Y-103938809D01* +X172936904Y-103843571D01* +X172984523Y-103795952D01* +X173079761Y-103748333D01* +X173270238Y-103748333D01* +X173365476Y-103795952D01* +X173413095Y-103843571D01* +X173460714Y-103938809D01* +%TO.C,R3*% +X173521666Y-123007380D02* +X173855000Y-122531190D01* +X174093095Y-123007380D02* +X174093095Y-122007380D01* +X173712142Y-122007380D01* +X173616904Y-122055000D01* +X173569285Y-122102619D01* +X173521666Y-122197857D01* +X173521666Y-122340714D01* +X173569285Y-122435952D01* +X173616904Y-122483571D01* +X173712142Y-122531190D01* +X174093095Y-122531190D01* +X173188333Y-122007380D02* +X172569285Y-122007380D01* +X172902619Y-122388333D01* +X172759761Y-122388333D01* +X172664523Y-122435952D01* +X172616904Y-122483571D01* +X172569285Y-122578809D01* +X172569285Y-122816904D01* +X172616904Y-122912142D01* +X172664523Y-122959761D01* +X172759761Y-123007380D01* +X173045476Y-123007380D01* +X173140714Y-122959761D01* +X173188333Y-122912142D01* +%TO.C,C19*% +X143457142Y-119057142D02* +X143504761Y-119009523D01* +X143552380Y-118866666D01* +X143552380Y-118771428D01* +X143504761Y-118628571D01* +X143409523Y-118533333D01* +X143314285Y-118485714D01* +X143123809Y-118438095D01* +X142980952Y-118438095D01* +X142790476Y-118485714D01* +X142695238Y-118533333D01* +X142600000Y-118628571D01* +X142552380Y-118771428D01* +X142552380Y-118866666D01* +X142600000Y-119009523D01* +X142647619Y-119057142D01* +X143552380Y-120009523D02* +X143552380Y-119438095D01* +X143552380Y-119723809D02* +X142552380Y-119723809D01* +X142695238Y-119628571D01* +X142790476Y-119533333D01* +X142838095Y-119438095D01* +X143552380Y-120485714D02* +X143552380Y-120676190D01* +X143504761Y-120771428D01* +X143457142Y-120819047D01* +X143314285Y-120914285D01* +X143123809Y-120961904D01* +X142742857Y-120961904D01* +X142647619Y-120914285D01* +X142600000Y-120866666D01* +X142552380Y-120771428D01* +X142552380Y-120580952D01* +X142600000Y-120485714D01* +X142647619Y-120438095D01* +X142742857Y-120390476D01* +X142980952Y-120390476D01* +X143076190Y-120438095D01* +X143123809Y-120485714D01* +X143171428Y-120580952D01* +X143171428Y-120771428D01* +X143123809Y-120866666D01* +X143076190Y-120914285D01* +X142980952Y-120961904D01* +%TO.C,U3*% +X116966904Y-97877380D02* +X116966904Y-98686904D01* +X116919285Y-98782142D01* +X116871666Y-98829761D01* +X116776428Y-98877380D01* +X116585952Y-98877380D01* +X116490714Y-98829761D01* +X116443095Y-98782142D01* +X116395476Y-98686904D01* +X116395476Y-97877380D01* +X116014523Y-97877380D02* +X115395476Y-97877380D01* +X115728809Y-98258333D01* +X115585952Y-98258333D01* +X115490714Y-98305952D01* +X115443095Y-98353571D01* +X115395476Y-98448809D01* +X115395476Y-98686904D01* +X115443095Y-98782142D01* +X115490714Y-98829761D01* +X115585952Y-98877380D01* +X115871666Y-98877380D01* +X115966904Y-98829761D01* +X116014523Y-98782142D01* +%TO.C,Q2*% +X128817619Y-108489761D02* +X128770000Y-108394523D01* +X128674761Y-108299285D01* +X128531904Y-108156428D01* +X128484285Y-108061190D01* +X128484285Y-107965952D01* +X128722380Y-108013571D02* +X128674761Y-107918333D01* +X128579523Y-107823095D01* +X128389047Y-107775476D01* +X128055714Y-107775476D01* +X127865238Y-107823095D01* +X127770000Y-107918333D01* +X127722380Y-108013571D01* +X127722380Y-108204047D01* +X127770000Y-108299285D01* +X127865238Y-108394523D01* +X128055714Y-108442142D01* +X128389047Y-108442142D01* +X128579523Y-108394523D01* +X128674761Y-108299285D01* +X128722380Y-108204047D01* +X128722380Y-108013571D01* +X127817619Y-108823095D02* +X127770000Y-108870714D01* +X127722380Y-108965952D01* +X127722380Y-109204047D01* +X127770000Y-109299285D01* +X127817619Y-109346904D01* +X127912857Y-109394523D01* +X128008095Y-109394523D01* +X128150952Y-109346904D01* +X128722380Y-108775476D01* +X128722380Y-109394523D01* +%TO.C,R24*% +X132087857Y-114497380D02* +X132421190Y-114021190D01* +X132659285Y-114497380D02* +X132659285Y-113497380D01* +X132278333Y-113497380D01* +X132183095Y-113545000D01* +X132135476Y-113592619D01* +X132087857Y-113687857D01* +X132087857Y-113830714D01* +X132135476Y-113925952D01* +X132183095Y-113973571D01* +X132278333Y-114021190D01* +X132659285Y-114021190D01* +X131706904Y-113592619D02* +X131659285Y-113545000D01* +X131564047Y-113497380D01* +X131325952Y-113497380D01* +X131230714Y-113545000D01* +X131183095Y-113592619D01* +X131135476Y-113687857D01* +X131135476Y-113783095D01* +X131183095Y-113925952D01* +X131754523Y-114497380D01* +X131135476Y-114497380D01* +X130278333Y-113830714D02* +X130278333Y-114497380D01* +X130516428Y-113449761D02* +X130754523Y-114164047D01* +X130135476Y-114164047D01* +%TO.C,R1*% +X134786666Y-104592380D02* +X135120000Y-104116190D01* +X135358095Y-104592380D02* +X135358095Y-103592380D01* +X134977142Y-103592380D01* +X134881904Y-103640000D01* +X134834285Y-103687619D01* +X134786666Y-103782857D01* +X134786666Y-103925714D01* +X134834285Y-104020952D01* +X134881904Y-104068571D01* +X134977142Y-104116190D01* +X135358095Y-104116190D01* +X133834285Y-104592380D02* +X134405714Y-104592380D01* +X134120000Y-104592380D02* +X134120000Y-103592380D01* +X134215238Y-103735238D01* +X134310476Y-103830476D01* +X134405714Y-103878095D01* +%TO.C,C7*% +X186822142Y-130323333D02* +X186869761Y-130275714D01* +X186917380Y-130132857D01* +X186917380Y-130037619D01* +X186869761Y-129894761D01* +X186774523Y-129799523D01* +X186679285Y-129751904D01* +X186488809Y-129704285D01* +X186345952Y-129704285D01* +X186155476Y-129751904D01* +X186060238Y-129799523D01* +X185965000Y-129894761D01* +X185917380Y-130037619D01* +X185917380Y-130132857D01* +X185965000Y-130275714D01* +X186012619Y-130323333D01* +X185917380Y-130656666D02* +X185917380Y-131323333D01* +X186917380Y-130894761D01* +%TO.C,R16*% +X117292380Y-123459642D02* +X116816190Y-123126309D01* +X117292380Y-122888214D02* +X116292380Y-122888214D01* +X116292380Y-123269166D01* +X116340000Y-123364404D01* +X116387619Y-123412023D01* +X116482857Y-123459642D01* +X116625714Y-123459642D01* +X116720952Y-123412023D01* +X116768571Y-123364404D01* +X116816190Y-123269166D01* +X116816190Y-122888214D01* +X117292380Y-124412023D02* +X117292380Y-123840595D01* +X117292380Y-124126309D02* +X116292380Y-124126309D01* +X116435238Y-124031071D01* +X116530476Y-123935833D01* +X116578095Y-123840595D01* +X116292380Y-125269166D02* +X116292380Y-125078690D01* +X116340000Y-124983452D01* +X116387619Y-124935833D01* +X116530476Y-124840595D01* +X116720952Y-124792976D01* +X117101904Y-124792976D01* +X117197142Y-124840595D01* +X117244761Y-124888214D01* +X117292380Y-124983452D01* +X117292380Y-125173928D01* +X117244761Y-125269166D01* +X117197142Y-125316785D01* +X117101904Y-125364404D01* +X116863809Y-125364404D01* +X116768571Y-125316785D01* +X116720952Y-125269166D01* +X116673333Y-125173928D01* +X116673333Y-124983452D01* +X116720952Y-124888214D01* +X116768571Y-124840595D01* +X116863809Y-124792976D01* +%TO.C,R13*% +X178887380Y-105402142D02* +X178411190Y-105068809D01* +X178887380Y-104830714D02* +X177887380Y-104830714D01* +X177887380Y-105211666D01* +X177935000Y-105306904D01* +X177982619Y-105354523D01* +X178077857Y-105402142D01* +X178220714Y-105402142D01* +X178315952Y-105354523D01* +X178363571Y-105306904D01* +X178411190Y-105211666D01* +X178411190Y-104830714D01* +X178887380Y-106354523D02* +X178887380Y-105783095D01* +X178887380Y-106068809D02* +X177887380Y-106068809D01* +X178030238Y-105973571D01* +X178125476Y-105878333D01* +X178173095Y-105783095D01* +X177887380Y-106687857D02* +X177887380Y-107306904D01* +X178268333Y-106973571D01* +X178268333Y-107116428D01* +X178315952Y-107211666D01* +X178363571Y-107259285D01* +X178458809Y-107306904D01* +X178696904Y-107306904D01* +X178792142Y-107259285D01* +X178839761Y-107211666D01* +X178887380Y-107116428D01* +X178887380Y-106830714D01* +X178839761Y-106735476D01* +X178792142Y-106687857D01* +%TO.C,U7*% +X149186904Y-103592380D02* +X149186904Y-104401904D01* +X149139285Y-104497142D01* +X149091666Y-104544761D01* +X148996428Y-104592380D01* +X148805952Y-104592380D01* +X148710714Y-104544761D01* +X148663095Y-104497142D01* +X148615476Y-104401904D01* +X148615476Y-103592380D01* +X148234523Y-103592380D02* +X147567857Y-103592380D01* +X147996428Y-104592380D01* +%TO.C,R21*% +X170632380Y-114927142D02* +X170156190Y-114593809D01* +X170632380Y-114355714D02* +X169632380Y-114355714D01* +X169632380Y-114736666D01* +X169680000Y-114831904D01* +X169727619Y-114879523D01* +X169822857Y-114927142D01* +X169965714Y-114927142D01* +X170060952Y-114879523D01* +X170108571Y-114831904D01* +X170156190Y-114736666D01* +X170156190Y-114355714D01* +X169727619Y-115308095D02* +X169680000Y-115355714D01* +X169632380Y-115450952D01* +X169632380Y-115689047D01* +X169680000Y-115784285D01* +X169727619Y-115831904D01* +X169822857Y-115879523D01* +X169918095Y-115879523D01* +X170060952Y-115831904D01* +X170632380Y-115260476D01* +X170632380Y-115879523D01* +X170632380Y-116831904D02* +X170632380Y-116260476D01* +X170632380Y-116546190D02* +X169632380Y-116546190D01* +X169775238Y-116450952D01* +X169870476Y-116355714D01* +X169918095Y-116260476D01* +%TO.C,C3*% +X187272142Y-105878333D02* +X187319761Y-105830714D01* +X187367380Y-105687857D01* +X187367380Y-105592619D01* +X187319761Y-105449761D01* +X187224523Y-105354523D01* +X187129285Y-105306904D01* +X186938809Y-105259285D01* +X186795952Y-105259285D01* +X186605476Y-105306904D01* +X186510238Y-105354523D01* +X186415000Y-105449761D01* +X186367380Y-105592619D01* +X186367380Y-105687857D01* +X186415000Y-105830714D01* +X186462619Y-105878333D01* +X186367380Y-106211666D02* +X186367380Y-106830714D01* +X186748333Y-106497380D01* +X186748333Y-106640238D01* +X186795952Y-106735476D01* +X186843571Y-106783095D01* +X186938809Y-106830714D01* +X187176904Y-106830714D01* +X187272142Y-106783095D01* +X187319761Y-106735476D01* +X187367380Y-106640238D01* +X187367380Y-106354523D01* +X187319761Y-106259285D01* +X187272142Y-106211666D01* +%TO.C,R2*% +X125896666Y-102687380D02* +X126230000Y-102211190D01* +X126468095Y-102687380D02* +X126468095Y-101687380D01* +X126087142Y-101687380D01* +X125991904Y-101735000D01* +X125944285Y-101782619D01* +X125896666Y-101877857D01* +X125896666Y-102020714D01* +X125944285Y-102115952D01* +X125991904Y-102163571D01* +X126087142Y-102211190D01* +X126468095Y-102211190D01* +X125515714Y-101782619D02* +X125468095Y-101735000D01* +X125372857Y-101687380D01* +X125134761Y-101687380D01* +X125039523Y-101735000D01* +X124991904Y-101782619D01* +X124944285Y-101877857D01* +X124944285Y-101973095D01* +X124991904Y-102115952D01* +X125563333Y-102687380D01* +X124944285Y-102687380D01* +%TO.C,JP1*% +X151328333Y-128357380D02* +X151328333Y-129071666D01* +X151375952Y-129214523D01* +X151471190Y-129309761D01* +X151614047Y-129357380D01* +X151709285Y-129357380D01* +X150852142Y-129357380D02* +X150852142Y-128357380D01* +X150471190Y-128357380D01* +X150375952Y-128405000D01* +X150328333Y-128452619D01* +X150280714Y-128547857D01* +X150280714Y-128690714D01* +X150328333Y-128785952D01* +X150375952Y-128833571D01* +X150471190Y-128881190D01* +X150852142Y-128881190D01* +X149328333Y-129357380D02* +X149899761Y-129357380D01* +X149614047Y-129357380D02* +X149614047Y-128357380D01* +X149709285Y-128500238D01* +X149804523Y-128595476D01* +X149899761Y-128643095D01* +X152809285Y-126817380D02* +X153380714Y-126817380D01* +X153095000Y-126817380D02* +X153095000Y-125817380D01* +X153190238Y-125960238D01* +X153285476Y-126055476D01* +X153380714Y-126103095D01* +X148228333Y-125817380D02* +X147609285Y-125817380D01* +X147942619Y-126198333D01* +X147799761Y-126198333D01* +X147704523Y-126245952D01* +X147656904Y-126293571D01* +X147609285Y-126388809D01* +X147609285Y-126626904D01* +X147656904Y-126722142D01* +X147704523Y-126769761D01* +X147799761Y-126817380D01* +X148085476Y-126817380D01* +X148180714Y-126769761D01* +X148228333Y-126722142D01* +%TO.C,C8*% +X170346666Y-91929642D02* +X170394285Y-91977261D01* +X170537142Y-92024880D01* +X170632380Y-92024880D01* +X170775238Y-91977261D01* +X170870476Y-91882023D01* +X170918095Y-91786785D01* +X170965714Y-91596309D01* +X170965714Y-91453452D01* +X170918095Y-91262976D01* +X170870476Y-91167738D01* +X170775238Y-91072500D01* +X170632380Y-91024880D01* +X170537142Y-91024880D01* +X170394285Y-91072500D01* +X170346666Y-91120119D01* +X169775238Y-91453452D02* +X169870476Y-91405833D01* +X169918095Y-91358214D01* +X169965714Y-91262976D01* +X169965714Y-91215357D01* +X169918095Y-91120119D01* +X169870476Y-91072500D01* +X169775238Y-91024880D01* +X169584761Y-91024880D01* +X169489523Y-91072500D01* +X169441904Y-91120119D01* +X169394285Y-91215357D01* +X169394285Y-91262976D01* +X169441904Y-91358214D01* +X169489523Y-91405833D01* +X169584761Y-91453452D01* +X169775238Y-91453452D01* +X169870476Y-91501071D01* +X169918095Y-91548690D01* +X169965714Y-91643928D01* +X169965714Y-91834404D01* +X169918095Y-91929642D01* +X169870476Y-91977261D01* +X169775238Y-92024880D01* +X169584761Y-92024880D01* +X169489523Y-91977261D01* +X169441904Y-91929642D01* +X169394285Y-91834404D01* +X169394285Y-91643928D01* +X169441904Y-91548690D01* +X169489523Y-91501071D01* +X169584761Y-91453452D01* +%TO.C,R5*% +X173521666Y-120467380D02* +X173855000Y-119991190D01* +X174093095Y-120467380D02* +X174093095Y-119467380D01* +X173712142Y-119467380D01* +X173616904Y-119515000D01* +X173569285Y-119562619D01* +X173521666Y-119657857D01* +X173521666Y-119800714D01* +X173569285Y-119895952D01* +X173616904Y-119943571D01* +X173712142Y-119991190D01* +X174093095Y-119991190D01* +X172616904Y-119467380D02* +X173093095Y-119467380D01* +X173140714Y-119943571D01* +X173093095Y-119895952D01* +X172997857Y-119848333D01* +X172759761Y-119848333D01* +X172664523Y-119895952D01* +X172616904Y-119943571D01* +X172569285Y-120038809D01* +X172569285Y-120276904D01* +X172616904Y-120372142D01* +X172664523Y-120419761D01* +X172759761Y-120467380D01* +X172997857Y-120467380D01* +X173093095Y-120419761D01* +X173140714Y-120372142D01* +%TO.C,R11*% +X185554857Y-78684380D02* +X185888190Y-78208190D01* +X186126285Y-78684380D02* +X186126285Y-77684380D01* +X185745333Y-77684380D01* +X185650095Y-77732000D01* +X185602476Y-77779619D01* +X185554857Y-77874857D01* +X185554857Y-78017714D01* +X185602476Y-78112952D01* +X185650095Y-78160571D01* +X185745333Y-78208190D01* +X186126285Y-78208190D01* +X184602476Y-78684380D02* +X185173904Y-78684380D01* +X184888190Y-78684380D02* +X184888190Y-77684380D01* +X184983428Y-77827238D01* +X185078666Y-77922476D01* +X185173904Y-77970095D01* +X183650095Y-78684380D02* +X184221523Y-78684380D01* +X183935809Y-78684380D02* +X183935809Y-77684380D01* +X184031047Y-77827238D01* +X184126285Y-77922476D01* +X184221523Y-77970095D01* +%TO.C,C5*% +X185269142Y-80853833D02* +X185316761Y-80806214D01* +X185364380Y-80663357D01* +X185364380Y-80568119D01* +X185316761Y-80425261D01* +X185221523Y-80330023D01* +X185126285Y-80282404D01* +X184935809Y-80234785D01* +X184792952Y-80234785D01* +X184602476Y-80282404D01* +X184507238Y-80330023D01* +X184412000Y-80425261D01* +X184364380Y-80568119D01* +X184364380Y-80663357D01* +X184412000Y-80806214D01* +X184459619Y-80853833D01* +X184364380Y-81758595D02* +X184364380Y-81282404D01* +X184840571Y-81234785D01* +X184792952Y-81282404D01* +X184745333Y-81377642D01* +X184745333Y-81615738D01* +X184792952Y-81710976D01* +X184840571Y-81758595D01* +X184935809Y-81806214D01* +X185173904Y-81806214D01* +X185269142Y-81758595D01* +X185316761Y-81710976D01* +X185364380Y-81615738D01* +X185364380Y-81377642D01* +X185316761Y-81282404D01* +X185269142Y-81234785D01* +%TO.C,R18*% +X173362857Y-126182380D02* +X173696190Y-125706190D01* +X173934285Y-126182380D02* +X173934285Y-125182380D01* +X173553333Y-125182380D01* +X173458095Y-125230000D01* +X173410476Y-125277619D01* +X173362857Y-125372857D01* +X173362857Y-125515714D01* +X173410476Y-125610952D01* +X173458095Y-125658571D01* +X173553333Y-125706190D01* +X173934285Y-125706190D01* +X172410476Y-126182380D02* +X172981904Y-126182380D01* +X172696190Y-126182380D02* +X172696190Y-125182380D01* +X172791428Y-125325238D01* +X172886666Y-125420476D01* +X172981904Y-125468095D01* +X171839047Y-125610952D02* +X171934285Y-125563333D01* +X171981904Y-125515714D01* +X172029523Y-125420476D01* +X172029523Y-125372857D01* +X171981904Y-125277619D01* +X171934285Y-125230000D01* +X171839047Y-125182380D01* +X171648571Y-125182380D01* +X171553333Y-125230000D01* +X171505714Y-125277619D01* +X171458095Y-125372857D01* +X171458095Y-125420476D01* +X171505714Y-125515714D01* +X171553333Y-125563333D01* +X171648571Y-125610952D01* +X171839047Y-125610952D01* +X171934285Y-125658571D01* +X171981904Y-125706190D01* +X172029523Y-125801428D01* +X172029523Y-125991904D01* +X171981904Y-126087142D01* +X171934285Y-126134761D01* +X171839047Y-126182380D01* +X171648571Y-126182380D01* +X171553333Y-126134761D01* +X171505714Y-126087142D01* +X171458095Y-125991904D01* +X171458095Y-125801428D01* +X171505714Y-125706190D01* +X171553333Y-125658571D01* +X171648571Y-125610952D01* +%TO.C,R19*% +X167012857Y-131897380D02* +X167346190Y-131421190D01* +X167584285Y-131897380D02* +X167584285Y-130897380D01* +X167203333Y-130897380D01* +X167108095Y-130945000D01* +X167060476Y-130992619D01* +X167012857Y-131087857D01* +X167012857Y-131230714D01* +X167060476Y-131325952D01* +X167108095Y-131373571D01* +X167203333Y-131421190D01* +X167584285Y-131421190D01* +X166060476Y-131897380D02* +X166631904Y-131897380D01* +X166346190Y-131897380D02* +X166346190Y-130897380D01* +X166441428Y-131040238D01* +X166536666Y-131135476D01* +X166631904Y-131183095D01* +X165584285Y-131897380D02* +X165393809Y-131897380D01* +X165298571Y-131849761D01* +X165250952Y-131802142D01* +X165155714Y-131659285D01* +X165108095Y-131468809D01* +X165108095Y-131087857D01* +X165155714Y-130992619D01* +X165203333Y-130945000D01* +X165298571Y-130897380D01* +X165489047Y-130897380D01* +X165584285Y-130945000D01* +X165631904Y-130992619D01* +X165679523Y-131087857D01* +X165679523Y-131325952D01* +X165631904Y-131421190D01* +X165584285Y-131468809D01* +X165489047Y-131516428D01* +X165298571Y-131516428D01* +X165203333Y-131468809D01* +X165155714Y-131421190D01* +X165108095Y-131325952D01* +%TO.C,C13*% +X119067857Y-112977142D02* +X119115476Y-113024761D01* +X119258333Y-113072380D01* +X119353571Y-113072380D01* +X119496428Y-113024761D01* +X119591666Y-112929523D01* +X119639285Y-112834285D01* +X119686904Y-112643809D01* +X119686904Y-112500952D01* +X119639285Y-112310476D01* +X119591666Y-112215238D01* +X119496428Y-112120000D01* +X119353571Y-112072380D01* +X119258333Y-112072380D01* +X119115476Y-112120000D01* +X119067857Y-112167619D01* +X118115476Y-113072380D02* +X118686904Y-113072380D01* +X118401190Y-113072380D02* +X118401190Y-112072380D01* +X118496428Y-112215238D01* +X118591666Y-112310476D01* +X118686904Y-112358095D01* +X117782142Y-112072380D02* +X117163095Y-112072380D01* +X117496428Y-112453333D01* +X117353571Y-112453333D01* +X117258333Y-112500952D01* +X117210714Y-112548571D01* +X117163095Y-112643809D01* +X117163095Y-112881904D01* +X117210714Y-112977142D01* +X117258333Y-113024761D01* +X117353571Y-113072380D01* +X117639285Y-113072380D01* +X117734523Y-113024761D01* +X117782142Y-112977142D01* +%TO.C,U4*% +X182371904Y-117562380D02* +X182371904Y-118371904D01* +X182324285Y-118467142D01* +X182276666Y-118514761D01* +X182181428Y-118562380D01* +X181990952Y-118562380D01* +X181895714Y-118514761D01* +X181848095Y-118467142D01* +X181800476Y-118371904D01* +X181800476Y-117562380D01* +X180895714Y-117895714D02* +X180895714Y-118562380D01* +X181133809Y-117514761D02* +X181371904Y-118229047D01* +X180752857Y-118229047D01* +%TO.C,R9*% +X183681666Y-120848380D02* +X184015000Y-120372190D01* +X184253095Y-120848380D02* +X184253095Y-119848380D01* +X183872142Y-119848380D01* +X183776904Y-119896000D01* +X183729285Y-119943619D01* +X183681666Y-120038857D01* +X183681666Y-120181714D01* +X183729285Y-120276952D01* +X183776904Y-120324571D01* +X183872142Y-120372190D01* +X184253095Y-120372190D01* +X183205476Y-120848380D02* +X183015000Y-120848380D01* +X182919761Y-120800761D01* +X182872142Y-120753142D01* +X182776904Y-120610285D01* +X182729285Y-120419809D01* +X182729285Y-120038857D01* +X182776904Y-119943619D01* +X182824523Y-119896000D01* +X182919761Y-119848380D01* +X183110238Y-119848380D01* +X183205476Y-119896000D01* +X183253095Y-119943619D01* +X183300714Y-120038857D01* +X183300714Y-120276952D01* +X183253095Y-120372190D01* +X183205476Y-120419809D01* +X183110238Y-120467428D01* +X182919761Y-120467428D01* +X182824523Y-120419809D01* +X182776904Y-120372190D01* +X182729285Y-120276952D01* +%TO.C,R14*% +X183967380Y-105402142D02* +X183491190Y-105068809D01* +X183967380Y-104830714D02* +X182967380Y-104830714D01* +X182967380Y-105211666D01* +X183015000Y-105306904D01* +X183062619Y-105354523D01* +X183157857Y-105402142D01* +X183300714Y-105402142D01* +X183395952Y-105354523D01* +X183443571Y-105306904D01* +X183491190Y-105211666D01* +X183491190Y-104830714D01* +X183967380Y-106354523D02* +X183967380Y-105783095D01* +X183967380Y-106068809D02* +X182967380Y-106068809D01* +X183110238Y-105973571D01* +X183205476Y-105878333D01* +X183253095Y-105783095D01* +X183300714Y-107211666D02* +X183967380Y-107211666D01* +X182919761Y-106973571D02* +X183634047Y-106735476D01* +X183634047Y-107354523D01* +%TO.C,R29*% +X162377380Y-117467142D02* +X161901190Y-117133809D01* +X162377380Y-116895714D02* +X161377380Y-116895714D01* +X161377380Y-117276666D01* +X161425000Y-117371904D01* +X161472619Y-117419523D01* +X161567857Y-117467142D01* +X161710714Y-117467142D01* +X161805952Y-117419523D01* +X161853571Y-117371904D01* +X161901190Y-117276666D01* +X161901190Y-116895714D01* +X161472619Y-117848095D02* +X161425000Y-117895714D01* +X161377380Y-117990952D01* +X161377380Y-118229047D01* +X161425000Y-118324285D01* +X161472619Y-118371904D01* +X161567857Y-118419523D01* +X161663095Y-118419523D01* +X161805952Y-118371904D01* +X162377380Y-117800476D01* +X162377380Y-118419523D01* +X162377380Y-118895714D02* +X162377380Y-119086190D01* +X162329761Y-119181428D01* +X162282142Y-119229047D01* +X162139285Y-119324285D01* +X161948809Y-119371904D01* +X161567857Y-119371904D01* +X161472619Y-119324285D01* +X161425000Y-119276666D01* +X161377380Y-119181428D01* +X161377380Y-118990952D01* +X161425000Y-118895714D01* +X161472619Y-118848095D01* +X161567857Y-118800476D01* +X161805952Y-118800476D01* +X161901190Y-118848095D01* +X161948809Y-118895714D01* +X161996428Y-118990952D01* +X161996428Y-119181428D01* +X161948809Y-119276666D01* +X161901190Y-119324285D01* +X161805952Y-119371904D01* +%TO.C,C10*% +X167362142Y-89659642D02* +X167409761Y-89612023D01* +X167457380Y-89469166D01* +X167457380Y-89373928D01* +X167409761Y-89231071D01* +X167314523Y-89135833D01* +X167219285Y-89088214D01* +X167028809Y-89040595D01* +X166885952Y-89040595D01* +X166695476Y-89088214D01* +X166600238Y-89135833D01* +X166505000Y-89231071D01* +X166457380Y-89373928D01* +X166457380Y-89469166D01* +X166505000Y-89612023D01* +X166552619Y-89659642D01* +X167457380Y-90612023D02* +X167457380Y-90040595D01* +X167457380Y-90326309D02* +X166457380Y-90326309D01* +X166600238Y-90231071D01* +X166695476Y-90135833D01* +X166743095Y-90040595D01* +X166457380Y-91231071D02* +X166457380Y-91326309D01* +X166505000Y-91421547D01* +X166552619Y-91469166D01* +X166647857Y-91516785D01* +X166838333Y-91564404D01* +X167076428Y-91564404D01* +X167266904Y-91516785D01* +X167362142Y-91469166D01* +X167409761Y-91421547D01* +X167457380Y-91326309D01* +X167457380Y-91231071D01* +X167409761Y-91135833D01* +X167362142Y-91088214D01* +X167266904Y-91040595D01* +X167076428Y-90992976D01* +X166838333Y-90992976D01* +X166647857Y-91040595D01* +X166552619Y-91088214D01* +X166505000Y-91135833D01* +X166457380Y-91231071D01* +%TO.C,R26*% +X147962857Y-124277380D02* +X148296190Y-123801190D01* +X148534285Y-124277380D02* +X148534285Y-123277380D01* +X148153333Y-123277380D01* +X148058095Y-123325000D01* +X148010476Y-123372619D01* +X147962857Y-123467857D01* +X147962857Y-123610714D01* +X148010476Y-123705952D01* +X148058095Y-123753571D01* +X148153333Y-123801190D01* +X148534285Y-123801190D01* +X147581904Y-123372619D02* +X147534285Y-123325000D01* +X147439047Y-123277380D01* +X147200952Y-123277380D01* +X147105714Y-123325000D01* +X147058095Y-123372619D01* +X147010476Y-123467857D01* +X147010476Y-123563095D01* +X147058095Y-123705952D01* +X147629523Y-124277380D01* +X147010476Y-124277380D01* +X146153333Y-123277380D02* +X146343809Y-123277380D01* +X146439047Y-123325000D01* +X146486666Y-123372619D01* +X146581904Y-123515476D01* +X146629523Y-123705952D01* +X146629523Y-124086904D01* +X146581904Y-124182142D01* +X146534285Y-124229761D01* +X146439047Y-124277380D01* +X146248571Y-124277380D01* +X146153333Y-124229761D01* +X146105714Y-124182142D01* +X146058095Y-124086904D01* +X146058095Y-123848809D01* +X146105714Y-123753571D01* +X146153333Y-123705952D01* +X146248571Y-123658333D01* +X146439047Y-123658333D01* +X146534285Y-123705952D01* +X146581904Y-123753571D01* +X146629523Y-123848809D01* +%TO.C,R28*% +X164917380Y-117467142D02* +X164441190Y-117133809D01* +X164917380Y-116895714D02* +X163917380Y-116895714D01* +X163917380Y-117276666D01* +X163965000Y-117371904D01* +X164012619Y-117419523D01* +X164107857Y-117467142D01* +X164250714Y-117467142D01* +X164345952Y-117419523D01* +X164393571Y-117371904D01* +X164441190Y-117276666D01* +X164441190Y-116895714D01* +X164012619Y-117848095D02* +X163965000Y-117895714D01* +X163917380Y-117990952D01* +X163917380Y-118229047D01* +X163965000Y-118324285D01* +X164012619Y-118371904D01* +X164107857Y-118419523D01* +X164203095Y-118419523D01* +X164345952Y-118371904D01* +X164917380Y-117800476D01* +X164917380Y-118419523D01* +X164345952Y-118990952D02* +X164298333Y-118895714D01* +X164250714Y-118848095D01* +X164155476Y-118800476D01* +X164107857Y-118800476D01* +X164012619Y-118848095D01* +X163965000Y-118895714D01* +X163917380Y-118990952D01* +X163917380Y-119181428D01* +X163965000Y-119276666D01* +X164012619Y-119324285D01* +X164107857Y-119371904D01* +X164155476Y-119371904D01* +X164250714Y-119324285D01* +X164298333Y-119276666D01* +X164345952Y-119181428D01* +X164345952Y-118990952D01* +X164393571Y-118895714D01* +X164441190Y-118848095D01* +X164536428Y-118800476D01* +X164726904Y-118800476D01* +X164822142Y-118848095D01* +X164869761Y-118895714D01* +X164917380Y-118990952D01* +X164917380Y-119181428D01* +X164869761Y-119276666D01* +X164822142Y-119324285D01* +X164726904Y-119371904D01* +X164536428Y-119371904D01* +X164441190Y-119324285D01* +X164393571Y-119276666D01* +X164345952Y-119181428D01* +%TO.C,R8*% +X185364380Y-91400333D02* +X184888190Y-91067000D01* +X185364380Y-90828904D02* +X184364380Y-90828904D01* +X184364380Y-91209857D01* +X184412000Y-91305095D01* +X184459619Y-91352714D01* +X184554857Y-91400333D01* +X184697714Y-91400333D01* +X184792952Y-91352714D01* +X184840571Y-91305095D01* +X184888190Y-91209857D01* +X184888190Y-90828904D01* +X184792952Y-91971761D02* +X184745333Y-91876523D01* +X184697714Y-91828904D01* +X184602476Y-91781285D01* +X184554857Y-91781285D01* +X184459619Y-91828904D01* +X184412000Y-91876523D01* +X184364380Y-91971761D01* +X184364380Y-92162238D01* +X184412000Y-92257476D01* +X184459619Y-92305095D01* +X184554857Y-92352714D01* +X184602476Y-92352714D01* +X184697714Y-92305095D01* +X184745333Y-92257476D01* +X184792952Y-92162238D01* +X184792952Y-91971761D01* +X184840571Y-91876523D01* +X184888190Y-91828904D01* +X184983428Y-91781285D01* +X185173904Y-91781285D01* +X185269142Y-91828904D01* +X185316761Y-91876523D01* +X185364380Y-91971761D01* +X185364380Y-92162238D01* +X185316761Y-92257476D01* +X185269142Y-92305095D01* +X185173904Y-92352714D01* +X184983428Y-92352714D01* +X184888190Y-92305095D01* +X184840571Y-92257476D01* +X184792952Y-92162238D01* +%TO.C,R6*% +X125896666Y-100147380D02* +X126230000Y-99671190D01* +X126468095Y-100147380D02* +X126468095Y-99147380D01* +X126087142Y-99147380D01* +X125991904Y-99195000D01* +X125944285Y-99242619D01* +X125896666Y-99337857D01* +X125896666Y-99480714D01* +X125944285Y-99575952D01* +X125991904Y-99623571D01* +X126087142Y-99671190D01* +X126468095Y-99671190D01* +X125039523Y-99147380D02* +X125230000Y-99147380D01* +X125325238Y-99195000D01* +X125372857Y-99242619D01* +X125468095Y-99385476D01* +X125515714Y-99575952D01* +X125515714Y-99956904D01* +X125468095Y-100052142D01* +X125420476Y-100099761D01* +X125325238Y-100147380D01* +X125134761Y-100147380D01* +X125039523Y-100099761D01* +X124991904Y-100052142D01* +X124944285Y-99956904D01* +X124944285Y-99718809D01* +X124991904Y-99623571D01* +X125039523Y-99575952D01* +X125134761Y-99528333D01* +X125325238Y-99528333D01* +X125420476Y-99575952D01* +X125468095Y-99623571D01* +X125515714Y-99718809D01* +%TO.C,R25*% +X135897857Y-107132380D02* +X136231190Y-106656190D01* +X136469285Y-107132380D02* +X136469285Y-106132380D01* +X136088333Y-106132380D01* +X135993095Y-106180000D01* +X135945476Y-106227619D01* +X135897857Y-106322857D01* +X135897857Y-106465714D01* +X135945476Y-106560952D01* +X135993095Y-106608571D01* +X136088333Y-106656190D01* +X136469285Y-106656190D01* +X135516904Y-106227619D02* +X135469285Y-106180000D01* +X135374047Y-106132380D01* +X135135952Y-106132380D01* +X135040714Y-106180000D01* +X134993095Y-106227619D01* +X134945476Y-106322857D01* +X134945476Y-106418095D01* +X134993095Y-106560952D01* +X135564523Y-107132380D01* +X134945476Y-107132380D01* +X134040714Y-106132380D02* +X134516904Y-106132380D01* +X134564523Y-106608571D01* +X134516904Y-106560952D01* +X134421666Y-106513333D01* +X134183571Y-106513333D01* +X134088333Y-106560952D01* +X134040714Y-106608571D01* +X133993095Y-106703809D01* +X133993095Y-106941904D01* +X134040714Y-107037142D01* +X134088333Y-107084761D01* +X134183571Y-107132380D01* +X134421666Y-107132380D01* +X134516904Y-107084761D01* +X134564523Y-107037142D01* +%TO.C,R27*% +X168092380Y-117467142D02* +X167616190Y-117133809D01* +X168092380Y-116895714D02* +X167092380Y-116895714D01* +X167092380Y-117276666D01* +X167140000Y-117371904D01* +X167187619Y-117419523D01* +X167282857Y-117467142D01* +X167425714Y-117467142D01* +X167520952Y-117419523D01* +X167568571Y-117371904D01* +X167616190Y-117276666D01* +X167616190Y-116895714D01* +X167187619Y-117848095D02* +X167140000Y-117895714D01* +X167092380Y-117990952D01* +X167092380Y-118229047D01* +X167140000Y-118324285D01* +X167187619Y-118371904D01* +X167282857Y-118419523D01* +X167378095Y-118419523D01* +X167520952Y-118371904D01* +X168092380Y-117800476D01* +X168092380Y-118419523D01* +X167092380Y-118752857D02* +X167092380Y-119419523D01* +X168092380Y-118990952D01* +%TO.C,C14*% +X127007857Y-90527142D02* +X127055476Y-90574761D01* +X127198333Y-90622380D01* +X127293571Y-90622380D01* +X127436428Y-90574761D01* +X127531666Y-90479523D01* +X127579285Y-90384285D01* +X127626904Y-90193809D01* +X127626904Y-90050952D01* +X127579285Y-89860476D01* +X127531666Y-89765238D01* +X127436428Y-89670000D01* +X127293571Y-89622380D01* +X127198333Y-89622380D01* +X127055476Y-89670000D01* +X127007857Y-89717619D01* +X126055476Y-90622380D02* +X126626904Y-90622380D01* +X126341190Y-90622380D02* +X126341190Y-89622380D01* +X126436428Y-89765238D01* +X126531666Y-89860476D01* +X126626904Y-89908095D01* +X125198333Y-89955714D02* +X125198333Y-90622380D01* +X125436428Y-89574761D02* +X125674523Y-90289047D01* +X125055476Y-90289047D01* +%TO.C,R23*% +X121356380Y-123459642D02* +X120880190Y-123126309D01* +X121356380Y-122888214D02* +X120356380Y-122888214D01* +X120356380Y-123269166D01* +X120404000Y-123364404D01* +X120451619Y-123412023D01* +X120546857Y-123459642D01* +X120689714Y-123459642D01* +X120784952Y-123412023D01* +X120832571Y-123364404D01* +X120880190Y-123269166D01* +X120880190Y-122888214D01* +X120451619Y-123840595D02* +X120404000Y-123888214D01* +X120356380Y-123983452D01* +X120356380Y-124221547D01* +X120404000Y-124316785D01* +X120451619Y-124364404D01* +X120546857Y-124412023D01* +X120642095Y-124412023D01* +X120784952Y-124364404D01* +X121356380Y-123792976D01* +X121356380Y-124412023D01* +X120356380Y-124745357D02* +X120356380Y-125364404D01* +X120737333Y-125031071D01* +X120737333Y-125173928D01* +X120784952Y-125269166D01* +X120832571Y-125316785D01* +X120927809Y-125364404D01* +X121165904Y-125364404D01* +X121261142Y-125316785D01* +X121308761Y-125269166D01* +X121356380Y-125173928D01* +X121356380Y-124888214D01* +X121308761Y-124792976D01* +X121261142Y-124745357D01* +%TO.C,R12*% +X181427380Y-105402142D02* +X180951190Y-105068809D01* +X181427380Y-104830714D02* +X180427380Y-104830714D01* +X180427380Y-105211666D01* +X180475000Y-105306904D01* +X180522619Y-105354523D01* +X180617857Y-105402142D01* +X180760714Y-105402142D01* +X180855952Y-105354523D01* +X180903571Y-105306904D01* +X180951190Y-105211666D01* +X180951190Y-104830714D01* +X181427380Y-106354523D02* +X181427380Y-105783095D01* +X181427380Y-106068809D02* +X180427380Y-106068809D01* +X180570238Y-105973571D01* +X180665476Y-105878333D01* +X180713095Y-105783095D01* +X180522619Y-106735476D02* +X180475000Y-106783095D01* +X180427380Y-106878333D01* +X180427380Y-107116428D01* +X180475000Y-107211666D01* +X180522619Y-107259285D01* +X180617857Y-107306904D01* +X180713095Y-107306904D01* +X180855952Y-107259285D01* +X181427380Y-106687857D01* +X181427380Y-107306904D01* +%TO.C,C15*% +X124817142Y-131752142D02* +X124864761Y-131704523D01* +X124912380Y-131561666D01* +X124912380Y-131466428D01* +X124864761Y-131323571D01* +X124769523Y-131228333D01* +X124674285Y-131180714D01* +X124483809Y-131133095D01* +X124340952Y-131133095D01* +X124150476Y-131180714D01* +X124055238Y-131228333D01* +X123960000Y-131323571D01* +X123912380Y-131466428D01* +X123912380Y-131561666D01* +X123960000Y-131704523D01* +X124007619Y-131752142D01* +X124912380Y-132704523D02* +X124912380Y-132133095D01* +X124912380Y-132418809D02* +X123912380Y-132418809D01* +X124055238Y-132323571D01* +X124150476Y-132228333D01* +X124198095Y-132133095D01* +X123912380Y-133609285D02* +X123912380Y-133133095D01* +X124388571Y-133085476D01* +X124340952Y-133133095D01* +X124293333Y-133228333D01* +X124293333Y-133466428D01* +X124340952Y-133561666D01* +X124388571Y-133609285D01* +X124483809Y-133656904D01* +X124721904Y-133656904D01* +X124817142Y-133609285D01* +X124864761Y-133561666D01* +X124912380Y-133466428D01* +X124912380Y-133228333D01* +X124864761Y-133133095D01* +X124817142Y-133085476D01* +%TO.C,C12*% +X151076857Y-93673142D02* +X151124476Y-93720761D01* +X151267333Y-93768380D01* +X151362571Y-93768380D01* +X151505428Y-93720761D01* +X151600666Y-93625523D01* +X151648285Y-93530285D01* +X151695904Y-93339809D01* +X151695904Y-93196952D01* +X151648285Y-93006476D01* +X151600666Y-92911238D01* +X151505428Y-92816000D01* +X151362571Y-92768380D01* +X151267333Y-92768380D01* +X151124476Y-92816000D01* +X151076857Y-92863619D01* +X150124476Y-93768380D02* +X150695904Y-93768380D01* +X150410190Y-93768380D02* +X150410190Y-92768380D01* +X150505428Y-92911238D01* +X150600666Y-93006476D01* +X150695904Y-93054095D01* +X149743523Y-92863619D02* +X149695904Y-92816000D01* +X149600666Y-92768380D01* +X149362571Y-92768380D01* +X149267333Y-92816000D01* +X149219714Y-92863619D01* +X149172095Y-92958857D01* +X149172095Y-93054095D01* +X149219714Y-93196952D01* +X149791142Y-93768380D01* +X149172095Y-93768380D01* +%TO.C,C1*% +X114657142Y-104481333D02* +X114704761Y-104433714D01* +X114752380Y-104290857D01* +X114752380Y-104195619D01* +X114704761Y-104052761D01* +X114609523Y-103957523D01* +X114514285Y-103909904D01* +X114323809Y-103862285D01* +X114180952Y-103862285D01* +X113990476Y-103909904D01* +X113895238Y-103957523D01* +X113800000Y-104052761D01* +X113752380Y-104195619D01* +X113752380Y-104290857D01* +X113800000Y-104433714D01* +X113847619Y-104481333D01* +X114752380Y-105433714D02* +X114752380Y-104862285D01* +X114752380Y-105148000D02* +X113752380Y-105148000D01* +X113895238Y-105052761D01* +X113990476Y-104957523D01* +X114038095Y-104862285D01* +%TO.C,Q1*% +X130905238Y-98972619D02* +X131000476Y-98925000D01* +X131095714Y-98829761D01* +X131238571Y-98686904D01* +X131333809Y-98639285D01* +X131429047Y-98639285D01* +X131381428Y-98877380D02* +X131476666Y-98829761D01* +X131571904Y-98734523D01* +X131619523Y-98544047D01* +X131619523Y-98210714D01* +X131571904Y-98020238D01* +X131476666Y-97925000D01* +X131381428Y-97877380D01* +X131190952Y-97877380D01* +X131095714Y-97925000D01* +X131000476Y-98020238D01* +X130952857Y-98210714D01* +X130952857Y-98544047D01* +X131000476Y-98734523D01* +X131095714Y-98829761D01* +X131190952Y-98877380D01* +X131381428Y-98877380D01* +X130000476Y-98877380D02* +X130571904Y-98877380D01* +X130286190Y-98877380D02* +X130286190Y-97877380D01* +X130381428Y-98020238D01* +X130476666Y-98115476D01* +X130571904Y-98163095D01* +%TO.C,U6*% +X175386904Y-94199880D02* +X175386904Y-95009404D01* +X175339285Y-95104642D01* +X175291666Y-95152261D01* +X175196428Y-95199880D01* +X175005952Y-95199880D01* +X174910714Y-95152261D01* +X174863095Y-95104642D01* +X174815476Y-95009404D01* +X174815476Y-94199880D01* +X173910714Y-94199880D02* +X174101190Y-94199880D01* +X174196428Y-94247500D01* +X174244047Y-94295119D01* +X174339285Y-94437976D01* +X174386904Y-94628452D01* +X174386904Y-95009404D01* +X174339285Y-95104642D01* +X174291666Y-95152261D01* +X174196428Y-95199880D01* +X174005952Y-95199880D01* +X173910714Y-95152261D01* +X173863095Y-95104642D01* +X173815476Y-95009404D01* +X173815476Y-94771309D01* +X173863095Y-94676071D01* +X173910714Y-94628452D01* +X174005952Y-94580833D01* +X174196428Y-94580833D01* +X174291666Y-94628452D01* +X174339285Y-94676071D01* +X174386904Y-94771309D01* +%TO.C,C9*% +X181141666Y-102724642D02* +X181189285Y-102772261D01* +X181332142Y-102819880D01* +X181427380Y-102819880D01* +X181570238Y-102772261D01* +X181665476Y-102677023D01* +X181713095Y-102581785D01* +X181760714Y-102391309D01* +X181760714Y-102248452D01* +X181713095Y-102057976D01* +X181665476Y-101962738D01* +X181570238Y-101867500D01* +X181427380Y-101819880D01* +X181332142Y-101819880D01* +X181189285Y-101867500D01* +X181141666Y-101915119D01* +X180665476Y-102819880D02* +X180475000Y-102819880D01* +X180379761Y-102772261D01* +X180332142Y-102724642D01* +X180236904Y-102581785D01* +X180189285Y-102391309D01* +X180189285Y-102010357D01* +X180236904Y-101915119D01* +X180284523Y-101867500D01* +X180379761Y-101819880D01* +X180570238Y-101819880D01* +X180665476Y-101867500D01* +X180713095Y-101915119D01* +X180760714Y-102010357D01* +X180760714Y-102248452D01* +X180713095Y-102343690D01* +X180665476Y-102391309D01* +X180570238Y-102438928D01* +X180379761Y-102438928D01* +X180284523Y-102391309D01* +X180236904Y-102343690D01* +X180189285Y-102248452D01* +%TO.C,C11*% +X180697142Y-97279642D02* +X180744761Y-97232023D01* +X180792380Y-97089166D01* +X180792380Y-96993928D01* +X180744761Y-96851071D01* +X180649523Y-96755833D01* +X180554285Y-96708214D01* +X180363809Y-96660595D01* +X180220952Y-96660595D01* +X180030476Y-96708214D01* +X179935238Y-96755833D01* +X179840000Y-96851071D01* +X179792380Y-96993928D01* +X179792380Y-97089166D01* +X179840000Y-97232023D01* +X179887619Y-97279642D01* +X180792380Y-98232023D02* +X180792380Y-97660595D01* +X180792380Y-97946309D02* +X179792380Y-97946309D01* +X179935238Y-97851071D01* +X180030476Y-97755833D01* +X180078095Y-97660595D01* +X180792380Y-99184404D02* +X180792380Y-98612976D01* +X180792380Y-98898690D02* +X179792380Y-98898690D01* +X179935238Y-98803452D01* +X180030476Y-98708214D01* +X180078095Y-98612976D01* +%TO.C,C18*% +X159107142Y-117467142D02* +X159154761Y-117419523D01* +X159202380Y-117276666D01* +X159202380Y-117181428D01* +X159154761Y-117038571D01* +X159059523Y-116943333D01* +X158964285Y-116895714D01* +X158773809Y-116848095D01* +X158630952Y-116848095D01* +X158440476Y-116895714D01* +X158345238Y-116943333D01* +X158250000Y-117038571D01* +X158202380Y-117181428D01* +X158202380Y-117276666D01* +X158250000Y-117419523D01* +X158297619Y-117467142D01* +X159202380Y-118419523D02* +X159202380Y-117848095D01* +X159202380Y-118133809D02* +X158202380Y-118133809D01* +X158345238Y-118038571D01* +X158440476Y-117943333D01* +X158488095Y-117848095D01* +X158630952Y-118990952D02* +X158583333Y-118895714D01* +X158535714Y-118848095D01* +X158440476Y-118800476D01* +X158392857Y-118800476D01* +X158297619Y-118848095D01* +X158250000Y-118895714D01* +X158202380Y-118990952D01* +X158202380Y-119181428D01* +X158250000Y-119276666D01* +X158297619Y-119324285D01* +X158392857Y-119371904D01* +X158440476Y-119371904D01* +X158535714Y-119324285D01* +X158583333Y-119276666D01* +X158630952Y-119181428D01* +X158630952Y-118990952D01* +X158678571Y-118895714D01* +X158726190Y-118848095D01* +X158821428Y-118800476D01* +X159011904Y-118800476D01* +X159107142Y-118848095D01* +X159154761Y-118895714D01* +X159202380Y-118990952D01* +X159202380Y-119181428D01* +X159154761Y-119276666D01* +X159107142Y-119324285D01* +X159011904Y-119371904D01* +X158821428Y-119371904D01* +X158726190Y-119324285D01* +X158678571Y-119276666D01* +X158630952Y-119181428D01* +%TO.C,R22*% +X119324380Y-123459642D02* +X118848190Y-123126309D01* +X119324380Y-122888214D02* +X118324380Y-122888214D01* +X118324380Y-123269166D01* +X118372000Y-123364404D01* +X118419619Y-123412023D01* +X118514857Y-123459642D01* +X118657714Y-123459642D01* +X118752952Y-123412023D01* +X118800571Y-123364404D01* +X118848190Y-123269166D01* +X118848190Y-122888214D01* +X118419619Y-123840595D02* +X118372000Y-123888214D01* +X118324380Y-123983452D01* +X118324380Y-124221547D01* +X118372000Y-124316785D01* +X118419619Y-124364404D01* +X118514857Y-124412023D01* +X118610095Y-124412023D01* +X118752952Y-124364404D01* +X119324380Y-123792976D01* +X119324380Y-124412023D01* +X118419619Y-124792976D02* +X118372000Y-124840595D01* +X118324380Y-124935833D01* +X118324380Y-125173928D01* +X118372000Y-125269166D01* +X118419619Y-125316785D01* +X118514857Y-125364404D01* +X118610095Y-125364404D01* +X118752952Y-125316785D01* +X119324380Y-124745357D01* +X119324380Y-125364404D01* +%TO.C,U5*% +X174116904Y-82544880D02* +X174116904Y-83354404D01* +X174069285Y-83449642D01* +X174021666Y-83497261D01* +X173926428Y-83544880D01* +X173735952Y-83544880D01* +X173640714Y-83497261D01* +X173593095Y-83449642D01* +X173545476Y-83354404D01* +X173545476Y-82544880D01* +X172593095Y-82544880D02* +X173069285Y-82544880D01* +X173116904Y-83021071D01* +X173069285Y-82973452D01* +X172974047Y-82925833D01* +X172735952Y-82925833D01* +X172640714Y-82973452D01* +X172593095Y-83021071D01* +X172545476Y-83116309D01* +X172545476Y-83354404D01* +X172593095Y-83449642D01* +X172640714Y-83497261D01* +X172735952Y-83544880D01* +X172974047Y-83544880D01* +X173069285Y-83497261D01* +X173116904Y-83449642D01* +%TO.C,C16*% +X156852857Y-122277142D02* +X156900476Y-122324761D01* +X157043333Y-122372380D01* +X157138571Y-122372380D01* +X157281428Y-122324761D01* +X157376666Y-122229523D01* +X157424285Y-122134285D01* +X157471904Y-121943809D01* +X157471904Y-121800952D01* +X157424285Y-121610476D01* +X157376666Y-121515238D01* +X157281428Y-121420000D01* +X157138571Y-121372380D01* +X157043333Y-121372380D01* +X156900476Y-121420000D01* +X156852857Y-121467619D01* +X155900476Y-122372380D02* +X156471904Y-122372380D01* +X156186190Y-122372380D02* +X156186190Y-121372380D01* +X156281428Y-121515238D01* +X156376666Y-121610476D01* +X156471904Y-121658095D01* +X155043333Y-121372380D02* +X155233809Y-121372380D01* +X155329047Y-121420000D01* +X155376666Y-121467619D01* +X155471904Y-121610476D01* +X155519523Y-121800952D01* +X155519523Y-122181904D01* +X155471904Y-122277142D01* +X155424285Y-122324761D01* +X155329047Y-122372380D01* +X155138571Y-122372380D01* +X155043333Y-122324761D01* +X154995714Y-122277142D01* +X154948095Y-122181904D01* +X154948095Y-121943809D01* +X154995714Y-121848571D01* +X155043333Y-121800952D01* +X155138571Y-121753333D01* +X155329047Y-121753333D01* +X155424285Y-121800952D01* +X155471904Y-121848571D01* +X155519523Y-121943809D01* +%TO.C,R4*% +X125896666Y-105227380D02* +X126230000Y-104751190D01* +X126468095Y-105227380D02* +X126468095Y-104227380D01* +X126087142Y-104227380D01* +X125991904Y-104275000D01* +X125944285Y-104322619D01* +X125896666Y-104417857D01* +X125896666Y-104560714D01* +X125944285Y-104655952D01* +X125991904Y-104703571D01* +X126087142Y-104751190D01* +X126468095Y-104751190D01* +X125039523Y-104560714D02* +X125039523Y-105227380D01* +X125277619Y-104179761D02* +X125515714Y-104894047D01* +X124896666Y-104894047D01* +%TO.C,C2*% +X118591666Y-105992142D02* +X118639285Y-106039761D01* +X118782142Y-106087380D01* +X118877380Y-106087380D01* +X119020238Y-106039761D01* +X119115476Y-105944523D01* +X119163095Y-105849285D01* +X119210714Y-105658809D01* +X119210714Y-105515952D01* +X119163095Y-105325476D01* +X119115476Y-105230238D01* +X119020238Y-105135000D01* +X118877380Y-105087380D01* +X118782142Y-105087380D01* +X118639285Y-105135000D01* +X118591666Y-105182619D01* +X118210714Y-105182619D02* +X118163095Y-105135000D01* +X118067857Y-105087380D01* +X117829761Y-105087380D01* +X117734523Y-105135000D01* +X117686904Y-105182619D01* +X117639285Y-105277857D01* +X117639285Y-105373095D01* +X117686904Y-105515952D01* +X118258333Y-106087380D01* +X117639285Y-106087380D01* +%TO.C,R15*% +X168347380Y-97279642D02* +X167871190Y-96946309D01* +X168347380Y-96708214D02* +X167347380Y-96708214D01* +X167347380Y-97089166D01* +X167395000Y-97184404D01* +X167442619Y-97232023D01* +X167537857Y-97279642D01* +X167680714Y-97279642D01* +X167775952Y-97232023D01* +X167823571Y-97184404D01* +X167871190Y-97089166D01* +X167871190Y-96708214D01* +X168347380Y-98232023D02* +X168347380Y-97660595D01* +X168347380Y-97946309D02* +X167347380Y-97946309D01* +X167490238Y-97851071D01* +X167585476Y-97755833D01* +X167633095Y-97660595D01* +X167347380Y-99136785D02* +X167347380Y-98660595D01* +X167823571Y-98612976D01* +X167775952Y-98660595D01* +X167728333Y-98755833D01* +X167728333Y-98993928D01* +X167775952Y-99089166D01* +X167823571Y-99136785D01* +X167918809Y-99184404D01* +X168156904Y-99184404D01* +X168252142Y-99136785D01* +X168299761Y-99089166D01* +X168347380Y-98993928D01* +X168347380Y-98755833D01* +X168299761Y-98660595D01* +X168252142Y-98612976D01* +%TO.C,R20*% +X167012857Y-129357380D02* +X167346190Y-128881190D01* +X167584285Y-129357380D02* +X167584285Y-128357380D01* +X167203333Y-128357380D01* +X167108095Y-128405000D01* +X167060476Y-128452619D01* +X167012857Y-128547857D01* +X167012857Y-128690714D01* +X167060476Y-128785952D01* +X167108095Y-128833571D01* +X167203333Y-128881190D01* +X167584285Y-128881190D01* +X166631904Y-128452619D02* +X166584285Y-128405000D01* +X166489047Y-128357380D01* +X166250952Y-128357380D01* +X166155714Y-128405000D01* +X166108095Y-128452619D01* +X166060476Y-128547857D01* +X166060476Y-128643095D01* +X166108095Y-128785952D01* +X166679523Y-129357380D01* +X166060476Y-129357380D01* +X165441428Y-128357380D02* +X165346190Y-128357380D01* +X165250952Y-128405000D01* +X165203333Y-128452619D01* +X165155714Y-128547857D01* +X165108095Y-128738333D01* +X165108095Y-128976428D01* +X165155714Y-129166904D01* +X165203333Y-129262142D01* +X165250952Y-129309761D01* +X165346190Y-129357380D01* +X165441428Y-129357380D01* +X165536666Y-129309761D01* +X165584285Y-129262142D01* +X165631904Y-129166904D01* +X165679523Y-128976428D01* +X165679523Y-128738333D01* +X165631904Y-128547857D01* +X165584285Y-128452619D01* +X165536666Y-128405000D01* +X165441428Y-128357380D01* +D13* +%TO.C,D1*% +X138955000Y-99805000D02* +X136795000Y-99805000D01* +X138955000Y-102125000D02* +X137295000Y-102125000D01* +%TO.C,C17*% +X156945000Y-106306252D02* +X156945000Y-105783748D01* +X155475000Y-106306252D02* +X155475000Y-105783748D01* +%TO.C,R10*% +X174524936Y-80265000D02* +X174979064Y-80265000D01* +X174524936Y-81735000D02* +X174979064Y-81735000D01* +%TO.C,U2*% +X154105000Y-109420000D02* +X154105000Y-109870000D01* +X146885000Y-116640000D02* +X146885000Y-116190000D01* +X153655000Y-116640000D02* +X154105000Y-116640000D01* +X153655000Y-109420000D02* +X154105000Y-109420000D01* +X146885000Y-109420000D02* +X146885000Y-109870000D01* +X147335000Y-109420000D02* +X146885000Y-109420000D01* +X154105000Y-116640000D02* +X154105000Y-116190000D01* +X146885000Y-116190000D02* +X145595000Y-116190000D01* +X147335000Y-116640000D02* +X146885000Y-116640000D01* +%TO.C,C4*% +X185520000Y-115831252D02* +X185520000Y-115308748D01* +X184050000Y-115831252D02* +X184050000Y-115308748D01* +%TO.C,R7*% +X174852064Y-112295000D02* +X174397936Y-112295000D01* +X174852064Y-113765000D02* +X174397936Y-113765000D01* +%TO.C,C20*% +X142340000Y-111498748D02* +X142340000Y-112021252D01* +X140870000Y-111498748D02* +X140870000Y-112021252D01* +%TO.C,R17*% +X169772064Y-122455000D02* +X169317936Y-122455000D01* +X169772064Y-123925000D02* +X169317936Y-123925000D01* +%TO.C,C6*% +X173413748Y-102970000D02* +X173936252Y-102970000D01* +X173413748Y-101500000D02* +X173936252Y-101500000D01* +%TO.C,R3*% +X176025436Y-123290000D02* +X176479564Y-123290000D01* +X176025436Y-121820000D02* +X176479564Y-121820000D01* +%TO.C,C19*% +X145515000Y-119438748D02* +X145515000Y-119961252D01* +X144045000Y-119438748D02* +X144045000Y-119961252D01* +%TO.C,U3*% +X118110000Y-103160000D02* +X116310000Y-103160000D01* +X118110000Y-100040000D02* +X118910000Y-100040000D01* +X118110000Y-103160000D02* +X118910000Y-103160000D01* +X118110000Y-100040000D02* +X117310000Y-100040000D01* +%TO.C,Q2*% +X130645000Y-107620000D02* +X132945000Y-107620000D01* +X132245000Y-110820000D02* +X130645000Y-110820000D01* +%TO.C,R24*% +X131217936Y-113130000D02* +X131672064Y-113130000D01* +X131217936Y-111660000D02* +X131672064Y-111660000D01* +%TO.C,R1*% +X131217936Y-103405000D02* +X131672064Y-103405000D01* +X131217936Y-104875000D02* +X131672064Y-104875000D01* +%TO.C,C7*% +X184050000Y-130751252D02* +X184050000Y-130228748D01* +X185520000Y-130751252D02* +X185520000Y-130228748D01* +%TO.C,R16*% +X116105000Y-120700436D02* +X116105000Y-121154564D01* +X117575000Y-120700436D02* +X117575000Y-121154564D01* +%TO.C,R13*% +X179170000Y-110082064D02* +X179170000Y-109627936D01* +X177700000Y-110082064D02* +X177700000Y-109627936D01* +D10* +%TO.C,U7*% +X152565000Y-102900000D02* +X148425000Y-102900000D01* +X153495000Y-97760000D02* +X148425000Y-97760000D01* +D13* +%TO.C,R21*% +X174852064Y-114835000D02* +X174397936Y-114835000D01* +X174852064Y-116305000D02* +X174397936Y-116305000D01* +%TO.C,C3*% +X187860000Y-105783748D02* +X187860000Y-106306252D01* +X189330000Y-105783748D02* +X189330000Y-106306252D01* +%TO.C,R2*% +X122782064Y-101500000D02* +X122327936Y-101500000D01* +X122782064Y-102970000D02* +X122327936Y-102970000D01* +%TO.C,JP1*% +X148445000Y-126065000D02* +X148445000Y-126665000D01* +X151895000Y-125365000D02* +X149095000Y-125365000D01* +X152545000Y-126665000D02* +X152545000Y-126065000D01* +X149095000Y-127365000D02* +X151895000Y-127365000D01* +X149145000Y-125365000D02* +G75* +G03* +X148445000Y-126065000I0J-700000D01* +G01* +X148445000Y-126665000D02* +G75* +G03* +X149145000Y-127365000I700000J0D01* +G01* +X151845000Y-127365000D02* +G75* +G03* +X152545000Y-126665000I1J699999D01* +G01* +X152545000Y-126065000D02* +G75* +G03* +X151845000Y-125365000I-699999J1D01* +G01* +%TO.C,C8*% +X173093748Y-90837500D02* +X173616252Y-90837500D01* +X173093748Y-92307500D02* +X173616252Y-92307500D01* +%TO.C,R5*% +X176025436Y-119280000D02* +X176479564Y-119280000D01* +X176025436Y-120750000D02* +X176479564Y-120750000D01* +%TO.C,R11*% +X180463564Y-83593000D02* +X180009436Y-83593000D01* +X180463564Y-85063000D02* +X180009436Y-85063000D01* +%TO.C,C5*% +X184177000Y-84066748D02* +X184177000Y-84589252D01* +X185647000Y-84066748D02* +X185647000Y-84589252D01* +%TO.C,R18*% +X169317936Y-124995000D02* +X169772064Y-124995000D01* +X169317936Y-126465000D02* +X169772064Y-126465000D01* +%TO.C,R19*% +X169772064Y-130710000D02* +X169317936Y-130710000D01* +X169772064Y-132180000D02* +X169317936Y-132180000D01* +%TO.C,C13*% +X118686252Y-115035000D02* +X118163748Y-115035000D01* +X118686252Y-113565000D02* +X118163748Y-113565000D01* +%TO.C,U4*% +X178638200Y-116636800D02* +X178638200Y-116144741D01* +X182041800Y-116636800D02* +X181549741Y-116636800D01* +X181549741Y-113233200D02* +X182041800Y-113233200D01* +X178638200Y-113233200D02* +X179130259Y-113233200D01* +X182041800Y-116144741D02* +X182041800Y-116636800D01* +X182041800Y-113233200D02* +X182041800Y-113725259D01* +X179130259Y-116636800D02* +X178638200Y-116636800D01* +X178638200Y-113725259D02* +X178638200Y-113233200D01* +G36* +X178206400Y-115375500D02* +G01* +X177952400Y-115375500D01* +X177952400Y-114994499D01* +X178206400Y-114994499D01* +X178206400Y-115375500D01* +G37* +D14* +X178206400Y-115375500D02* +X177952400Y-115375500D01* +X177952400Y-114994499D01* +X178206400Y-114994499D01* +X178206400Y-115375500D01* +D13* +%TO.C,R9*% +X180112936Y-119661000D02* +X180567064Y-119661000D01* +X180112936Y-121131000D02* +X180567064Y-121131000D01* +%TO.C,R14*% +X184250000Y-110082064D02* +X184250000Y-109627936D01* +X182780000Y-110082064D02* +X182780000Y-109627936D01* +%TO.C,R29*% +X162660000Y-114884564D02* +X162660000Y-114430436D01* +X161190000Y-114884564D02* +X161190000Y-114430436D01* +%TO.C,C10*% +X166270000Y-86231248D02* +X166270000Y-86753752D01* +X167740000Y-86231248D02* +X167740000Y-86753752D01* +%TO.C,R26*% +X149125000Y-122147064D02* +X149125000Y-121692936D01* +X150595000Y-122147064D02* +X150595000Y-121692936D01* +%TO.C,R28*% +X163730000Y-114430436D02* +X163730000Y-114884564D01* +X165200000Y-114430436D02* +X165200000Y-114884564D01* +%TO.C,R8*% +X184177000Y-88619064D02* +X184177000Y-88164936D01* +X185647000Y-88619064D02* +X185647000Y-88164936D01* +%TO.C,R6*% +X122782064Y-100430000D02* +X122327936Y-100430000D01* +X122782064Y-98960000D02* +X122327936Y-98960000D01* +%TO.C,R25*% +X135990000Y-109447064D02* +X135990000Y-108992936D01* +X134520000Y-109447064D02* +X134520000Y-108992936D01* +%TO.C,R27*% +X167740000Y-114884564D02* +X167740000Y-114430436D01* +X166270000Y-114884564D02* +X166270000Y-114430436D01* +%TO.C,C14*% +X129801252Y-90905000D02* +X129278748Y-90905000D01* +X129801252Y-89435000D02* +X129278748Y-89435000D01* +%TO.C,R23*% +X121639000Y-120700436D02* +X121639000Y-121154564D01* +X120169000Y-120700436D02* +X120169000Y-121154564D01* +%TO.C,R12*% +X181710000Y-110082064D02* +X181710000Y-109627936D01* +X180240000Y-110082064D02* +X180240000Y-109627936D01* +%TO.C,C15*% +X123725000Y-128846252D02* +X123725000Y-128323748D01* +X125195000Y-128846252D02* +X125195000Y-128323748D01* +%TO.C,C12*% +X150695252Y-95731000D02* +X150172748Y-95731000D01* +X150695252Y-94261000D02* +X150172748Y-94261000D01* +%TO.C,C1*% +X113565000Y-101861252D02* +X113565000Y-101338748D01* +X115035000Y-101861252D02* +X115035000Y-101338748D01* +%TO.C,Q1*% +X132245000Y-102565000D02* +X130645000Y-102565000D01* +X130645000Y-99365000D02* +X132945000Y-99365000D01* +%TO.C,U6*% +X175550000Y-97922500D02* +X175550000Y-97122500D01* +X172430000Y-97922500D02* +X172430000Y-97122500D01* +X172430000Y-97922500D02* +X172430000Y-98722500D01* +X175550000Y-97922500D02* +X175550000Y-99722500D01* +%TO.C,C9*% +X178061252Y-102970000D02* +X177538748Y-102970000D01* +X178061252Y-101500000D02* +X177538748Y-101500000D01* +%TO.C,C11*% +X177700000Y-97528748D02* +X177700000Y-98051252D01* +X179170000Y-97528748D02* +X179170000Y-98051252D01* +%TO.C,C18*% +X158650000Y-114876252D02* +X158650000Y-114353748D01* +X160120000Y-114876252D02* +X160120000Y-114353748D01* +%TO.C,R22*% +X119607000Y-120700436D02* +X119607000Y-121154564D01* +X118137000Y-120700436D02* +X118137000Y-121154564D01* +%TO.C,U5*% +X173355000Y-89052500D02* +X171405000Y-89052500D01* +X173355000Y-83932500D02* +X176805000Y-83932500D01* +X173355000Y-83932500D02* +X171405000Y-83932500D01* +X173355000Y-89052500D02* +X175305000Y-89052500D01* +%TO.C,C16*% +X152981252Y-123290000D02* +X152458748Y-123290000D01* +X152981252Y-121820000D02* +X152458748Y-121820000D01* +%TO.C,R4*% +X122782064Y-104040000D02* +X122327936Y-104040000D01* +X122782064Y-105510000D02* +X122327936Y-105510000D01* +%TO.C,C2*% +X118686252Y-106580000D02* +X118163748Y-106580000D01* +X118686252Y-108050000D02* +X118163748Y-108050000D01* +%TO.C,R15*% +X168810000Y-97695436D02* +X168810000Y-98149564D01* +X170280000Y-97695436D02* +X170280000Y-98149564D01* +%TO.C,R20*% +X169317936Y-128170000D02* +X169772064Y-128170000D01* +X169317936Y-129640000D02* +X169772064Y-129640000D01* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-Edge_Cuts.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-Edge_Cuts.gbr new file mode 100644 index 0000000..188dfa8 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-Edge_Cuts.gbr @@ -0,0 +1,175 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Profile,NP*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Adhesive.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Adhesive.gbr new file mode 100644 index 0000000..0480dc5 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Adhesive.gbr @@ -0,0 +1,176 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Glue,Top*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Courtyard.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Courtyard.gbr new file mode 100644 index 0000000..acd8446 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Courtyard.gbr @@ -0,0 +1,414 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Other,User*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12C,0.120000*% +%ADD13C,0.050000*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.C,M1*% +X142650000Y-139000000D02* +X142650000Y-121000000D01* +X157650000Y-121000000D02* +X159150000Y-121000000D01* +X142650000Y-121000000D02* +X157650000Y-121000000D01* +X134150000Y-143000000D02* +X166150000Y-143000000D01* +X166150000Y-143000000D02* +X166150000Y-150000000D01* +X146650000Y-143000000D02* +X146650000Y-139000000D01* +X156150000Y-109000000D02* +X156150000Y-121000000D01* +X144150000Y-109000000D02* +X156150000Y-109000000D01* +X142650000Y-125500000D02* +X142650000Y-130000000D01* +X142650000Y-130000000D02* +X141150000Y-130000000D01* +X153650000Y-139000000D02* +X153650000Y-143000000D01* +X157650000Y-121000000D02* +X157650000Y-139000000D01* +X157650000Y-130000000D02* +X159150000Y-130000000D01* +X147150000Y-139000000D02* +X154150000Y-139000000D01* +X134150000Y-150000000D02* +X134150000Y-143000000D01* +X157650000Y-139000000D02* +X142650000Y-139000000D01* +X166150000Y-150000000D02* +X134150000Y-150000000D01* +X142650000Y-121000000D02* +X141150000Y-121000000D01* +X144150000Y-121000000D02* +X144150000Y-109000000D01* +X141150000Y-121000000D02* +G75* +G03* +X141150000Y-130000000I0J-4500000D01* +G01* +X159150000Y-130000000D02* +G75* +G03* +X159150000Y-121000000I0J4500000D01* +G01* +X143400000Y-125500000D02* +G75* +G03* +X143400000Y-125500000I-2000000J0D01* +G01* +X161150000Y-125500000D02* +G75* +G03* +X161150000Y-125500000I-2000000J0D01* +G01* +D13* +%TO.C,SW1*% +X118134202Y-84496404D02* +X113233666Y-81999456D01* +X121675328Y-77546553D02* +X116774792Y-75049605D01* +X121675328Y-77546553D02* +X118134202Y-84496404D01* +X116774792Y-75049605D02* +X113233666Y-81999456D01* +%TO.C,J1*% +X134680000Y-76310000D02* +X124780000Y-76310000D01* +X134680000Y-92600000D02* +X134680000Y-76310000D01* +X124780000Y-76310000D02* +X124780000Y-92600000D01* +X124780000Y-92600000D02* +X134680000Y-92600000D01* +%TO.C,D2*% +X169390000Y-83510000D02* +X165890000Y-83510000D01* +X169390000Y-76510000D02* +X169390000Y-83510000D01* +X165890000Y-76510000D02* +X169390000Y-76510000D01* +X165890000Y-83510000D02* +X165890000Y-76510000D01* +%TO.C,D5*% +X116620077Y-135647724D02* +X115670077Y-134002276D01* +X118579923Y-132322276D02* +X119529923Y-133967724D01* +X119529923Y-133967724D02* +X116620077Y-135647724D01* +X115670077Y-134002276D02* +X118579923Y-132322276D01* +D12* +%TO.C,M2*% +X153900000Y-69000000D02* +X153900000Y-73000000D01* +X144400000Y-103000000D02* +X144400000Y-91000000D01* +X146900000Y-73000000D02* +X146900000Y-69000000D01* +X142900000Y-91000000D02* +X142900000Y-73000000D01* +X157900000Y-91000000D02* +X142900000Y-91000000D01* +X134400000Y-62000000D02* +X166400000Y-62000000D01* +X156400000Y-103000000D02* +X144400000Y-103000000D01* +X134400000Y-69000000D02* +X134400000Y-62000000D01* +X156400000Y-91000000D02* +X156400000Y-103000000D01* +X142900000Y-82000000D02* +X141400000Y-82000000D01* +X157900000Y-86500000D02* +X157900000Y-82000000D01* +X166400000Y-62000000D02* +X166400000Y-69000000D01* +X157900000Y-73000000D02* +X157900000Y-91000000D01* +X153400000Y-73000000D02* +X146400000Y-73000000D01* +X142900000Y-91000000D02* +X141400000Y-91000000D01* +X142900000Y-73000000D02* +X157900000Y-73000000D01* +X166400000Y-69000000D02* +X134400000Y-69000000D01* +X157900000Y-82000000D02* +X159400000Y-82000000D01* +X157900000Y-91000000D02* +X159400000Y-91000000D01* +X141400000Y-82000000D02* +G75* +G03* +X141400000Y-91000000I0J-4500000D01* +G01* +X159400000Y-91000000D02* +G75* +G03* +X159400000Y-82000000I0J4500000D01* +G01* +X143400000Y-86500000D02* +G75* +G03* +X143400000Y-86500000I-2000000J0D01* +G01* +X161150000Y-86500000D02* +G75* +G03* +X161150000Y-86500000I-2000000J0D01* +G01* +%TO.C,BT1*% +X172500000Y-136000000D02* +X188500000Y-136000000D01* +X188500000Y-136000000D02* +X188500000Y-76000000D01* +X188500000Y-76000000D02* +X172500000Y-76000000D01* +X172500000Y-76000000D02* +X172500000Y-136000000D01* +D13* +%TO.C,J2*% +X124780000Y-135600000D02* +X134680000Y-135600000D01* +X134680000Y-119310000D02* +X124780000Y-119310000D01* +X134680000Y-135600000D02* +X134680000Y-119310000D01* +X124780000Y-119310000D02* +X124780000Y-135600000D01* +%TO.C,P1*% +X190645000Y-100750000D02* +X198355000Y-100750000D01* +X198355000Y-111300000D02* +X198355000Y-100750000D01* +X190645000Y-111300000D02* +X190645000Y-100750000D01* +X190645000Y-111300000D02* +X198355000Y-111300000D01* +%TO.C,J3*% +X160165000Y-109745000D02* +X168765000Y-109745000D01* +X168765000Y-102345000D02* +X160165000Y-102345000D01* +X160165000Y-102345000D02* +X160165000Y-109745000D01* +X168765000Y-109745000D02* +X168765000Y-102345000D01* +%TO.C,L2*% +X164755000Y-89825000D02* +X164755000Y-94325000D01* +X169255000Y-94325000D02* +X169255000Y-89825000D01* +X164755000Y-94325000D02* +X169255000Y-94325000D01* +X169255000Y-89825000D02* +X164755000Y-89825000D01* +D12* +%TO.C,U1*% +X111835000Y-101200000D02* +X118335000Y-93600000D01* +X111835000Y-110400000D02* +X118335000Y-118000000D01* +X139435000Y-118000000D02* +X139435000Y-93600000D01* +X111835000Y-110400000D02* +X111835000Y-101200000D01* +X139435000Y-93600000D02* +X118335000Y-93600000D01* +X139435000Y-118000000D02* +X118335000Y-118000000D01* +D13* +%TO.C,D4*% +X118388923Y-132062724D02* +X115479077Y-133742724D01* +X115479077Y-133742724D02* +X114529077Y-132097276D01* +X114529077Y-132097276D02* +X117438923Y-130417276D01* +X117438923Y-130417276D02* +X118388923Y-132062724D01* +%TO.C,D3*% +X113470077Y-130192276D02* +X116379923Y-128512276D01* +X117329923Y-130157724D02* +X114420077Y-131837724D01* +X116379923Y-128512276D02* +X117329923Y-130157724D01* +X114420077Y-131837724D02* +X113470077Y-130192276D01* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Cu.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Cu.gbr new file mode 100644 index 0000000..7b541e4 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Cu.gbr @@ -0,0 +1,1433 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L1,Top*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +%AMRotRect* +0 Rectangle, with rotation* +0 The origin of the aperture is its center* +0 $1 length* +0 $2 width* +0 $3 Rotation angle, in degrees counterclockwise* +0 Add horizontal line* +21,1,$1,$2,0,0,$3*% +G04 Aperture macros list end* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD12RotRect,1.550000X1.000000X243.000000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD13RoundRect,0.250000X0.600000X0.600000X-0.600000X0.600000X-0.600000X-0.600000X0.600000X-0.600000X0*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD14C,1.700000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD15R,1.800000X2.500000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD16RoundRect,0.243750X0.017031X-0.516999X0.439219X-0.273249X-0.017031X0.516999X-0.439219X0.273249X0*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD17C,3.500000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD18R,1.200000X0.700000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD19R,1.200000X0.760000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD20R,1.200000X0.800000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD21O,1.700000X1.100000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD22R,2.400000X0.740000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD23R,1.200000X3.700000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD24R,1.200000X1.200000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD25C,1.200000*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD26C,0.800000*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD27C,0.900000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD28C,0.250000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD29C,0.700000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD30C,0.400000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD31C,0.300000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD32C,1.000000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD33C,0.500000*% +%TD*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.P,SW1,1,1*% +%TO.N,GND*% +X118334370Y-77275216D03* +X115950919Y-81953000D03* +%TO.P,SW1,2,2*% +%TO.N,Net-(SW1-Pad2)*% +X119849081Y-78047000D03* +X117465630Y-82724784D03* +%TD*% +D13* +%TO.P,J1,1,Pin_1*% +%TO.N,/Cpu/OUTGAUCHE_A*% +X131000000Y-87000000D03* +D14* +%TO.P,J1,2,Pin_2*% +%TO.N,/Cpu/OUTGAUCHE_B*% +X128460000Y-87000000D03* +%TO.P,J1,3,Pin_3*% +%TO.N,Net-(J1-Pad3)*% +X131000000Y-84460000D03* +%TO.P,J1,4,Pin_4*% +%TO.N,/Cpu/ENCGAUCHE_A*% +X128460000Y-84460000D03* +%TO.P,J1,5,Pin_5*% +%TO.N,/Cpu/ENCGAUCHE_B*% +X131000000Y-81920000D03* +%TO.P,J1,6,Pin_6*% +%TO.N,GND*% +X128460000Y-81920000D03* +%TD*% +D15* +%TO.P,D2,1,K*% +%TO.N,+5V*% +X167640000Y-78010000D03* +%TO.P,D2,2,A*% +%TO.N,Net-(D2-Pad2)*% +X167640000Y-82010000D03* +%TD*% +D16* +%TO.P,D5,1,K*% +%TO.N,GND*% +X116788101Y-134453750D03* +%TO.P,D5,2,A*% +%TO.N,Net-(D5-Pad2)*% +X118411899Y-133516250D03* +%TD*% +D17* +%TO.P,BT1,1,+*% +%TO.N,+BATT*% +X180500000Y-124250000D03* +X180500000Y-131850000D03* +%TO.P,BT1,2,-*% +%TO.N,GND*% +X180500000Y-80150000D03* +X180500000Y-87750000D03* +%TD*% +D13* +%TO.P,J2,1,Pin_1*% +%TO.N,/Cpu/OUTDROIT_A*% +X131000000Y-130000000D03* +D14* +%TO.P,J2,2,Pin_2*% +%TO.N,/Cpu/OUTDROIT_B*% +X128460000Y-130000000D03* +%TO.P,J2,3,Pin_3*% +%TO.N,Net-(J1-Pad3)*% +X131000000Y-127460000D03* +%TO.P,J2,4,Pin_4*% +%TO.N,/Cpu/ENCDROIT_A*% +X128460000Y-127460000D03* +%TO.P,J2,5,Pin_5*% +%TO.N,/Cpu/ENCDROIT_B*% +X131000000Y-124920000D03* +%TO.P,J2,6,Pin_6*% +%TO.N,GND*% +X128460000Y-124920000D03* +%TD*% +D18* +%TO.P,P1,A5,CC1*% +%TO.N,unconnected-(P1-PadA5)*% +X191835000Y-106530000D03* +D19* +%TO.P,P1,A9,VBUS*% +%TO.N,VBUS*% +X191835000Y-104510000D03* +D20* +%TO.P,P1,A12,GND*% +%TO.N,GND*% +X191835000Y-103280000D03* +D18* +%TO.P,P1,B5,CC2*% +%TO.N,unconnected-(P1-PadB5)*% +X191835000Y-105530000D03* +D19* +%TO.P,P1,B9,VBUS*% +%TO.N,VBUS*% +X191835000Y-107550000D03* +D20* +%TO.P,P1,B12,GND*% +%TO.N,GND*% +X191835000Y-108780000D03* +D21* +%TO.P,P1,S1,SHIELD*% +X191835000Y-101710000D03* +X195635000Y-110350000D03* +X195635000Y-101700000D03* +X191835000Y-110350000D03* +%TD*% +D22* +%TO.P,J3,1,Pin_1*% +%TO.N,+2V5*% +X162515000Y-103505000D03* +%TO.P,J3,2,Pin_2*% +%TO.N,/Cpu/SWDIO*% +X166415000Y-103505000D03* +%TO.P,J3,3,Pin_3*% +%TO.N,GND*% +X162515000Y-104775000D03* +%TO.P,J3,4,Pin_4*% +%TO.N,/Cpu/SWCLK*% +X166415000Y-104775000D03* +%TO.P,J3,5,Pin_5*% +%TO.N,GND*% +X162515000Y-106045000D03* +%TO.P,J3,6,Pin_6*% +%TO.N,unconnected-(J3-Pad6)*% +X166415000Y-106045000D03* +%TO.P,J3,7,Pin_7*% +%TO.N,unconnected-(J3-Pad7)*% +X162515000Y-107315000D03* +%TO.P,J3,8,Pin_8*% +%TO.N,unconnected-(J3-Pad8)*% +X166415000Y-107315000D03* +%TO.P,J3,9,Pin_9*% +%TO.N,GND*% +X162515000Y-108585000D03* +%TO.P,J3,10,Pin_10*% +%TO.N,/Cpu/RESET*% +X166415000Y-108585000D03* +%TD*% +D23* +%TO.P,L2,1,1*% +%TO.N,Net-(C6-Pad1)*% +X168405000Y-92075000D03* +%TO.P,L2,2,2*% +%TO.N,Net-(D2-Pad2)*% +X165605000Y-92075000D03* +%TD*% +D24* +%TO.P,U1,1,VCC*% +%TO.N,+2V5*% +X119435000Y-116800000D03* +D25* +%TO.P,U1,2,DOUT*% +%TO.N,/Cpu/USART_RX*% +X121435000Y-116800000D03* +%TO.P,U1,3,DIN*% +%TO.N,/Cpu/USART_TX*% +X123435000Y-116800000D03* +%TO.P,U1,4,DIO12*% +%TO.N,unconnected-(U1-Pad4)*% +X125435000Y-116800000D03* +%TO.P,U1,5,~{RESET}*% +%TO.N,/Cpu/XBEE_RESET*% +X127435000Y-116800000D03* +%TO.P,U1,6,RSSI*% +%TO.N,unconnected-(U1-Pad6)*% +X129435000Y-116800000D03* +%TO.P,U1,7,DIO11*% +%TO.N,unconnected-(U1-Pad7)*% +X131435000Y-116800000D03* +%TO.P,U1,8*% +%TO.N,N/C*% +X133435000Y-116800000D03* +%TO.P,U1,9,~{DTR}/SLEEP_REQ*% +%TO.N,unconnected-(U1-Pad9)*% +X135435000Y-116800000D03* +%TO.P,U1,10,GND*% +%TO.N,GND*% +X137435000Y-116800000D03* +%TO.P,U1,11,DIO4*% +%TO.N,unconnected-(U1-Pad11)*% +X137435000Y-94800000D03* +%TO.P,U1,12,~{CTS}*% +%TO.N,unconnected-(U1-Pad12)*% +X135435000Y-94800000D03* +%TO.P,U1,13,~{SLEEP}*% +%TO.N,unconnected-(U1-Pad13)*% +X133435000Y-94800000D03* +%TO.P,U1,14*% +%TO.N,N/C*% +X131435000Y-94800000D03* +%TO.P,U1,15,ASSOCIATE*% +%TO.N,unconnected-(U1-Pad15)*% +X129435000Y-94800000D03* +%TO.P,U1,16,~{RTS}*% +%TO.N,unconnected-(U1-Pad16)*% +X127435000Y-94800000D03* +%TO.P,U1,17,DIO3*% +%TO.N,unconnected-(U1-Pad17)*% +X125435000Y-94800000D03* +%TO.P,U1,18,DIO2*% +%TO.N,unconnected-(U1-Pad18)*% +X123435000Y-94800000D03* +%TO.P,U1,19,DIO1*% +%TO.N,unconnected-(U1-Pad19)*% +X121435000Y-94800000D03* +%TO.P,U1,20,DIO0*% +%TO.N,unconnected-(U1-Pad20)*% +X119435000Y-94800000D03* +%TD*% +D16* +%TO.P,D4,1,K*% +%TO.N,GND*% +X115647101Y-132548750D03* +%TO.P,D4,2,A*% +%TO.N,Net-(D4-Pad2)*% +X117270899Y-131611250D03* +%TD*% +%TO.P,D3,1,K*% +%TO.N,GND*% +X114588101Y-130643750D03* +%TO.P,D3,2,A*% +%TO.N,Net-(D3-Pad2)*% +X116211899Y-129706250D03* +%TD*% +D26* +%TO.N,/Cpu/BUTTON_SENSE*% +X114300000Y-110490000D03* +X119380000Y-97040500D03* +X113030000Y-95885000D03* +X119380000Y-99060000D03* +%TO.N,/Power_Charge/Sense_BATT*% +X187960000Y-111125000D03* +X188595000Y-113570500D03* +X167005000Y-133350000D03* +X139065000Y-95250000D03* +%TO.N,+BATT*% +X114935000Y-106045000D03* +X116840000Y-104140000D03* +%TO.N,/Cpu/SHUTDOWN*% +X121285000Y-109220000D03* +X111760000Y-105410000D03* +D27* +%TO.N,+BATT*% +X171704000Y-115570000D03* +D26* +X153035000Y-96520000D03* +X125095000Y-97790000D03* +D27* +%TO.N,GND*% +X117475000Y-116840000D03* +D26* +X162560000Y-109855000D03* +X149860000Y-100330000D03* +X173990000Y-100584000D03* +X153350000Y-105095000D03* +X163195000Y-112395000D03* +D27* +X112776000Y-99060000D03* +D26* +%TO.N,VBUS*% +X142404500Y-94996000D03* +X169164000Y-110236000D03* +D27* +X194310000Y-105410000D03* +X183515000Y-113030000D03* +X177165000Y-116840000D03* +D26* +X164084000Y-97536000D03* +X170561000Y-117729000D03* +D27* +X179705000Y-111760000D03* +D26* +%TO.N,+2V5*% +X159385000Y-103505000D03* +X166370000Y-117475000D03* +X143764000Y-117348000D03* +X151387793Y-114811542D03* +X180225500Y-96520000D03* +X148860122Y-112764776D03* +X151892000Y-112268000D03* +X171704000Y-120015000D03* +D27* +%TO.N,+5V*% +X164465000Y-78105000D03* +D26* +X175260000Y-78232000D03* +%TO.N,Net-(C9-Pad1)*% +X171450000Y-95250000D03* +X180340000Y-95250000D03* +D27* +%TO.N,Net-(D2-Pad2)*% +X170815000Y-82550000D03* +D26* +%TO.N,/Cpu/RESET*% +X139700000Y-121195500D03* +X154940000Y-129629500D03* +X155575000Y-123190000D03* +X144145000Y-113030000D03* +X166370000Y-111125000D03* +%TO.N,Net-(J1-Pad3)*% +X127000000Y-99695000D03* +X127000000Y-109220000D03* +X133350000Y-88900000D03* +X126365000Y-117945500D03* +X127000000Y-104775000D03* +%TO.N,Net-(R7-Pad2)*% +X178308000Y-117856000D03* +X174625000Y-111125000D03* +%TO.N,/Cpu/OUTDROIT_A*% +X145415000Y-101600000D03* +X112776000Y-106680000D03* +%TO.N,/Cpu/OUTDROIT_B*% +X113665000Y-107950000D03* +X146050000Y-102870000D03* +%TO.N,Net-(SW1-Pad2)*% +X118110000Y-99060000D03* +%TO.N,Net-(D3-Pad2)*% +X116840000Y-126365000D03* +%TO.N,Net-(D4-Pad2)*% +X118745000Y-126365000D03* +%TO.N,Net-(D5-Pad2)*% +X120650000Y-126365000D03* +%TO.N,/Cpu/ENCGAUCHE_A*% +X144272000Y-99060000D03* +X141605000Y-104140000D03* +X138430000Y-109855000D03* +X138340500Y-114935000D03* +X144272000Y-104140000D03* +X140208000Y-99060000D03* +%TO.N,/Cpu/ENCDROIT_A*% +X127635000Y-114210500D03* +X139259800Y-108779800D03* +%TO.N,/Cpu/ENCDROIT_B*% +X149860000Y-113792000D03* +%TO.N,/Cpu/LED_ROUGE*% +X156845000Y-109220000D03* +X115570000Y-118110000D03* +%TO.N,/Cpu/LED_ORANGE*% +X156845000Y-110490000D03* +X122555000Y-121285000D03* +%TO.N,/Cpu/LED_VERTE*% +X158115000Y-109855000D03* +X124460000Y-121920000D03* +%TO.N,/Cpu/USART_RX*% +X135255000Y-112395000D03* +X151995500Y-106045000D03* +%TO.N,/Cpu/USART_TX*% +X135979500Y-113101755D03* +X151520500Y-106997462D03* +%TO.N,/Cpu/XBEE_RESET*% +X136525000Y-117945500D03* +X142710500Y-120650000D03* +X152469500Y-118745000D03* +X138340500Y-115934503D03* +%TO.N,/Cpu/CHARGER_ST1*% +X182880000Y-116205000D03* +X176530000Y-124460000D03* +%TO.N,/Cpu/SHUTDOWN*% +X135890000Y-125095000D03* +X146050000Y-121830500D03* +%TO.N,/Cpu/CHARGER_ST2*% +X171704000Y-118745000D03* +X156210000Y-120015000D03* +X151020500Y-118745000D03* +X169545000Y-118745000D03* +X182880000Y-114935000D03* +X178816000Y-118872000D03* +%TO.N,/Cpu/PWM_GAUCHE_B*% +X146812000Y-105955500D03* +X154940000Y-99060000D03* +%TO.N,/Cpu/BUTTON_SENSE*% +X150368000Y-115570000D03* +X115387601Y-121285000D03* +%TO.N,/Cpu/BATTERY_SENSE*% +X148844000Y-111252000D03* +X157983701Y-122423701D03* +X167132000Y-125984000D03* +X168632500Y-130071500D03* +%TO.N,/Cpu/SHUTDOWN_ENC*% +X137160000Y-108204000D03* +X159385000Y-110490000D03* +%TO.N,/Cpu/SWDIO*% +X156395480Y-118295480D03* +X152908000Y-113030000D03* +X171450000Y-104775000D03* +%TO.N,/Cpu/SWCLK*% +X160020000Y-117475000D03* +X167005000Y-112395000D03* +X170180000Y-105410000D03* +%TO.N,/Cpu/SHUTDOWN_5V*% +X173990000Y-88265000D03* +X186690000Y-110490000D03* +X186690000Y-113284000D03* +X147320000Y-121830500D03* +%TO.N,Net-(C6-Pad1)*% +X176530000Y-98425000D03* +D27* +X170180000Y-92710000D03* +D26* +X171225000Y-98835000D03* +X141224000Y-93980000D03* +%TD*% +D28* +%TO.N,/Cpu/ENCGAUCHE_A*% +X140208000Y-99060000D02* +X144272000Y-99060000D01* +D29* +%TO.N,Net-(C6-Pad1)*% +X141224000Y-93980000D02* +X141859000Y-93345000D01* +X141859000Y-93345000D02* +X153670000Y-93345000D01* +X153670000Y-93345000D02* +X156210000Y-95885000D01* +X156210000Y-95885000D02* +X167640000Y-95885000D01* +X167640000Y-95885000D02* +X168405000Y-95120000D01* +X168405000Y-95120000D02* +X168405000Y-92075000D01* +D30* +%TO.N,VBUS*% +X142404500Y-94996000D02* +X153203150Y-94996000D01* +X153203150Y-94996000D02* +X155235150Y-97028000D01* +X155235150Y-97028000D02* +X163576000Y-97028000D01* +X163576000Y-97028000D02* +X164084000Y-97536000D01* +D28* +%TO.N,/Cpu/BUTTON_SENSE*% +X111085000Y-97195000D02* +X112395000Y-95885000D01* +X114300000Y-110490000D02* +X111760000Y-110490000D01* +X112395000Y-95885000D02* +X113030000Y-95885000D01* +X111085000Y-103545000D02* +X111085000Y-97195000D01* +X111085000Y-109815000D02* +X111085000Y-103545000D01* +X119380000Y-97040500D02* +X119380000Y-99060000D01* +X111760000Y-110490000D02* +X111085000Y-109815000D01* +D31* +%TO.N,/Cpu/SHUTDOWN*% +X121285000Y-109220000D02* +X111760000Y-109220000D01* +X111760000Y-109220000D02* +X111760000Y-105410000D01* +D30* +%TO.N,/Power_Charge/Sense_BATT*% +X139700000Y-89535000D02* +X149860000Y-89535000D01* +X150495000Y-88900000D02* +X150495000Y-74930000D01* +X149860000Y-89535000D02* +X150495000Y-88900000D01* +X188595000Y-135890000D02* +X186055000Y-138430000D01* +X188595000Y-113570500D02* +X188595000Y-135890000D01* +X180340000Y-74295000D02* +X182245000Y-74295000D01* +X151130000Y-74295000D02* +X180340000Y-74295000D01* +X167005000Y-137795000D02* +X167005000Y-133350000D01* +X188595000Y-110490000D02* +X187960000Y-111125000D01* +X139065000Y-90170000D02* +X139700000Y-89535000D01* +X186055000Y-138430000D02* +X167640000Y-138430000D01* +X167640000Y-138430000D02* +X167005000Y-137795000D01* +X182245000Y-74295000D02* +X187960000Y-80010000D01* +X188595000Y-80645000D02* +X188595000Y-110490000D01* +X150495000Y-74930000D02* +X151130000Y-74295000D01* +X187960000Y-80010000D02* +X188595000Y-80645000D01* +X139065000Y-95250000D02* +X139065000Y-90170000D01* +%TO.N,+BATT*% +X114935000Y-106045000D02* +X116840000Y-104140000D01* +%TO.N,/Cpu/OUTDROIT_A*% +X116065680Y-102235000D02* +X116700680Y-101600000D01* +X112776000Y-106680000D02* +X112776000Y-102235000D01* +X112776000Y-102235000D02* +X116065680Y-102235000D01* +X116700680Y-101600000D02* +X145415000Y-101600000D01* +D29* +%TO.N,+BATT*% +X174277000Y-126652000D02* +X180500000Y-126652000D01* +X126606699Y-100644511D02* +X125095000Y-99132812D01* +X136244270Y-96520000D02* +X132119759Y-100644511D01* +X153035000Y-96520000D02* +X136244270Y-96520000D01* +X132119759Y-100644511D02* +X126606699Y-100644511D01* +D32* +X180500000Y-126652000D02* +X180500000Y-131850000D01* +X180500000Y-124250000D02* +X180500000Y-126652000D01* +D29* +X125095000Y-99132812D02* +X125095000Y-97790000D01* +X173355000Y-125730000D02* +X174277000Y-126652000D01* +X171704000Y-115570000D02* +X173355000Y-117221000D01* +X173355000Y-117221000D02* +X173355000Y-125730000D01* +D30* +%TO.N,GND*% +X118110000Y-118745000D02* +X117475000Y-118110000D01* +X165100000Y-100584000D02* +X173990000Y-100584000D01* +X190060000Y-108780000D02* +X189865000Y-108585000D01* +X163195000Y-112395000D02* +X162515000Y-111715000D01* +X189865000Y-108585000D02* +X189865000Y-103505000D01* +D29* +X191835000Y-103280000D02* +X191835000Y-101710000D01* +D30* +X191835000Y-108780000D02* +X190060000Y-108780000D01* +X118745000Y-75565000D02* +X127635000Y-75565000D01* +X118334370Y-77275216D02* +X118334370Y-75975630D01* +X137435000Y-116800000D02* +X137435000Y-118470000D01* +X137160000Y-118745000D02* +X118110000Y-118745000D01* +X164465000Y-105410000D02* +X164465000Y-107734022D01* +D29* +X153350000Y-105095000D02* +X150180000Y-105095000D01* +D30* +X115824000Y-94488000D02* +X115824000Y-82079919D01* +X162515000Y-104775000D02* +X163830000Y-104775000D01* +X114588101Y-130643750D02* +X114588101Y-117821899D01* +X163614022Y-108585000D02* +X162515000Y-108585000D01* +X114588101Y-117821899D02* +X115570000Y-116840000D01* +X189865000Y-103505000D02* +X190090000Y-103280000D01* +X118334370Y-75975630D02* +X118745000Y-75565000D01* +X115824000Y-82079919D02* +X115950919Y-81953000D01* +X190090000Y-103280000D02* +X191835000Y-103280000D01* +D29* +X191835000Y-110350000D02* +X191835000Y-108780000D01* +D30* +X115647101Y-133312750D02* +X116788101Y-134453750D01* +X127635000Y-75565000D02* +X128460000Y-76390000D01* +X115570000Y-81572081D02* +X115950919Y-81953000D01* +X117475000Y-118110000D02* +X117475000Y-116840000D01* +D32* +X180500000Y-80150000D02* +X180500000Y-87750000D01* +D30* +X118334370Y-77275216D02* +X115570000Y-80039586D01* +X112776000Y-97536000D02* +X115824000Y-94488000D01* +D29* +X149860000Y-104775000D02* +X149860000Y-100330000D01* +D30* +X115647101Y-132548750D02* +X115647101Y-133312750D01* +X164465000Y-105410000D02* +X164465000Y-101219000D01* +X114588101Y-131489750D02* +X115647101Y-132548750D01* +D29* +X150180000Y-105095000D02* +X149860000Y-104775000D01* +D30* +X163830000Y-104775000D02* +X164465000Y-105410000D01* +X164465000Y-101219000D02* +X165100000Y-100584000D01* +X162515000Y-104775000D02* +X162515000Y-106045000D01* +X115570000Y-116840000D02* +X117475000Y-116840000D01* +X112776000Y-99060000D02* +X112776000Y-97536000D01* +X164465000Y-107734022D02* +X163614022Y-108585000D01* +X128460000Y-76390000D02* +X128460000Y-81920000D01* +X114588101Y-130643750D02* +X114588101Y-131489750D01* +X137435000Y-118470000D02* +X137160000Y-118745000D01* +X115570000Y-80039586D02* +X115570000Y-81572081D01* +X162515000Y-111715000D02* +X162515000Y-108585000D01* +%TO.N,VBUS*% +X169164000Y-116840000D02* +X170053000Y-117729000D01* +X193548000Y-107442000D02* +X193548000Y-105537000D01* +X193548000Y-111887000D02* +X193040000Y-112395000D01* +X193040000Y-112395000D02* +X184150000Y-112395000D01* +X170053000Y-117729000D02* +X170561000Y-117729000D01* +X169164000Y-110236000D02* +X169164000Y-116840000D01* +X184150000Y-112395000D02* +X183515000Y-113030000D01* +X191835000Y-107550000D02* +X193440000Y-107550000D01* +X179705000Y-111760000D02* +X182245000Y-111760000D01* +X193440000Y-107550000D02* +X193548000Y-107658000D01* +X193548000Y-105410000D02* +X193548000Y-104648000D01* +X182245000Y-111760000D02* +X183515000Y-113030000D01* +X193548000Y-104648000D02* +X193410000Y-104510000D01* +X193548000Y-105537000D02* +X193675000Y-105410000D01* +X193410000Y-104510000D02* +X191835000Y-104510000D01* +X177165000Y-112395000D02* +X177800000Y-111760000D01* +X193440000Y-107550000D02* +X193548000Y-107442000D01* +X193548000Y-107658000D02* +X193548000Y-111887000D01* +X177800000Y-111760000D02* +X179705000Y-111760000D01* +X177165000Y-116840000D02* +X177165000Y-112395000D01* +X194310000Y-105410000D02* +X193675000Y-105410000D01* +%TO.N,+2V5*% +X166370000Y-120015000D02* +X166370000Y-117475000D01* +D33* +X151384000Y-116332000D02* +X150368000Y-117348000D01* +D31* +X151384251Y-114808000D02* +X151387793Y-114811542D01* +D33* +X159385000Y-103505000D02* +X162515000Y-103505000D01* +X150864776Y-112764776D02* +X151130000Y-113030000D01* +X151384000Y-113284000D02* +X151384000Y-114808000D01* +X150368000Y-117348000D02* +X143764000Y-117348000D01* +X151130000Y-113030000D02* +X151384000Y-113284000D01* +X179705000Y-99695000D02* +X180225500Y-99174500D01* +X148860122Y-112764776D02* +X150864776Y-112764776D01* +D30* +X171704000Y-120015000D02* +X166370000Y-120015000D01* +D33* +X151130000Y-113030000D02* +X151892000Y-112268000D01* +D31* +X151384000Y-114808000D02* +X151384251Y-114808000D01* +D33* +X163449000Y-99695000D02* +X179705000Y-99695000D01* +X151384000Y-114808000D02* +X151384000Y-116332000D01* +X162515000Y-100629000D02* +X163449000Y-99695000D01* +X162515000Y-103505000D02* +X162515000Y-100629000D01* +X180225500Y-99174500D02* +X180225500Y-96520000D01* +D30* +%TO.N,+5V*% +X164560000Y-78010000D02* +X164465000Y-78105000D01* +D29* +X164560000Y-78010000D02* +X167640000Y-78010000D01* +D30* +X175260000Y-78232000D02* +X175038000Y-78010000D01* +X175038000Y-78010000D02* +X167640000Y-78010000D01* +D31* +%TO.N,Net-(C9-Pad1)*% +X180340000Y-95250000D02* +X171450000Y-95250000D01* +D30* +%TO.N,Net-(D2-Pad2)*% +X170275000Y-82010000D02* +X170815000Y-82550000D01* +D29* +X165605000Y-84045000D02* +X167640000Y-82010000D01* +X165605000Y-92075000D02* +X165605000Y-84045000D01* +D30* +X167640000Y-82010000D02* +X170275000Y-82010000D01* +D28* +%TO.N,/Cpu/RESET*% +X159004000Y-122428000D02* +X159004000Y-113665000D01* +X166415000Y-108585000D02* +X166415000Y-111080000D01* +X166370000Y-111760000D02* +X166370000Y-111125000D01* +X166415000Y-111080000D02* +X166370000Y-111125000D01* +X164465000Y-113665000D02* +X166370000Y-111760000D01* +X154940000Y-129629500D02* +X154940000Y-123825000D01* +X158242000Y-123190000D02* +X159004000Y-122428000D01* +X155575000Y-123190000D02* +X158242000Y-123190000D01* +X140652500Y-113347500D02* +X140652500Y-120331782D01* +X140652500Y-120331782D02* +X139700000Y-121284282D01* +X139700000Y-121284282D02* +X139700000Y-121195500D01* +X159004000Y-113665000D02* +X164465000Y-113665000D01* +X140970000Y-113030000D02* +X140652500Y-113347500D01* +X144145000Y-113030000D02* +X140970000Y-113030000D01* +X154940000Y-123825000D02* +X155575000Y-123190000D01* +D31* +%TO.N,Net-(J1-Pad3)*% +X132485489Y-99289511D02* +X132485489Y-93574511D01* +X133350000Y-92710000D02* +X133350000Y-88900000D01* +X132080000Y-99695000D02* +X132485489Y-99289511D01* +X127000000Y-99695000D02* +X132080000Y-99695000D01* +X132485489Y-93574511D02* +X133350000Y-92710000D01* +X126384511Y-109835489D02* +X127000000Y-109220000D01* +X126384511Y-117925989D02* +X126384511Y-109835489D01* +X127000000Y-104775000D02* +X127000000Y-109220000D01* +X126365000Y-117945500D02* +X126384511Y-117925989D01* +D28* +%TO.N,Net-(R7-Pad2)*% +X176665614Y-117856000D02* +X174625000Y-115815386D01* +X178308000Y-117856000D02* +X176665614Y-117856000D01* +X174625000Y-115815386D02* +X174625000Y-111125000D01* +D30* +%TO.N,/Cpu/OUTDROIT_B*% +X146050000Y-102870000D02* +X113665000Y-102870000D01* +X113665000Y-102870000D02* +X113665000Y-107950000D01* +D28* +%TO.N,Net-(SW1-Pad2)*% +X117465630Y-82724784D02* +X117465630Y-80430451D01* +X118110000Y-99060000D02* +X118110000Y-97155000D01* +X117465630Y-80430451D02* +X119849081Y-78047000D01* +X118110000Y-97155000D02* +X117465630Y-96510630D01* +X117465630Y-96510630D02* +X117465630Y-82724784D01* +D31* +%TO.N,Net-(D3-Pad2)*% +X116211899Y-126993101D02* +X116211899Y-129706250D01* +X116840000Y-126365000D02* +X116211899Y-126993101D01* +%TO.N,Net-(D4-Pad2)*% +X118110000Y-127000000D02* +X118110000Y-130772149D01* +X118110000Y-130772149D02* +X117270899Y-131611250D01* +X118745000Y-126365000D02* +X118110000Y-127000000D01* +%TO.N,Net-(D5-Pad2)*% +X120650000Y-126365000D02* +X120650000Y-131278149D01* +X120650000Y-131278149D02* +X118411899Y-133516250D01* +D28* +%TO.N,/Cpu/ENCGAUCHE_A*% +X144272000Y-104140000D02* +X141605000Y-104140000D01* +X138430000Y-109855000D02* +X138430000Y-114935000D01* +X138430000Y-114935000D02* +X138340500Y-114935000D01* +%TO.N,/Cpu/ENCDROIT_A*% +X139259800Y-108779800D02* +X139192000Y-108712000D01* +X137460103Y-108928511D02* +X137451489Y-108928511D01* +X137676614Y-108712000D02* +X137460103Y-108928511D01* +X136704011Y-109675989D02* +X136704011Y-113485989D01* +X136704011Y-113485989D02* +X135890000Y-114300000D01* +X135890000Y-114300000D02* +X127635000Y-114300000D01* +X139192000Y-108712000D02* +X137676614Y-108712000D01* +X137451489Y-108928511D02* +X136704011Y-109675989D01* +X127635000Y-114300000D02* +X127635000Y-114210500D01* +%TO.N,/Cpu/ENCDROIT_B*% +X131000000Y-123635000D02* +X131000000Y-124920000D01* +X149352000Y-114300000D02* +X141732000Y-114300000D01* +X140000114Y-121920000D02* +X132715000Y-121920000D01* +X141102020Y-120818094D02* +X140000114Y-121920000D01* +X141102020Y-114929980D02* +X141102020Y-120818094D01* +X132715000Y-121920000D02* +X131000000Y-123635000D01* +X141732000Y-114300000D02* +X141102020Y-114929980D01* +X149860000Y-113792000D02* +X149352000Y-114300000D01* +%TO.N,/Cpu/LED_ROUGE*% +X156845000Y-109220000D02* +X155829000Y-108204000D01* +X139065000Y-110363000D02* +X139065000Y-119380000D01* +X116205000Y-120015000D02* +X115570000Y-119380000D01* +X115570000Y-119380000D02* +X115570000Y-118110000D01* +X139065000Y-119380000D02* +X138430000Y-120015000D01* +X141224000Y-108204000D02* +X139065000Y-110363000D01* +X138430000Y-120015000D02* +X116205000Y-120015000D01* +X155829000Y-108204000D02* +X141224000Y-108204000D01* +%TO.N,/Cpu/LED_ORANGE*% +X123825000Y-120650000D02* +X138430718Y-120650000D01* +X139700000Y-110363718D02* +X141351718Y-108712000D01* +X141351718Y-108712000D02* +X155067000Y-108712000D01* +X155067000Y-108712000D02* +X156845000Y-110490000D01* +X122555000Y-121285000D02* +X123190000Y-121285000D01* +X138430718Y-120650000D02* +X139700000Y-119380718D01* +X123190000Y-121285000D02* +X123825000Y-120650000D01* +X139700000Y-119380718D02* +X139700000Y-110363718D01* +%TO.N,/Cpu/LED_VERTE*% +X125095000Y-121285000D02* +X124460000Y-121920000D01* +X158115000Y-110244614D02* +X157145103Y-111214511D01* +X140149520Y-110802480D02* +X140149520Y-119566916D01* +X140149520Y-119566916D02* +X138431436Y-121285000D01* +X141732000Y-109220000D02* +X140149520Y-110802480D01* +X156544897Y-111214511D02* +X154550386Y-109220000D01* +X157145103Y-111214511D02* +X156544897Y-111214511D01* +X158115000Y-109855000D02* +X158115000Y-110244614D01* +X138431436Y-121285000D02* +X125095000Y-121285000D01* +X154550386Y-109220000D02* +X141732000Y-109220000D01* +%TO.N,/Cpu/USART_RX*% +X151448348Y-106045000D02* +X151995500Y-106045000D01* +X135255000Y-107569000D02* +X135636000Y-107188000D01* +X136154039Y-106680000D02* +X150813348Y-106680000D01* +X135636000Y-107188000D02* +X135646039Y-107188000D01* +X150813348Y-106680000D02* +X151448348Y-106045000D01* +X135255000Y-112395000D02* +X135255000Y-107569000D01* +X135646039Y-107188000D02* +X136154039Y-106680000D01* +%TO.N,/Cpu/USART_TX*% +X135979511Y-113101744D02* +X135979500Y-113101755D01* +X136652000Y-107188000D02* +X135979511Y-107860489D01* +X151520500Y-106997462D02* +X151329962Y-107188000D01* +X151329962Y-107188000D02* +X136652000Y-107188000D01* +X135979511Y-107860489D02* +X135979511Y-113101744D01* +%TO.N,/Cpu/XBEE_RESET*% +X149860000Y-120650000D02* +X149860000Y-118745000D01* +X151744989Y-118020489D02* +X152469500Y-118745000D01* +X137990508Y-115584511D02* +X138340500Y-115934503D01* +X136510489Y-115584511D02* +X137990508Y-115584511D01* +X149860000Y-118745000D02* +X150584511Y-118020489D01* +X136510489Y-117930989D02* +X136510489Y-115584511D01* +X136525000Y-117945500D02* +X136510489Y-117930989D01* +X142710500Y-120650000D02* +X149860000Y-120650000D01* +X150584511Y-118020489D02* +X151744989Y-118020489D01* +%TO.N,/Cpu/CHARGER_ST1*% +X176530000Y-124460000D02* +X176530000Y-121158000D01* +X182372000Y-120904000D02* +X182880000Y-120396000D01* +X182880000Y-120396000D02* +X182880000Y-116205000D01* +X176530000Y-121158000D02* +X176784000Y-120904000D01* +X176784000Y-120904000D02* +X182372000Y-120904000D01* +%TO.N,/Cpu/SHUTDOWN*% +X145415000Y-123190000D02* +X146050000Y-122555000D01* +X137795000Y-123190000D02* +X145415000Y-123190000D01* +X135890000Y-125095000D02* +X137795000Y-123190000D01* +X146050000Y-122555000D02* +X146050000Y-121830500D01* +%TO.N,/Cpu/CHARGER_ST2*% +X178816000Y-118872000D02* +X181610000Y-118872000D01* +X169545000Y-118745000D02* +X171704000Y-118745000D01* +X152290500Y-120015000D02* +X151020500Y-118745000D01* +X181610000Y-116205000D02* +X182880000Y-114935000D01* +X181610000Y-118872000D02* +X181610000Y-116205000D01* +X156210000Y-120015000D02* +X152290500Y-120015000D01* +%TO.N,/Cpu/PWM_GAUCHE_B*% +X146812000Y-105955500D02* +X146812000Y-104648000D01* +X148844000Y-104140000D02* +X148844000Y-99568000D01* +X149352000Y-99060000D02* +X154940000Y-99060000D01* +X147320000Y-104140000D02* +X148844000Y-104140000D01* +X146812000Y-104648000D02* +X147320000Y-104140000D01* +X148844000Y-99568000D02* +X149352000Y-99060000D01* +%TO.N,/Cpu/BUTTON_SENSE*% +X133350000Y-122555000D02* +X132715000Y-123190000D01* +X141859718Y-114808000D02* +X141605000Y-115062718D01* +X132715000Y-123190000D02* +X132715000Y-125730000D01* +X124380489Y-126285489D02* +X121920000Y-123825000D01* +X141605000Y-115062718D02* +X141605000Y-121285718D01* +X116205000Y-123825000D02* +X121920000Y-123825000D01* +X115387601Y-123007601D02* +X116205000Y-123825000D01* +X132159511Y-126285489D02* +X124380489Y-126285489D01* +X149606000Y-114808000D02* +X141859718Y-114808000D01* +X150368000Y-115570000D02* +X149606000Y-114808000D01* +X132715000Y-125730000D02* +X132159511Y-126285489D01* +X141605000Y-121285718D02* +X140335718Y-122555000D01* +X140335718Y-122555000D02* +X133350000Y-122555000D01* +X115387601Y-123007601D02* +X115387601Y-121285000D01* +%TO.N,/Cpu/BATTERY_SENSE*% +X167132000Y-129032000D02* +X168171500Y-130071500D01* +X158496000Y-121911402D02* +X157983701Y-122423701D01* +X168171500Y-130071500D02* +X168632500Y-130071500D01* +X155448000Y-111252000D02* +X155956000Y-111760000D01* +X148844000Y-111252000D02* +X155448000Y-111252000D01* +X155956000Y-111760000D02* +X157988000Y-111760000D01* +X157988000Y-111760000D02* +X158496000Y-112268000D01* +X167132000Y-125984000D02* +X167132000Y-129032000D01* +X158496000Y-112268000D02* +X158496000Y-121911402D01* +%TO.N,/Cpu/SHUTDOWN_ENC*% +X137668000Y-108204000D02* +X138150027Y-107721973D01* +X138150027Y-107721973D02* +X159029973Y-107721973D01* +X159029973Y-107721973D02* +X159385000Y-108077000D01* +X159385000Y-108077000D02* +X159385000Y-110490000D01* +X137160000Y-108204000D02* +X137668000Y-108204000D01* +%TO.N,/Cpu/SWDIO*% +X155945960Y-118745000D02* +X156395480Y-118295480D01* +X153035000Y-113157000D02* +X153035000Y-118110000D01* +X170815000Y-103505000D02* +X166415000Y-103505000D01* +X153035000Y-118110000D02* +X153670000Y-118745000D01* +X171450000Y-104140000D02* +X170815000Y-103505000D01* +X153670000Y-118745000D02* +X155945960Y-118745000D01* +X171450000Y-104775000D02* +X171450000Y-104140000D01* +X152908000Y-113030000D02* +X153035000Y-113157000D01* +%TO.N,/Cpu/SWCLK*% +X164465000Y-117475000D02* +X165735000Y-116205000D01* +X169545000Y-104775000D02* +X170180000Y-105410000D01* +X160020000Y-117475000D02* +X164465000Y-117475000D01* +X165735000Y-116205000D02* +X165735000Y-113665000D01* +X166415000Y-104775000D02* +X169545000Y-104775000D01* +X165735000Y-113665000D02* +X167005000Y-112395000D01* +%TO.N,/Cpu/SHUTDOWN_5V*% +X169545000Y-131445000D02* +X168910000Y-130810000D01* +X173990000Y-91186000D02* +X174752000Y-91948000D01* +X170180000Y-137160000D02* +X169545000Y-136525000D01* +X186690000Y-135890000D02* +X185420000Y-137160000D01* +X173990000Y-88265000D02* +X173990000Y-91186000D01* +X185420000Y-137160000D02* +X170180000Y-137160000D01* +X186690000Y-110490000D02* +X186690000Y-92710000D01* +X168910000Y-130810000D02* +X147955000Y-130810000D01* +X186690000Y-113284000D02* +X186690000Y-135890000D01* +X147955000Y-130810000D02* +X147320000Y-130175000D01* +X185928000Y-91948000D02* +X186690000Y-92710000D01* +X169545000Y-136525000D02* +X169545000Y-131445000D01* +X147320000Y-130175000D02* +X147320000Y-121830500D01* +X174752000Y-91948000D02* +X185928000Y-91948000D01* +D29* +%TO.N,Net-(C6-Pad1)*% +X169545000Y-92075000D02* +X170180000Y-92710000D01* +X168405000Y-92075000D02* +X169545000Y-92075000D01* +X171225000Y-98835000D02* +X171635000Y-98425000D01* +X171635000Y-98425000D02* +X176530000Y-98425000D01* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Fab.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Fab.gbr new file mode 100644 index 0000000..bfad127 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Fab.gbr @@ -0,0 +1,2405 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,AssemblyDrawing,Top*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12C,0.150000*% +%ADD13C,0.100000*% +%ADD14C,0.080000*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +X93480952Y-110428571D02* +X93433333Y-110523809D01* +X93385714Y-110571428D01* +X93290476Y-110619047D01* +X93242857Y-110619047D01* +X93147619Y-110571428D01* +X93100000Y-110523809D01* +X93052380Y-110428571D01* +X93052380Y-110238095D01* +X93100000Y-110142857D01* +X93147619Y-110095238D01* +X93242857Y-110047619D01* +X93290476Y-110047619D01* +X93385714Y-110095238D01* +X93433333Y-110142857D01* +X93480952Y-110238095D01* +X93480952Y-110428571D01* +X93528571Y-110523809D01* +X93576190Y-110571428D01* +X93671428Y-110619047D01* +X93861904Y-110619047D01* +X93957142Y-110571428D01* +X94004761Y-110523809D01* +X94052380Y-110428571D01* +X94052380Y-110238095D01* +X94004761Y-110142857D01* +X93957142Y-110095238D01* +X93861904Y-110047619D01* +X93671428Y-110047619D01* +X93576190Y-110095238D01* +X93528571Y-110142857D01* +X93480952Y-110238095D01* +X93052380Y-109190476D02* +X93052380Y-109380952D01* +X93100000Y-109476190D01* +X93147619Y-109523809D01* +X93290476Y-109619047D01* +X93480952Y-109666666D01* +X93861904Y-109666666D01* +X93957142Y-109619047D01* +X94004761Y-109571428D01* +X94052380Y-109476190D01* +X94052380Y-109285714D01* +X94004761Y-109190476D01* +X93957142Y-109142857D01* +X93861904Y-109095238D01* +X93623809Y-109095238D01* +X93528571Y-109142857D01* +X93480952Y-109190476D01* +X93433333Y-109285714D01* +X93433333Y-109476190D01* +X93480952Y-109571428D01* +X93528571Y-109619047D01* +X93623809Y-109666666D01* +X94004761Y-108619047D02* +X94052380Y-108619047D01* +X94147619Y-108666666D01* +X94195238Y-108714285D01* +X93052380Y-108000000D02* +X93052380Y-107904761D01* +X93100000Y-107809523D01* +X93147619Y-107761904D01* +X93242857Y-107714285D01* +X93433333Y-107666666D01* +X93671428Y-107666666D01* +X93861904Y-107714285D01* +X93957142Y-107761904D01* +X94004761Y-107809523D01* +X94052380Y-107904761D01* +X94052380Y-108000000D01* +X94004761Y-108095238D01* +X93957142Y-108142857D01* +X93861904Y-108190476D01* +X93671428Y-108238095D01* +X93433333Y-108238095D01* +X93242857Y-108190476D01* +X93147619Y-108142857D01* +X93100000Y-108095238D01* +X93052380Y-108000000D01* +X93052380Y-107047619D02* +X93052380Y-106952380D01* +X93100000Y-106857142D01* +X93147619Y-106809523D01* +X93242857Y-106761904D01* +X93433333Y-106714285D01* +X93671428Y-106714285D01* +X93861904Y-106761904D01* +X93957142Y-106809523D01* +X94004761Y-106857142D01* +X94052380Y-106952380D01* +X94052380Y-107047619D01* +X94004761Y-107142857D01* +X93957142Y-107190476D01* +X93861904Y-107238095D01* +X93671428Y-107285714D01* +X93433333Y-107285714D01* +X93242857Y-107238095D01* +X93147619Y-107190476D01* +X93100000Y-107142857D01* +X93052380Y-107047619D01* +X93052380Y-106095238D02* +X93052380Y-106000000D01* +X93100000Y-105904761D01* +X93147619Y-105857142D01* +X93242857Y-105809523D01* +X93433333Y-105761904D01* +X93671428Y-105761904D01* +X93861904Y-105809523D01* +X93957142Y-105857142D01* +X94004761Y-105904761D01* +X94052380Y-106000000D01* +X94052380Y-106095238D01* +X94004761Y-106190476D01* +X93957142Y-106238095D01* +X93861904Y-106285714D01* +X93671428Y-106333333D01* +X93433333Y-106333333D01* +X93242857Y-106285714D01* +X93147619Y-106238095D01* +X93100000Y-106190476D01* +X93052380Y-106095238D01* +X93052380Y-105142857D02* +X93052380Y-105047619D01* +X93100000Y-104952380D01* +X93147619Y-104904761D01* +X93242857Y-104857142D01* +X93433333Y-104809523D01* +X93671428Y-104809523D01* +X93861904Y-104857142D01* +X93957142Y-104904761D01* +X94004761Y-104952380D01* +X94052380Y-105047619D01* +X94052380Y-105142857D01* +X94004761Y-105238095D01* +X93957142Y-105285714D01* +X93861904Y-105333333D01* +X93671428Y-105380952D01* +X93433333Y-105380952D01* +X93242857Y-105333333D01* +X93147619Y-105285714D01* +X93100000Y-105238095D01* +X93052380Y-105142857D01* +X94052380Y-103619047D02* +X93385714Y-103619047D01* +X93480952Y-103619047D02* +X93433333Y-103571428D01* +X93385714Y-103476190D01* +X93385714Y-103333333D01* +X93433333Y-103238095D01* +X93528571Y-103190476D01* +X94052380Y-103190476D01* +X93528571Y-103190476D02* +X93433333Y-103142857D01* +X93385714Y-103047619D01* +X93385714Y-102904761D01* +X93433333Y-102809523D01* +X93528571Y-102761904D01* +X94052380Y-102761904D01* +X94052380Y-102285714D02* +X93385714Y-102285714D01* +X93480952Y-102285714D02* +X93433333Y-102238095D01* +X93385714Y-102142857D01* +X93385714Y-102000000D01* +X93433333Y-101904761D01* +X93528571Y-101857142D01* +X94052380Y-101857142D01* +X93528571Y-101857142D02* +X93433333Y-101809523D01* +X93385714Y-101714285D01* +X93385714Y-101571428D01* +X93433333Y-101476190D01* +X93528571Y-101428571D01* +X94052380Y-101428571D01* +D13* +X129750000Y-63000000D02* +X94163580Y-63000000D01* +X129750000Y-149000000D02* +X94163580Y-149000000D01* +X94750000Y-63000000D02* +X94750000Y-149000000D01* +X94750000Y-63000000D02* +X94750000Y-149000000D01* +X94750000Y-63000000D02* +X94163579Y-64126504D01* +X94750000Y-63000000D02* +X95336421Y-64126504D01* +X94750000Y-149000000D02* +X95336421Y-147873496D01* +X94750000Y-149000000D02* +X94163579Y-147873496D01* +D12* +X149321428Y-37230952D02* +X149226190Y-37183333D01* +X149178571Y-37135714D01* +X149130952Y-37040476D01* +X149130952Y-36992857D01* +X149178571Y-36897619D01* +X149226190Y-36850000D01* +X149321428Y-36802380D01* +X149511904Y-36802380D01* +X149607142Y-36850000D01* +X149654761Y-36897619D01* +X149702380Y-36992857D01* +X149702380Y-37040476D01* +X149654761Y-37135714D01* +X149607142Y-37183333D01* +X149511904Y-37230952D01* +X149321428Y-37230952D01* +X149226190Y-37278571D01* +X149178571Y-37326190D01* +X149130952Y-37421428D01* +X149130952Y-37611904D01* +X149178571Y-37707142D01* +X149226190Y-37754761D01* +X149321428Y-37802380D01* +X149511904Y-37802380D01* +X149607142Y-37754761D01* +X149654761Y-37707142D01* +X149702380Y-37611904D01* +X149702380Y-37421428D01* +X149654761Y-37326190D01* +X149607142Y-37278571D01* +X149511904Y-37230952D01* +X150273809Y-37230952D02* +X150178571Y-37183333D01* +X150130952Y-37135714D01* +X150083333Y-37040476D01* +X150083333Y-36992857D01* +X150130952Y-36897619D01* +X150178571Y-36850000D01* +X150273809Y-36802380D01* +X150464285Y-36802380D01* +X150559523Y-36850000D01* +X150607142Y-36897619D01* +X150654761Y-36992857D01* +X150654761Y-37040476D01* +X150607142Y-37135714D01* +X150559523Y-37183333D01* +X150464285Y-37230952D01* +X150273809Y-37230952D01* +X150178571Y-37278571D01* +X150130952Y-37326190D01* +X150083333Y-37421428D01* +X150083333Y-37611904D01* +X150130952Y-37707142D01* +X150178571Y-37754761D01* +X150273809Y-37802380D01* +X150464285Y-37802380D01* +X150559523Y-37754761D01* +X150607142Y-37707142D01* +X150654761Y-37611904D01* +X150654761Y-37421428D01* +X150607142Y-37326190D01* +X150559523Y-37278571D01* +X150464285Y-37230952D01* +X151130952Y-37754761D02* +X151130952Y-37802380D01* +X151083333Y-37897619D01* +X151035714Y-37945238D01* +X151750000Y-36802380D02* +X151845238Y-36802380D01* +X151940476Y-36850000D01* +X151988095Y-36897619D01* +X152035714Y-36992857D01* +X152083333Y-37183333D01* +X152083333Y-37421428D01* +X152035714Y-37611904D01* +X151988095Y-37707142D01* +X151940476Y-37754761D01* +X151845238Y-37802380D01* +X151750000Y-37802380D01* +X151654761Y-37754761D01* +X151607142Y-37707142D01* +X151559523Y-37611904D01* +X151511904Y-37421428D01* +X151511904Y-37183333D01* +X151559523Y-36992857D01* +X151607142Y-36897619D01* +X151654761Y-36850000D01* +X151750000Y-36802380D01* +X152702380Y-36802380D02* +X152797619Y-36802380D01* +X152892857Y-36850000D01* +X152940476Y-36897619D01* +X152988095Y-36992857D01* +X153035714Y-37183333D01* +X153035714Y-37421428D01* +X152988095Y-37611904D01* +X152940476Y-37707142D01* +X152892857Y-37754761D01* +X152797619Y-37802380D01* +X152702380Y-37802380D01* +X152607142Y-37754761D01* +X152559523Y-37707142D01* +X152511904Y-37611904D01* +X152464285Y-37421428D01* +X152464285Y-37183333D01* +X152511904Y-36992857D01* +X152559523Y-36897619D01* +X152607142Y-36850000D01* +X152702380Y-36802380D01* +X153654761Y-36802380D02* +X153750000Y-36802380D01* +X153845238Y-36850000D01* +X153892857Y-36897619D01* +X153940476Y-36992857D01* +X153988095Y-37183333D01* +X153988095Y-37421428D01* +X153940476Y-37611904D01* +X153892857Y-37707142D01* +X153845238Y-37754761D01* +X153750000Y-37802380D01* +X153654761Y-37802380D01* +X153559523Y-37754761D01* +X153511904Y-37707142D01* +X153464285Y-37611904D01* +X153416666Y-37421428D01* +X153416666Y-37183333D01* +X153464285Y-36992857D01* +X153511904Y-36897619D01* +X153559523Y-36850000D01* +X153654761Y-36802380D01* +X154607142Y-36802380D02* +X154702380Y-36802380D01* +X154797619Y-36850000D01* +X154845238Y-36897619D01* +X154892857Y-36992857D01* +X154940476Y-37183333D01* +X154940476Y-37421428D01* +X154892857Y-37611904D01* +X154845238Y-37707142D01* +X154797619Y-37754761D01* +X154702380Y-37802380D01* +X154607142Y-37802380D01* +X154511904Y-37754761D01* +X154464285Y-37707142D01* +X154416666Y-37611904D01* +X154369047Y-37421428D01* +X154369047Y-37183333D01* +X154416666Y-36992857D01* +X154464285Y-36897619D01* +X154511904Y-36850000D01* +X154607142Y-36802380D01* +X156130952Y-37802380D02* +X156130952Y-37135714D01* +X156130952Y-37230952D02* +X156178571Y-37183333D01* +X156273809Y-37135714D01* +X156416666Y-37135714D01* +X156511904Y-37183333D01* +X156559523Y-37278571D01* +X156559523Y-37802380D01* +X156559523Y-37278571D02* +X156607142Y-37183333D01* +X156702380Y-37135714D01* +X156845238Y-37135714D01* +X156940476Y-37183333D01* +X156988095Y-37278571D01* +X156988095Y-37802380D01* +X157464285Y-37802380D02* +X157464285Y-37135714D01* +X157464285Y-37230952D02* +X157511904Y-37183333D01* +X157607142Y-37135714D01* +X157750000Y-37135714D01* +X157845238Y-37183333D01* +X157892857Y-37278571D01* +X157892857Y-37802380D01* +X157892857Y-37278571D02* +X157940476Y-37183333D01* +X158035714Y-37135714D01* +X158178571Y-37135714D01* +X158273809Y-37183333D01* +X158321428Y-37278571D01* +X158321428Y-37802380D01* +D13* +X109750000Y-102000000D02* +X109750000Y-37913580D01* +X197750000Y-102000000D02* +X197750000Y-37913580D01* +X109750000Y-38500000D02* +X197750000Y-38500000D01* +X109750000Y-38500000D02* +X197750000Y-38500000D01* +X109750000Y-38500000D02* +X110876504Y-39086421D01* +X109750000Y-38500000D02* +X110876504Y-37913579D01* +X197750000Y-38500000D02* +X196623496Y-37913579D01* +X197750000Y-38500000D02* +X196623496Y-39086421D01* +D12* +%TO.C,M1*% +X179102380Y-151933333D02* +X178102380Y-151933333D01* +X178816666Y-151600000D01* +X178102380Y-151266666D01* +X179102380Y-151266666D01* +X179102380Y-150647619D02* +X179054761Y-150742857D01* +X179007142Y-150790476D01* +X178911904Y-150838095D01* +X178626190Y-150838095D01* +X178530952Y-150790476D01* +X178483333Y-150742857D01* +X178435714Y-150647619D01* +X178435714Y-150504761D01* +X178483333Y-150409523D01* +X178530952Y-150361904D01* +X178626190Y-150314285D01* +X178911904Y-150314285D01* +X179007142Y-150361904D01* +X179054761Y-150409523D01* +X179102380Y-150504761D01* +X179102380Y-150647619D01* +X178435714Y-150028571D02* +X178435714Y-149647619D01* +X178102380Y-149885714D02* +X178959523Y-149885714D01* +X179054761Y-149838095D01* +X179102380Y-149742857D01* +X179102380Y-149647619D01* +X179102380Y-149171428D02* +X179054761Y-149266666D01* +X179007142Y-149314285D01* +X178911904Y-149361904D01* +X178626190Y-149361904D01* +X178530952Y-149314285D01* +X178483333Y-149266666D01* +X178435714Y-149171428D01* +X178435714Y-149028571D01* +X178483333Y-148933333D01* +X178530952Y-148885714D01* +X178626190Y-148838095D01* +X178911904Y-148838095D01* +X179007142Y-148885714D01* +X179054761Y-148933333D01* +X179102380Y-149028571D01* +X179102380Y-149171428D01* +X179102380Y-148409523D02* +X178435714Y-148409523D01* +X178626190Y-148409523D02* +X178530952Y-148361904D01* +X178483333Y-148314285D01* +X178435714Y-148219047D01* +X178435714Y-148123809D01* +%TO.C,SW1*% +X119995578Y-84488173D02* +X120102863Y-84382505D01* +X120210956Y-84170361D01* +X120211764Y-84063884D01* +X120190954Y-83999837D01* +X120127714Y-83914171D01* +X120042857Y-83870933D01* +X119936380Y-83870125D01* +X119872333Y-83890935D01* +X119786667Y-83954175D01* +X119657763Y-84102272D01* +X119572097Y-84165511D01* +X119508050Y-84186321D01* +X119401574Y-84185513D01* +X119316716Y-84142275D01* +X119253477Y-84056609D01* +X119232666Y-83992562D01* +X119233475Y-83886086D01* +X119341568Y-83673941D01* +X119448852Y-83568273D01* +X119557754Y-83249652D02* +X120556853Y-83491498D01* +X120006894Y-82997504D01* +X120729802Y-83152067D01* +X119946888Y-82485932D01* +X120987608Y-82855874D02* +X121333506Y-82177011D01* +X121356741Y-81921630D02* +X120465735Y-81467639D01* +X120638683Y-81128208D01* +X120724349Y-81064969D01* +X120788397Y-81044159D01* +X120894873Y-81044967D01* +X121022160Y-81109823D01* +X121085399Y-81195489D01* +X121106209Y-81259536D01* +X121105401Y-81366013D01* +X120932452Y-81705444D01* +X121411295Y-80346103D02* +X122005299Y-80648763D01* +X121216727Y-80727963D02* +X121683445Y-80965767D01* +X121789921Y-80966576D01* +X121875587Y-80903337D01* +X121940443Y-80776050D01* +X121941251Y-80669574D01* +X121920441Y-80605526D01* +X122157437Y-80245285D02* +X122243103Y-80182046D01* +X122329578Y-80012330D01* +X122330386Y-79905854D01* +X122267147Y-79820188D01* +X122224718Y-79798569D01* +X122118242Y-79797761D01* +X122032576Y-79861000D01* +X121967720Y-79988287D01* +X121882054Y-80051526D01* +X121775577Y-80050717D01* +X121733149Y-80029099D01* +X121669909Y-79943433D01* +X121670718Y-79836956D01* +X121735574Y-79709670D01* +X121821240Y-79646431D01* +X122589001Y-79503184D02* +X121697994Y-79049193D01* +X122783568Y-79121324D02* +X122316851Y-78883519D01* +X122210374Y-78882711D01* +X122124708Y-78945950D01* +X122059852Y-79073237D01* +X122059044Y-79179713D01* +X122079854Y-79243760D01* +X117655324Y-81371766D02* +X117762609Y-81266098D01* +X117870702Y-81053954D01* +X117871510Y-80947477D01* +X117850700Y-80883430D01* +X117787461Y-80797764D01* +X117702603Y-80754527D01* +X117596127Y-80753718D01* +X117532079Y-80774529D01* +X117446413Y-80837768D01* +X117317510Y-80985865D01* +X117231844Y-81049104D01* +X117167796Y-81069914D01* +X117061320Y-81069106D01* +X116976462Y-81025869D01* +X116913223Y-80940203D01* +X116892413Y-80876155D01* +X116893221Y-80769679D01* +X117001314Y-80557534D01* +X117108599Y-80451866D01* +X117217500Y-80133246D02* +X118216599Y-80375092D01* +X117666641Y-79881097D01* +X118389548Y-80035661D01* +X117606635Y-79369526D01* +X118908395Y-79017367D02* +X118648971Y-79526514D01* +X118778683Y-79271941D02* +X117887676Y-78817950D01* +X117971726Y-78967664D01* +X118013346Y-79095759D01* +X118012538Y-79202235D01* +%TO.C,J1*% +X122087142Y-76177142D02* +X122039523Y-76224761D01* +X121896666Y-76272380D01* +X121801428Y-76272380D01* +X121658571Y-76224761D01* +X121563333Y-76129523D01* +X121515714Y-76034285D01* +X121468095Y-75843809D01* +X121468095Y-75700952D01* +X121515714Y-75510476D01* +X121563333Y-75415238D01* +X121658571Y-75320000D01* +X121801428Y-75272380D01* +X121896666Y-75272380D01* +X122039523Y-75320000D01* +X122087142Y-75367619D01* +X122658571Y-76272380D02* +X122563333Y-76224761D01* +X122515714Y-76177142D01* +X122468095Y-76081904D01* +X122468095Y-75796190D01* +X122515714Y-75700952D01* +X122563333Y-75653333D01* +X122658571Y-75605714D01* +X122801428Y-75605714D01* +X122896666Y-75653333D01* +X122944285Y-75700952D01* +X122991904Y-75796190D01* +X122991904Y-76081904D01* +X122944285Y-76177142D01* +X122896666Y-76224761D01* +X122801428Y-76272380D01* +X122658571Y-76272380D01* +X123420476Y-75605714D02* +X123420476Y-76272380D01* +X123420476Y-75700952D02* +X123468095Y-75653333D01* +X123563333Y-75605714D01* +X123706190Y-75605714D01* +X123801428Y-75653333D01* +X123849047Y-75748571D01* +X123849047Y-76272380D01* +X124325238Y-75605714D02* +X124325238Y-76272380D01* +X124325238Y-75700952D02* +X124372857Y-75653333D01* +X124468095Y-75605714D01* +X124610952Y-75605714D01* +X124706190Y-75653333D01* +X124753809Y-75748571D01* +X124753809Y-76272380D01* +X124991904Y-76367619D02* +X125753809Y-76367619D01* +X126182380Y-75272380D02* +X126277619Y-75272380D01* +X126372857Y-75320000D01* +X126420476Y-75367619D01* +X126468095Y-75462857D01* +X126515714Y-75653333D01* +X126515714Y-75891428D01* +X126468095Y-76081904D01* +X126420476Y-76177142D01* +X126372857Y-76224761D01* +X126277619Y-76272380D01* +X126182380Y-76272380D01* +X126087142Y-76224761D01* +X126039523Y-76177142D01* +X125991904Y-76081904D01* +X125944285Y-75891428D01* +X125944285Y-75653333D01* +X125991904Y-75462857D01* +X126039523Y-75367619D01* +X126087142Y-75320000D01* +X126182380Y-75272380D01* +X126896666Y-75367619D02* +X126944285Y-75320000D01* +X127039523Y-75272380D01* +X127277619Y-75272380D01* +X127372857Y-75320000D01* +X127420476Y-75367619D01* +X127468095Y-75462857D01* +X127468095Y-75558095D01* +X127420476Y-75700952D01* +X126849047Y-76272380D01* +X127468095Y-76272380D01* +X127801428Y-76272380D02* +X128325238Y-75605714D01* +X127801428Y-75605714D02* +X128325238Y-76272380D01* +X128896666Y-75272380D02* +X128991904Y-75272380D01* +X129087142Y-75320000D01* +X129134761Y-75367619D01* +X129182380Y-75462857D01* +X129230000Y-75653333D01* +X129230000Y-75891428D01* +X129182380Y-76081904D01* +X129134761Y-76177142D01* +X129087142Y-76224761D01* +X128991904Y-76272380D01* +X128896666Y-76272380D01* +X128801428Y-76224761D01* +X128753809Y-76177142D01* +X128706190Y-76081904D01* +X128658571Y-75891428D01* +X128658571Y-75653333D01* +X128706190Y-75462857D01* +X128753809Y-75367619D01* +X128801428Y-75320000D01* +X128896666Y-75272380D01* +X129563333Y-75272380D02* +X130182380Y-75272380D01* +X129849047Y-75653333D01* +X129991904Y-75653333D01* +X130087142Y-75700952D01* +X130134761Y-75748571D01* +X130182380Y-75843809D01* +X130182380Y-76081904D01* +X130134761Y-76177142D01* +X130087142Y-76224761D01* +X129991904Y-76272380D01* +X129706190Y-76272380D01* +X129610952Y-76224761D01* +X129563333Y-76177142D01* +X130372857Y-76367619D02* +X131134761Y-76367619D01* +X131563333Y-75272380D02* +X131753809Y-75272380D01* +X131849047Y-75320000D01* +X131944285Y-75415238D01* +X131991904Y-75605714D01* +X131991904Y-75939047D01* +X131944285Y-76129523D01* +X131849047Y-76224761D01* +X131753809Y-76272380D01* +X131563333Y-76272380D01* +X131468095Y-76224761D01* +X131372857Y-76129523D01* +X131325238Y-75939047D01* +X131325238Y-75605714D01* +X131372857Y-75415238D01* +X131468095Y-75320000D01* +X131563333Y-75272380D01* +X132849047Y-76272380D02* +X132849047Y-75272380D01* +X132849047Y-76224761D02* +X132753809Y-76272380D01* +X132563333Y-76272380D01* +X132468095Y-76224761D01* +X132420476Y-76177142D01* +X132372857Y-76081904D01* +X132372857Y-75796190D01* +X132420476Y-75700952D01* +X132468095Y-75653333D01* +X132563333Y-75605714D01* +X132753809Y-75605714D01* +X132849047Y-75653333D01* +X133753809Y-76272380D02* +X133753809Y-75272380D01* +X133753809Y-76224761D02* +X133658571Y-76272380D01* +X133468095Y-76272380D01* +X133372857Y-76224761D01* +X133325238Y-76177142D01* +X133277619Y-76081904D01* +X133277619Y-75796190D01* +X133325238Y-75700952D01* +X133372857Y-75653333D01* +X133468095Y-75605714D01* +X133658571Y-75605714D01* +X133753809Y-75653333D01* +X133991904Y-76367619D02* +X134753809Y-76367619D01* +X134991904Y-75748571D02* +X135325238Y-75748571D01* +X135468095Y-76272380D02* +X134991904Y-76272380D01* +X134991904Y-75272380D01* +X135468095Y-75272380D01* +X135801428Y-75605714D02* +X136039523Y-76272380D01* +X136277619Y-75605714D01* +X137039523Y-76224761D02* +X136944285Y-76272380D01* +X136753809Y-76272380D01* +X136658571Y-76224761D01* +X136610952Y-76129523D01* +X136610952Y-75748571D01* +X136658571Y-75653333D01* +X136753809Y-75605714D01* +X136944285Y-75605714D01* +X137039523Y-75653333D01* +X137087142Y-75748571D01* +X137087142Y-75843809D01* +X136610952Y-75939047D01* +X137515714Y-75605714D02* +X137515714Y-76272380D01* +X137515714Y-75700952D02* +X137563333Y-75653333D01* +X137658571Y-75605714D01* +X137801428Y-75605714D01* +X137896666Y-75653333D01* +X137944285Y-75748571D01* +X137944285Y-76272380D01* +X129182380Y-84793333D02* +X129896666Y-84793333D01* +X130039523Y-84840952D01* +X130134761Y-84936190D01* +X130182380Y-85079047D01* +X130182380Y-85174285D01* +X130182380Y-83793333D02* +X130182380Y-84364761D01* +X130182380Y-84079047D02* +X129182380Y-84079047D01* +X129325238Y-84174285D01* +X129420476Y-84269523D01* +X129468095Y-84364761D01* +%TO.C,D2*% +X164968571Y-83533809D02* +X164968571Y-83867142D01* +X165492380Y-83867142D02* +X164492380Y-83867142D01* +X164492380Y-83390952D01* +X165492380Y-83010000D02* +X164492380Y-83010000D01* +X165206666Y-82676666D01* +X164492380Y-82343333D01* +X165492380Y-82343333D01* +X164492380Y-81390952D02* +X164492380Y-81867142D01* +X164968571Y-81914761D01* +X164920952Y-81867142D01* +X164873333Y-81771904D01* +X164873333Y-81533809D01* +X164920952Y-81438571D01* +X164968571Y-81390952D01* +X165063809Y-81343333D01* +X165301904Y-81343333D01* +X165397142Y-81390952D01* +X165444761Y-81438571D01* +X165492380Y-81533809D01* +X165492380Y-81771904D01* +X165444761Y-81867142D01* +X165397142Y-81914761D01* +X164920952Y-80771904D02* +X164873333Y-80867142D01* +X164825714Y-80914761D01* +X164730476Y-80962380D01* +X164682857Y-80962380D01* +X164587619Y-80914761D01* +X164540000Y-80867142D01* +X164492380Y-80771904D01* +X164492380Y-80581428D01* +X164540000Y-80486190D01* +X164587619Y-80438571D01* +X164682857Y-80390952D01* +X164730476Y-80390952D01* +X164825714Y-80438571D01* +X164873333Y-80486190D01* +X164920952Y-80581428D01* +X164920952Y-80771904D01* +X164968571Y-80867142D01* +X165016190Y-80914761D01* +X165111428Y-80962380D01* +X165301904Y-80962380D01* +X165397142Y-80914761D01* +X165444761Y-80867142D01* +X165492380Y-80771904D01* +X165492380Y-80581428D01* +X165444761Y-80486190D01* +X165397142Y-80438571D01* +X165301904Y-80390952D01* +X165111428Y-80390952D01* +X165016190Y-80438571D01* +X164968571Y-80486190D01* +X164920952Y-80581428D01* +X165492380Y-79438571D02* +X165492380Y-80010000D01* +X165492380Y-79724285D02* +X164492380Y-79724285D01* +X164635238Y-79819523D01* +X164730476Y-79914761D01* +X164778095Y-80010000D01* +X164920952Y-78867142D02* +X164873333Y-78962380D01* +X164825714Y-79010000D01* +X164730476Y-79057619D01* +X164682857Y-79057619D01* +X164587619Y-79010000D01* +X164540000Y-78962380D01* +X164492380Y-78867142D01* +X164492380Y-78676666D01* +X164540000Y-78581428D01* +X164587619Y-78533809D01* +X164682857Y-78486190D01* +X164730476Y-78486190D01* +X164825714Y-78533809D01* +X164873333Y-78581428D01* +X164920952Y-78676666D01* +X164920952Y-78867142D01* +X164968571Y-78962380D01* +X165016190Y-79010000D01* +X165111428Y-79057619D01* +X165301904Y-79057619D01* +X165397142Y-79010000D01* +X165444761Y-78962380D01* +X165492380Y-78867142D01* +X165492380Y-78676666D01* +X165444761Y-78581428D01* +X165397142Y-78533809D01* +X165301904Y-78486190D01* +X165111428Y-78486190D01* +X165016190Y-78533809D01* +X164968571Y-78581428D01* +X164920952Y-78676666D01* +X165111428Y-78057619D02* +X165111428Y-77295714D01* +X164492380Y-76914761D02* +X165492380Y-76676666D01* +X164778095Y-76486190D01* +X165492380Y-76295714D01* +X164492380Y-76057619D01* +X170592380Y-80748095D02* +X169592380Y-80748095D01* +X169592380Y-80510000D01* +X169640000Y-80367142D01* +X169735238Y-80271904D01* +X169830476Y-80224285D01* +X170020952Y-80176666D01* +X170163809Y-80176666D01* +X170354285Y-80224285D01* +X170449523Y-80271904D01* +X170544761Y-80367142D01* +X170592380Y-80510000D01* +X170592380Y-80748095D01* +X169687619Y-79795714D02* +X169640000Y-79748095D01* +X169592380Y-79652857D01* +X169592380Y-79414761D01* +X169640000Y-79319523D01* +X169687619Y-79271904D01* +X169782857Y-79224285D01* +X169878095Y-79224285D01* +X170020952Y-79271904D01* +X170592380Y-79843333D01* +X170592380Y-79224285D01* +%TO.C,D5*% +X118094459Y-136127143D02* +X117682066Y-136365239D01* +X117182066Y-135499213D01* +X118121230Y-135506844D02* +X118409905Y-135340178D01* +X118795528Y-135722382D02* +X118383134Y-135960477D01* +X117883134Y-135094451D01* +X118295528Y-134856356D01* +X119166681Y-135508096D02* +X118666681Y-134642070D01* +X118872878Y-134523023D01* +X119020405Y-134492834D01* +X119150503Y-134527693D01* +X119239361Y-134586362D01* +X119375839Y-134727510D01* +X119447267Y-134851228D01* +X119501266Y-135039995D01* +X119507646Y-135146283D01* +X119472786Y-135276380D01* +X119372878Y-135389048D01* +X119166681Y-135508096D01* +D14* +X117393490Y-134365410D02* +X117143490Y-133932397D01* +X117246588Y-133872873D01* +X117320352Y-133857779D01* +X117385401Y-133875209D01* +X117429830Y-133904543D01* +X117498069Y-133975117D01* +X117533783Y-134036976D01* +X117560782Y-134131359D01* +X117563972Y-134184503D01* +X117546543Y-134249552D01* +X117496588Y-134305886D01* +X117393490Y-134365410D01* +X117782699Y-133563350D02* +X117576503Y-133682397D01* +X117674931Y-133900499D01* +X117683646Y-133867974D01* +X117712980Y-133823545D01* +X117816078Y-133764021D01* +X117869223Y-133760831D01* +X117901747Y-133769546D01* +X117946176Y-133798881D01* +X118005700Y-133901979D01* +X118008890Y-133955123D01* +X118000175Y-133987647D01* +X117970840Y-134032077D01* +X117867742Y-134091600D01* +X117814598Y-134094790D01* +X117782074Y-134086075D01* +D12* +%TO.C,M2*% +X121447619Y-60066666D02* +X122447619Y-60066666D01* +X121733333Y-60400000D01* +X122447619Y-60733333D01* +X121447619Y-60733333D01* +X121447619Y-61352380D02* +X121495238Y-61257142D01* +X121542857Y-61209523D01* +X121638095Y-61161904D01* +X121923809Y-61161904D01* +X122019047Y-61209523D01* +X122066666Y-61257142D01* +X122114285Y-61352380D01* +X122114285Y-61495238D01* +X122066666Y-61590476D01* +X122019047Y-61638095D01* +X121923809Y-61685714D01* +X121638095Y-61685714D01* +X121542857Y-61638095D01* +X121495238Y-61590476D01* +X121447619Y-61495238D01* +X121447619Y-61352380D01* +X122114285Y-61971428D02* +X122114285Y-62352380D01* +X122447619Y-62114285D02* +X121590476Y-62114285D01* +X121495238Y-62161904D01* +X121447619Y-62257142D01* +X121447619Y-62352380D01* +X121447619Y-62828571D02* +X121495238Y-62733333D01* +X121542857Y-62685714D01* +X121638095Y-62638095D01* +X121923809Y-62638095D01* +X122019047Y-62685714D01* +X122066666Y-62733333D01* +X122114285Y-62828571D01* +X122114285Y-62971428D01* +X122066666Y-63066666D01* +X122019047Y-63114285D01* +X121923809Y-63161904D01* +X121638095Y-63161904D01* +X121542857Y-63114285D01* +X121495238Y-63066666D01* +X121447619Y-62971428D01* +X121447619Y-62828571D01* +X121447619Y-63590476D02* +X122114285Y-63590476D01* +X121923809Y-63590476D02* +X122019047Y-63638095D01* +X122066666Y-63685714D01* +X122114285Y-63780952D01* +X122114285Y-63876190D01* +%TO.C,BT1*% +X194952380Y-107833333D02* +X194952380Y-108309523D01* +X193952380Y-108309523D01* +X194952380Y-107500000D02* +X194285714Y-107500000D01* +X193952380Y-107500000D02* +X194000000Y-107547619D01* +X194047619Y-107500000D01* +X194000000Y-107452380D01* +X193952380Y-107500000D01* +X194047619Y-107500000D01* +X194571428Y-107023809D02* +X194571428Y-106261904D01* +X194952380Y-105785714D02* +X193952380Y-105785714D01* +X193952380Y-105119047D02* +X193952380Y-104928571D01* +X194000000Y-104833333D01* +X194095238Y-104738095D01* +X194285714Y-104690476D01* +X194619047Y-104690476D01* +X194809523Y-104738095D01* +X194904761Y-104833333D01* +X194952380Y-104928571D01* +X194952380Y-105119047D01* +X194904761Y-105214285D01* +X194809523Y-105309523D01* +X194619047Y-105357142D01* +X194285714Y-105357142D01* +X194095238Y-105309523D01* +X194000000Y-105214285D01* +X193952380Y-105119047D01* +X194952380Y-104261904D02* +X193952380Y-104261904D01* +X194952380Y-103690476D01* +X193952380Y-103690476D01* +%TO.C,J2*% +X122087142Y-119177142D02* +X122039523Y-119224761D01* +X121896666Y-119272380D01* +X121801428Y-119272380D01* +X121658571Y-119224761D01* +X121563333Y-119129523D01* +X121515714Y-119034285D01* +X121468095Y-118843809D01* +X121468095Y-118700952D01* +X121515714Y-118510476D01* +X121563333Y-118415238D01* +X121658571Y-118320000D01* +X121801428Y-118272380D01* +X121896666Y-118272380D01* +X122039523Y-118320000D01* +X122087142Y-118367619D01* +X122658571Y-119272380D02* +X122563333Y-119224761D01* +X122515714Y-119177142D01* +X122468095Y-119081904D01* +X122468095Y-118796190D01* +X122515714Y-118700952D01* +X122563333Y-118653333D01* +X122658571Y-118605714D01* +X122801428Y-118605714D01* +X122896666Y-118653333D01* +X122944285Y-118700952D01* +X122991904Y-118796190D01* +X122991904Y-119081904D01* +X122944285Y-119177142D01* +X122896666Y-119224761D01* +X122801428Y-119272380D01* +X122658571Y-119272380D01* +X123420476Y-118605714D02* +X123420476Y-119272380D01* +X123420476Y-118700952D02* +X123468095Y-118653333D01* +X123563333Y-118605714D01* +X123706190Y-118605714D01* +X123801428Y-118653333D01* +X123849047Y-118748571D01* +X123849047Y-119272380D01* +X124325238Y-118605714D02* +X124325238Y-119272380D01* +X124325238Y-118700952D02* +X124372857Y-118653333D01* +X124468095Y-118605714D01* +X124610952Y-118605714D01* +X124706190Y-118653333D01* +X124753809Y-118748571D01* +X124753809Y-119272380D01* +X124991904Y-119367619D02* +X125753809Y-119367619D01* +X126182380Y-118272380D02* +X126277619Y-118272380D01* +X126372857Y-118320000D01* +X126420476Y-118367619D01* +X126468095Y-118462857D01* +X126515714Y-118653333D01* +X126515714Y-118891428D01* +X126468095Y-119081904D01* +X126420476Y-119177142D01* +X126372857Y-119224761D01* +X126277619Y-119272380D01* +X126182380Y-119272380D01* +X126087142Y-119224761D01* +X126039523Y-119177142D01* +X125991904Y-119081904D01* +X125944285Y-118891428D01* +X125944285Y-118653333D01* +X125991904Y-118462857D01* +X126039523Y-118367619D01* +X126087142Y-118320000D01* +X126182380Y-118272380D01* +X126896666Y-118367619D02* +X126944285Y-118320000D01* +X127039523Y-118272380D01* +X127277619Y-118272380D01* +X127372857Y-118320000D01* +X127420476Y-118367619D01* +X127468095Y-118462857D01* +X127468095Y-118558095D01* +X127420476Y-118700952D01* +X126849047Y-119272380D01* +X127468095Y-119272380D01* +X127801428Y-119272380D02* +X128325238Y-118605714D01* +X127801428Y-118605714D02* +X128325238Y-119272380D01* +X128896666Y-118272380D02* +X128991904Y-118272380D01* +X129087142Y-118320000D01* +X129134761Y-118367619D01* +X129182380Y-118462857D01* +X129230000Y-118653333D01* +X129230000Y-118891428D01* +X129182380Y-119081904D01* +X129134761Y-119177142D01* +X129087142Y-119224761D01* +X128991904Y-119272380D01* +X128896666Y-119272380D01* +X128801428Y-119224761D01* +X128753809Y-119177142D01* +X128706190Y-119081904D01* +X128658571Y-118891428D01* +X128658571Y-118653333D01* +X128706190Y-118462857D01* +X128753809Y-118367619D01* +X128801428Y-118320000D01* +X128896666Y-118272380D01* +X129563333Y-118272380D02* +X130182380Y-118272380D01* +X129849047Y-118653333D01* +X129991904Y-118653333D01* +X130087142Y-118700952D01* +X130134761Y-118748571D01* +X130182380Y-118843809D01* +X130182380Y-119081904D01* +X130134761Y-119177142D01* +X130087142Y-119224761D01* +X129991904Y-119272380D01* +X129706190Y-119272380D01* +X129610952Y-119224761D01* +X129563333Y-119177142D01* +X130372857Y-119367619D02* +X131134761Y-119367619D01* +X131563333Y-118272380D02* +X131753809Y-118272380D01* +X131849047Y-118320000D01* +X131944285Y-118415238D01* +X131991904Y-118605714D01* +X131991904Y-118939047D01* +X131944285Y-119129523D01* +X131849047Y-119224761D01* +X131753809Y-119272380D01* +X131563333Y-119272380D01* +X131468095Y-119224761D01* +X131372857Y-119129523D01* +X131325238Y-118939047D01* +X131325238Y-118605714D01* +X131372857Y-118415238D01* +X131468095Y-118320000D01* +X131563333Y-118272380D01* +X132849047Y-119272380D02* +X132849047Y-118272380D01* +X132849047Y-119224761D02* +X132753809Y-119272380D01* +X132563333Y-119272380D01* +X132468095Y-119224761D01* +X132420476Y-119177142D01* +X132372857Y-119081904D01* +X132372857Y-118796190D01* +X132420476Y-118700952D01* +X132468095Y-118653333D01* +X132563333Y-118605714D01* +X132753809Y-118605714D01* +X132849047Y-118653333D01* +X133753809Y-119272380D02* +X133753809Y-118272380D01* +X133753809Y-119224761D02* +X133658571Y-119272380D01* +X133468095Y-119272380D01* +X133372857Y-119224761D01* +X133325238Y-119177142D01* +X133277619Y-119081904D01* +X133277619Y-118796190D01* +X133325238Y-118700952D01* +X133372857Y-118653333D01* +X133468095Y-118605714D01* +X133658571Y-118605714D01* +X133753809Y-118653333D01* +X133991904Y-119367619D02* +X134753809Y-119367619D01* +X134991904Y-118748571D02* +X135325238Y-118748571D01* +X135468095Y-119272380D02* +X134991904Y-119272380D01* +X134991904Y-118272380D01* +X135468095Y-118272380D01* +X135801428Y-118605714D02* +X136039523Y-119272380D01* +X136277619Y-118605714D01* +X137039523Y-119224761D02* +X136944285Y-119272380D01* +X136753809Y-119272380D01* +X136658571Y-119224761D01* +X136610952Y-119129523D01* +X136610952Y-118748571D01* +X136658571Y-118653333D01* +X136753809Y-118605714D01* +X136944285Y-118605714D01* +X137039523Y-118653333D01* +X137087142Y-118748571D01* +X137087142Y-118843809D01* +X136610952Y-118939047D01* +X137515714Y-118605714D02* +X137515714Y-119272380D01* +X137515714Y-118700952D02* +X137563333Y-118653333D01* +X137658571Y-118605714D01* +X137801428Y-118605714D01* +X137896666Y-118653333D01* +X137944285Y-118748571D01* +X137944285Y-119272380D01* +X129182380Y-127793333D02* +X129896666Y-127793333D01* +X130039523Y-127840952D01* +X130134761Y-127936190D01* +X130182380Y-128079047D01* +X130182380Y-128174285D01* +X129277619Y-127364761D02* +X129230000Y-127317142D01* +X129182380Y-127221904D01* +X129182380Y-126983809D01* +X129230000Y-126888571D01* +X129277619Y-126840952D01* +X129372857Y-126793333D01* +X129468095Y-126793333D01* +X129610952Y-126840952D01* +X130182380Y-127412380D01* +X130182380Y-126793333D01* +%TO.C,P1*% +X200532380Y-117263095D02* +X201341904Y-117263095D01* +X201437142Y-117215476D01* +X201484761Y-117167857D01* +X201532380Y-117072619D01* +X201532380Y-116882142D01* +X201484761Y-116786904D01* +X201437142Y-116739285D01* +X201341904Y-116691666D01* +X200532380Y-116691666D01* +X201484761Y-116263095D02* +X201532380Y-116120238D01* +X201532380Y-115882142D01* +X201484761Y-115786904D01* +X201437142Y-115739285D01* +X201341904Y-115691666D01* +X201246666Y-115691666D01* +X201151428Y-115739285D01* +X201103809Y-115786904D01* +X201056190Y-115882142D01* +X201008571Y-116072619D01* +X200960952Y-116167857D01* +X200913333Y-116215476D01* +X200818095Y-116263095D01* +X200722857Y-116263095D01* +X200627619Y-116215476D01* +X200580000Y-116167857D01* +X200532380Y-116072619D01* +X200532380Y-115834523D01* +X200580000Y-115691666D01* +X201008571Y-114929761D02* +X201056190Y-114786904D01* +X201103809Y-114739285D01* +X201199047Y-114691666D01* +X201341904Y-114691666D01* +X201437142Y-114739285D01* +X201484761Y-114786904D01* +X201532380Y-114882142D01* +X201532380Y-115263095D01* +X200532380Y-115263095D01* +X200532380Y-114929761D01* +X200580000Y-114834523D01* +X200627619Y-114786904D01* +X200722857Y-114739285D01* +X200818095Y-114739285D01* +X200913333Y-114786904D01* +X200960952Y-114834523D01* +X201008571Y-114929761D01* +X201008571Y-115263095D01* +X201627619Y-114501190D02* +X201627619Y-113739285D01* +X201437142Y-112929761D02* +X201484761Y-112977380D01* +X201532380Y-113120238D01* +X201532380Y-113215476D01* +X201484761Y-113358333D01* +X201389523Y-113453571D01* +X201294285Y-113501190D01* +X201103809Y-113548809D01* +X200960952Y-113548809D01* +X200770476Y-113501190D01* +X200675238Y-113453571D01* +X200580000Y-113358333D01* +X200532380Y-113215476D01* +X200532380Y-113120238D01* +X200580000Y-112977380D01* +X200627619Y-112929761D01* +X201627619Y-112739285D02* +X201627619Y-111977380D01* +X201532380Y-111739285D02* +X200532380Y-111739285D01* +X200532380Y-111358333D01* +X200580000Y-111263095D01* +X200627619Y-111215476D01* +X200722857Y-111167857D01* +X200865714Y-111167857D01* +X200960952Y-111215476D01* +X201008571Y-111263095D01* +X201056190Y-111358333D01* +X201056190Y-111739285D01* +X201532380Y-110596428D02* +X201484761Y-110691666D01* +X201389523Y-110739285D01* +X200532380Y-110739285D01* +X200865714Y-109786904D02* +X201532380Y-109786904D01* +X200865714Y-110215476D02* +X201389523Y-110215476D01* +X201484761Y-110167857D01* +X201532380Y-110072619D01* +X201532380Y-109929761D01* +X201484761Y-109834523D01* +X201437142Y-109786904D01* +X200865714Y-108882142D02* +X201675238Y-108882142D01* +X201770476Y-108929761D01* +X201818095Y-108977380D01* +X201865714Y-109072619D01* +X201865714Y-109215476D01* +X201818095Y-109310714D01* +X201484761Y-108882142D02* +X201532380Y-108977380D01* +X201532380Y-109167857D01* +X201484761Y-109263095D01* +X201437142Y-109310714D01* +X201341904Y-109358333D01* +X201056190Y-109358333D01* +X200960952Y-109310714D01* +X200913333Y-109263095D01* +X200865714Y-109167857D01* +X200865714Y-108977380D01* +X200913333Y-108882142D01* +X201627619Y-108644047D02* +X201627619Y-107882142D01* +X200580000Y-107120238D02* +X200532380Y-107215476D01* +X200532380Y-107358333D01* +X200580000Y-107501190D01* +X200675238Y-107596428D01* +X200770476Y-107644047D01* +X200960952Y-107691666D01* +X201103809Y-107691666D01* +X201294285Y-107644047D01* +X201389523Y-107596428D01* +X201484761Y-107501190D01* +X201532380Y-107358333D01* +X201532380Y-107263095D01* +X201484761Y-107120238D01* +X201437142Y-107072619D01* +X201103809Y-107072619D01* +X201103809Y-107263095D01* +X201437142Y-106072619D02* +X201484761Y-106120238D01* +X201532380Y-106263095D01* +X201532380Y-106358333D01* +X201484761Y-106501190D01* +X201389523Y-106596428D01* +X201294285Y-106644047D01* +X201103809Y-106691666D01* +X200960952Y-106691666D01* +X200770476Y-106644047D01* +X200675238Y-106596428D01* +X200580000Y-106501190D01* +X200532380Y-106358333D01* +X200532380Y-106263095D01* +X200580000Y-106120238D01* +X200627619Y-106072619D01* +X200532380Y-105786904D02* +X200532380Y-105215476D01* +X201532380Y-105501190D02* +X200532380Y-105501190D01* +X201627619Y-105120238D02* +X201627619Y-104358333D01* +X200532380Y-104120238D02* +X201341904Y-104120238D01* +X201437142Y-104072619D01* +X201484761Y-104025000D01* +X201532380Y-103929761D01* +X201532380Y-103739285D01* +X201484761Y-103644047D01* +X201437142Y-103596428D01* +X201341904Y-103548809D01* +X200532380Y-103548809D01* +X201484761Y-103120238D02* +X201532380Y-102977380D01* +X201532380Y-102739285D01* +X201484761Y-102644047D01* +X201437142Y-102596428D01* +X201341904Y-102548809D01* +X201246666Y-102548809D01* +X201151428Y-102596428D01* +X201103809Y-102644047D01* +X201056190Y-102739285D01* +X201008571Y-102929761D01* +X200960952Y-103025000D01* +X200913333Y-103072619D01* +X200818095Y-103120238D01* +X200722857Y-103120238D01* +X200627619Y-103072619D01* +X200580000Y-103025000D01* +X200532380Y-102929761D01* +X200532380Y-102691666D01* +X200580000Y-102548809D01* +X201008571Y-101786904D02* +X201056190Y-101644047D01* +X201103809Y-101596428D01* +X201199047Y-101548809D01* +X201341904Y-101548809D01* +X201437142Y-101596428D01* +X201484761Y-101644047D01* +X201532380Y-101739285D01* +X201532380Y-102120238D01* +X200532380Y-102120238D01* +X200532380Y-101786904D01* +X200580000Y-101691666D01* +X200627619Y-101644047D01* +X200722857Y-101596428D01* +X200818095Y-101596428D01* +X200913333Y-101644047D01* +X200960952Y-101691666D01* +X201008571Y-101786904D01* +X201008571Y-102120238D01* +X200865714Y-100691666D02* +X201532380Y-100691666D01* +X200484761Y-100929761D02* +X201199047Y-101167857D01* +X201199047Y-100548809D01* +X201532380Y-99644047D02* +X201532380Y-100215476D01* +X201532380Y-99929761D02* +X200532380Y-99929761D01* +X200675238Y-100025000D01* +X200770476Y-100120238D01* +X200818095Y-100215476D01* +X200627619Y-99263095D02* +X200580000Y-99215476D01* +X200532380Y-99120238D01* +X200532380Y-98882142D01* +X200580000Y-98786904D01* +X200627619Y-98739285D01* +X200722857Y-98691666D01* +X200818095Y-98691666D01* +X200960952Y-98739285D01* +X201532380Y-99310714D01* +X201532380Y-98691666D01* +X200532380Y-97786904D02* +X200532380Y-98263095D01* +X201008571Y-98310714D01* +X200960952Y-98263095D01* +X200913333Y-98167857D01* +X200913333Y-97929761D01* +X200960952Y-97834523D01* +X201008571Y-97786904D01* +X201103809Y-97739285D01* +X201341904Y-97739285D01* +X201437142Y-97786904D01* +X201484761Y-97834523D01* +X201532380Y-97929761D01* +X201532380Y-98167857D01* +X201484761Y-98263095D01* +X201437142Y-98310714D01* +X196182380Y-106763095D02* +X195182380Y-106763095D01* +X195182380Y-106382142D01* +X195230000Y-106286904D01* +X195277619Y-106239285D01* +X195372857Y-106191666D01* +X195515714Y-106191666D01* +X195610952Y-106239285D01* +X195658571Y-106286904D01* +X195706190Y-106382142D01* +X195706190Y-106763095D01* +X196182380Y-105239285D02* +X196182380Y-105810714D01* +X196182380Y-105525000D02* +X195182380Y-105525000D01* +X195325238Y-105620238D01* +X195420476Y-105715476D01* +X195468095Y-105810714D01* +%TO.C,J3*% +X156822142Y-110637142D02* +X156774523Y-110684761D01* +X156631666Y-110732380D01* +X156536428Y-110732380D01* +X156393571Y-110684761D01* +X156298333Y-110589523D01* +X156250714Y-110494285D01* +X156203095Y-110303809D01* +X156203095Y-110160952D01* +X156250714Y-109970476D01* +X156298333Y-109875238D01* +X156393571Y-109780000D01* +X156536428Y-109732380D01* +X156631666Y-109732380D01* +X156774523Y-109780000D01* +X156822142Y-109827619D01* +X157393571Y-110732380D02* +X157298333Y-110684761D01* +X157250714Y-110637142D01* +X157203095Y-110541904D01* +X157203095Y-110256190D01* +X157250714Y-110160952D01* +X157298333Y-110113333D01* +X157393571Y-110065714D01* +X157536428Y-110065714D01* +X157631666Y-110113333D01* +X157679285Y-110160952D01* +X157726904Y-110256190D01* +X157726904Y-110541904D01* +X157679285Y-110637142D01* +X157631666Y-110684761D01* +X157536428Y-110732380D01* +X157393571Y-110732380D01* +X158155476Y-110065714D02* +X158155476Y-110732380D01* +X158155476Y-110160952D02* +X158203095Y-110113333D01* +X158298333Y-110065714D01* +X158441190Y-110065714D01* +X158536428Y-110113333D01* +X158584047Y-110208571D01* +X158584047Y-110732380D01* +X159060238Y-110065714D02* +X159060238Y-110732380D01* +X159060238Y-110160952D02* +X159107857Y-110113333D01* +X159203095Y-110065714D01* +X159345952Y-110065714D01* +X159441190Y-110113333D01* +X159488809Y-110208571D01* +X159488809Y-110732380D01* +X159726904Y-110827619D02* +X160488809Y-110827619D01* +X160917380Y-109732380D02* +X161012619Y-109732380D01* +X161107857Y-109780000D01* +X161155476Y-109827619D01* +X161203095Y-109922857D01* +X161250714Y-110113333D01* +X161250714Y-110351428D01* +X161203095Y-110541904D01* +X161155476Y-110637142D01* +X161107857Y-110684761D01* +X161012619Y-110732380D01* +X160917380Y-110732380D01* +X160822142Y-110684761D01* +X160774523Y-110637142D01* +X160726904Y-110541904D01* +X160679285Y-110351428D01* +X160679285Y-110113333D01* +X160726904Y-109922857D01* +X160774523Y-109827619D01* +X160822142Y-109780000D01* +X160917380Y-109732380D01* +X161631666Y-109827619D02* +X161679285Y-109780000D01* +X161774523Y-109732380D01* +X162012619Y-109732380D01* +X162107857Y-109780000D01* +X162155476Y-109827619D01* +X162203095Y-109922857D01* +X162203095Y-110018095D01* +X162155476Y-110160952D01* +X161584047Y-110732380D01* +X162203095Y-110732380D01* +X162536428Y-110732380D02* +X163060238Y-110065714D01* +X162536428Y-110065714D02* +X163060238Y-110732380D01* +X163631666Y-109732380D02* +X163726904Y-109732380D01* +X163822142Y-109780000D01* +X163869761Y-109827619D01* +X163917380Y-109922857D01* +X163965000Y-110113333D01* +X163965000Y-110351428D01* +X163917380Y-110541904D01* +X163869761Y-110637142D01* +X163822142Y-110684761D01* +X163726904Y-110732380D01* +X163631666Y-110732380D01* +X163536428Y-110684761D01* +X163488809Y-110637142D01* +X163441190Y-110541904D01* +X163393571Y-110351428D01* +X163393571Y-110113333D01* +X163441190Y-109922857D01* +X163488809Y-109827619D01* +X163536428Y-109780000D01* +X163631666Y-109732380D01* +X164869761Y-109732380D02* +X164393571Y-109732380D01* +X164345952Y-110208571D01* +X164393571Y-110160952D01* +X164488809Y-110113333D01* +X164726904Y-110113333D01* +X164822142Y-110160952D01* +X164869761Y-110208571D01* +X164917380Y-110303809D01* +X164917380Y-110541904D01* +X164869761Y-110637142D01* +X164822142Y-110684761D01* +X164726904Y-110732380D01* +X164488809Y-110732380D01* +X164393571Y-110684761D01* +X164345952Y-110637142D01* +X165107857Y-110827619D02* +X165869761Y-110827619D01* +X166298333Y-109732380D02* +X166488809Y-109732380D01* +X166584047Y-109780000D01* +X166679285Y-109875238D01* +X166726904Y-110065714D01* +X166726904Y-110399047D01* +X166679285Y-110589523D01* +X166584047Y-110684761D01* +X166488809Y-110732380D01* +X166298333Y-110732380D01* +X166203095Y-110684761D01* +X166107857Y-110589523D01* +X166060238Y-110399047D01* +X166060238Y-110065714D01* +X166107857Y-109875238D01* +X166203095Y-109780000D01* +X166298333Y-109732380D01* +X167584047Y-110732380D02* +X167584047Y-109732380D01* +X167584047Y-110684761D02* +X167488809Y-110732380D01* +X167298333Y-110732380D01* +X167203095Y-110684761D01* +X167155476Y-110637142D01* +X167107857Y-110541904D01* +X167107857Y-110256190D01* +X167155476Y-110160952D01* +X167203095Y-110113333D01* +X167298333Y-110065714D01* +X167488809Y-110065714D01* +X167584047Y-110113333D01* +X168488809Y-110732380D02* +X168488809Y-109732380D01* +X168488809Y-110684761D02* +X168393571Y-110732380D01* +X168203095Y-110732380D01* +X168107857Y-110684761D01* +X168060238Y-110637142D01* +X168012619Y-110541904D01* +X168012619Y-110256190D01* +X168060238Y-110160952D01* +X168107857Y-110113333D01* +X168203095Y-110065714D01* +X168393571Y-110065714D01* +X168488809Y-110113333D01* +X168726904Y-110827619D02* +X169488809Y-110827619D01* +X169726904Y-110208571D02* +X170060238Y-110208571D01* +X170203095Y-110732380D02* +X169726904Y-110732380D01* +X169726904Y-109732380D01* +X170203095Y-109732380D01* +X170536428Y-110065714D02* +X170774523Y-110732380D01* +X171012619Y-110065714D01* +X171774523Y-110684761D02* +X171679285Y-110732380D01* +X171488809Y-110732380D01* +X171393571Y-110684761D01* +X171345952Y-110589523D01* +X171345952Y-110208571D01* +X171393571Y-110113333D01* +X171488809Y-110065714D01* +X171679285Y-110065714D01* +X171774523Y-110113333D01* +X171822142Y-110208571D01* +X171822142Y-110303809D01* +X171345952Y-110399047D01* +X172250714Y-110065714D02* +X172250714Y-110732380D01* +X172250714Y-110160952D02* +X172298333Y-110113333D01* +X172393571Y-110065714D01* +X172536428Y-110065714D01* +X172631666Y-110113333D01* +X172679285Y-110208571D01* +X172679285Y-110732380D01* +X163917380Y-106378333D02* +X164631666Y-106378333D01* +X164774523Y-106425952D01* +X164869761Y-106521190D01* +X164917380Y-106664047D01* +X164917380Y-106759285D01* +X163917380Y-105997380D02* +X163917380Y-105378333D01* +X164298333Y-105711666D01* +X164298333Y-105568809D01* +X164345952Y-105473571D01* +X164393571Y-105425952D01* +X164488809Y-105378333D01* +X164726904Y-105378333D01* +X164822142Y-105425952D01* +X164869761Y-105473571D01* +X164917380Y-105568809D01* +X164917380Y-105854523D01* +X164869761Y-105949761D01* +X164822142Y-105997380D01* +%TO.C,L2*% +X165195476Y-88122619D02* +X165243095Y-88075000D01* +X165338333Y-88027380D01* +X165576428Y-88027380D01* +X165671666Y-88075000D01* +X165719285Y-88122619D01* +X165766904Y-88217857D01* +X165766904Y-88313095D01* +X165719285Y-88455952D01* +X165147857Y-89027380D01* +X165766904Y-89027380D01* +X166147857Y-88122619D02* +X166195476Y-88075000D01* +X166290714Y-88027380D01* +X166528809Y-88027380D01* +X166624047Y-88075000D01* +X166671666Y-88122619D01* +X166719285Y-88217857D01* +X166719285Y-88313095D01* +X166671666Y-88455952D01* +X166100238Y-89027380D01* +X166719285Y-89027380D01* +X167147857Y-88360714D02* +X167147857Y-89360714D01* +X167624047Y-88884523D02* +X167671666Y-88979761D01* +X167766904Y-89027380D01* +X167147857Y-88884523D02* +X167195476Y-88979761D01* +X167290714Y-89027380D01* +X167481190Y-89027380D01* +X167576428Y-88979761D01* +X167624047Y-88884523D01* +X167624047Y-88360714D01* +X168195476Y-89027380D02* +X168195476Y-88027380D01* +X168195476Y-88503571D02* +X168766904Y-88503571D01* +X168766904Y-89027380D02* +X168766904Y-88027380D01* +X166838333Y-92527380D02* +X166362142Y-92527380D01* +X166362142Y-91527380D01* +X167124047Y-91622619D02* +X167171666Y-91575000D01* +X167266904Y-91527380D01* +X167505000Y-91527380D01* +X167600238Y-91575000D01* +X167647857Y-91622619D01* +X167695476Y-91717857D01* +X167695476Y-91813095D01* +X167647857Y-91955952D01* +X167076428Y-92527380D01* +X167695476Y-92527380D01* +%TO.C,U1*% +X141687380Y-115033333D02* +X142687380Y-114366666D01* +X141687380Y-114366666D02* +X142687380Y-115033333D01* +X142163571Y-113652380D02* +X142211190Y-113509523D01* +X142258809Y-113461904D01* +X142354047Y-113414285D01* +X142496904Y-113414285D01* +X142592142Y-113461904D01* +X142639761Y-113509523D01* +X142687380Y-113604761D01* +X142687380Y-113985714D01* +X141687380Y-113985714D01* +X141687380Y-113652380D01* +X141735000Y-113557142D01* +X141782619Y-113509523D01* +X141877857Y-113461904D01* +X141973095Y-113461904D01* +X142068333Y-113509523D01* +X142115952Y-113557142D01* +X142163571Y-113652380D01* +X142163571Y-113985714D01* +X142163571Y-112985714D02* +X142163571Y-112652380D01* +X142687380Y-112509523D02* +X142687380Y-112985714D01* +X141687380Y-112985714D01* +X141687380Y-112509523D01* +X142163571Y-112080952D02* +X142163571Y-111747619D01* +X142687380Y-111604761D02* +X142687380Y-112080952D01* +X141687380Y-112080952D01* +X141687380Y-111604761D01* +X142306428Y-111176190D02* +X142306428Y-110414285D01* +X141687380Y-110033333D02* +X141687380Y-109414285D01* +X142068333Y-109747619D01* +X142068333Y-109604761D01* +X142115952Y-109509523D01* +X142163571Y-109461904D01* +X142258809Y-109414285D01* +X142496904Y-109414285D01* +X142592142Y-109461904D01* +X142639761Y-109509523D01* +X142687380Y-109604761D01* +X142687380Y-109890476D01* +X142639761Y-109985714D01* +X142592142Y-110033333D01* +%TO.C,D4*% +X116953459Y-134222143D02* +X116541066Y-134460239D01* +X116041066Y-133594213D01* +X116980230Y-133601844D02* +X117268905Y-133435178D01* +X117654528Y-133817382D02* +X117242134Y-134055477D01* +X116742134Y-133189451D01* +X117154528Y-132951356D01* +X118025681Y-133603096D02* +X117525681Y-132737070D01* +X117731878Y-132618023D01* +X117879405Y-132587834D01* +X118009503Y-132622693D01* +X118098361Y-132681362D01* +X118234839Y-132822510D01* +X118306267Y-132946228D01* +X118360266Y-133134995D01* +X118366646Y-133241283D01* +X118331786Y-133371380D01* +X118231878Y-133484048D01* +X118025681Y-133603096D01* +D14* +X116252490Y-132460410D02* +X116002490Y-132027397D01* +X116105588Y-131967873D01* +X116179352Y-131952779D01* +X116244401Y-131970209D01* +X116288830Y-131999543D01* +X116357069Y-132070117D01* +X116392783Y-132131976D01* +X116419782Y-132226359D01* +X116422972Y-132279503D01* +X116405543Y-132344552D01* +X116355588Y-132400886D01* +X116252490Y-132460410D01* +X116704413Y-131814592D02* +X116871080Y-132103267D01* +X116506077Y-131709159D02* +X116581550Y-132077977D01* +X116849605Y-131923215D01* +D12* +%TO.C,D3*% +X115894459Y-132317143D02* +X115482066Y-132555239D01* +X114982066Y-131689213D01* +X115921230Y-131696844D02* +X116209905Y-131530178D01* +X116595528Y-131912382D02* +X116183134Y-132150477D01* +X115683134Y-131284451D01* +X116095528Y-131046356D01* +X116966681Y-131698096D02* +X116466681Y-130832070D01* +X116672878Y-130713023D01* +X116820405Y-130682834D01* +X116950503Y-130717693D01* +X117039361Y-130776362D01* +X117175839Y-130917510D01* +X117247267Y-131041228D01* +X117301266Y-131229995D01* +X117307646Y-131336283D01* +X117272786Y-131466380D01* +X117172878Y-131579048D01* +X116966681Y-131698096D01* +D14* +X115193490Y-130555410D02* +X114943490Y-130122397D01* +X115046588Y-130062873D01* +X115120352Y-130047779D01* +X115185401Y-130065209D01* +X115229830Y-130094543D01* +X115298069Y-130165117D01* +X115333783Y-130226976D01* +X115360782Y-130321359D01* +X115363972Y-130374503D01* +X115346543Y-130439552D01* +X115296588Y-130495886D01* +X115193490Y-130555410D01* +X115335264Y-129896207D02* +X115603319Y-129741445D01* +X115554220Y-129989735D01* +X115616078Y-129954021D01* +X115669223Y-129950831D01* +X115701747Y-129959546D01* +X115746176Y-129988881D01* +X115805700Y-130091979D01* +X115808890Y-130145123D01* +X115800175Y-130177647D01* +X115770840Y-130222077D01* +X115647122Y-130293505D01* +X115593978Y-130296695D01* +X115561454Y-130287980D01* +D12* +%TO.C,C11*% +X192872380Y-168305832D02* +X192872380Y-168877261D01* +X192872380Y-168591546D02* +X191872380Y-168591546D01* +X192015238Y-168686785D01* +X192110476Y-168782023D01* +X192158095Y-168877261D01* +X192205714Y-167877261D02* +X193205714Y-167877261D01* +X192729523Y-167401070D02* +X192824761Y-167353451D01* +X192872380Y-167258213D01* +X192729523Y-167877261D02* +X192824761Y-167829642D01* +X192872380Y-167734404D01* +X192872380Y-167543927D01* +X192824761Y-167448689D01* +X192729523Y-167401070D01* +X192205714Y-167401070D01* +X192348571Y-166496308D02* +X192348571Y-166829642D01* +X192872380Y-166829642D02* +X191872380Y-166829642D01* +X191872380Y-166353451D01* +D14* +X190918571Y-167960594D02* +X190942380Y-167984404D01* +X190966190Y-168055832D01* +X190966190Y-168103451D01* +X190942380Y-168174880D01* +X190894761Y-168222499D01* +X190847142Y-168246308D01* +X190751904Y-168270118D01* +X190680476Y-168270118D01* +X190585238Y-168246308D01* +X190537619Y-168222499D01* +X190490000Y-168174880D01* +X190466190Y-168103451D01* +X190466190Y-168055832D01* +X190490000Y-167984404D01* +X190513809Y-167960594D01* +X190966190Y-167484404D02* +X190966190Y-167770118D01* +X190966190Y-167627261D02* +X190466190Y-167627261D01* +X190537619Y-167674880D01* +X190585238Y-167722499D01* +X190609047Y-167770118D01* +X190966190Y-167008213D02* +X190966190Y-167293927D01* +X190966190Y-167151070D02* +X190466190Y-167151070D01* +X190537619Y-167198689D01* +X190585238Y-167246308D01* +X190609047Y-167293927D01* +D13* +%TO.C,SW1*% +X116039920Y-77593218D02* +X114859544Y-79909835D01* +X118392384Y-82888349D02* +X115273861Y-81299382D01* +X120526139Y-78700618D02* +X117407616Y-77111651D01* +X116039920Y-77593218D02* +X116930926Y-78047208D01* +X120526139Y-78700618D02* +X118392384Y-82888349D01* +X114859544Y-79909835D02* +X115750551Y-80363825D01* +X117407616Y-77111651D02* +X115273861Y-81299382D01* +%TO.C,J1*% +X126480000Y-90910000D02* +X126480000Y-78010000D01* +X125280000Y-92100000D02* +X125280000Y-76820000D01* +X126480000Y-78010000D02* +X132980000Y-78010000D01* +X125280000Y-76820000D02* +X134180000Y-76820000D01* +X134180000Y-76820000D02* +X134180000Y-91100000D01* +X132980000Y-86510000D02* +X132980000Y-90910000D01* +X132980000Y-82410000D02* +X134180000Y-82410000D01* +X134180000Y-86510000D02* +X132980000Y-86510000D01* +X132980000Y-90910000D02* +X126480000Y-90910000D01* +X132980000Y-82410000D02* +X132980000Y-82410000D01* +X132980000Y-78010000D02* +X132980000Y-82410000D01* +X134180000Y-91100000D02* +X133180000Y-92100000D01* +X133180000Y-92100000D02* +X125280000Y-92100000D01* +%TO.C,D2*% +X167638980Y-79360560D02* +X167638980Y-78458860D01* +X166140000Y-82310000D02* +X166140000Y-77710000D01* +X169140000Y-82310000D02* +X166140000Y-82310000D01* +X168439080Y-79360560D02* +X166838880Y-79360560D01* +X166140000Y-77710000D02* +X169140000Y-77710000D01* +X167638980Y-80511180D02* +X167638980Y-81509400D01* +X166889680Y-80511180D02* +X168439080Y-80511180D01* +X167638980Y-79360560D02* +X166889680Y-80511180D01* +X169140000Y-82310000D02* +X169140000Y-77710000D01* +X167638980Y-79360560D02* +X168439080Y-80511180D01* +%TO.C,D5*% +X117033975Y-135004615D02* +X118766025Y-134004615D01* +X116693782Y-133815385D02* +X116583975Y-134225192D01* +X118166025Y-132965385D02* +X116693782Y-133815385D01* +X118766025Y-134004615D02* +X118166025Y-132965385D01* +X116583975Y-134225192D02* +X117033975Y-135004615D01* +%TO.C,J2*% +X133180000Y-135100000D02* +X125280000Y-135100000D01* +X132980000Y-133910000D02* +X126480000Y-133910000D01* +X126480000Y-133910000D02* +X126480000Y-121010000D01* +X125280000Y-135100000D02* +X125280000Y-119820000D01* +X125280000Y-119820000D02* +X134180000Y-119820000D01* +X132980000Y-125410000D02* +X132980000Y-125410000D01* +X134180000Y-129510000D02* +X132980000Y-129510000D01* +X126480000Y-121010000D02* +X132980000Y-121010000D01* +X132980000Y-129510000D02* +X132980000Y-133910000D01* +X132980000Y-121010000D02* +X132980000Y-125410000D01* +X134180000Y-119820000D02* +X134180000Y-134100000D01* +X132980000Y-125410000D02* +X134180000Y-125410000D01* +X134180000Y-134100000D02* +X133180000Y-135100000D01* +%TO.C,P1*% +X191145000Y-101550000D02* +X197955000Y-101550000D01* +X191145000Y-110500000D02* +X197955000Y-110500000D01* +X191145000Y-110500000D02* +X191145000Y-101550000D01* +X197955000Y-110500000D02* +X197955000Y-101550000D01* +%TO.C,J3*% +X167215000Y-107515000D02* +X166170000Y-107515000D01* +X167215000Y-103305000D02* +X167215000Y-103705000D01* +X163195000Y-102870000D02* +X166170000Y-102870000D01* +X167215000Y-103705000D02* +X166170000Y-103705000D01* +X161715000Y-108385000D02* +X161715000Y-108785000D01* +X167215000Y-107115000D02* +X167215000Y-107515000D01* +X162760000Y-103305000D02* +X163195000Y-102870000D01* +X161715000Y-107515000D02* +X162760000Y-107515000D01* +X166170000Y-103305000D02* +X167215000Y-103305000D01* +X166170000Y-108385000D02* +X167215000Y-108385000D01* +X162760000Y-109220000D02* +X162760000Y-103305000D01* +X161715000Y-108785000D02* +X162760000Y-108785000D01* +X161715000Y-104975000D02* +X162760000Y-104975000D01* +X167215000Y-104975000D02* +X166170000Y-104975000D01* +X166170000Y-107115000D02* +X167215000Y-107115000D01* +X161715000Y-103305000D02* +X161715000Y-103705000D01* +X162760000Y-108385000D02* +X161715000Y-108385000D01* +X167215000Y-108785000D02* +X166170000Y-108785000D01* +X161715000Y-103705000D02* +X162760000Y-103705000D01* +X166170000Y-102870000D02* +X166170000Y-109220000D01* +X166170000Y-109220000D02* +X162760000Y-109220000D01* +X162760000Y-107115000D02* +X161715000Y-107115000D01* +X167215000Y-104575000D02* +X167215000Y-104975000D01* +X161715000Y-106245000D02* +X162760000Y-106245000D01* +X161715000Y-104575000D02* +X161715000Y-104975000D01* +X162760000Y-103305000D02* +X161715000Y-103305000D01* +X167215000Y-105845000D02* +X167215000Y-106245000D01* +X166170000Y-105845000D02* +X167215000Y-105845000D01* +X166170000Y-104575000D02* +X167215000Y-104575000D01* +X167215000Y-108385000D02* +X167215000Y-108785000D01* +X162760000Y-104575000D02* +X161715000Y-104575000D01* +X161715000Y-105845000D02* +X161715000Y-106245000D01* +X162760000Y-105845000D02* +X161715000Y-105845000D01* +X161715000Y-107115000D02* +X161715000Y-107515000D01* +X167215000Y-106245000D02* +X166170000Y-106245000D01* +%TO.C,L2*% +X165005000Y-90075000D02* +X165005000Y-94075000D01* +X169005000Y-90075000D02* +X165005000Y-90075000D01* +X169005000Y-94075000D02* +X169005000Y-90075000D01* +X165005000Y-94075000D02* +X169005000Y-94075000D01* +%TO.C,D4*% +X117025025Y-131060385D02* +X115552782Y-131910385D01* +X115892975Y-133099615D02* +X117625025Y-132099615D01* +X115552782Y-131910385D02* +X115442975Y-132320192D01* +X115442975Y-132320192D02* +X115892975Y-133099615D01* +X117625025Y-132099615D02* +X117025025Y-131060385D01* +%TO.C,D3*% +X114383975Y-130415192D02* +X114833975Y-131194615D01* +X115966025Y-129155385D02* +X114493782Y-130005385D01* +X114833975Y-131194615D02* +X116566025Y-130194615D01* +X114493782Y-130005385D02* +X114383975Y-130415192D01* +X116566025Y-130194615D02* +X115966025Y-129155385D01* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Mask.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Mask.gbr new file mode 100644 index 0000000..a4b0ecc --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Mask.gbr @@ -0,0 +1,330 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Soldermask,Top*% +%TF.FilePolarity,Negative*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +%AMRotRect* +0 Rectangle, with rotation* +0 The origin of the aperture is its center* +0 $1 length* +0 $2 width* +0 $3 Rotation angle, in degrees counterclockwise* +0 Add horizontal line* +21,1,$1,$2,0,0,$3*% +G04 Aperture macros list end* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12RotRect,1.550000X1.000000X243.000000*% +%ADD13RoundRect,0.250000X0.600000X0.600000X-0.600000X0.600000X-0.600000X-0.600000X0.600000X-0.600000X0*% +%ADD14C,1.700000*% +%ADD15R,1.800000X2.500000*% +%ADD16RoundRect,0.243750X0.017031X-0.516999X0.439219X-0.273249X-0.017031X0.516999X-0.439219X0.273249X0*% +%ADD17C,3.500000*% +%ADD18R,1.200000X0.700000*% +%ADD19R,1.200000X0.760000*% +%ADD20R,1.200000X0.800000*% +%ADD21O,1.700000X1.100000*% +%ADD22R,2.400000X0.740000*% +%ADD23R,1.200000X3.700000*% +%ADD24R,1.200000X1.200000*% +%ADD25C,1.200000*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.C,SW1*% +X118334370Y-77275216D03* +X115950919Y-81953000D03* +X119849081Y-78047000D03* +X117465630Y-82724784D03* +%TD*% +D13* +%TO.C,J1*% +X131000000Y-87000000D03* +D14* +X128460000Y-87000000D03* +X131000000Y-84460000D03* +X128460000Y-84460000D03* +X131000000Y-81920000D03* +X128460000Y-81920000D03* +%TD*% +D15* +%TO.C,D2*% +X167640000Y-78010000D03* +X167640000Y-82010000D03* +%TD*% +D16* +%TO.C,D5*% +X116788101Y-134453750D03* +X118411899Y-133516250D03* +%TD*% +D17* +%TO.C,BT1*% +X180500000Y-124250000D03* +X180500000Y-131850000D03* +X180500000Y-80150000D03* +X180500000Y-87750000D03* +%TD*% +D13* +%TO.C,J2*% +X131000000Y-130000000D03* +D14* +X128460000Y-130000000D03* +X131000000Y-127460000D03* +X128460000Y-127460000D03* +X131000000Y-124920000D03* +X128460000Y-124920000D03* +%TD*% +D18* +%TO.C,P1*% +X191835000Y-106530000D03* +D19* +X191835000Y-104510000D03* +D20* +X191835000Y-103280000D03* +D18* +X191835000Y-105530000D03* +D19* +X191835000Y-107550000D03* +D20* +X191835000Y-108780000D03* +D21* +X191835000Y-101710000D03* +X195635000Y-110350000D03* +X195635000Y-101700000D03* +X191835000Y-110350000D03* +%TD*% +D22* +%TO.C,J3*% +X162515000Y-103505000D03* +X166415000Y-103505000D03* +X162515000Y-104775000D03* +X166415000Y-104775000D03* +X162515000Y-106045000D03* +X166415000Y-106045000D03* +X162515000Y-107315000D03* +X166415000Y-107315000D03* +X162515000Y-108585000D03* +X166415000Y-108585000D03* +%TD*% +D23* +%TO.C,L2*% +X168405000Y-92075000D03* +X165605000Y-92075000D03* +%TD*% +D24* +%TO.C,U1*% +X119435000Y-116800000D03* +D25* +X121435000Y-116800000D03* +X123435000Y-116800000D03* +X125435000Y-116800000D03* +X127435000Y-116800000D03* +X129435000Y-116800000D03* +X131435000Y-116800000D03* +X133435000Y-116800000D03* +X135435000Y-116800000D03* +X137435000Y-116800000D03* +X137435000Y-94800000D03* +X135435000Y-94800000D03* +X133435000Y-94800000D03* +X131435000Y-94800000D03* +X129435000Y-94800000D03* +X127435000Y-94800000D03* +X125435000Y-94800000D03* +X123435000Y-94800000D03* +X121435000Y-94800000D03* +X119435000Y-94800000D03* +%TD*% +D16* +%TO.C,D4*% +X115647101Y-132548750D03* +X117270899Y-131611250D03* +%TD*% +%TO.C,D3*% +X114588101Y-130643750D03* +X116211899Y-129706250D03* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Paste.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Paste.gbr new file mode 100644 index 0000000..a759076 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Paste.gbr @@ -0,0 +1,268 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Paste,Top*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +%AMRotRect* +0 Rectangle, with rotation* +0 The origin of the aperture is its center* +0 $1 length* +0 $2 width* +0 $3 Rotation angle, in degrees counterclockwise* +0 Add horizontal line* +21,1,$1,$2,0,0,$3*% +G04 Aperture macros list end* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12RotRect,1.550000X1.000000X243.000000*% +%ADD13R,1.800000X2.500000*% +%ADD14RoundRect,0.243750X0.017031X-0.516999X0.439219X-0.273249X-0.017031X0.516999X-0.439219X0.273249X0*% +%ADD15R,1.200000X0.700000*% +%ADD16R,1.200000X0.760000*% +%ADD17R,1.200000X0.800000*% +%ADD18R,2.400000X0.740000*% +%ADD19R,1.200000X3.700000*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.C,SW1*% +X118334370Y-77275216D03* +X115950919Y-81953000D03* +X119849081Y-78047000D03* +X117465630Y-82724784D03* +%TD*% +D13* +%TO.C,D2*% +X167640000Y-78010000D03* +X167640000Y-82010000D03* +%TD*% +D14* +%TO.C,D5*% +X116788101Y-134453750D03* +X118411899Y-133516250D03* +%TD*% +D15* +%TO.C,P1*% +X191835000Y-106530000D03* +D16* +X191835000Y-104510000D03* +D17* +X191835000Y-103280000D03* +D15* +X191835000Y-105530000D03* +D16* +X191835000Y-107550000D03* +D17* +X191835000Y-108780000D03* +%TD*% +D18* +%TO.C,J3*% +X162515000Y-103505000D03* +X166415000Y-103505000D03* +X162515000Y-104775000D03* +X166415000Y-104775000D03* +X162515000Y-106045000D03* +X166415000Y-106045000D03* +X162515000Y-107315000D03* +X166415000Y-107315000D03* +X162515000Y-108585000D03* +X166415000Y-108585000D03* +%TD*% +D19* +%TO.C,L2*% +X168405000Y-92075000D03* +X165605000Y-92075000D03* +%TD*% +D14* +%TO.C,D4*% +X115647101Y-132548750D03* +X117270899Y-131611250D03* +%TD*% +%TO.C,D3*% +X114588101Y-130643750D03* +X116211899Y-129706250D03* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Silkscreen.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Silkscreen.gbr new file mode 100644 index 0000000..11dc53b --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Silkscreen.gbr @@ -0,0 +1,717 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1*% +%TF.CreationDate,2022-08-31T16:11:48+02:00*% +%TF.ProjectId,dumber-v3,64756d62-6572-42d7-9633-2e6b69636164,1.1*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Legend,Top*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 6.0.7-f9a2dced07~116~ubuntu20.04.1) date 2022-08-31 16:11:48* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,Profile*% +%ADD10C,0.010050*% +%TD*% +%TA.AperFunction,Profile*% +%ADD11C,0.500000*% +%TD*% +%ADD12C,0.150000*% +%ADD13C,0.300000*% +%ADD14C,0.120000*% +G04 APERTURE END LIST* +D10* +X173755025Y-70000000D02* +G75* +G03* +X173755025Y-70000000I-5025J0D01* +G01* +X141505025Y-86500000D02* +G75* +G03* +X141505025Y-86500000I-5025J0D01* +G01* +D11* +X175350000Y-70000000D02* +G75* +G03* +X175350000Y-70000000I-1600000J0D01* +G01* +X142550000Y-86500000D02* +G75* +G03* +X142550000Y-86500000I-1050000J0D01* +G01* +X167750000Y-63000000D02* +X167750000Y-71500000D01* +X109750000Y-96000000D02* +X109750000Y-116000000D01* +X129350000Y-142000000D02* +G75* +G03* +X129350000Y-142000000I-1600000J0D01* +G01* +X127750000Y-63000000D02* +G75* +G03* +X109750000Y-96000000I21250000J-33000000D01* +G01* +X197750000Y-127000000D02* +X197750000Y-85000000D01* +X129350000Y-70000000D02* +G75* +G03* +X129350000Y-70000000I-1600000J0D01* +G01* +X167750000Y-149000000D02* +X172750000Y-149000000D01* +X172750000Y-63000000D02* +X167750000Y-63000000D01* +D10* +X172755025Y-123795455D02* +G75* +G03* +X172755025Y-123795455I-5025J0D01* +G01* +X159005025Y-125500000D02* +G75* +G03* +X159005025Y-125500000I-5025J0D01* +G01* +X159005025Y-86500000D02* +G75* +G03* +X159005025Y-86500000I-5025J0D01* +G01* +X172755025Y-88204545D02* +G75* +G03* +X172755025Y-88204545I-5025J0D01* +G01* +X149005025Y-116000000D02* +G75* +G03* +X149005025Y-116000000I-5025J0D01* +G01* +D11* +X132750000Y-149000000D02* +X132750000Y-140500000D01* +X167750000Y-140500000D02* +X167750000Y-149000000D01* +X127750000Y-149000000D02* +X132750000Y-149000000D01* +X167750000Y-71500000D02* +X132750000Y-71500000D01* +D10* +X127755025Y-70000000D02* +G75* +G03* +X127755025Y-70000000I-5025J0D01* +G01* +D11* +X109750000Y-116000000D02* +G75* +G03* +X127750000Y-149000000I39250000J0D01* +G01* +X175350000Y-142000000D02* +G75* +G03* +X175350000Y-142000000I-1600000J0D01* +G01* +D10* +X149005025Y-96000000D02* +G75* +G03* +X149005025Y-96000000I-5025J0D01* +G01* +D11* +X132750000Y-63000000D02* +X127750000Y-63000000D01* +X132750000Y-71500000D02* +X132750000Y-63000000D01* +X197750047Y-84999994D02* +G75* +G03* +X172750000Y-63000000I-25000047J-3204606D01* +G01* +X160050000Y-86500000D02* +G75* +G03* +X160050000Y-86500000I-1050000J0D01* +G01* +D10* +X173755025Y-142000000D02* +G75* +G03* +X173755025Y-142000000I-5025J0D01* +G01* +X141505025Y-125500000D02* +G75* +G03* +X141505025Y-125500000I-5025J0D01* +G01* +D11* +X132750000Y-140500000D02* +X167750000Y-140500000D01* +X160050000Y-125500000D02* +G75* +G03* +X160050000Y-125500000I-1050000J0D01* +G01* +X142550000Y-125500000D02* +G75* +G03* +X142550000Y-125500000I-1050000J0D01* +G01* +X172750000Y-149000005D02* +G75* +G03* +X197750000Y-127000000I0J25204545D01* +G01* +D10* +X127755025Y-142000000D02* +G75* +G03* +X127755025Y-142000000I-5025J0D01* +G01* +D12* +%TO.C,M1*% +X159952380Y-138809523D02* +X158952380Y-138809523D01* +X159666666Y-138476190D01* +X158952380Y-138142857D01* +X159952380Y-138142857D01* +X159952380Y-137142857D02* +X159952380Y-137714285D01* +X159952380Y-137428571D02* +X158952380Y-137428571D01* +X159095238Y-137523809D01* +X159190476Y-137619047D01* +X159238095Y-137714285D01* +%TO.C,SW1*% +X119770324Y-84556766D02* +X119877609Y-84451098D01* +X119985702Y-84238954D01* +X119986510Y-84132477D01* +X119965700Y-84068430D01* +X119902461Y-83982764D01* +X119817603Y-83939527D01* +X119711127Y-83938718D01* +X119647079Y-83959529D01* +X119561413Y-84022768D01* +X119432510Y-84170865D01* +X119346844Y-84234104D01* +X119282796Y-84254914D01* +X119176320Y-84254106D01* +X119091462Y-84210869D01* +X119028223Y-84125203D01* +X119007413Y-84061155D01* +X119008221Y-83954679D01* +X119116314Y-83742534D01* +X119223599Y-83636866D01* +X119332500Y-83318246D02* +X120331599Y-83560092D01* +X119781641Y-83066097D01* +X120504548Y-83220661D01* +X119721635Y-82554526D01* +X121023395Y-82202367D02* +X120763971Y-82711514D01* +X120893683Y-82456941D02* +X120002676Y-82002950D01* +X120086726Y-82152664D01* +X120128346Y-82280759D01* +X120127538Y-82387235D01* +%TO.C,J1*% +X135342380Y-77168333D02* +X136056666Y-77168333D01* +X136199523Y-77215952D01* +X136294761Y-77311190D01* +X136342380Y-77454047D01* +X136342380Y-77549285D01* +X136342380Y-76168333D02* +X136342380Y-76739761D01* +X136342380Y-76454047D02* +X135342380Y-76454047D01* +X135485238Y-76549285D01* +X135580476Y-76644523D01* +X135628095Y-76739761D01* +%TO.C,D2*% +X166901904Y-76017380D02* +X166901904Y-75017380D01* +X167140000Y-75017380D01* +X167282857Y-75065000D01* +X167378095Y-75160238D01* +X167425714Y-75255476D01* +X167473333Y-75445952D01* +X167473333Y-75588809D01* +X167425714Y-75779285D01* +X167378095Y-75874523D01* +X167282857Y-75969761D01* +X167140000Y-76017380D01* +X166901904Y-76017380D01* +X167854285Y-75112619D02* +X167901904Y-75065000D01* +X167997142Y-75017380D01* +X168235238Y-75017380D01* +X168330476Y-75065000D01* +X168378095Y-75112619D01* +X168425714Y-75207857D01* +X168425714Y-75303095D01* +X168378095Y-75445952D01* +X167806666Y-76017380D01* +X168425714Y-76017380D01* +%TO.C,D5*% +X119726981Y-133602821D02* +X119226981Y-132736795D01* +X119433177Y-132617747D01* +X119580705Y-132587558D01* +X119710802Y-132622418D01* +X119799661Y-132681087D01* +X119936138Y-132822235D01* +X120007567Y-132945952D01* +X120061565Y-133134719D01* +X120067945Y-133241007D01* +X120033086Y-133371105D01* +X119933177Y-133483773D01* +X119726981Y-133602821D01* +X120505399Y-131998700D02* +X120093006Y-132236795D01* +X120289862Y-132672998D01* +X120307292Y-132607949D01* +X120365961Y-132519091D01* +X120572157Y-132400043D01* +X120678446Y-132393663D01* +X120743494Y-132411093D01* +X120832353Y-132469762D01* +X120951400Y-132675959D01* +X120957780Y-132782247D01* +X120940350Y-132847295D01* +X120881681Y-132936154D01* +X120675485Y-133055201D01* +X120569197Y-133061581D01* +X120504148Y-133044151D01* +%TO.C,M2*% +X160002380Y-74809523D02* +X159002380Y-74809523D01* +X159716666Y-74476190D01* +X159002380Y-74142857D01* +X160002380Y-74142857D01* +X159097619Y-73714285D02* +X159050000Y-73666666D01* +X159002380Y-73571428D01* +X159002380Y-73333333D01* +X159050000Y-73238095D01* +X159097619Y-73190476D01* +X159192857Y-73142857D01* +X159288095Y-73142857D01* +X159430952Y-73190476D01* +X160002380Y-73761904D01* +X160002380Y-73142857D01* +%TO.C,BT1*% +X189920571Y-135913714D02* +X189968190Y-135770857D01* +X190015809Y-135723238D01* +X190111047Y-135675619D01* +X190253904Y-135675619D01* +X190349142Y-135723238D01* +X190396761Y-135770857D01* +X190444380Y-135866095D01* +X190444380Y-136247047D01* +X189444380Y-136247047D01* +X189444380Y-135913714D01* +X189492000Y-135818476D01* +X189539619Y-135770857D01* +X189634857Y-135723238D01* +X189730095Y-135723238D01* +X189825333Y-135770857D01* +X189872952Y-135818476D01* +X189920571Y-135913714D01* +X189920571Y-136247047D01* +X189444380Y-135389904D02* +X189444380Y-134818476D01* +X190444380Y-135104190D02* +X189444380Y-135104190D01* +X190444380Y-133961333D02* +X190444380Y-134532761D01* +X190444380Y-134247047D02* +X189444380Y-134247047D01* +X189587238Y-134342285D01* +X189682476Y-134437523D01* +X189730095Y-134532761D01* +D13* +X180678571Y-138952380D02* +X180678571Y-137047619D01* +X181630952Y-138000000D02* +X179726190Y-138000000D01* +X180478571Y-74952380D02* +X180478571Y-73047619D01* +D12* +%TO.C,J2*% +X135342380Y-135588333D02* +X136056666Y-135588333D01* +X136199523Y-135635952D01* +X136294761Y-135731190D01* +X136342380Y-135874047D01* +X136342380Y-135969285D01* +X135437619Y-135159761D02* +X135390000Y-135112142D01* +X135342380Y-135016904D01* +X135342380Y-134778809D01* +X135390000Y-134683571D01* +X135437619Y-134635952D01* +X135532857Y-134588333D01* +X135628095Y-134588333D01* +X135770952Y-134635952D01* +X136342380Y-135207380D01* +X136342380Y-134588333D01* +%TO.C,P1*% +X191477380Y-99798095D02* +X190477380Y-99798095D01* +X190477380Y-99417142D01* +X190525000Y-99321904D01* +X190572619Y-99274285D01* +X190667857Y-99226666D01* +X190810714Y-99226666D01* +X190905952Y-99274285D01* +X190953571Y-99321904D01* +X191001190Y-99417142D01* +X191001190Y-99798095D01* +X191477380Y-98274285D02* +X191477380Y-98845714D01* +X191477380Y-98560000D02* +X190477380Y-98560000D01* +X190620238Y-98655238D01* +X190715476Y-98750476D01* +X190763095Y-98845714D01* +%TO.C,J3*% +X164131666Y-101262380D02* +X164131666Y-101976666D01* +X164084047Y-102119523D01* +X163988809Y-102214761D01* +X163845952Y-102262380D01* +X163750714Y-102262380D01* +X164512619Y-101262380D02* +X165131666Y-101262380D01* +X164798333Y-101643333D01* +X164941190Y-101643333D01* +X165036428Y-101690952D01* +X165084047Y-101738571D01* +X165131666Y-101833809D01* +X165131666Y-102071904D01* +X165084047Y-102167142D01* +X165036428Y-102214761D01* +X164941190Y-102262380D01* +X164655476Y-102262380D01* +X164560238Y-102214761D01* +X164512619Y-102167142D01* +%TO.C,L2*% +X165568333Y-95702380D02* +X165092142Y-95702380D01* +X165092142Y-94702380D01* +X165854047Y-94797619D02* +X165901666Y-94750000D01* +X165996904Y-94702380D01* +X166235000Y-94702380D01* +X166330238Y-94750000D01* +X166377857Y-94797619D01* +X166425476Y-94892857D01* +X166425476Y-94988095D01* +X166377857Y-95130952D01* +X165806428Y-95702380D01* +X166425476Y-95702380D01* +%TO.C,U1*% +X112482380Y-97916904D02* +X113291904Y-97916904D01* +X113387142Y-97869285D01* +X113434761Y-97821666D01* +X113482380Y-97726428D01* +X113482380Y-97535952D01* +X113434761Y-97440714D01* +X113387142Y-97393095D01* +X113291904Y-97345476D01* +X112482380Y-97345476D01* +X113482380Y-96345476D02* +X113482380Y-96916904D01* +X113482380Y-96631190D02* +X112482380Y-96631190D01* +X112625238Y-96726428D01* +X112720476Y-96821666D01* +X112768095Y-96916904D01* +%TO.C,D4*% +X118839981Y-131509437D02* +X118339981Y-130643411D01* +X118546177Y-130524363D01* +X118693705Y-130494174D01* +X118823802Y-130529034D01* +X118912661Y-130587703D01* +X119049138Y-130728851D01* +X119120567Y-130852568D01* +X119174565Y-131041335D01* +X119180945Y-131147623D01* +X119146086Y-131277721D01* +X119046177Y-131390389D01* +X118839981Y-131509437D01* +X119743827Y-130217801D02* +X120077160Y-130795151D01* +X119347154Y-130006934D02* +X119498100Y-130744571D01* +X120034211Y-130435047D01* +%TO.C,D3*% +X117399981Y-129411821D02* +X116899981Y-128545795D01* +X117106177Y-128426747D01* +X117253705Y-128396558D01* +X117383802Y-128431418D01* +X117472661Y-128490087D01* +X117609138Y-128631235D01* +X117680567Y-128754952D01* +X117734565Y-128943719D01* +X117740945Y-129050007D01* +X117706086Y-129180105D01* +X117606177Y-129292773D01* +X117399981Y-129411821D01* +X117683528Y-128093414D02* +X118219639Y-127783890D01* +X118121440Y-128280471D01* +X118245157Y-128209043D01* +X118351446Y-128202663D01* +X118416494Y-128220093D01* +X118505353Y-128278762D01* +X118624400Y-128484959D01* +X118630780Y-128591247D01* +X118613350Y-128656295D01* +X118554681Y-128745154D01* +X118307245Y-128888011D01* +X118200957Y-128894391D01* +X118135908Y-128876961D01* +D14* +%TO.C,M1*% +X142150000Y-139000000D02* +X142150000Y-130000000D01* +X143150000Y-120000000D02* +X143150000Y-121000000D01* +X143150000Y-120000000D02* +X143150000Y-108000000D01* +X158150000Y-139000000D02* +X158150000Y-130000000D01* +X157150000Y-108000000D02* +X157150000Y-121000000D01* +X143150000Y-121000000D02* +X140150000Y-121000000D01* +X142150000Y-130000000D02* +X140150000Y-130000000D01* +X158150000Y-130000000D02* +X160150000Y-130000000D01* +X143150000Y-108000000D02* +X157150000Y-108000000D01* +X157150000Y-121000000D02* +X160150000Y-121000000D01* +X160150000Y-130000000D02* +G75* +G03* +X160150000Y-121000000I0J4500000D01* +G01* +X140150000Y-121000000D02* +G75* +G03* +X140150000Y-130000000I0J-4500000D01* +G01* +%TO.C,SW1*% +X119257304Y-77941881D02* +X118767250Y-77692187D01* +X117318516Y-77066252D02* +X116898574Y-77890433D01* +X117032750Y-82307813D02* +X116542696Y-82058119D01* +X120615240Y-78746017D02* +X118481484Y-82933748D01* +X115604701Y-80429802D02* +X115184760Y-81253983D01* +%TO.C,J1*% +X132980000Y-78010000D02* +X132980000Y-82410000D01* +X134290000Y-86510000D02* +X132980000Y-86510000D01* +X132980000Y-82410000D02* +X134290000Y-82410000D01* +X134290000Y-76710000D02* +X134290000Y-92210000D01* +X134680000Y-87000000D02* +X135680000Y-87500000D01* +X126480000Y-78010000D02* +X132980000Y-78010000D01* +X125170000Y-92210000D02* +X125170000Y-76710000D01* +X126480000Y-90910000D02* +X126480000Y-78010000D01* +X132980000Y-86510000D02* +X132980000Y-90910000D01* +X125170000Y-76710000D02* +X134290000Y-76710000D01* +X132980000Y-82410000D02* +X132980000Y-82410000D01* +X135680000Y-86500000D02* +X134680000Y-87000000D01* +X132980000Y-90910000D02* +X126480000Y-90910000D01* +X134290000Y-92210000D02* +X125170000Y-92210000D01* +X135680000Y-87500000D02* +X135680000Y-86500000D01* +%TO.C,D2*% +X165990000Y-76610000D02* +X165990000Y-82010000D01* +X169290000Y-76610000D02* +X169290000Y-82010000D01* +X169290000Y-76610000D02* +X165990000Y-76610000D01* +%TO.C,D5*% +X116620747Y-135658884D02* +X118946025Y-134316384D01* +X115660747Y-133996116D02* +X116620747Y-135658884D01* +X117986025Y-132653616D02* +X115660747Y-133996116D01* +%TO.C,M2*% +X157400000Y-92000000D02* +X157400000Y-104000000D01* +X157400000Y-92000000D02* +X157400000Y-91000000D01* +X142400000Y-82000000D02* +X140400000Y-82000000D01* +X158400000Y-73000000D02* +X158400000Y-82000000D01* +X157400000Y-91000000D02* +X160400000Y-91000000D01* +X143400000Y-104000000D02* +X143400000Y-91000000D01* +X143400000Y-91000000D02* +X140400000Y-91000000D01* +X142400000Y-73000000D02* +X142400000Y-82000000D01* +X157400000Y-104000000D02* +X143400000Y-104000000D01* +X158400000Y-82000000D02* +X160400000Y-82000000D01* +X140400000Y-82000000D02* +G75* +G03* +X140400000Y-91000000I0J-4500000D01* +G01* +X160400000Y-91000000D02* +G75* +G03* +X160400000Y-82000000I0J4500000D01* +G01* +%TO.C,BT1*% +X172700000Y-120200000D02* +X188300000Y-120200000D01* +X172700000Y-91800000D02* +X188300000Y-91800000D01* +X172700000Y-135800000D02* +X188300000Y-135800000D01* +X188300000Y-135800000D02* +X188300000Y-76200000D01* +X188300000Y-76200000D02* +X172700000Y-76200000D01* +X172700000Y-76200000D02* +X172700000Y-135800000D01* +%TO.C,J2*% +X134290000Y-129510000D02* +X132980000Y-129510000D01* +X132980000Y-125410000D02* +X134290000Y-125410000D01* +X126480000Y-133910000D02* +X126480000Y-121010000D01* +X132980000Y-133910000D02* +X126480000Y-133910000D01* +X135680000Y-129500000D02* +X134680000Y-130000000D01* +X134680000Y-130000000D02* +X135680000Y-130500000D01* +X132980000Y-125410000D02* +X132980000Y-125410000D01* +X125170000Y-119710000D02* +X134290000Y-119710000D01* +X135680000Y-130500000D02* +X135680000Y-129500000D01* +X126480000Y-121010000D02* +X132980000Y-121010000D01* +X125170000Y-135210000D02* +X125170000Y-119710000D01* +X134290000Y-135210000D02* +X125170000Y-135210000D01* +X132980000Y-129510000D02* +X132980000Y-133910000D01* +X132980000Y-121010000D02* +X132980000Y-125410000D01* +X134290000Y-119710000D02* +X134290000Y-135210000D01* +%TO.C,P1*% +X193155000Y-101430000D02* +X194155000Y-101430000D01* +X193155000Y-110620000D02* +X194155000Y-110620000D01* +X191025000Y-109000000D02* +X191025000Y-103050000D01* +X198055000Y-110620000D02* +X198055000Y-101430000D01* +X197155000Y-101430000D02* +X198055000Y-101430000D01* +X197155000Y-110620000D02* +X198055000Y-110620000D01* +%TO.C,J3*% +X166230000Y-102810000D02* +X166230000Y-102875000D01* +X166230000Y-109215000D02* +X166230000Y-109280000D01* +X162700000Y-109280000D02* +X166230000Y-109280000D01* +X161375000Y-102875000D02* +X162700000Y-102875000D01* +X162700000Y-109215000D02* +X162700000Y-109280000D01* +X162700000Y-102810000D02* +X166230000Y-102810000D01* +X162700000Y-102810000D02* +X162700000Y-102875000D01* +%TO.C,L2*% +X169005000Y-89975000D02* +X165005000Y-89975000D01* +X169005000Y-94175000D02* +X165005000Y-94175000D01* +%TO.C,U1*% +X118335000Y-118000000D02* +X139435000Y-118000000D01* +X139435000Y-118000000D02* +X139435000Y-93600000D01* +X120435000Y-115800000D02* +X118835000Y-115800000D01* +X111835000Y-110400000D02* +X118335000Y-118000000D01* +X111835000Y-101200000D02* +X111835000Y-110400000D01* +X120435000Y-117400000D02* +X120435000Y-115800000D01* +X118335000Y-93600000D02* +X111835000Y-101200000D01* +X139435000Y-93600000D02* +X118335000Y-93600000D01* +%TO.C,D4*% +X116845025Y-130748616D02* +X114519747Y-132091116D01* +X114519747Y-132091116D02* +X115479747Y-133753884D01* +X115479747Y-133753884D02* +X117805025Y-132411384D01* +%TO.C,D3*% +X115786025Y-128843616D02* +X113460747Y-130186116D01* +X114420747Y-131848884D02* +X116746025Y-130506384D01* +X113460747Y-130186116D02* +X114420747Y-131848884D01* +%TD*% +M02* diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-NPTH.drl b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-NPTH.drl new file mode 100644 index 0000000..658a0c5 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-NPTH.drl @@ -0,0 +1,13 @@ +M48 +; DRILL file {KiCad 6.0.7-f9a2dced07~116~ubuntu20.04.1} date mer. 31 août 2022 16:11:39 +; FORMAT={-:-/ absolute / inch / decimal} +; #@! TF.CreationDate,2022-08-31T16:11:39+02:00 +; #@! TF.GenerationSoftware,Kicad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1 +; #@! TF.FileFunction,NonPlated,1,2,NPTH +FMAT,2 +INCH +% +G90 +G05 +T0 +M30 diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-PTH.drl b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-PTH.drl new file mode 100644 index 0000000..f4196d4 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-PTH.drl @@ -0,0 +1,207 @@ +M48 +; DRILL file {KiCad 6.0.7-f9a2dced07~116~ubuntu20.04.1} date mer. 31 août 2022 16:11:39 +; FORMAT={-:-/ absolute / inch / decimal} +; #@! TF.CreationDate,2022-08-31T16:11:39+02:00 +; #@! TF.GenerationSoftware,Kicad,Pcbnew,6.0.7-f9a2dced07~116~ubuntu20.04.1 +; #@! TF.FileFunction,Plated,1,2,PTH +FMAT,2 +INCH +; #@! TA.AperFunction,Plated,PTH,ViaDrill +T1C0.0118 +; #@! TA.AperFunction,Plated,PTH,ViaDrill +T2C0.0157 +; #@! TA.AperFunction,Plated,PTH,ComponentDrill +T3C0.0236 +; #@! TA.AperFunction,Plated,PTH,ComponentDrill +T4C0.0276 +; #@! TA.AperFunction,Plated,PTH,ComponentDrill +T5C0.0394 +; #@! TA.AperFunction,Plated,PTH,ComponentDrill +T6C0.0748 +% +G90 +G05 +T1 +X4.4Y-4.15 +X4.44Y-4.2 +X4.45Y-3.775 +X4.475Y-4.25 +X4.5Y-4.35 +X4.525Y-4.175 +X4.55Y-4.65 +X4.6Y-4.1 +X4.6Y-4.975 +X4.65Y-3.9 +X4.675Y-4.975 +X4.7Y-3.8205 +X4.7Y-3.9 +X4.75Y-4.975 +X4.775Y-4.3 +X4.825Y-4.775 +X4.9Y-4.8 +X4.925Y-3.85 +X4.975Y-4.6435 +X5.0Y-3.925 +X5.0Y-4.125 +X5.0Y-4.3 +X5.025Y-4.4965 +X5.25Y-3.5 +X5.325Y-4.425 +X5.3535Y-4.4528 +X5.375Y-4.6435 +X5.4Y-4.26 +X5.4465Y-4.525 +X5.4465Y-4.5644 +X5.45Y-4.325 +X5.475Y-3.75 +X5.4827Y-4.2827 +X5.5Y-4.7715 +X5.52Y-3.9 +X5.56Y-3.7 +X5.575Y-4.1 +X5.6065Y-3.74 +X5.6185Y-4.75 +X5.66Y-4.62 +X5.675Y-4.45 +X5.68Y-3.9 +X5.68Y-4.1 +X5.725Y-4.0 +X5.75Y-4.05 +X5.78Y-4.1715 +X5.8Y-4.7965 +X5.86Y-4.38 +X5.8606Y-4.4396 +X5.9Y-3.95 +X5.9Y-4.48 +X5.92Y-4.55 +X5.9457Y-4.675 +X5.9601Y-4.5201 +X5.9654Y-4.2125 +X5.98Y-4.42 +X5.9841Y-4.175 +X6.0027Y-4.675 +X6.02Y-4.45 +X6.025Y-3.8 +X6.0374Y-4.1376 +X6.1Y-3.9 +X6.1Y-5.1035 +X6.125Y-4.85 +X6.15Y-4.725 +X6.1573Y-4.6573 +X6.175Y-4.3 +X6.175Y-4.35 +X6.2198Y-4.8198 +X6.225Y-4.325 +X6.275Y-4.075 +X6.275Y-4.35 +X6.3Y-4.625 +X6.4Y-4.325 +X6.425Y-4.425 +X6.46Y-3.84 +X6.55Y-4.375 +X6.55Y-4.625 +X6.575Y-4.425 +X6.575Y-5.25 +X6.58Y-4.96 +X6.6391Y-5.1209 +X6.66Y-4.34 +X6.675Y-4.675 +X6.7Y-4.15 +X6.715Y-4.635 +X6.7411Y-3.8911 +X6.75Y-3.75 +X6.75Y-4.125 +X6.76Y-4.675 +X6.76Y-4.725 +X6.85Y-3.475 +X6.85Y-3.96 +X6.875Y-4.375 +X6.9Y-3.08 +X6.95Y-3.875 +X6.95Y-4.9 +X7.02Y-4.64 +X7.04Y-4.68 +X7.0955Y-3.8 +X7.1Y-3.75 +X7.2Y-4.525 +X7.2Y-4.575 +X7.35Y-4.35 +X7.35Y-4.46 +X7.4Y-4.375 +X7.425Y-4.4713 +T2 +X4.44Y-3.9 +X4.5428Y-4.775 +X4.625Y-4.6 +X5.35Y-4.925 +X5.75Y-4.7965 +X6.475Y-3.075 +X6.7Y-3.65 +X6.725Y-3.25 +X6.76Y-4.55 +X6.975Y-4.6 +X7.075Y-4.4 +X7.225Y-4.45 +X7.65Y-4.15 +T4 +X4.7022Y-3.7323 +X4.7022Y-4.5984 +X4.7809Y-3.7323 +X4.7809Y-4.5984 +X4.8596Y-3.7323 +X4.8596Y-4.5984 +X4.9384Y-3.7323 +X4.9384Y-4.5984 +X5.0171Y-3.7323 +X5.0171Y-4.5984 +X5.0959Y-3.7323 +X5.0959Y-4.5984 +X5.1746Y-3.7323 +X5.1746Y-4.5984 +X5.2533Y-3.7323 +X5.2533Y-4.5984 +X5.3321Y-3.7323 +X5.3321Y-4.5984 +X5.4108Y-3.7323 +X5.4108Y-4.5984 +T5 +X5.0575Y-3.2252 +X5.0575Y-3.3252 +X5.0575Y-3.4252 +X5.0575Y-4.9181 +X5.0575Y-5.0181 +X5.0575Y-5.1181 +X5.1575Y-3.2252 +X5.1575Y-3.3252 +X5.1575Y-3.4252 +X5.1575Y-4.9181 +X5.1575Y-5.0181 +X5.1575Y-5.1181 +T6 +X7.1063Y-3.1555 +X7.1063Y-3.4547 +X7.1063Y-4.8917 +X7.1063Y-5.1909 +T3 +G00X7.5407Y-4.0043 +M15 +G01X7.5644Y-4.0043 +M16 +G05 +G00X7.5407Y-4.3445 +M15 +G01X7.5644Y-4.3445 +M16 +G05 +G00X7.6904Y-4.0039 +M15 +G01X7.714Y-4.0039 +M16 +G05 +G00X7.6904Y-4.3445 +M15 +G01X7.714Y-4.3445 +M16 +G05 +T0 +M30 diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-job.gbrjob b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-job.gbrjob new file mode 100644 index 0000000..6cf94a2 --- /dev/null +++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-job.gbrjob @@ -0,0 +1,147 @@ +{ + "Header": { + "GenerationSoftware": { + "Vendor": "KiCad", + "Application": "Pcbnew", + "Version": "6.0.7-f9a2dced07~116~ubuntu20.04.1" + }, + "CreationDate": "2022-08-31T16:11:48+02:00" + }, + "GeneralSpecs": { + "ProjectId": { + "Name": "dumber-v3", + "GUID": "64756d62-6572-42d7-9633-2e6b69636164", + "Revision": "1.1" + }, + "Size": { + "X": 88.5, + "Y": 86.5 + }, + "LayerNumber": 2, + "BoardThickness": 1.6, + "Finish": "None" + }, + "DesignRules": [ + { + "Layers": "Outer", + "PadToPad": 0.15, + "PadToTrack": 0.15, + "TrackToTrack": 0.15, + "MinLineWidth": 0.2, + "TrackToRegion": 0.508, + "RegionToRegion": 0.508 + } + ], + "FilesAttributes": [ + { + "Path": "dumber-v3-F_Cu.gbr", + "FileFunction": "Copper,L1,Top", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-B_Cu.gbr", + "FileFunction": "Copper,L2,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-F_Adhesive.gbr", + "FileFunction": "Glue,Top", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-B_Adhesive.gbr", + "FileFunction": "Glue,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-F_Paste.gbr", + "FileFunction": "SolderPaste,Top", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-B_Paste.gbr", + "FileFunction": "SolderPaste,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-F_Silkscreen.gbr", + "FileFunction": "Legend,Top", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-B_Silkscreen.gbr", + "FileFunction": "Legend,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-F_Mask.gbr", + "FileFunction": "SolderMask,Top", + "FilePolarity": "Negative" + }, + { + "Path": "dumber-v3-B_Mask.gbr", + "FileFunction": "SolderMask,Bot", + "FilePolarity": "Negative" + }, + { + "Path": "dumber-v3-Edge_Cuts.gbr", + "FileFunction": "Profile", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-F_Fab.gbr", + "FileFunction": "AssemblyDrawing,Top", + "FilePolarity": "Positive" + }, + { + "Path": "dumber-v3-B_Fab.gbr", + "FileFunction": "AssemblyDrawing,Bot", + "FilePolarity": "Positive" + } + ], + "MaterialStackup": [ + { + "Type": "Legend", + "Name": "Top Silk Screen" + }, + { + "Type": "SolderPaste", + "Name": "Top Solder Paste" + }, + { + "Type": "SolderMask", + "Thickness": 0.01, + "Name": "Top Solder Mask" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "F.Cu" + }, + { + "Type": "Dielectric", + "Thickness": 1.51, + "Material": "FR4", + "Name": "F.Cu/B.Cu", + "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "B.Cu" + }, + { + "Type": "SolderMask", + "Thickness": 0.01, + "Name": "Bottom Solder Mask" + }, + { + "Type": "SolderPaste", + "Name": "Bottom Solder Paste" + }, + { + "Type": "Legend", + "Name": "Bottom Silk Screen" + } + ] +} diff --git a/hardware/pcb/Dumber-v3/dumber-v3/cpu.kicad_sch b/hardware/pcb/Dumber-v3/dumber-v3/cpu.kicad_sch index 652a157..7c31009 100644 --- a/hardware/pcb/Dumber-v3/dumber-v3/cpu.kicad_sch +++ b/hardware/pcb/Dumber-v3/dumber-v3/cpu.kicad_sch @@ -737,71 +737,6 @@ ) ) ) - (symbol "Jumper:Jumper_3_Bridged12" (pin_names (offset 0) hide) (in_bom yes) (on_board yes) - (property "Reference" "JP" (id 0) (at -2.54 -2.54 0) - (effects (font (size 1.27 1.27))) - ) - (property "Value" "Jumper_3_Bridged12" (id 1) (at 0 2.794 0) - (effects (font (size 1.27 1.27))) - ) - (property "Footprint" "" (id 2) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "~" (id 3) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "ki_keywords" "Jumper SPDT" (id 4) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "ki_description" "Jumper, 3-pole, pins 1+2 closed/bridged" (id 5) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "ki_fp_filters" "Jumper* TestPoint*3Pads* TestPoint*Bridge*" (id 6) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (symbol "Jumper_3_Bridged12_0_0" - (circle (center -3.302 0) (radius 0.508) - (stroke (width 0) (type default) (color 0 0 0 0)) - (fill (type none)) - ) - (circle (center 0 0) (radius 0.508) - (stroke (width 0) (type default) (color 0 0 0 0)) - (fill (type none)) - ) - (circle (center 3.302 0) (radius 0.508) - (stroke (width 0) (type default) (color 0 0 0 0)) - (fill (type none)) - ) - ) - (symbol "Jumper_3_Bridged12_0_1" - (arc (start -0.254 0.508) (mid -1.651 0.9912) (end -3.048 0.508) - (stroke (width 0) (type default) (color 0 0 0 0)) - (fill (type none)) - ) - (polyline - (pts - (xy 0 -1.27) - (xy 0 -0.508) - ) - (stroke (width 0) (type default) (color 0 0 0 0)) - (fill (type none)) - ) - ) - (symbol "Jumper_3_Bridged12_1_1" - (pin passive line (at -6.35 0 0) (length 2.54) - (name "A" (effects (font (size 1.27 1.27)))) - (number "1" (effects (font (size 1.27 1.27)))) - ) - (pin passive line (at 0 -3.81 90) (length 2.54) - (name "C" (effects (font (size 1.27 1.27)))) - (number "2" (effects (font (size 1.27 1.27)))) - ) - (pin passive line (at 6.35 0 180) (length 2.54) - (name "B" (effects (font (size 1.27 1.27)))) - (number "3" (effects (font (size 1.27 1.27)))) - ) - ) - ) (symbol "MCU_ST_STM32L0:STM32L031C6Tx" (in_bom yes) (on_board yes) (property "Reference" "U" (id 0) (at -12.7 36.83 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -1442,10 +1377,6 @@ (stroke (width 0) (type default) (color 0 0 0 0)) (uuid 40d90da6-2b0f-4b61-a452-39aaaee37955) ) - (wire (pts (xy 93.98 50.8) (xy 93.98 53.34)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid 426ffd8f-0543-411e-9727-6263781275e0) - ) (wire (pts (xy 147.32 93.98) (xy 170.18 93.98)) (stroke (width 0) (type default) (color 0 0 0 0)) (uuid 42fd8cbf-0fe9-4e6d-8428-a36d8919f760) @@ -1719,10 +1650,6 @@ (stroke (width 0) (type default) (color 0 0 0 0)) (uuid c1c46e33-32c0-4fc1-a0b3-9216c005d19d) ) - (wire (pts (xy 106.68 53.34) (xy 109.22 53.34)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid c1cdc35c-e86c-4b62-bb8d-3dfe9782b16b) - ) (wire (pts (xy 266.7 82.55) (xy 275.59 82.55)) (stroke (width 0) (type default) (color 0 0 0 0)) (uuid c1f7c763-984e-4e36-b1ae-fa83a87a1e36) @@ -2032,7 +1959,7 @@ (effects (font (size 1.27 1.27)) (justify right bottom)) (uuid f18092e7-4590-44e1-bbc5-69dd11a9374c) ) - (label "RESET" (at 99.06 43.18 0) + (label "RESET" (at 105.41 43.18 0) (effects (font (size 1.27 1.27)) (justify left bottom)) (uuid fb6fdd3b-b29a-47d5-a1d0-5ece548815c1) ) @@ -2066,17 +1993,17 @@ (uuid b5fb48a3-6f50-4aaf-a7a9-38328e800948) ) - (symbol (lib_id "power:GND") (at 109.22 53.34 0) (unit 1) + (symbol (lib_id "power:GND") (at 100.33 49.53 0) (unit 1) (in_bom yes) (on_board yes) (fields_autoplaced) (uuid 0e54446f-aeb2-4641-9a9e-b60cb11a5233) - (property "Reference" "#PWR030" (id 0) (at 109.22 59.69 0) + (property "Reference" "#PWR030" (id 0) (at 100.33 55.88 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Value" "GND" (id 1) (at 109.22 57.7834 0)) - (property "Footprint" "" (id 2) (at 109.22 53.34 0) + (property "Value" "GND" (id 1) (at 100.33 53.9734 0)) + (property "Footprint" "" (id 2) (at 100.33 49.53 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Datasheet" "" (id 3) (at 109.22 53.34 0) + (property "Datasheet" "" (id 3) (at 100.33 49.53 0) (effects (font (size 1.27 1.27)) hide) ) (pin "1" (uuid de3d1d97-8822-41a3-92e9-9fa0f1046d38)) @@ -2314,24 +2241,6 @@ (pin "2" (uuid 335869f0-0f98-4c01-b6aa-c1702876cd96)) ) - (symbol (lib_id "Jumper:Jumper_3_Bridged12") (at 100.33 53.34 180) (unit 1) - (in_bom yes) (on_board yes) (fields_autoplaced) - (uuid 55f864fb-4849-4d8d-9e04-3291044a27a8) - (property "Reference" "JP1" (id 0) (at 100.33 56.2346 0)) - (property "Value" "Jumper_3_Bridged12" (id 1) (at 100.33 58.7715 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Footprint" "Jumper:SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm_NumberLabels" (id 2) (at 100.33 53.34 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "~" (id 3) (at 100.33 53.34 0) - (effects (font (size 1.27 1.27)) hide) - ) - (pin "1" (uuid 679254ce-c54c-4d81-b7ef-fd967a56b22f)) - (pin "2" (uuid 9fbda050-17ec-465c-9a6e-df43f77d341f)) - (pin "3" (uuid 092d651d-050f-4034-a6e9-32349e68b22a)) - ) - (symbol (lib_id "power:GND") (at 250.19 48.26 0) (unit 1) (in_bom yes) (on_board yes) (fields_autoplaced) (uuid 58bfb7a0-de14-4c9a-b46c-85ecf6fcb60e) @@ -2373,7 +2282,7 @@ (property "Reference" "R16" (id 0) (at 36.068 60.1253 0) (effects (font (size 1.27 1.27)) (justify left)) ) - (property "Value" "1.5K" (id 1) (at 36.068 62.6622 0) + (property "Value" "1K" (id 1) (at 36.068 62.6622 0) (effects (font (size 1.27 1.27)) (justify left)) ) (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 32.512 60.96 90) @@ -2411,7 +2320,7 @@ (property "Reference" "R22" (id 0) (at 47.498 60.1253 0) (effects (font (size 1.27 1.27)) (justify left)) ) - (property "Value" "1.5K" (id 1) (at 47.498 62.6622 0) + (property "Value" "1K" (id 1) (at 47.498 62.6622 0) (effects (font (size 1.27 1.27)) (justify left)) ) (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 43.942 60.96 90) @@ -2554,10 +2463,10 @@ ) (symbol (lib_id "Device:R") (at 109.22 48.26 90) (unit 1) - (in_bom yes) (on_board yes) (fields_autoplaced) + (in_bom yes) (on_board yes) (uuid 847724be-a104-4b2b-97ba-095b66aec5e9) - (property "Reference" "R26" (id 0) (at 109.22 43.5442 90)) - (property "Value" "10K" (id 1) (at 109.22 46.0811 90)) + (property "Reference" "R26" (id 0) (at 106.68 45.72 90)) + (property "Value" "10K" (id 1) (at 111.76 45.72 90)) (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 109.22 50.038 90) (effects (font (size 1.27 1.27)) hide) ) @@ -2625,7 +2534,7 @@ (property "Reference" "R23" (id 0) (at 57.658 60.1253 0) (effects (font (size 1.27 1.27)) (justify left)) ) - (property "Value" "1.5K" (id 1) (at 57.658 62.6622 0) + (property "Value" "820" (id 1) (at 57.658 62.6622 0) (effects (font (size 1.27 1.27)) (justify left)) ) (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 54.102 60.96 90) @@ -2658,7 +2567,7 @@ ) (symbol (lib_id "Insa:XBEE-3") (at 49.53 171.45 0) (unit 1) - (in_bom yes) (on_board yes) (fields_autoplaced) + (in_bom yes) (on_board yes) (uuid a2266a25-f3f8-4b9b-b976-3534cc857ce9) (property "Reference" "U1" (id 0) (at 51.5494 130.971 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -2692,22 +2601,6 @@ (pin "9" (uuid e5e29027-3740-4aab-97f4-71a560e76d6b)) ) - (symbol (lib_id "power:+2V5") (at 93.98 50.8 0) (unit 1) - (in_bom yes) (on_board yes) (fields_autoplaced) - (uuid a9030619-07d6-40a1-a218-b160d5d918d4) - (property "Reference" "#PWR029" (id 0) (at 93.98 54.61 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Value" "+2V5" (id 1) (at 93.98 47.2242 0)) - (property "Footprint" "" (id 2) (at 93.98 50.8 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "" (id 3) (at 93.98 50.8 0) - (effects (font (size 1.27 1.27)) hide) - ) - (pin "1" (uuid 3fc1f7b9-a825-439b-a9a7-1f24dc593a8f)) - ) - (symbol (lib_id "Connector_Generic:Conn_02x03_Odd_Even") (at 240.03 29.21 0) (unit 1) (in_bom yes) (on_board yes) (fields_autoplaced) (uuid ad90e2d3-97b9-46c2-8dd0-1f06ea84ef6b) diff --git a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-B_Cu.pdf b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-B_Cu.pdf new file mode 100644 index 0000000000000000000000000000000000000000..9f1e7776a44d38b06359afba515dfd70e8c00f93 GIT binary patch literal 33658 zcmbq)by!s0+Bb@bbV?2-(kLB63kcGok^<5#-6f)QO3BbUl0zdoBAr7HB_TERP(#Nz zJkL4rd(Qiw@B8PwuDSMa@3rpz+bi#NulruZqA9QNjPJP+F3ZQ@Pa(JhjJ%9aW_Gv| z5{x{mmLII$Z5Rd7N!pA&3bqdJmab@YFm<<-w={RMuw;~y!gX_ZwKR3a^`0%bR*7Y8 z9Das-a;vrah}0KUKtirLBqkubz`pdP+O5>b1S4a!vbbN$&D6VasL2zd!sf{SFc(0Wh{Gl<&GrX`1wVe4rS}{^QP^imqFa> z_(wdaQQwLz!NIkRD?r;GYnl|ug2KlKtv`8|3hhLf&jM;)ByLZdA{**-V9P9Ei2xd3 z-|uSplg{Lj5xg6nn$K)dDyFHRC|ky%Wh`)Q3IaNz*&l9Y`kG-qSmH}ie89`Qav&SJ z(iJk_c2e?)wpNt9_SM7UliY6Rk;l(nBBr}nQ(zxzr*DKVbJVC)^ci2i& zZC*hrTT1oTJqPw{Q)Bj?D+&Uns8sQblGF|L#H6rS1^daR25kNqPTPOPk~{- zcqHheS^}sM*zK>Q!Wm$fmZ2}%&A9>qPpqqUrIRTdjzuLhya1~eSBv`W5LQL&y9pa* zPtp`&k2gDVz;4SotlYMi)zmpEw2OtvtByI(O>VC$G7Put2G3kU&s^YyBV0EZKIPhP z%B}fgkMY9vD1r!I4@(Dwslh14U05Z ztxLB};bH2-$b)uB;J88ZkzeEKwh!UGbtgA^%gHX3udw<81j=ht2rJT+#%a#+x}_O7 zXxVa0W}`dzTU)L2b4rHcsepsV(SzygKE3Qs_@7fq8QWx)f%R}PR>Xu0ywqtF#(nvc z=O$0r{+^_ylE$Msva4krr64AnXhPCbm#o48TW=k4H(}xHKdnnV6DpI=-3K1ECvArr zLf<~p;R`QC5GXE{Udx*C5h!fS47q&77TghOuE}+BMPLQq?}G(Al#V%n+tGBbS~c6uNB zF?Gbb^I(X$rs&vWitffbBPIJn|1|uA$L%__H2u1j+~lUA93s9lCDXUsMlY6`c~DJ{ zQh8vCrxbk`8PdNC3pUH0<-q(U_F( zzj)NfF?%X{02Rvf_MHD-n$kyQ9&4;~4T=NB8W~hHhrQc%h*MSOZq|)?_LjOe30wio z0Kj{_^qaXX;gMc;X4_g$s1MQ*TLWx#l&2pDk+mS%eZUVMd-$}a=UoD4CI-k zU+oOIOaFzd+T2Mq>2=_n&qzYr>#zCdy8aFC9ioslwAahcVbBre6FZEdgkl$q9c2Qs z`a*)(z)h^c7tpsIT(OIBuEvjz{4fIfu2z6?+kF)CMj8)iefe*rN}%5FG#=72V6!!5 zIgGZWEOMj?c|L9TWrQ-vO7HYJ^q$xN?~{)K z6b2>?lFa0VE7M09E;m(N-sv%Btu1yXxgW&hgmy}RlZt^_iqn|$=XH%96Yo~&<)!td zWDIOC6RiS!ldMJR^vw}HGUYX%eLSuUa^KIX`6Xuz#(mc`;Fd z5P={1z;X%MFxDA4che}Zo^12JSXFZ2eHrWD`Px|e(2@6xEyl%9lklMU(}i0lfv&;S z?K}YDyuoGNVRYV0OL^{h=55!Ai43OAZXST`Sw==^C0o*IzPL084CPFT5`N&4`8#CCBmNAFU!@@4be!B+~!&J7}(2qeQ&I@2X#D;xH9+;M1rp3I|4T)NtbaBB{`!+)h7aq zDa{`y-(Bn-8|r0xlt@|yXswc*?7Vx<|H0nF}hefeYdi)ru}h4x62Vh z-KI4(R+~ZWBz^u@;E?K(nOB=5+@3wmV4vpQVlLU-x6|K4%e8IBjP_&pGbRA(IMk(X zCldP@9_%|@9rj1CNijV@9y{{S4|I!DtJzRNsMS}>_F(pp{NMu)50ro6UEMd94T)Px zBovJ0wIFmUyEtB4FLS!oJ1zAdGeQ(koeAQAd*6BDn-W>DvUMwkUDKGj4+jj04&Rig zrq!*CfUFv&!q)UtPbEUm)`74ZD0apKcdHz->^UdqK)Fuc1LSPtiK@tzSFM5#zfAiv zuDTWFE07agJ@f_l?*vi>d3P}wAB5>%{fU%rStf#nx3RB=X2jcY_pR^IgL(u&?6a4ad<@ZFyV|TjGV@N@}$N`AN&9 z#h9!mBbFF44WoaZw})t=d?IY7+YR-mkO+Fqxjy0^UE&@sfsmDHlv z3j_Aap>JL|6o~}65E$2Fc~TTLZ1Q!o)YVP;H~Z)dCPH5|&7WJoL=ch&Z>;_&^$0H3 z|cTd8jrbsV%t6K;aXz_Q(hQ~S~V4W zRi!bttl*a-6zPJBTKop$qJHuSOZYdKeX>^WO!5s*pwBQURmu{6)+kM!nc?fVpX`DL_V12kMSx8gRG8l^PpTCB72X)V444dl{+*KR=3*l^&CDQyh;N+Jpw8ZWA|9AdBNv@c1Eq!Tb z11YD3=p>=eV~N?<#&#$UdsXaVwkSUPO~-SIvAu{Xsqgx42JF}TpNZ5Vh13%<5oAEr z_{?i*XuVg8m#r=2W=*j>?Dks2$6)dDUeeKki-PeHE$dMc(?PR{x~&Ja=I|(*)4qMR z_p+ka*5(|FN`YHvhARh@wUYUX#7kxJbV?rK=#S-Hces?4;c6SV2wqchr3YNyzj@I? z-3~L***u>S8e3+==1W4DcDh{&pWurwBcJWgm<7zb&9=!>)OHcY{x$0^sHJyTDEEnI zh93n|-G=j9RiE{ZQYnC1MSo^=TnFAfsB+E8u^AN@Ing zk$x2K*$oV`MoQ&KU|$QOzTDY8xlfs8Hvs0gIkN;D{9cU;Y?YHX6S)jGYLQ!AIL&U; zGME)#rD}9p3ew0N9rk)rXZ*euDa-cUZNj)dl~W0nkeHuPD!3f_A&R#C0PpPKsyZ@A ztmqp>oD@tnd?_M%bhshN=Uui)&+V=$`id*rCwVM5ZfIO zAAA0!qUN5}6k_str%pv86RA9fp#D#lB3gl&BDXyc67%_1ffyE@tzmsEW~=^o>rHbUHcj-=V%`ZkN?ElkF6=L9bz zhUS%Z8F^yjiQ$4^uYzPvyJPUNY*4OL$rVZa;-oKww5W`X9o@>f?{P%?;#uY#Z zMy)9Z;S*w?n79kabY2OxO3&?wnw_POLb`}(Mh7;=^HL9rql^_RPw=jl!4F5GvjJyB z1mQ%&`1ib-0B7un)(?VCcUM-h6|Z_4u$McgBA7lRDKEeHFMfMCvOgjkjzL4r;DB-O z=x<}U`@qZOC*fWBuJ2n$U&L%_jzIL#(rciHBl76V1k(sA%rfF0|5I9y+?}F57p+io zj)}&at^cy@Ie^r$FzQ&--7GYzoq~B@hgeT6ImWF^E zgN#-)DPSw!Gq9ChggKHKl<`B6y~df=BI#(N+Us@NguscFBe;R(`isGb=Gdz|C;Ma# zZs}IKOAeXSjjr+f067ncktTb*dK^B>=1 z%car+=WUd6jtvVq5Bj~*|2%?+|9(c3bn!ut3C}y}_BL=!4}->>A|0zymgJ`d$qXn3 z!j|8xPi=$mWFbSdd7?hcEpdi!W=R@Ymn6xyEGijEpIJ6mXXnUGqRJWCmkf;uN z%%58yX%arn3;lWWTVyvBRJ-2Mpy_q(d?Oy)y-`4p1=de+g=4844Vzz5-{cEZu5kt* zWQa!J>?E^v*_H)#^f3cv%l(p6YkLeF0||!>?!m$)t{#v{mWWLGr(E@F9G`IwoiUm| zk^$#FXbyeqFHrjjig*=G81%CJ57fnV15>Hvw(}&h?zE_e_Zh1st02&iqNMA$CDG>U z&f`i7OYEcNRVHYA)>Ml9G@F2VfCa)~&W$2#&z`3)b(1;5ackGS*U84O*P-eH0W_Ub z;(2@mlz;%qU$tM*=;|V}0r3YUqOl6L{4&3e??0;{kRO7Qtss@nY#kJpR{afNFYO|I zzHRH{mVRKREX;q5{R)F)97oXfv3Hb7R$^AeAWaQI&WV${ups622StK*+*}`|C{1=B z2Ie?k(x7m>;H|m?lq(oyff{$80_ZQ8LH9z87kcWTPzIL?8qIO9f><4H)ra0`#_#Rw zgPYF~z_p07^CxfZWFkt}wHdLtSyJ;;k}?QymFz#C_~pD83r?EB0p zM6~gr%A1g0;`fhoRm{gNbhItxcPWnMqwaI5Yv7TpD~#spbdArv9h?+_rG=!*S+&Z= z)sM)HeHd6a zSbrPK^mE94lg6B3((eaAzhB0S<+Zv%sy(ys@C&ab)I6;yH6ywui)J1!qgyiRFvS2l zQsa@_sxoKD!qnL*?I;yo_RVS8rqc~ zW|WuNFVogYnFuS=>AQ7UKXV1dj97g9w27r{m2NWzC0le-HVrj~xon010rnI#x6N(q zAxC<8`0`MgT-q9V6zU2GuD*|7TN}FQ-V&+@4!dkU+NAP{A>KZpl#<te{wyxNG zj>mXdL?+tKnNVQDR==1mLt_ie1g!%OXJ})uK9ribzK9#`>V;$Pupc#RIP=T&AKzE0 zA!zA>h9oX(Z$I;`txhl#TU0h5io4K$g*NW~wJqh7ZZfHYv`LM;+&_?z`>vH(LPCQMC((y%!m#eF|15a!$`y{kaNz4vTMHsspx38^L_+5Yh5bhC2e2wnI zvZsex&|{Vaxy0Uxu9BMTpZ1fV{ojLX%I2x|YOJ{Wmy(=Qj3eTM7rqW_v)g9xyB0D6 zqFj}{$>qU{cKRs2NE3RegX^WIwlCD}%$HEO>I?PnZQIb}SLeP^0p@K}BEAo~9X?M6 zJi1pOJXNM4Ia0ygqP#j|ebzcb=B2{{K93m78*HlRY~~-C?~8tIAwilqmCsTynYWy+ zXk;cTDn2a78LE4ZYrJqFJJE7<7O3+Owm~YSVjA;(xM|u#BebKW%QI)jf-+L>-Iy3% zMy64h3JQZ`V^<4~GvqndHqxJyuQ@%}_m_Ugg5*;;s2WKEd2b4yu8VRi zt+Ge-aacon6=Suu9vZt?D<6N`d-o^wB3zQQdo{Y?*#mx#41+20V{e8bl89pm9bBB& zPbr^z&$M5Sv0-r3ZI8TJ1T4>8hAbS=@zY{Lbe+ZegUmPWdV_bZS>i98SK{8@=YkEn zE%U}U9O^k0)Tkq-VWT6x<=O5Gh;)Ao$I>FNHFdFtS8}J|M$(@V&*eGz>BFL>g7qRC z;}D0#%+GHaGU)PC_1V44KaFdh(5mQ)6FNw91&?J1#fcoP9_t2aT4d*SlgFpN*z2w+0XRxUpN zabgw!b{@3@y|S@!&GJp^TiwC`5SCQ`cD#8Z7iMaB>L~EgnV7`_AA3Wn?ET#S=b%ua z*?z|3!c-DK%fgqW25!AOS4MWSjNMF()XiMR1ycW^(#gJf+1PN*`oW;9XS-=uwtKW8 z8+a`URy`oekU!By-D7C$TFX>ZiajY|6X8e*a!A*t0^eH`vd3iFpr`p>r(F z9R7S`dj~jwlE2$G3KYu3bIZ6&`IP~(?QTie@A;kK6Min=fkn#9u^IiW z!+>g?PgtYF8PX<3lO_C~2Ps>f-K$>^%KF75j4AK$Y4*=*hf!1)JwmiGGE?qUxuc&x zUemLq*8m&OV4*2R02{Qha@Y)1MPUxFGB&?4Rl~j!H()Nn*UB+|@^UVe^~&$hr4h&b z)^YcNl6?K1rUIYvI+f0klWI|8F621<#Lu=^^6b*SnU{}<>S+j4mjOWwhcF(C(kG|%{n@|?WU$ychFc~;gCI*uZdR$uuYJ3i!BRQ24gJE|#(3AZF!bo6;b zffIK9;-9$I_eIox)r0jrv;4?P2;Pl3BK75lXykp%@I*V7ueB<*RjK`=)pPw8l?(&5 zp`~n{ZO@OM>k&0y6Y0jOP@BoLc1F}k6#Ab2I!Py8YI|k3z94UaxOwT@D;Z0J>GgtN z8Rp~e#c1&{WfLpUiuRkEMy^XGa-^VAWK{6fO9L&nZrVWa*)y^zS zh=;Z@?_Yja6FJ!e1?(V%7^)DITJLo$yEa85u`I(WQKYYDS@))`?EyPoLL4*Y_P*J7 zWYG0RbIG09C7;tDta5LC>7YG+Ke?&wk;;# zACCR@0oY{x5iXKlG&-*K!9_NPhu?lO6Tvl zI7fc`19gz>{y^59v<{WQ#y*EML~k@Gb&K;QIz);n+x|U&0vj*J9{g3T>MQE>-S>4D zfYJdBiks=~!s&@FKrpH&-lr&{_D=I)w4?WphGxywyH3~C5n^Y;JoI*{O~Q(Xal|`4 z7N*@SKFp}}UDb@2x=joVyEWKSf2@DRWX>)FVZyqbPXe7JAudmq6Ymig>BjR9$c(id zO$WBNVO}+wy&(Tl@}l6!;S0e=G1<<>Ps>0@KzSG!pL$INTy)z{NRb)i%cI>>nRfU4 zY&Ce?Ln1kjH?-J%AaZBkp`ZO_X!CqzKUa{Q_$os|JlclsdTrEMA7qhn0N^T z$)8+cJ}DG00D%06k~<8&^nHe3LF#Kx?SSP?=>w@PJEu=>?&wxDA8r1`@gz_>v$Bag zjfJ0O;9tmWq0M{hS0FF?If$1WY0%ED0D0vtEdCe$iw@GuM+8ngLdSraxD92QQ|>1I zk${*Ae0K!%07h+;wk3eHB-LhAn4~aBK9f&0wtKT+1W#LFKhNWdG7(WUbb;1kEvMPY z2q?HNr~urNtf?S(*DddO=e6J)yEE*e-4rslIcd~3T)&5@z!C4sR}$Uv0!5=!>FE7S zx&y!`s_x&HLn+uAnS5v2XZM_zN*?OmZ(5nl)x0yq=7D=76Z30?F7v^AqD?CEN}KAQ zV12J<@$ErGxh2MI*LQwG>`8mQ_WD0KxA-odOQJO3L|Kzpcin-PwVwUw5(OmT!j!yT z((K(J3Qx+)bGF%1!VCM6)$N=SVBFES5kUy{%072aL8(4Ez;--{_}oR58JeIcME)n0 ziC~dVam7u01GAV?G|iFGcEQI1D#d4cwtdbJCM&NYlW`14=+K7I0BcbaUspELSl9{? zpbRU?%hj^&P4<*~Hc_Pfp%0E}3@RPNe@V;H{Y&%lZ_7+b98=x40SroD!v^$EkLC*! z7v_msz=kSc=Nw#JDVzFiu6!&seyvJqCmPtqYYjiDUbfTD@9nSNq*DvLH(=fiYPx{S z#;bZg8~U@VB;rG+`2>>58MiseWUFJZH^j7kO}!rt@YUc@c-8t7BZZ)FH+}hR`^$Ff zw8&7C&7<0@UNJmAyGCjHE*&%RDyKp?+2zTEyBV}X1X$(tj3q9>o~1PU3|^~#-%kTY{mDhAuK9qI)m%&s_ z$oDr^C)-$1;_{>U{g2EkejH6ij}|h z?4@1wPSqPQi-pWKutD2VlJwzh)Z0Gl)OlgrN(#K{Zb{;L8K~(Vt%tIPINv{WVNP!K z%RHk6?GFcMpX<)TffmhGBM)duZQ{Bwi3n8f24D{ZYs zn<9}t5s-fDg+hpvL`TlFxIvW&&U>QFpIJH)l9J3}3$G(dv>|3P1M*4%r3NsKchZ{y zvwOL?msv#t23D6&vq;Mm61B_j!N3CB+q9V}!Cmv1BO7T4?YNW4qVt*7#+krcD9=tn zujwU4+An$x1H8*ede3(hmyAqJLjFUWC$;BGCMEx>@e>LQIq@Up*rlZd%?62e*2SR! zn_-zrCzI+mCy3#Ty#piaM~*Bxq!svYO1UuW9Bh7x%K`3OOPdAcIA9<1H3zgNM|Pgp zq>QW;ID<@3%`EOf-4q?qjn=FM_-?SdOOuuFhwB+@`7s(H6_ua!J_LU4mtx~u>go$% zuxd#UMa#mu`aJme;K{0cV=zzF@s1Bsga<#PcxKgF>f|J}r=uo3llFK)G(28gJ{S~1 z?ntJB+WUDj?lN*S%zSfX#GrnKXqKX5mvmM5{pV~V00cK}{ZJ`6ige{1SBjY?Y6V3s z=+pa!eaa=G*^v7+LYWyVRYr5MAFVg;*E9M^O_`UsRR*o470=dPuJJF0xGD`ML#|d@ z5di}e{(PnuLTX6*Lt838kH+F+3Cxw6s?%A-SbT?HXA5FT5?uJ&?x}td|B#!1)l|UH zg;ev`&0NIO)sNtb&v;O+p{kW_Eci+YgwmUe3;I?NcZE?~nS{WO)vQ+i&E_9G1gx#! zF5&dCiaFs}NiRv~k>SqY@H{OH^&hHa|r|$}h(Su4vl#E*6s>6jVvHtJuYnjoNMU1Svl+*)_7P zXqjwfaG%q^%IsuzBcC|0&D8y^9{?K623aqCJB_b?lsl#Q(NRvh#g98Rt>;AL%Kif^ zB4`LEdH`uW#_So)i2f-iWFdgXc6=r)&8x_D9QsY-!V=#?X}&Fa)Wb@9*{$};ds2B5 z57GbwmW$(mYPraJ1DWi$L&SifR_E(gtKUX!aGNKT!1D&t!-pnEYL~I|O$(dbbRy8Q z_Jm92u_l~GJaF%vZOm|1fSc3TIj97f?K(zT($@Wt%uyoZROb+$9RLZruy!BI{LGqg ze4J`)#C+|or_Qw1`fL9=;f$Q^-GEl&c=BRMJ_;VeF6nQ2WuzqG2Z`pv(T_VknQ|OC z*gqJp`9ab1x`RunM@xeJ<>2?UA7f2Vcy6d;AnJ+itpKrsaiY@g;bd2DostYcAtaq5 za{;-QW^1R?E~%35$uIPYkqt39N06T%;egwc^O>-$@457^qsUPga%^Q1j!BiLlNC>5 zd>BW{J)cQlwXNlr-={I`U-~{-WG}U@kB5meZ1n=f#A|nc1VxaRlPUS0-I?y+vd4TN zFwIkZ(UK2!*;9LnKLLYPCjzlEK1BjLFcJw>+;3@COLlN99~5kZc(f={eFlUB1#6#{eJHb)uR|pa>kbhZ+NQS zG|S9gJawI3=jaFwHkk1m;lHHx?U4$<>m=I%YUj!u!dLp)?0N=}&8lmfpti)~$%V*D z2PbuJYbRa#pCY{Z?tqt{wB@5f5$xq;9&O2ef9B$}F9HjU1A@l*7b}lrolMaahNiG} zDEPs`=}+91d+lT0cxapI0I`uI=IH;ZR5yT>`^${)X|Kk_M%T}h z0I|31U3^c3+yF}30Q)hySVihDD>enf6<9RFCs<~}QWUC=4|e%(R%xGY(!pM|jodP` z!S>YLh{5}>Qp!ZIwV}@?O$-O}cU$Qe3|@M&8#Dt6#AS_r+iG+?gEq?lgo=#^xJ91i zIZ0;gMX{)4$r><+HJO*8YBdPUTaW#%V_tog`~CfLowzSG3sT-_APa=!Yz4Z#d*-uw zJ_st)FyC{S7vtU@|JGhYg1)YS07lu}s?)0*7w*h(y=-AZI9LsLd%Q>=4jvNL$>%$@ z01RrpcqpJ(^tk4o6}5ordS>pIM*ziqK@LV!P;iPq+7BWghqSi*7(k`*1s?1w^ZJL5U1rwIShQtsr+xwLB8_fiG$zCBLjwi>^x+ zaLaCZuzz<9n>bOgxrC^_^Uk39N#|t-bmTs^Zk6m>&m-`+s2ZY2tz`S^$L4M! z!-iKTLzt5hq9eF1|8amaaloX~v2F6kxPa@1WFZw3>hJJdL*6z%TSayNml_+K7A(~a zerKYxt+UZ4TKpbfD)9>k=jc;2>zYCOaB@RH9vD98BfGZRIb)Wr6aX-odWI-@`3!P} z{{#~W_j+Wdk$4rF;UVCDs9m?~K(2mdd`@H4T#=rO-iZJdWT;~j3?lA7BjfO8v$<*7 zzb+#0pLQdwAh-JCs;;@u*-AM~I-u+h!Kq33`n`qeCO8lyV?Lk zQq!|v8QPv4`xMHgc)-i?-U<|4qK|#J&IFA9q#d0Eig;K~#^)<4y5hEcr4&RiJLeiu zzd6b9rBWbTt*K88vHF=iW3;kpKHo}-T#yy~cxJwDE;m`gj7v|8vN$1cg3xZkk2T%7 z^TJ=P)bZd$LCQq>SJ2fj(Kw5vP*v)$D0nS=T1bGMd+MnO`A>0Is(Xc0EJ9>Bvz|7^ zL9{Rv9)BoDh?d`6<1>OVu~>epZT}ZiBmT-gZTDaLXOb~sgNcTCUKJ;Vv`82GNPLwZ zbASl_t|9LZSEP=Ilk(yu1>3%){$`nUuSJ0H2``7dEhzZ2KDN%j`pA{XpG*C~*lI&t zj;|(b(ko>|?0x(RmNz#qDF=F8x6Zn?13h<-Qk2bwiR(Pv=+RD&EMyr=<{#eJHI2}{ zbaSAvy5ypsihZi?5u9|J#r-yv`A(xO>ZhBhcTfnBzCIe#=Z6}LNr`9b&>N-Adq%IT zSxN59bq4m3w1Q)iI~bBH7+m9iZXYKNVIpunfoSv7{qK8=&c8Q1Fu@6m7 zgj;8K`O_dZbpwcP;HX2h6P-yGz;3E97a;~be#aJ;wY@sxmI?5!NR)$lxNi9TeY-0L zoG@k!oAq%0ZuFm^Rh_U7&2gfL&ir?RMs-5Te__89LUWI5ApP3 zwO|iQoV2WQ<{ZY)3r?ph6ZPbh9d$j{tDxUACxy6YbT+Ah$64CZ@xH38eDD1`*`X$kcolJE?<{@8#9< zW02}R{FI!GF;dGfdT`AR)}G&GN7T+u_Lof112b7NOt9GmL=1I`KR1W;XWb5PNc4(` zznJ!NuMjcB#{@B3jc?CbG0VmNuOC(t_B|<+#@O^;wpP^!* z$*(8jw#bSX-7T5HcClm3=CkJ6wZru`aFM>J^{0?GaYO61l;EWk{`RwV;uVdmmT%KyVhUd(qL_;N{b=x;EcGEDSd(a^R7yXWY5;I9gYMdUY)P zIOHln5b-Z2d8bf`>I@sXKG9GwTBj*^eoQD?zDG0Zqq|d|X->P3#A((!tbg4%Ub|iG zFJSXqr z@TQ9b9T#iQ-tRfv&ATbZj(04)SSj#j@7m719t>;-tvwgu+aGp=pM7W0W_d61%-1a{ zXVUdKrZvH2^E*9_f2{(nP|dkVzZ`h3eH1=2QrIJwPj(u#)v8~26SfG(uQAB6^!zhC;t zyJ%?R{z9QERX5WdTPDEbSYA~@?_HkV+pvE{I`8+?%jnJUu)y0B+vH1xg z@)6!4nZYv5w@3S(=QYXM$)-Op#~wNEh&vI)jTn#?1kYR<#L!QU$Wl-n^;XqS9#TyN$~7gjqTFI$Heo79|5d;?hdoo-sh;n7aVFPTZElh zL@(SFGud>f*D;v32DA3K>hHS6Cx*P!xh$}t?r_!bD=(;-djFhjO>n@nPuN zvop|N3zI=l;<>}p&646f)U;GnI@A)>(HCI5>yL;x4CuS#VWNS(s%$z@w;w1qfv~ym zh0(~?M9rPtJBQH|HCS)%X=fHmwJMqGifu6&OF89?>mSsKTIr;~% zmBW7rEeN*<)L(HKvKq~pjwPdy@BA;|5?2kh4C^yl&y=HJ(8c|Fj_6-bgm6op z|1U7n_dn!{itBn5;clsAe5zu?NSiHyM)FZ*seI-`o=*i{_Mo zad8gI2ym`2awf{YDbmm5p9>GJ8Ci9{mbEnFh8WZ!D}i=u(JOE5e+0Jwo8M$#5J~6{ z?Yp)pWGtWilT$v&R9HTjTa3nv@;SEx4{;91dG(t557q$xbBl7EXl|-U}IOmduBtt7$q+wy7cc zhmaqwK3vEk+;mRUxAkV#@8w+xH&}A}7X}k&b(DkU^;~Z)# zxl4c>T@%dZY+2C00XeD%-4;O|LM~`eSV|HDBF1*ak58R02HGB2)*sO}@jJCx>ep9A<%=wYKl?!hRTj;d85|-~}LK0W3 zW+F2j`P5VOoe~YWUhIziKC<;IchE&2@=6d0dqO7K@Tk1qN@&ux(nk&T+?j%m3H7!C0@SpYTr5EaJ@^6$y7M$zPfsOQrX(7!gxO80Qax%JWFviTHgIX!SO$e6E|GC$_e#V*yeZpR?1jK zLAOTUW%u#&QuG0k?uS&x>ZQmkQ|n0z)#BWtcuk@s{oEdK45K${iyzlDwUox(_BzD2KC?x`&TU6n;0fUN_jxL`mqV zJEvhKCUzy}bMeP5e5s685_YzjI%1SsI!=Dv;$7TU{mBc`2zkAhj=3FRi3R!9mrf{K zE-(=LwY7I|s+#$?ebVds;gW^aB?-))mawFkkA_0;m(gl3XPTXFf7wkvJFWJD1F!rz z&|A@Yy@$Wa`#cOcf`d$2WyD0e$c7_=qJ4YBg&=iMvfJd`sTBr0x3fg;tKF%ei-Pxq z3|Mad>AD+|4~9o1`LgNV_?ljBW`cZiMZ1~&o})6H<>AY*HJw~ujGo;6J}Y$tT3$3; zX{(>hx>l1uzt)TA)c8z4`A#8}J}UuE%jFU&#`0S$G7-KyZR=2oY7wp@%-Aei3wB#P zzT19sC@2ldf2xn5xHj~@@kNLHsmn57qu9Ubdt+-~`}|OR1M`ooXnq}h)|-6#daHtG zNcu%FaO2TPhyw-*nE08w%*`qL7m)HX-`D!V2h#(CJ6I#Qf&9^5R{ZQfc&Ih`Z z4%FOtD%S z$SQ^^XYHx!rj~B_8jWG9y@Qdl`L=6J`G8RU^Sk68IP~^|pXUHa&0M?_qUkbJiOrt? zJ|Cp2-cD&gA27Ho=>HZzPm~uf+8L`(i-gZ^ti~!ubfrj`}UrB>HvJ% z6{!bZ9<@it(~ zIytr}!9RQy37K=q^9!t=yx9JUyYS_=@l6=d0-f zjel=O4JZ}bdf>tgFK$=9e{u0&1OP`XYkTCY2o7;*r; z5CI;3$>9_8&0k`9zyWzXa-4#4i1+E?fB%3RQ=yNak(3+r{TI?D$_~6m*!uH|^9kRW z^DUwEQV1V1jwYwRL5$7Y{*gT8Z`ayAfueaW4dFw%#i0K&rh47-SHhINsu6_G z<2oNrF$9Kh(|$KzltEoQESVC~Y;6nPLJ_=yIOX^TU{2m;9TlT4;AK+{>uv$|QvU^3 zt!+ZvsB(RX)6fOmQE`o;qw90$R}1->9-i6K6OyLe#N%RNBJNYu1N`(d19+xSLQ*+P^%_ z8oi6yWKMMd+->CPbQvIiQv{i^2+sTXdXuz218d9{9 zs4$M~68K{;%s67u@VSzDJLgFb3ByzTd!x2g?IpR7VEDG)NFZr$;w+VDYvk9O-v@6` z0LPTmsR6!cz2vhO;;(JCk*c}n*=e!}O=L1h5@3C~AlhoXKxh4^z;gYnz-th1wqN}9 zhCf#e|CeE}pIonP2CR!l&egpwaanqv^ja5b+6j>#ioa%WH7^=LpF~OeWQmJKk#b7v zt^Yxl(e7LzxM^+rX_${FN7uW|i9!FY+To1s<9MGJB&92>UPYSk*98%1U_?p`q6?B# z{ptwKRZeTRmdSDa<;eQd#8{kXx$fu*8h)YS-G9MdVw4Wr!ke|lmf?mLp9m*L94-KXOhvl9E+{T&fO${L5FMS_PBf&CzX zZqc`H-QV5>WRYFJQ9RuMvk@kfEM}p@%}V~UIuBIuv%g?-7A*ZaEAj84SF*oCPTWzN zw3ltjbKmhRb#d5eLFt;;R#f+fOKpI-u0D2{hll5oeR)eGrum3gM;mg^rGK~?S*WZY zwm^DH@NxLCpNe!+M1zw0Tr1Da;ky`@LR_r@U)yKvIx~D+Bpo&hDCs@=g!)(ghq3!Z zD;Lx!_KR*_(_xuwz0Abg`&6jW%ZLDzv{J&IQ;>@!uqtc%)Z_UF0EnS4#;)E=m@Q1o zHYT35^P@oo*)uXFZ)+Ro`>;`Vf}r;HeQfPe>By;I~0gtEfK4C1u{+<84pw*PnNJIUQF z+xaNc6bL<5>KhiFZFURM5}{Am!f8EB0CI zok@kS{^v?W09Io7V4*hqI?T8&6H!uZvu-V@bAkhd8F|@^kFiE)0$+G7tfto=D45?)!`FF9+bX zJ!Rqt`lKxV0bNBtfdj3|W|& zj|9YNQ>}PUx1#!j@++mJp2h+{u+@3~a`g1;b)yxLO{~DG{fTM8cfS27ZBT_+XMsk@ zSZ_Rf#Nw#s^>wrwK5?4q%PT*^KOT?AscnBdaNM{KwzmkkxqT=iD$8fM!%|WHlKGI< zh_dLuEkhyw(n0<#vv+J@P#leBzz?DtT$O;VabFUpyG&!sr1nWlqkM}K5;AczZ$JMz zO=tqwTe3w2Qy&;J{jI_K%BI+WYwN1YNA{M5n20SA;VF&jmF_9W?+s z1y`9B*vtfG3^7q5hcgk-bq-lB>Q|fPi!`btN$ZWIXw*kcI!wEny>!zWusYnh zG47!fBG4Zj@*M6IKhVMt4p1X|sRBvhQ^Vr--fu{IvyNzDW;k|7_9iJhN`%BhT{rw< z7w*+8g)tDh55{IDeH9qcW)N@*FjvRiZojVX<|2H>Aj``a$K*GErVTTR`n`7jNf4WkR+W*bz z8QJ~q%<95){U_*aNDW`bzQpIJK5Sw)E$?#z-$yt^zTwdf9_Ne+azE7nsVu>Cd$f@= zS7MWMDAOgYgN0T8;S2WaJQH9t^E+WIFnuHb_Y@{I44}48*RG<+Yb>{Y9k@@oJ>*9r zXD)H~!2zvwN5Ks)J7B#R#V4a!Id$KZHwXA75C9c^zxU?5P+v9D*e`nRjB8~WeeMKMQo=^swdi1Ke&S;uYq%G~(3Yeuwx{a+lM zX>5A~8`-dm-*HAu|B>(3-kG^VjZ&?Xvy2a>|E=^cLCP1J$nC>SGhra(nlYE=_N@# zFq>rB{U1Gcf4Lwai{M0w2dy=VfWBL<<$v-n)BGdHzcT)p_pkh0IB}rE7S`9c>%*Rj zX4HrE&w?|7pt^($fkEn(!6_NS!TeN$l2(rIYhz7P8Lyypa?N|SwV;HjE>|*Fx%%1s zNcV0-V|-m`<&;?So({-GUe5UUetCNE>i%~#blWy%Svs${ihD|Ux7OCwwmynB54izh z275xE#R?*Md-*fWDz_10SiHMmGN$VreI06p1(CGUXeXJ z{m6iOT&KyuFnFfwp}&3Bpj-M<8w+Z7HE{9c2GJ9ZUv$qt;#d;)T-%D)R^Mv8{y}?> zqwwhBDH;)yPYcPsiGHVjF>Y|bcZ1RPoG4}qC|Q}{wm2`|Jab!H!-2BA zbVVfQs$#j`(n3xI>Y3hAwO`EqLIEjHk%1OyoD9&v(JDx@DyR&|g^u6h@nI=GZ*)E1 z)oml~K;qdSzzxE|o9zD8vXbf9>PQO2Lv9MZI&Fec^e;q3mD17Qec)^IqUK|5fR5UKU z9~t?bp9BZpdvz@IHm(~n&YP{F${S=HT1Fz4Ns%Yg1MXn&P!7 zrW3)EJO@m%|;}bLrXBiw@E3gYk5&-HN>e$7zsYC6*+9 z5+{p9*Z;-3P1Ap$0R6u_v6krOc=)X@IVCn{G{U|yVJC(r^4kI zS<|q#ts})0SOqOA(fxi@NRuII%e~|p?2%w!Lb9lR?N5V*6wy1_;yoL)>`|#Csj~~< zCu-Seqm+G6LH@oDw0QGjph4wS{o9rby#qQJ!}pTioX~wx&S+c<{;tQ}>}Rdo3^v&? zz)lr_B?PR9#emy`r74?PqJ66f&SGa>Z`?qkCzWn=A9A{Bi?%`T3DoTF78IQmDOScm z_uO@x+qv;i@|kbQV|pi@3ZMx#{xjH(0*C~mILm8xx&dx*Qy`Qt&2@0ZH^H<38&yv`p zeHS!>$!gyVKl;=cNV6H^I=vvR&LDh|utx{7a;lOL`7XR~G~ z6r-f=@#d4B(D6%nB7EY7lx0z%cm!Z~>inW=FxD^H@k8>tLy#{0BI0Bj6z!Nj9P74; zSVwn56i`RE?bj-wnPT`>6@zULcbb7TqZipN$O34YudFXDWc<*u0GgDy*-&O2D!iE~`w7}-M1FRdqetwJb(hdgkL9D`+=TM% za6r~Fox1Ok!R$^!LUTSV!!lh3hG}-Ewi33M-NyjDDiqhMF-g>=_U9xh>PxNAmr=)r z07ii+%OTMp$esiO-yv=056PmAyV^y$44~PKMUk`6=A(;<<*X7L4F>J4oab@w>DiBX zKND(K*q_{VNLF3ny)%g9wY1t*altagY-u~k#j5q`?6V)3AD+;j%Up`vL}>s~zbIRE z!nm7#68imE{l>()A8rUnzqUF1#JEN88GUVxqcZAi;;yK(4we=^@|zICbsZBg>);Y~ zOeP?!&z4bmt4meYxwYDXgne`6PI1?oj}%j#)OUtB_anfu zX79Y?j#@5ivmNt$?Tt2(Pk$IMZbW1aruKmHL2i5rV1`KcrcbBx(P^>L%gT;YiiRuH zYNjg>2Cmt#FI)v`wM$W7YaZA)Y`K4gmm}bDJtpIA*`A|kkDkSQ|HrmLP8*|vGL;QU zpi_1C)=y+lyL?No)=nI|W(a$+=iU^_wiJAO?rJ(uu}wlfC>&(Cmz`(UKC-UtSW2g6 zXad)j&>h6lEOqv>hXhDEh%HGwmNJ)@C+{LkbfkdAFb`X!x}=FIz-F;uQ47W&OtR7iZQEqM~g(`)KV_UuA(*T3AZ@ z6)KZzo;tvlPaZ6IWX2bY+m-c)Bv0BTq)ghab~`~PyFHF^ebE;hb6(hYGphwIO>W;? zb|p_Im;=AZ_)oEFi2i!z{oQ$&gk~SN1=U5|bW*e%aUsRwoqAP2<%UW_Xjf!OKjY8W zWN?9wD-OY#%Kpn9skz*~LoD7y`dVS)y2kRYkYSFyn)6!~@!$UsBnQ0ddS6fCVx|_tCU)0fsnx>0%;eh-6U& z+ePF;#4WkZ9e9#`K4dPk(IST(rZLUuWSkn5S0TLJP@$wrUppQ=f^g9?Jrx*(1;zfZ z3P-ubW{~;d6a^Ii;@+x*@=A&kBc!Fdv7&CiVe4wHxSdJv!*cfML^zq!7>rB>@fT9f zf`*UWf`(&VfpflfRnaGSc&{O-`nliERMzx+_mOqajY5VOESWN67;4!ozO9>5g8tFNMEQxSqEE~1M|Pmo>o z{YF3h;wzX*14q@CcwEY1xX3T^L9SVbv$9?9Pt~lc+k+C?WQK$?eP1KD@9x^(4xU_J zEFJ6CD~(kwjRmfix(sIJk}ZaT0T7H&Eyf3eId(YM8C$nJiSj+o@p!GQc$@={+0Gxl zPo6of;vYkd5=a;qQ4)uJ%75WIq>S8@R;0_7m0Z7Nx~~|sZT`E$!j^OzY0r7)?0jA~ zL~TDtHR&SKD;&$0J<7)tyNyidJPQugaD1D4^bb1h;R8dZM0uAz z=o)0`Jx31J4X4c-M?Bj2$b7vXxn6p#&T+NxU*t&EKAC^0Z3Rd=H0_2IP6m0A(@Q? zPZM1Pi-zvdZqBTRLzeTQ@Fccb$dNL`CRB3K4y_>dsZAKs)QdVbI@rUipZc8BZesT@ ziu^gNv!ww}ZqeI_7@8>ANO`$IcFMXkdUrY5k%2ufmUan;jK=4J7X)0r32mh1Kq$? zFFm$WkiqPgWD6od91+lr2nc|j96RgbKM0o2-CKpNpU+mESF9i1%4QhvrR@q{!T z6=aZz6Jz8rfTf=V2oH*aGc&^v%18gGBY`$owkMnCtaiEb2@>TsZt5*K7aR@Vid0T; z_ALwKyZ@cBR9=jT$F7W7Vv8a_MfSQ~_0EEDX$+}DkEP&k+w1$d(5l}i`8;&MKVv*} z8a^x<>uj}UmR_?)mTWY{Sl-uYWI&cYw5-c4O{*2t!|5B;*%84yb~muCUQ9ZWtvGwa z1necQQ}d+c+sftlFK^$r|87i}Wyy)Vn*;hIO2t=#sRZL2p7=M_&@>z7KVAGrFlvJm zahQP$|A!}PFo{H;7>VRK-152of`jyoT>y?bQPcR%-&5|fmF^mq?l8p$Wa;!?>GWvn z^kV6B2jH}}7TAuq|8T9xpV9gYKhZQpI;|RwhYdQdW|*x6_Ewk1!^wb(K+)yu2c>gD z1qY`$cI8{m_l8qB*MO1q;K+o7RmBqoHz)G zOlyvr+w+YX*;qXBjoID5=oZsBr6zkhn^rq0R%tRaIiLy`5uco-67euOQqJwhT10a) ze|r%+A_{h@t<~>C_49MMZly_XQ*2XF2i%t8IGtXK?iL-M@Lmf|IDCZ*u2q@y4`J?i z>`#95{LZS5WbE|lpqV(+=9FB{pS?1Wv-_v;Of`=5JB3pH1m}PiQ^3??toLkeW-!-J zLu({-BzB{i{^KJ%>xL1MVuL=GnrM}wetpA8EsxAEH-~<-N96x#>26;FZxnsT$(70= zI>rfjdy}CYDwo&$d?q~0Si1KHpM@jS!weI%mp>ML>Ui_SZg|V4 zA#2h}j{)xlq*G`=mzcgVQnXHGtuYt;)#(0u&qDl1=9z+No2QsC)@8)UfRMat=5n)Q zpBOIvBtSdxg_5IC;Y3kI=Rk@D1T-C((#!sugiiDrK?d7RAmQ~=Dh!U8l|ZQ3S0LyU zGj_WtwCjt-5GG8;7yCvBd)8j~dq{RXP+3EHpe3a6s;WF+^x#9jB&GsJmEITHRZPUM z@G7pmSbcx0nCMav-F~hDy>+&65wLx2%=nZD*Z}db6963oAp2d>G#6z5=gICp51YOH zi->B+g1CtNK-j#g9RbV z=!ymqfCp7iKY-hVTUR$NB{dN7<0tR+2NS%ivzRw6Bs376NO5~bL!^)r>g>ic=v?N& zBPjH6M?9N(lMraGT2w74WqdbiEtQo_jA9m`&JWz?Hq>AG{oDbEh zeI6U1$){JH{l6i%DS-MrdnIm&>-taMp<;0CMNM3QuwrKLSxWEV&fOSMB5F`p?Kn{5 zt49Tu?p4A5e4>?hW(`w5d?3(R+Pzv~n%{(>o*DD-EOIPWKwf&_q3qdwG4Z0{6WSR_ z>tsawkoT&j@zC{CyJ7g6ZI0bpLO+w|Ka0pVv<9dnt29h5LTD{i`OXF3r)8%yyFQZRC7qTG^SxAIrDQTI}{ zC|S&ms0{;^=4rJN5@^Ap(5?CL{(1$z^!z$eEB|L7Pm)WM8$&Z-pa_v=X(pP7c2=Qp z#cQM^g9fdJB*F5(((jdK4PIn#4WhbZ?&MdOy3>jYuIOVXsDi#RRv-z$*Utt?=UBs6zbX7->Z4>z5 z-La*WlCZ|S@iQF5f8LU89laH&ODcj34+BY2qdVFIf7%hHbY#zQ@p1iniRWY}a} zio=t$HdEsyKyTw2oqhNLDUv+%W}Jl~Lx3%PxxS((#dyC-N8Rs6!=0C-jz6No81obK}fLA2#BOo75 zn{-DU;VOQchRT)y9(mNHJKisy1gWY*wG1=;=1ic{W1iP3FnRy<$fyzU zT?#MhW;FuGB2R>^{V^A#hqJIJ?+dD@>@o~UJcPjyS6pqB`*-?3DgoWs4^G&H{*T3& zSM?)6%!t&6?s{G}RP?ZZBqTEx<|xIN4R^DVWd3kFei4ZAwR-JjyW)Yc zz1hpRcd`Hs{P&L~|Ln}SR>sk&w6s3)CT)Rj)6Ti{(BV*vynV`abZ;r1M&(kU`MbZ7 zB1FfZQK8$o=viA=A2T}IB;h4yQofl4gGfB57a?_Rq~_O9bX3R5%9<4++wc@{XPf`C zR}=yE)klvWH4Ud7;iJMZ=gu`*JxBf>eoWbmiFW`U%imY}jmo!3 z^w~@6RIes(YF8lP|mqolkdw<|o zz5il2Zx>E49EPl3gDUn27xDZ17pCs0EvFJYqinl`5%52ou3*td)fzNky&~^5nj$#c z;+GdUCii>RSF_BnKowv56SfCc+we8t9I{yKaLbawHK)#^B>Jbc2K(;Twy0-~!+S^l zGQ`UP42~y`5U~DXfuMn-&Qx%RcN6 zT|NVIp-#=ra9YT(!5hkH74#3bT00H$f1FTbpZQoXSf~4rXSR#f)*X&=?s?2ZY+f90 zt-3_RKZQG8n6mD|bv_HI?DNuHWS-cgdLwp5Gv|J^7TWl)mF5O;fGi2$UL^dWx-jrA z4rXxo(KZlyxz1}6x&%8G*O!sQOSq70Un>YZ^R*8!OuEQPa1Mp9-ZJSy`Z%^dXIz&-fsCqEU-J0T_nF9w;p#|)?r z7cf#n4(5ADOv{bsb(2|AaxOXHCPD0%ezxal3cdK>!#~UKnI{Y~2X4z(AanZ)2Z}fu&qd50B{- z2^ww10(ds4O%5q*)-pHOrqpGVhZ4M~nAUd2V2V_glCKWj-OX1T&v#Er>Ugd3x}|*Y z?VDa)WJ)O4Jt-~0N_}dQ>2TK^Y(3R^%CmcA3m*N9K(6p6ZpTiiMu~VUDgF-8F25c1 zUFL6-XLVGX;iTELwuS~5I5G^S19!s_Wb^Wn`Sa^v*HX;u<2Z*L1m>Wu&1P;};qgx* z4?g09w7G$G1WTjI_vTT)dCFfNqz%vczE+IXZ0B1026y`&6|uK1Zl1;&=@0$-EC@{EyIVma66LUnU7ujC30?Y^^Tm_;`w4}6|Wcr+FYIHc?j+JEc1b? zWbjVpNQ*VIls0muWB)lY0KD?5hk^|)rGa91^f=4NwmX?J;F2t`=l5h`QwR64XP2N) zTBdZYXtuxgkNG0K9g1%~*Zx*sJ?O9aEUZ3twHeILQT7l<@IZy%yEDYhdn7??ZjHQXc;dMfH->hM@4 z{-uC>;b`Wg1rKS`0}MkR`#R&M;wOQzFNh;jvSK&xMv{oWB;Qh4sMwXGHR~5E+7tS} z(B$D9g%7{Fe#9|~H2K&r7Ck`LFBh?q6ZtMW-A&o7fGH}N!&!HUy#vzVm2va5CzB*t ztiazNedJs(TiwDZ6gS;pV3!cNc1G?~rxu)%#xvkme7~NTQ|0rfq6P1rD-UB%Z!45nYVYY8ApQN-u6*5` zk9pK2bdlmXy;P3Y4jY4W(#NQxT}a=q^N}Y%l)m8pWgK%-i4-t7B<=rPGMY>H5C^HJ1(=ksH7eMT5Oj;LZc-sDm4`jW(^?ZZ(~eU*^B zY}IxNYg2Ozg^q9*!i8cXQ{vA75QY%Nk6LxN{Fz3%IZlU4reF~Al^;a)5SsvwGVzP+ zf>JW8WD#xk6KkkGy&WRMQ*%0aIHKme^;w~V*Do%>NL_`SA}3?5tb}G~7%4;ZI0ZgR z%9kQ$+m>LUJI9HJt$zAK>Q-@oyVT%31bXp8w;~2TUdeQX&--fX@npXY{1fbc;sbWW z?7cC+o8A)uR`n-@86U)xBmv^?OB)G=P^R(kBV z#c+MPo6%&UeV*ACGivs5QrRo{|) z@Zmx?bv1hWi}0_lfWE66fvA*tNJ4Z{hanPS`-*4a0!*5_z4Lk>o025Mncy>IAr_B! z7xtzSHuI^XCQ4I<>T`H|cQ3-Q7Pj-Dg%6K}W5E8?SAN4joWqJ@Sl$#dmSDRa=VR3^ zAy^_w$-DcbK{0P=o&|ZA(y<7nbj?!{pj4RbBu#DFRac&n8YP6ZCPiUad>ESU-l6_h zsUlX9338iHs}1!rj)E_{MfjLh9Hu@0>_s~^W%sC2dQR+7L(3r6Av@oJe&C%3ar+9I zi#72EAyeZt6vXcv<<)O9Crm`3`u=WBP`t@-0M4fEZ5k?*pOJB@s#<)IcfX{OUa$@X zdNy3A;Cy1$@mA$4wKm<&PX-@Oz7PsI1c5koKd)eyyr7`wj;|t47a#Q)L`ry=p5<#F ztYOwly5y^~w1~+u=XcVdP@fjL4x_!ucW!8de(m@n%%fPNiN!?H9Bu@B(0-ifhS!{F zcX+V9J{y)S@8u=b!Gj6NolmLS{`gp$VRHPXO<2u#i3NneW{j#+@@&f|0~EN=`ekgR zzKV<3u=rSW{(CddTot*-6&5anV48Hli8axykL8S-Zn!>#9cbr_MXnno_K@d?6i5BIt-F+}6INq#Ts1W+HpOws68H6sEI% z$Y1VW%j0q%k*WD3%*VQ+qfBcD^nRVH$%dFz>}HPch;LUh`b{2tpzYW}4a_t3p7^M= zm3jJ;VKB;hc>_;VjbQ^G zVK=sE!mNtjZ>Jp>sOOB4BKW4?sZ5Dll@_>=sq;m0V4_#79~NH92i_D>H&3KZKXJ;P zqx@L*LDD$QphnGWeDIg4ddE#4iJ#k_R^yR2?p+FE(T;nBwF(?~SADzv7dJ)izJ1u( z%S`!IO33nX)^E1N4K|YSxe!hI+>XNJY=as(b&z z_Nm|W%P}#(-K&pK&z8F0J(}VS)+|5tFfDxUs-nJ$G}bSA-TP{D;?es@8ci#wd8bk# zAWi#VABceq=uAm^Cyt}E&q3B3gi~(htnf%7Wxy%%_3XW~lE~iG9ouGe$Qw2D{?!WG z<8K4HyGs}r-4)T9oJA-z?iO(sA6#X1*J;-273ky3w(yKxPD8Zvh|W_hrCMJ0 z7|oeBc_b>mt50k(o4j>8inO8Uz1p&;X z$&9MCO_7c@OIQ;rxNpvh&(XdByBoYeffyioSQZY-@s!FZ8fm)S?nw*#EpdzRfF&oZ)8=~E|MyPGq&rqwaV>ka0xanQm%xa!a%8XMuBXh;5IUR=F_ zWzf<=z;sI7ua{o;$qQ|tpO!6kD!Wu z@S*y1Ox!<>46qZCH;#6uS1lQ^zgV5Gkyw(NLQggAdPKr~cv6>?)`ZxcNb9Q1L#x8` z*wiK>T)kuN%j1bVPS^cPB)!coj2JeezR+)~hf6-78Qf)|yhs!<>R&Kwy(MZFX;=cERWUm!?a{+ zf>pLXR}uYol2ru0xL<@k-5LtACo8MBF%;f!L)v+^rgO`sA6;-k!>}F25C87|i}j8) z0Zp&C@1j`g>Z16{#DwNfIwMtztlfNRPQhVYb|QQBbLNap=gf^@4Mhlu+hge31!|k8_UKlA24E36vItzJX*&S4v5{EJTB;5viAS%MBlrD>N)vrL%i za1EX^ZD9Jx^x36qvy{N`CjmF!+sg?$6m4(`z#ZZTENyCu?g>lXOoj#D2-%9XD2d)_B_&83#O z2YWV62s%MizO{JbZsieOU^2$=jc0Pmy}X@t+aysq|9)Jpqy7xD`Q6to$+?P-cN>_C z>_zi+Jf2X>(56ns@YE)u_uR7l?GI?OH@}5>${hQ>f7!J_pdFx2bnp0tY7{a0X>*l} z_~MESO!FNYqYd-Lf5sna$V=-e-LKQ6Sp9uTU-(u4F49?`+(aeyv@o3GU=7A@3iR z58-9UKh5S@!YY0qYNiquUQ?gjn%gJJM5snXLjy*^)I_(;$^`J;sE zC5PZ_!^k~022nMHsfM)}qUvd*7F(ZEAw4Vh?&-cho=3LUiMXMXvpeav`fL0qg80GZ zaf;(eT6t}g2c@yEwM&x4-cCvtJd=L0g`w5-;|p3-DDG>lyQhePpcVJ z6q%kiXD$|tDn5ASn5diT($K0L6COEfUCj65)8naA8(;eVYaR4x`ES>Hh_dO^a{H`t zQ}?Q0Pj@S5>cz&@U#GF?sfU5(7)0B?F!q&g-TN@I@H6r#^qU`Ei-#07_(8E)t*f-> zQWTw*SGZmkd~i3jE^72@eJ($FqHcTXTillnk+_lyRo4^Fp4~3n-|iz+8zC_XF{qa8 zX7Q_9QQ^*U5onvAS|^kt&%b8=*6v;xS9vs^J|F89q88IlZf|9KNqfm=s<_sttPK&V^v5wwRbQh};cC%Mv zgK2*G3?wR#AM>|TPdYMz;jd}n?0HO-9MJfE4}&h)X*yWMhu5N^fRV@fhh zU)r*TPbj`7mMao8E`s#O_=pgBt(R|)8&jf|3}b$ILpN<-trIT9#HB>i&nK?r*-8vM z?zXjzvmd|7l9dc!>6;L)>L2YF3cVk5EDo2;VJJ`zu0l z637x;YAN-?n3QHmn2JqrwJm*!kjI$a1vH^W`rS#zjdYAVqJh0eAdC-z3hfworyCzP z+3jbWI!{LS3{nOOkC>hd5v#x8PU%iA6&N!0tgm>TpXrO+s-z!vpC0{qJC(!#+xi}r zywPY$(_x7I4;B5uEbSsr>$k^0sTZKD(G8Z%JB)oHO3VkL(by%n@G!DlT*K~HB=5R4 zqqslnG>!TU9b>q_BP=o;#CnFkRf=6WkECD0$l*=_L5_moj80R{vSKR>u^aE{eWY{g zo?hjDB{o1ItR$sas>Y^8_=%vJFS^=2Eo{J^=juE~X(Ut4jTE!VrEd@Jz7$E4BFr%X zSEyH8G$FMiO4QmH#{nztam)>&JV5_}M0gO`5cb*umytXzZ&?YKvMa|AwRWtg9}lIr z=mJay(3X**icnYaEa$!mFJd_LD(@-J%%xvRMqA~#nyIE-IlL`GtCP1XxG`pjr0cxD zAALx=7?9h@UcLuii|$NuqLTP4#)NI39{LO_-0mz=lr6d1cRMCJ7EV$Woh2LCYxz`b z!aa44)Vgrbu6XBLwfY0-RX~NJ6VI;btFo!p((~MW`^0Ed{WY|VcD&9aX<~vaVFGWd zw7oyixOcH(d^t>`GCh^H*!nhz4w~1VyjeWpX zn2n00q*Oei*BQ;vgB_{uoSL&2KekBAU~PZ0d1P53B^4_90!%6w#u#UxI@RvRxFE5V>{$D_Wzc-G@=X&AmYR$-{X>Mzc4_w`?ojniiBGA=%hM%(~Qn4gzXKt#|4pGy`<29)T*c)69mHa?K_ zuQwC~?tgD>FJtau{YQRWO4d$Z)}Hp3=9h*1_2!o`f80I?S$O{OEtg-!^9M-Y+0wJKVjl2-dafXa-QWcW|04C5uL{tK$ic=<{H?d}1T&&b8YDez~Mnu`@6v^pNv z>MqWI$gQpQGjm@T5Fn1v0e*L~{zIPsB~Cu>);9Ruj6A&f+ z|B+6Z7r@8A!}xgqyWGo{`ByqmcXN9uYj=Ec@k`YBSpzs=;m^)7;(j4}9?fhYgi+-XaV{&DIj2C0%LPn zAUPNoCj7vG-OVKQ=U~e0*QDFY4p$7DTD*n}w+}Q;o)lZy$ zq7D`NcHyns#Dnni(fmyrTZXJhImziX^-4muS8-w#b&*0O&g`-oHOq~aD(P#pAoAY- zE|rR1v?+e#m=$MP2G=`kM9tA`v>KV5Y`8ixx2NPOU~Nd6Xm_+bGwG#|IL^G(?V*S< zjpz+-q78YE^bAHX*TuV22UX+t9Fd%;_$RgQ>V}Syp_WPAYR9CTlh}?x&pllALD^)w zjrQ1$U3ca7NgNF#tYvE#^97L}r=`80^YQyTf}U}lzKLW^>5(sI#|O=H;=e1_X~|1V zJvZ{aM>^@j_yFR#(aQr`yHxil*u9ukc_opw9Ca_}=j$o)zvq#9rke52z43F^9d7UX zGrh~SXoCA~&4F!3WL>3+%&ek@WRDQ{$aB$7a?~+6vagNnYm#AdM5*oJVT9bgk%{w3 z;cTyl@u2Q>KjuUH$hJv))%Z|B4`H+7V>uf*f5RL>Me^JXzn3KArnc#H%cyYz!Tp9> z^NrT(Y6JF~zHv@>`JHI(jhBh#D*4-{X?e0*d)`RS?4Vk=(0&Wd%eYhD?Oxt~Klp`U zyZzFmrNGnEv1XdQ^5(z}LF7dpuinRQ2Gm)pfo~?ZHQpF>qcgAG6h>5EqU~Mk=z28_ z|MkcD7%N{zc>b6VE3C2V zQcY{gKk{a3&>K}67qhH{5yjb^`WN7Z+UYUcw(2{h%SvxnT^g%lJyxN3G_9S+%bCQP z_$%qsrpdsrz&ofk>scibXWClsjk0y_&uxArMpMF5BG;>N!31#m2YS@SK3K- z6z1MEGNDu`J1o&X+4afUvEHTxF5mVds*s;BGG9FO#w^-yn`Y46l+g1o6J{5>1h!$E z^5aP#*WFaH>B0&QtdEsU?SuUngqKH3_<wlEeD|N@aHWAdd24}cylvQ{ zLr*eWFm1KUb)jo6Y)QS{bgwl_HUHGN4SU@(0(GMEPi3dQy`i0d3U%I06SH{Tf@h{F z2ZjH8isrz{NfV`GFZW;do?huf5$thR2Y=(IT&CKr+Ou;mvu zBmjlvTMEe*zrh=)X}rtL8U8(QT@Qv6gVghPOced<(wbtZZ7=akDL{D>vDD45#`S4V z^7YOuNgP`k2N=M|^NERetzn&$jMQ~jt;&L6@p4g>o3R{WFB$!E01$Sx_dYe zD|wgrs{!IVUd-Vy4S;j#BlE=xD^R>QBV^V|b ztcN2n0k8Kh+>=nVc%rzq$nDzbo9fr&n=%^Lx{&rCPIu>=H%Bh%n6FV$a1eAYXX0HsD>xA=E7fzt$

U zdhkRx4>A{6P2!yt5?| zUK0xy6~GND)CrLc;k1u5+4|OyyoQ%M30C^m1z%t*qCaaRE9VkKpylq#3c^+)SMjc z4O+6fNEW3W8r)Cy5ouWlfzqi08I+au3f+mavM3dcdXym!2V23ge`RbK!ueF_7yvbd1B>bJ1abfm1XKY42xl;i10ZaJp|R#G zy_wf1ODiVy9kjR#fD%69N034zn=!)x4Z1WH-oOinFo(<_Mm8X-AxJRDbY+GH z(DUb-!i>xY#ot5Nfb>w1L-Qw#NLFSpdLw>x;`(vKYZ0voC59{+P{~1KPyvJsjbX}Q z(>?=VFya0?ldioVopzWD{*8==|AWztNvHgcbol>+?(biu$oHQdC|U}Du!Fot5qnYO zTGA@e77)2%HEITkw(2X?77#7zOSOmuyF&Jbp4l*nmBI!*U?RPfU}C*-Mf(22{V0(j zKaYjS!`$$076uFi(maHDyI<#*dUR~5C<<6B#@6Xxll|xL87OF;-LO_Oog$)02mTL zp<&3s8eo9MVz58}u!5m+NNBS}4Pg9*L9x0TLn2XM*`e?T{{b`n3PYpxA#bnZKx3gJ zU=@Zj_}We%2WeuJ9nJtc

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ +#include #include "main.h" #include "cmsis_os.h" + /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "moteurs.h" +#include "leds.h" +#include "xbee.h" +#include "batterie.h" +#include "messages.h" /* USER CODE END Includes */ @@ -55,9 +62,9 @@ TIM_HandleTypeDef htim21; /* Definitions for defaultTask */ osThreadId_t defaultTaskHandle; const osThreadAttr_t defaultTask_attributes = { - .name = "defaultTask", - .stack_size = 128 * 4, - .priority = (osPriority_t) osPriorityNormal, + .name = "defaultTask", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityNormal, }; /* USER CODE BEGIN PV */ @@ -84,491 +91,527 @@ void StartDefaultTask(void *argument); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ - /* USER CODE END SysInit */ + /* USER CODE END SysInit */ - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_DMA_Init(); - MX_LPTIM1_Init(); - MX_LPUART1_UART_Init(); - MX_TIM2_Init(); - MX_TIM21_Init(); - MX_ADC_Init(); - /* USER CODE BEGIN 2 */ + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + MX_LPTIM1_Init(); + MX_LPUART1_UART_Init(); + MX_TIM2_Init(); + MX_TIM21_Init(); + MX_ADC_Init(); + /* USER CODE BEGIN 2 */ + /* Init des messages box */ + MESSAGE_Init(); - /* USER CODE END 2 */ + LEDS_Init(); - /* Init scheduler */ - osKernelInitialize(); + /*MOTEURS_Init(); + MOTEURS_Test();*/ + /* USER CODE END 2 */ - /* USER CODE BEGIN RTOS_MUTEX */ - /* add mutexes, ... */ - /* USER CODE END RTOS_MUTEX */ + /* Init scheduler */ + osKernelInitialize(); - /* USER CODE BEGIN RTOS_SEMAPHORES */ - /* add semaphores, ... */ - /* USER CODE END RTOS_SEMAPHORES */ + /* USER CODE BEGIN RTOS_MUTEX */ + /* add mutexes, ... */ + /* USER CODE END RTOS_MUTEX */ - /* USER CODE BEGIN RTOS_TIMERS */ - /* start timers, add new ones, ... */ - /* USER CODE END RTOS_TIMERS */ + /* USER CODE BEGIN RTOS_SEMAPHORES */ + /* add semaphores, ... */ + /* USER CODE END RTOS_SEMAPHORES */ - /* USER CODE BEGIN RTOS_QUEUES */ - /* add queues, ... */ - /* USER CODE END RTOS_QUEUES */ + /* USER CODE BEGIN RTOS_TIMERS */ + /* start timers, add new ones, ... */ + /* USER CODE END RTOS_TIMERS */ - /* Create the thread(s) */ - /* creation of defaultTask */ - defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); + /* USER CODE BEGIN RTOS_QUEUES */ + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ - /* USER CODE BEGIN RTOS_THREADS */ - /* add threads, ... */ - /* USER CODE END RTOS_THREADS */ + /* Create the thread(s) */ + /* creation of defaultTask */ + defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); - /* USER CODE BEGIN RTOS_EVENTS */ - /* add events, ... */ - /* USER CODE END RTOS_EVENTS */ + /* USER CODE BEGIN RTOS_THREADS */ + /* add threads, ... */ - /* Start scheduler */ - osKernelStart(); + /* USER CODE END RTOS_THREADS */ - /* We should never get here as control is now taken by the scheduler */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ + /* Start scheduler */ + osKernelStart(); + + /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure the main internal regulator output voltage - */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.MSICalibrationValue = 0; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_DIV4; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_3; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_LPTIM1; - PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; - PeriphClkInit.LptimClockSelection = RCC_LPTIM1CLKSOURCE_PCLK; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_LPTIM1; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + PeriphClkInit.LptimClockSelection = RCC_LPTIM1CLKSOURCE_PCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } } /** - * @brief ADC Initialization Function - * @param None - * @retval None - */ + * @brief ADC Initialization Function + * @param None + * @retval None + */ static void MX_ADC_Init(void) { - /* USER CODE BEGIN ADC_Init 0 */ + /* USER CODE BEGIN ADC_Init 0 */ - /* USER CODE END ADC_Init 0 */ + /* USER CODE END ADC_Init 0 */ - ADC_ChannelConfTypeDef sConfig = {0}; + ADC_ChannelConfTypeDef sConfig = {0}; - /* USER CODE BEGIN ADC_Init 1 */ + /* USER CODE BEGIN ADC_Init 1 */ - /* USER CODE END ADC_Init 1 */ - /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) - */ - hadc.Instance = ADC1; - hadc.Init.OversamplingMode = DISABLE; - hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1; - hadc.Init.Resolution = ADC_RESOLUTION_12B; - hadc.Init.SamplingTime = ADC_SAMPLETIME_160CYCLES_5; - hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; - hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc.Init.ContinuousConvMode = DISABLE; - hadc.Init.DiscontinuousConvMode = DISABLE; - hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc.Init.DMAContinuousRequests = DISABLE; - hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; - hadc.Init.LowPowerAutoWait = DISABLE; - hadc.Init.LowPowerFrequencyMode = ENABLE; - hadc.Init.LowPowerAutoPowerOff = DISABLE; - if (HAL_ADC_Init(&hadc) != HAL_OK) - { - Error_Handler(); - } - /** Configure for the selected ADC regular channel to be converted. - */ - sConfig.Channel = ADC_CHANNEL_0; - sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; - if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ADC_Init 2 */ + /* USER CODE END ADC_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc.Instance = ADC1; + hadc.Init.OversamplingMode = DISABLE; + hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1; + hadc.Init.Resolution = ADC_RESOLUTION_8B; + hadc.Init.SamplingTime = ADC_SAMPLETIME_160CYCLES_5; + hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; + hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc.Init.ContinuousConvMode = DISABLE; + hadc.Init.DiscontinuousConvMode = DISABLE; + hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc.Init.DMAContinuousRequests = DISABLE; + hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc.Init.LowPowerAutoWait = DISABLE; + hadc.Init.LowPowerFrequencyMode = DISABLE; + hadc.Init.LowPowerAutoPowerOff = DISABLE; + if (HAL_ADC_Init(&hadc) != HAL_OK) + { + Error_Handler(); + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_0; + sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC_Init 2 */ - /* USER CODE END ADC_Init 2 */ + /* USER CODE END ADC_Init 2 */ } /** - * @brief LPTIM1 Initialization Function - * @param None - * @retval None - */ + * @brief LPTIM1 Initialization Function + * @param None + * @retval None + */ static void MX_LPTIM1_Init(void) { - /* USER CODE BEGIN LPTIM1_Init 0 */ + /* USER CODE BEGIN LPTIM1_Init 0 */ - /* USER CODE END LPTIM1_Init 0 */ + /* USER CODE END LPTIM1_Init 0 */ - /* USER CODE BEGIN LPTIM1_Init 1 */ + /* USER CODE BEGIN LPTIM1_Init 1 */ - /* USER CODE END LPTIM1_Init 1 */ - hlptim1.Instance = LPTIM1; - hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; - hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; - hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING; - hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION; - hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; - hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; - hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; - hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL; - if (HAL_LPTIM_Init(&hlptim1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN LPTIM1_Init 2 */ + /* USER CODE END LPTIM1_Init 1 */ + hlptim1.Instance = LPTIM1; + hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING; + hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION; + hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL; + if (HAL_LPTIM_Init(&hlptim1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPTIM1_Init 2 */ - /* USER CODE END LPTIM1_Init 2 */ + /* USER CODE END LPTIM1_Init 2 */ } /** - * @brief LPUART1 Initialization Function - * @param None - * @retval None - */ + * @brief LPUART1 Initialization Function + * @param None + * @retval None + */ static void MX_LPUART1_UART_Init(void) { - /* USER CODE BEGIN LPUART1_Init 0 */ + /* USER CODE BEGIN LPUART1_Init 0 */ - /* USER CODE END LPUART1_Init 0 */ + /* USER CODE END LPUART1_Init 0 */ - /* USER CODE BEGIN LPUART1_Init 1 */ + /* USER CODE BEGIN LPUART1_Init 1 */ - /* USER CODE END LPUART1_Init 1 */ - hlpuart1.Instance = LPUART1; - hlpuart1.Init.BaudRate = 9600; - hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; - hlpuart1.Init.StopBits = UART_STOPBITS_1; - hlpuart1.Init.Parity = UART_PARITY_NONE; - hlpuart1.Init.Mode = UART_MODE_TX_RX; - hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&hlpuart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN LPUART1_Init 2 */ + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + hlpuart1.Init.BaudRate = 9600; + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + hlpuart1.Init.StopBits = UART_STOPBITS_1; + hlpuart1.Init.Parity = UART_PARITY_NONE; + hlpuart1.Init.Mode = UART_MODE_TX_RX; + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&hlpuart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPUART1_Init 2 */ - /* USER CODE END LPUART1_Init 2 */ + /* USER CODE END LPUART1_Init 2 */ } /** - * @brief TIM2 Initialization Function - * @param None - * @retval None - */ + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ static void MX_TIM2_Init(void) { - /* USER CODE BEGIN TIM2_Init 0 */ + /* USER CODE BEGIN TIM2_Init 0 */ - /* USER CODE END TIM2_Init 0 */ + /* USER CODE END TIM2_Init 0 */ - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - TIM_OC_InitTypeDef sConfigOC = {0}; + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; - /* USER CODE BEGIN TIM2_Init 1 */ + /* USER CODE BEGIN TIM2_Init 1 */ - /* USER CODE END TIM2_Init 1 */ - htim2.Instance = TIM2; - htim2.Init.Prescaler = 0; - htim2.Init.CounterMode = TIM_COUNTERMODE_UP; - htim2.Init.Period = 65535; - htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim2) != HAL_OK) - { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) - { - Error_Handler(); - } - if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - sConfigOC.OCMode = TIM_OCMODE_PWM1; - sConfigOC.Pulse = 0; - sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) - { - Error_Handler(); - } - if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) - { - Error_Handler(); - } - if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) - { - Error_Handler(); - } - if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM2_Init 2 */ + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 255; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ - /* USER CODE END TIM2_Init 2 */ - HAL_TIM_MspPostInit(&htim2); + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); } /** - * @brief TIM21 Initialization Function - * @param None - * @retval None - */ + * @brief TIM21 Initialization Function + * @param None + * @retval None + */ static void MX_TIM21_Init(void) { - /* USER CODE BEGIN TIM21_Init 0 */ + /* USER CODE BEGIN TIM21_Init 0 */ - /* USER CODE END TIM21_Init 0 */ + /* USER CODE END TIM21_Init 0 */ - TIM_Encoder_InitTypeDef sConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_Encoder_InitTypeDef sConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; - /* USER CODE BEGIN TIM21_Init 1 */ + /* USER CODE BEGIN TIM21_Init 1 */ - /* USER CODE END TIM21_Init 1 */ - htim21.Instance = TIM21; - htim21.Init.Prescaler = 0; - htim21.Init.CounterMode = TIM_COUNTERMODE_UP; - htim21.Init.Period = 65535; - htim21.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim21.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - sConfig.EncoderMode = TIM_ENCODERMODE_TI1; - sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; - sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; - sConfig.IC1Prescaler = TIM_ICPSC_DIV1; - sConfig.IC1Filter = 0; - sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; - sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; - sConfig.IC2Prescaler = TIM_ICPSC_DIV1; - sConfig.IC2Filter = 0; - if (HAL_TIM_Encoder_Init(&htim21, &sConfig) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim21, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM21_Init 2 */ + /* USER CODE END TIM21_Init 1 */ + htim21.Instance = TIM21; + htim21.Init.Prescaler = 0; + htim21.Init.CounterMode = TIM_COUNTERMODE_UP; + htim21.Init.Period = 65535; + htim21.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim21.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + sConfig.EncoderMode = TIM_ENCODERMODE_TI1; + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + sConfig.IC1Filter = 0; + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + sConfig.IC2Filter = 0; + if (HAL_TIM_Encoder_Init(&htim21, &sConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim21, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM21_Init 2 */ - /* USER CODE END TIM21_Init 2 */ + /* USER CODE END TIM21_Init 2 */ } /** - * Enable DMA controller clock - */ + * Enable DMA controller clock + */ static void MX_DMA_Init(void) { - /* DMA controller clock enable */ - __HAL_RCC_DMA1_CLK_ENABLE(); + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); - /* DMA interrupt init */ - /* DMA1_Channel2_3_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3, 0); - HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + /* DMA interrupt init */ + /* DMA1_Channel2_3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); } /** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ + * @brief GPIO Initialization Function + * @param None + * @retval None + */ static void MX_GPIO_Init(void) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; + GPIO_InitTypeDef GPIO_InitStruct = {0}; - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOB, LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin|SHUTDOWN_ENCODERS_Pin - |SHUTDOWN_5V_Pin|SHUTDOWN_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin|SHUTDOWN_ENCODERS_Pin + |SHUTDOWN_5V_Pin, GPIO_PIN_RESET); - /*Configure GPIO pins : LED_ROUGE_Pin LED_ORANGE_Pin LED_VERTE_Pin SHUTDOWN_ENCODERS_Pin - SHUTDOWN_5V_Pin SHUTDOWN_Pin */ - GPIO_InitStruct.Pin = LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin|SHUTDOWN_ENCODERS_Pin - |SHUTDOWN_5V_Pin|SHUTDOWN_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(SHUTDOWN_GPIO_Port, SHUTDOWN_Pin, GPIO_PIN_SET); - /*Configure GPIO pins : BUTTON_SENSE_Pin USB_SENSE_Pin */ - GPIO_InitStruct.Pin = BUTTON_SENSE_Pin|USB_SENSE_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /*Configure GPIO pins : LED_ROUGE_Pin LED_ORANGE_Pin LED_VERTE_Pin */ + GPIO_InitStruct.Pin = LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - /*Configure GPIO pins : CHARGER_ST2_Pin CHARGER_ST1_Pin */ - GPIO_InitStruct.Pin = CHARGER_ST2_Pin|CHARGER_ST1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /*Configure GPIO pins : SHUTDOWN_ENCODERS_Pin SHUTDOWN_5V_Pin SHUTDOWN_Pin */ + GPIO_InitStruct.Pin = SHUTDOWN_ENCODERS_Pin|SHUTDOWN_5V_Pin|SHUTDOWN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - /* EXTI interrupt init*/ - HAL_NVIC_SetPriority(EXTI2_3_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(EXTI2_3_IRQn); + /*Configure GPIO pins : BUTTON_SENSE_Pin USB_SENSE_Pin */ + GPIO_InitStruct.Pin = BUTTON_SENSE_Pin|USB_SENSE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /*Configure GPIO pins : CHARGER_ST2_Pin CHARGER_ST1_Pin */ + GPIO_InitStruct.Pin = CHARGER_ST2_Pin|CHARGER_ST1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI2_3_IRQn, 3, 0); + HAL_NVIC_EnableIRQ(EXTI2_3_IRQn); } /* USER CODE BEGIN 4 */ +TickType_t msToTicks(TickType_t ms) { + TickType_t tmp = ms; + if (ms<(1000/configTICK_RATE_HZ)) + tmp = 1; + else { + tmp = ms/(1000/configTICK_RATE_HZ); + + if (ms % (1000/configTICK_RATE_HZ)) // if the delay is not true multiple of tick rate, increase by one (delay longer) + tmp ++; + } + return tmp; +} /* USER CODE END 4 */ /* USER CODE BEGIN Header_StartDefaultTask */ /** - * @brief Function implementing the defaultTask thread. - * @param argument: Not used - * @retval None - */ + * @brief Function implementing the defaultTask thread. + * @param argument: Not used + * @retval None + */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { - /* USER CODE BEGIN 5 */ - /* Infinite loop */ - for(;;) - { - osDelay(1); - } - /* USER CODE END 5 */ + /* USER CODE BEGIN 5 */ + LEDS_State state = leds_off; + + /* Infinite loop */ + for(;;) + { + state++; + MESSAGE_SendMailbox(LEDS_Mailbox, MSG_ID_LED_ETAT, SEQUENCEUR_Mailbox, (void*)&state); + + if (state>leds_erreur) + state = leds_off; + + vTaskDelay(pdMS_TO_TICKS(5000)); + } + /* USER CODE END 5 */ } /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/software/dumber3/Core/Src/messages.c b/software/dumber3/Core/Src/messages.c new file mode 100644 index 0000000..8c2df94 --- /dev/null +++ b/software/dumber3/Core/Src/messages.c @@ -0,0 +1,64 @@ +/* + * messages.c + * + * Created on: 14 sept. 2022 + * Author: dimercur + */ + +#include "messages.h" +#include "stdlib.h" + +#define QUEUE_SIZE 5 + +QueueHandle_t LEDS_Mailbox; +QueueHandle_t MOTEURS_Mailbox; +QueueHandle_t SEQUENCEUR_Mailbox; +QueueHandle_t BATTERIE_Mailbox; +QueueHandle_t XBEE_Mailbox; + +void MESSAGE_Init(void) { + LEDS_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + MOTEURS_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + SEQUENCEUR_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + BATTERIE_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + XBEE_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); +} + +MESSAGE_Typedef MESSAGE_ReadMailbox(QueueHandle_t mbx) { + MESSAGE_Typedef msg= {0}; + char msg_received =0; + + while (!msg_received) { + if (xQueueReceive(mbx, &msg, portMAX_DELAY)) { // un message à été reçu + msg_received=1; + + return msg; + } + } + + return msg; +} + +MESSAGE_Typedef MESSAGE_ReadMailboxNoDelay(QueueHandle_t mbx) { + MESSAGE_Typedef msg= {0}; + + if (!xQueueReceive(mbx, &msg, 0)) // Pas de message dans la mailbox + msg.id=MSG_ID_NO_MESSAGE; + + return msg; +} + +void MESSAGE_SendMailbox(QueueHandle_t mbx_dest, uint16_t id, QueueHandle_t mbx_sender, void *data){ + MESSAGE_Typedef msg; + + msg.id=id; + msg.sender = &mbx_sender; + msg.data=data; + + if (!xQueueSend(mbx_dest, &msg, 0)) { // envoi sans attendre + //printf("Failed to send data, Queue full.\r\n"); + } +} + + + diff --git a/software/dumber3/Core/Src/moteurs.c b/software/dumber3/Core/Src/moteurs.c new file mode 100644 index 0000000..00be383 --- /dev/null +++ b/software/dumber3/Core/Src/moteurs.c @@ -0,0 +1,215 @@ +/* + * moteurs.c + * + * Created on: Sep 12, 2022 + * Author: dimercur + */ + +#include "main.h" + +extern LPTIM_HandleTypeDef hlptim1; + +extern TIM_HandleTypeDef htim2; +extern TIM_HandleTypeDef htim21; + +int16_t MOTEUR_CmdMoteurG; +int16_t MOTEUR_CmdMoteurD; +int16_t MOTEUR_ConsigneMoteurG; +int16_t MOTEUR_ConsigneMoteurD; + +int16_t MOTEUR_NBImpulsionsG; +int16_t MOTEUR_NBImpulsionsD; + +uint16_t MOTEUR_DerniereValEncodeursG; +uint16_t MOTEUR_DerniereValEncodeursD; + +#define MOTEUR_GAUCHE 0 +#define MOTEUR_DROIT 1 + +#define MOTEUR_Kp 15 +#define MOTEUR_DELAY 3 + +/* + * Global informations + * Main clock: 6 Mhz + * Tim2 PWM range: 0 - 255 (freq: 23437,5 Mhz) + * TIM21: encodeur gauche (0 - 65535) + * LPTIM: encodeur droit (0 - 65535) + */ + +/** + * + */ +void MOTEURS_DesactiveAlim(void) { + HAL_GPIO_WritePin(GPIOB, SHUTDOWN_ENCODERS_Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOB, SHUTDOWN_5V_Pin, GPIO_PIN_RESET); +} + +/** + * + */ +void MOTEURS_ActiveAlim(void) { + HAL_GPIO_WritePin(GPIOB, SHUTDOWN_ENCODERS_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOB, SHUTDOWN_5V_Pin, GPIO_PIN_SET); +} + +/** + * + */ +GPIO_PinState MOTEURS_EtatAlim(void) { + return HAL_GPIO_ReadPin(GPIOB, SHUTDOWN_5V_Pin); +} + +int16_t MOTEUR_LireEncodeursGauche(void) { + uint16_t loc_val= htim21.Instance->CNT; + uint16_t overflow = htim21.Instance->SR; + int16_t val_end; + + htim21.Instance->SR = htim21.Instance->SR & ~(TIM_SR_UIF); + + if (overflow & TIM_SR_UIF) { + val_end = 0xFFFF-loc_val + MOTEUR_DerniereValEncodeursG; + } else { + val_end = MOTEUR_DerniereValEncodeursG-loc_val; + } + + MOTEUR_DerniereValEncodeursG = loc_val; + return val_end; +} + +int16_t MOTEUR_LireEncodeursDroit(void) { + uint16_t loc_val= hlptim1.Instance->CNT; + uint32_t status = hlptim1.Instance->ISR; + int16_t val_end; + + hlptim1.Instance->ICR=0xFF; // refait descendre les flags ISR + + if (status & LPTIM_ISR_ARRM) { + val_end = 0xFFFF-loc_val + MOTEUR_DerniereValEncodeursD; + } else { + val_end = MOTEUR_DerniereValEncodeursD-loc_val; + } + + val_end= -val_end; + + MOTEUR_DerniereValEncodeursD = loc_val; + return val_end; +} + +/** + * + */ +void MOTEURS_Init(void) { + /* Desactive les alimentations des moteurs */ + MOTEURS_DesactiveAlim(); + + /* Lance les timers (timers PWM + timers encodeurs) et regle tout à zero*/ + hlptim1.Instance->CR = LPTIM_CR_ENABLE; + hlptim1.Instance->CR = LPTIM_CR_ENABLE | LPTIM_CR_CNTSTRT; + hlptim1.Instance->ARR = 65535; + hlptim1.Instance->CFGR = LPTIM_CFGR_ENC; + + hlptim1.Instance->CNT = 0; + + htim21.Instance->ARR = 65535; + htim21.Instance->CR1 = htim21.Instance->CR1 | TIM_CR1_CEN| TIM_CR1_URS; + htim21.Instance->CNT = 0; + + htim2.Instance->ARR = 255; + htim2.Instance->CNT = 0; + htim2.Instance->CCR1 = 0; + htim2.Instance->CCR2 = 0; + htim2.Instance->CCR3 = 0; + htim2.Instance->CCR4 = 0; + htim2.Instance->CR1 = htim2.Instance->CR1 | TIM_CR1_CEN; + htim2.Instance->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E; + + MOTEUR_CmdMoteurG =0; + MOTEUR_CmdMoteurD =0; + MOTEUR_ConsigneMoteurG =0; + MOTEUR_ConsigneMoteurD =0; +} + +/** + * @brief Active les encodeurs et le regulateur des moteur si necessaire et + * regle la commande du moteur (entre -255 et +255) + */ +void MOTEURS_Set(uint8_t mot, int16_t val) { + uint8_t loc_val; + + if (val>=0) { + if (val>255) loc_val = 255; + else loc_val =(uint8_t)val; + } else { + if (val < -255) loc_val = 255; + else loc_val =(uint8_t)(-val); + } + + if (MOTEURS_EtatAlim()==GPIO_PIN_RESET) + MOTEURS_ActiveAlim(); + + if (mot == MOTEUR_DROIT) { + if (val >=0) { + htim2.Instance->CCR1 = (uint16_t)loc_val; + htim2.Instance->CCR2 = 0; + } else { + htim2.Instance->CCR2 = (uint16_t)loc_val; + htim2.Instance->CCR1 = 0; + } + } else { + if (val >=0) { + htim2.Instance->CCR4 = (uint16_t)loc_val; + htim2.Instance->CCR3 = 0; + } else { + htim2.Instance->CCR3 = (uint16_t)loc_val; + htim2.Instance->CCR4 = 0; + } + } +} + +void MOTEURS_Test (void) { + int16_t deltaG, deltaD =0; + + MOTEUR_LireEncodeursGauche(); + MOTEUR_LireEncodeursDroit(); + + while (1) { + HAL_Delay(MOTEUR_DELAY); + + MOTEUR_NBImpulsionsG = MOTEUR_LireEncodeursGauche(); + MOTEUR_NBImpulsionsD = MOTEUR_LireEncodeursDroit(); + + deltaG = MOTEUR_ConsigneMoteurG - MOTEUR_NBImpulsionsG; + deltaD = MOTEUR_ConsigneMoteurD - MOTEUR_NBImpulsionsD; + + if (((MOTEUR_ConsigneMoteurD ==0) && (MOTEUR_ConsigneMoteurG ==0)) && + ((deltaD==0) && (deltaG==0))) MOTEURS_DesactiveAlim(); + else MOTEURS_ActiveAlim(); + + if (deltaG !=0) { + MOTEUR_CmdMoteurG = MOTEUR_CmdMoteurG + MOTEUR_Kp*deltaG; + if (MOTEUR_ConsigneMoteurG>=0) { + if (MOTEUR_CmdMoteurG>255) MOTEUR_CmdMoteurG=255; + if (MOTEUR_CmdMoteurG<0) MOTEUR_CmdMoteurG=0; + } else { + if (MOTEUR_CmdMoteurG>0) MOTEUR_CmdMoteurG=0; + if (MOTEUR_CmdMoteurG<-255) MOTEUR_CmdMoteurG=-255; + } + + MOTEURS_Set(MOTEUR_GAUCHE, MOTEUR_CmdMoteurG); + } + + if (deltaD !=0) { + MOTEUR_CmdMoteurD = MOTEUR_CmdMoteurD + MOTEUR_Kp*deltaD; + if (MOTEUR_ConsigneMoteurD>=0) { + if (MOTEUR_CmdMoteurD>255) MOTEUR_CmdMoteurD=255; + if (MOTEUR_CmdMoteurD<0) MOTEUR_CmdMoteurD=0; + } else { + if (MOTEUR_CmdMoteurD>0) MOTEUR_CmdMoteurD=0; + if (MOTEUR_CmdMoteurD<-255) MOTEUR_CmdMoteurD=-255; + } + + MOTEURS_Set(MOTEUR_DROIT, MOTEUR_CmdMoteurD); + } + } +} diff --git a/software/dumber3/Core/Src/sequenceur.c b/software/dumber3/Core/Src/sequenceur.c new file mode 100644 index 0000000..18902e4 --- /dev/null +++ b/software/dumber3/Core/Src/sequenceur.c @@ -0,0 +1,8 @@ +/* + * statemachine.c + * + * Created on: Sep 12, 2022 + * Author: dimercur + */ + + diff --git a/software/dumber3/Core/Src/xbee.c b/software/dumber3/Core/Src/xbee.c new file mode 100644 index 0000000..3ac50a4 --- /dev/null +++ b/software/dumber3/Core/Src/xbee.c @@ -0,0 +1,8 @@ +/* + * xbee.c + * + * Created on: Sep 12, 2022 + * Author: dimercur + */ + + diff --git a/software/dumber3/Debug/Core/Src/batterie.su b/software/dumber3/Debug/Core/Src/batterie.su new file mode 100644 index 0000000..e69de29 diff --git a/software/dumber3/Debug/Core/Src/freertos.su b/software/dumber3/Debug/Core/Src/freertos.su new file mode 100644 index 0000000..b383c15 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/freertos.su @@ -0,0 +1,2 @@ +freertos.c:57:13:PreSleepProcessing 16 static +freertos.c:62:13:PostSleepProcessing 16 static diff --git a/software/dumber3/Debug/Core/Src/leds.su b/software/dumber3/Debug/Core/Src/leds.su new file mode 100644 index 0000000..4e62631 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/leds.su @@ -0,0 +1,3 @@ +leds.c:30:6:LEDS_Init 24 static +leds.c:51:6:LEDS_RegleAnimation 16 static +leds.c:55:6:LEDS_AnimationThread 40 static diff --git a/software/dumber3/Debug/Core/Src/main.su b/software/dumber3/Debug/Core/Src/main.su new file mode 100644 index 0000000..e294325 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/main.su @@ -0,0 +1,12 @@ +main.c:97:5:main 8 static +main.c:188:6:SystemClock_Config 112 static +main.c:239:13:MX_ADC_Init 16 static +main.c:293:13:MX_LPTIM1_Init 8 static +main.c:327:13:MX_LPUART1_UART_Init 8 static +main.c:361:13:MX_TIM2_Init 48 static +main.c:432:13:MX_TIM21_Init 64 static +main.c:479:13:MX_DMA_Init 16 static +main.c:497:13:MX_GPIO_Init 48 static +main.c:545:12:msToTicks 24 static +main.c:567:6:StartDefaultTask 32 static +main.c:590:6:Error_Handler 8 static,ignoring_inline_asm diff --git a/software/dumber3/Debug/Core/Src/messages.su b/software/dumber3/Debug/Core/Src/messages.su new file mode 100644 index 0000000..0ee776e --- /dev/null +++ b/software/dumber3/Debug/Core/Src/messages.su @@ -0,0 +1,4 @@ +messages.c:19:7:MESSAGE_Init 8 static +messages.c:27:17:MESSAGE_ReadMailbox 40 static +messages.c:42:17:MESSAGE_ReadMailboxNoDelay 40 static +messages.c:51:6:MESSAGE_SendMailbox 40 static diff --git a/software/dumber3/Debug/Core/Src/moteurs.su b/software/dumber3/Debug/Core/Src/moteurs.su new file mode 100644 index 0000000..f0b7147 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/moteurs.su @@ -0,0 +1,8 @@ +moteurs.c:43:6:MOTEURS_DesactiveAlim 8 static +moteurs.c:51:6:MOTEURS_ActiveAlim 8 static +moteurs.c:59:15:MOTEURS_EtatAlim 8 static +moteurs.c:63:9:MOTEUR_LireEncodeursGauche 16 static +moteurs.c:80:9:MOTEUR_LireEncodeursDroit 16 static +moteurs.c:102:6:MOTEURS_Init 8 static +moteurs.c:137:6:MOTEURS_Set 24 static +moteurs.c:170:6:MOTEURS_Test 16 static diff --git a/software/dumber3/Debug/Core/Src/sequenceur.su b/software/dumber3/Debug/Core/Src/sequenceur.su new file mode 100644 index 0000000..e69de29 diff --git a/software/dumber3/Debug/Core/Src/statemachine.su b/software/dumber3/Debug/Core/Src/statemachine.su new file mode 100644 index 0000000..e69de29 diff --git a/software/dumber3/Debug/Core/Src/stm32l0xx_hal_msp.su b/software/dumber3/Debug/Core/Src/stm32l0xx_hal_msp.su new file mode 100644 index 0000000..a0d2174 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/stm32l0xx_hal_msp.su @@ -0,0 +1,12 @@ +stm32l0xx_hal_msp.c:69:6:HAL_MspInit 8 static +stm32l0xx_hal_msp.c:93:6:HAL_ADC_MspInit 48 static +stm32l0xx_hal_msp.c:129:6:HAL_ADC_MspDeInit 16 static +stm32l0xx_hal_msp.c:159:6:HAL_LPTIM_MspInit 56 static +stm32l0xx_hal_msp.c:203:6:HAL_LPTIM_MspDeInit 16 static +stm32l0xx_hal_msp.c:234:6:HAL_UART_MspInit 48 static +stm32l0xx_hal_msp.c:308:6:HAL_UART_MspDeInit 16 static +stm32l0xx_hal_msp.c:343:6:HAL_TIM_Base_MspInit 16 static +stm32l0xx_hal_msp.c:365:6:HAL_TIM_Encoder_MspInit 48 static +stm32l0xx_hal_msp.c:395:6:HAL_TIM_MspPostInit 56 static +stm32l0xx_hal_msp.c:445:6:HAL_TIM_Base_MspDeInit 16 static +stm32l0xx_hal_msp.c:467:6:HAL_TIM_Encoder_MspDeInit 16 static diff --git a/software/dumber3/Debug/Core/Src/stm32l0xx_it.su b/software/dumber3/Debug/Core/Src/stm32l0xx_it.su new file mode 100644 index 0000000..764b6f0 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/stm32l0xx_it.su @@ -0,0 +1,7 @@ +stm32l0xx_it.c:75:6:NMI_Handler 8 static +stm32l0xx_it.c:90:6:HardFault_Handler 8 static +stm32l0xx_it.c:105:6:SysTick_Handler 8 static +stm32l0xx_it.c:134:6:EXTI2_3_IRQHandler 8 static +stm32l0xx_it.c:148:6:DMA1_Channel2_3_IRQHandler 8 static +stm32l0xx_it.c:163:6:ADC1_IRQHandler 8 static +stm32l0xx_it.c:177:6:LPUART1_IRQHandler 8 static diff --git a/software/dumber3/Debug/Core/Src/subdir.mk b/software/dumber3/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..09c74b8 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/subdir.mk @@ -0,0 +1,56 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/batterie.c \ +../Core/Src/freertos.c \ +../Core/Src/leds.c \ +../Core/Src/main.c \ +../Core/Src/messages.c \ +../Core/Src/moteurs.c \ +../Core/Src/sequenceur.c \ +../Core/Src/stm32l0xx_hal_msp.c \ +../Core/Src/stm32l0xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32l0xx.c \ +../Core/Src/xbee.c + +OBJS += \ +./Core/Src/batterie.o \ +./Core/Src/freertos.o \ +./Core/Src/leds.o \ +./Core/Src/main.o \ +./Core/Src/messages.o \ +./Core/Src/moteurs.o \ +./Core/Src/sequenceur.o \ +./Core/Src/stm32l0xx_hal_msp.o \ +./Core/Src/stm32l0xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32l0xx.o \ +./Core/Src/xbee.o + +C_DEPS += \ +./Core/Src/batterie.d \ +./Core/Src/freertos.d \ +./Core/Src/leds.d \ +./Core/Src/main.d \ +./Core/Src/messages.d \ +./Core/Src/moteurs.d \ +./Core/Src/sequenceur.d \ +./Core/Src/stm32l0xx_hal_msp.d \ +./Core/Src/stm32l0xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32l0xx.d \ +./Core/Src/xbee.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/software/dumber3/Debug/Core/Src/syscalls.su b/software/dumber3/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..2661431 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +syscalls.c:45:6:initialise_monitor_handles 8 static +syscalls.c:49:5:_getpid 8 static +syscalls.c:54:5:_kill 16 static +syscalls.c:60:6:_exit 16 static +syscalls.c:66:27:_read 32 static +syscalls.c:78:27:_write 32 static +syscalls.c:89:5:_close 16 static +syscalls.c:95:5:_fstat 16 static +syscalls.c:101:5:_isatty 16 static +syscalls.c:106:5:_lseek 24 static +syscalls.c:111:5:_open 20 static +syscalls.c:117:5:_wait 16 static +syscalls.c:123:5:_unlink 16 static +syscalls.c:129:5:_times 16 static +syscalls.c:134:5:_stat 16 static +syscalls.c:140:5:_link 16 static +syscalls.c:146:5:_fork 8 static +syscalls.c:152:5:_execve 24 static diff --git a/software/dumber3/Debug/Core/Src/sysmem.su b/software/dumber3/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..4474c68 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +sysmem.c:54:7:_sbrk 32 static diff --git a/software/dumber3/Debug/Core/Src/system_stm32l0xx.su b/software/dumber3/Debug/Core/Src/system_stm32l0xx.su new file mode 100644 index 0000000..abf8ac4 --- /dev/null +++ b/software/dumber3/Debug/Core/Src/system_stm32l0xx.su @@ -0,0 +1,2 @@ +system_stm32l0xx.c:154:6:SystemInit 8 static +system_stm32l0xx.c:200:6:SystemCoreClockUpdate 32 static diff --git a/software/dumber3/Debug/Core/Src/xbee.su b/software/dumber3/Debug/Core/Src/xbee.su new file mode 100644 index 0000000..e69de29 diff --git a/software/dumber3/Debug/Core/Startup/subdir.mk b/software/dumber3/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..8294105 --- /dev/null +++ b/software/dumber3/Debug/Core/Startup/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32l010c6tx.s + +OBJS += \ +./Core/Startup/startup_stm32l010c6tx.o + +S_DEPS += \ +./Core/Startup/startup_stm32l010c6tx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m0plus -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su new file mode 100644 index 0000000..585fd26 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su @@ -0,0 +1,31 @@ +stm32l0xx_hal.c:140:19:HAL_Init 16 static +stm32l0xx_hal.c:178:19:HAL_DeInit 8 static +stm32l0xx_hal.c:204:13:HAL_MspInit 8 static +stm32l0xx_hal.c:215:13:HAL_MspDeInit 8 static +stm32l0xx_hal.c:238:26:HAL_InitTick 24 static +stm32l0xx_hal.c:294:13:HAL_IncTick 8 static +stm32l0xx_hal.c:305:17:HAL_GetTick 8 static +stm32l0xx_hal.c:314:10:HAL_GetTickPrio 8 static +stm32l0xx_hal.c:323:19:HAL_SetTickFreq 40 static +stm32l0xx_hal.c:355:21:HAL_GetTickFreq 8 static +stm32l0xx_hal.c:371:13:HAL_Delay 24 static +stm32l0xx_hal.c:397:13:HAL_SuspendTick 8 static +stm32l0xx_hal.c:413:13:HAL_ResumeTick 8 static +stm32l0xx_hal.c:423:10:HAL_GetHalVersion 8 static +stm32l0xx_hal.c:432:10:HAL_GetREVID 8 static +stm32l0xx_hal.c:441:10:HAL_GetDEVID 8 static +stm32l0xx_hal.c:450:10:HAL_GetUIDw0 8 static +stm32l0xx_hal.c:459:10:HAL_GetUIDw1 8 static +stm32l0xx_hal.c:468:10:HAL_GetUIDw2 8 static +stm32l0xx_hal.c:497:6:HAL_DBGMCU_EnableDBGSleepMode 8 static +stm32l0xx_hal.c:506:6:HAL_DBGMCU_DisableDBGSleepMode 8 static +stm32l0xx_hal.c:515:6:HAL_DBGMCU_EnableDBGStopMode 8 static +stm32l0xx_hal.c:524:6:HAL_DBGMCU_DisableDBGStopMode 8 static +stm32l0xx_hal.c:533:6:HAL_DBGMCU_EnableDBGStandbyMode 8 static +stm32l0xx_hal.c:542:6:HAL_DBGMCU_DisableDBGStandbyMode 8 static +stm32l0xx_hal.c:556:6:HAL_DBGMCU_DBG_EnableLowPowerConfig 16 static +stm32l0xx_hal.c:573:6:HAL_DBGMCU_DBG_DisableLowPowerConfig 16 static +stm32l0xx_hal.c:610:11:HAL_SYSCFG_GetBootMode 8 static +stm32l0xx_hal.c:627:6:HAL_SYSCFG_VREFINT_OutputSelect 16 static +stm32l0xx_hal.c:641:6:HAL_SYSCFG_Enable_Lock_VREFINT 8 static +stm32l0xx_hal.c:651:6:HAL_SYSCFG_Disable_Lock_VREFINT 8 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.su new file mode 100644 index 0000000..87b0f03 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.su @@ -0,0 +1,29 @@ +stm32l0xx_hal_adc.c:402:19:HAL_ADC_Init 16 static +stm32l0xx_hal_adc.c:648:19:HAL_ADC_DeInit 32 static +stm32l0xx_hal_adc.c:779:13:HAL_ADC_MspInit 16 static +stm32l0xx_hal_adc.c:794:13:HAL_ADC_MspDeInit 16 static +stm32l0xx_hal_adc.c:1032:19:HAL_ADC_Start 32 static +stm32l0xx_hal_adc.c:1098:19:HAL_ADC_Stop 32 static +stm32l0xx_hal_adc.c:1152:19:HAL_ADC_PollForConversion 24 static +stm32l0xx_hal_adc.c:1282:19:HAL_ADC_PollForEvent 32 static +stm32l0xx_hal_adc.c:1369:19:HAL_ADC_Start_IT 32 static +stm32l0xx_hal_adc.c:1450:19:HAL_ADC_Stop_IT 32 static +stm32l0xx_hal_adc.c:1500:19:HAL_ADC_Start_DMA 40 static +stm32l0xx_hal_adc.c:1590:19:HAL_ADC_Stop_DMA 32 static +stm32l0xx_hal_adc.c:1675:10:HAL_ADC_GetValue 16 static +stm32l0xx_hal_adc.c:1692:6:HAL_ADC_IRQHandler 16 static +stm32l0xx_hal_adc.c:1823:13:HAL_ADC_ConvCpltCallback 16 static +stm32l0xx_hal_adc.c:1838:13:HAL_ADC_ConvHalfCpltCallback 16 static +stm32l0xx_hal_adc.c:1853:13:HAL_ADC_LevelOutOfWindowCallback 16 static +stm32l0xx_hal_adc.c:1875:13:HAL_ADC_ErrorCallback 16 static +stm32l0xx_hal_adc.c:1926:19:HAL_ADC_ConfigChannel 16 static +stm32l0xx_hal_adc.c:2045:19:HAL_ADC_AnalogWDGConfig 32 static +stm32l0xx_hal_adc.c:2162:10:HAL_ADC_GetState 16 static +stm32l0xx_hal_adc.c:2176:10:HAL_ADC_GetError 16 static +stm32l0xx_hal_adc.c:2209:26:ADC_Enable 24 static +stm32l0xx_hal_adc.c:2271:26:ADC_Disable 24 static +stm32l0xx_hal_adc.c:2332:26:ADC_ConversionStop 24 static +stm32l0xx_hal_adc.c:2386:13:ADC_DMAConvCplt 24 static +stm32l0xx_hal_adc.c:2450:13:ADC_DMAHalfConvCplt 24 static +stm32l0xx_hal_adc.c:2468:13:ADC_DMAError 24 static +stm32l0xx_hal_adc.c:2492:13:ADC_DelayMicroSecond 24 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.su new file mode 100644 index 0000000..54b5cd8 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.su @@ -0,0 +1,7 @@ +stm32l0xx_hal_adc_ex.c:107:19:HAL_ADCEx_Calibration_Start 32 static +stm32l0xx_hal_adc_ex.c:192:10:HAL_ADCEx_Calibration_GetValue 16 static +stm32l0xx_hal_adc_ex.c:211:19:HAL_ADCEx_Calibration_SetValue 32 static +stm32l0xx_hal_adc_ex.c:259:19:HAL_ADCEx_EnableVREFINT 16 static +stm32l0xx_hal_adc_ex.c:291:6:HAL_ADCEx_DisableVREFINT 8 static +stm32l0xx_hal_adc_ex.c:306:19:HAL_ADCEx_EnableVREFINTTempSensor 16 static +stm32l0xx_hal_adc_ex.c:338:6:HAL_ADCEx_DisableVREFINTTempSensor 8 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su new file mode 100644 index 0000000..111a14b --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su @@ -0,0 +1,21 @@ +core_cm0plus.h:741:22:__NVIC_EnableIRQ 16 static +core_cm0plus.h:777:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +core_cm0plus.h:796:26:__NVIC_GetPendingIRQ 16 static +core_cm0plus.h:815:22:__NVIC_SetPendingIRQ 16 static +core_cm0plus.h:830:22:__NVIC_ClearPendingIRQ 16 static +core_cm0plus.h:848:22:__NVIC_SetPriority 24 static +core_cm0plus.h:872:26:__NVIC_GetPriority 16 static +core_cm0plus.h:983:34:__NVIC_SystemReset 8 static,ignoring_inline_asm +core_cm0plus.h:1054:26:SysTick_Config 16 static +stm32l0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority 24 static +stm32l0xx_hal_cortex.c:148:6:HAL_NVIC_EnableIRQ 16 static +stm32l0xx_hal_cortex.c:164:6:HAL_NVIC_DisableIRQ 16 static +stm32l0xx_hal_cortex.c:177:6:HAL_NVIC_SystemReset 8 static +stm32l0xx_hal_cortex.c:190:10:HAL_SYSTICK_Config 16 static +stm32l0xx_hal_cortex.c:222:10:HAL_NVIC_GetPriority 16 static +stm32l0xx_hal_cortex.c:235:6:HAL_NVIC_SetPendingIRQ 16 static +stm32l0xx_hal_cortex.c:250:10:HAL_NVIC_GetPendingIRQ 16 static +stm32l0xx_hal_cortex.c:263:6:HAL_NVIC_ClearPendingIRQ 16 static +stm32l0xx_hal_cortex.c:278:6:HAL_SYSTICK_CLKSourceConfig 16 static +stm32l0xx_hal_cortex.c:296:6:HAL_SYSTICK_IRQHandler 8 static +stm32l0xx_hal_cortex.c:305:13:HAL_SYSTICK_Callback 8 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su new file mode 100644 index 0000000..498911c --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su @@ -0,0 +1,13 @@ +stm32l0xx_hal_dma.c:139:19:HAL_DMA_Init 24 static +stm32l0xx_hal_dma.c:214:19:HAL_DMA_DeInit 16 static +stm32l0xx_hal_dma.c:294:19:HAL_DMA_Start 32 static +stm32l0xx_hal_dma.c:337:19:HAL_DMA_Start_IT 32 static +stm32l0xx_hal_dma.c:392:19:HAL_DMA_Abort 24 static +stm32l0xx_hal_dma.c:433:19:HAL_DMA_Abort_IT 24 static +stm32l0xx_hal_dma.c:478:19:HAL_DMA_PollForTransfer 32 static +stm32l0xx_hal_dma.c:579:6:HAL_DMA_IRQHandler 24 static +stm32l0xx_hal_dma.c:673:19:HAL_DMA_RegisterCallback 32 static +stm32l0xx_hal_dma.c:724:19:HAL_DMA_UnRegisterCallback 24 static +stm32l0xx_hal_dma.c:802:22:HAL_DMA_GetState 16 static +stm32l0xx_hal_dma.c:814:10:HAL_DMA_GetError 16 static +stm32l0xx_hal_dma.c:840:13:DMA_SetConfig 24 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su new file mode 100644 index 0000000..e2e6501 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su @@ -0,0 +1,9 @@ +stm32l0xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 32 static +stm32l0xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine 32 static +stm32l0xx_hal_exti.c:317:19:HAL_EXTI_ClearConfigLine 32 static +stm32l0xx_hal_exti.c:370:19:HAL_EXTI_RegisterCallback 32 static +stm32l0xx_hal_exti.c:395:19:HAL_EXTI_GetHandle 16 static +stm32l0xx_hal_exti.c:435:6:HAL_EXTI_IRQHandler 24 static +stm32l0xx_hal_exti.c:467:10:HAL_EXTI_GetPending 32 static +stm32l0xx_hal_exti.c:496:6:HAL_EXTI_ClearPending 24 static +stm32l0xx_hal_exti.c:517:6:HAL_EXTI_GenerateSWI 24 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su new file mode 100644 index 0000000..a580d01 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su @@ -0,0 +1,13 @@ +stm32l0xx_hal_flash.c:231:19:HAL_FLASH_Program 40 static +stm32l0xx_hal_flash.c:273:19:HAL_FLASH_Program_IT 32 static +stm32l0xx_hal_flash.c:304:6:HAL_FLASH_IRQHandler 16 static +stm32l0xx_hal_flash.c:428:13:HAL_FLASH_EndOfOperationCallback 16 static +stm32l0xx_hal_flash.c:445:13:HAL_FLASH_OperationErrorCallback 16 static +stm32l0xx_hal_flash.c:478:19:HAL_FLASH_Unlock 32 static,ignoring_inline_asm +stm32l0xx_hal_flash.c:527:19:HAL_FLASH_Lock 8 static +stm32l0xx_hal_flash.c:542:19:HAL_FLASH_OB_Unlock 24 static,ignoring_inline_asm +stm32l0xx_hal_flash.c:579:19:HAL_FLASH_OB_Lock 8 static +stm32l0xx_hal_flash.c:592:19:HAL_FLASH_OB_Launch 8 static +stm32l0xx_hal_flash.c:624:10:HAL_FLASH_GetError 8 static +stm32l0xx_hal_flash.c:646:19:FLASH_WaitForLastOperation 24 static +stm32l0xx_hal_flash.c:703:13:FLASH_SetErrorCode 16 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su new file mode 100644 index 0000000..8a09913 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su @@ -0,0 +1,25 @@ +stm32l0xx_hal_flash_ex.c:171:19:HAL_FLASHEx_Erase 32 static +stm32l0xx_hal_flash_ex.c:235:19:HAL_FLASHEx_Erase_IT 32 static +stm32l0xx_hal_flash_ex.c:327:19:HAL_FLASHEx_OBProgram 32 static +stm32l0xx_hal_flash_ex.c:410:6:HAL_FLASHEx_OBGetConfig 16 static +stm32l0xx_hal_flash_ex.c:443:19:HAL_FLASHEx_AdvOBProgram 32 static +stm32l0xx_hal_flash_ex.c:486:6:HAL_FLASHEx_AdvOBGetConfig 16 static +stm32l0xx_hal_flash_ex.c:526:19:HAL_FLASHEx_OB_SelectPCROP 40 static +stm32l0xx_hal_flash_ex.c:568:19:HAL_FLASHEx_OB_DeSelectPCROP 40 static +stm32l0xx_hal_flash_ex.c:634:19:HAL_FLASHEx_DATAEEPROM_Unlock 24 static,ignoring_inline_asm +stm32l0xx_hal_flash_ex.c:664:19:HAL_FLASHEx_DATAEEPROM_Lock 8 static +stm32l0xx_hal_flash_ex.c:682:19:HAL_FLASHEx_DATAEEPROM_Erase 32 static +stm32l0xx_hal_flash_ex.c:724:21:HAL_FLASHEx_DATAEEPROM_Program 40 static +stm32l0xx_hal_flash_ex.c:780:6:HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram 8 static +stm32l0xx_hal_flash_ex.c:789:6:HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram 8 static +stm32l0xx_hal_flash_ex.c:825:26:FLASH_OB_RDPConfig 40 static +stm32l0xx_hal_flash_ex.c:876:26:FLASH_OB_BORConfig 40 static +stm32l0xx_hal_flash_ex.c:918:27:FLASH_OB_BOOTBit1Config 40 static +stm32l0xx_hal_flash_ex.c:953:16:FLASH_OB_GetUser 8 static +stm32l0xx_hal_flash_ex.c:967:16:FLASH_OB_GetRDP 16 static +stm32l0xx_hal_flash_ex.c:985:16:FLASH_OB_GetBOR 8 static +stm32l0xx_hal_flash_ex.c:995:16:FLASH_OB_GetBOOTBit1 8 static +stm32l0xx_hal_flash_ex.c:1006:17:FLASH_OB_GetWRP 8 static +stm32l0xx_hal_flash_ex.c:1046:26:FLASH_OB_ProtectedSectorsConfig 40 static +stm32l0xx_hal_flash_ex.c:1140:26:FLASH_OB_UserConfig 40 static +stm32l0xx_hal_flash_ex.c:1246:6:FLASH_PageErase 16 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su new file mode 100644 index 0000000..acd0979 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su @@ -0,0 +1,6 @@ +stm32l0xx_hal_flash_ramfunc.c:115:30:HAL_FLASHEx_EnableRunPowerDown 8 static +stm32l0xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_DisableRunPowerDown 8 static +stm32l0xx_hal_flash_ramfunc.c:305:30:HAL_FLASHEx_HalfPageProgram 32 static,ignoring_inline_asm +stm32l0xx_hal_flash_ramfunc.c:376:30:HAL_FLASHEx_GetError 16 static +stm32l0xx_hal_flash_ramfunc.c:458:37:FLASHRAM_WaitForLastOperation 16 static +stm32l0xx_hal_flash_ramfunc.c:398:37:FLASHRAM_SetErrorCode 16 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su new file mode 100644 index 0000000..14262a9 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su @@ -0,0 +1,8 @@ +stm32l0xx_hal_gpio.c:156:6:HAL_GPIO_Init 32 static +stm32l0xx_hal_gpio.c:286:6:HAL_GPIO_DeInit 32 static +stm32l0xx_hal_gpio.c:367:15:HAL_GPIO_ReadPin 24 static +stm32l0xx_hal_gpio.c:403:6:HAL_GPIO_WritePin 16 static +stm32l0xx_hal_gpio.c:427:6:HAL_GPIO_TogglePin 24 static +stm32l0xx_hal_gpio.c:454:19:HAL_GPIO_LockPin 24 static +stm32l0xx_hal_gpio.c:487:6:HAL_GPIO_EXTI_IRQHandler 16 static +stm32l0xx_hal_gpio.c:502:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su new file mode 100644 index 0000000..b7d0802 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su @@ -0,0 +1,79 @@ +stm32l0xx_hal_i2c.c:522:19:HAL_I2C_Init 16 static +stm32l0xx_hal_i2c.c:632:19:HAL_I2C_DeInit 16 static +stm32l0xx_hal_i2c.c:678:13:HAL_I2C_MspInit 16 static +stm32l0xx_hal_i2c.c:694:13:HAL_I2C_MspDeInit 16 static +stm32l0xx_hal_i2c.c:1115:19:HAL_I2C_Master_Transmit 48 static +stm32l0xx_hal_i2c.c:1234:19:HAL_I2C_Master_Receive 48 static +stm32l0xx_hal_i2c.c:1352:19:HAL_I2C_Slave_Transmit 40 static +stm32l0xx_hal_i2c.c:1490:19:HAL_I2C_Slave_Receive 40 static +stm32l0xx_hal_i2c.c:1617:19:HAL_I2C_Master_Transmit_IT 48 static +stm32l0xx_hal_i2c.c:1688:19:HAL_I2C_Master_Receive_IT 48 static +stm32l0xx_hal_i2c.c:1757:19:HAL_I2C_Slave_Transmit_IT 24 static +stm32l0xx_hal_i2c.c:1807:19:HAL_I2C_Slave_Receive_IT 24 static +stm32l0xx_hal_i2c.c:1859:19:HAL_I2C_Master_Transmit_DMA 48 static +stm32l0xx_hal_i2c.c:2006:19:HAL_I2C_Master_Receive_DMA 48 static +stm32l0xx_hal_i2c.c:2151:19:HAL_I2C_Slave_Transmit_DMA 40 static +stm32l0xx_hal_i2c.c:2255:19:HAL_I2C_Slave_Receive_DMA 40 static +stm32l0xx_hal_i2c.c:2363:19:HAL_I2C_Mem_Write 48 static +stm32l0xx_hal_i2c.c:2500:19:HAL_I2C_Mem_Read 48 static +stm32l0xx_hal_i2c.c:2637:19:HAL_I2C_Mem_Write_IT 48 static +stm32l0xx_hal_i2c.c:2731:19:HAL_I2C_Mem_Read_IT 48 static +stm32l0xx_hal_i2c.c:2823:19:HAL_I2C_Mem_Write_DMA 56 static +stm32l0xx_hal_i2c.c:2970:19:HAL_I2C_Mem_Read_DMA 56 static +stm32l0xx_hal_i2c.c:3113:19:HAL_I2C_IsDeviceReady 48 static +stm32l0xx_hal_i2c.c:3255:19:HAL_I2C_Master_Seq_Transmit_IT 48 static +stm32l0xx_hal_i2c.c:3342:19:HAL_I2C_Master_Seq_Transmit_DMA 56 static +stm32l0xx_hal_i2c.c:3510:19:HAL_I2C_Master_Seq_Receive_IT 48 static +stm32l0xx_hal_i2c.c:3597:19:HAL_I2C_Master_Seq_Receive_DMA 56 static +stm32l0xx_hal_i2c.c:3763:19:HAL_I2C_Slave_Seq_Transmit_IT 24 static +stm32l0xx_hal_i2c.c:3859:19:HAL_I2C_Slave_Seq_Transmit_DMA 40 static +stm32l0xx_hal_i2c.c:4040:19:HAL_I2C_Slave_Seq_Receive_IT 24 static +stm32l0xx_hal_i2c.c:4136:19:HAL_I2C_Slave_Seq_Receive_DMA 40 static +stm32l0xx_hal_i2c.c:4313:19:HAL_I2C_EnableListen_IT 16 static +stm32l0xx_hal_i2c.c:4337:19:HAL_I2C_DisableListen_IT 24 static +stm32l0xx_hal_i2c.c:4370:19:HAL_I2C_Master_Abort_IT 24 static +stm32l0xx_hal_i2c.c:4432:6:HAL_I2C_EV_IRQHandler 24 static +stm32l0xx_hal_i2c.c:4451:6:HAL_I2C_ER_IRQHandler 32 static +stm32l0xx_hal_i2c.c:4503:13:HAL_I2C_MasterTxCpltCallback 16 static +stm32l0xx_hal_i2c.c:4519:13:HAL_I2C_MasterRxCpltCallback 16 static +stm32l0xx_hal_i2c.c:4534:13:HAL_I2C_SlaveTxCpltCallback 16 static +stm32l0xx_hal_i2c.c:4550:13:HAL_I2C_SlaveRxCpltCallback 16 static +stm32l0xx_hal_i2c.c:4568:13:HAL_I2C_AddrCallback 16 static +stm32l0xx_hal_i2c.c:4586:13:HAL_I2C_ListenCpltCallback 16 static +stm32l0xx_hal_i2c.c:4602:13:HAL_I2C_MemTxCpltCallback 16 static +stm32l0xx_hal_i2c.c:4618:13:HAL_I2C_MemRxCpltCallback 16 static +stm32l0xx_hal_i2c.c:4634:13:HAL_I2C_ErrorCallback 16 static +stm32l0xx_hal_i2c.c:4650:13:HAL_I2C_AbortCpltCallback 16 static +stm32l0xx_hal_i2c.c:4685:22:HAL_I2C_GetState 16 static +stm32l0xx_hal_i2c.c:4697:21:HAL_I2C_GetMode 16 static +stm32l0xx_hal_i2c.c:4708:10:HAL_I2C_GetError 16 static +stm32l0xx_hal_i2c.c:4733:26:I2C_Master_ISR_IT 48 static +stm32l0xx_hal_i2c.c:4879:26:I2C_Slave_ISR_IT 32 static +stm32l0xx_hal_i2c.c:5020:26:I2C_Master_ISR_DMA 48 static +stm32l0xx_hal_i2c.c:5160:26:I2C_Slave_ISR_DMA 40 static +stm32l0xx_hal_i2c.c:5305:26:I2C_RequestMemoryWrite 40 static +stm32l0xx_hal_i2c.c:5360:26:I2C_RequestMemoryRead 40 static +stm32l0xx_hal_i2c.c:5409:13:I2C_ITAddrCplt 32 static +stm32l0xx_hal_i2c.c:5504:13:I2C_ITMasterSeqCplt 16 static +stm32l0xx_hal_i2c.c:5557:13:I2C_ITSlaveSeqCplt 24 static +stm32l0xx_hal_i2c.c:5631:13:I2C_ITMasterCplt 32 static +stm32l0xx_hal_i2c.c:5774:13:I2C_ITSlaveCplt 32 static +stm32l0xx_hal_i2c.c:5933:13:I2C_ITListenCplt 16 static +stm32l0xx_hal_i2c.c:5984:13:I2C_ITError 24 static +stm32l0xx_hal_i2c.c:6096:13:I2C_TreatErrorCallback 16 static +stm32l0xx_hal_i2c.c:6134:13:I2C_Flush_TXDR 16 static +stm32l0xx_hal_i2c.c:6155:13:I2C_DMAMasterTransmitCplt 24 static +stm32l0xx_hal_i2c.c:6205:13:I2C_DMASlaveTransmitCplt 24 static +stm32l0xx_hal_i2c.c:6233:13:I2C_DMAMasterReceiveCplt 24 static +stm32l0xx_hal_i2c.c:6283:13:I2C_DMASlaveReceiveCplt 24 static +stm32l0xx_hal_i2c.c:6311:13:I2C_DMAError 24 static +stm32l0xx_hal_i2c.c:6329:13:I2C_DMAAbort 24 static +stm32l0xx_hal_i2c.c:6357:26:I2C_WaitOnFlagUntilTimeout 24 static +stm32l0xx_hal_i2c.c:6388:26:I2C_WaitOnTXISFlagUntilTimeout 24 static +stm32l0xx_hal_i2c.c:6426:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static +stm32l0xx_hal_i2c.c:6461:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static +stm32l0xx_hal_i2c.c:6525:26:I2C_IsAcknowledgeFailed 24 static +stm32l0xx_hal_i2c.c:6599:13:I2C_TransferConfig 32 static +stm32l0xx_hal_i2c.c:6624:13:I2C_Enable_IRQ 24 static +stm32l0xx_hal_i2c.c:6695:13:I2C_Disable_IRQ 24 static +stm32l0xx_hal_i2c.c:6758:13:I2C_ConvertOtherXferOptions 16 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su new file mode 100644 index 0000000..6c35e69 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su @@ -0,0 +1,4 @@ +stm32l0xx_hal_i2c_ex.c:97:19:HAL_I2CEx_ConfigAnalogFilter 16 static +stm32l0xx_hal_i2c_ex.c:141:19:HAL_I2CEx_ConfigDigitalFilter 24 static +stm32l0xx_hal_i2c_ex.c:209:19:HAL_I2CEx_EnableWakeUp 16 static +stm32l0xx_hal_i2c_ex.c:248:19:HAL_I2CEx_DisableWakeUp 16 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.su new file mode 100644 index 0000000..9567e89 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.su @@ -0,0 +1,42 @@ +stm32l0xx_hal_lptim.c:220:19:HAL_LPTIM_Init 24 static +stm32l0xx_hal_lptim.c:341:19:HAL_LPTIM_DeInit 16 static +stm32l0xx_hal_lptim.c:388:13:HAL_LPTIM_MspInit 16 static +stm32l0xx_hal_lptim.c:403:13:HAL_LPTIM_MspDeInit 16 static +stm32l0xx_hal_lptim.c:452:19:HAL_LPTIM_PWM_Start 24 static +stm32l0xx_hal_lptim.c:507:19:HAL_LPTIM_PWM_Stop 16 static +stm32l0xx_hal_lptim.c:539:19:HAL_LPTIM_PWM_Start_IT 24 static +stm32l0xx_hal_lptim.c:624:19:HAL_LPTIM_PWM_Stop_IT 16 static +stm32l0xx_hal_lptim.c:675:19:HAL_LPTIM_OnePulse_Start 24 static +stm32l0xx_hal_lptim.c:730:19:HAL_LPTIM_OnePulse_Stop 16 static +stm32l0xx_hal_lptim.c:762:19:HAL_LPTIM_OnePulse_Start_IT 24 static +stm32l0xx_hal_lptim.c:847:19:HAL_LPTIM_OnePulse_Stop_IT 16 static +stm32l0xx_hal_lptim.c:898:19:HAL_LPTIM_SetOnce_Start 24 static +stm32l0xx_hal_lptim.c:953:19:HAL_LPTIM_SetOnce_Stop 16 static +stm32l0xx_hal_lptim.c:985:19:HAL_LPTIM_SetOnce_Start_IT 24 static +stm32l0xx_hal_lptim.c:1070:19:HAL_LPTIM_SetOnce_Stop_IT 16 static +stm32l0xx_hal_lptim.c:1119:19:HAL_LPTIM_Encoder_Start 24 static +stm32l0xx_hal_lptim.c:1178:19:HAL_LPTIM_Encoder_Stop 16 static +stm32l0xx_hal_lptim.c:1211:19:HAL_LPTIM_Encoder_Start_IT 24 static +stm32l0xx_hal_lptim.c:1288:19:HAL_LPTIM_Encoder_Stop_IT 16 static +stm32l0xx_hal_lptim.c:1331:19:HAL_LPTIM_TimeOut_Start 24 static +stm32l0xx_hal_lptim.c:1386:19:HAL_LPTIM_TimeOut_Stop 16 static +stm32l0xx_hal_lptim.c:1423:19:HAL_LPTIM_TimeOut_Start_IT 24 static +stm32l0xx_hal_lptim.c:1495:19:HAL_LPTIM_TimeOut_Stop_IT 16 static +stm32l0xx_hal_lptim.c:1534:19:HAL_LPTIM_Counter_Start 16 static +stm32l0xx_hal_lptim.c:1583:19:HAL_LPTIM_Counter_Stop 16 static +stm32l0xx_hal_lptim.c:1613:19:HAL_LPTIM_Counter_Start_IT 16 static +stm32l0xx_hal_lptim.c:1682:19:HAL_LPTIM_Counter_Stop_IT 16 static +stm32l0xx_hal_lptim.c:1737:10:HAL_LPTIM_ReadCounter 16 static +stm32l0xx_hal_lptim.c:1750:10:HAL_LPTIM_ReadAutoReload 16 static +stm32l0xx_hal_lptim.c:1763:10:HAL_LPTIM_ReadCompare 16 static +stm32l0xx_hal_lptim.c:1802:6:HAL_LPTIM_IRQHandler 16 static +stm32l0xx_hal_lptim.c:1929:13:HAL_LPTIM_CompareMatchCallback 16 static +stm32l0xx_hal_lptim.c:1944:13:HAL_LPTIM_AutoReloadMatchCallback 16 static +stm32l0xx_hal_lptim.c:1959:13:HAL_LPTIM_TriggerCallback 16 static +stm32l0xx_hal_lptim.c:1974:13:HAL_LPTIM_CompareWriteCallback 16 static +stm32l0xx_hal_lptim.c:1989:13:HAL_LPTIM_AutoReloadWriteCallback 16 static +stm32l0xx_hal_lptim.c:2004:13:HAL_LPTIM_DirectionUpCallback 16 static +stm32l0xx_hal_lptim.c:2019:13:HAL_LPTIM_DirectionDownCallback 16 static +stm32l0xx_hal_lptim.c:2273:24:HAL_LPTIM_GetState 16 static +stm32l0xx_hal_lptim.c:2320:26:LPTIM_WaitForFlag 24 static +stm32l0xx_hal_lptim.c:2345:6:LPTIM_Disable 40 static,ignoring_inline_asm diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su new file mode 100644 index 0000000..d0d236e --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su @@ -0,0 +1,12 @@ +stm32l0xx_hal_pwr.c:80:6:HAL_PWR_DeInit 8 static +stm32l0xx_hal_pwr.c:327:6:HAL_PWR_EnableBkUpAccess 8 static +stm32l0xx_hal_pwr.c:340:6:HAL_PWR_DisableBkUpAccess 8 static +stm32l0xx_hal_pwr.c:425:6:HAL_PWR_EnableWakeUpPin 16 static +stm32l0xx_hal_pwr.c:442:6:HAL_PWR_DisableWakeUpPin 16 static +stm32l0xx_hal_pwr.c:465:6:HAL_PWR_EnterSLEEPMode 32 static,ignoring_inline_asm +stm32l0xx_hal_pwr.c:546:6:HAL_PWR_EnterSTOPMode 32 static,ignoring_inline_asm +stm32l0xx_hal_pwr.c:615:6:HAL_PWR_EnterSTANDBYMode 8 static,ignoring_inline_asm +stm32l0xx_hal_pwr.c:639:6:HAL_PWR_EnableSleepOnExit 8 static +stm32l0xx_hal_pwr.c:652:6:HAL_PWR_DisableSleepOnExit 8 static +stm32l0xx_hal_pwr.c:665:6:HAL_PWR_EnableSEVOnPend 8 static +stm32l0xx_hal_pwr.c:678:6:HAL_PWR_DisableSEVOnPend 8 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su new file mode 100644 index 0000000..fa2f762 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su @@ -0,0 +1,7 @@ +stm32l0xx_hal_pwr_ex.c:70:10:HAL_PWREx_GetVoltageRange 8 static +stm32l0xx_hal_pwr_ex.c:83:6:HAL_PWREx_EnableFastWakeUp 8 static +stm32l0xx_hal_pwr_ex.c:93:6:HAL_PWREx_DisableFastWakeUp 8 static +stm32l0xx_hal_pwr_ex.c:103:6:HAL_PWREx_EnableUltraLowPower 8 static +stm32l0xx_hal_pwr_ex.c:113:6:HAL_PWREx_DisableUltraLowPower 8 static +stm32l0xx_hal_pwr_ex.c:131:6:HAL_PWREx_EnableLowPowerRunMode 8 static +stm32l0xx_hal_pwr_ex.c:146:19:HAL_PWREx_DisableLowPowerRunMode 16 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su new file mode 100644 index 0000000..2c9153c --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su @@ -0,0 +1,13 @@ +stm32l0xx_hal_rcc.c:223:19:HAL_RCC_DeInit 32 static +stm32l0xx_hal_rcc.c:338:19:HAL_RCC_OscConfig 56 static +stm32l0xx_hal_rcc.c:859:19:HAL_RCC_ClockConfig 32 static +stm32l0xx_hal_rcc.c:1120:6:HAL_RCC_MCOConfig 64 static +stm32l0xx_hal_rcc.c:1177:6:HAL_RCC_EnableCSS 8 static +stm32l0xx_hal_rcc.c:1213:10:HAL_RCC_GetSysClockFreq 72 static +stm32l0xx_hal_rcc.c:1283:10:HAL_RCC_GetHCLKFreq 8 static +stm32l0xx_hal_rcc.c:1294:10:HAL_RCC_GetPCLK1Freq 8 static +stm32l0xx_hal_rcc.c:1306:10:HAL_RCC_GetPCLK2Freq 8 static +stm32l0xx_hal_rcc.c:1319:6:HAL_RCC_GetOscConfig 16 static +stm32l0xx_hal_rcc.c:1422:6:HAL_RCC_GetClockConfig 16 static +stm32l0xx_hal_rcc.c:1453:6:HAL_RCC_NMI_IRQHandler 8 static +stm32l0xx_hal_rcc.c:1470:13:HAL_RCC_CSSCallback 8 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su new file mode 100644 index 0000000..2dbe186 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su @@ -0,0 +1,8 @@ +stm32l0xx_hal_rcc_ex.c:97:19:HAL_RCCEx_PeriphCLKConfig 32 static +stm32l0xx_hal_rcc_ex.c:296:6:HAL_RCCEx_GetPeriphCLKConfig 24 static +stm32l0xx_hal_rcc_ex.c:374:10:HAL_RCCEx_GetPeriphCLKFreq 32 static +stm32l0xx_hal_rcc_ex.c:744:6:HAL_RCCEx_EnableLSECSS 8 static +stm32l0xx_hal_rcc_ex.c:756:6:HAL_RCCEx_DisableLSECSS 8 static +stm32l0xx_hal_rcc_ex.c:770:6:HAL_RCCEx_EnableLSECSS_IT 8 static +stm32l0xx_hal_rcc_ex.c:787:6:HAL_RCCEx_LSECSS_IRQHandler 8 static +stm32l0xx_hal_rcc_ex.c:804:13:HAL_RCCEx_LSECSS_Callback 8 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su new file mode 100644 index 0000000..786182c --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su @@ -0,0 +1,119 @@ +stm32l0xx_hal_tim.c:269:19:HAL_TIM_Base_Init 16 static +stm32l0xx_hal_tim.c:329:19:HAL_TIM_Base_DeInit 16 static +stm32l0xx_hal_tim.c:371:13:HAL_TIM_Base_MspInit 16 static +stm32l0xx_hal_tim.c:386:13:HAL_TIM_Base_MspDeInit 16 static +stm32l0xx_hal_tim.c:402:19:HAL_TIM_Base_Start 24 static +stm32l0xx_hal_tim.c:441:19:HAL_TIM_Base_Stop 16 static +stm32l0xx_hal_tim.c:461:19:HAL_TIM_Base_Start_IT 24 static +stm32l0xx_hal_tim.c:503:19:HAL_TIM_Base_Stop_IT 16 static +stm32l0xx_hal_tim.c:528:19:HAL_TIM_Base_Start_DMA 32 static +stm32l0xx_hal_tim.c:597:19:HAL_TIM_Base_Stop_DMA 16 static +stm32l0xx_hal_tim.c:652:19:HAL_TIM_OC_Init 16 static +stm32l0xx_hal_tim.c:712:19:HAL_TIM_OC_DeInit 16 static +stm32l0xx_hal_tim.c:754:13:HAL_TIM_OC_MspInit 16 static +stm32l0xx_hal_tim.c:769:13:HAL_TIM_OC_MspDeInit 16 static +stm32l0xx_hal_tim.c:790:19:HAL_TIM_OC_Start 24 static +stm32l0xx_hal_tim.c:838:19:HAL_TIM_OC_Stop 16 static +stm32l0xx_hal_tim.c:867:19:HAL_TIM_OC_Start_IT 24 static +stm32l0xx_hal_tim.c:954:19:HAL_TIM_OC_Stop_IT 24 static +stm32l0xx_hal_tim.c:1025:19:HAL_TIM_OC_Start_DMA 32 static +stm32l0xx_hal_tim.c:1182:19:HAL_TIM_OC_Stop_DMA 24 static +stm32l0xx_hal_tim.c:1279:19:HAL_TIM_PWM_Init 16 static +stm32l0xx_hal_tim.c:1339:19:HAL_TIM_PWM_DeInit 16 static +stm32l0xx_hal_tim.c:1381:13:HAL_TIM_PWM_MspInit 16 static +stm32l0xx_hal_tim.c:1396:13:HAL_TIM_PWM_MspDeInit 16 static +stm32l0xx_hal_tim.c:1417:19:HAL_TIM_PWM_Start 24 static +stm32l0xx_hal_tim.c:1465:19:HAL_TIM_PWM_Stop 16 static +stm32l0xx_hal_tim.c:1494:19:HAL_TIM_PWM_Start_IT 24 static +stm32l0xx_hal_tim.c:1581:19:HAL_TIM_PWM_Stop_IT 24 static +stm32l0xx_hal_tim.c:1652:19:HAL_TIM_PWM_Start_DMA 32 static +stm32l0xx_hal_tim.c:1808:19:HAL_TIM_PWM_Stop_DMA 24 static +stm32l0xx_hal_tim.c:1905:19:HAL_TIM_IC_Init 16 static +stm32l0xx_hal_tim.c:1965:19:HAL_TIM_IC_DeInit 16 static +stm32l0xx_hal_tim.c:2007:13:HAL_TIM_IC_MspInit 16 static +stm32l0xx_hal_tim.c:2022:13:HAL_TIM_IC_MspDeInit 16 static +stm32l0xx_hal_tim.c:2043:19:HAL_TIM_IC_Start 24 static +stm32l0xx_hal_tim.c:2092:19:HAL_TIM_IC_Stop 16 static +stm32l0xx_hal_tim.c:2121:19:HAL_TIM_IC_Start_IT 24 static +stm32l0xx_hal_tim.c:2210:19:HAL_TIM_IC_Stop_IT 24 static +stm32l0xx_hal_tim.c:2281:19:HAL_TIM_IC_Start_DMA 32 static +stm32l0xx_hal_tim.c:2436:19:HAL_TIM_IC_Stop_DMA 24 static +stm32l0xx_hal_tim.c:2540:19:HAL_TIM_OnePulse_Init 16 static +stm32l0xx_hal_tim.c:2608:19:HAL_TIM_OnePulse_DeInit 16 static +stm32l0xx_hal_tim.c:2651:13:HAL_TIM_OnePulse_MspInit 16 static +stm32l0xx_hal_tim.c:2666:13:HAL_TIM_OnePulse_MspDeInit 16 static +stm32l0xx_hal_tim.c:2686:19:HAL_TIM_OnePulse_Start 32 static +stm32l0xx_hal_tim.c:2731:19:HAL_TIM_OnePulse_Stop 16 static +stm32l0xx_hal_tim.c:2766:19:HAL_TIM_OnePulse_Start_IT 32 static +stm32l0xx_hal_tim.c:2817:19:HAL_TIM_OnePulse_Stop_IT 16 static +stm32l0xx_hal_tim.c:2888:19:HAL_TIM_Encoder_Init 32 static +stm32l0xx_hal_tim.c:3002:19:HAL_TIM_Encoder_DeInit 16 static +stm32l0xx_hal_tim.c:3045:13:HAL_TIM_Encoder_MspInit 16 static +stm32l0xx_hal_tim.c:3060:13:HAL_TIM_Encoder_MspDeInit 16 static +stm32l0xx_hal_tim.c:3080:19:HAL_TIM_Encoder_Start 24 static +stm32l0xx_hal_tim.c:3164:19:HAL_TIM_Encoder_Stop 16 static +stm32l0xx_hal_tim.c:3221:19:HAL_TIM_Encoder_Start_IT 24 static +stm32l0xx_hal_tim.c:3311:19:HAL_TIM_Encoder_Stop_IT 16 static +stm32l0xx_hal_tim.c:3373:19:HAL_TIM_Encoder_Start_DMA 32 static +stm32l0xx_hal_tim.c:3572:19:HAL_TIM_Encoder_Stop_DMA 16 static +stm32l0xx_hal_tim.c:3646:6:HAL_TIM_IRQHandler 16 static +stm32l0xx_hal_tim.c:3834:19:HAL_TIM_OC_ConfigChannel 32 static +stm32l0xx_hal_tim.c:3913:19:HAL_TIM_IC_ConfigChannel 32 static +stm32l0xx_hal_tim.c:4012:19:HAL_TIM_PWM_ConfigChannel 32 static +stm32l0xx_hal_tim.c:4126:19:HAL_TIM_OnePulse_ConfigChannel 48 static +stm32l0xx_hal_tim.c:4269:19:HAL_TIM_DMABurst_WriteStart 48 static +stm32l0xx_hal_tim.c:4321:19:HAL_TIM_DMABurst_MultiWriteStart 32 static +stm32l0xx_hal_tim.c:4487:19:HAL_TIM_DMABurst_WriteStop 24 static +stm32l0xx_hal_tim.c:4581:19:HAL_TIM_DMABurst_ReadStart 48 static +stm32l0xx_hal_tim.c:4632:19:HAL_TIM_DMABurst_MultiReadStart 32 static +stm32l0xx_hal_tim.c:4798:19:HAL_TIM_DMABurst_ReadStop 24 static +stm32l0xx_hal_tim.c:4871:19:HAL_TIM_GenerateEvent 16 static +stm32l0xx_hal_tim.c:4908:19:HAL_TIM_ConfigOCrefClear 32 static +stm32l0xx_hal_tim.c:5038:19:HAL_TIM_ConfigClockSource 24 static +stm32l0xx_hal_tim.c:5192:19:HAL_TIM_ConfigTI1Input 24 static +stm32l0xx_hal_tim.c:5224:19:HAL_TIM_SlaveConfigSynchro 16 static +stm32l0xx_hal_tim.c:5264:19:HAL_TIM_SlaveConfigSynchro_IT 16 static +stm32l0xx_hal_tim.c:5307:10:HAL_TIM_ReadCapturedValue 24 static +stm32l0xx_hal_tim.c:5391:13:HAL_TIM_PeriodElapsedCallback 16 static +stm32l0xx_hal_tim.c:5406:13:HAL_TIM_PeriodElapsedHalfCpltCallback 16 static +stm32l0xx_hal_tim.c:5421:13:HAL_TIM_OC_DelayElapsedCallback 16 static +stm32l0xx_hal_tim.c:5436:13:HAL_TIM_IC_CaptureCallback 16 static +stm32l0xx_hal_tim.c:5451:13:HAL_TIM_IC_CaptureHalfCpltCallback 16 static +stm32l0xx_hal_tim.c:5466:13:HAL_TIM_PWM_PulseFinishedCallback 16 static +stm32l0xx_hal_tim.c:5481:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 16 static +stm32l0xx_hal_tim.c:5496:13:HAL_TIM_TriggerCallback 16 static +stm32l0xx_hal_tim.c:5511:13:HAL_TIM_TriggerHalfCpltCallback 16 static +stm32l0xx_hal_tim.c:5526:13:HAL_TIM_ErrorCallback 16 static +stm32l0xx_hal_tim.c:6011:22:HAL_TIM_Base_GetState 16 static +stm32l0xx_hal_tim.c:6021:22:HAL_TIM_OC_GetState 16 static +stm32l0xx_hal_tim.c:6031:22:HAL_TIM_PWM_GetState 16 static +stm32l0xx_hal_tim.c:6041:22:HAL_TIM_IC_GetState 16 static +stm32l0xx_hal_tim.c:6051:22:HAL_TIM_OnePulse_GetState 16 static +stm32l0xx_hal_tim.c:6061:22:HAL_TIM_Encoder_GetState 16 static +stm32l0xx_hal_tim.c:6071:23:HAL_TIM_GetActiveChannel 16 static +stm32l0xx_hal_tim.c:6089:29:HAL_TIM_GetChannelState 24 static +stm32l0xx_hal_tim.c:6106:30:HAL_TIM_DMABurstState 16 static +stm32l0xx_hal_tim.c:6131:6:TIM_DMAError 24 static +stm32l0xx_hal_tim.c:6174:13:TIM_DMADelayPulseCplt 24 static +stm32l0xx_hal_tim.c:6233:13:TIM_DMADelayPulseHalfCplt 24 static +stm32l0xx_hal_tim.c:6272:6:TIM_DMACaptureCplt 24 static +stm32l0xx_hal_tim.c:6331:6:TIM_DMACaptureHalfCplt 24 static +stm32l0xx_hal_tim.c:6370:13:TIM_DMAPeriodElapsedCplt 24 static +stm32l0xx_hal_tim.c:6391:13:TIM_DMAPeriodElapsedHalfCplt 24 static +stm32l0xx_hal_tim.c:6407:13:TIM_DMATriggerCplt 24 static +stm32l0xx_hal_tim.c:6428:13:TIM_DMATriggerHalfCplt 24 static +stm32l0xx_hal_tim.c:6445:13:TIM_Base_SetConfig 24 static +stm32l0xx_hal_tim.c:6487:13:TIM_OC1_SetConfig 32 static +stm32l0xx_hal_tim.c:6534:13:TIM_OC2_SetConfig 32 static +stm32l0xx_hal_tim.c:6582:13:TIM_OC3_SetConfig 32 static +stm32l0xx_hal_tim.c:6629:13:TIM_OC4_SetConfig 32 static +stm32l0xx_hal_tim.c:6677:26:TIM_SlaveTimer_SetConfig 32 static +stm32l0xx_hal_tim.c:6811:13:TIM_TI1_SetConfig 32 static +stm32l0xx_hal_tim.c:6858:13:TIM_TI1_ConfigInputStage 32 static +stm32l0xx_hal_tim.c:6901:13:TIM_TI2_SetConfig 32 static +stm32l0xx_hal_tim.c:6941:13:TIM_TI2_ConfigInputStage 32 static +stm32l0xx_hal_tim.c:6984:13:TIM_TI3_SetConfig 32 static +stm32l0xx_hal_tim.c:7032:13:TIM_TI4_SetConfig 32 static +stm32l0xx_hal_tim.c:7075:13:TIM_ITRx_SetConfig 24 static +stm32l0xx_hal_tim.c:7105:13:TIM_ETR_SetConfig 32 static +stm32l0xx_hal_tim.c:7135:13:TIM_CCxChannelCmd 32 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su new file mode 100644 index 0000000..4a9d059 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su @@ -0,0 +1,2 @@ +stm32l0xx_hal_tim_ex.c:82:19:HAL_TIMEx_MasterConfigSynchronization 24 static +stm32l0xx_hal_tim_ex.c:394:19:HAL_TIMEx_RemapConfig 16 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su new file mode 100644 index 0000000..ca12311 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su @@ -0,0 +1,66 @@ +stm32l0xx_hal_uart.c:291:19:HAL_UART_Init 16 static +stm32l0xx_hal_uart.c:364:19:HAL_HalfDuplex_Init 16 static +stm32l0xx_hal_uart.c:437:19:HAL_LIN_Init 16 static +stm32l0xx_hal_uart.c:534:19:HAL_MultiProcessor_Init 24 static +stm32l0xx_hal_uart.c:608:19:HAL_UART_DeInit 16 static +stm32l0xx_hal_uart.c:654:13:HAL_UART_MspInit 16 static +stm32l0xx_hal_uart.c:669:13:HAL_UART_MspDeInit 16 static +stm32l0xx_hal_uart.c:1087:19:HAL_UART_Transmit 48 static +stm32l0xx_hal_uart.c:1188:19:HAL_UART_Receive 48 static +stm32l0xx_hal_uart.c:1290:19:HAL_UART_Transmit_IT 40 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1359:19:HAL_UART_Receive_IT 40 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1418:19:HAL_UART_Transmit_DMA 40 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1510:19:HAL_UART_Receive_DMA 40 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1559:19:HAL_UART_DMAPause 88 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1593:19:HAL_UART_DMAResume 80 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1625:19:HAL_UART_DMAStop 56 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1700:19:HAL_UART_Abort 96 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1795:19:HAL_UART_AbortTransmit 48 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1847:19:HAL_UART_AbortReceive 80 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:1914:19:HAL_UART_Abort_IT 104 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:2060:19:HAL_UART_AbortTransmit_IT 48 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:2144:19:HAL_UART_AbortReceive_IT 80 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:2236:6:HAL_UART_IRQHandler 184 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:2527:13:HAL_UART_TxCpltCallback 16 static +stm32l0xx_hal_uart.c:2542:13:HAL_UART_TxHalfCpltCallback 16 static +stm32l0xx_hal_uart.c:2557:13:HAL_UART_RxCpltCallback 16 static +stm32l0xx_hal_uart.c:2572:13:HAL_UART_RxHalfCpltCallback 16 static +stm32l0xx_hal_uart.c:2587:13:HAL_UART_ErrorCallback 16 static +stm32l0xx_hal_uart.c:2602:13:HAL_UART_AbortCpltCallback 16 static +stm32l0xx_hal_uart.c:2617:13:HAL_UART_AbortTransmitCpltCallback 16 static +stm32l0xx_hal_uart.c:2632:13:HAL_UART_AbortReceiveCpltCallback 16 static +stm32l0xx_hal_uart.c:2649:13:HAL_UARTEx_RxEventCallback 16 static +stm32l0xx_hal_uart.c:2697:6:HAL_UART_ReceiverTimeout_Config 16 static +stm32l0xx_hal_uart.c:2712:19:HAL_UART_EnableReceiverTimeout 16 static +stm32l0xx_hal_uart.c:2750:19:HAL_UART_DisableReceiverTimeout 16 static +stm32l0xx_hal_uart.c:2788:19:HAL_MultiProcessor_EnableMuteMode 32 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:2808:19:HAL_MultiProcessor_DisableMuteMode 32 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:2828:6:HAL_MultiProcessor_EnterMuteMode 16 static +stm32l0xx_hal_uart.c:2838:19:HAL_HalfDuplex_EnableTransmitter 48 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:2861:19:HAL_HalfDuplex_EnableReceiver 48 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:2885:19:HAL_LIN_SendBreak 16 static +stm32l0xx_hal_uart.c:2930:23:HAL_UART_GetState 24 static +stm32l0xx_hal_uart.c:2946:10:HAL_UART_GetError 16 static +stm32l0xx_hal_uart.c:2990:19:UART_SetConfig 72 static +stm32l0xx_hal_uart.c:3214:6:UART_AdvFeatureConfig 16 static +stm32l0xx_hal_uart.c:3288:19:UART_CheckIdleState 32 static +stm32l0xx_hal_uart.c:3339:19:UART_WaitOnFlagUntilTimeout 88 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3401:19:UART_Start_Receive_IT 56 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3445:19:UART_Start_Receive_DMA 72 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3502:13:UART_EndTxTransfer 32 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3517:13:UART_EndRxTransfer 64 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3543:13:UART_DMATransmitCplt 56 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3577:13:UART_DMATxHalfCplt 24 static +stm32l0xx_hal_uart.c:3595:13:UART_DMAReceiveCplt 88 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3652:13:UART_DMARxHalfCplt 24 static +stm32l0xx_hal_uart.c:3686:13:UART_DMAError 32 static +stm32l0xx_hal_uart.c:3726:13:UART_DMAAbortOnError 24 static +stm32l0xx_hal_uart.c:3749:13:UART_DMATxAbortCallback 24 static +stm32l0xx_hal_uart.c:3799:13:UART_DMARxAbortCallback 24 static +stm32l0xx_hal_uart.c:3851:13:UART_DMATxOnlyAbortCallback 24 static +stm32l0xx_hal_uart.c:3879:13:UART_DMARxOnlyAbortCallback 24 static +stm32l0xx_hal_uart.c:3912:13:UART_TxISR_8BIT 48 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3941:13:UART_TxISR_16BIT 56 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3973:13:UART_EndTransmit_IT 32 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:3998:13:UART_RxISR_8BIT 72 static,ignoring_inline_asm +stm32l0xx_hal_uart.c:4075:13:UART_RxISR_16BIT 72 static,ignoring_inline_asm diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su new file mode 100644 index 0000000..93233c0 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su @@ -0,0 +1,12 @@ +stm32l0xx_hal_uart_ex.c:148:19:HAL_RS485Ex_Init 32 static +stm32l0xx_hal_uart_ex.c:250:13:HAL_UARTEx_WakeupCallback 16 static +stm32l0xx_hal_uart_ex.c:330:19:HAL_UARTEx_EnableClockStopMode 32 static,ignoring_inline_asm +stm32l0xx_hal_uart_ex.c:349:19:HAL_UARTEx_DisableClockStopMode 32 static,ignoring_inline_asm +stm32l0xx_hal_uart_ex.c:376:19:HAL_MultiProcessorEx_AddressLength_Set 16 static +stm32l0xx_hal_uart_ex.c:414:19:HAL_UARTEx_StopModeWakeUpSourceConfig 40 static +stm32l0xx_hal_uart_ex.c:469:19:HAL_UARTEx_EnableStopMode 32 static,ignoring_inline_asm +stm32l0xx_hal_uart_ex.c:488:19:HAL_UARTEx_DisableStopMode 32 static,ignoring_inline_asm +stm32l0xx_hal_uart_ex.c:524:19:HAL_UARTEx_ReceiveToIdle 40 static +stm32l0xx_hal_uart_ex.c:665:19:HAL_UARTEx_ReceiveToIdle_IT 56 static,ignoring_inline_asm +stm32l0xx_hal_uart_ex.c:743:19:HAL_UARTEx_ReceiveToIdle_DMA 56 static,ignoring_inline_asm +stm32l0xx_hal_uart_ex.c:817:13:UARTEx_Wakeup_AddressConfig 24 static diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..c579eb3 --- /dev/null +++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,80 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c + +OBJS += \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + +C_DEPS += \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32L0xx_HAL_Driver/Src/%.o: ../Drivers/STM32L0xx_HAL_Driver/Src/%.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/software/dumber3/Debug/Dumber3.bin b/software/dumber3/Debug/Dumber3.bin new file mode 100755 index 0000000000000000000000000000000000000000..38769ab735ac4c2849e963138edb60e9914902a2 GIT binary patch literal 31032 zcmb__4S1W?eeZcC*_OXz#||LBa)K-+As{|dLJP6@5Oxs6f|3T>28rIvPC{SF38bu} z!D6jfXq!T}210j1>i61S`U%SxMx&%;rMH82y_IZsZ)~$wVO`U0-B8P($@Uvd_xC&J zeI+?SxBEOdd0xHeocDbE&;R_t&i{N^_=Iokxx)Qt=Lq*-;t{{&-|z3Me}D9Y!hIb1 zUqV?H;k)sfIqTa$S@BLQpIzqc=Ir_!zn`79&T5l+x{oy99M~^{Erq722s-kvn?zAO zuLT18x{r4Y;bWfshlSe}?LH!c&b)K0%F%uNM1I4_!!MwA`P56f^=h6w@k%kWR9UI0`mp~(_5{D=$>%WzbN z2{}s0@C)b*@(Y&c84s+7ZVSqIBuJ zmiGnlacGUtn1k88I9aAJTbh{wY6`pOLX`=pYlu|doEHsUOMvL$U7r9ME*WfJmM0a z;<3n+kq4i7WN72bOY&PI+ajWLbpAro%z-Z*nct*85%GnxkxehhBDX~jg@+>N3%=Kg zr-uelK0PD~`-}0&SG~ut7eO)m`$gdw0r8l2NDIV}i|--4#i0$wj}857#{Sxo6+tcE zpLkzFJfS`5e5Q0P7dagHM&wI?Zz$pmWcBTl+3@v|UNI7RIDDQ!tHXAyKdjX<4BXD- z&6a!J`fwzYcCRRYYe*}6WvJuiSM|?duld&Y?Y&+MXxFaw+;Y9Rv^oE+p?{k}jH#E- z7ua$7cQ~w>T`teSCA3cGzs_1=L%mK@rxlho;mUf3Ez1E z)5DtEd`+br&%6@V4fonm-%8;D4gQa%^VX&N^!@2R?Q(rzsLy*q1lJcreOW`_KNZ#Y z6{7n7Le#rIGvv+xFNE>zV~>6+q1H-ISJ|TB%IvN_C%>@mKR?AXU$M&UsD5i%ZE-DYeTi1Tu&lPY_F1d8YpajeYWuX6NAvfF z=MGbOOt@Nhq4y&Ce z>&v}Xjq{ag4VH+kYuqaHFBOi1Va0w?xl(@JWyN2SUlUgBZ!3-M&S^0#{iRC(vUcaR z+pTtwRk~{Jw#k}rvC2FxYaX#;Pa!s^MXcDDEB{_>Y$>jVtuK#PPFr8>9&Wb2e6liY zeQ{f(y2<)7QTeI$r9F6#q=btt==Mq&F0^8IAr{xxS+Vz54$D%ch3^#k<$SBY?aQ!` z)%vXTNae|8u+4#A6~%3?e7XkP3JF1n)yl;Z0=E@gSJ_`{^Y@A;BD?y8k35Cb zQQE&KN;~k(BfNe=l(ysfHJ(o+ez{pK-@W82UA@>e(i{~79^ooI1}W!)lyjBdw^%uy z0G>{D3HQeHgzw;yCn3u&hTQUqD+0O@1I?v;#RJLU5v#2Di@I`B9%=3_N-J>ga%cdy$$M)1yD|S1*r^d7>A~)N`XQz_N<^W@j&RjIP9Q zY-cxqXGd2=sTn+0zjvS)s2}i8`nPMb#Gq)7Qg>*jTjy0TZj`;C20RgY&I1}>tA$Ai zz0p;GyN5L=SaT-P#rhLc&y99OJ4a%pZAj6_TA638B|7Qvab?Du(7sms(HT{{N7gRu z1|5h8fTt>TZ@vCM@jnK*R0}H_T4;}UpqFeRGwPP@w8(Z?zq9nJ1^urUlqNk9xq|iI zBmn!vpfyEX-PR~%mbxXa*`xB<6358?`pD9CfPJb-Ph7(m5?8a$#9*|F-fm{gqgOJ0 z^c`r~QTmoO`rle0MG>odV#0Ho#Hyq8@RI8H=N2xKxnH(&Kfch7+^9=ZTMQ-qvV^mA ziPe(_7eXRo(OXQ?TgIZj&Eh;A+D@c(M%^;)53RI2kmd#+ zneW3^+N}#NKqg9uOk%E0j{AO$`@tiB1iW=f9$jnUt#T%`x=zdGGwY)3K@)3l)sTzfS@|pZ47p@Fc@7jS@iI2ySz+PuV;0U9=R>QB zG5&&bS1ZbOlpe1t9RKq?d(a8~TLl>{+?qvOwCg&e`gnU(8-U!{39DD4{Dx_Z-b;$g0N4f*~Ly3^_n}FAGxg~#py9kLcF12L%zbuCOivB53Qm9Wu zUqi6GF#3H?U@g?QZlq6igQrpp#O;Ir9*3Uj5X*BCzo9m_ zP=2MAXISPr(J)fX0oiJO-?TtnH3LiUtnxP@an%ZJW8MZ_QC}Q9@^Rp6f1=B>QM*9n z-u>F9*~4j%zOOy%G1_6TvQ;r4O83qaep-``89CzN#4+l%?*`(n4egoM)?+g2lM)OosK|!h~q*I{#eECOPzN2Taeq-yV^_}m~)IA8oH?9 zL9OSZrca5s;n>bqpweE8dRJQ1OR8qibV++L{E{XH`@R&IYf@Tc!#rE>06h#>`1@`N z1F3>~L&5Qg#NjF_No+V~7751&z%f$TfF4~yt=`NYtpywbi@OFa?h1{Dl53E@+Jet( z!DlAS8hp_E7JP(qR)+Oa%#0-ciqdqI)aH})&Af^O_&bX*b?$`6?w2SXlhobLen3Y_ z`gW7PDG$!Z>F>$DM9>$J|9J5R^kxfs^OA$T83NSTTfBdr#rq1Y(EQ+U!qf;2IXvxY z1~h5U6&B?8RWFZj8qpJPi#7r7%cPvW6u+~Hi=n6V(V&#Gv?wy88<;-29_f#1`q)}2 z*`Ja+s9KIy(uQwD|G@dt2_rKG+X8j2k#+V<`-9fSY@$!r>5+AwE9*Q**4b;-xl-2o z5v$IPsIzlq_O1?DCuw0dsNk9<{@%JodX%&PJuGnu8L<(%WutI}e+B*AkGDO~P8+%b zJGLn^)KqW*hfX=xnVqbI68WuZ`p*|gOXmUq8w%%vreP03*1k1G6XzXoK?l$;%jn>_ zIz2<5yfr<45HQ&A#|oEW)GxJY^n&~dSoV|@Uzg{Uy_M7TUr{Hjt=ohR>5kIPmRCgC za?G#fn-IM>eLRBsj?ucJcjQsfOV3TcTeU>5^}A~8su2-z6kp!)!)>ljKlFThXkmKg z$jX~VKr8kpT$g`k$ega0|4+5Kl$@`Y|7Zc4#V33&_<+vGa|LvnhPMzHZ}rbd-|mL{ zg`4khLoX;@M7zSIMFP#H8*R}rt&4;ccvuM=&Y3q?L#pi4iq-P!C3CeGMpezW@X@w- zP|3w;zp)BFl|Hc;ctTXlzd7R+Xab>MBSakLr2V4>x{7JT8Eij!zoAK~&u<6JW^f*~ zTtF1H09$ZUW&ut(%GoE0=O)yz3;Y^W9%qBjV;%#I5w{NMi=r3mL`0=2e;90}pjOZV zcbrNa@x3D0R-o0C*_}4F$=OF59;|Bl#WVcc4a=rG*pw$fW)0d!?FchnA5I&wS{W^H zxvVWS(i;YaTi;m5i85NyjW)daPYVi^hSo(9Jq&I|ddxTx@HS_LSaZyl7*?3+D`iILkGUa95$Z!cW-x>?8eIiUdX2_B_hSV2NB3`S3+svdqJ792Gd>jMcrxd#Ea@3| zco@buE=QrT|BI2QjbA1m= z?vXIcUxoiV_N7HWx&rlk4R2D7cS}QU8gQ;^i^&mfK|CgFzXS2iILkrSBSq0Y+GtLyuHRG;GPVgBkPY_u@#6B+U*W|Oj*Mt}3S1e;|ma~6+wA~m~L@iM8xYk=ob3v1P7t&H2cyn?Z?^}e0*19mWMs9fUk@u?SgPgsNgKrli&C{%AA$H`e%~a&Q)bj5V*1lnYGZqCh;2}2DBU{IBt-XuT9yQ;3+1~O|uGd{3Rjl;Bfzr?m^o>?x z-0Inh2&EiHT8K$&opUodJ3T4_Cf=dZt*1i3pEfX&q*Ns5nBYB87({y9vKpK6cGwZz zNPT34M$^eSBq7IRb~u!T-)%HRYYwSQ8%*{NBabnd%mCwY7sZj_OE%URX znlR`w$qen43&b~>`xU(^* z2RSo|bE9)_k~6z3XD4#bCelf5QyR1c4oJ?1d)J8kcYmp3%PE6}j@ce*FMs`>3;Mg~n>yAAG^G4v|}}Pqs$m z$)l@#4!|DGH%A$YjpkN+5763bkzR1ihh1w^m9uNJ<+-iD_Jh+el@gt+;LupLnO&uP zK0G{^)^yjLly`AMll+@WO=7=AX2@AEjWw{lDGTGtAVwauU#!+CKE2S=bTP=htkQIH z1`?OQ*#_+v2T!y8*(7KgylHE_v)hw-P}{OR$xgJ}2Fl}1!PcMkI;c4@Zs-fOUR~R9 z{pq^%tJTVH`l`>!wIZe09R<*9X^;6LXrcqOZ;t*bI&0BlPR>9$TM>mnD4I#EZs*Np zN3f@GG)ZdB40RTcLNCLo4|)`Z6!6Qw-6iWBf)7?vb!Mog@C@=j4Lg%FEj@7oa>mG2 zsAEOp8~FB=)?v;{`M1@^oWFSWXSYZrX3nikC{mq=!TfOwvbDTV5smx@H_nk(6-P% zoarBabq_fEZqQ7h;0Wsu16E5caTjv7qLx0fD>{)Pu0-iyOid&(KHkmI=Ra-}?i-URlg`^aOFJl~VAvb78H@2b^#t5s*Ee1EO)AF}$6SvatC z*Q*f=*5BlZ0pSe|5MC!C^c1f_pRb1eq}5X?-(IWf)@3za|LP{YCaI}8uM&kXgN{Tn zT)0?a7&?v`GK(}~<$_n&qs@!0HuY3Mwm5(^ucNOGm{01>Yh)U5mWsD)o3Q%o$b|b8 zcAz)(tv|VQHmn0TdIN5bRqD7&NZkDPlxp?5Ja#Ar*lRBf$KlT0dTpF#pxEetci1^%aky zR4#f3LAZ%Cb{@2->|uGRAK zWwm_x)R&@O%wK!MzsY-wpGTR`sc}S^eYG;<%gVg()FHc!Y?pK_3g0aTu*yR#_0#ZT zgD2tnX)SyT;RD2F6ITU7(pvqbggcIr)(a0I{9psF-%)GxZC0C#R|BW$sY0zNRYD&# zGE6zL4=~?j*RcC-;KnTYzM}x|)ZS!toLJob0fg^To~qqG|GVT7HwvBVqC$yqVRd}O9$Tf zp&#*-BX~n$BQSGW^zDQ!Q7L~`wnBP2XtkpF_+!QO5`$S6FjxqHKd7fDYceU?zH%l8 zuUbE-a5mvZUY(e5DIQ4GYTdo8*7p{>>$T=@Ep{T-5$&;HxwTemWLc@Ji}1!$OGsF* zC`vv8zmS#W9ulzAfnFhy@|sF@RM}hQ6J3oq=ZxH_(mAm2;MvOzbwLM}0`LbSK8JV< z;_yPb82652R-IRN80WHW&pab-m1pFfd4Gbw6(w&roca?;32Hd3Ob)G?0i`2G>3c9b z2ww>?{0sP}%>>8%=VvgBHm3E5t#NEU^~r|P|0cPEyw#e25D=GSJ*2*mN*n_&*^(%H zs)*hh*g;oNR8EcLgY-Kk)165Fy&Aq&A^mSRx9O)B>bwyl?C=AZS`Y^)sL?g-;0ve{_fywg+U7nm3Oz5_ZBPfXNosl zc{`AItp%A^)_bd!SK7p&^ZSd~Hz4bEA@2&be65vZ(5lTSUS;Jd6|QK&<(jFDwUM~A zHWKI8Mnbph;mRsGYD;l#LuoY<5>I&_>i1ccKWnV6jRd7x^fP z{4s1@;?o>kOmzf$!yT|-#7w&A!mfLFuswfYaSPg`=5#wpAbN-qbG}1^vR4ad8F_(gs9_SP2 zqSR9P>kTFPk&fjg2)Cv3M6E=6JhZd32#eo{w{vC~8VjXt?cOUwSRW0I6SFHUUKXv_ z2(k9xh3J_OpMxGgdu@k$nQ2wnb{cj-U@Y5MuM1;21Md;*q7R5;^SD*MT7JdKJNKXD zwe~1m8jze#Yfuz^Q2fINZTJy{|A11pK^xLuRC-M>d>G;TZ2bdC^Yo%qgrq(CP3$QQ z)hySSi+gLON_leq2}nN9I>_fLya@Tl`KgRM^e|FkTelUU<0yHN!e7WmNQ!S4cR>Fz z2kS5)3q!S%y>j6rN0ZPdDi@}$A;-YBZ-g^EEn6_K( z)ur|f0NeiP1(x-a;2d)--54QHk?VP{HnOWHaF(}$SM|Js%1;R{S0B~xYzM3gRj@t2W*XWIV9@l zhB@k0wK?ii`R||=H(PU5%*YMbChm|Dr7vP<#f(A6@i(8~$^dzT7P@I%Ra;5=PLVO?5x4D1yk|ZOEW3m61mC+6`(wm-vI{g8 z9LRqXWxU2wL!G`jyuernUMjEQ#=JKJ@01;rGL(O5?p;HcM8 zhhuisCHIii6MrH?Y;y0il0(!gYFs!)wEa(;YdZzg4I^<3IJQT^<|;2{Gu$`zVNeX; zJ3wzaNgqeCb1npEx#Q{3P&lvNV&*`RdvUQRt56Hge5AN9=z$$EQA`AH#rwYEHb{6e zb8j&md@tU27dHlX=EqO^f{DCwQUu?Z?+(WEI{}Xe6#66{QtF%`N`n^PD42QyQyMT3 zmhEqnJ0No_F2o#5!^kJDwesB|Ys4P-(x1qEOxxsMzS6>_Z}|Qf@_RylFD|Tk!}t5- z_ptn)U*MX$j=Hh;LCV6vUT7+E9fPBzJU5DGh-;41@->bVkt${#^>JeF%)|ur82!C+ zg&A7Q4Zq($i-+Uzul0hf8}sy7c~)YyC{gCDJSIl#(6BB59V863HCMGLU(&|xSV&5! z%vc(;g4k$nWq|v6<$8Tx4tlZ2mi3^g$n8y0ipAl<#Y`wk`J!MmrR}dIn&nYUI#3Rh z4OFFMTpDsFCgI2+H3m3hJJa~4OAjn5x4tgHmb!muyS=i%rqN^d+Y2v^-LmwA$(Fs^ zTeZzuZe!ck&pL}Y zpVk3KVAY#opt}x%^Q|D@ifJPTK##8h1`7|>pWCn~d2Y(F=dYp%6ZBw$2B?`h+mu>O z8&s=3$u>Fm6Oez@Zl=^Q=Calrbp>lxqixs9GG5FN((pJFmubUm^&^!0l58z!c&*l0 zZ$`FJrzG@6>LazLNqwFLZ`ss32;I;-42#_2i;Ua>(6~0H`W!+Dskf7@7Cv$Lv#iNaQRW-Xh8?en~GeFS*-mbV7>}erRYJzla)I#_bwuS*vor@WxSt z(Jrk1WwmJ>fs*2_zVU zKfZuH336`Kl@D1Vu3g0Mrf=(sR~b^Pu#dg^1pQzrBMPfdeNKkymuW71NroRp&7#n9 z>Z`RcJ$ZiNxX??;eRA}#P(n`nvpWzPMra_mO_iWuW@Wx!ugZ^|JXU_!S@}6Xcw>I# zvhu4vK=t}LV>nMjr25-bIJ+%(tt>(fu(1c+J=I(5&m8<@9kM_0ZexG5>XF*%!xmMX zm|C##!P)1EhSs@XfjB0$+89=)9v_(S^vY4p8exR&==0F{ljMtSe|YLd-MuH&}| zH|o4w3ySyO)22{p!dE6nT+jpsf9tn5sW*Ri6wD+BJ+6S;eGJ9E}I z;?mq{j;B!~v@5iyUP9rK91i}xC%r3eePfB-uH2pwN|?LMH)+%k?FSX?@MmJM5eDM1?BQuWb2x3y z0bZH^K5)0g|0KTxQ<=km3}48@I&diCS)4QG8Ug4*V)PqD*>6bL18WESNJAm$EE`%I zmRlvZaGsm$VvLrWimfgd&6B8 zhce8(S#anY`BpN}W922^DQV!9Jjne9tnI}!ZmdN%<8k3};Gupz5 z_4%|~i$6QwhLw4J(oPjZ`6A~>^?=9!c;wiYom=G0F_|&UB<8lmW-=~+=Qvm1i8S=| z7-VvvV0dDjT7;pv@tl>4*&pIu(=?OWq$+b5deeoKQEzHu+^#2Ud}mob8ClOaknY4=Y1b&h(m7gdw)Y55_sQx8{&`+ z`)(}~-cO<3;ld-)**$7cE6=as6j5HiFFi?#d}yc#^Dn;F0~!~?Q{vFj8zEZX&;lV^ z(-0>_=QhL%(TavRA!Lnq%h_-;LiMe1D$)^s!EyF!wslvDPBIykqt8x8}EU6>9S-GZ`~_MOW_g*wDbw;QZ%$4m+l6;Uw`g*#9&Q)?4wj0$bMP6P3Hp+G*9Ox< zNKsy7v%C*$NA03l{Dl3WM)8{(RKkSyHWvM>O8EIbzFl5Q{2DwzjXq-p>y`k5+sQIo8>5 zSaqlz)Ca4jZiySKZ8-MS;n4Re?oc}-J#oSXWrJWNJBVO&}-0R3>y_ zeH1UwM}Lk-2EK@QS^5|qa$m5r%FdLxW9DF@H(vZFPTW|LH=*+$b?(QBHSrjhdrB9} z6W`9jKvCr*c3oD!0`hfQ`8-xW+JQbf`)SnVYJOCoPXQop^2p#P&zpcPXX5Aj*cLilYLTT>F!8)o#N&6^=5_L<6B^sg3?McH5dNU{|{XW>( zb!fXKv~x+!ZNo=_!`RSm*Uuf+v6r8B>xe@1v>Jz1m@mFx+8$ib+@Fxxf(4h}32fD% zOH0W4yH4SEyl%_MzQT43p+p@z=3QptjW4s=VE22}Si)0kj$tfeU#fo9+p_FiXr#Km z*+@^6Fr@tz=!3GK>^<*UtPYs4W-;&BZW`OIH}}ZDTizj{c5Evz9pTRbiuCB4LqQu| z$8O5yP;h2X*+%QGTK3CYl@IQ0o2`B(Q28ofd%a1v$8$^)+u%L;5AvOm+m4{K(2P?A zW}*Y@sa~Wv6IJY)4!}+tu=)Rozk8 zHVNE0GEc4kR`ow~qQa&B%`cbyT@y9$N|7kfpAf?cn;{G!SW)FV|>f zV;;~2^(vtc!MYZ~Em9)V-r;DQNXw!;W7#BWi1#5e0`WN`9&DRIZTQX|_sr+OK9bN_H%c*A2ljZ(;VsX&;j62FUE5=r z5WZjIsq0YpCVHG>sF`Q}GkB|%*;+`4PY|;NS;tvxi8ys@Ym`RsdfYG*A?Z;w!Pz0K zBbdPJAX+i;o58mUgSC2%SU)gXgRWjj2;azQ+9oIW+rSIlQ6yxfJQL$g%8nxs)+mPl zV+#C>R${0(Zq>gi+hmLXSzD@hPyt|i45df`6UKH4E7Q0iI4vbBaRfZjUy4&bCg5hs z=C3;JX$c+IS?_(ea#|~;tH=xeF*A<*d!oazl_YeK2|Lvn;)OZp#_vGAcAiE6WKX#Nj0X-8fwU0H1{s#_dzAs?0Vy)8B>?>~km?l5=~>Z^?-C zk!}F(_wS!DzGuv1m$~8qoY0eW&zmI<9(lxqOP&U+LBrM@;6D@l$W4s*ZNro&+t4>h zX#{(Kl|1Rm=aS^2ZP>@2LyKGkGFPL$B-_hb?KREkWP3ctuf|Jp40Ij#t+OR3cJdy@ zetbtUmjsO_a!Ks7-ib6r-<3;hSdAh^k=lRrK+pcz?KWSjdwEoCa+Wh@N-u?tIaPNk z<=yi}+=Zmf4W)SY^lZFpr6O)@a)1KgSWYXwvl2>W##xe959?V|7zBnx+?7-MB2I0Y zqoGtBQm8c_N|7E!=>)uTEua=(#f7;PYDHMDXr;jlWG;A&IM7O)Dk5-u5t0hK(I~Y@ zXWBfqwpLn)8?@fPq?NkR`WE=z!&*tov5(2E({(c}#S+wau(5$~ifQTm5@ z%-C>3Pum39pCtCr1$8RyYv_3wbPjY3eyOe9#a`fr_sYy2zThqf_nZaXh@CK>3K65TLU`V3F-wd z-Eyqh&#b(KODmaYw32s83yjsMXB9>SwA4U7qVy{0i`3J+BuZhFD4qGQQ_ru@G*V9i z?b_7S5AGoKtgTT`2dI+J{Tc3Ydnay%dKA?2%`<;&(aYD7I(){ar7t3OHQ-?WGH@db z6PB$@T54Q3qmDLlf-Xeq4<242EqD=pC*E1;0Ijq^o<}fg=_Q6GCi?Jg2c){bCx`jJ zRyq!u9OFD<4>bT~K4V#EnBcUn2i8Nzoop!crzkTk%fyFRiaJ5YQK|)cFSG1h8WNzX z5W*-q@}Z;_q8%FRN3NYp&Nf<|T&ZJEczSr&V0g-d5Ki~cLR$I6zJIv=-g4!f;l-J%pyw227* zWum`0!^bl+W$bD4+qKeXk(cv&DFv40&ot!cxj$7q&;6N+bBZgXi^ddA z#L>2Fm*LGuVO#46biO=`OkLBAvDaYXm_|$RmoxQKgnQ(j7WMr;Cg&feZDu-Im%a>B z`lca2Y>CV;)1d#6mp#O(e#jx}U}EpHXGj&*a=#o;(gtryv#s|~B8?JCyXR`5JEg69 zr={o9Nq+I=nR9hMC#A>4xW3a&-XZs|T@Cw*`d0*;hs>nokO$+U9SV&r?SBU(3*q>O zdE%Usnzj^ma~+OQf+xgy8Z3)7ORe-Sc&@1D1w6xd`n1wkda~sF0%x?~htzjA7uhSV z^y(QUK~3b<@$C+Y3)FVt>SZvc$LkPvTM%WS>2jlLj?)O2eV)_SFS(Qlw2&3L_}YM0 z`rk{r6#Yh5Z~Zh*PV8>UUQz1zUA@F69EJ zRLkoY0jmu85IUODVHaHGpVD)w%qZhAl)@Yt`FAKhrR0qG_Ca`WLlU37p$z>?P^x40 z#X6+jPP)M!fNJ$RdrqO19Emb z$!hs87qn7-p$++|vs&=BThOMo(wF6(WSq@_&)P93!nN0bgZC?VUc^&E+~#3&a2mCA z%Xv2~Cfc~7^mp?}mHU%E0iEWdwFTZK&uG@2XKIf2E7Z5VuAHpT;w_x;YmIUbZw{Wz z7KEB$duM@V+Jdano?(2O^)%GQc?RK9^{hb;G3yz+9P2ZW)o$=Sq4<;etBo}5ckfp3O^(Mj+#SvPqy6~uL#zbg+&|8%dI33S;k3r%QB5Z%0Rzb5pJK_&n@c$WMh0+T~4e>7x6Wy+Oy`2qw_pF99we*pxY$B z#0!_p_j~h~72k$^?sIaMsd)Oyd3$spM`$)h?jx5le8E|xyLQ>=u9f-8e;i%M^csoN zKH1VwV80LpqBLnTg*_6%F2r}xj?CkJJzzdOkFA^+-1d_ zaphW%)fZ(G`(k8xyqa%rU;mifJG599b8?ixvt z9yxs;;9!ekdi=IZnjiemoE0If;k3Y#cL= z7spMFnP1lA%nwM)xUwj3PQ|T!q@9*xnypCsRy5PMbpmURN_NL#8U0(n9`6~+dP35l z6SF)!e7kY`ldBK{F74DftX1$_qDf-Z_C+ZgBV3KJ+WLu>uMG+5$0I#pob6P~->-zQ z`-)b{=V~_xlQxz7R(jv8mF}=gn{wt_DgOcXQYZ-)AIf3xXwI6^-Y4s#w5->~bJ;d+ z*wEOc|7Vr+B__{@PN3B0DN&9+$JeF@&sp?v&N6zq3Ul9~-QG8n8*J}4JRKuGn z{bq@lKnOlScBk_phwuQ^yiXdl>I?k4MM__Q|Sdtk8&5BZctZX285Xa%TsbO z=eaT`wP43o2)RsSO2-?RrUv?QmE~QO*X%LEqV)U{twpt)n{czA?1MUIM9e7NplDp# z^rG~Y`5v?nZ_SJ-J+M@@&JLPLDa};Ng)_LR73U=hp*BUyR4q@_PL&#rQknGiOO&ge zIf=jjuv{llzES6>`}Vp~3uURgnXd;c){XHt+$Y4l`ue~dKhc4Og1MSI5V&$vmzx|v z!cY6*gzOvJpuXxT);Vq!IF6L|+cRn4niBoW;A=BoQKtRs4Da3M8OcuhE~1Bwzj6k* z;NpGqOk0%R>9(i~zcv@LU)#{$F1Cs1aXf^}hNb z?jlTZ6(Y6D?P!lfwxu z%8HyZwU%qk|==2W;uWyM~!&%jec*(xvsxa?A8Y zgnUzz7qz)Bc^oGS@vFF*Jg&w!EUBy=vYggA<(j@)x1`jpxxTn)q>X7$E`hrw(c4(! zD0mq=M5b^@vOzd)z4uGA8`cP-QSd)UQQ4|CkCP6m)9f*_?N$>s z_R=EtrkbM>^Nn^a?q4vK9ox0FOWLuHnjM>%$Bq`@O^q}yM{>M9I;I?7+NAv*!q)-2 zboaP$`w*t*+xF;%*xp#ZRKJ8|W1ja7vnQdx31B1C2N{R)X$tneQZ4@stMU%auyB{H zaddohp9oaSf600B*s3D<6st}P9$4G{O8MI|wH4Io!8(abuatMwyNQ)F(jRY3C497( zxc0wUYH#u;`=Z8f44#e+;2T}Ia1ON(Gm8xDnt~^dIx*KTy#VX*Jm_+H|1<6U0o+T9 z+aqWN@y1O`L{$U#x6d4Am}?x~)S|qf${sEJwWAsjs9A(4-3Bk4DXBquC!O%%{dE2{ z-0EukTdL)ii+1k+CUdjZpro{p!i1zF_sMEGyhs{jE!FaY>S}5QP$Fr|E5}T&Z-g+* z@E9yLtq&S~kadID8sUe}8f${3k1X;&RBuhYpNMz>v%;T(hf>U{&yQ2X{3@#4vMsMz?17#LA$RlCQTbNdwgq&g12c9$ z-(p>t5)bSHJvol2zg=|ua~}4(Yc_}b@YgPgbs? z#9^De;N?~H=U?Q#{nhe4peb{dV~x91aGLG@Vn%GSb~}Yqq)_Y*0(~+3sLNR!? zv&n)d)E74vlUJpx<-M32zYjHg;W^>mXsVo|?04nu5>uY5QlMjtmM;Lmsda_0q-DD; z(z0sn3atFTp?$!~_A~IjWYHfbvk_04fXGZLc-B>6!^pC_aDcmD?Mm--+H9-US#O8_ zAg=wpv1gz6w^zy~+^#F~H^QnQ7peP?OOQ2+CJ$gNu9v&M=0KGp+^_8gXE*ZphcMf> z`LL18*MrNmNmy!-$)Ewy$_m&qb!y`Ml66Y(;=I;iavA?q#z4o}{U+3;hv%?o0keZq z++A<Xp z4&Vw=B4QV?i{2B)jsgRA*bUDv!>f=^>A|p1mY|eXy66V{O+aN=P{(j40`G;?>ii1< z#MPO6-MTpu>5%LE^*ti(BfU7u=i4~>dg}p)Z}Rn32cCcZp3hu&?7I>7G1sxNXFd44 zV2%H&qZy}dOP$#ntq!!xn?Tf!&xqm9dRkfkZGnG{L{C)9KZUegxlk>C3$`;Mr@zdH z`z>u)nsAT$_9i{?{Oh-VhOLw8n8zjWz~tXLpp=XCb8OGfW7nZ}uPAlomMB%RrTcRKN2!1EsK4yAV^4C`{u?f4QMp7xld zw;{9$UUJQBlOfE5MhWW~tZH=^wvOB!?E&RPQ0@kG=TG7Wgdt>qP7b$uP~E8(WgD|@JLyK(_cfbXujxm_8%U z?C7)Y6Z6J=`JXMx8SAHa?Y7}Q(F?tW^8|?%7QOvrMbV<_M-FqdO1TMpk9cbo}1>&Uzch0dv-@J z0i7$qRhNW;e5gtulDY7AR?u#Xyq#51BB;&B_Tcjtgn{kaaH#gx+?O_crTpWit*DW5 zPn3%DHzJHVS6Jllr{>0~88>W#tcS9ZD+D|>#T5g$oPpKX445~O-z-aKhT~T48At6L8OBBMH-(E>0%J9V^+4*0tjEOuG#wHgRFaGt@R#XsoUFqAV6A>o3ONA-f9CMm%frT!F{7>(a22h=aH10qxKt;H2~=tTBW1 z#k+B6SLT$pWzCIZ2EAOkk&3e*ls*@;pqQMQ&kgHg_Nh`{#C#|weYR5`*fUoD#^)>L z%a%CaN>+&Ir! z3z{SjiBsZ{IAtGfd|m+9xs!_4Cx1yb<&(sy36BaPWC~A2lSVMg9)$3XbehA%JWS(= zdytE_OEb(fEHUUiuPlSGtetX?I~~Z|3~?uq3N0cIX$kyIAia)n8}@xi#QKg~I&a?P z{c88uhgu6_y(k6e+iq#IQkn|;j{mv%mmN>ssJ-LgPTQg1p7!DI8`#fUghinHNCtaZ zyO00Poj<%?+cbaLDL&@mdHQ`f_U+R)Eu0o&{s`__IOaa~1^iXl#_-KIY`M*M{oTpE zqaRA%bGHz?cHcGn`+Gig`{?hDi>+I3zJc23_PzJ|Zo6+M-|u4lB>vu|t68{*@NCC( z5YGubc|83s!aa!RaXcri=bdih=5x||E^ig?dH!wPv;R2+W-M>~r#YOi<`#D=zc7rL zyQACV!(Kx1g&T$YDLjYq;5>u-MeEHlpDDz@i}!PQet_qn@tm~Y4D)#v&*%2mANSqp l2c8{x>~uTriBDBO%D*}BPq-fZukb)z3jRF`rhOCt{x5@$2#Npz literal 0 HcmV?d00001 diff --git a/software/dumber3/Debug/Dumber3.list b/software/dumber3/Debug/Dumber3.list new file mode 100644 index 0000000..832081d --- /dev/null +++ b/software/dumber3/Debug/Dumber3.list @@ -0,0 +1,22798 @@ + +Dumber3.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00007728 080000c0 080000c0 000100c0 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000130 080077e8 080077e8 000177e8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08007918 08007918 00020010 2**0 + CONTENTS + 4 .ARM 00000008 08007918 08007918 00017918 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08007920 08007920 00020010 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08007920 08007920 00017920 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08007924 08007924 00017924 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000010 20000000 08007928 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 0000199c 20000010 08007938 00020010 2**2 + ALLOC + 10 ._user_heap_stack 00000604 200019ac 08007938 000219ac 2**0 + ALLOC + 11 .ARM.attributes 00000028 00000000 00000000 00020010 2**0 + CONTENTS, READONLY + 12 .debug_info 0001c98c 00000000 00000000 00020038 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 00003b25 00000000 00000000 0003c9c4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00001650 00000000 00000000 000404f0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_ranges 000014d8 00000000 00000000 00041b40 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 00013dc2 00000000 00000000 00043018 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 00019121 00000000 00000000 00056dda 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 0007a4cb 00000000 00000000 0006fefb 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000053 00000000 00000000 000ea3c6 2**0 + CONTENTS, READONLY + 20 .debug_frame 00005064 00000000 00000000 000ea41c 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080000c0 <__do_global_dtors_aux>: + 80000c0: b510 push {r4, lr} + 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) + 80000c4: 7823 ldrb r3, [r4, #0] + 80000c6: 2b00 cmp r3, #0 + 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> + 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) + 80000cc: 2b00 cmp r3, #0 + 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) + 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d4: bf00 nop + 80000d6: 2301 movs r3, #1 + 80000d8: 7023 strb r3, [r4, #0] + 80000da: bd10 pop {r4, pc} + 80000dc: 20000010 .word 0x20000010 + 80000e0: 00000000 .word 0x00000000 + 80000e4: 080077d0 .word 0x080077d0 + +080000e8 : + 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) + 80000ea: b510 push {r4, lr} + 80000ec: 2b00 cmp r3, #0 + 80000ee: d003 beq.n 80000f8 + 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) + 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) + 80000f4: e000 b.n 80000f8 + 80000f6: bf00 nop + 80000f8: bd10 pop {r4, pc} + 80000fa: 46c0 nop ; (mov r8, r8) + 80000fc: 00000000 .word 0x00000000 + 8000100: 20000014 .word 0x20000014 + 8000104: 080077d0 .word 0x080077d0 + +08000108 <__udivsi3>: + 8000108: 2200 movs r2, #0 + 800010a: 0843 lsrs r3, r0, #1 + 800010c: 428b cmp r3, r1 + 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> + 8000110: 0903 lsrs r3, r0, #4 + 8000112: 428b cmp r3, r1 + 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> + 8000116: 0a03 lsrs r3, r0, #8 + 8000118: 428b cmp r3, r1 + 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> + 800011c: 0b03 lsrs r3, r0, #12 + 800011e: 428b cmp r3, r1 + 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> + 8000122: 0c03 lsrs r3, r0, #16 + 8000124: 428b cmp r3, r1 + 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> + 8000128: 22ff movs r2, #255 ; 0xff + 800012a: 0209 lsls r1, r1, #8 + 800012c: ba12 rev r2, r2 + 800012e: 0c03 lsrs r3, r0, #16 + 8000130: 428b cmp r3, r1 + 8000132: d302 bcc.n 800013a <__udivsi3+0x32> + 8000134: 1212 asrs r2, r2, #8 + 8000136: 0209 lsls r1, r1, #8 + 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> + 800013a: 0b03 lsrs r3, r0, #12 + 800013c: 428b cmp r3, r1 + 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> + 8000140: e000 b.n 8000144 <__udivsi3+0x3c> + 8000142: 0a09 lsrs r1, r1, #8 + 8000144: 0bc3 lsrs r3, r0, #15 + 8000146: 428b cmp r3, r1 + 8000148: d301 bcc.n 800014e <__udivsi3+0x46> + 800014a: 03cb lsls r3, r1, #15 + 800014c: 1ac0 subs r0, r0, r3 + 800014e: 4152 adcs r2, r2 + 8000150: 0b83 lsrs r3, r0, #14 + 8000152: 428b cmp r3, r1 + 8000154: d301 bcc.n 800015a <__udivsi3+0x52> + 8000156: 038b lsls r3, r1, #14 + 8000158: 1ac0 subs r0, r0, r3 + 800015a: 4152 adcs r2, r2 + 800015c: 0b43 lsrs r3, r0, #13 + 800015e: 428b cmp r3, r1 + 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> + 8000162: 034b lsls r3, r1, #13 + 8000164: 1ac0 subs r0, r0, r3 + 8000166: 4152 adcs r2, r2 + 8000168: 0b03 lsrs r3, r0, #12 + 800016a: 428b cmp r3, r1 + 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> + 800016e: 030b lsls r3, r1, #12 + 8000170: 1ac0 subs r0, r0, r3 + 8000172: 4152 adcs r2, r2 + 8000174: 0ac3 lsrs r3, r0, #11 + 8000176: 428b cmp r3, r1 + 8000178: d301 bcc.n 800017e <__udivsi3+0x76> + 800017a: 02cb lsls r3, r1, #11 + 800017c: 1ac0 subs r0, r0, r3 + 800017e: 4152 adcs r2, r2 + 8000180: 0a83 lsrs r3, r0, #10 + 8000182: 428b cmp r3, r1 + 8000184: d301 bcc.n 800018a <__udivsi3+0x82> + 8000186: 028b lsls r3, r1, #10 + 8000188: 1ac0 subs r0, r0, r3 + 800018a: 4152 adcs r2, r2 + 800018c: 0a43 lsrs r3, r0, #9 + 800018e: 428b cmp r3, r1 + 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> + 8000192: 024b lsls r3, r1, #9 + 8000194: 1ac0 subs r0, r0, r3 + 8000196: 4152 adcs r2, r2 + 8000198: 0a03 lsrs r3, r0, #8 + 800019a: 428b cmp r3, r1 + 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> + 800019e: 020b lsls r3, r1, #8 + 80001a0: 1ac0 subs r0, r0, r3 + 80001a2: 4152 adcs r2, r2 + 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> + 80001a6: 09c3 lsrs r3, r0, #7 + 80001a8: 428b cmp r3, r1 + 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> + 80001ac: 01cb lsls r3, r1, #7 + 80001ae: 1ac0 subs r0, r0, r3 + 80001b0: 4152 adcs r2, r2 + 80001b2: 0983 lsrs r3, r0, #6 + 80001b4: 428b cmp r3, r1 + 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> + 80001b8: 018b lsls r3, r1, #6 + 80001ba: 1ac0 subs r0, r0, r3 + 80001bc: 4152 adcs r2, r2 + 80001be: 0943 lsrs r3, r0, #5 + 80001c0: 428b cmp r3, r1 + 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> + 80001c4: 014b lsls r3, r1, #5 + 80001c6: 1ac0 subs r0, r0, r3 + 80001c8: 4152 adcs r2, r2 + 80001ca: 0903 lsrs r3, r0, #4 + 80001cc: 428b cmp r3, r1 + 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> + 80001d0: 010b lsls r3, r1, #4 + 80001d2: 1ac0 subs r0, r0, r3 + 80001d4: 4152 adcs r2, r2 + 80001d6: 08c3 lsrs r3, r0, #3 + 80001d8: 428b cmp r3, r1 + 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> + 80001dc: 00cb lsls r3, r1, #3 + 80001de: 1ac0 subs r0, r0, r3 + 80001e0: 4152 adcs r2, r2 + 80001e2: 0883 lsrs r3, r0, #2 + 80001e4: 428b cmp r3, r1 + 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> + 80001e8: 008b lsls r3, r1, #2 + 80001ea: 1ac0 subs r0, r0, r3 + 80001ec: 4152 adcs r2, r2 + 80001ee: 0843 lsrs r3, r0, #1 + 80001f0: 428b cmp r3, r1 + 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> + 80001f4: 004b lsls r3, r1, #1 + 80001f6: 1ac0 subs r0, r0, r3 + 80001f8: 4152 adcs r2, r2 + 80001fa: 1a41 subs r1, r0, r1 + 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> + 80001fe: 4601 mov r1, r0 + 8000200: 4152 adcs r2, r2 + 8000202: 4610 mov r0, r2 + 8000204: 4770 bx lr + 8000206: e7ff b.n 8000208 <__udivsi3+0x100> + 8000208: b501 push {r0, lr} + 800020a: 2000 movs r0, #0 + 800020c: f000 f806 bl 800021c <__aeabi_idiv0> + 8000210: bd02 pop {r1, pc} + 8000212: 46c0 nop ; (mov r8, r8) + +08000214 <__aeabi_uidivmod>: + 8000214: 2900 cmp r1, #0 + 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> + 8000218: e776 b.n 8000108 <__udivsi3> + 800021a: 4770 bx lr + +0800021c <__aeabi_idiv0>: + 800021c: 4770 bx lr + 800021e: 46c0 nop ; (mov r8, r8) + +08000220 <__aeabi_uldivmod>: + 8000220: 2b00 cmp r3, #0 + 8000222: d111 bne.n 8000248 <__aeabi_uldivmod+0x28> + 8000224: 2a00 cmp r2, #0 + 8000226: d10f bne.n 8000248 <__aeabi_uldivmod+0x28> + 8000228: 2900 cmp r1, #0 + 800022a: d100 bne.n 800022e <__aeabi_uldivmod+0xe> + 800022c: 2800 cmp r0, #0 + 800022e: d002 beq.n 8000236 <__aeabi_uldivmod+0x16> + 8000230: 2100 movs r1, #0 + 8000232: 43c9 mvns r1, r1 + 8000234: 1c08 adds r0, r1, #0 + 8000236: b407 push {r0, r1, r2} + 8000238: 4802 ldr r0, [pc, #8] ; (8000244 <__aeabi_uldivmod+0x24>) + 800023a: a102 add r1, pc, #8 ; (adr r1, 8000244 <__aeabi_uldivmod+0x24>) + 800023c: 1840 adds r0, r0, r1 + 800023e: 9002 str r0, [sp, #8] + 8000240: bd03 pop {r0, r1, pc} + 8000242: 46c0 nop ; (mov r8, r8) + 8000244: ffffffd9 .word 0xffffffd9 + 8000248: b403 push {r0, r1} + 800024a: 4668 mov r0, sp + 800024c: b501 push {r0, lr} + 800024e: 9802 ldr r0, [sp, #8] + 8000250: f000 f82e bl 80002b0 <__udivmoddi4> + 8000254: 9b01 ldr r3, [sp, #4] + 8000256: 469e mov lr, r3 + 8000258: b002 add sp, #8 + 800025a: bc0c pop {r2, r3} + 800025c: 4770 bx lr + 800025e: 46c0 nop ; (mov r8, r8) + +08000260 <__aeabi_lmul>: + 8000260: b5f0 push {r4, r5, r6, r7, lr} + 8000262: 0415 lsls r5, r2, #16 + 8000264: 0c2d lsrs r5, r5, #16 + 8000266: 000f movs r7, r1 + 8000268: 0001 movs r1, r0 + 800026a: 002e movs r6, r5 + 800026c: 46c6 mov lr, r8 + 800026e: 4684 mov ip, r0 + 8000270: 0400 lsls r0, r0, #16 + 8000272: 0c14 lsrs r4, r2, #16 + 8000274: 0c00 lsrs r0, r0, #16 + 8000276: 0c09 lsrs r1, r1, #16 + 8000278: 4346 muls r6, r0 + 800027a: 434d muls r5, r1 + 800027c: 4360 muls r0, r4 + 800027e: 4361 muls r1, r4 + 8000280: 1940 adds r0, r0, r5 + 8000282: 0c34 lsrs r4, r6, #16 + 8000284: 1824 adds r4, r4, r0 + 8000286: b500 push {lr} + 8000288: 42a5 cmp r5, r4 + 800028a: d903 bls.n 8000294 <__aeabi_lmul+0x34> + 800028c: 2080 movs r0, #128 ; 0x80 + 800028e: 0240 lsls r0, r0, #9 + 8000290: 4680 mov r8, r0 + 8000292: 4441 add r1, r8 + 8000294: 0c25 lsrs r5, r4, #16 + 8000296: 186d adds r5, r5, r1 + 8000298: 4661 mov r1, ip + 800029a: 4359 muls r1, r3 + 800029c: 437a muls r2, r7 + 800029e: 0430 lsls r0, r6, #16 + 80002a0: 1949 adds r1, r1, r5 + 80002a2: 0424 lsls r4, r4, #16 + 80002a4: 0c00 lsrs r0, r0, #16 + 80002a6: 1820 adds r0, r4, r0 + 80002a8: 1889 adds r1, r1, r2 + 80002aa: bc80 pop {r7} + 80002ac: 46b8 mov r8, r7 + 80002ae: bdf0 pop {r4, r5, r6, r7, pc} + +080002b0 <__udivmoddi4>: + 80002b0: b5f0 push {r4, r5, r6, r7, lr} + 80002b2: 4657 mov r7, sl + 80002b4: 464e mov r6, r9 + 80002b6: 4645 mov r5, r8 + 80002b8: 46de mov lr, fp + 80002ba: b5e0 push {r5, r6, r7, lr} + 80002bc: 0004 movs r4, r0 + 80002be: 000d movs r5, r1 + 80002c0: 4692 mov sl, r2 + 80002c2: 4699 mov r9, r3 + 80002c4: b083 sub sp, #12 + 80002c6: 428b cmp r3, r1 + 80002c8: d830 bhi.n 800032c <__udivmoddi4+0x7c> + 80002ca: d02d beq.n 8000328 <__udivmoddi4+0x78> + 80002cc: 4649 mov r1, r9 + 80002ce: 4650 mov r0, sl + 80002d0: f000 f8ba bl 8000448 <__clzdi2> + 80002d4: 0029 movs r1, r5 + 80002d6: 0006 movs r6, r0 + 80002d8: 0020 movs r0, r4 + 80002da: f000 f8b5 bl 8000448 <__clzdi2> + 80002de: 1a33 subs r3, r6, r0 + 80002e0: 4698 mov r8, r3 + 80002e2: 3b20 subs r3, #32 + 80002e4: 469b mov fp, r3 + 80002e6: d433 bmi.n 8000350 <__udivmoddi4+0xa0> + 80002e8: 465a mov r2, fp + 80002ea: 4653 mov r3, sl + 80002ec: 4093 lsls r3, r2 + 80002ee: 4642 mov r2, r8 + 80002f0: 001f movs r7, r3 + 80002f2: 4653 mov r3, sl + 80002f4: 4093 lsls r3, r2 + 80002f6: 001e movs r6, r3 + 80002f8: 42af cmp r7, r5 + 80002fa: d83a bhi.n 8000372 <__udivmoddi4+0xc2> + 80002fc: 42af cmp r7, r5 + 80002fe: d100 bne.n 8000302 <__udivmoddi4+0x52> + 8000300: e078 b.n 80003f4 <__udivmoddi4+0x144> + 8000302: 465b mov r3, fp + 8000304: 1ba4 subs r4, r4, r6 + 8000306: 41bd sbcs r5, r7 + 8000308: 2b00 cmp r3, #0 + 800030a: da00 bge.n 800030e <__udivmoddi4+0x5e> + 800030c: e075 b.n 80003fa <__udivmoddi4+0x14a> + 800030e: 2200 movs r2, #0 + 8000310: 2300 movs r3, #0 + 8000312: 9200 str r2, [sp, #0] + 8000314: 9301 str r3, [sp, #4] + 8000316: 2301 movs r3, #1 + 8000318: 465a mov r2, fp + 800031a: 4093 lsls r3, r2 + 800031c: 9301 str r3, [sp, #4] + 800031e: 2301 movs r3, #1 + 8000320: 4642 mov r2, r8 + 8000322: 4093 lsls r3, r2 + 8000324: 9300 str r3, [sp, #0] + 8000326: e028 b.n 800037a <__udivmoddi4+0xca> + 8000328: 4282 cmp r2, r0 + 800032a: d9cf bls.n 80002cc <__udivmoddi4+0x1c> + 800032c: 2200 movs r2, #0 + 800032e: 2300 movs r3, #0 + 8000330: 9200 str r2, [sp, #0] + 8000332: 9301 str r3, [sp, #4] + 8000334: 9b0c ldr r3, [sp, #48] ; 0x30 + 8000336: 2b00 cmp r3, #0 + 8000338: d001 beq.n 800033e <__udivmoddi4+0x8e> + 800033a: 601c str r4, [r3, #0] + 800033c: 605d str r5, [r3, #4] + 800033e: 9800 ldr r0, [sp, #0] + 8000340: 9901 ldr r1, [sp, #4] + 8000342: b003 add sp, #12 + 8000344: bcf0 pop {r4, r5, r6, r7} + 8000346: 46bb mov fp, r7 + 8000348: 46b2 mov sl, r6 + 800034a: 46a9 mov r9, r5 + 800034c: 46a0 mov r8, r4 + 800034e: bdf0 pop {r4, r5, r6, r7, pc} + 8000350: 4642 mov r2, r8 + 8000352: 2320 movs r3, #32 + 8000354: 1a9b subs r3, r3, r2 + 8000356: 4652 mov r2, sl + 8000358: 40da lsrs r2, r3 + 800035a: 4641 mov r1, r8 + 800035c: 0013 movs r3, r2 + 800035e: 464a mov r2, r9 + 8000360: 408a lsls r2, r1 + 8000362: 0017 movs r7, r2 + 8000364: 4642 mov r2, r8 + 8000366: 431f orrs r7, r3 + 8000368: 4653 mov r3, sl + 800036a: 4093 lsls r3, r2 + 800036c: 001e movs r6, r3 + 800036e: 42af cmp r7, r5 + 8000370: d9c4 bls.n 80002fc <__udivmoddi4+0x4c> + 8000372: 2200 movs r2, #0 + 8000374: 2300 movs r3, #0 + 8000376: 9200 str r2, [sp, #0] + 8000378: 9301 str r3, [sp, #4] + 800037a: 4643 mov r3, r8 + 800037c: 2b00 cmp r3, #0 + 800037e: d0d9 beq.n 8000334 <__udivmoddi4+0x84> + 8000380: 07fb lsls r3, r7, #31 + 8000382: 0872 lsrs r2, r6, #1 + 8000384: 431a orrs r2, r3 + 8000386: 4646 mov r6, r8 + 8000388: 087b lsrs r3, r7, #1 + 800038a: e00e b.n 80003aa <__udivmoddi4+0xfa> + 800038c: 42ab cmp r3, r5 + 800038e: d101 bne.n 8000394 <__udivmoddi4+0xe4> + 8000390: 42a2 cmp r2, r4 + 8000392: d80c bhi.n 80003ae <__udivmoddi4+0xfe> + 8000394: 1aa4 subs r4, r4, r2 + 8000396: 419d sbcs r5, r3 + 8000398: 2001 movs r0, #1 + 800039a: 1924 adds r4, r4, r4 + 800039c: 416d adcs r5, r5 + 800039e: 2100 movs r1, #0 + 80003a0: 3e01 subs r6, #1 + 80003a2: 1824 adds r4, r4, r0 + 80003a4: 414d adcs r5, r1 + 80003a6: 2e00 cmp r6, #0 + 80003a8: d006 beq.n 80003b8 <__udivmoddi4+0x108> + 80003aa: 42ab cmp r3, r5 + 80003ac: d9ee bls.n 800038c <__udivmoddi4+0xdc> + 80003ae: 3e01 subs r6, #1 + 80003b0: 1924 adds r4, r4, r4 + 80003b2: 416d adcs r5, r5 + 80003b4: 2e00 cmp r6, #0 + 80003b6: d1f8 bne.n 80003aa <__udivmoddi4+0xfa> + 80003b8: 9800 ldr r0, [sp, #0] + 80003ba: 9901 ldr r1, [sp, #4] + 80003bc: 465b mov r3, fp + 80003be: 1900 adds r0, r0, r4 + 80003c0: 4169 adcs r1, r5 + 80003c2: 2b00 cmp r3, #0 + 80003c4: db24 blt.n 8000410 <__udivmoddi4+0x160> + 80003c6: 002b movs r3, r5 + 80003c8: 465a mov r2, fp + 80003ca: 4644 mov r4, r8 + 80003cc: 40d3 lsrs r3, r2 + 80003ce: 002a movs r2, r5 + 80003d0: 40e2 lsrs r2, r4 + 80003d2: 001c movs r4, r3 + 80003d4: 465b mov r3, fp + 80003d6: 0015 movs r5, r2 + 80003d8: 2b00 cmp r3, #0 + 80003da: db2a blt.n 8000432 <__udivmoddi4+0x182> + 80003dc: 0026 movs r6, r4 + 80003de: 409e lsls r6, r3 + 80003e0: 0033 movs r3, r6 + 80003e2: 0026 movs r6, r4 + 80003e4: 4647 mov r7, r8 + 80003e6: 40be lsls r6, r7 + 80003e8: 0032 movs r2, r6 + 80003ea: 1a80 subs r0, r0, r2 + 80003ec: 4199 sbcs r1, r3 + 80003ee: 9000 str r0, [sp, #0] + 80003f0: 9101 str r1, [sp, #4] + 80003f2: e79f b.n 8000334 <__udivmoddi4+0x84> + 80003f4: 42a3 cmp r3, r4 + 80003f6: d8bc bhi.n 8000372 <__udivmoddi4+0xc2> + 80003f8: e783 b.n 8000302 <__udivmoddi4+0x52> + 80003fa: 4642 mov r2, r8 + 80003fc: 2320 movs r3, #32 + 80003fe: 2100 movs r1, #0 + 8000400: 1a9b subs r3, r3, r2 + 8000402: 2200 movs r2, #0 + 8000404: 9100 str r1, [sp, #0] + 8000406: 9201 str r2, [sp, #4] + 8000408: 2201 movs r2, #1 + 800040a: 40da lsrs r2, r3 + 800040c: 9201 str r2, [sp, #4] + 800040e: e786 b.n 800031e <__udivmoddi4+0x6e> + 8000410: 4642 mov r2, r8 + 8000412: 2320 movs r3, #32 + 8000414: 1a9b subs r3, r3, r2 + 8000416: 002a movs r2, r5 + 8000418: 4646 mov r6, r8 + 800041a: 409a lsls r2, r3 + 800041c: 0023 movs r3, r4 + 800041e: 40f3 lsrs r3, r6 + 8000420: 4644 mov r4, r8 + 8000422: 4313 orrs r3, r2 + 8000424: 002a movs r2, r5 + 8000426: 40e2 lsrs r2, r4 + 8000428: 001c movs r4, r3 + 800042a: 465b mov r3, fp + 800042c: 0015 movs r5, r2 + 800042e: 2b00 cmp r3, #0 + 8000430: dad4 bge.n 80003dc <__udivmoddi4+0x12c> + 8000432: 4642 mov r2, r8 + 8000434: 002f movs r7, r5 + 8000436: 2320 movs r3, #32 + 8000438: 0026 movs r6, r4 + 800043a: 4097 lsls r7, r2 + 800043c: 1a9b subs r3, r3, r2 + 800043e: 40de lsrs r6, r3 + 8000440: 003b movs r3, r7 + 8000442: 4333 orrs r3, r6 + 8000444: e7cd b.n 80003e2 <__udivmoddi4+0x132> + 8000446: 46c0 nop ; (mov r8, r8) + +08000448 <__clzdi2>: + 8000448: b510 push {r4, lr} + 800044a: 2900 cmp r1, #0 + 800044c: d103 bne.n 8000456 <__clzdi2+0xe> + 800044e: f000 f807 bl 8000460 <__clzsi2> + 8000452: 3020 adds r0, #32 + 8000454: e002 b.n 800045c <__clzdi2+0x14> + 8000456: 1c08 adds r0, r1, #0 + 8000458: f000 f802 bl 8000460 <__clzsi2> + 800045c: bd10 pop {r4, pc} + 800045e: 46c0 nop ; (mov r8, r8) + +08000460 <__clzsi2>: + 8000460: 211c movs r1, #28 + 8000462: 2301 movs r3, #1 + 8000464: 041b lsls r3, r3, #16 + 8000466: 4298 cmp r0, r3 + 8000468: d301 bcc.n 800046e <__clzsi2+0xe> + 800046a: 0c00 lsrs r0, r0, #16 + 800046c: 3910 subs r1, #16 + 800046e: 0a1b lsrs r3, r3, #8 + 8000470: 4298 cmp r0, r3 + 8000472: d301 bcc.n 8000478 <__clzsi2+0x18> + 8000474: 0a00 lsrs r0, r0, #8 + 8000476: 3908 subs r1, #8 + 8000478: 091b lsrs r3, r3, #4 + 800047a: 4298 cmp r0, r3 + 800047c: d301 bcc.n 8000482 <__clzsi2+0x22> + 800047e: 0900 lsrs r0, r0, #4 + 8000480: 3904 subs r1, #4 + 8000482: a202 add r2, pc, #8 ; (adr r2, 800048c <__clzsi2+0x2c>) + 8000484: 5c10 ldrb r0, [r2, r0] + 8000486: 1840 adds r0, r0, r1 + 8000488: 4770 bx lr + 800048a: 46c0 nop ; (mov r8, r8) + 800048c: 02020304 .word 0x02020304 + 8000490: 01010101 .word 0x01010101 + ... + +0800049c : + +/* USER CODE END FunctionPrototypes */ + +/* USER CODE BEGIN PREPOSTSLEEP */ +__weak void PreSleepProcessing(uint32_t *ulExpectedIdleTime) +{ + 800049c: b580 push {r7, lr} + 800049e: b082 sub sp, #8 + 80004a0: af00 add r7, sp, #0 + 80004a2: 6078 str r0, [r7, #4] +/* place for user code */ +} + 80004a4: 46c0 nop ; (mov r8, r8) + 80004a6: 46bd mov sp, r7 + 80004a8: b002 add sp, #8 + 80004aa: bd80 pop {r7, pc} + +080004ac : + +__weak void PostSleepProcessing(uint32_t *ulExpectedIdleTime) +{ + 80004ac: b580 push {r7, lr} + 80004ae: b082 sub sp, #8 + 80004b0: af00 add r7, sp, #0 + 80004b2: 6078 str r0, [r7, #4] +/* place for user code */ +} + 80004b4: 46c0 nop ; (mov r8, r8) + 80004b6: 46bd mov sp, r7 + 80004b8: b002 add sp, #8 + 80004ba: bd80 pop {r7, pc} + +080004bc : +StackType_t xStackLeds[ STACK_SIZE ]; +TaskHandle_t xHandleLeds = NULL; + +void LEDS_AnimationThread(void* params); + +void LEDS_Init(void) { + 80004bc: b580 push {r7, lr} + 80004be: b084 sub sp, #16 + 80004c0: af04 add r7, sp, #16 + LEDS_EteintVerte(); + 80004c2: 2380 movs r3, #128 ; 0x80 + 80004c4: 01db lsls r3, r3, #7 + 80004c6: 4816 ldr r0, [pc, #88] ; (8000520 ) + 80004c8: 2200 movs r2, #0 + 80004ca: 0019 movs r1, r3 + 80004cc: f002 f818 bl 8002500 + LEDS_EteintJaune(); + 80004d0: 2380 movs r3, #128 ; 0x80 + 80004d2: 019b lsls r3, r3, #6 + 80004d4: 4812 ldr r0, [pc, #72] ; (8000520 ) + 80004d6: 2200 movs r2, #0 + 80004d8: 0019 movs r1, r3 + 80004da: f002 f811 bl 8002500 + LEDS_EteintRouge(); + 80004de: 2380 movs r3, #128 ; 0x80 + 80004e0: 015b lsls r3, r3, #5 + 80004e2: 480f ldr r0, [pc, #60] ; (8000520 ) + 80004e4: 2200 movs r2, #0 + 80004e6: 0019 movs r1, r3 + 80004e8: f002 f80a bl 8002500 + + LEDS_Animation=leds_off; + 80004ec: 4b0d ldr r3, [pc, #52] ; (8000524 ) + 80004ee: 2200 movs r2, #0 + 80004f0: 701a strb r2, [r3, #0] + + /* Mailbox is created in messages.c */ + + /* Create the task without using any dynamic memory allocation. */ + xHandleLeds = xTaskCreateStatic( + 80004f2: 490d ldr r1, [pc, #52] ; (8000528 ) + 80004f4: 480d ldr r0, [pc, #52] ; (800052c ) + 80004f6: 4b0e ldr r3, [pc, #56] ; (8000530 ) + 80004f8: 9302 str r3, [sp, #8] + 80004fa: 4b0e ldr r3, [pc, #56] ; (8000534 ) + 80004fc: 9301 str r3, [sp, #4] + 80004fe: 2333 movs r3, #51 ; 0x33 + 8000500: 9300 str r3, [sp, #0] + 8000502: 2300 movs r3, #0 + 8000504: 2264 movs r2, #100 ; 0x64 + 8000506: f005 fae4 bl 8005ad2 + 800050a: 0002 movs r2, r0 + 800050c: 4b0a ldr r3, [pc, #40] ; (8000538 ) + 800050e: 601a str r2, [r3, #0] + STACK_SIZE, /* Number of indexes in the xStack array. */ + NULL, /* Parameter passed into the task. */ + PriorityLeds,/* Priority at which the task is created. */ + xStackLeds, /* Array to use as the task's stack. */ + &xTaskLeds); /* Variable to hold the task's data structure. */ + vTaskResume(xHandleLeds); + 8000510: 4b09 ldr r3, [pc, #36] ; (8000538 ) + 8000512: 681b ldr r3, [r3, #0] + 8000514: 0018 movs r0, r3 + 8000516: f005 fcaf bl 8005e78 +} + 800051a: 46c0 nop ; (mov r8, r8) + 800051c: 46bd mov sp, r7 + 800051e: bd80 pop {r7, pc} + 8000520: 50000400 .word 0x50000400 + 8000524: 2000153c .word 0x2000153c + 8000528: 080077e8 .word 0x080077e8 + 800052c: 0800053d .word 0x0800053d + 8000530: 200016d4 .word 0x200016d4 + 8000534: 20001540 .word 0x20001540 + 8000538: 2000002c .word 0x2000002c + +0800053c : + +void LEDS_RegleAnimation(LEDS_State etat) { + LEDS_Animation=etat; +} + +void LEDS_AnimationThread(void* params) { + 800053c: b5b0 push {r4, r5, r7, lr} + 800053e: b086 sub sp, #24 + 8000540: af00 add r7, sp, #0 + 8000542: 6078 str r0, [r7, #4] + MESSAGE_Typedef msg; + uint8_t cnt=0; + 8000544: 2317 movs r3, #23 + 8000546: 18fb adds r3, r7, r3 + 8000548: 2200 movs r2, #0 + 800054a: 701a strb r2, [r3, #0] + + while (1) { + vTaskDelay(pdMS_TO_TICKS(100)); + 800054c: 200a movs r0, #10 + 800054e: f005 fc47 bl 8005de0 + + msg = MESSAGE_ReadMailboxNoDelay(LEDS_Mailbox); + 8000552: 4bdc ldr r3, [pc, #880] ; (80008c4 ) + 8000554: 681a ldr r2, [r3, #0] + 8000556: 2408 movs r4, #8 + 8000558: 193b adds r3, r7, r4 + 800055a: 0011 movs r1, r2 + 800055c: 0018 movs r0, r3 + 800055e: f000 fda7 bl 80010b0 + + cnt++; + 8000562: 2517 movs r5, #23 + 8000564: 197b adds r3, r7, r5 + 8000566: 781a ldrb r2, [r3, #0] + 8000568: 197b adds r3, r7, r5 + 800056a: 3201 adds r2, #1 + 800056c: 701a strb r2, [r3, #0] + + if (msg.id == MSG_ID_LED_ETAT) { // Si c'est bien un message de changemnet d'etat LEDS + 800056e: 193b adds r3, r7, r4 + 8000570: 881b ldrh r3, [r3, #0] + 8000572: 2b00 cmp r3, #0 + 8000574: d126 bne.n 80005c4 + LEDS_Animation = *((LEDS_State*)msg.data); + 8000576: 193b adds r3, r7, r4 + 8000578: 689b ldr r3, [r3, #8] + 800057a: 781a ldrb r2, [r3, #0] + 800057c: 4bd2 ldr r3, [pc, #840] ; (80008c8 ) + 800057e: 701a strb r2, [r3, #0] + + if (LEDS_Animation != LEDS_AnimationAncien) { // si le nouvel etat est different de l'ancien + 8000580: 4bd1 ldr r3, [pc, #836] ; (80008c8 ) + 8000582: 781a ldrb r2, [r3, #0] + 8000584: 4bd1 ldr r3, [pc, #836] ; (80008cc ) + 8000586: 781b ldrb r3, [r3, #0] + 8000588: 429a cmp r2, r3 + 800058a: d01b beq.n 80005c4 + // dans ce cas, on eteint les leds pour repartir sur une base saine + LEDS_AnimationAncien = LEDS_Animation; + 800058c: 4bce ldr r3, [pc, #824] ; (80008c8 ) + 800058e: 781a ldrb r2, [r3, #0] + 8000590: 4bce ldr r3, [pc, #824] ; (80008cc ) + 8000592: 701a strb r2, [r3, #0] + + LEDS_EteintVerte(); + 8000594: 2380 movs r3, #128 ; 0x80 + 8000596: 01db lsls r3, r3, #7 + 8000598: 48cd ldr r0, [pc, #820] ; (80008d0 ) + 800059a: 2200 movs r2, #0 + 800059c: 0019 movs r1, r3 + 800059e: f001 ffaf bl 8002500 + LEDS_EteintJaune(); + 80005a2: 2380 movs r3, #128 ; 0x80 + 80005a4: 019b lsls r3, r3, #6 + 80005a6: 48ca ldr r0, [pc, #808] ; (80008d0 ) + 80005a8: 2200 movs r2, #0 + 80005aa: 0019 movs r1, r3 + 80005ac: f001 ffa8 bl 8002500 + LEDS_EteintRouge(); + 80005b0: 2380 movs r3, #128 ; 0x80 + 80005b2: 015b lsls r3, r3, #5 + 80005b4: 48c6 ldr r0, [pc, #792] ; (80008d0 ) + 80005b6: 2200 movs r2, #0 + 80005b8: 0019 movs r1, r3 + 80005ba: f001 ffa1 bl 8002500 + cnt=0; + 80005be: 197b adds r3, r7, r5 + 80005c0: 2200 movs r2, #0 + 80005c2: 701a strb r2, [r3, #0] + } + } + + switch (LEDS_Animation) { + 80005c4: 4bc0 ldr r3, [pc, #768] ; (80008c8 ) + 80005c6: 781b ldrb r3, [r3, #0] + 80005c8: 2b10 cmp r3, #16 + 80005ca: d900 bls.n 80005ce + 80005cc: e1ec b.n 80009a8 + 80005ce: 009a lsls r2, r3, #2 + 80005d0: 4bc0 ldr r3, [pc, #768] ; (80008d4 ) + 80005d2: 18d3 adds r3, r2, r3 + 80005d4: 681b ldr r3, [r3, #0] + 80005d6: 469f mov pc, r3 + case leds_off: + LEDS_EteintVerte(); + 80005d8: 2380 movs r3, #128 ; 0x80 + 80005da: 01db lsls r3, r3, #7 + 80005dc: 48bc ldr r0, [pc, #752] ; (80008d0 ) + 80005de: 2200 movs r2, #0 + 80005e0: 0019 movs r1, r3 + 80005e2: f001 ff8d bl 8002500 + LEDS_EteintJaune(); + 80005e6: 2380 movs r3, #128 ; 0x80 + 80005e8: 019b lsls r3, r3, #6 + 80005ea: 48b9 ldr r0, [pc, #740] ; (80008d0 ) + 80005ec: 2200 movs r2, #0 + 80005ee: 0019 movs r1, r3 + 80005f0: f001 ff86 bl 8002500 + LEDS_EteintRouge(); + 80005f4: 2380 movs r3, #128 ; 0x80 + 80005f6: 015b lsls r3, r3, #5 + 80005f8: 48b5 ldr r0, [pc, #724] ; (80008d0 ) + 80005fa: 2200 movs r2, #0 + 80005fc: 0019 movs r1, r3 + 80005fe: f001 ff7f bl 8002500 + break; + 8000602: e1d2 b.n 80009aa + case leds_idle: + if (cnt<5) + 8000604: 2317 movs r3, #23 + 8000606: 18fb adds r3, r7, r3 + 8000608: 781b ldrb r3, [r3, #0] + 800060a: 2b04 cmp r3, #4 + 800060c: d807 bhi.n 800061e + LEDS_AllumeVerte(); + 800060e: 2380 movs r3, #128 ; 0x80 + 8000610: 01db lsls r3, r3, #7 + 8000612: 48af ldr r0, [pc, #700] ; (80008d0 ) + 8000614: 2201 movs r2, #1 + 8000616: 0019 movs r1, r3 + 8000618: f001 ff72 bl 8002500 + else if (cnt<10) + LEDS_EteintVerte(); + else + cnt=0; + break; + 800061c: e1c5 b.n 80009aa + else if (cnt<10) + 800061e: 2317 movs r3, #23 + 8000620: 18fb adds r3, r7, r3 + 8000622: 781b ldrb r3, [r3, #0] + 8000624: 2b09 cmp r3, #9 + 8000626: d807 bhi.n 8000638 + LEDS_EteintVerte(); + 8000628: 2380 movs r3, #128 ; 0x80 + 800062a: 01db lsls r3, r3, #7 + 800062c: 48a8 ldr r0, [pc, #672] ; (80008d0 ) + 800062e: 2200 movs r2, #0 + 8000630: 0019 movs r1, r3 + 8000632: f001 ff65 bl 8002500 + break; + 8000636: e1b8 b.n 80009aa + cnt=0; + 8000638: 2317 movs r3, #23 + 800063a: 18fb adds r3, r7, r3 + 800063c: 2200 movs r2, #0 + 800063e: 701a strb r2, [r3, #0] + break; + 8000640: e1b3 b.n 80009aa + case leds_connecte: + LEDS_AllumeVerte(); + 8000642: 2380 movs r3, #128 ; 0x80 + 8000644: 01db lsls r3, r3, #7 + 8000646: 48a2 ldr r0, [pc, #648] ; (80008d0 ) + 8000648: 2201 movs r2, #1 + 800064a: 0019 movs r1, r3 + 800064c: f001 ff58 bl 8002500 + break; + 8000650: e1ab b.n 80009aa + case leds_watchdog_expire: + if (cnt<5) + 8000652: 2317 movs r3, #23 + 8000654: 18fb adds r3, r7, r3 + 8000656: 781b ldrb r3, [r3, #0] + 8000658: 2b04 cmp r3, #4 + 800065a: d807 bhi.n 800066c + LEDS_AllumeRouge(); + 800065c: 2380 movs r3, #128 ; 0x80 + 800065e: 015b lsls r3, r3, #5 + 8000660: 489b ldr r0, [pc, #620] ; (80008d0 ) + 8000662: 2201 movs r2, #1 + 8000664: 0019 movs r1, r3 + 8000666: f001 ff4b bl 8002500 + else if (cnt<10) + LEDS_EteintRouge(); + else + cnt=0; + break; + 800066a: e19e b.n 80009aa + else if (cnt<10) + 800066c: 2317 movs r3, #23 + 800066e: 18fb adds r3, r7, r3 + 8000670: 781b ldrb r3, [r3, #0] + 8000672: 2b09 cmp r3, #9 + 8000674: d807 bhi.n 8000686 + LEDS_EteintRouge(); + 8000676: 2380 movs r3, #128 ; 0x80 + 8000678: 015b lsls r3, r3, #5 + 800067a: 4895 ldr r0, [pc, #596] ; (80008d0 ) + 800067c: 2200 movs r2, #0 + 800067e: 0019 movs r1, r3 + 8000680: f001 ff3e bl 8002500 + break; + 8000684: e191 b.n 80009aa + cnt=0; + 8000686: 2317 movs r3, #23 + 8000688: 18fb adds r3, r7, r3 + 800068a: 2200 movs r2, #0 + 800068c: 701a strb r2, [r3, #0] + break; + 800068e: e18c b.n 80009aa + case leds_niveau_bat_0: + if (!(cnt%2)) + 8000690: 2317 movs r3, #23 + 8000692: 18fb adds r3, r7, r3 + 8000694: 781b ldrb r3, [r3, #0] + 8000696: 2201 movs r2, #1 + 8000698: 4013 ands r3, r2 + 800069a: b2db uxtb r3, r3 + 800069c: 2b00 cmp r3, #0 + 800069e: d107 bne.n 80006b0 + LEDS_AllumeRouge(); + 80006a0: 2380 movs r3, #128 ; 0x80 + 80006a2: 015b lsls r3, r3, #5 + 80006a4: 488a ldr r0, [pc, #552] ; (80008d0 ) + 80006a6: 2201 movs r2, #1 + 80006a8: 0019 movs r1, r3 + 80006aa: f001 ff29 bl 8002500 + else + LEDS_EteintRouge(); + break; + 80006ae: e17c b.n 80009aa + LEDS_EteintRouge(); + 80006b0: 2380 movs r3, #128 ; 0x80 + 80006b2: 015b lsls r3, r3, #5 + 80006b4: 4886 ldr r0, [pc, #536] ; (80008d0 ) + 80006b6: 2200 movs r2, #0 + 80006b8: 0019 movs r1, r3 + 80006ba: f001 ff21 bl 8002500 + break; + 80006be: e174 b.n 80009aa + case leds_niveau_bat_1: + LEDS_AllumeRouge(); + 80006c0: 2380 movs r3, #128 ; 0x80 + 80006c2: 015b lsls r3, r3, #5 + 80006c4: 4882 ldr r0, [pc, #520] ; (80008d0 ) + 80006c6: 2201 movs r2, #1 + 80006c8: 0019 movs r1, r3 + 80006ca: f001 ff19 bl 8002500 + break; + 80006ce: e16c b.n 80009aa + case leds_niveau_bat_2: + LEDS_AllumeRouge(); + 80006d0: 2380 movs r3, #128 ; 0x80 + 80006d2: 015b lsls r3, r3, #5 + 80006d4: 487e ldr r0, [pc, #504] ; (80008d0 ) + 80006d6: 2201 movs r2, #1 + 80006d8: 0019 movs r1, r3 + 80006da: f001 ff11 bl 8002500 + + if (cnt<3) + 80006de: 2317 movs r3, #23 + 80006e0: 18fb adds r3, r7, r3 + 80006e2: 781b ldrb r3, [r3, #0] + 80006e4: 2b02 cmp r3, #2 + 80006e6: d807 bhi.n 80006f8 + LEDS_AllumeJaune(); + 80006e8: 2380 movs r3, #128 ; 0x80 + 80006ea: 019b lsls r3, r3, #6 + 80006ec: 4878 ldr r0, [pc, #480] ; (80008d0 ) + 80006ee: 2201 movs r2, #1 + 80006f0: 0019 movs r1, r3 + 80006f2: f001 ff05 bl 8002500 + else if (cnt<6) + LEDS_EteintJaune(); + else + cnt=0; + break; + 80006f6: e158 b.n 80009aa + else if (cnt<6) + 80006f8: 2317 movs r3, #23 + 80006fa: 18fb adds r3, r7, r3 + 80006fc: 781b ldrb r3, [r3, #0] + 80006fe: 2b05 cmp r3, #5 + 8000700: d807 bhi.n 8000712 + LEDS_EteintJaune(); + 8000702: 2380 movs r3, #128 ; 0x80 + 8000704: 019b lsls r3, r3, #6 + 8000706: 4872 ldr r0, [pc, #456] ; (80008d0 ) + 8000708: 2200 movs r2, #0 + 800070a: 0019 movs r1, r3 + 800070c: f001 fef8 bl 8002500 + break; + 8000710: e14b b.n 80009aa + cnt=0; + 8000712: 2317 movs r3, #23 + 8000714: 18fb adds r3, r7, r3 + 8000716: 2200 movs r2, #0 + 8000718: 701a strb r2, [r3, #0] + break; + 800071a: e146 b.n 80009aa + case leds_niveau_bat_3: + LEDS_AllumeRouge(); + 800071c: 2380 movs r3, #128 ; 0x80 + 800071e: 015b lsls r3, r3, #5 + 8000720: 486b ldr r0, [pc, #428] ; (80008d0 ) + 8000722: 2201 movs r2, #1 + 8000724: 0019 movs r1, r3 + 8000726: f001 feeb bl 8002500 + LEDS_AllumeJaune(); + 800072a: 2380 movs r3, #128 ; 0x80 + 800072c: 019b lsls r3, r3, #6 + 800072e: 4868 ldr r0, [pc, #416] ; (80008d0 ) + 8000730: 2201 movs r2, #1 + 8000732: 0019 movs r1, r3 + 8000734: f001 fee4 bl 8002500 + break; + 8000738: e137 b.n 80009aa + case leds_niveau_bat_4: + LEDS_AllumeRouge(); + 800073a: 2380 movs r3, #128 ; 0x80 + 800073c: 015b lsls r3, r3, #5 + 800073e: 4864 ldr r0, [pc, #400] ; (80008d0 ) + 8000740: 2201 movs r2, #1 + 8000742: 0019 movs r1, r3 + 8000744: f001 fedc bl 8002500 + LEDS_AllumeJaune(); + 8000748: 2380 movs r3, #128 ; 0x80 + 800074a: 019b lsls r3, r3, #6 + 800074c: 4860 ldr r0, [pc, #384] ; (80008d0 ) + 800074e: 2201 movs r2, #1 + 8000750: 0019 movs r1, r3 + 8000752: f001 fed5 bl 8002500 + + if (cnt<3) + 8000756: 2317 movs r3, #23 + 8000758: 18fb adds r3, r7, r3 + 800075a: 781b ldrb r3, [r3, #0] + 800075c: 2b02 cmp r3, #2 + 800075e: d807 bhi.n 8000770 + LEDS_AllumeVerte(); + 8000760: 2380 movs r3, #128 ; 0x80 + 8000762: 01db lsls r3, r3, #7 + 8000764: 485a ldr r0, [pc, #360] ; (80008d0 ) + 8000766: 2201 movs r2, #1 + 8000768: 0019 movs r1, r3 + 800076a: f001 fec9 bl 8002500 + else if (cnt<6) + LEDS_EteintVerte(); + else + cnt=0; + break; + 800076e: e11c b.n 80009aa + else if (cnt<6) + 8000770: 2317 movs r3, #23 + 8000772: 18fb adds r3, r7, r3 + 8000774: 781b ldrb r3, [r3, #0] + 8000776: 2b05 cmp r3, #5 + 8000778: d807 bhi.n 800078a + LEDS_EteintVerte(); + 800077a: 2380 movs r3, #128 ; 0x80 + 800077c: 01db lsls r3, r3, #7 + 800077e: 4854 ldr r0, [pc, #336] ; (80008d0 ) + 8000780: 2200 movs r2, #0 + 8000782: 0019 movs r1, r3 + 8000784: f001 febc bl 8002500 + break; + 8000788: e10f b.n 80009aa + cnt=0; + 800078a: 2317 movs r3, #23 + 800078c: 18fb adds r3, r7, r3 + 800078e: 2200 movs r2, #0 + 8000790: 701a strb r2, [r3, #0] + break; + 8000792: e10a b.n 80009aa + case leds_niveau_bat_5: + LEDS_AllumeRouge(); + 8000794: 2380 movs r3, #128 ; 0x80 + 8000796: 015b lsls r3, r3, #5 + 8000798: 484d ldr r0, [pc, #308] ; (80008d0 ) + 800079a: 2201 movs r2, #1 + 800079c: 0019 movs r1, r3 + 800079e: f001 feaf bl 8002500 + LEDS_AllumeJaune(); + 80007a2: 2380 movs r3, #128 ; 0x80 + 80007a4: 019b lsls r3, r3, #6 + 80007a6: 484a ldr r0, [pc, #296] ; (80008d0 ) + 80007a8: 2201 movs r2, #1 + 80007aa: 0019 movs r1, r3 + 80007ac: f001 fea8 bl 8002500 + LEDS_AllumeVerte(); + 80007b0: 2380 movs r3, #128 ; 0x80 + 80007b2: 01db lsls r3, r3, #7 + 80007b4: 4846 ldr r0, [pc, #280] ; (80008d0 ) + 80007b6: 2201 movs r2, #1 + 80007b8: 0019 movs r1, r3 + 80007ba: f001 fea1 bl 8002500 + break; + 80007be: e0f4 b.n 80009aa + case leds_charge_bat_0: + case leds_charge_bat_1: + if (cnt<3) + 80007c0: 2317 movs r3, #23 + 80007c2: 18fb adds r3, r7, r3 + 80007c4: 781b ldrb r3, [r3, #0] + 80007c6: 2b02 cmp r3, #2 + 80007c8: d807 bhi.n 80007da + LEDS_AllumeRouge(); + 80007ca: 2380 movs r3, #128 ; 0x80 + 80007cc: 015b lsls r3, r3, #5 + 80007ce: 4840 ldr r0, [pc, #256] ; (80008d0 ) + 80007d0: 2201 movs r2, #1 + 80007d2: 0019 movs r1, r3 + 80007d4: f001 fe94 bl 8002500 + LEDS_EteintVerte(); + LEDS_EteintJaune(); + LEDS_EteintRouge(); + } else + cnt=0; + break; + 80007d8: e0e7 b.n 80009aa + else if (cnt<6) + 80007da: 2317 movs r3, #23 + 80007dc: 18fb adds r3, r7, r3 + 80007de: 781b ldrb r3, [r3, #0] + 80007e0: 2b05 cmp r3, #5 + 80007e2: d807 bhi.n 80007f4 + LEDS_AllumeJaune(); + 80007e4: 2380 movs r3, #128 ; 0x80 + 80007e6: 019b lsls r3, r3, #6 + 80007e8: 4839 ldr r0, [pc, #228] ; (80008d0 ) + 80007ea: 2201 movs r2, #1 + 80007ec: 0019 movs r1, r3 + 80007ee: f001 fe87 bl 8002500 + break; + 80007f2: e0da b.n 80009aa + else if (cnt<9) + 80007f4: 2317 movs r3, #23 + 80007f6: 18fb adds r3, r7, r3 + 80007f8: 781b ldrb r3, [r3, #0] + 80007fa: 2b08 cmp r3, #8 + 80007fc: d807 bhi.n 800080e + LEDS_AllumeVerte(); + 80007fe: 2380 movs r3, #128 ; 0x80 + 8000800: 01db lsls r3, r3, #7 + 8000802: 4833 ldr r0, [pc, #204] ; (80008d0 ) + 8000804: 2201 movs r2, #1 + 8000806: 0019 movs r1, r3 + 8000808: f001 fe7a bl 8002500 + break; + 800080c: e0cd b.n 80009aa + else if (cnt<12){ + 800080e: 2317 movs r3, #23 + 8000810: 18fb adds r3, r7, r3 + 8000812: 781b ldrb r3, [r3, #0] + 8000814: 2b0b cmp r3, #11 + 8000816: d815 bhi.n 8000844 + LEDS_EteintVerte(); + 8000818: 2380 movs r3, #128 ; 0x80 + 800081a: 01db lsls r3, r3, #7 + 800081c: 482c ldr r0, [pc, #176] ; (80008d0 ) + 800081e: 2200 movs r2, #0 + 8000820: 0019 movs r1, r3 + 8000822: f001 fe6d bl 8002500 + LEDS_EteintJaune(); + 8000826: 2380 movs r3, #128 ; 0x80 + 8000828: 019b lsls r3, r3, #6 + 800082a: 4829 ldr r0, [pc, #164] ; (80008d0 ) + 800082c: 2200 movs r2, #0 + 800082e: 0019 movs r1, r3 + 8000830: f001 fe66 bl 8002500 + LEDS_EteintRouge(); + 8000834: 2380 movs r3, #128 ; 0x80 + 8000836: 015b lsls r3, r3, #5 + 8000838: 4825 ldr r0, [pc, #148] ; (80008d0 ) + 800083a: 2200 movs r2, #0 + 800083c: 0019 movs r1, r3 + 800083e: f001 fe5f bl 8002500 + break; + 8000842: e0b2 b.n 80009aa + cnt=0; + 8000844: 2317 movs r3, #23 + 8000846: 18fb adds r3, r7, r3 + 8000848: 2200 movs r2, #0 + 800084a: 701a strb r2, [r3, #0] + break; + 800084c: e0ad b.n 80009aa + case leds_charge_bat_2: + case leds_charge_bat_3: + LEDS_AllumeRouge(); + 800084e: 2380 movs r3, #128 ; 0x80 + 8000850: 015b lsls r3, r3, #5 + 8000852: 481f ldr r0, [pc, #124] ; (80008d0 ) + 8000854: 2201 movs r2, #1 + 8000856: 0019 movs r1, r3 + 8000858: f001 fe52 bl 8002500 + if (cnt<3) + 800085c: 2317 movs r3, #23 + 800085e: 18fb adds r3, r7, r3 + 8000860: 781b ldrb r3, [r3, #0] + 8000862: 2b02 cmp r3, #2 + 8000864: d807 bhi.n 8000876 + LEDS_AllumeJaune(); + 8000866: 2380 movs r3, #128 ; 0x80 + 8000868: 019b lsls r3, r3, #6 + 800086a: 4819 ldr r0, [pc, #100] ; (80008d0 ) + 800086c: 2201 movs r2, #1 + 800086e: 0019 movs r1, r3 + 8000870: f001 fe46 bl 8002500 + else if (cnt <9){ + LEDS_EteintVerte(); + LEDS_EteintJaune(); + } else + cnt=0; + break; + 8000874: e099 b.n 80009aa + else if (cnt<6) + 8000876: 2317 movs r3, #23 + 8000878: 18fb adds r3, r7, r3 + 800087a: 781b ldrb r3, [r3, #0] + 800087c: 2b05 cmp r3, #5 + 800087e: d807 bhi.n 8000890 + LEDS_AllumeVerte(); + 8000880: 2380 movs r3, #128 ; 0x80 + 8000882: 01db lsls r3, r3, #7 + 8000884: 4812 ldr r0, [pc, #72] ; (80008d0 ) + 8000886: 2201 movs r2, #1 + 8000888: 0019 movs r1, r3 + 800088a: f001 fe39 bl 8002500 + break; + 800088e: e08c b.n 80009aa + else if (cnt <9){ + 8000890: 2317 movs r3, #23 + 8000892: 18fb adds r3, r7, r3 + 8000894: 781b ldrb r3, [r3, #0] + 8000896: 2b08 cmp r3, #8 + 8000898: d80e bhi.n 80008b8 + LEDS_EteintVerte(); + 800089a: 2380 movs r3, #128 ; 0x80 + 800089c: 01db lsls r3, r3, #7 + 800089e: 480c ldr r0, [pc, #48] ; (80008d0 ) + 80008a0: 2200 movs r2, #0 + 80008a2: 0019 movs r1, r3 + 80008a4: f001 fe2c bl 8002500 + LEDS_EteintJaune(); + 80008a8: 2380 movs r3, #128 ; 0x80 + 80008aa: 019b lsls r3, r3, #6 + 80008ac: 4808 ldr r0, [pc, #32] ; (80008d0 ) + 80008ae: 2200 movs r2, #0 + 80008b0: 0019 movs r1, r3 + 80008b2: f001 fe25 bl 8002500 + break; + 80008b6: e078 b.n 80009aa + cnt=0; + 80008b8: 2317 movs r3, #23 + 80008ba: 18fb adds r3, r7, r3 + 80008bc: 2200 movs r2, #0 + 80008be: 701a strb r2, [r3, #0] + break; + 80008c0: e073 b.n 80009aa + 80008c2: 46c0 nop ; (mov r8, r8) + 80008c4: 20001964 .word 0x20001964 + 80008c8: 2000153c .word 0x2000153c + 80008cc: 200016d0 .word 0x200016d0 + 80008d0: 50000400 .word 0x50000400 + 80008d4: 0800781c .word 0x0800781c + case leds_charge_bat_4: + case leds_charge_bat_5: + LEDS_AllumeRouge(); + 80008d8: 2380 movs r3, #128 ; 0x80 + 80008da: 015b lsls r3, r3, #5 + 80008dc: 4833 ldr r0, [pc, #204] ; (80009ac ) + 80008de: 2201 movs r2, #1 + 80008e0: 0019 movs r1, r3 + 80008e2: f001 fe0d bl 8002500 + LEDS_AllumeJaune(); + 80008e6: 2380 movs r3, #128 ; 0x80 + 80008e8: 019b lsls r3, r3, #6 + 80008ea: 4830 ldr r0, [pc, #192] ; (80009ac ) + 80008ec: 2201 movs r2, #1 + 80008ee: 0019 movs r1, r3 + 80008f0: f001 fe06 bl 8002500 + + if (cnt<3) + 80008f4: 2317 movs r3, #23 + 80008f6: 18fb adds r3, r7, r3 + 80008f8: 781b ldrb r3, [r3, #0] + 80008fa: 2b02 cmp r3, #2 + 80008fc: d807 bhi.n 800090e + LEDS_AllumeVerte(); + 80008fe: 2380 movs r3, #128 ; 0x80 + 8000900: 01db lsls r3, r3, #7 + 8000902: 482a ldr r0, [pc, #168] ; (80009ac ) + 8000904: 2201 movs r2, #1 + 8000906: 0019 movs r1, r3 + 8000908: f001 fdfa bl 8002500 + else if (cnt<6) + LEDS_EteintVerte(); + else + cnt=0; + break; + 800090c: e04d b.n 80009aa + else if (cnt<6) + 800090e: 2317 movs r3, #23 + 8000910: 18fb adds r3, r7, r3 + 8000912: 781b ldrb r3, [r3, #0] + 8000914: 2b05 cmp r3, #5 + 8000916: d807 bhi.n 8000928 + LEDS_EteintVerte(); + 8000918: 2380 movs r3, #128 ; 0x80 + 800091a: 01db lsls r3, r3, #7 + 800091c: 4823 ldr r0, [pc, #140] ; (80009ac ) + 800091e: 2200 movs r2, #0 + 8000920: 0019 movs r1, r3 + 8000922: f001 fded bl 8002500 + break; + 8000926: e040 b.n 80009aa + cnt=0; + 8000928: 2317 movs r3, #23 + 800092a: 18fb adds r3, r7, r3 + 800092c: 2200 movs r2, #0 + 800092e: 701a strb r2, [r3, #0] + break; + 8000930: e03b b.n 80009aa + case leds_erreur: + if (cnt<5) { + 8000932: 2317 movs r3, #23 + 8000934: 18fb adds r3, r7, r3 + 8000936: 781b ldrb r3, [r3, #0] + 8000938: 2b04 cmp r3, #4 + 800093a: d815 bhi.n 8000968 + LEDS_AllumeRouge(); + 800093c: 2380 movs r3, #128 ; 0x80 + 800093e: 015b lsls r3, r3, #5 + 8000940: 481a ldr r0, [pc, #104] ; (80009ac ) + 8000942: 2201 movs r2, #1 + 8000944: 0019 movs r1, r3 + 8000946: f001 fddb bl 8002500 + LEDS_AllumeJaune(); + 800094a: 2380 movs r3, #128 ; 0x80 + 800094c: 019b lsls r3, r3, #6 + 800094e: 4817 ldr r0, [pc, #92] ; (80009ac ) + 8000950: 2201 movs r2, #1 + 8000952: 0019 movs r1, r3 + 8000954: f001 fdd4 bl 8002500 + LEDS_AllumeVerte(); + 8000958: 2380 movs r3, #128 ; 0x80 + 800095a: 01db lsls r3, r3, #7 + 800095c: 4813 ldr r0, [pc, #76] ; (80009ac ) + 800095e: 2201 movs r2, #1 + 8000960: 0019 movs r1, r3 + 8000962: f001 fdcd bl 8002500 + LEDS_EteintJaune(); + LEDS_EteintVerte(); + } + else + cnt=0; + break; + 8000966: e020 b.n 80009aa + else if (cnt<10) { + 8000968: 2317 movs r3, #23 + 800096a: 18fb adds r3, r7, r3 + 800096c: 781b ldrb r3, [r3, #0] + 800096e: 2b09 cmp r3, #9 + 8000970: d815 bhi.n 800099e + LEDS_EteintRouge(); + 8000972: 2380 movs r3, #128 ; 0x80 + 8000974: 015b lsls r3, r3, #5 + 8000976: 480d ldr r0, [pc, #52] ; (80009ac ) + 8000978: 2200 movs r2, #0 + 800097a: 0019 movs r1, r3 + 800097c: f001 fdc0 bl 8002500 + LEDS_EteintJaune(); + 8000980: 2380 movs r3, #128 ; 0x80 + 8000982: 019b lsls r3, r3, #6 + 8000984: 4809 ldr r0, [pc, #36] ; (80009ac ) + 8000986: 2200 movs r2, #0 + 8000988: 0019 movs r1, r3 + 800098a: f001 fdb9 bl 8002500 + LEDS_EteintVerte(); + 800098e: 2380 movs r3, #128 ; 0x80 + 8000990: 01db lsls r3, r3, #7 + 8000992: 4806 ldr r0, [pc, #24] ; (80009ac ) + 8000994: 2200 movs r2, #0 + 8000996: 0019 movs r1, r3 + 8000998: f001 fdb2 bl 8002500 + break; + 800099c: e005 b.n 80009aa + cnt=0; + 800099e: 2317 movs r3, #23 + 80009a0: 18fb adds r3, r7, r3 + 80009a2: 2200 movs r2, #0 + 80009a4: 701a strb r2, [r3, #0] + break; + 80009a6: e000 b.n 80009aa + default: + break; + 80009a8: 46c0 nop ; (mov r8, r8) + vTaskDelay(pdMS_TO_TICKS(100)); + 80009aa: e5cf b.n 800054c + 80009ac: 50000400 .word 0x50000400 + +080009b0
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 80009b0: b580 push {r7, lr} + 80009b2: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80009b4: f000 fe8a bl 80016cc + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80009b8: f000 f826 bl 8000a08 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 80009bc: f000 fa78 bl 8000eb0 + MX_DMA_Init(); + 80009c0: f000 fa58 bl 8000e74 + MX_LPTIM1_Init(); + 80009c4: f000 f8f8 bl 8000bb8 + MX_LPUART1_UART_Init(); + 80009c8: f000 f926 bl 8000c18 + MX_TIM2_Init(); + 80009cc: f000 f952 bl 8000c74 + MX_TIM21_Init(); + 80009d0: f000 f9ec bl 8000dac + MX_ADC_Init(); + 80009d4: f000 f88c bl 8000af0 + /* USER CODE BEGIN 2 */ + /* Init des messages box */ + MESSAGE_Init(); + 80009d8: f000 fb32 bl 8001040 + + LEDS_Init(); + 80009dc: f7ff fd6e bl 80004bc + /*MOTEURS_Init(); + MOTEURS_Test();*/ + /* USER CODE END 2 */ + + /* Init scheduler */ + osKernelInitialize(); + 80009e0: f004 fa3c bl 8004e5c + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* creation of defaultTask */ + defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); + 80009e4: 4a05 ldr r2, [pc, #20] ; (80009fc ) + 80009e6: 4b06 ldr r3, [pc, #24] ; (8000a00 ) + 80009e8: 2100 movs r1, #0 + 80009ea: 0018 movs r0, r3 + 80009ec: f004 fa92 bl 8004f14 + 80009f0: 0002 movs r2, r0 + 80009f2: 4b04 ldr r3, [pc, #16] ; (8000a04 ) + 80009f4: 601a str r2, [r3, #0] + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ + + /* Start scheduler */ + osKernelStart(); + 80009f6: f004 fa5d bl 8004eb4 + + /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + 80009fa: e7fe b.n 80009fa + 80009fc: 08007860 .word 0x08007860 + 8000a00: 08000fe1 .word 0x08000fe1 + 8000a04: 20001730 .word 0x20001730 + +08000a08 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000a08: b590 push {r4, r7, lr} + 8000a0a: b099 sub sp, #100 ; 0x64 + 8000a0c: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000a0e: 242c movs r4, #44 ; 0x2c + 8000a10: 193b adds r3, r7, r4 + 8000a12: 0018 movs r0, r3 + 8000a14: 2334 movs r3, #52 ; 0x34 + 8000a16: 001a movs r2, r3 + 8000a18: 2100 movs r1, #0 + 8000a1a: f006 fed0 bl 80077be + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000a1e: 2318 movs r3, #24 + 8000a20: 18fb adds r3, r7, r3 + 8000a22: 0018 movs r0, r3 + 8000a24: 2314 movs r3, #20 + 8000a26: 001a movs r2, r3 + 8000a28: 2100 movs r1, #0 + 8000a2a: f006 fec8 bl 80077be + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 8000a2e: 003b movs r3, r7 + 8000a30: 0018 movs r0, r3 + 8000a32: 2318 movs r3, #24 + 8000a34: 001a movs r2, r3 + 8000a36: 2100 movs r1, #0 + 8000a38: f006 fec1 bl 80077be + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000a3c: 4b2a ldr r3, [pc, #168] ; (8000ae8 ) + 8000a3e: 681b ldr r3, [r3, #0] + 8000a40: 4a2a ldr r2, [pc, #168] ; (8000aec ) + 8000a42: 401a ands r2, r3 + 8000a44: 4b28 ldr r3, [pc, #160] ; (8000ae8 ) + 8000a46: 2180 movs r1, #128 ; 0x80 + 8000a48: 0109 lsls r1, r1, #4 + 8000a4a: 430a orrs r2, r1 + 8000a4c: 601a str r2, [r3, #0] + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000a4e: 0021 movs r1, r4 + 8000a50: 187b adds r3, r7, r1 + 8000a52: 2202 movs r2, #2 + 8000a54: 601a str r2, [r3, #0] + RCC_OscInitStruct.HSIState = RCC_HSI_DIV4; + 8000a56: 187b adds r3, r7, r1 + 8000a58: 2209 movs r2, #9 + 8000a5a: 60da str r2, [r3, #12] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000a5c: 187b adds r3, r7, r1 + 8000a5e: 2210 movs r2, #16 + 8000a60: 611a str r2, [r3, #16] + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8000a62: 187b adds r3, r7, r1 + 8000a64: 2202 movs r2, #2 + 8000a66: 625a str r2, [r3, #36] ; 0x24 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + 8000a68: 187b adds r3, r7, r1 + 8000a6a: 2200 movs r2, #0 + 8000a6c: 629a str r2, [r3, #40] ; 0x28 + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_3; + 8000a6e: 187b adds r3, r7, r1 + 8000a70: 2200 movs r2, #0 + 8000a72: 62da str r2, [r3, #44] ; 0x2c + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; + 8000a74: 187b adds r3, r7, r1 + 8000a76: 2280 movs r2, #128 ; 0x80 + 8000a78: 03d2 lsls r2, r2, #15 + 8000a7a: 631a str r2, [r3, #48] ; 0x30 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000a7c: 187b adds r3, r7, r1 + 8000a7e: 0018 movs r0, r3 + 8000a80: f001 fe0e bl 80026a0 + 8000a84: 1e03 subs r3, r0, #0 + 8000a86: d001 beq.n 8000a8c + { + Error_Handler(); + 8000a88: f000 fad4 bl 8001034 + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000a8c: 2118 movs r1, #24 + 8000a8e: 187b adds r3, r7, r1 + 8000a90: 220f movs r2, #15 + 8000a92: 601a str r2, [r3, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8000a94: 187b adds r3, r7, r1 + 8000a96: 2203 movs r2, #3 + 8000a98: 605a str r2, [r3, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000a9a: 187b adds r3, r7, r1 + 8000a9c: 2200 movs r2, #0 + 8000a9e: 609a str r2, [r3, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000aa0: 187b adds r3, r7, r1 + 8000aa2: 2200 movs r2, #0 + 8000aa4: 60da str r2, [r3, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000aa6: 187b adds r3, r7, r1 + 8000aa8: 2200 movs r2, #0 + 8000aaa: 611a str r2, [r3, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 8000aac: 187b adds r3, r7, r1 + 8000aae: 2100 movs r1, #0 + 8000ab0: 0018 movs r0, r3 + 8000ab2: f002 f971 bl 8002d98 + 8000ab6: 1e03 subs r3, r0, #0 + 8000ab8: d001 beq.n 8000abe + { + Error_Handler(); + 8000aba: f000 fabb bl 8001034 + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_LPTIM1; + 8000abe: 003b movs r3, r7 + 8000ac0: 2284 movs r2, #132 ; 0x84 + 8000ac2: 601a str r2, [r3, #0] + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + 8000ac4: 003b movs r3, r7 + 8000ac6: 2200 movs r2, #0 + 8000ac8: 60da str r2, [r3, #12] + PeriphClkInit.LptimClockSelection = RCC_LPTIM1CLKSOURCE_PCLK; + 8000aca: 003b movs r3, r7 + 8000acc: 2200 movs r2, #0 + 8000ace: 615a str r2, [r3, #20] + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8000ad0: 003b movs r3, r7 + 8000ad2: 0018 movs r0, r3 + 8000ad4: f002 fb84 bl 80031e0 + 8000ad8: 1e03 subs r3, r0, #0 + 8000ada: d001 beq.n 8000ae0 + { + Error_Handler(); + 8000adc: f000 faaa bl 8001034 + } +} + 8000ae0: 46c0 nop ; (mov r8, r8) + 8000ae2: 46bd mov sp, r7 + 8000ae4: b019 add sp, #100 ; 0x64 + 8000ae6: bd90 pop {r4, r7, pc} + 8000ae8: 40007000 .word 0x40007000 + 8000aec: ffffe7ff .word 0xffffe7ff + +08000af0 : + * @brief ADC Initialization Function + * @param None + * @retval None + */ +static void MX_ADC_Init(void) +{ + 8000af0: b580 push {r7, lr} + 8000af2: b082 sub sp, #8 + 8000af4: af00 add r7, sp, #0 + + /* USER CODE BEGIN ADC_Init 0 */ + + /* USER CODE END ADC_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + 8000af6: 003b movs r3, r7 + 8000af8: 0018 movs r0, r3 + 8000afa: 2308 movs r3, #8 + 8000afc: 001a movs r2, r3 + 8000afe: 2100 movs r1, #0 + 8000b00: f006 fe5d bl 80077be + /* USER CODE BEGIN ADC_Init 1 */ + + /* USER CODE END ADC_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc.Instance = ADC1; + 8000b04: 4b2a ldr r3, [pc, #168] ; (8000bb0 ) + 8000b06: 4a2b ldr r2, [pc, #172] ; (8000bb4 ) + 8000b08: 601a str r2, [r3, #0] + hadc.Init.OversamplingMode = DISABLE; + 8000b0a: 4b29 ldr r3, [pc, #164] ; (8000bb0 ) + 8000b0c: 2200 movs r2, #0 + 8000b0e: 63da str r2, [r3, #60] ; 0x3c + hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1; + 8000b10: 4b27 ldr r3, [pc, #156] ; (8000bb0 ) + 8000b12: 22c0 movs r2, #192 ; 0xc0 + 8000b14: 0612 lsls r2, r2, #24 + 8000b16: 605a str r2, [r3, #4] + hadc.Init.Resolution = ADC_RESOLUTION_8B; + 8000b18: 4b25 ldr r3, [pc, #148] ; (8000bb0 ) + 8000b1a: 2210 movs r2, #16 + 8000b1c: 609a str r2, [r3, #8] + hadc.Init.SamplingTime = ADC_SAMPLETIME_160CYCLES_5; + 8000b1e: 4b24 ldr r3, [pc, #144] ; (8000bb0 ) + 8000b20: 2207 movs r2, #7 + 8000b22: 639a str r2, [r3, #56] ; 0x38 + hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; + 8000b24: 4b22 ldr r3, [pc, #136] ; (8000bb0 ) + 8000b26: 2201 movs r2, #1 + 8000b28: 611a str r2, [r3, #16] + hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 8000b2a: 4b21 ldr r3, [pc, #132] ; (8000bb0 ) + 8000b2c: 2200 movs r2, #0 + 8000b2e: 60da str r2, [r3, #12] + hadc.Init.ContinuousConvMode = DISABLE; + 8000b30: 4b1f ldr r3, [pc, #124] ; (8000bb0 ) + 8000b32: 2220 movs r2, #32 + 8000b34: 2100 movs r1, #0 + 8000b36: 5499 strb r1, [r3, r2] + hadc.Init.DiscontinuousConvMode = DISABLE; + 8000b38: 4b1d ldr r3, [pc, #116] ; (8000bb0 ) + 8000b3a: 2221 movs r2, #33 ; 0x21 + 8000b3c: 2100 movs r1, #0 + 8000b3e: 5499 strb r1, [r3, r2] + hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 8000b40: 4b1b ldr r3, [pc, #108] ; (8000bb0 ) + 8000b42: 2200 movs r2, #0 + 8000b44: 629a str r2, [r3, #40] ; 0x28 + hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 8000b46: 4b1a ldr r3, [pc, #104] ; (8000bb0 ) + 8000b48: 22c2 movs r2, #194 ; 0xc2 + 8000b4a: 32ff adds r2, #255 ; 0xff + 8000b4c: 625a str r2, [r3, #36] ; 0x24 + hadc.Init.DMAContinuousRequests = DISABLE; + 8000b4e: 4b18 ldr r3, [pc, #96] ; (8000bb0 ) + 8000b50: 222c movs r2, #44 ; 0x2c + 8000b52: 2100 movs r1, #0 + 8000b54: 5499 strb r1, [r3, r2] + hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 8000b56: 4b16 ldr r3, [pc, #88] ; (8000bb0 ) + 8000b58: 2204 movs r2, #4 + 8000b5a: 615a str r2, [r3, #20] + hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; + 8000b5c: 4b14 ldr r3, [pc, #80] ; (8000bb0 ) + 8000b5e: 2200 movs r2, #0 + 8000b60: 631a str r2, [r3, #48] ; 0x30 + hadc.Init.LowPowerAutoWait = DISABLE; + 8000b62: 4b13 ldr r3, [pc, #76] ; (8000bb0 ) + 8000b64: 2200 movs r2, #0 + 8000b66: 619a str r2, [r3, #24] + hadc.Init.LowPowerFrequencyMode = DISABLE; + 8000b68: 4b11 ldr r3, [pc, #68] ; (8000bb0 ) + 8000b6a: 2200 movs r2, #0 + 8000b6c: 635a str r2, [r3, #52] ; 0x34 + hadc.Init.LowPowerAutoPowerOff = DISABLE; + 8000b6e: 4b10 ldr r3, [pc, #64] ; (8000bb0 ) + 8000b70: 2200 movs r2, #0 + 8000b72: 61da str r2, [r3, #28] + if (HAL_ADC_Init(&hadc) != HAL_OK) + 8000b74: 4b0e ldr r3, [pc, #56] ; (8000bb0 ) + 8000b76: 0018 movs r0, r3 + 8000b78: f000 fe18 bl 80017ac + 8000b7c: 1e03 subs r3, r0, #0 + 8000b7e: d001 beq.n 8000b84 + { + Error_Handler(); + 8000b80: f000 fa58 bl 8001034 + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_0; + 8000b84: 003b movs r3, r7 + 8000b86: 2201 movs r2, #1 + 8000b88: 601a str r2, [r3, #0] + sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; + 8000b8a: 003b movs r3, r7 + 8000b8c: 2280 movs r2, #128 ; 0x80 + 8000b8e: 0152 lsls r2, r2, #5 + 8000b90: 605a str r2, [r3, #4] + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) + 8000b92: 003a movs r2, r7 + 8000b94: 4b06 ldr r3, [pc, #24] ; (8000bb0 ) + 8000b96: 0011 movs r1, r2 + 8000b98: 0018 movs r0, r3 + 8000b9a: f001 f84f bl 8001c3c + 8000b9e: 1e03 subs r3, r0, #0 + 8000ba0: d001 beq.n 8000ba6 + { + Error_Handler(); + 8000ba2: f000 fa47 bl 8001034 + } + /* USER CODE BEGIN ADC_Init 2 */ + + /* USER CODE END ADC_Init 2 */ + +} + 8000ba6: 46c0 nop ; (mov r8, r8) + 8000ba8: 46bd mov sp, r7 + 8000baa: b002 add sp, #8 + 8000bac: bd80 pop {r7, pc} + 8000bae: 46c0 nop ; (mov r8, r8) + 8000bb0: 200018b8 .word 0x200018b8 + 8000bb4: 40012400 .word 0x40012400 + +08000bb8 : + * @brief LPTIM1 Initialization Function + * @param None + * @retval None + */ +static void MX_LPTIM1_Init(void) +{ + 8000bb8: b580 push {r7, lr} + 8000bba: af00 add r7, sp, #0 + /* USER CODE END LPTIM1_Init 0 */ + + /* USER CODE BEGIN LPTIM1_Init 1 */ + + /* USER CODE END LPTIM1_Init 1 */ + hlptim1.Instance = LPTIM1; + 8000bbc: 4b13 ldr r3, [pc, #76] ; (8000c0c ) + 8000bbe: 4a14 ldr r2, [pc, #80] ; (8000c10 ) + 8000bc0: 601a str r2, [r3, #0] + hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + 8000bc2: 4b12 ldr r3, [pc, #72] ; (8000c0c ) + 8000bc4: 2200 movs r2, #0 + 8000bc6: 605a str r2, [r3, #4] + hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + 8000bc8: 4b10 ldr r3, [pc, #64] ; (8000c0c ) + 8000bca: 2200 movs r2, #0 + 8000bcc: 609a str r2, [r3, #8] + hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING; + 8000bce: 4b0f ldr r3, [pc, #60] ; (8000c0c ) + 8000bd0: 2200 movs r2, #0 + 8000bd2: 60da str r2, [r3, #12] + hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION; + 8000bd4: 4b0d ldr r3, [pc, #52] ; (8000c0c ) + 8000bd6: 2200 movs r2, #0 + 8000bd8: 611a str r2, [r3, #16] + hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + 8000bda: 4b0c ldr r3, [pc, #48] ; (8000c0c ) + 8000bdc: 4a0d ldr r2, [pc, #52] ; (8000c14 ) + 8000bde: 615a str r2, [r3, #20] + hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + 8000be0: 4b0a ldr r3, [pc, #40] ; (8000c0c ) + 8000be2: 2200 movs r2, #0 + 8000be4: 621a str r2, [r3, #32] + hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + 8000be6: 4b09 ldr r3, [pc, #36] ; (8000c0c ) + 8000be8: 2200 movs r2, #0 + 8000bea: 625a str r2, [r3, #36] ; 0x24 + hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL; + 8000bec: 4b07 ldr r3, [pc, #28] ; (8000c0c ) + 8000bee: 2280 movs r2, #128 ; 0x80 + 8000bf0: 0412 lsls r2, r2, #16 + 8000bf2: 629a str r2, [r3, #40] ; 0x28 + if (HAL_LPTIM_Init(&hlptim1) != HAL_OK) + 8000bf4: 4b05 ldr r3, [pc, #20] ; (8000c0c ) + 8000bf6: 0018 movs r0, r3 + 8000bf8: f001 fcc6 bl 8002588 + 8000bfc: 1e03 subs r3, r0, #0 + 8000bfe: d001 beq.n 8000c04 + { + Error_Handler(); + 8000c00: f000 fa18 bl 8001034 + } + /* USER CODE BEGIN LPTIM1_Init 2 */ + + /* USER CODE END LPTIM1_Init 2 */ + +} + 8000c04: 46c0 nop ; (mov r8, r8) + 8000c06: 46bd mov sp, r7 + 8000c08: bd80 pop {r7, pc} + 8000c0a: 46c0 nop ; (mov r8, r8) + 8000c0c: 200017b8 .word 0x200017b8 + 8000c10: 40007c00 .word 0x40007c00 + 8000c14: 0000ffff .word 0x0000ffff + +08000c18 : + * @brief LPUART1 Initialization Function + * @param None + * @retval None + */ +static void MX_LPUART1_UART_Init(void) +{ + 8000c18: b580 push {r7, lr} + 8000c1a: af00 add r7, sp, #0 + /* USER CODE END LPUART1_Init 0 */ + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + 8000c1c: 4b13 ldr r3, [pc, #76] ; (8000c6c ) + 8000c1e: 4a14 ldr r2, [pc, #80] ; (8000c70 ) + 8000c20: 601a str r2, [r3, #0] + hlpuart1.Init.BaudRate = 9600; + 8000c22: 4b12 ldr r3, [pc, #72] ; (8000c6c ) + 8000c24: 2296 movs r2, #150 ; 0x96 + 8000c26: 0192 lsls r2, r2, #6 + 8000c28: 605a str r2, [r3, #4] + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + 8000c2a: 4b10 ldr r3, [pc, #64] ; (8000c6c ) + 8000c2c: 2200 movs r2, #0 + 8000c2e: 609a str r2, [r3, #8] + hlpuart1.Init.StopBits = UART_STOPBITS_1; + 8000c30: 4b0e ldr r3, [pc, #56] ; (8000c6c ) + 8000c32: 2200 movs r2, #0 + 8000c34: 60da str r2, [r3, #12] + hlpuart1.Init.Parity = UART_PARITY_NONE; + 8000c36: 4b0d ldr r3, [pc, #52] ; (8000c6c ) + 8000c38: 2200 movs r2, #0 + 8000c3a: 611a str r2, [r3, #16] + hlpuart1.Init.Mode = UART_MODE_TX_RX; + 8000c3c: 4b0b ldr r3, [pc, #44] ; (8000c6c ) + 8000c3e: 220c movs r2, #12 + 8000c40: 615a str r2, [r3, #20] + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8000c42: 4b0a ldr r3, [pc, #40] ; (8000c6c ) + 8000c44: 2200 movs r2, #0 + 8000c46: 619a str r2, [r3, #24] + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8000c48: 4b08 ldr r3, [pc, #32] ; (8000c6c ) + 8000c4a: 2200 movs r2, #0 + 8000c4c: 621a str r2, [r3, #32] + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 8000c4e: 4b07 ldr r3, [pc, #28] ; (8000c6c ) + 8000c50: 2200 movs r2, #0 + 8000c52: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&hlpuart1) != HAL_OK) + 8000c54: 4b05 ldr r3, [pc, #20] ; (8000c6c ) + 8000c56: 0018 movs r0, r3 + 8000c58: f003 f8e2 bl 8003e20 + 8000c5c: 1e03 subs r3, r0, #0 + 8000c5e: d001 beq.n 8000c64 + { + Error_Handler(); + 8000c60: f000 f9e8 bl 8001034 + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ + +} + 8000c64: 46c0 nop ; (mov r8, r8) + 8000c66: 46bd mov sp, r7 + 8000c68: bd80 pop {r7, pc} + 8000c6a: 46c0 nop ; (mov r8, r8) + 8000c6c: 20001734 .word 0x20001734 + 8000c70: 40004800 .word 0x40004800 + +08000c74 : + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + 8000c74: b580 push {r7, lr} + 8000c76: b08a sub sp, #40 ; 0x28 + 8000c78: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 8000c7a: 2318 movs r3, #24 + 8000c7c: 18fb adds r3, r7, r3 + 8000c7e: 0018 movs r0, r3 + 8000c80: 2310 movs r3, #16 + 8000c82: 001a movs r2, r3 + 8000c84: 2100 movs r1, #0 + 8000c86: f006 fd9a bl 80077be + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000c8a: 2310 movs r3, #16 + 8000c8c: 18fb adds r3, r7, r3 + 8000c8e: 0018 movs r0, r3 + 8000c90: 2308 movs r3, #8 + 8000c92: 001a movs r2, r3 + 8000c94: 2100 movs r1, #0 + 8000c96: f006 fd92 bl 80077be + TIM_OC_InitTypeDef sConfigOC = {0}; + 8000c9a: 003b movs r3, r7 + 8000c9c: 0018 movs r0, r3 + 8000c9e: 2310 movs r3, #16 + 8000ca0: 001a movs r2, r3 + 8000ca2: 2100 movs r1, #0 + 8000ca4: f006 fd8b bl 80077be + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8000ca8: 4b3f ldr r3, [pc, #252] ; (8000da8 ) + 8000caa: 2280 movs r2, #128 ; 0x80 + 8000cac: 05d2 lsls r2, r2, #23 + 8000cae: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 0; + 8000cb0: 4b3d ldr r3, [pc, #244] ; (8000da8 ) + 8000cb2: 2200 movs r2, #0 + 8000cb4: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000cb6: 4b3c ldr r3, [pc, #240] ; (8000da8 ) + 8000cb8: 2200 movs r2, #0 + 8000cba: 609a str r2, [r3, #8] + htim2.Init.Period = 255; + 8000cbc: 4b3a ldr r3, [pc, #232] ; (8000da8 ) + 8000cbe: 22ff movs r2, #255 ; 0xff + 8000cc0: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000cc2: 4b39 ldr r3, [pc, #228] ; (8000da8 ) + 8000cc4: 2200 movs r2, #0 + 8000cc6: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000cc8: 4b37 ldr r3, [pc, #220] ; (8000da8 ) + 8000cca: 2200 movs r2, #0 + 8000ccc: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + 8000cce: 4b36 ldr r3, [pc, #216] ; (8000da8 ) + 8000cd0: 0018 movs r0, r3 + 8000cd2: f002 fbab bl 800342c + 8000cd6: 1e03 subs r3, r0, #0 + 8000cd8: d001 beq.n 8000cde + { + Error_Handler(); + 8000cda: f000 f9ab bl 8001034 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8000cde: 2118 movs r1, #24 + 8000ce0: 187b adds r3, r7, r1 + 8000ce2: 2280 movs r2, #128 ; 0x80 + 8000ce4: 0152 lsls r2, r2, #5 + 8000ce6: 601a str r2, [r3, #0] + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + 8000ce8: 187a adds r2, r7, r1 + 8000cea: 4b2f ldr r3, [pc, #188] ; (8000da8 ) + 8000cec: 0011 movs r1, r2 + 8000cee: 0018 movs r0, r3 + 8000cf0: f002 fd8a bl 8003808 + 8000cf4: 1e03 subs r3, r0, #0 + 8000cf6: d001 beq.n 8000cfc + { + Error_Handler(); + 8000cf8: f000 f99c bl 8001034 + } + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) + 8000cfc: 4b2a ldr r3, [pc, #168] ; (8000da8 ) + 8000cfe: 0018 movs r0, r3 + 8000d00: f002 fbd4 bl 80034ac + 8000d04: 1e03 subs r3, r0, #0 + 8000d06: d001 beq.n 8000d0c + { + Error_Handler(); + 8000d08: f000 f994 bl 8001034 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000d0c: 2110 movs r1, #16 + 8000d0e: 187b adds r3, r7, r1 + 8000d10: 2200 movs r2, #0 + 8000d12: 601a str r2, [r3, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000d14: 187b adds r3, r7, r1 + 8000d16: 2200 movs r2, #0 + 8000d18: 605a str r2, [r3, #4] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 8000d1a: 187a adds r2, r7, r1 + 8000d1c: 4b22 ldr r3, [pc, #136] ; (8000da8 ) + 8000d1e: 0011 movs r1, r2 + 8000d20: 0018 movs r0, r3 + 8000d22: f003 f82d bl 8003d80 + 8000d26: 1e03 subs r3, r0, #0 + 8000d28: d001 beq.n 8000d2e + { + Error_Handler(); + 8000d2a: f000 f983 bl 8001034 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 8000d2e: 003b movs r3, r7 + 8000d30: 2260 movs r2, #96 ; 0x60 + 8000d32: 601a str r2, [r3, #0] + sConfigOC.Pulse = 0; + 8000d34: 003b movs r3, r7 + 8000d36: 2200 movs r2, #0 + 8000d38: 605a str r2, [r3, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 8000d3a: 003b movs r3, r7 + 8000d3c: 2200 movs r2, #0 + 8000d3e: 609a str r2, [r3, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 8000d40: 003b movs r3, r7 + 8000d42: 2200 movs r2, #0 + 8000d44: 60da str r2, [r3, #12] + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 8000d46: 0039 movs r1, r7 + 8000d48: 4b17 ldr r3, [pc, #92] ; (8000da8 ) + 8000d4a: 2200 movs r2, #0 + 8000d4c: 0018 movs r0, r3 + 8000d4e: f002 fc95 bl 800367c + 8000d52: 1e03 subs r3, r0, #0 + 8000d54: d001 beq.n 8000d5a + { + Error_Handler(); + 8000d56: f000 f96d bl 8001034 + } + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + 8000d5a: 0039 movs r1, r7 + 8000d5c: 4b12 ldr r3, [pc, #72] ; (8000da8 ) + 8000d5e: 2204 movs r2, #4 + 8000d60: 0018 movs r0, r3 + 8000d62: f002 fc8b bl 800367c + 8000d66: 1e03 subs r3, r0, #0 + 8000d68: d001 beq.n 8000d6e + { + Error_Handler(); + 8000d6a: f000 f963 bl 8001034 + } + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + 8000d6e: 0039 movs r1, r7 + 8000d70: 4b0d ldr r3, [pc, #52] ; (8000da8 ) + 8000d72: 2208 movs r2, #8 + 8000d74: 0018 movs r0, r3 + 8000d76: f002 fc81 bl 800367c + 8000d7a: 1e03 subs r3, r0, #0 + 8000d7c: d001 beq.n 8000d82 + { + Error_Handler(); + 8000d7e: f000 f959 bl 8001034 + } + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + 8000d82: 0039 movs r1, r7 + 8000d84: 4b08 ldr r3, [pc, #32] ; (8000da8 ) + 8000d86: 220c movs r2, #12 + 8000d88: 0018 movs r0, r3 + 8000d8a: f002 fc77 bl 800367c + 8000d8e: 1e03 subs r3, r0, #0 + 8000d90: d001 beq.n 8000d96 + { + Error_Handler(); + 8000d92: f000 f94f bl 8001034 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); + 8000d96: 4b04 ldr r3, [pc, #16] ; (8000da8 ) + 8000d98: 0018 movs r0, r3 + 8000d9a: f000 fb93 bl 80014c4 + +} + 8000d9e: 46c0 nop ; (mov r8, r8) + 8000da0: 46bd mov sp, r7 + 8000da2: b00a add sp, #40 ; 0x28 + 8000da4: bd80 pop {r7, pc} + 8000da6: 46c0 nop ; (mov r8, r8) + 8000da8: 20001878 .word 0x20001878 + +08000dac : + * @brief TIM21 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM21_Init(void) +{ + 8000dac: b590 push {r4, r7, lr} + 8000dae: b08d sub sp, #52 ; 0x34 + 8000db0: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM21_Init 0 */ + + /* USER CODE END TIM21_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = {0}; + 8000db2: 240c movs r4, #12 + 8000db4: 193b adds r3, r7, r4 + 8000db6: 0018 movs r0, r3 + 8000db8: 2324 movs r3, #36 ; 0x24 + 8000dba: 001a movs r2, r3 + 8000dbc: 2100 movs r1, #0 + 8000dbe: f006 fcfe bl 80077be + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000dc2: 1d3b adds r3, r7, #4 + 8000dc4: 0018 movs r0, r3 + 8000dc6: 2308 movs r3, #8 + 8000dc8: 001a movs r2, r3 + 8000dca: 2100 movs r1, #0 + 8000dcc: f006 fcf7 bl 80077be + + /* USER CODE BEGIN TIM21_Init 1 */ + + /* USER CODE END TIM21_Init 1 */ + htim21.Instance = TIM21; + 8000dd0: 4b25 ldr r3, [pc, #148] ; (8000e68 ) + 8000dd2: 4a26 ldr r2, [pc, #152] ; (8000e6c ) + 8000dd4: 601a str r2, [r3, #0] + htim21.Init.Prescaler = 0; + 8000dd6: 4b24 ldr r3, [pc, #144] ; (8000e68 ) + 8000dd8: 2200 movs r2, #0 + 8000dda: 605a str r2, [r3, #4] + htim21.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000ddc: 4b22 ldr r3, [pc, #136] ; (8000e68 ) + 8000dde: 2200 movs r2, #0 + 8000de0: 609a str r2, [r3, #8] + htim21.Init.Period = 65535; + 8000de2: 4b21 ldr r3, [pc, #132] ; (8000e68 ) + 8000de4: 4a22 ldr r2, [pc, #136] ; (8000e70 ) + 8000de6: 60da str r2, [r3, #12] + htim21.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000de8: 4b1f ldr r3, [pc, #124] ; (8000e68 ) + 8000dea: 2200 movs r2, #0 + 8000dec: 611a str r2, [r3, #16] + htim21.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000dee: 4b1e ldr r3, [pc, #120] ; (8000e68 ) + 8000df0: 2200 movs r2, #0 + 8000df2: 615a str r2, [r3, #20] + sConfig.EncoderMode = TIM_ENCODERMODE_TI1; + 8000df4: 0021 movs r1, r4 + 8000df6: 187b adds r3, r7, r1 + 8000df8: 2201 movs r2, #1 + 8000dfa: 601a str r2, [r3, #0] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 8000dfc: 187b adds r3, r7, r1 + 8000dfe: 2200 movs r2, #0 + 8000e00: 605a str r2, [r3, #4] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8000e02: 187b adds r3, r7, r1 + 8000e04: 2201 movs r2, #1 + 8000e06: 609a str r2, [r3, #8] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 8000e08: 187b adds r3, r7, r1 + 8000e0a: 2200 movs r2, #0 + 8000e0c: 60da str r2, [r3, #12] + sConfig.IC1Filter = 0; + 8000e0e: 187b adds r3, r7, r1 + 8000e10: 2200 movs r2, #0 + 8000e12: 611a str r2, [r3, #16] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 8000e14: 187b adds r3, r7, r1 + 8000e16: 2200 movs r2, #0 + 8000e18: 615a str r2, [r3, #20] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 8000e1a: 187b adds r3, r7, r1 + 8000e1c: 2201 movs r2, #1 + 8000e1e: 619a str r2, [r3, #24] + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 8000e20: 187b adds r3, r7, r1 + 8000e22: 2200 movs r2, #0 + 8000e24: 61da str r2, [r3, #28] + sConfig.IC2Filter = 0; + 8000e26: 187b adds r3, r7, r1 + 8000e28: 2200 movs r2, #0 + 8000e2a: 621a str r2, [r3, #32] + if (HAL_TIM_Encoder_Init(&htim21, &sConfig) != HAL_OK) + 8000e2c: 187a adds r2, r7, r1 + 8000e2e: 4b0e ldr r3, [pc, #56] ; (8000e68 ) + 8000e30: 0011 movs r1, r2 + 8000e32: 0018 movs r0, r3 + 8000e34: f002 fb82 bl 800353c + 8000e38: 1e03 subs r3, r0, #0 + 8000e3a: d001 beq.n 8000e40 + { + Error_Handler(); + 8000e3c: f000 f8fa bl 8001034 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000e40: 1d3b adds r3, r7, #4 + 8000e42: 2200 movs r2, #0 + 8000e44: 601a str r2, [r3, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000e46: 1d3b adds r3, r7, #4 + 8000e48: 2200 movs r2, #0 + 8000e4a: 605a str r2, [r3, #4] + if (HAL_TIMEx_MasterConfigSynchronization(&htim21, &sMasterConfig) != HAL_OK) + 8000e4c: 1d3a adds r2, r7, #4 + 8000e4e: 4b06 ldr r3, [pc, #24] ; (8000e68 ) + 8000e50: 0011 movs r1, r2 + 8000e52: 0018 movs r0, r3 + 8000e54: f002 ff94 bl 8003d80 + 8000e58: 1e03 subs r3, r0, #0 + 8000e5a: d001 beq.n 8000e60 + { + Error_Handler(); + 8000e5c: f000 f8ea bl 8001034 + } + /* USER CODE BEGIN TIM21_Init 2 */ + + /* USER CODE END TIM21_Init 2 */ + +} + 8000e60: 46c0 nop ; (mov r8, r8) + 8000e62: 46bd mov sp, r7 + 8000e64: b00d add sp, #52 ; 0x34 + 8000e66: bd90 pop {r4, r7, pc} + 8000e68: 20001914 .word 0x20001914 + 8000e6c: 40010800 .word 0x40010800 + 8000e70: 0000ffff .word 0x0000ffff + +08000e74 : + +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + 8000e74: b580 push {r7, lr} + 8000e76: b082 sub sp, #8 + 8000e78: af00 add r7, sp, #0 + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + 8000e7a: 4b0c ldr r3, [pc, #48] ; (8000eac ) + 8000e7c: 6b1a ldr r2, [r3, #48] ; 0x30 + 8000e7e: 4b0b ldr r3, [pc, #44] ; (8000eac ) + 8000e80: 2101 movs r1, #1 + 8000e82: 430a orrs r2, r1 + 8000e84: 631a str r2, [r3, #48] ; 0x30 + 8000e86: 4b09 ldr r3, [pc, #36] ; (8000eac ) + 8000e88: 6b1b ldr r3, [r3, #48] ; 0x30 + 8000e8a: 2201 movs r2, #1 + 8000e8c: 4013 ands r3, r2 + 8000e8e: 607b str r3, [r7, #4] + 8000e90: 687b ldr r3, [r7, #4] + + /* DMA interrupt init */ + /* DMA1_Channel2_3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3, 0); + 8000e92: 2200 movs r2, #0 + 8000e94: 2103 movs r1, #3 + 8000e96: 200a movs r0, #10 + 8000e98: f000 ffe4 bl 8001e64 + HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + 8000e9c: 200a movs r0, #10 + 8000e9e: f000 fff6 bl 8001e8e + +} + 8000ea2: 46c0 nop ; (mov r8, r8) + 8000ea4: 46bd mov sp, r7 + 8000ea6: b002 add sp, #8 + 8000ea8: bd80 pop {r7, pc} + 8000eaa: 46c0 nop ; (mov r8, r8) + 8000eac: 40021000 .word 0x40021000 + +08000eb0 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000eb0: b590 push {r4, r7, lr} + 8000eb2: b089 sub sp, #36 ; 0x24 + 8000eb4: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000eb6: 240c movs r4, #12 + 8000eb8: 193b adds r3, r7, r4 + 8000eba: 0018 movs r0, r3 + 8000ebc: 2314 movs r3, #20 + 8000ebe: 001a movs r2, r3 + 8000ec0: 2100 movs r1, #0 + 8000ec2: f006 fc7c bl 80077be + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000ec6: 4b44 ldr r3, [pc, #272] ; (8000fd8 ) + 8000ec8: 6ada ldr r2, [r3, #44] ; 0x2c + 8000eca: 4b43 ldr r3, [pc, #268] ; (8000fd8 ) + 8000ecc: 2104 movs r1, #4 + 8000ece: 430a orrs r2, r1 + 8000ed0: 62da str r2, [r3, #44] ; 0x2c + 8000ed2: 4b41 ldr r3, [pc, #260] ; (8000fd8 ) + 8000ed4: 6adb ldr r3, [r3, #44] ; 0x2c + 8000ed6: 2204 movs r2, #4 + 8000ed8: 4013 ands r3, r2 + 8000eda: 60bb str r3, [r7, #8] + 8000edc: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000ede: 4b3e ldr r3, [pc, #248] ; (8000fd8 ) + 8000ee0: 6ada ldr r2, [r3, #44] ; 0x2c + 8000ee2: 4b3d ldr r3, [pc, #244] ; (8000fd8 ) + 8000ee4: 2101 movs r1, #1 + 8000ee6: 430a orrs r2, r1 + 8000ee8: 62da str r2, [r3, #44] ; 0x2c + 8000eea: 4b3b ldr r3, [pc, #236] ; (8000fd8 ) + 8000eec: 6adb ldr r3, [r3, #44] ; 0x2c + 8000eee: 2201 movs r2, #1 + 8000ef0: 4013 ands r3, r2 + 8000ef2: 607b str r3, [r7, #4] + 8000ef4: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000ef6: 4b38 ldr r3, [pc, #224] ; (8000fd8 ) + 8000ef8: 6ada ldr r2, [r3, #44] ; 0x2c + 8000efa: 4b37 ldr r3, [pc, #220] ; (8000fd8 ) + 8000efc: 2102 movs r1, #2 + 8000efe: 430a orrs r2, r1 + 8000f00: 62da str r2, [r3, #44] ; 0x2c + 8000f02: 4b35 ldr r3, [pc, #212] ; (8000fd8 ) + 8000f04: 6adb ldr r3, [r3, #44] ; 0x2c + 8000f06: 2202 movs r2, #2 + 8000f08: 4013 ands r3, r2 + 8000f0a: 603b str r3, [r7, #0] + 8000f0c: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin|SHUTDOWN_ENCODERS_Pin + 8000f0e: 23f1 movs r3, #241 ; 0xf1 + 8000f10: 021b lsls r3, r3, #8 + 8000f12: 4832 ldr r0, [pc, #200] ; (8000fdc ) + 8000f14: 2200 movs r2, #0 + 8000f16: 0019 movs r1, r3 + 8000f18: f001 faf2 bl 8002500 + |SHUTDOWN_5V_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(SHUTDOWN_GPIO_Port, SHUTDOWN_Pin, GPIO_PIN_SET); + 8000f1c: 2380 movs r3, #128 ; 0x80 + 8000f1e: 009b lsls r3, r3, #2 + 8000f20: 482e ldr r0, [pc, #184] ; (8000fdc ) + 8000f22: 2201 movs r2, #1 + 8000f24: 0019 movs r1, r3 + 8000f26: f001 faeb bl 8002500 + + /*Configure GPIO pins : LED_ROUGE_Pin LED_ORANGE_Pin LED_VERTE_Pin */ + GPIO_InitStruct.Pin = LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin; + 8000f2a: 193b adds r3, r7, r4 + 8000f2c: 22e0 movs r2, #224 ; 0xe0 + 8000f2e: 01d2 lsls r2, r2, #7 + 8000f30: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000f32: 193b adds r3, r7, r4 + 8000f34: 2201 movs r2, #1 + 8000f36: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000f38: 193b adds r3, r7, r4 + 8000f3a: 2200 movs r2, #0 + 8000f3c: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000f3e: 193b adds r3, r7, r4 + 8000f40: 2203 movs r2, #3 + 8000f42: 60da str r2, [r3, #12] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000f44: 193b adds r3, r7, r4 + 8000f46: 4a25 ldr r2, [pc, #148] ; (8000fdc ) + 8000f48: 0019 movs r1, r3 + 8000f4a: 0010 movs r0, r2 + 8000f4c: f001 f96a bl 8002224 + + /*Configure GPIO pins : SHUTDOWN_ENCODERS_Pin SHUTDOWN_5V_Pin SHUTDOWN_Pin */ + GPIO_InitStruct.Pin = SHUTDOWN_ENCODERS_Pin|SHUTDOWN_5V_Pin|SHUTDOWN_Pin; + 8000f50: 0021 movs r1, r4 + 8000f52: 187b adds r3, r7, r1 + 8000f54: 2283 movs r2, #131 ; 0x83 + 8000f56: 0212 lsls r2, r2, #8 + 8000f58: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000f5a: 000c movs r4, r1 + 8000f5c: 193b adds r3, r7, r4 + 8000f5e: 2201 movs r2, #1 + 8000f60: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000f62: 193b adds r3, r7, r4 + 8000f64: 2200 movs r2, #0 + 8000f66: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000f68: 193b adds r3, r7, r4 + 8000f6a: 2200 movs r2, #0 + 8000f6c: 60da str r2, [r3, #12] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000f6e: 193b adds r3, r7, r4 + 8000f70: 4a1a ldr r2, [pc, #104] ; (8000fdc ) + 8000f72: 0019 movs r1, r3 + 8000f74: 0010 movs r0, r2 + 8000f76: f001 f955 bl 8002224 + + /*Configure GPIO pins : BUTTON_SENSE_Pin USB_SENSE_Pin */ + GPIO_InitStruct.Pin = BUTTON_SENSE_Pin|USB_SENSE_Pin; + 8000f7a: 0021 movs r1, r4 + 8000f7c: 187b adds r3, r7, r1 + 8000f7e: 2218 movs r2, #24 + 8000f80: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 8000f82: 187b adds r3, r7, r1 + 8000f84: 2288 movs r2, #136 ; 0x88 + 8000f86: 0352 lsls r2, r2, #13 + 8000f88: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000f8a: 187b adds r3, r7, r1 + 8000f8c: 2200 movs r2, #0 + 8000f8e: 609a str r2, [r3, #8] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000f90: 000c movs r4, r1 + 8000f92: 187b adds r3, r7, r1 + 8000f94: 4a11 ldr r2, [pc, #68] ; (8000fdc ) + 8000f96: 0019 movs r1, r3 + 8000f98: 0010 movs r0, r2 + 8000f9a: f001 f943 bl 8002224 + + /*Configure GPIO pins : CHARGER_ST2_Pin CHARGER_ST1_Pin */ + GPIO_InitStruct.Pin = CHARGER_ST2_Pin|CHARGER_ST1_Pin; + 8000f9e: 0021 movs r1, r4 + 8000fa0: 187b adds r3, r7, r1 + 8000fa2: 22c0 movs r2, #192 ; 0xc0 + 8000fa4: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8000fa6: 187b adds r3, r7, r1 + 8000fa8: 2200 movs r2, #0 + 8000faa: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000fac: 187b adds r3, r7, r1 + 8000fae: 2200 movs r2, #0 + 8000fb0: 609a str r2, [r3, #8] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000fb2: 187b adds r3, r7, r1 + 8000fb4: 4a09 ldr r2, [pc, #36] ; (8000fdc ) + 8000fb6: 0019 movs r1, r3 + 8000fb8: 0010 movs r0, r2 + 8000fba: f001 f933 bl 8002224 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI2_3_IRQn, 3, 0); + 8000fbe: 2200 movs r2, #0 + 8000fc0: 2103 movs r1, #3 + 8000fc2: 2006 movs r0, #6 + 8000fc4: f000 ff4e bl 8001e64 + HAL_NVIC_EnableIRQ(EXTI2_3_IRQn); + 8000fc8: 2006 movs r0, #6 + 8000fca: f000 ff60 bl 8001e8e +} + 8000fce: 46c0 nop ; (mov r8, r8) + 8000fd0: 46bd mov sp, r7 + 8000fd2: b009 add sp, #36 ; 0x24 + 8000fd4: bd90 pop {r4, r7, pc} + 8000fd6: 46c0 nop ; (mov r8, r8) + 8000fd8: 40021000 .word 0x40021000 + 8000fdc: 50000400 .word 0x50000400 + +08000fe0 : + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void *argument) +{ + 8000fe0: b590 push {r4, r7, lr} + 8000fe2: b085 sub sp, #20 + 8000fe4: af00 add r7, sp, #0 + 8000fe6: 6078 str r0, [r7, #4] + /* USER CODE BEGIN 5 */ + LEDS_State state = leds_off; + 8000fe8: 230f movs r3, #15 + 8000fea: 18fb adds r3, r7, r3 + 8000fec: 2200 movs r2, #0 + 8000fee: 701a strb r2, [r3, #0] + + /* Infinite loop */ + for(;;) + { + state++; + 8000ff0: 210f movs r1, #15 + 8000ff2: 187b adds r3, r7, r1 + 8000ff4: 781b ldrb r3, [r3, #0] + 8000ff6: 3301 adds r3, #1 + 8000ff8: b2da uxtb r2, r3 + 8000ffa: 187b adds r3, r7, r1 + 8000ffc: 701a strb r2, [r3, #0] + MESSAGE_SendMailbox(LEDS_Mailbox, MSG_ID_LED_ETAT, SEQUENCEUR_Mailbox, (void*)&state); + 8000ffe: 4b0b ldr r3, [pc, #44] ; (800102c ) + 8001000: 6818 ldr r0, [r3, #0] + 8001002: 4b0b ldr r3, [pc, #44] ; (8001030 ) + 8001004: 681a ldr r2, [r3, #0] + 8001006: 000c movs r4, r1 + 8001008: 187b adds r3, r7, r1 + 800100a: 2100 movs r1, #0 + 800100c: f000 f872 bl 80010f4 + + if (state>leds_erreur) + 8001010: 0021 movs r1, r4 + 8001012: 187b adds r3, r7, r1 + 8001014: 781b ldrb r3, [r3, #0] + 8001016: 2b10 cmp r3, #16 + 8001018: d902 bls.n 8001020 + state = leds_off; + 800101a: 187b adds r3, r7, r1 + 800101c: 2200 movs r2, #0 + 800101e: 701a strb r2, [r3, #0] + + vTaskDelay(pdMS_TO_TICKS(5000)); + 8001020: 23fa movs r3, #250 ; 0xfa + 8001022: 005b lsls r3, r3, #1 + 8001024: 0018 movs r0, r3 + 8001026: f004 fedb bl 8005de0 + state++; + 800102a: e7e1 b.n 8000ff0 + 800102c: 20001964 .word 0x20001964 + 8001030: 20001960 .word 0x20001960 + +08001034 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8001034: b580 push {r7, lr} + 8001036: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8001038: b672 cpsid i +} + 800103a: 46c0 nop ; (mov r8, r8) + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 800103c: e7fe b.n 800103c + ... + +08001040 : +QueueHandle_t MOTEURS_Mailbox; +QueueHandle_t SEQUENCEUR_Mailbox; +QueueHandle_t BATTERIE_Mailbox; +QueueHandle_t XBEE_Mailbox; + +void MESSAGE_Init(void) { + 8001040: b580 push {r7, lr} + 8001042: af00 add r7, sp, #0 + LEDS_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + 8001044: 2200 movs r2, #0 + 8001046: 210c movs r1, #12 + 8001048: 2005 movs r0, #5 + 800104a: f004 f980 bl 800534e + 800104e: 0002 movs r2, r0 + 8001050: 4b12 ldr r3, [pc, #72] ; (800109c ) + 8001052: 601a str r2, [r3, #0] + MOTEURS_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + 8001054: 2200 movs r2, #0 + 8001056: 210c movs r1, #12 + 8001058: 2005 movs r0, #5 + 800105a: f004 f978 bl 800534e + 800105e: 0002 movs r2, r0 + 8001060: 4b0f ldr r3, [pc, #60] ; (80010a0 ) + 8001062: 601a str r2, [r3, #0] + SEQUENCEUR_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + 8001064: 2200 movs r2, #0 + 8001066: 210c movs r1, #12 + 8001068: 2005 movs r0, #5 + 800106a: f004 f970 bl 800534e + 800106e: 0002 movs r2, r0 + 8001070: 4b0c ldr r3, [pc, #48] ; (80010a4 ) + 8001072: 601a str r2, [r3, #0] + BATTERIE_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + 8001074: 2200 movs r2, #0 + 8001076: 210c movs r1, #12 + 8001078: 2005 movs r0, #5 + 800107a: f004 f968 bl 800534e + 800107e: 0002 movs r2, r0 + 8001080: 4b09 ldr r3, [pc, #36] ; (80010a8 ) + 8001082: 601a str r2, [r3, #0] + XBEE_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef)); + 8001084: 2200 movs r2, #0 + 8001086: 210c movs r1, #12 + 8001088: 2005 movs r0, #5 + 800108a: f004 f960 bl 800534e + 800108e: 0002 movs r2, r0 + 8001090: 4b06 ldr r3, [pc, #24] ; (80010ac ) + 8001092: 601a str r2, [r3, #0] +} + 8001094: 46c0 nop ; (mov r8, r8) + 8001096: 46bd mov sp, r7 + 8001098: bd80 pop {r7, pc} + 800109a: 46c0 nop ; (mov r8, r8) + 800109c: 20001964 .word 0x20001964 + 80010a0: 20001958 .word 0x20001958 + 80010a4: 20001960 .word 0x20001960 + 80010a8: 2000195c .word 0x2000195c + 80010ac: 20001954 .word 0x20001954 + +080010b0 : + } + + return msg; +} + +MESSAGE_Typedef MESSAGE_ReadMailboxNoDelay(QueueHandle_t mbx) { + 80010b0: b590 push {r4, r7, lr} + 80010b2: b087 sub sp, #28 + 80010b4: af00 add r7, sp, #0 + 80010b6: 6078 str r0, [r7, #4] + 80010b8: 6039 str r1, [r7, #0] + MESSAGE_Typedef msg= {0}; + 80010ba: 240c movs r4, #12 + 80010bc: 193b adds r3, r7, r4 + 80010be: 0018 movs r0, r3 + 80010c0: 230c movs r3, #12 + 80010c2: 001a movs r2, r3 + 80010c4: 2100 movs r1, #0 + 80010c6: f006 fb7a bl 80077be + + if (!xQueueReceive(mbx, &msg, 0)) // Pas de message dans la mailbox + 80010ca: 1939 adds r1, r7, r4 + 80010cc: 683b ldr r3, [r7, #0] + 80010ce: 2200 movs r2, #0 + 80010d0: 0018 movs r0, r3 + 80010d2: f004 fad0 bl 8005676 + 80010d6: 1e03 subs r3, r0, #0 + 80010d8: d103 bne.n 80010e2 + msg.id=MSG_ID_NO_MESSAGE; + 80010da: 193b adds r3, r7, r4 + 80010dc: 2201 movs r2, #1 + 80010de: 4252 negs r2, r2 + 80010e0: 801a strh r2, [r3, #0] + + return msg; + 80010e2: 687b ldr r3, [r7, #4] + 80010e4: 220c movs r2, #12 + 80010e6: 18ba adds r2, r7, r2 + 80010e8: ca13 ldmia r2!, {r0, r1, r4} + 80010ea: c313 stmia r3!, {r0, r1, r4} +} + 80010ec: 6878 ldr r0, [r7, #4] + 80010ee: 46bd mov sp, r7 + 80010f0: b007 add sp, #28 + 80010f2: bd90 pop {r4, r7, pc} + +080010f4 : + +void MESSAGE_SendMailbox(QueueHandle_t mbx_dest, uint16_t id, QueueHandle_t mbx_sender, void *data){ + 80010f4: b580 push {r7, lr} + 80010f6: b088 sub sp, #32 + 80010f8: af00 add r7, sp, #0 + 80010fa: 60f8 str r0, [r7, #12] + 80010fc: 607a str r2, [r7, #4] + 80010fe: 603b str r3, [r7, #0] + 8001100: 200a movs r0, #10 + 8001102: 183b adds r3, r7, r0 + 8001104: 1c0a adds r2, r1, #0 + 8001106: 801a strh r2, [r3, #0] + MESSAGE_Typedef msg; + + msg.id=id; + 8001108: 2114 movs r1, #20 + 800110a: 187b adds r3, r7, r1 + 800110c: 183a adds r2, r7, r0 + 800110e: 8812 ldrh r2, [r2, #0] + 8001110: 801a strh r2, [r3, #0] + msg.sender = &mbx_sender; + 8001112: 187b adds r3, r7, r1 + 8001114: 1d3a adds r2, r7, #4 + 8001116: 605a str r2, [r3, #4] + msg.data=data; + 8001118: 187b adds r3, r7, r1 + 800111a: 683a ldr r2, [r7, #0] + 800111c: 609a str r2, [r3, #8] + + if (!xQueueSend(mbx_dest, &msg, 0)) { // envoi sans attendre + 800111e: 1879 adds r1, r7, r1 + 8001120: 68f8 ldr r0, [r7, #12] + 8001122: 2300 movs r3, #0 + 8001124: 2200 movs r2, #0 + 8001126: f004 f971 bl 800540c + //printf("Failed to send data, Queue full.\r\n"); + } +} + 800112a: 46c0 nop ; (mov r8, r8) + 800112c: 46bd mov sp, r7 + 800112e: b008 add sp, #32 + 8001130: bd80 pop {r7, pc} + ... + +08001134 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8001134: b580 push {r7, lr} + 8001136: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8001138: 4b0b ldr r3, [pc, #44] ; (8001168 ) + 800113a: 6b5a ldr r2, [r3, #52] ; 0x34 + 800113c: 4b0a ldr r3, [pc, #40] ; (8001168 ) + 800113e: 2101 movs r1, #1 + 8001140: 430a orrs r2, r1 + 8001142: 635a str r2, [r3, #52] ; 0x34 + __HAL_RCC_PWR_CLK_ENABLE(); + 8001144: 4b08 ldr r3, [pc, #32] ; (8001168 ) + 8001146: 6b9a ldr r2, [r3, #56] ; 0x38 + 8001148: 4b07 ldr r3, [pc, #28] ; (8001168 ) + 800114a: 2180 movs r1, #128 ; 0x80 + 800114c: 0549 lsls r1, r1, #21 + 800114e: 430a orrs r2, r1 + 8001150: 639a str r2, [r3, #56] ; 0x38 + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 3, 0); + 8001152: 2302 movs r3, #2 + 8001154: 425b negs r3, r3 + 8001156: 2200 movs r2, #0 + 8001158: 2103 movs r1, #3 + 800115a: 0018 movs r0, r3 + 800115c: f000 fe82 bl 8001e64 + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8001160: 46c0 nop ; (mov r8, r8) + 8001162: 46bd mov sp, r7 + 8001164: bd80 pop {r7, pc} + 8001166: 46c0 nop ; (mov r8, r8) + 8001168: 40021000 .word 0x40021000 + +0800116c : +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + 800116c: b590 push {r4, r7, lr} + 800116e: b089 sub sp, #36 ; 0x24 + 8001170: af00 add r7, sp, #0 + 8001172: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001174: 240c movs r4, #12 + 8001176: 193b adds r3, r7, r4 + 8001178: 0018 movs r0, r3 + 800117a: 2314 movs r3, #20 + 800117c: 001a movs r2, r3 + 800117e: 2100 movs r1, #0 + 8001180: f006 fb1d bl 80077be + if(hadc->Instance==ADC1) + 8001184: 687b ldr r3, [r7, #4] + 8001186: 681b ldr r3, [r3, #0] + 8001188: 4a18 ldr r2, [pc, #96] ; (80011ec ) + 800118a: 4293 cmp r3, r2 + 800118c: d12a bne.n 80011e4 + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + 800118e: 4b18 ldr r3, [pc, #96] ; (80011f0 ) + 8001190: 6b5a ldr r2, [r3, #52] ; 0x34 + 8001192: 4b17 ldr r3, [pc, #92] ; (80011f0 ) + 8001194: 2180 movs r1, #128 ; 0x80 + 8001196: 0089 lsls r1, r1, #2 + 8001198: 430a orrs r2, r1 + 800119a: 635a str r2, [r3, #52] ; 0x34 + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800119c: 4b14 ldr r3, [pc, #80] ; (80011f0 ) + 800119e: 6ada ldr r2, [r3, #44] ; 0x2c + 80011a0: 4b13 ldr r3, [pc, #76] ; (80011f0 ) + 80011a2: 2101 movs r1, #1 + 80011a4: 430a orrs r2, r1 + 80011a6: 62da str r2, [r3, #44] ; 0x2c + 80011a8: 4b11 ldr r3, [pc, #68] ; (80011f0 ) + 80011aa: 6adb ldr r3, [r3, #44] ; 0x2c + 80011ac: 2201 movs r2, #1 + 80011ae: 4013 ands r3, r2 + 80011b0: 60bb str r3, [r7, #8] + 80011b2: 68bb ldr r3, [r7, #8] + /**ADC GPIO Configuration + PA0 ------> ADC_IN0 + */ + GPIO_InitStruct.Pin = BATTERY_SENSE_Pin; + 80011b4: 193b adds r3, r7, r4 + 80011b6: 2201 movs r2, #1 + 80011b8: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80011ba: 193b adds r3, r7, r4 + 80011bc: 2203 movs r2, #3 + 80011be: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80011c0: 193b adds r3, r7, r4 + 80011c2: 2200 movs r2, #0 + 80011c4: 609a str r2, [r3, #8] + HAL_GPIO_Init(BATTERY_SENSE_GPIO_Port, &GPIO_InitStruct); + 80011c6: 193a adds r2, r7, r4 + 80011c8: 23a0 movs r3, #160 ; 0xa0 + 80011ca: 05db lsls r3, r3, #23 + 80011cc: 0011 movs r1, r2 + 80011ce: 0018 movs r0, r3 + 80011d0: f001 f828 bl 8002224 + + /* ADC1 interrupt Init */ + HAL_NVIC_SetPriority(ADC1_IRQn, 3, 0); + 80011d4: 2200 movs r2, #0 + 80011d6: 2103 movs r1, #3 + 80011d8: 200c movs r0, #12 + 80011da: f000 fe43 bl 8001e64 + HAL_NVIC_EnableIRQ(ADC1_IRQn); + 80011de: 200c movs r0, #12 + 80011e0: f000 fe55 bl 8001e8e + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + 80011e4: 46c0 nop ; (mov r8, r8) + 80011e6: 46bd mov sp, r7 + 80011e8: b009 add sp, #36 ; 0x24 + 80011ea: bd90 pop {r4, r7, pc} + 80011ec: 40012400 .word 0x40012400 + 80011f0: 40021000 .word 0x40021000 + +080011f4 : +* This function configures the hardware resources used in this example +* @param hlptim: LPTIM handle pointer +* @retval None +*/ +void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) +{ + 80011f4: b590 push {r4, r7, lr} + 80011f6: b08b sub sp, #44 ; 0x2c + 80011f8: af00 add r7, sp, #0 + 80011fa: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80011fc: 2414 movs r4, #20 + 80011fe: 193b adds r3, r7, r4 + 8001200: 0018 movs r0, r3 + 8001202: 2314 movs r3, #20 + 8001204: 001a movs r2, r3 + 8001206: 2100 movs r1, #0 + 8001208: f006 fad9 bl 80077be + if(hlptim->Instance==LPTIM1) + 800120c: 687b ldr r3, [r7, #4] + 800120e: 681b ldr r3, [r3, #0] + 8001210: 4a28 ldr r2, [pc, #160] ; (80012b4 ) + 8001212: 4293 cmp r3, r2 + 8001214: d14a bne.n 80012ac + { + /* USER CODE BEGIN LPTIM1_MspInit 0 */ + + /* USER CODE END LPTIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_LPTIM1_CLK_ENABLE(); + 8001216: 4b28 ldr r3, [pc, #160] ; (80012b8 ) + 8001218: 6b9a ldr r2, [r3, #56] ; 0x38 + 800121a: 4b27 ldr r3, [pc, #156] ; (80012b8 ) + 800121c: 2180 movs r1, #128 ; 0x80 + 800121e: 0609 lsls r1, r1, #24 + 8001220: 430a orrs r2, r1 + 8001222: 639a str r2, [r3, #56] ; 0x38 + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8001224: 4b24 ldr r3, [pc, #144] ; (80012b8 ) + 8001226: 6ada ldr r2, [r3, #44] ; 0x2c + 8001228: 4b23 ldr r3, [pc, #140] ; (80012b8 ) + 800122a: 2104 movs r1, #4 + 800122c: 430a orrs r2, r1 + 800122e: 62da str r2, [r3, #44] ; 0x2c + 8001230: 4b21 ldr r3, [pc, #132] ; (80012b8 ) + 8001232: 6adb ldr r3, [r3, #44] ; 0x2c + 8001234: 2204 movs r2, #4 + 8001236: 4013 ands r3, r2 + 8001238: 613b str r3, [r7, #16] + 800123a: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800123c: 4b1e ldr r3, [pc, #120] ; (80012b8 ) + 800123e: 6ada ldr r2, [r3, #44] ; 0x2c + 8001240: 4b1d ldr r3, [pc, #116] ; (80012b8 ) + 8001242: 2101 movs r1, #1 + 8001244: 430a orrs r2, r1 + 8001246: 62da str r2, [r3, #44] ; 0x2c + 8001248: 4b1b ldr r3, [pc, #108] ; (80012b8 ) + 800124a: 6adb ldr r3, [r3, #44] ; 0x2c + 800124c: 2201 movs r2, #1 + 800124e: 4013 ands r3, r2 + 8001250: 60fb str r3, [r7, #12] + 8001252: 68fb ldr r3, [r7, #12] + /**LPTIM1 GPIO Configuration + PC0 ------> LPTIM1_IN1 + PA5 ------> LPTIM1_IN2 + */ + GPIO_InitStruct.Pin = ENC_PHA_GAUCHE_Pin; + 8001254: 193b adds r3, r7, r4 + 8001256: 2201 movs r2, #1 + 8001258: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800125a: 193b adds r3, r7, r4 + 800125c: 2202 movs r2, #2 + 800125e: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001260: 193b adds r3, r7, r4 + 8001262: 2200 movs r2, #0 + 8001264: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001266: 193b adds r3, r7, r4 + 8001268: 2200 movs r2, #0 + 800126a: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF0_LPTIM1; + 800126c: 193b adds r3, r7, r4 + 800126e: 2200 movs r2, #0 + 8001270: 611a str r2, [r3, #16] + HAL_GPIO_Init(ENC_PHA_GAUCHE_GPIO_Port, &GPIO_InitStruct); + 8001272: 193b adds r3, r7, r4 + 8001274: 4a11 ldr r2, [pc, #68] ; (80012bc ) + 8001276: 0019 movs r1, r3 + 8001278: 0010 movs r0, r2 + 800127a: f000 ffd3 bl 8002224 + + GPIO_InitStruct.Pin = ENC_PHB_GAUCHE_Pin; + 800127e: 0021 movs r1, r4 + 8001280: 187b adds r3, r7, r1 + 8001282: 2220 movs r2, #32 + 8001284: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001286: 187b adds r3, r7, r1 + 8001288: 2202 movs r2, #2 + 800128a: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800128c: 187b adds r3, r7, r1 + 800128e: 2200 movs r2, #0 + 8001290: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001292: 187b adds r3, r7, r1 + 8001294: 2200 movs r2, #0 + 8001296: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF1_LPTIM1; + 8001298: 187b adds r3, r7, r1 + 800129a: 2201 movs r2, #1 + 800129c: 611a str r2, [r3, #16] + HAL_GPIO_Init(ENC_PHB_GAUCHE_GPIO_Port, &GPIO_InitStruct); + 800129e: 187a adds r2, r7, r1 + 80012a0: 23a0 movs r3, #160 ; 0xa0 + 80012a2: 05db lsls r3, r3, #23 + 80012a4: 0011 movs r1, r2 + 80012a6: 0018 movs r0, r3 + 80012a8: f000 ffbc bl 8002224 + /* USER CODE BEGIN LPTIM1_MspInit 1 */ + + /* USER CODE END LPTIM1_MspInit 1 */ + } + +} + 80012ac: 46c0 nop ; (mov r8, r8) + 80012ae: 46bd mov sp, r7 + 80012b0: b00b add sp, #44 ; 0x2c + 80012b2: bd90 pop {r4, r7, pc} + 80012b4: 40007c00 .word 0x40007c00 + 80012b8: 40021000 .word 0x40021000 + 80012bc: 50000800 .word 0x50000800 + +080012c0 : +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + 80012c0: b590 push {r4, r7, lr} + 80012c2: b089 sub sp, #36 ; 0x24 + 80012c4: af00 add r7, sp, #0 + 80012c6: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80012c8: 240c movs r4, #12 + 80012ca: 193b adds r3, r7, r4 + 80012cc: 0018 movs r0, r3 + 80012ce: 2314 movs r3, #20 + 80012d0: 001a movs r2, r3 + 80012d2: 2100 movs r1, #0 + 80012d4: f006 fa73 bl 80077be + if(huart->Instance==LPUART1) + 80012d8: 687b ldr r3, [r7, #4] + 80012da: 681b ldr r3, [r3, #0] + 80012dc: 4a46 ldr r2, [pc, #280] ; (80013f8 ) + 80012de: 4293 cmp r3, r2 + 80012e0: d000 beq.n 80012e4 + 80012e2: e085 b.n 80013f0 + { + /* USER CODE BEGIN LPUART1_MspInit 0 */ + + /* USER CODE END LPUART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + 80012e4: 4b45 ldr r3, [pc, #276] ; (80013fc ) + 80012e6: 6b9a ldr r2, [r3, #56] ; 0x38 + 80012e8: 4b44 ldr r3, [pc, #272] ; (80013fc ) + 80012ea: 2180 movs r1, #128 ; 0x80 + 80012ec: 02c9 lsls r1, r1, #11 + 80012ee: 430a orrs r2, r1 + 80012f0: 639a str r2, [r3, #56] ; 0x38 + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 80012f2: 4b42 ldr r3, [pc, #264] ; (80013fc ) + 80012f4: 6ada ldr r2, [r3, #44] ; 0x2c + 80012f6: 4b41 ldr r3, [pc, #260] ; (80013fc ) + 80012f8: 2102 movs r1, #2 + 80012fa: 430a orrs r2, r1 + 80012fc: 62da str r2, [r3, #44] ; 0x2c + 80012fe: 4b3f ldr r3, [pc, #252] ; (80013fc ) + 8001300: 6adb ldr r3, [r3, #44] ; 0x2c + 8001302: 2202 movs r2, #2 + 8001304: 4013 ands r3, r2 + 8001306: 60bb str r3, [r7, #8] + 8001308: 68bb ldr r3, [r7, #8] + /**LPUART1 GPIO Configuration + PB10 ------> LPUART1_TX + PB11 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; + 800130a: 193b adds r3, r7, r4 + 800130c: 22c0 movs r2, #192 ; 0xc0 + 800130e: 0112 lsls r2, r2, #4 + 8001310: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001312: 0021 movs r1, r4 + 8001314: 187b adds r3, r7, r1 + 8001316: 2202 movs r2, #2 + 8001318: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800131a: 187b adds r3, r7, r1 + 800131c: 2200 movs r2, #0 + 800131e: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001320: 187b adds r3, r7, r1 + 8001322: 2203 movs r2, #3 + 8001324: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF6_LPUART1; + 8001326: 187b adds r3, r7, r1 + 8001328: 2206 movs r2, #6 + 800132a: 611a str r2, [r3, #16] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800132c: 187b adds r3, r7, r1 + 800132e: 4a34 ldr r2, [pc, #208] ; (8001400 ) + 8001330: 0019 movs r1, r3 + 8001332: 0010 movs r0, r2 + 8001334: f000 ff76 bl 8002224 + + /* LPUART1 DMA Init */ + /* LPUART1_RX Init */ + hdma_lpuart1_rx.Instance = DMA1_Channel3; + 8001338: 4b32 ldr r3, [pc, #200] ; (8001404 ) + 800133a: 4a33 ldr r2, [pc, #204] ; (8001408 ) + 800133c: 601a str r2, [r3, #0] + hdma_lpuart1_rx.Init.Request = DMA_REQUEST_5; + 800133e: 4b31 ldr r3, [pc, #196] ; (8001404 ) + 8001340: 2205 movs r2, #5 + 8001342: 605a str r2, [r3, #4] + hdma_lpuart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + 8001344: 4b2f ldr r3, [pc, #188] ; (8001404 ) + 8001346: 2200 movs r2, #0 + 8001348: 609a str r2, [r3, #8] + hdma_lpuart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; + 800134a: 4b2e ldr r3, [pc, #184] ; (8001404 ) + 800134c: 2200 movs r2, #0 + 800134e: 60da str r2, [r3, #12] + hdma_lpuart1_rx.Init.MemInc = DMA_MINC_ENABLE; + 8001350: 4b2c ldr r3, [pc, #176] ; (8001404 ) + 8001352: 2280 movs r2, #128 ; 0x80 + 8001354: 611a str r2, [r3, #16] + hdma_lpuart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001356: 4b2b ldr r3, [pc, #172] ; (8001404 ) + 8001358: 2200 movs r2, #0 + 800135a: 615a str r2, [r3, #20] + hdma_lpuart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 800135c: 4b29 ldr r3, [pc, #164] ; (8001404 ) + 800135e: 2200 movs r2, #0 + 8001360: 619a str r2, [r3, #24] + hdma_lpuart1_rx.Init.Mode = DMA_NORMAL; + 8001362: 4b28 ldr r3, [pc, #160] ; (8001404 ) + 8001364: 2200 movs r2, #0 + 8001366: 61da str r2, [r3, #28] + hdma_lpuart1_rx.Init.Priority = DMA_PRIORITY_HIGH; + 8001368: 4b26 ldr r3, [pc, #152] ; (8001404 ) + 800136a: 2280 movs r2, #128 ; 0x80 + 800136c: 0192 lsls r2, r2, #6 + 800136e: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_lpuart1_rx) != HAL_OK) + 8001370: 4b24 ldr r3, [pc, #144] ; (8001404 ) + 8001372: 0018 movs r0, r3 + 8001374: f000 fda8 bl 8001ec8 + 8001378: 1e03 subs r3, r0, #0 + 800137a: d001 beq.n 8001380 + { + Error_Handler(); + 800137c: f7ff fe5a bl 8001034 + } + + __HAL_LINKDMA(huart,hdmarx,hdma_lpuart1_rx); + 8001380: 687b ldr r3, [r7, #4] + 8001382: 4a20 ldr r2, [pc, #128] ; (8001404 ) + 8001384: 671a str r2, [r3, #112] ; 0x70 + 8001386: 4b1f ldr r3, [pc, #124] ; (8001404 ) + 8001388: 687a ldr r2, [r7, #4] + 800138a: 629a str r2, [r3, #40] ; 0x28 + + /* LPUART1_TX Init */ + hdma_lpuart1_tx.Instance = DMA1_Channel2; + 800138c: 4b1f ldr r3, [pc, #124] ; (800140c ) + 800138e: 4a20 ldr r2, [pc, #128] ; (8001410 ) + 8001390: 601a str r2, [r3, #0] + hdma_lpuart1_tx.Init.Request = DMA_REQUEST_5; + 8001392: 4b1e ldr r3, [pc, #120] ; (800140c ) + 8001394: 2205 movs r2, #5 + 8001396: 605a str r2, [r3, #4] + hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 8001398: 4b1c ldr r3, [pc, #112] ; (800140c ) + 800139a: 2210 movs r2, #16 + 800139c: 609a str r2, [r3, #8] + hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 800139e: 4b1b ldr r3, [pc, #108] ; (800140c ) + 80013a0: 2200 movs r2, #0 + 80013a2: 60da str r2, [r3, #12] + hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE; + 80013a4: 4b19 ldr r3, [pc, #100] ; (800140c ) + 80013a6: 2280 movs r2, #128 ; 0x80 + 80013a8: 611a str r2, [r3, #16] + hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 80013aa: 4b18 ldr r3, [pc, #96] ; (800140c ) + 80013ac: 2200 movs r2, #0 + 80013ae: 615a str r2, [r3, #20] + hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 80013b0: 4b16 ldr r3, [pc, #88] ; (800140c ) + 80013b2: 2200 movs r2, #0 + 80013b4: 619a str r2, [r3, #24] + hdma_lpuart1_tx.Init.Mode = DMA_NORMAL; + 80013b6: 4b15 ldr r3, [pc, #84] ; (800140c ) + 80013b8: 2200 movs r2, #0 + 80013ba: 61da str r2, [r3, #28] + hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_HIGH; + 80013bc: 4b13 ldr r3, [pc, #76] ; (800140c ) + 80013be: 2280 movs r2, #128 ; 0x80 + 80013c0: 0192 lsls r2, r2, #6 + 80013c2: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK) + 80013c4: 4b11 ldr r3, [pc, #68] ; (800140c ) + 80013c6: 0018 movs r0, r3 + 80013c8: f000 fd7e bl 8001ec8 + 80013cc: 1e03 subs r3, r0, #0 + 80013ce: d001 beq.n 80013d4 + { + Error_Handler(); + 80013d0: f7ff fe30 bl 8001034 + } + + __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx); + 80013d4: 687b ldr r3, [r7, #4] + 80013d6: 4a0d ldr r2, [pc, #52] ; (800140c ) + 80013d8: 66da str r2, [r3, #108] ; 0x6c + 80013da: 4b0c ldr r3, [pc, #48] ; (800140c ) + 80013dc: 687a ldr r2, [r7, #4] + 80013de: 629a str r2, [r3, #40] ; 0x28 + + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 3, 0); + 80013e0: 2200 movs r2, #0 + 80013e2: 2103 movs r1, #3 + 80013e4: 201d movs r0, #29 + 80013e6: f000 fd3d bl 8001e64 + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + 80013ea: 201d movs r0, #29 + 80013ec: f000 fd4f bl 8001e8e + /* USER CODE BEGIN LPUART1_MspInit 1 */ + + /* USER CODE END LPUART1_MspInit 1 */ + } + +} + 80013f0: 46c0 nop ; (mov r8, r8) + 80013f2: 46bd mov sp, r7 + 80013f4: b009 add sp, #36 ; 0x24 + 80013f6: bd90 pop {r4, r7, pc} + 80013f8: 40004800 .word 0x40004800 + 80013fc: 40021000 .word 0x40021000 + 8001400: 50000400 .word 0x50000400 + 8001404: 20001830 .word 0x20001830 + 8001408: 40020030 .word 0x40020030 + 800140c: 200017e8 .word 0x200017e8 + 8001410: 4002001c .word 0x4002001c + +08001414 : +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8001414: b580 push {r7, lr} + 8001416: b082 sub sp, #8 + 8001418: af00 add r7, sp, #0 + 800141a: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM2) + 800141c: 687b ldr r3, [r7, #4] + 800141e: 681a ldr r2, [r3, #0] + 8001420: 2380 movs r3, #128 ; 0x80 + 8001422: 05db lsls r3, r3, #23 + 8001424: 429a cmp r2, r3 + 8001426: d105 bne.n 8001434 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 8001428: 4b04 ldr r3, [pc, #16] ; (800143c ) + 800142a: 6b9a ldr r2, [r3, #56] ; 0x38 + 800142c: 4b03 ldr r3, [pc, #12] ; (800143c ) + 800142e: 2101 movs r1, #1 + 8001430: 430a orrs r2, r1 + 8001432: 639a str r2, [r3, #56] ; 0x38 + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + +} + 8001434: 46c0 nop ; (mov r8, r8) + 8001436: 46bd mov sp, r7 + 8001438: b002 add sp, #8 + 800143a: bd80 pop {r7, pc} + 800143c: 40021000 .word 0x40021000 + +08001440 : +* This function configures the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) +{ + 8001440: b590 push {r4, r7, lr} + 8001442: b089 sub sp, #36 ; 0x24 + 8001444: af00 add r7, sp, #0 + 8001446: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001448: 240c movs r4, #12 + 800144a: 193b adds r3, r7, r4 + 800144c: 0018 movs r0, r3 + 800144e: 2314 movs r3, #20 + 8001450: 001a movs r2, r3 + 8001452: 2100 movs r1, #0 + 8001454: f006 f9b3 bl 80077be + if(htim_encoder->Instance==TIM21) + 8001458: 687b ldr r3, [r7, #4] + 800145a: 681b ldr r3, [r3, #0] + 800145c: 4a17 ldr r2, [pc, #92] ; (80014bc ) + 800145e: 4293 cmp r3, r2 + 8001460: d128 bne.n 80014b4 + { + /* USER CODE BEGIN TIM21_MspInit 0 */ + + /* USER CODE END TIM21_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM21_CLK_ENABLE(); + 8001462: 4b17 ldr r3, [pc, #92] ; (80014c0 ) + 8001464: 6b5a ldr r2, [r3, #52] ; 0x34 + 8001466: 4b16 ldr r3, [pc, #88] ; (80014c0 ) + 8001468: 2104 movs r1, #4 + 800146a: 430a orrs r2, r1 + 800146c: 635a str r2, [r3, #52] ; 0x34 + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800146e: 4b14 ldr r3, [pc, #80] ; (80014c0 ) + 8001470: 6ada ldr r2, [r3, #44] ; 0x2c + 8001472: 4b13 ldr r3, [pc, #76] ; (80014c0 ) + 8001474: 2101 movs r1, #1 + 8001476: 430a orrs r2, r1 + 8001478: 62da str r2, [r3, #44] ; 0x2c + 800147a: 4b11 ldr r3, [pc, #68] ; (80014c0 ) + 800147c: 6adb ldr r3, [r3, #44] ; 0x2c + 800147e: 2201 movs r2, #1 + 8001480: 4013 ands r3, r2 + 8001482: 60bb str r3, [r7, #8] + 8001484: 68bb ldr r3, [r7, #8] + /**TIM21 GPIO Configuration + PA2 ------> TIM21_CH1 + PA3 ------> TIM21_CH2 + */ + GPIO_InitStruct.Pin = ENC_PHA_DROIT_Pin|ENC_PHB_DROIT_Pin; + 8001486: 0021 movs r1, r4 + 8001488: 187b adds r3, r7, r1 + 800148a: 220c movs r2, #12 + 800148c: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800148e: 187b adds r3, r7, r1 + 8001490: 2202 movs r2, #2 + 8001492: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001494: 187b adds r3, r7, r1 + 8001496: 2200 movs r2, #0 + 8001498: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800149a: 187b adds r3, r7, r1 + 800149c: 2200 movs r2, #0 + 800149e: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF0_TIM21; + 80014a0: 187b adds r3, r7, r1 + 80014a2: 2200 movs r2, #0 + 80014a4: 611a str r2, [r3, #16] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80014a6: 187a adds r2, r7, r1 + 80014a8: 23a0 movs r3, #160 ; 0xa0 + 80014aa: 05db lsls r3, r3, #23 + 80014ac: 0011 movs r1, r2 + 80014ae: 0018 movs r0, r3 + 80014b0: f000 feb8 bl 8002224 + /* USER CODE BEGIN TIM21_MspInit 1 */ + + /* USER CODE END TIM21_MspInit 1 */ + } + +} + 80014b4: 46c0 nop ; (mov r8, r8) + 80014b6: 46bd mov sp, r7 + 80014b8: b009 add sp, #36 ; 0x24 + 80014ba: bd90 pop {r4, r7, pc} + 80014bc: 40010800 .word 0x40010800 + 80014c0: 40021000 .word 0x40021000 + +080014c4 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 80014c4: b590 push {r4, r7, lr} + 80014c6: b08b sub sp, #44 ; 0x2c + 80014c8: af00 add r7, sp, #0 + 80014ca: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80014cc: 2414 movs r4, #20 + 80014ce: 193b adds r3, r7, r4 + 80014d0: 0018 movs r0, r3 + 80014d2: 2314 movs r3, #20 + 80014d4: 001a movs r2, r3 + 80014d6: 2100 movs r1, #0 + 80014d8: f006 f971 bl 80077be + if(htim->Instance==TIM2) + 80014dc: 687b ldr r3, [r7, #4] + 80014de: 681a ldr r2, [r3, #0] + 80014e0: 2380 movs r3, #128 ; 0x80 + 80014e2: 05db lsls r3, r3, #23 + 80014e4: 429a cmp r2, r3 + 80014e6: d15a bne.n 800159e + { + /* USER CODE BEGIN TIM2_MspPostInit 0 */ + + /* USER CODE END TIM2_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80014e8: 4b2f ldr r3, [pc, #188] ; (80015a8 ) + 80014ea: 6ada ldr r2, [r3, #44] ; 0x2c + 80014ec: 4b2e ldr r3, [pc, #184] ; (80015a8 ) + 80014ee: 2101 movs r1, #1 + 80014f0: 430a orrs r2, r1 + 80014f2: 62da str r2, [r3, #44] ; 0x2c + 80014f4: 4b2c ldr r3, [pc, #176] ; (80015a8 ) + 80014f6: 6adb ldr r3, [r3, #44] ; 0x2c + 80014f8: 2201 movs r2, #1 + 80014fa: 4013 ands r3, r2 + 80014fc: 613b str r3, [r7, #16] + 80014fe: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001500: 4b29 ldr r3, [pc, #164] ; (80015a8 ) + 8001502: 6ada ldr r2, [r3, #44] ; 0x2c + 8001504: 4b28 ldr r3, [pc, #160] ; (80015a8 ) + 8001506: 2102 movs r1, #2 + 8001508: 430a orrs r2, r1 + 800150a: 62da str r2, [r3, #44] ; 0x2c + 800150c: 4b26 ldr r3, [pc, #152] ; (80015a8 ) + 800150e: 6adb ldr r3, [r3, #44] ; 0x2c + 8001510: 2202 movs r2, #2 + 8001512: 4013 ands r3, r2 + 8001514: 60fb str r3, [r7, #12] + 8001516: 68fb ldr r3, [r7, #12] + PA1 ------> TIM2_CH2 + PB0 ------> TIM2_CH3 + PB1 ------> TIM2_CH4 + PA8 ------> TIM2_CH1 + */ + GPIO_InitStruct.Pin = PWM_B_GAUCHE_Pin; + 8001518: 193b adds r3, r7, r4 + 800151a: 2202 movs r2, #2 + 800151c: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800151e: 193b adds r3, r7, r4 + 8001520: 2202 movs r2, #2 + 8001522: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001524: 193b adds r3, r7, r4 + 8001526: 2200 movs r2, #0 + 8001528: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800152a: 193b adds r3, r7, r4 + 800152c: 2200 movs r2, #0 + 800152e: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM2; + 8001530: 193b adds r3, r7, r4 + 8001532: 2202 movs r2, #2 + 8001534: 611a str r2, [r3, #16] + HAL_GPIO_Init(PWM_B_GAUCHE_GPIO_Port, &GPIO_InitStruct); + 8001536: 193a adds r2, r7, r4 + 8001538: 23a0 movs r3, #160 ; 0xa0 + 800153a: 05db lsls r3, r3, #23 + 800153c: 0011 movs r1, r2 + 800153e: 0018 movs r0, r3 + 8001540: f000 fe70 bl 8002224 + + GPIO_InitStruct.Pin = PWM_A_DROIT_Pin|PWM_B_DROIT_Pin; + 8001544: 193b adds r3, r7, r4 + 8001546: 2203 movs r2, #3 + 8001548: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800154a: 193b adds r3, r7, r4 + 800154c: 2202 movs r2, #2 + 800154e: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001550: 193b adds r3, r7, r4 + 8001552: 2200 movs r2, #0 + 8001554: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001556: 193b adds r3, r7, r4 + 8001558: 2200 movs r2, #0 + 800155a: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF5_TIM2; + 800155c: 193b adds r3, r7, r4 + 800155e: 2205 movs r2, #5 + 8001560: 611a str r2, [r3, #16] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001562: 193b adds r3, r7, r4 + 8001564: 4a11 ldr r2, [pc, #68] ; (80015ac ) + 8001566: 0019 movs r1, r3 + 8001568: 0010 movs r0, r2 + 800156a: f000 fe5b bl 8002224 + + GPIO_InitStruct.Pin = PWM_A_GAUCHE_Pin; + 800156e: 0021 movs r1, r4 + 8001570: 187b adds r3, r7, r1 + 8001572: 2280 movs r2, #128 ; 0x80 + 8001574: 0052 lsls r2, r2, #1 + 8001576: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001578: 187b adds r3, r7, r1 + 800157a: 2202 movs r2, #2 + 800157c: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800157e: 187b adds r3, r7, r1 + 8001580: 2200 movs r2, #0 + 8001582: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001584: 187b adds r3, r7, r1 + 8001586: 2200 movs r2, #0 + 8001588: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF5_TIM2; + 800158a: 187b adds r3, r7, r1 + 800158c: 2205 movs r2, #5 + 800158e: 611a str r2, [r3, #16] + HAL_GPIO_Init(PWM_A_GAUCHE_GPIO_Port, &GPIO_InitStruct); + 8001590: 187a adds r2, r7, r1 + 8001592: 23a0 movs r3, #160 ; 0xa0 + 8001594: 05db lsls r3, r3, #23 + 8001596: 0011 movs r1, r2 + 8001598: 0018 movs r0, r3 + 800159a: f000 fe43 bl 8002224 + /* USER CODE BEGIN TIM2_MspPostInit 1 */ + + /* USER CODE END TIM2_MspPostInit 1 */ + } + +} + 800159e: 46c0 nop ; (mov r8, r8) + 80015a0: 46bd mov sp, r7 + 80015a2: b00b add sp, #44 ; 0x2c + 80015a4: bd90 pop {r4, r7, pc} + 80015a6: 46c0 nop ; (mov r8, r8) + 80015a8: 40021000 .word 0x40021000 + 80015ac: 50000400 .word 0x50000400 + +080015b0 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable Interrupt. + */ +void NMI_Handler(void) +{ + 80015b0: b580 push {r7, lr} + 80015b2: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 80015b4: e7fe b.n 80015b4 + +080015b6 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 80015b6: b580 push {r7, lr} + 80015b8: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 80015ba: e7fe b.n 80015ba + +080015bc : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 80015bc: b580 push {r7, lr} + 80015be: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 80015c0: f000 f8d8 bl 8001774 +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + 80015c4: f005 f930 bl 8006828 + 80015c8: 0003 movs r3, r0 + 80015ca: 2b01 cmp r3, #1 + 80015cc: d001 beq.n 80015d2 + { +#endif /* INCLUDE_xTaskGetSchedulerState */ + xPortSysTickHandler(); + 80015ce: f005 fe03 bl 80071d8 + } +#endif /* INCLUDE_xTaskGetSchedulerState */ + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 80015d2: 46c0 nop ; (mov r8, r8) + 80015d4: 46bd mov sp, r7 + 80015d6: bd80 pop {r7, pc} + +080015d8 : + +/** + * @brief This function handles EXTI line 2 and line 3 interrupts. + */ +void EXTI2_3_IRQHandler(void) +{ + 80015d8: b580 push {r7, lr} + 80015da: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI2_3_IRQn 0 */ + + /* USER CODE END EXTI2_3_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); + 80015dc: 2008 movs r0, #8 + 80015de: f000 ffad bl 800253c + /* USER CODE BEGIN EXTI2_3_IRQn 1 */ + + /* USER CODE END EXTI2_3_IRQn 1 */ +} + 80015e2: 46c0 nop ; (mov r8, r8) + 80015e4: 46bd mov sp, r7 + 80015e6: bd80 pop {r7, pc} + +080015e8 : + +/** + * @brief This function handles DMA1 channel 2 and channel 3 interrupts. + */ +void DMA1_Channel2_3_IRQHandler(void) +{ + 80015e8: b580 push {r7, lr} + 80015ea: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_lpuart1_tx); + 80015ec: 4b05 ldr r3, [pc, #20] ; (8001604 ) + 80015ee: 0018 movs r0, r3 + 80015f0: f000 fd69 bl 80020c6 + HAL_DMA_IRQHandler(&hdma_lpuart1_rx); + 80015f4: 4b04 ldr r3, [pc, #16] ; (8001608 ) + 80015f6: 0018 movs r0, r3 + 80015f8: f000 fd65 bl 80020c6 + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 1 */ +} + 80015fc: 46c0 nop ; (mov r8, r8) + 80015fe: 46bd mov sp, r7 + 8001600: bd80 pop {r7, pc} + 8001602: 46c0 nop ; (mov r8, r8) + 8001604: 200017e8 .word 0x200017e8 + 8001608: 20001830 .word 0x20001830 + +0800160c : + +/** + * @brief This function handles ADC global interrupt. + */ +void ADC1_IRQHandler(void) +{ + 800160c: b580 push {r7, lr} + 800160e: af00 add r7, sp, #0 + /* USER CODE BEGIN ADC1_IRQn 0 */ + + /* USER CODE END ADC1_IRQn 0 */ + HAL_ADC_IRQHandler(&hadc); + 8001610: 4b03 ldr r3, [pc, #12] ; (8001620 ) + 8001612: 0018 movs r0, r3 + 8001614: f000 fa3e bl 8001a94 + /* USER CODE BEGIN ADC1_IRQn 1 */ + + /* USER CODE END ADC1_IRQn 1 */ +} + 8001618: 46c0 nop ; (mov r8, r8) + 800161a: 46bd mov sp, r7 + 800161c: bd80 pop {r7, pc} + 800161e: 46c0 nop ; (mov r8, r8) + 8001620: 200018b8 .word 0x200018b8 + +08001624 : + +/** + * @brief This function handles LPUART1 global interrupt / LPUART1 wake-up interrupt through EXTI line 28. + */ +void LPUART1_IRQHandler(void) +{ + 8001624: b580 push {r7, lr} + 8001626: af00 add r7, sp, #0 + /* USER CODE BEGIN LPUART1_IRQn 0 */ + + /* USER CODE END LPUART1_IRQn 0 */ + HAL_UART_IRQHandler(&hlpuart1); + 8001628: 4b03 ldr r3, [pc, #12] ; (8001638 ) + 800162a: 0018 movs r0, r3 + 800162c: f002 fc4c bl 8003ec8 + /* USER CODE BEGIN LPUART1_IRQn 1 */ + + /* USER CODE END LPUART1_IRQn 1 */ +} + 8001630: 46c0 nop ; (mov r8, r8) + 8001632: 46bd mov sp, r7 + 8001634: bd80 pop {r7, pc} + 8001636: 46c0 nop ; (mov r8, r8) + 8001638: 20001734 .word 0x20001734 + +0800163c : + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 800163c: b580 push {r7, lr} + 800163e: af00 add r7, sp, #0 + /* Configure the Vector Table location add offset address ------------------*/ +#if defined (USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8001640: 46c0 nop ; (mov r8, r8) + 8001642: 46bd mov sp, r7 + 8001644: bd80 pop {r7, pc} + ... + +08001648 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 8001648: 4813 ldr r0, [pc, #76] ; (8001698 ) + mov sp, r0 /* set stack pointer */ + 800164a: 4685 mov sp, r0 + +/*Check if boot space corresponds to system memory*/ + + LDR R0,=0x00000004 + 800164c: 4813 ldr r0, [pc, #76] ; (800169c ) + LDR R1, [R0] + 800164e: 6801 ldr r1, [r0, #0] + LSRS R1, R1, #24 + 8001650: 0e09 lsrs r1, r1, #24 + LDR R2,=0x1F + 8001652: 4a13 ldr r2, [pc, #76] ; (80016a0 ) + CMP R1, R2 + 8001654: 4291 cmp r1, r2 + BNE ApplicationStart + 8001656: d105 bne.n 8001664 + + /*SYSCFG clock enable*/ + LDR R0,=0x40021034 + 8001658: 4812 ldr r0, [pc, #72] ; (80016a4 ) + LDR R1,=0x00000001 + 800165a: 4913 ldr r1, [pc, #76] ; (80016a8 ) + STR R1, [R0] + 800165c: 6001 str r1, [r0, #0] + +/*Set CFGR1 register with flash memory remap at address 0*/ + LDR R0,=0x40010000 + 800165e: 4813 ldr r0, [pc, #76] ; (80016ac ) + LDR R1,=0x00000000 + 8001660: 4913 ldr r1, [pc, #76] ; (80016b0 ) + STR R1, [R0] + 8001662: 6001 str r1, [r0, #0] + +08001664 : + +ApplicationStart: +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8001664: 4813 ldr r0, [pc, #76] ; (80016b4 ) + ldr r1, =_edata + 8001666: 4914 ldr r1, [pc, #80] ; (80016b8 ) + ldr r2, =_sidata + 8001668: 4a14 ldr r2, [pc, #80] ; (80016bc ) + movs r3, #0 + 800166a: 2300 movs r3, #0 + b LoopCopyDataInit + 800166c: e002 b.n 8001674 + +0800166e : + +CopyDataInit: + ldr r4, [r2, r3] + 800166e: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8001670: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8001672: 3304 adds r3, #4 + +08001674 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8001674: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8001676: 428c cmp r4, r1 + bcc CopyDataInit + 8001678: d3f9 bcc.n 800166e + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 800167a: 4a11 ldr r2, [pc, #68] ; (80016c0 ) + ldr r4, =_ebss + 800167c: 4c11 ldr r4, [pc, #68] ; (80016c4 ) + movs r3, #0 + 800167e: 2300 movs r3, #0 + b LoopFillZerobss + 8001680: e001 b.n 8001686 + +08001682 : + +FillZerobss: + str r3, [r2] + 8001682: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8001684: 3204 adds r2, #4 + +08001686 : + +LoopFillZerobss: + cmp r2, r4 + 8001686: 42a2 cmp r2, r4 + bcc FillZerobss + 8001688: d3fb bcc.n 8001682 + +/* Call the clock system intitialization function.*/ + bl SystemInit + 800168a: f7ff ffd7 bl 800163c +/* Call static constructors */ + bl __libc_init_array + 800168e: f006 f869 bl 8007764 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8001692: f7ff f98d bl 80009b0
+ +08001696 : + +LoopForever: + b LoopForever + 8001696: e7fe b.n 8001696 + ldr r0, =_estack + 8001698: 20002000 .word 0x20002000 + LDR R0,=0x00000004 + 800169c: 00000004 .word 0x00000004 + LDR R2,=0x1F + 80016a0: 0000001f .word 0x0000001f + LDR R0,=0x40021034 + 80016a4: 40021034 .word 0x40021034 + LDR R1,=0x00000001 + 80016a8: 00000001 .word 0x00000001 + LDR R0,=0x40010000 + 80016ac: 40010000 .word 0x40010000 + LDR R1,=0x00000000 + 80016b0: 00000000 .word 0x00000000 + ldr r0, =_sdata + 80016b4: 20000000 .word 0x20000000 + ldr r1, =_edata + 80016b8: 20000010 .word 0x20000010 + ldr r2, =_sidata + 80016bc: 08007928 .word 0x08007928 + ldr r2, =_sbss + 80016c0: 20000010 .word 0x20000010 + ldr r4, =_ebss + 80016c4: 200019ac .word 0x200019ac + +080016c8 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80016c8: e7fe b.n 80016c8 + ... + +080016cc : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 80016cc: b580 push {r7, lr} + 80016ce: b082 sub sp, #8 + 80016d0: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 80016d2: 1dfb adds r3, r7, #7 + 80016d4: 2200 movs r2, #0 + 80016d6: 701a strb r2, [r3, #0] +#if (BUFFER_CACHE_DISABLE != 0) + __HAL_FLASH_BUFFER_CACHE_DISABLE(); +#endif /* BUFFER_CACHE_DISABLE */ + +#if (PREREAD_ENABLE != 0) + __HAL_FLASH_PREREAD_BUFFER_ENABLE(); + 80016d8: 4b0b ldr r3, [pc, #44] ; (8001708 ) + 80016da: 681a ldr r2, [r3, #0] + 80016dc: 4b0a ldr r3, [pc, #40] ; (8001708 ) + 80016de: 2140 movs r1, #64 ; 0x40 + 80016e0: 430a orrs r2, r1 + 80016e2: 601a str r2, [r3, #0] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 80016e4: 2003 movs r0, #3 + 80016e6: f000 f811 bl 800170c + 80016ea: 1e03 subs r3, r0, #0 + 80016ec: d003 beq.n 80016f6 + { + status = HAL_ERROR; + 80016ee: 1dfb adds r3, r7, #7 + 80016f0: 2201 movs r2, #1 + 80016f2: 701a strb r2, [r3, #0] + 80016f4: e001 b.n 80016fa + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 80016f6: f7ff fd1d bl 8001134 + } + + /* Return function status */ + return status; + 80016fa: 1dfb adds r3, r7, #7 + 80016fc: 781b ldrb r3, [r3, #0] +} + 80016fe: 0018 movs r0, r3 + 8001700: 46bd mov sp, r7 + 8001702: b002 add sp, #8 + 8001704: bd80 pop {r7, pc} + 8001706: 46c0 nop ; (mov r8, r8) + 8001708: 40022000 .word 0x40022000 + +0800170c : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 800170c: b590 push {r4, r7, lr} + 800170e: b083 sub sp, #12 + 8001710: af00 add r7, sp, #0 + 8001712: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8001714: 4b14 ldr r3, [pc, #80] ; (8001768 ) + 8001716: 681c ldr r4, [r3, #0] + 8001718: 4b14 ldr r3, [pc, #80] ; (800176c ) + 800171a: 781b ldrb r3, [r3, #0] + 800171c: 0019 movs r1, r3 + 800171e: 23fa movs r3, #250 ; 0xfa + 8001720: 0098 lsls r0, r3, #2 + 8001722: f7fe fcf1 bl 8000108 <__udivsi3> + 8001726: 0003 movs r3, r0 + 8001728: 0019 movs r1, r3 + 800172a: 0020 movs r0, r4 + 800172c: f7fe fcec bl 8000108 <__udivsi3> + 8001730: 0003 movs r3, r0 + 8001732: 0018 movs r0, r3 + 8001734: f000 fbbb bl 8001eae + 8001738: 1e03 subs r3, r0, #0 + 800173a: d001 beq.n 8001740 + { + return HAL_ERROR; + 800173c: 2301 movs r3, #1 + 800173e: e00f b.n 8001760 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8001740: 687b ldr r3, [r7, #4] + 8001742: 2b03 cmp r3, #3 + 8001744: d80b bhi.n 800175e + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8001746: 6879 ldr r1, [r7, #4] + 8001748: 2301 movs r3, #1 + 800174a: 425b negs r3, r3 + 800174c: 2200 movs r2, #0 + 800174e: 0018 movs r0, r3 + 8001750: f000 fb88 bl 8001e64 + uwTickPrio = TickPriority; + 8001754: 4b06 ldr r3, [pc, #24] ; (8001770 ) + 8001756: 687a ldr r2, [r7, #4] + 8001758: 601a str r2, [r3, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 800175a: 2300 movs r3, #0 + 800175c: e000 b.n 8001760 + return HAL_ERROR; + 800175e: 2301 movs r3, #1 +} + 8001760: 0018 movs r0, r3 + 8001762: 46bd mov sp, r7 + 8001764: b003 add sp, #12 + 8001766: bd90 pop {r4, r7, pc} + 8001768: 20000000 .word 0x20000000 + 800176c: 20000008 .word 0x20000008 + 8001770: 20000004 .word 0x20000004 + +08001774 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8001774: b580 push {r7, lr} + 8001776: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8001778: 4b05 ldr r3, [pc, #20] ; (8001790 ) + 800177a: 781b ldrb r3, [r3, #0] + 800177c: 001a movs r2, r3 + 800177e: 4b05 ldr r3, [pc, #20] ; (8001794 ) + 8001780: 681b ldr r3, [r3, #0] + 8001782: 18d2 adds r2, r2, r3 + 8001784: 4b03 ldr r3, [pc, #12] ; (8001794 ) + 8001786: 601a str r2, [r3, #0] +} + 8001788: 46c0 nop ; (mov r8, r8) + 800178a: 46bd mov sp, r7 + 800178c: bd80 pop {r7, pc} + 800178e: 46c0 nop ; (mov r8, r8) + 8001790: 20000008 .word 0x20000008 + 8001794: 20001968 .word 0x20001968 + +08001798 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8001798: b580 push {r7, lr} + 800179a: af00 add r7, sp, #0 + return uwTick; + 800179c: 4b02 ldr r3, [pc, #8] ; (80017a8 ) + 800179e: 681b ldr r3, [r3, #0] +} + 80017a0: 0018 movs r0, r3 + 80017a2: 46bd mov sp, r7 + 80017a4: bd80 pop {r7, pc} + 80017a6: 46c0 nop ; (mov r8, r8) + 80017a8: 20001968 .word 0x20001968 + +080017ac : + * function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + 80017ac: b580 push {r7, lr} + 80017ae: b082 sub sp, #8 + 80017b0: af00 add r7, sp, #0 + 80017b2: 6078 str r0, [r7, #4] + + /* Check ADC handle */ + if(hadc == NULL) + 80017b4: 687b ldr r3, [r7, #4] + 80017b6: 2b00 cmp r3, #0 + 80017b8: d101 bne.n 80017be + { + return HAL_ERROR; + 80017ba: 2301 movs r3, #1 + 80017bc: e159 b.n 8001a72 + /* Refer to header of this file for more details on clock enabling procedure*/ + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + /* - ADC voltage regulator enable */ + if(hadc->State == HAL_ADC_STATE_RESET) + 80017be: 687b ldr r3, [r7, #4] + 80017c0: 6d5b ldr r3, [r3, #84] ; 0x54 + 80017c2: 2b00 cmp r3, #0 + 80017c4: d10a bne.n 80017dc + { + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + 80017c6: 687b ldr r3, [r7, #4] + 80017c8: 2200 movs r2, #0 + 80017ca: 659a str r2, [r3, #88] ; 0x58 + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + 80017cc: 687b ldr r3, [r7, #4] + 80017ce: 2250 movs r2, #80 ; 0x50 + 80017d0: 2100 movs r1, #0 + 80017d2: 5499 strb r1, [r3, r2] + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); + 80017d4: 687b ldr r3, [r7, #4] + 80017d6: 0018 movs r0, r3 + 80017d8: f7ff fcc8 bl 800116c + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + /* and if there is no conversion on going on regular group (ADC can be */ + /* enabled anyway, in case of call of this function to update a parameter */ + /* on the fly). */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) || + 80017dc: 687b ldr r3, [r7, #4] + 80017de: 6d5b ldr r3, [r3, #84] ; 0x54 + 80017e0: 2210 movs r2, #16 + 80017e2: 4013 ands r3, r2 + 80017e4: 2b10 cmp r3, #16 + 80017e6: d005 beq.n 80017f4 + (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) ) + 80017e8: 687b ldr r3, [r7, #4] + 80017ea: 681b ldr r3, [r3, #0] + 80017ec: 689b ldr r3, [r3, #8] + 80017ee: 2204 movs r2, #4 + 80017f0: 4013 ands r3, r2 + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) || + 80017f2: d00b beq.n 800180c + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 80017f4: 687b ldr r3, [r7, #4] + 80017f6: 6d5b ldr r3, [r3, #84] ; 0x54 + 80017f8: 2210 movs r2, #16 + 80017fa: 431a orrs r2, r3 + 80017fc: 687b ldr r3, [r7, #4] + 80017fe: 655a str r2, [r3, #84] ; 0x54 + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 8001800: 687b ldr r3, [r7, #4] + 8001802: 2250 movs r2, #80 ; 0x50 + 8001804: 2100 movs r1, #0 + 8001806: 5499 strb r1, [r3, r2] + return HAL_ERROR; + 8001808: 2301 movs r3, #1 + 800180a: e132 b.n 8001a72 + } + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 800180c: 687b ldr r3, [r7, #4] + 800180e: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001810: 4a9a ldr r2, [pc, #616] ; (8001a7c ) + 8001812: 4013 ands r3, r2 + 8001814: 2202 movs r2, #2 + 8001816: 431a orrs r2, r3 + 8001818: 687b ldr r3, [r7, #4] + 800181a: 655a str r2, [r3, #84] ; 0x54 + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - ADC clock mode */ + /* - ADC clock prescaler */ + /* - ADC Resolution */ + if (ADC_IS_ENABLE(hadc) == RESET) + 800181c: 687b ldr r3, [r7, #4] + 800181e: 681b ldr r3, [r3, #0] + 8001820: 689b ldr r3, [r3, #8] + 8001822: 2203 movs r2, #3 + 8001824: 4013 ands r3, r2 + 8001826: 2b01 cmp r3, #1 + 8001828: d108 bne.n 800183c + 800182a: 687b ldr r3, [r7, #4] + 800182c: 681b ldr r3, [r3, #0] + 800182e: 681b ldr r3, [r3, #0] + 8001830: 2201 movs r2, #1 + 8001832: 4013 ands r3, r2 + 8001834: 2b01 cmp r3, #1 + 8001836: d101 bne.n 800183c + 8001838: 2301 movs r3, #1 + 800183a: e000 b.n 800183e + 800183c: 2300 movs r3, #0 + 800183e: 2b00 cmp r3, #0 + 8001840: d149 bne.n 80018d6 + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + /* Configuration of ADC clock: clock source PCLK or asynchronous with + selectable prescaler */ + __HAL_ADC_CLOCK_PRESCALER(hadc); + 8001842: 687b ldr r3, [r7, #4] + 8001844: 685a ldr r2, [r3, #4] + 8001846: 23c0 movs r3, #192 ; 0xc0 + 8001848: 061b lsls r3, r3, #24 + 800184a: 429a cmp r2, r3 + 800184c: d00b beq.n 8001866 + 800184e: 687b ldr r3, [r7, #4] + 8001850: 685a ldr r2, [r3, #4] + 8001852: 2380 movs r3, #128 ; 0x80 + 8001854: 05db lsls r3, r3, #23 + 8001856: 429a cmp r2, r3 + 8001858: d005 beq.n 8001866 + 800185a: 687b ldr r3, [r7, #4] + 800185c: 685a ldr r2, [r3, #4] + 800185e: 2380 movs r3, #128 ; 0x80 + 8001860: 061b lsls r3, r3, #24 + 8001862: 429a cmp r2, r3 + 8001864: d111 bne.n 800188a + 8001866: 687b ldr r3, [r7, #4] + 8001868: 681b ldr r3, [r3, #0] + 800186a: 691a ldr r2, [r3, #16] + 800186c: 687b ldr r3, [r7, #4] + 800186e: 681b ldr r3, [r3, #0] + 8001870: 0092 lsls r2, r2, #2 + 8001872: 0892 lsrs r2, r2, #2 + 8001874: 611a str r2, [r3, #16] + 8001876: 687b ldr r3, [r7, #4] + 8001878: 681b ldr r3, [r3, #0] + 800187a: 6919 ldr r1, [r3, #16] + 800187c: 687b ldr r3, [r7, #4] + 800187e: 685a ldr r2, [r3, #4] + 8001880: 687b ldr r3, [r7, #4] + 8001882: 681b ldr r3, [r3, #0] + 8001884: 430a orrs r2, r1 + 8001886: 611a str r2, [r3, #16] + 8001888: e014 b.n 80018b4 + 800188a: 687b ldr r3, [r7, #4] + 800188c: 681b ldr r3, [r3, #0] + 800188e: 691a ldr r2, [r3, #16] + 8001890: 687b ldr r3, [r7, #4] + 8001892: 681b ldr r3, [r3, #0] + 8001894: 0092 lsls r2, r2, #2 + 8001896: 0892 lsrs r2, r2, #2 + 8001898: 611a str r2, [r3, #16] + 800189a: 4b79 ldr r3, [pc, #484] ; (8001a80 ) + 800189c: 681a ldr r2, [r3, #0] + 800189e: 4b78 ldr r3, [pc, #480] ; (8001a80 ) + 80018a0: 4978 ldr r1, [pc, #480] ; (8001a84 ) + 80018a2: 400a ands r2, r1 + 80018a4: 601a str r2, [r3, #0] + 80018a6: 4b76 ldr r3, [pc, #472] ; (8001a80 ) + 80018a8: 6819 ldr r1, [r3, #0] + 80018aa: 687b ldr r3, [r7, #4] + 80018ac: 685a ldr r2, [r3, #4] + 80018ae: 4b74 ldr r3, [pc, #464] ; (8001a80 ) + 80018b0: 430a orrs r2, r1 + 80018b2: 601a str r2, [r3, #0] + + /* Configuration of ADC: */ + /* - Resolution */ + hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES); + 80018b4: 687b ldr r3, [r7, #4] + 80018b6: 681b ldr r3, [r3, #0] + 80018b8: 68da ldr r2, [r3, #12] + 80018ba: 687b ldr r3, [r7, #4] + 80018bc: 681b ldr r3, [r3, #0] + 80018be: 2118 movs r1, #24 + 80018c0: 438a bics r2, r1 + 80018c2: 60da str r2, [r3, #12] + hadc->Instance->CFGR1 |= hadc->Init.Resolution; + 80018c4: 687b ldr r3, [r7, #4] + 80018c6: 681b ldr r3, [r3, #0] + 80018c8: 68d9 ldr r1, [r3, #12] + 80018ca: 687b ldr r3, [r7, #4] + 80018cc: 689a ldr r2, [r3, #8] + 80018ce: 687b ldr r3, [r7, #4] + 80018d0: 681b ldr r3, [r3, #0] + 80018d2: 430a orrs r2, r1 + 80018d4: 60da str r2, [r3, #12] + } + + /* Set the Low Frequency mode */ + ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN; + 80018d6: 4b6a ldr r3, [pc, #424] ; (8001a80 ) + 80018d8: 681a ldr r2, [r3, #0] + 80018da: 4b69 ldr r3, [pc, #420] ; (8001a80 ) + 80018dc: 496a ldr r1, [pc, #424] ; (8001a88 ) + 80018de: 400a ands r2, r1 + 80018e0: 601a str r2, [r3, #0] + ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode); + 80018e2: 4b67 ldr r3, [pc, #412] ; (8001a80 ) + 80018e4: 6819 ldr r1, [r3, #0] + 80018e6: 687b ldr r3, [r7, #4] + 80018e8: 6b5b ldr r3, [r3, #52] ; 0x34 + 80018ea: 065a lsls r2, r3, #25 + 80018ec: 4b64 ldr r3, [pc, #400] ; (8001a80 ) + 80018ee: 430a orrs r2, r1 + 80018f0: 601a str r2, [r3, #0] + + /* Enable voltage regulator (if disabled at this step) */ + if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) + 80018f2: 687b ldr r3, [r7, #4] + 80018f4: 681b ldr r3, [r3, #0] + 80018f6: 689a ldr r2, [r3, #8] + 80018f8: 2380 movs r3, #128 ; 0x80 + 80018fa: 055b lsls r3, r3, #21 + 80018fc: 4013 ands r3, r2 + 80018fe: d108 bne.n 8001912 + { + /* Set ADVREGEN bit */ + hadc->Instance->CR |= ADC_CR_ADVREGEN; + 8001900: 687b ldr r3, [r7, #4] + 8001902: 681b ldr r3, [r3, #0] + 8001904: 689a ldr r2, [r3, #8] + 8001906: 687b ldr r3, [r7, #4] + 8001908: 681b ldr r3, [r3, #0] + 800190a: 2180 movs r1, #128 ; 0x80 + 800190c: 0549 lsls r1, r1, #21 + 800190e: 430a orrs r2, r1 + 8001910: 609a str r2, [r3, #8] + /* - Continuous conversion mode */ + /* - DMA continuous request */ + /* - Overrun */ + /* - AutoDelay feature */ + /* - Discontinuous mode */ + hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN | + 8001912: 687b ldr r3, [r7, #4] + 8001914: 681b ldr r3, [r3, #0] + 8001916: 68da ldr r2, [r3, #12] + 8001918: 687b ldr r3, [r7, #4] + 800191a: 681b ldr r3, [r3, #0] + 800191c: 495b ldr r1, [pc, #364] ; (8001a8c ) + 800191e: 400a ands r2, r1 + 8001920: 60da str r2, [r3, #12] + ADC_CFGR1_OVRMOD | + ADC_CFGR1_AUTDLY | + ADC_CFGR1_AUTOFF | + ADC_CFGR1_DISCEN ); + + hadc->Instance->CFGR1 |= (hadc->Init.DataAlign | + 8001922: 687b ldr r3, [r7, #4] + 8001924: 681b ldr r3, [r3, #0] + 8001926: 68d9 ldr r1, [r3, #12] + 8001928: 687b ldr r3, [r7, #4] + 800192a: 68da ldr r2, [r3, #12] + ADC_SCANDIR(hadc->Init.ScanConvMode) | + 800192c: 687b ldr r3, [r7, #4] + 800192e: 691b ldr r3, [r3, #16] + 8001930: 2b02 cmp r3, #2 + 8001932: d101 bne.n 8001938 + 8001934: 2304 movs r3, #4 + 8001936: e000 b.n 800193a + 8001938: 2300 movs r3, #0 + hadc->Instance->CFGR1 |= (hadc->Init.DataAlign | + 800193a: 431a orrs r2, r3 + ADC_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + 800193c: 687b ldr r3, [r7, #4] + 800193e: 2020 movs r0, #32 + 8001940: 5c1b ldrb r3, [r3, r0] + 8001942: 035b lsls r3, r3, #13 + ADC_SCANDIR(hadc->Init.ScanConvMode) | + 8001944: 431a orrs r2, r3 + ADC_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) | + 8001946: 687b ldr r3, [r7, #4] + 8001948: 202c movs r0, #44 ; 0x2c + 800194a: 5c1b ldrb r3, [r3, r0] + 800194c: 005b lsls r3, r3, #1 + ADC_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + 800194e: 431a orrs r2, r3 + hadc->Init.Overrun | + 8001950: 687b ldr r3, [r7, #4] + 8001952: 6b1b ldr r3, [r3, #48] ; 0x30 + ADC_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) | + 8001954: 431a orrs r2, r3 + __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) | + 8001956: 687b ldr r3, [r7, #4] + 8001958: 699b ldr r3, [r3, #24] + 800195a: 039b lsls r3, r3, #14 + hadc->Init.Overrun | + 800195c: 431a orrs r2, r3 + __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff)); + 800195e: 687b ldr r3, [r7, #4] + 8001960: 69db ldr r3, [r3, #28] + 8001962: 03db lsls r3, r3, #15 + __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) | + 8001964: 431a orrs r2, r3 + hadc->Instance->CFGR1 |= (hadc->Init.DataAlign | + 8001966: 687b ldr r3, [r7, #4] + 8001968: 681b ldr r3, [r3, #0] + 800196a: 430a orrs r2, r1 + 800196c: 60da str r2, [r3, #12] + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + 800196e: 687b ldr r3, [r7, #4] + 8001970: 6a5a ldr r2, [r3, #36] ; 0x24 + 8001972: 23c2 movs r3, #194 ; 0xc2 + 8001974: 33ff adds r3, #255 ; 0xff + 8001976: 429a cmp r2, r3 + 8001978: d00b beq.n 8001992 + { + hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv | + 800197a: 687b ldr r3, [r7, #4] + 800197c: 681b ldr r3, [r3, #0] + 800197e: 68d9 ldr r1, [r3, #12] + 8001980: 687b ldr r3, [r7, #4] + 8001982: 6a5a ldr r2, [r3, #36] ; 0x24 + hadc->Init.ExternalTrigConvEdge; + 8001984: 687b ldr r3, [r7, #4] + 8001986: 6a9b ldr r3, [r3, #40] ; 0x28 + hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv | + 8001988: 431a orrs r2, r3 + 800198a: 687b ldr r3, [r7, #4] + 800198c: 681b ldr r3, [r3, #0] + 800198e: 430a orrs r2, r1 + 8001990: 60da str r2, [r3, #12] + } + + /* Enable discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + 8001992: 687b ldr r3, [r7, #4] + 8001994: 2221 movs r2, #33 ; 0x21 + 8001996: 5c9b ldrb r3, [r3, r2] + 8001998: 2b01 cmp r3, #1 + 800199a: d11a bne.n 80019d2 + { + if (hadc->Init.ContinuousConvMode == DISABLE) + 800199c: 687b ldr r3, [r7, #4] + 800199e: 2220 movs r2, #32 + 80019a0: 5c9b ldrb r3, [r3, r2] + 80019a2: 2b00 cmp r3, #0 + 80019a4: d109 bne.n 80019ba + { + /* Enable the selected ADC group regular discontinuous mode */ + hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN); + 80019a6: 687b ldr r3, [r7, #4] + 80019a8: 681b ldr r3, [r3, #0] + 80019aa: 68da ldr r2, [r3, #12] + 80019ac: 687b ldr r3, [r7, #4] + 80019ae: 681b ldr r3, [r3, #0] + 80019b0: 2180 movs r1, #128 ; 0x80 + 80019b2: 0249 lsls r1, r1, #9 + 80019b4: 430a orrs r2, r1 + 80019b6: 60da str r2, [r3, #12] + 80019b8: e00b b.n 80019d2 + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 80019ba: 687b ldr r3, [r7, #4] + 80019bc: 6d5b ldr r3, [r3, #84] ; 0x54 + 80019be: 2220 movs r2, #32 + 80019c0: 431a orrs r2, r3 + 80019c2: 687b ldr r3, [r7, #4] + 80019c4: 655a str r2, [r3, #84] ; 0x54 + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 80019c6: 687b ldr r3, [r7, #4] + 80019c8: 6d9b ldr r3, [r3, #88] ; 0x58 + 80019ca: 2201 movs r2, #1 + 80019cc: 431a orrs r2, r3 + 80019ce: 687b ldr r3, [r7, #4] + 80019d0: 659a str r2, [r3, #88] ; 0x58 + } + } + + if (hadc->Init.OversamplingMode == ENABLE) + 80019d2: 687b ldr r3, [r7, #4] + 80019d4: 6bdb ldr r3, [r3, #60] ; 0x3c + 80019d6: 2b01 cmp r3, #1 + 80019d8: d11f bne.n 8001a1a + /* Configuration of Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + /* - Triggered mode */ + + hadc->Instance->CFGR2 &= ~( ADC_CFGR2_OVSR | + 80019da: 687b ldr r3, [r7, #4] + 80019dc: 681b ldr r3, [r3, #0] + 80019de: 691a ldr r2, [r3, #16] + 80019e0: 687b ldr r3, [r7, #4] + 80019e2: 681b ldr r3, [r3, #0] + 80019e4: 492a ldr r1, [pc, #168] ; (8001a90 ) + 80019e6: 400a ands r2, r1 + 80019e8: 611a str r2, [r3, #16] + ADC_CFGR2_OVSS | + ADC_CFGR2_TOVS ); + + hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio | + 80019ea: 687b ldr r3, [r7, #4] + 80019ec: 681b ldr r3, [r3, #0] + 80019ee: 6919 ldr r1, [r3, #16] + 80019f0: 687b ldr r3, [r7, #4] + 80019f2: 6c1a ldr r2, [r3, #64] ; 0x40 + hadc->Init.Oversample.RightBitShift | + 80019f4: 687b ldr r3, [r7, #4] + 80019f6: 6c5b ldr r3, [r3, #68] ; 0x44 + hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio | + 80019f8: 431a orrs r2, r3 + hadc->Init.Oversample.TriggeredMode ); + 80019fa: 687b ldr r3, [r7, #4] + 80019fc: 6c9b ldr r3, [r3, #72] ; 0x48 + hadc->Init.Oversample.RightBitShift | + 80019fe: 431a orrs r2, r3 + hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio | + 8001a00: 687b ldr r3, [r7, #4] + 8001a02: 681b ldr r3, [r3, #0] + 8001a04: 430a orrs r2, r1 + 8001a06: 611a str r2, [r3, #16] + + /* Enable OverSampling mode */ + hadc->Instance->CFGR2 |= ADC_CFGR2_OVSE; + 8001a08: 687b ldr r3, [r7, #4] + 8001a0a: 681b ldr r3, [r3, #0] + 8001a0c: 691a ldr r2, [r3, #16] + 8001a0e: 687b ldr r3, [r7, #4] + 8001a10: 681b ldr r3, [r3, #0] + 8001a12: 2101 movs r1, #1 + 8001a14: 430a orrs r2, r1 + 8001a16: 611a str r2, [r3, #16] + 8001a18: e00e b.n 8001a38 + } + else + { + if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE)) + 8001a1a: 687b ldr r3, [r7, #4] + 8001a1c: 681b ldr r3, [r3, #0] + 8001a1e: 691b ldr r3, [r3, #16] + 8001a20: 2201 movs r2, #1 + 8001a22: 4013 ands r3, r2 + 8001a24: 2b01 cmp r3, #1 + 8001a26: d107 bne.n 8001a38 + { + /* Disable OverSampling mode if needed */ + hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE; + 8001a28: 687b ldr r3, [r7, #4] + 8001a2a: 681b ldr r3, [r3, #0] + 8001a2c: 691a ldr r2, [r3, #16] + 8001a2e: 687b ldr r3, [r7, #4] + 8001a30: 681b ldr r3, [r3, #0] + 8001a32: 2101 movs r1, #1 + 8001a34: 438a bics r2, r1 + 8001a36: 611a str r2, [r3, #16] + } + } + + /* Clear the old sampling time */ + hadc->Instance->SMPR &= (uint32_t)(~ADC_SMPR_SMPR); + 8001a38: 687b ldr r3, [r7, #4] + 8001a3a: 681b ldr r3, [r3, #0] + 8001a3c: 695a ldr r2, [r3, #20] + 8001a3e: 687b ldr r3, [r7, #4] + 8001a40: 681b ldr r3, [r3, #0] + 8001a42: 2107 movs r1, #7 + 8001a44: 438a bics r2, r1 + 8001a46: 615a str r2, [r3, #20] + + /* Set the new sample time */ + hadc->Instance->SMPR |= hadc->Init.SamplingTime; + 8001a48: 687b ldr r3, [r7, #4] + 8001a4a: 681b ldr r3, [r3, #0] + 8001a4c: 6959 ldr r1, [r3, #20] + 8001a4e: 687b ldr r3, [r7, #4] + 8001a50: 6b9a ldr r2, [r3, #56] ; 0x38 + 8001a52: 687b ldr r3, [r7, #4] + 8001a54: 681b ldr r3, [r3, #0] + 8001a56: 430a orrs r2, r1 + 8001a58: 615a str r2, [r3, #20] + + /* Clear ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + 8001a5a: 687b ldr r3, [r7, #4] + 8001a5c: 2200 movs r2, #0 + 8001a5e: 659a str r2, [r3, #88] ; 0x58 + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 8001a60: 687b ldr r3, [r7, #4] + 8001a62: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001a64: 2203 movs r2, #3 + 8001a66: 4393 bics r3, r2 + 8001a68: 2201 movs r2, #1 + 8001a6a: 431a orrs r2, r3 + 8001a6c: 687b ldr r3, [r7, #4] + 8001a6e: 655a str r2, [r3, #84] ; 0x54 + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + + + /* Return function status */ + return HAL_OK; + 8001a70: 2300 movs r3, #0 +} + 8001a72: 0018 movs r0, r3 + 8001a74: 46bd mov sp, r7 + 8001a76: b002 add sp, #8 + 8001a78: bd80 pop {r7, pc} + 8001a7a: 46c0 nop ; (mov r8, r8) + 8001a7c: fffffefd .word 0xfffffefd + 8001a80: 40012708 .word 0x40012708 + 8001a84: ffc3ffff .word 0xffc3ffff + 8001a88: fdffffff .word 0xfdffffff + 8001a8c: fffe0219 .word 0xfffe0219 + 8001a90: fffffc03 .word 0xfffffc03 + +08001a94 : + * @brief Handle ADC interrupt request. + * @param hadc ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + 8001a94: b580 push {r7, lr} + 8001a96: b082 sub sp, #8 + 8001a98: af00 add r7, sp, #0 + 8001a9a: 6078 str r0, [r7, #4] + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + + /* ========== Check End of Conversion flag for regular group ========== */ + if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || + 8001a9c: 687b ldr r3, [r7, #4] + 8001a9e: 681b ldr r3, [r3, #0] + 8001aa0: 681b ldr r3, [r3, #0] + 8001aa2: 2204 movs r2, #4 + 8001aa4: 4013 ands r3, r2 + 8001aa6: 2b04 cmp r3, #4 + 8001aa8: d106 bne.n 8001ab8 + 8001aaa: 687b ldr r3, [r7, #4] + 8001aac: 681b ldr r3, [r3, #0] + 8001aae: 685b ldr r3, [r3, #4] + 8001ab0: 2204 movs r2, #4 + 8001ab2: 4013 ands r3, r2 + 8001ab4: 2b04 cmp r3, #4 + 8001ab6: d00d beq.n 8001ad4 + (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) + 8001ab8: 687b ldr r3, [r7, #4] + 8001aba: 681b ldr r3, [r3, #0] + 8001abc: 681b ldr r3, [r3, #0] + 8001abe: 2208 movs r2, #8 + 8001ac0: 4013 ands r3, r2 + if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || + 8001ac2: 2b08 cmp r3, #8 + 8001ac4: d154 bne.n 8001b70 + (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) + 8001ac6: 687b ldr r3, [r7, #4] + 8001ac8: 681b ldr r3, [r3, #0] + 8001aca: 685b ldr r3, [r3, #4] + 8001acc: 2208 movs r2, #8 + 8001ace: 4013 ands r3, r2 + 8001ad0: 2b08 cmp r3, #8 + 8001ad2: d14d bne.n 8001b70 + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + 8001ad4: 687b ldr r3, [r7, #4] + 8001ad6: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001ad8: 2210 movs r2, #16 + 8001ada: 4013 ands r3, r2 + 8001adc: d106 bne.n 8001aec + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + 8001ade: 687b ldr r3, [r7, #4] + 8001ae0: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001ae2: 2280 movs r2, #128 ; 0x80 + 8001ae4: 0092 lsls r2, r2, #2 + 8001ae6: 431a orrs r2, r3 + 8001ae8: 687b ldr r3, [r7, #4] + 8001aea: 655a str r2, [r3, #84] ; 0x54 + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 8001aec: 687b ldr r3, [r7, #4] + 8001aee: 681b ldr r3, [r3, #0] + 8001af0: 68da ldr r2, [r3, #12] + 8001af2: 23c0 movs r3, #192 ; 0xc0 + 8001af4: 011b lsls r3, r3, #4 + 8001af6: 4013 ands r3, r2 + 8001af8: d12e bne.n 8001b58 + (hadc->Init.ContinuousConvMode == DISABLE) ) + 8001afa: 687b ldr r3, [r7, #4] + 8001afc: 2220 movs r2, #32 + 8001afe: 5c9b ldrb r3, [r3, r2] + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 8001b00: 2b00 cmp r3, #0 + 8001b02: d129 bne.n 8001b58 + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + 8001b04: 687b ldr r3, [r7, #4] + 8001b06: 681b ldr r3, [r3, #0] + 8001b08: 681b ldr r3, [r3, #0] + 8001b0a: 2208 movs r2, #8 + 8001b0c: 4013 ands r3, r2 + 8001b0e: 2b08 cmp r3, #8 + 8001b10: d122 bne.n 8001b58 + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + 8001b12: 687b ldr r3, [r7, #4] + 8001b14: 681b ldr r3, [r3, #0] + 8001b16: 689b ldr r3, [r3, #8] + 8001b18: 2204 movs r2, #4 + 8001b1a: 4013 ands r3, r2 + 8001b1c: d110 bne.n 8001b40 + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + 8001b1e: 687b ldr r3, [r7, #4] + 8001b20: 681b ldr r3, [r3, #0] + 8001b22: 685a ldr r2, [r3, #4] + 8001b24: 687b ldr r3, [r7, #4] + 8001b26: 681b ldr r3, [r3, #0] + 8001b28: 210c movs r1, #12 + 8001b2a: 438a bics r2, r1 + 8001b2c: 605a str r2, [r3, #4] + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 8001b2e: 687b ldr r3, [r7, #4] + 8001b30: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001b32: 4a35 ldr r2, [pc, #212] ; (8001c08 ) + 8001b34: 4013 ands r3, r2 + 8001b36: 2201 movs r2, #1 + 8001b38: 431a orrs r2, r3 + 8001b3a: 687b ldr r3, [r7, #4] + 8001b3c: 655a str r2, [r3, #84] ; 0x54 + 8001b3e: e00b b.n 8001b58 + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 8001b40: 687b ldr r3, [r7, #4] + 8001b42: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001b44: 2220 movs r2, #32 + 8001b46: 431a orrs r2, r3 + 8001b48: 687b ldr r3, [r7, #4] + 8001b4a: 655a str r2, [r3, #84] ; 0x54 + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 8001b4c: 687b ldr r3, [r7, #4] + 8001b4e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001b50: 2201 movs r2, #1 + 8001b52: 431a orrs r2, r3 + 8001b54: 687b ldr r3, [r7, #4] + 8001b56: 659a str r2, [r3, #88] ; 0x58 + /* from EOC or EOS, possibility to use: */ + /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); + 8001b58: 687b ldr r3, [r7, #4] + 8001b5a: 0018 movs r0, r3 + 8001b5c: f000 f856 bl 8001c0c + /* Note: Management of low power auto-wait enabled: flags must be cleared */ + /* by user when fetching ADC conversion data. */ + /* This case is managed in IRQ handler, but this low-power mode */ + /* should not be used with programming model IT or DMA. */ + /* Refer to comment of parameter "LowPowerAutoWait". */ + if (hadc->Init.LowPowerAutoWait != ENABLE) + 8001b60: 687b ldr r3, [r7, #4] + 8001b62: 699b ldr r3, [r3, #24] + 8001b64: 2b01 cmp r3, #1 + 8001b66: d003 beq.n 8001b70 + { + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + 8001b68: 687b ldr r3, [r7, #4] + 8001b6a: 681b ldr r3, [r3, #0] + 8001b6c: 220c movs r2, #12 + 8001b6e: 601a str r2, [r3, #0] + } + } + + /* ========== Check analog watchdog 1 flag ========== */ + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) + 8001b70: 687b ldr r3, [r7, #4] + 8001b72: 681b ldr r3, [r3, #0] + 8001b74: 681b ldr r3, [r3, #0] + 8001b76: 2280 movs r2, #128 ; 0x80 + 8001b78: 4013 ands r3, r2 + 8001b7a: 2b80 cmp r3, #128 ; 0x80 + 8001b7c: d115 bne.n 8001baa + 8001b7e: 687b ldr r3, [r7, #4] + 8001b80: 681b ldr r3, [r3, #0] + 8001b82: 685b ldr r3, [r3, #4] + 8001b84: 2280 movs r2, #128 ; 0x80 + 8001b86: 4013 ands r3, r2 + 8001b88: 2b80 cmp r3, #128 ; 0x80 + 8001b8a: d10e bne.n 8001baa + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + 8001b8c: 687b ldr r3, [r7, #4] + 8001b8e: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001b90: 2280 movs r2, #128 ; 0x80 + 8001b92: 0252 lsls r2, r2, #9 + 8001b94: 431a orrs r2, r3 + 8001b96: 687b ldr r3, [r7, #4] + 8001b98: 655a str r2, [r3, #84] ; 0x54 + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); + 8001b9a: 687b ldr r3, [r7, #4] + 8001b9c: 0018 movs r0, r3 + 8001b9e: f000 f83d bl 8001c1c +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC Analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + 8001ba2: 687b ldr r3, [r7, #4] + 8001ba4: 681b ldr r3, [r3, #0] + 8001ba6: 2280 movs r2, #128 ; 0x80 + 8001ba8: 601a str r2, [r3, #0] + + } + + + /* ========== Check Overrun flag ========== */ + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) + 8001baa: 687b ldr r3, [r7, #4] + 8001bac: 681b ldr r3, [r3, #0] + 8001bae: 681b ldr r3, [r3, #0] + 8001bb0: 2210 movs r2, #16 + 8001bb2: 4013 ands r3, r2 + 8001bb4: 2b10 cmp r3, #16 + 8001bb6: d123 bne.n 8001c00 + 8001bb8: 687b ldr r3, [r7, #4] + 8001bba: 681b ldr r3, [r3, #0] + 8001bbc: 685b ldr r3, [r3, #4] + 8001bbe: 2210 movs r2, #16 + 8001bc0: 4013 ands r3, r2 + 8001bc2: 2b10 cmp r3, #16 + 8001bc4: d11c bne.n 8001c00 + /* overrun event is not considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + /* Exception for usage with DMA overrun event always considered as an */ + /* error. */ + if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || + 8001bc6: 687b ldr r3, [r7, #4] + 8001bc8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001bca: 2b00 cmp r3, #0 + 8001bcc: d006 beq.n 8001bdc + HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) + 8001bce: 687b ldr r3, [r7, #4] + 8001bd0: 681b ldr r3, [r3, #0] + 8001bd2: 68db ldr r3, [r3, #12] + 8001bd4: 2201 movs r2, #1 + 8001bd6: 4013 ands r3, r2 + if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || + 8001bd8: 2b01 cmp r3, #1 + 8001bda: d10d bne.n 8001bf8 + { + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + 8001bdc: 687b ldr r3, [r7, #4] + 8001bde: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001be0: 2202 movs r2, #2 + 8001be2: 431a orrs r2, r3 + 8001be4: 687b ldr r3, [r7, #4] + 8001be6: 659a str r2, [r3, #88] ; 0x58 + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + 8001be8: 687b ldr r3, [r7, #4] + 8001bea: 681b ldr r3, [r3, #0] + 8001bec: 2210 movs r2, #16 + 8001bee: 601a str r2, [r3, #0] + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); + 8001bf0: 687b ldr r3, [r7, #4] + 8001bf2: 0018 movs r0, r3 + 8001bf4: f000 f81a bl 8001c2c +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + 8001bf8: 687b ldr r3, [r7, #4] + 8001bfa: 681b ldr r3, [r3, #0] + 8001bfc: 2210 movs r2, #16 + 8001bfe: 601a str r2, [r3, #0] + } + +} + 8001c00: 46c0 nop ; (mov r8, r8) + 8001c02: 46bd mov sp, r7 + 8001c04: b002 add sp, #8 + 8001c06: bd80 pop {r7, pc} + 8001c08: fffffefe .word 0xfffffefe + +08001c0c : + * @brief Conversion complete callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + 8001c0c: b580 push {r7, lr} + 8001c0e: b082 sub sp, #8 + 8001c10: af00 add r7, sp, #0 + 8001c12: 6078 str r0, [r7, #4] + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + 8001c14: 46c0 nop ; (mov r8, r8) + 8001c16: 46bd mov sp, r7 + 8001c18: b002 add sp, #8 + 8001c1a: bd80 pop {r7, pc} + +08001c1c : + * @brief Analog watchdog 1 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + 8001c1c: b580 push {r7, lr} + 8001c1e: b082 sub sp, #8 + 8001c20: af00 add r7, sp, #0 + 8001c22: 6078 str r0, [r7, #4] + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. + */ +} + 8001c24: 46c0 nop ; (mov r8, r8) + 8001c26: 46bd mov sp, r7 + 8001c28: b002 add sp, #8 + 8001c2a: bd80 pop {r7, pc} + +08001c2c : + * (this function is also clearing overrun flag) + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + 8001c2c: b580 push {r7, lr} + 8001c2e: b082 sub sp, #8 + 8001c30: af00 add r7, sp, #0 + 8001c32: 6078 str r0, [r7, #4] + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + 8001c34: 46c0 nop ; (mov r8, r8) + 8001c36: 46bd mov sp, r7 + 8001c38: b002 add sp, #8 + 8001c3a: bd80 pop {r7, pc} + +08001c3c : + * @param hadc ADC handle + * @param sConfig Structure of ADC channel assigned to ADC group regular. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + 8001c3c: b580 push {r7, lr} + 8001c3e: b082 sub sp, #8 + 8001c40: af00 add r7, sp, #0 + 8001c42: 6078 str r0, [r7, #4] + 8001c44: 6039 str r1, [r7, #0] + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_RANK(sConfig->Rank)); + + /* Process locked */ + __HAL_LOCK(hadc); + 8001c46: 687b ldr r3, [r7, #4] + 8001c48: 2250 movs r2, #80 ; 0x50 + 8001c4a: 5c9b ldrb r3, [r3, r2] + 8001c4c: 2b01 cmp r3, #1 + 8001c4e: d101 bne.n 8001c54 + 8001c50: 2302 movs r3, #2 + 8001c52: e050 b.n 8001cf6 + 8001c54: 687b ldr r3, [r7, #4] + 8001c56: 2250 movs r2, #80 ; 0x50 + 8001c58: 2101 movs r1, #1 + 8001c5a: 5499 strb r1, [r3, r2] + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) + 8001c5c: 687b ldr r3, [r7, #4] + 8001c5e: 681b ldr r3, [r3, #0] + 8001c60: 689b ldr r3, [r3, #8] + 8001c62: 2204 movs r2, #4 + 8001c64: 4013 ands r3, r2 + 8001c66: d00b beq.n 8001c80 + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 8001c68: 687b ldr r3, [r7, #4] + 8001c6a: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001c6c: 2220 movs r2, #32 + 8001c6e: 431a orrs r2, r3 + 8001c70: 687b ldr r3, [r7, #4] + 8001c72: 655a str r2, [r3, #84] ; 0x54 + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 8001c74: 687b ldr r3, [r7, #4] + 8001c76: 2250 movs r2, #80 ; 0x50 + 8001c78: 2100 movs r1, #0 + 8001c7a: 5499 strb r1, [r3, r2] + return HAL_ERROR; + 8001c7c: 2301 movs r3, #1 + 8001c7e: e03a b.n 8001cf6 + } + + if (sConfig->Rank != ADC_RANK_NONE) + 8001c80: 683b ldr r3, [r7, #0] + 8001c82: 685b ldr r3, [r3, #4] + 8001c84: 4a1e ldr r2, [pc, #120] ; (8001d00 ) + 8001c86: 4293 cmp r3, r2 + 8001c88: d018 beq.n 8001cbc + { + /* Enable selected channels */ + hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK); + 8001c8a: 687b ldr r3, [r7, #4] + 8001c8c: 681b ldr r3, [r3, #0] + 8001c8e: 6a99 ldr r1, [r3, #40] ; 0x28 + 8001c90: 683b ldr r3, [r7, #0] + 8001c92: 681b ldr r3, [r3, #0] + 8001c94: 035b lsls r3, r3, #13 + 8001c96: 0b5a lsrs r2, r3, #13 + 8001c98: 687b ldr r3, [r7, #4] + 8001c9a: 681b ldr r3, [r3, #0] + 8001c9c: 430a orrs r2, r1 + 8001c9e: 629a str r2, [r3, #40] ; 0x28 + ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US); + } + #endif + + /* If VRefInt channel is selected, then enable the internal buffers and path */ + if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK)) + 8001ca0: 683b ldr r3, [r7, #0] + 8001ca2: 681a ldr r2, [r3, #0] + 8001ca4: 2380 movs r3, #128 ; 0x80 + 8001ca6: 029b lsls r3, r3, #10 + 8001ca8: 4013 ands r3, r2 + 8001caa: d01f beq.n 8001cec + { + ADC->CCR |= ADC_CCR_VREFEN; + 8001cac: 4b15 ldr r3, [pc, #84] ; (8001d04 ) + 8001cae: 681a ldr r2, [r3, #0] + 8001cb0: 4b14 ldr r3, [pc, #80] ; (8001d04 ) + 8001cb2: 2180 movs r1, #128 ; 0x80 + 8001cb4: 03c9 lsls r1, r1, #15 + 8001cb6: 430a orrs r2, r1 + 8001cb8: 601a str r2, [r3, #0] + 8001cba: e017 b.n 8001cec + } + else + { + /* Regular sequence configuration */ + /* Reset the channel selection register from the selected channel */ + hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK)); + 8001cbc: 687b ldr r3, [r7, #4] + 8001cbe: 681b ldr r3, [r3, #0] + 8001cc0: 6a9a ldr r2, [r3, #40] ; 0x28 + 8001cc2: 683b ldr r3, [r7, #0] + 8001cc4: 681b ldr r3, [r3, #0] + 8001cc6: 035b lsls r3, r3, #13 + 8001cc8: 0b5b lsrs r3, r3, #13 + 8001cca: 43d9 mvns r1, r3 + 8001ccc: 687b ldr r3, [r7, #4] + 8001cce: 681b ldr r3, [r3, #0] + 8001cd0: 400a ands r2, r1 + 8001cd2: 629a str r2, [r3, #40] ; 0x28 + ADC->CCR &= ~ADC_CCR_TSEN; + } + #endif + + /* If VRefInt channel is selected, then enable the internal buffers and path */ + if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK)) + 8001cd4: 683b ldr r3, [r7, #0] + 8001cd6: 681a ldr r2, [r3, #0] + 8001cd8: 2380 movs r3, #128 ; 0x80 + 8001cda: 029b lsls r3, r3, #10 + 8001cdc: 4013 ands r3, r2 + 8001cde: d005 beq.n 8001cec + { + ADC->CCR &= ~ADC_CCR_VREFEN; + 8001ce0: 4b08 ldr r3, [pc, #32] ; (8001d04 ) + 8001ce2: 681a ldr r2, [r3, #0] + 8001ce4: 4b07 ldr r3, [pc, #28] ; (8001d04 ) + 8001ce6: 4908 ldr r1, [pc, #32] ; (8001d08 ) + 8001ce8: 400a ands r2, r1 + 8001cea: 601a str r2, [r3, #0] + } +#endif + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 8001cec: 687b ldr r3, [r7, #4] + 8001cee: 2250 movs r2, #80 ; 0x50 + 8001cf0: 2100 movs r1, #0 + 8001cf2: 5499 strb r1, [r3, r2] + + /* Return function status */ + return HAL_OK; + 8001cf4: 2300 movs r3, #0 +} + 8001cf6: 0018 movs r0, r3 + 8001cf8: 46bd mov sp, r7 + 8001cfa: b002 add sp, #8 + 8001cfc: bd80 pop {r7, pc} + 8001cfe: 46c0 nop ; (mov r8, r8) + 8001d00: 00001001 .word 0x00001001 + 8001d04: 40012708 .word 0x40012708 + 8001d08: ffbfffff .word 0xffbfffff + +08001d0c <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001d0c: b580 push {r7, lr} + 8001d0e: b082 sub sp, #8 + 8001d10: af00 add r7, sp, #0 + 8001d12: 0002 movs r2, r0 + 8001d14: 1dfb adds r3, r7, #7 + 8001d16: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 8001d18: 1dfb adds r3, r7, #7 + 8001d1a: 781b ldrb r3, [r3, #0] + 8001d1c: 2b7f cmp r3, #127 ; 0x7f + 8001d1e: d809 bhi.n 8001d34 <__NVIC_EnableIRQ+0x28> + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001d20: 1dfb adds r3, r7, #7 + 8001d22: 781b ldrb r3, [r3, #0] + 8001d24: 001a movs r2, r3 + 8001d26: 231f movs r3, #31 + 8001d28: 401a ands r2, r3 + 8001d2a: 4b04 ldr r3, [pc, #16] ; (8001d3c <__NVIC_EnableIRQ+0x30>) + 8001d2c: 2101 movs r1, #1 + 8001d2e: 4091 lsls r1, r2 + 8001d30: 000a movs r2, r1 + 8001d32: 601a str r2, [r3, #0] + } +} + 8001d34: 46c0 nop ; (mov r8, r8) + 8001d36: 46bd mov sp, r7 + 8001d38: b002 add sp, #8 + 8001d3a: bd80 pop {r7, pc} + 8001d3c: e000e100 .word 0xe000e100 + +08001d40 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8001d40: b590 push {r4, r7, lr} + 8001d42: b083 sub sp, #12 + 8001d44: af00 add r7, sp, #0 + 8001d46: 0002 movs r2, r0 + 8001d48: 6039 str r1, [r7, #0] + 8001d4a: 1dfb adds r3, r7, #7 + 8001d4c: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 8001d4e: 1dfb adds r3, r7, #7 + 8001d50: 781b ldrb r3, [r3, #0] + 8001d52: 2b7f cmp r3, #127 ; 0x7f + 8001d54: d828 bhi.n 8001da8 <__NVIC_SetPriority+0x68> + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8001d56: 4a2f ldr r2, [pc, #188] ; (8001e14 <__NVIC_SetPriority+0xd4>) + 8001d58: 1dfb adds r3, r7, #7 + 8001d5a: 781b ldrb r3, [r3, #0] + 8001d5c: b25b sxtb r3, r3 + 8001d5e: 089b lsrs r3, r3, #2 + 8001d60: 33c0 adds r3, #192 ; 0xc0 + 8001d62: 009b lsls r3, r3, #2 + 8001d64: 589b ldr r3, [r3, r2] + 8001d66: 1dfa adds r2, r7, #7 + 8001d68: 7812 ldrb r2, [r2, #0] + 8001d6a: 0011 movs r1, r2 + 8001d6c: 2203 movs r2, #3 + 8001d6e: 400a ands r2, r1 + 8001d70: 00d2 lsls r2, r2, #3 + 8001d72: 21ff movs r1, #255 ; 0xff + 8001d74: 4091 lsls r1, r2 + 8001d76: 000a movs r2, r1 + 8001d78: 43d2 mvns r2, r2 + 8001d7a: 401a ands r2, r3 + 8001d7c: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8001d7e: 683b ldr r3, [r7, #0] + 8001d80: 019b lsls r3, r3, #6 + 8001d82: 22ff movs r2, #255 ; 0xff + 8001d84: 401a ands r2, r3 + 8001d86: 1dfb adds r3, r7, #7 + 8001d88: 781b ldrb r3, [r3, #0] + 8001d8a: 0018 movs r0, r3 + 8001d8c: 2303 movs r3, #3 + 8001d8e: 4003 ands r3, r0 + 8001d90: 00db lsls r3, r3, #3 + 8001d92: 409a lsls r2, r3 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8001d94: 481f ldr r0, [pc, #124] ; (8001e14 <__NVIC_SetPriority+0xd4>) + 8001d96: 1dfb adds r3, r7, #7 + 8001d98: 781b ldrb r3, [r3, #0] + 8001d9a: b25b sxtb r3, r3 + 8001d9c: 089b lsrs r3, r3, #2 + 8001d9e: 430a orrs r2, r1 + 8001da0: 33c0 adds r3, #192 ; 0xc0 + 8001da2: 009b lsls r3, r3, #2 + 8001da4: 501a str r2, [r3, r0] + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + 8001da6: e031 b.n 8001e0c <__NVIC_SetPriority+0xcc> + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8001da8: 4a1b ldr r2, [pc, #108] ; (8001e18 <__NVIC_SetPriority+0xd8>) + 8001daa: 1dfb adds r3, r7, #7 + 8001dac: 781b ldrb r3, [r3, #0] + 8001dae: 0019 movs r1, r3 + 8001db0: 230f movs r3, #15 + 8001db2: 400b ands r3, r1 + 8001db4: 3b08 subs r3, #8 + 8001db6: 089b lsrs r3, r3, #2 + 8001db8: 3306 adds r3, #6 + 8001dba: 009b lsls r3, r3, #2 + 8001dbc: 18d3 adds r3, r2, r3 + 8001dbe: 3304 adds r3, #4 + 8001dc0: 681b ldr r3, [r3, #0] + 8001dc2: 1dfa adds r2, r7, #7 + 8001dc4: 7812 ldrb r2, [r2, #0] + 8001dc6: 0011 movs r1, r2 + 8001dc8: 2203 movs r2, #3 + 8001dca: 400a ands r2, r1 + 8001dcc: 00d2 lsls r2, r2, #3 + 8001dce: 21ff movs r1, #255 ; 0xff + 8001dd0: 4091 lsls r1, r2 + 8001dd2: 000a movs r2, r1 + 8001dd4: 43d2 mvns r2, r2 + 8001dd6: 401a ands r2, r3 + 8001dd8: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8001dda: 683b ldr r3, [r7, #0] + 8001ddc: 019b lsls r3, r3, #6 + 8001dde: 22ff movs r2, #255 ; 0xff + 8001de0: 401a ands r2, r3 + 8001de2: 1dfb adds r3, r7, #7 + 8001de4: 781b ldrb r3, [r3, #0] + 8001de6: 0018 movs r0, r3 + 8001de8: 2303 movs r3, #3 + 8001dea: 4003 ands r3, r0 + 8001dec: 00db lsls r3, r3, #3 + 8001dee: 409a lsls r2, r3 + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8001df0: 4809 ldr r0, [pc, #36] ; (8001e18 <__NVIC_SetPriority+0xd8>) + 8001df2: 1dfb adds r3, r7, #7 + 8001df4: 781b ldrb r3, [r3, #0] + 8001df6: 001c movs r4, r3 + 8001df8: 230f movs r3, #15 + 8001dfa: 4023 ands r3, r4 + 8001dfc: 3b08 subs r3, #8 + 8001dfe: 089b lsrs r3, r3, #2 + 8001e00: 430a orrs r2, r1 + 8001e02: 3306 adds r3, #6 + 8001e04: 009b lsls r3, r3, #2 + 8001e06: 18c3 adds r3, r0, r3 + 8001e08: 3304 adds r3, #4 + 8001e0a: 601a str r2, [r3, #0] +} + 8001e0c: 46c0 nop ; (mov r8, r8) + 8001e0e: 46bd mov sp, r7 + 8001e10: b003 add sp, #12 + 8001e12: bd90 pop {r4, r7, pc} + 8001e14: e000e100 .word 0xe000e100 + 8001e18: e000ed00 .word 0xe000ed00 + +08001e1c : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8001e1c: b580 push {r7, lr} + 8001e1e: b082 sub sp, #8 + 8001e20: af00 add r7, sp, #0 + 8001e22: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8001e24: 687b ldr r3, [r7, #4] + 8001e26: 1e5a subs r2, r3, #1 + 8001e28: 2380 movs r3, #128 ; 0x80 + 8001e2a: 045b lsls r3, r3, #17 + 8001e2c: 429a cmp r2, r3 + 8001e2e: d301 bcc.n 8001e34 + { + return (1UL); /* Reload value impossible */ + 8001e30: 2301 movs r3, #1 + 8001e32: e010 b.n 8001e56 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8001e34: 4b0a ldr r3, [pc, #40] ; (8001e60 ) + 8001e36: 687a ldr r2, [r7, #4] + 8001e38: 3a01 subs r2, #1 + 8001e3a: 605a str r2, [r3, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8001e3c: 2301 movs r3, #1 + 8001e3e: 425b negs r3, r3 + 8001e40: 2103 movs r1, #3 + 8001e42: 0018 movs r0, r3 + 8001e44: f7ff ff7c bl 8001d40 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8001e48: 4b05 ldr r3, [pc, #20] ; (8001e60 ) + 8001e4a: 2200 movs r2, #0 + 8001e4c: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8001e4e: 4b04 ldr r3, [pc, #16] ; (8001e60 ) + 8001e50: 2207 movs r2, #7 + 8001e52: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8001e54: 2300 movs r3, #0 +} + 8001e56: 0018 movs r0, r3 + 8001e58: 46bd mov sp, r7 + 8001e5a: b002 add sp, #8 + 8001e5c: bd80 pop {r7, pc} + 8001e5e: 46c0 nop ; (mov r8, r8) + 8001e60: e000e010 .word 0xe000e010 + +08001e64 : + * with stm32l0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0+ based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001e64: b580 push {r7, lr} + 8001e66: b084 sub sp, #16 + 8001e68: af00 add r7, sp, #0 + 8001e6a: 60b9 str r1, [r7, #8] + 8001e6c: 607a str r2, [r7, #4] + 8001e6e: 210f movs r1, #15 + 8001e70: 187b adds r3, r7, r1 + 8001e72: 1c02 adds r2, r0, #0 + 8001e74: 701a strb r2, [r3, #0] + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); + 8001e76: 68ba ldr r2, [r7, #8] + 8001e78: 187b adds r3, r7, r1 + 8001e7a: 781b ldrb r3, [r3, #0] + 8001e7c: b25b sxtb r3, r3 + 8001e7e: 0011 movs r1, r2 + 8001e80: 0018 movs r0, r3 + 8001e82: f7ff ff5d bl 8001d40 <__NVIC_SetPriority> +} + 8001e86: 46c0 nop ; (mov r8, r8) + 8001e88: 46bd mov sp, r7 + 8001e8a: b004 add sp, #16 + 8001e8c: bd80 pop {r7, pc} + +08001e8e : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001e8e: b580 push {r7, lr} + 8001e90: b082 sub sp, #8 + 8001e92: af00 add r7, sp, #0 + 8001e94: 0002 movs r2, r0 + 8001e96: 1dfb adds r3, r7, #7 + 8001e98: 701a strb r2, [r3, #0] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8001e9a: 1dfb adds r3, r7, #7 + 8001e9c: 781b ldrb r3, [r3, #0] + 8001e9e: b25b sxtb r3, r3 + 8001ea0: 0018 movs r0, r3 + 8001ea2: f7ff ff33 bl 8001d0c <__NVIC_EnableIRQ> +} + 8001ea6: 46c0 nop ; (mov r8, r8) + 8001ea8: 46bd mov sp, r7 + 8001eaa: b002 add sp, #8 + 8001eac: bd80 pop {r7, pc} + +08001eae : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8001eae: b580 push {r7, lr} + 8001eb0: b082 sub sp, #8 + 8001eb2: af00 add r7, sp, #0 + 8001eb4: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8001eb6: 687b ldr r3, [r7, #4] + 8001eb8: 0018 movs r0, r3 + 8001eba: f7ff ffaf bl 8001e1c + 8001ebe: 0003 movs r3, r0 +} + 8001ec0: 0018 movs r0, r3 + 8001ec2: 46bd mov sp, r7 + 8001ec4: b002 add sp, #8 + 8001ec6: bd80 pop {r7, pc} + +08001ec8 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + 8001ec8: b580 push {r7, lr} + 8001eca: b084 sub sp, #16 + 8001ecc: af00 add r7, sp, #0 + 8001ece: 6078 str r0, [r7, #4] + uint32_t tmp; + + /* Check the DMA handle allocation */ + if(hdma == NULL) + 8001ed0: 687b ldr r3, [r7, #4] + 8001ed2: 2b00 cmp r3, #0 + 8001ed4: d101 bne.n 8001eda + { + return HAL_ERROR; + 8001ed6: 2301 movs r3, #1 + 8001ed8: e061 b.n 8001f9e + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + /* Compute the channel index */ + /* Only one DMA: DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + 8001eda: 687b ldr r3, [r7, #4] + 8001edc: 681b ldr r3, [r3, #0] + 8001ede: 4a32 ldr r2, [pc, #200] ; (8001fa8 ) + 8001ee0: 4694 mov ip, r2 + 8001ee2: 4463 add r3, ip + 8001ee4: 2114 movs r1, #20 + 8001ee6: 0018 movs r0, r3 + 8001ee8: f7fe f90e bl 8000108 <__udivsi3> + 8001eec: 0003 movs r3, r0 + 8001eee: 009a lsls r2, r3, #2 + 8001ef0: 687b ldr r3, [r7, #4] + 8001ef2: 645a str r2, [r3, #68] ; 0x44 + hdma->DmaBaseAddress = DMA1; + 8001ef4: 687b ldr r3, [r7, #4] + 8001ef6: 4a2d ldr r2, [pc, #180] ; (8001fac ) + 8001ef8: 641a str r2, [r3, #64] ; 0x40 + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8001efa: 687b ldr r3, [r7, #4] + 8001efc: 2225 movs r2, #37 ; 0x25 + 8001efe: 2102 movs r1, #2 + 8001f00: 5499 strb r1, [r3, r2] + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + 8001f02: 687b ldr r3, [r7, #4] + 8001f04: 681b ldr r3, [r3, #0] + 8001f06: 681b ldr r3, [r3, #0] + 8001f08: 60fb str r3, [r7, #12] + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | + 8001f0a: 68fb ldr r3, [r7, #12] + 8001f0c: 4a28 ldr r2, [pc, #160] ; (8001fb0 ) + 8001f0e: 4013 ands r3, r2 + 8001f10: 60fb str r3, [r7, #12] + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + 8001f12: 687b ldr r3, [r7, #4] + 8001f14: 689a ldr r2, [r3, #8] + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8001f16: 687b ldr r3, [r7, #4] + 8001f18: 68db ldr r3, [r3, #12] + tmp |= hdma->Init.Direction | + 8001f1a: 431a orrs r2, r3 + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8001f1c: 687b ldr r3, [r7, #4] + 8001f1e: 691b ldr r3, [r3, #16] + 8001f20: 431a orrs r2, r3 + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 8001f22: 687b ldr r3, [r7, #4] + 8001f24: 695b ldr r3, [r3, #20] + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8001f26: 431a orrs r2, r3 + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 8001f28: 687b ldr r3, [r7, #4] + 8001f2a: 699b ldr r3, [r3, #24] + 8001f2c: 431a orrs r2, r3 + hdma->Init.Mode | hdma->Init.Priority; + 8001f2e: 687b ldr r3, [r7, #4] + 8001f30: 69db ldr r3, [r3, #28] + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 8001f32: 431a orrs r2, r3 + hdma->Init.Mode | hdma->Init.Priority; + 8001f34: 687b ldr r3, [r7, #4] + 8001f36: 6a1b ldr r3, [r3, #32] + 8001f38: 4313 orrs r3, r2 + tmp |= hdma->Init.Direction | + 8001f3a: 68fa ldr r2, [r7, #12] + 8001f3c: 4313 orrs r3, r2 + 8001f3e: 60fb str r3, [r7, #12] + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + 8001f40: 687b ldr r3, [r7, #4] + 8001f42: 681b ldr r3, [r3, #0] + 8001f44: 68fa ldr r2, [r7, #12] + 8001f46: 601a str r2, [r3, #0] + + /* Set request selection */ + if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) + 8001f48: 687b ldr r3, [r7, #4] + 8001f4a: 689a ldr r2, [r3, #8] + 8001f4c: 2380 movs r3, #128 ; 0x80 + 8001f4e: 01db lsls r3, r3, #7 + 8001f50: 429a cmp r2, r3 + 8001f52: d018 beq.n 8001f86 + { + /* Write to DMA channel selection register */ + /* Reset request selection for DMA1 Channelx */ + DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); + 8001f54: 4b17 ldr r3, [pc, #92] ; (8001fb4 ) + 8001f56: 681a ldr r2, [r3, #0] + 8001f58: 687b ldr r3, [r7, #4] + 8001f5a: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001f5c: 211c movs r1, #28 + 8001f5e: 400b ands r3, r1 + 8001f60: 210f movs r1, #15 + 8001f62: 4099 lsls r1, r3 + 8001f64: 000b movs r3, r1 + 8001f66: 43d9 mvns r1, r3 + 8001f68: 4b12 ldr r3, [pc, #72] ; (8001fb4 ) + 8001f6a: 400a ands r2, r1 + 8001f6c: 601a str r2, [r3, #0] + + /* Configure request selection for DMA1 Channelx */ + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); + 8001f6e: 4b11 ldr r3, [pc, #68] ; (8001fb4 ) + 8001f70: 6819 ldr r1, [r3, #0] + 8001f72: 687b ldr r3, [r7, #4] + 8001f74: 685a ldr r2, [r3, #4] + 8001f76: 687b ldr r3, [r7, #4] + 8001f78: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001f7a: 201c movs r0, #28 + 8001f7c: 4003 ands r3, r0 + 8001f7e: 409a lsls r2, r3 + 8001f80: 4b0c ldr r3, [pc, #48] ; (8001fb4 ) + 8001f82: 430a orrs r2, r1 + 8001f84: 601a str r2, [r3, #0] + } + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8001f86: 687b ldr r3, [r7, #4] + 8001f88: 2200 movs r2, #0 + 8001f8a: 63da str r2, [r3, #60] ; 0x3c + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + 8001f8c: 687b ldr r3, [r7, #4] + 8001f8e: 2225 movs r2, #37 ; 0x25 + 8001f90: 2101 movs r1, #1 + 8001f92: 5499 strb r1, [r3, r2] + + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + 8001f94: 687b ldr r3, [r7, #4] + 8001f96: 2224 movs r2, #36 ; 0x24 + 8001f98: 2100 movs r1, #0 + 8001f9a: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8001f9c: 2300 movs r3, #0 +} + 8001f9e: 0018 movs r0, r3 + 8001fa0: 46bd mov sp, r7 + 8001fa2: b004 add sp, #16 + 8001fa4: bd80 pop {r7, pc} + 8001fa6: 46c0 nop ; (mov r8, r8) + 8001fa8: bffdfff8 .word 0xbffdfff8 + 8001fac: 40020000 .word 0x40020000 + 8001fb0: ffff800f .word 0xffff800f + 8001fb4: 400200a8 .word 0x400200a8 + +08001fb8 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + 8001fb8: b580 push {r7, lr} + 8001fba: b084 sub sp, #16 + 8001fbc: af00 add r7, sp, #0 + 8001fbe: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8001fc0: 230f movs r3, #15 + 8001fc2: 18fb adds r3, r7, r3 + 8001fc4: 2200 movs r2, #0 + 8001fc6: 701a strb r2, [r3, #0] + + /* Check the DMA peripheral state */ + if(hdma->State != HAL_DMA_STATE_BUSY) + 8001fc8: 687b ldr r3, [r7, #4] + 8001fca: 2225 movs r2, #37 ; 0x25 + 8001fcc: 5c9b ldrb r3, [r3, r2] + 8001fce: b2db uxtb r3, r3 + 8001fd0: 2b02 cmp r3, #2 + 8001fd2: d008 beq.n 8001fe6 + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8001fd4: 687b ldr r3, [r7, #4] + 8001fd6: 2204 movs r2, #4 + 8001fd8: 63da str r2, [r3, #60] ; 0x3c + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001fda: 687b ldr r3, [r7, #4] + 8001fdc: 2224 movs r2, #36 ; 0x24 + 8001fde: 2100 movs r1, #0 + 8001fe0: 5499 strb r1, [r3, r2] + + return HAL_ERROR; + 8001fe2: 2301 movs r3, #1 + 8001fe4: e024 b.n 8002030 + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8001fe6: 687b ldr r3, [r7, #4] + 8001fe8: 681b ldr r3, [r3, #0] + 8001fea: 681a ldr r2, [r3, #0] + 8001fec: 687b ldr r3, [r7, #4] + 8001fee: 681b ldr r3, [r3, #0] + 8001ff0: 210e movs r1, #14 + 8001ff2: 438a bics r2, r1 + 8001ff4: 601a str r2, [r3, #0] + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 8001ff6: 687b ldr r3, [r7, #4] + 8001ff8: 681b ldr r3, [r3, #0] + 8001ffa: 681a ldr r2, [r3, #0] + 8001ffc: 687b ldr r3, [r7, #4] + 8001ffe: 681b ldr r3, [r3, #0] + 8002000: 2101 movs r1, #1 + 8002002: 438a bics r2, r1 + 8002004: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); + 8002006: 687b ldr r3, [r7, #4] + 8002008: 6c5b ldr r3, [r3, #68] ; 0x44 + 800200a: 221c movs r2, #28 + 800200c: 401a ands r2, r3 + 800200e: 687b ldr r3, [r7, #4] + 8002010: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002012: 2101 movs r1, #1 + 8002014: 4091 lsls r1, r2 + 8002016: 000a movs r2, r1 + 8002018: 605a str r2, [r3, #4] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 800201a: 687b ldr r3, [r7, #4] + 800201c: 2225 movs r2, #37 ; 0x25 + 800201e: 2101 movs r1, #1 + 8002020: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8002022: 687b ldr r3, [r7, #4] + 8002024: 2224 movs r2, #36 ; 0x24 + 8002026: 2100 movs r1, #0 + 8002028: 5499 strb r1, [r3, r2] + + return status; + 800202a: 230f movs r3, #15 + 800202c: 18fb adds r3, r7, r3 + 800202e: 781b ldrb r3, [r3, #0] + } +} + 8002030: 0018 movs r0, r3 + 8002032: 46bd mov sp, r7 + 8002034: b004 add sp, #16 + 8002036: bd80 pop {r7, pc} + +08002038 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 8002038: b580 push {r7, lr} + 800203a: b084 sub sp, #16 + 800203c: af00 add r7, sp, #0 + 800203e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002040: 210f movs r1, #15 + 8002042: 187b adds r3, r7, r1 + 8002044: 2200 movs r2, #0 + 8002046: 701a strb r2, [r3, #0] + + if(HAL_DMA_STATE_BUSY != hdma->State) + 8002048: 687b ldr r3, [r7, #4] + 800204a: 2225 movs r2, #37 ; 0x25 + 800204c: 5c9b ldrb r3, [r3, r2] + 800204e: b2db uxtb r3, r3 + 8002050: 2b02 cmp r3, #2 + 8002052: d006 beq.n 8002062 + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8002054: 687b ldr r3, [r7, #4] + 8002056: 2204 movs r2, #4 + 8002058: 63da str r2, [r3, #60] ; 0x3c + + status = HAL_ERROR; + 800205a: 187b adds r3, r7, r1 + 800205c: 2201 movs r2, #1 + 800205e: 701a strb r2, [r3, #0] + 8002060: e02a b.n 80020b8 + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8002062: 687b ldr r3, [r7, #4] + 8002064: 681b ldr r3, [r3, #0] + 8002066: 681a ldr r2, [r3, #0] + 8002068: 687b ldr r3, [r7, #4] + 800206a: 681b ldr r3, [r3, #0] + 800206c: 210e movs r1, #14 + 800206e: 438a bics r2, r1 + 8002070: 601a str r2, [r3, #0] + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 8002072: 687b ldr r3, [r7, #4] + 8002074: 681b ldr r3, [r3, #0] + 8002076: 681a ldr r2, [r3, #0] + 8002078: 687b ldr r3, [r7, #4] + 800207a: 681b ldr r3, [r3, #0] + 800207c: 2101 movs r1, #1 + 800207e: 438a bics r2, r1 + 8002080: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); + 8002082: 687b ldr r3, [r7, #4] + 8002084: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002086: 221c movs r2, #28 + 8002088: 401a ands r2, r3 + 800208a: 687b ldr r3, [r7, #4] + 800208c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800208e: 2101 movs r1, #1 + 8002090: 4091 lsls r1, r2 + 8002092: 000a movs r2, r1 + 8002094: 605a str r2, [r3, #4] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002096: 687b ldr r3, [r7, #4] + 8002098: 2225 movs r2, #37 ; 0x25 + 800209a: 2101 movs r1, #1 + 800209c: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 800209e: 687b ldr r3, [r7, #4] + 80020a0: 2224 movs r2, #36 ; 0x24 + 80020a2: 2100 movs r1, #0 + 80020a4: 5499 strb r1, [r3, r2] + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + 80020a6: 687b ldr r3, [r7, #4] + 80020a8: 6b9b ldr r3, [r3, #56] ; 0x38 + 80020aa: 2b00 cmp r3, #0 + 80020ac: d004 beq.n 80020b8 + { + hdma->XferAbortCallback(hdma); + 80020ae: 687b ldr r3, [r7, #4] + 80020b0: 6b9b ldr r3, [r3, #56] ; 0x38 + 80020b2: 687a ldr r2, [r7, #4] + 80020b4: 0010 movs r0, r2 + 80020b6: 4798 blx r3 + } + } + return status; + 80020b8: 230f movs r3, #15 + 80020ba: 18fb adds r3, r7, r3 + 80020bc: 781b ldrb r3, [r3, #0] +} + 80020be: 0018 movs r0, r3 + 80020c0: 46bd mov sp, r7 + 80020c2: b004 add sp, #16 + 80020c4: bd80 pop {r7, pc} + +080020c6 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + 80020c6: b580 push {r7, lr} + 80020c8: b084 sub sp, #16 + 80020ca: af00 add r7, sp, #0 + 80020cc: 6078 str r0, [r7, #4] + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + 80020ce: 687b ldr r3, [r7, #4] + 80020d0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80020d2: 681b ldr r3, [r3, #0] + 80020d4: 60fb str r3, [r7, #12] + uint32_t source_it = hdma->Instance->CCR; + 80020d6: 687b ldr r3, [r7, #4] + 80020d8: 681b ldr r3, [r3, #0] + 80020da: 681b ldr r3, [r3, #0] + 80020dc: 60bb str r3, [r7, #8] + + /* Half Transfer Complete Interrupt management ******************************/ + if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT))) + 80020de: 687b ldr r3, [r7, #4] + 80020e0: 6c5b ldr r3, [r3, #68] ; 0x44 + 80020e2: 221c movs r2, #28 + 80020e4: 4013 ands r3, r2 + 80020e6: 2204 movs r2, #4 + 80020e8: 409a lsls r2, r3 + 80020ea: 0013 movs r3, r2 + 80020ec: 68fa ldr r2, [r7, #12] + 80020ee: 4013 ands r3, r2 + 80020f0: d026 beq.n 8002140 + 80020f2: 68bb ldr r3, [r7, #8] + 80020f4: 2204 movs r2, #4 + 80020f6: 4013 ands r3, r2 + 80020f8: d022 beq.n 8002140 + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 80020fa: 687b ldr r3, [r7, #4] + 80020fc: 681b ldr r3, [r3, #0] + 80020fe: 681b ldr r3, [r3, #0] + 8002100: 2220 movs r2, #32 + 8002102: 4013 ands r3, r2 + 8002104: d107 bne.n 8002116 + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 8002106: 687b ldr r3, [r7, #4] + 8002108: 681b ldr r3, [r3, #0] + 800210a: 681a ldr r2, [r3, #0] + 800210c: 687b ldr r3, [r7, #4] + 800210e: 681b ldr r3, [r3, #0] + 8002110: 2104 movs r1, #4 + 8002112: 438a bics r2, r1 + 8002114: 601a str r2, [r3, #0] + } + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU); + 8002116: 687b ldr r3, [r7, #4] + 8002118: 6c5b ldr r3, [r3, #68] ; 0x44 + 800211a: 221c movs r2, #28 + 800211c: 401a ands r2, r3 + 800211e: 687b ldr r3, [r7, #4] + 8002120: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002122: 2104 movs r1, #4 + 8002124: 4091 lsls r1, r2 + 8002126: 000a movs r2, r1 + 8002128: 605a str r2, [r3, #4] + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + 800212a: 687b ldr r3, [r7, #4] + 800212c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800212e: 2b00 cmp r3, #0 + 8002130: d100 bne.n 8002134 + 8002132: e071 b.n 8002218 + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + 8002134: 687b ldr r3, [r7, #4] + 8002136: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002138: 687a ldr r2, [r7, #4] + 800213a: 0010 movs r0, r2 + 800213c: 4798 blx r3 + if(hdma->XferHalfCpltCallback != NULL) + 800213e: e06b b.n 8002218 + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) + 8002140: 687b ldr r3, [r7, #4] + 8002142: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002144: 221c movs r2, #28 + 8002146: 4013 ands r3, r2 + 8002148: 2202 movs r2, #2 + 800214a: 409a lsls r2, r3 + 800214c: 0013 movs r3, r2 + 800214e: 68fa ldr r2, [r7, #12] + 8002150: 4013 ands r3, r2 + 8002152: d02d beq.n 80021b0 + 8002154: 68bb ldr r3, [r7, #8] + 8002156: 2202 movs r2, #2 + 8002158: 4013 ands r3, r2 + 800215a: d029 beq.n 80021b0 + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 800215c: 687b ldr r3, [r7, #4] + 800215e: 681b ldr r3, [r3, #0] + 8002160: 681b ldr r3, [r3, #0] + 8002162: 2220 movs r2, #32 + 8002164: 4013 ands r3, r2 + 8002166: d10b bne.n 8002180 + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + 8002168: 687b ldr r3, [r7, #4] + 800216a: 681b ldr r3, [r3, #0] + 800216c: 681a ldr r2, [r3, #0] + 800216e: 687b ldr r3, [r7, #4] + 8002170: 681b ldr r3, [r3, #0] + 8002172: 210a movs r1, #10 + 8002174: 438a bics r2, r1 + 8002176: 601a str r2, [r3, #0] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002178: 687b ldr r3, [r7, #4] + 800217a: 2225 movs r2, #37 ; 0x25 + 800217c: 2101 movs r1, #1 + 800217e: 5499 strb r1, [r3, r2] + } + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU)); + 8002180: 687b ldr r3, [r7, #4] + 8002182: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002184: 221c movs r2, #28 + 8002186: 401a ands r2, r3 + 8002188: 687b ldr r3, [r7, #4] + 800218a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800218c: 2102 movs r1, #2 + 800218e: 4091 lsls r1, r2 + 8002190: 000a movs r2, r1 + 8002192: 605a str r2, [r3, #4] + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8002194: 687b ldr r3, [r7, #4] + 8002196: 2224 movs r2, #36 ; 0x24 + 8002198: 2100 movs r1, #0 + 800219a: 5499 strb r1, [r3, r2] + + if(hdma->XferCpltCallback != NULL) + 800219c: 687b ldr r3, [r7, #4] + 800219e: 6adb ldr r3, [r3, #44] ; 0x2c + 80021a0: 2b00 cmp r3, #0 + 80021a2: d039 beq.n 8002218 + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + 80021a4: 687b ldr r3, [r7, #4] + 80021a6: 6adb ldr r3, [r3, #44] ; 0x2c + 80021a8: 687a ldr r2, [r7, #4] + 80021aa: 0010 movs r0, r2 + 80021ac: 4798 blx r3 + if(hdma->XferCpltCallback != NULL) + 80021ae: e033 b.n 8002218 + } + } + + /* Transfer Error Interrupt management **************************************/ + else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE))) + 80021b0: 687b ldr r3, [r7, #4] + 80021b2: 6c5b ldr r3, [r3, #68] ; 0x44 + 80021b4: 221c movs r2, #28 + 80021b6: 4013 ands r3, r2 + 80021b8: 2208 movs r2, #8 + 80021ba: 409a lsls r2, r3 + 80021bc: 0013 movs r3, r2 + 80021be: 68fa ldr r2, [r7, #12] + 80021c0: 4013 ands r3, r2 + 80021c2: d02a beq.n 800221a + 80021c4: 68bb ldr r3, [r7, #8] + 80021c6: 2208 movs r2, #8 + 80021c8: 4013 ands r3, r2 + 80021ca: d026 beq.n 800221a + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 80021cc: 687b ldr r3, [r7, #4] + 80021ce: 681b ldr r3, [r3, #0] + 80021d0: 681a ldr r2, [r3, #0] + 80021d2: 687b ldr r3, [r7, #4] + 80021d4: 681b ldr r3, [r3, #0] + 80021d6: 210e movs r1, #14 + 80021d8: 438a bics r2, r1 + 80021da: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); + 80021dc: 687b ldr r3, [r7, #4] + 80021de: 6c5b ldr r3, [r3, #68] ; 0x44 + 80021e0: 221c movs r2, #28 + 80021e2: 401a ands r2, r3 + 80021e4: 687b ldr r3, [r7, #4] + 80021e6: 6c1b ldr r3, [r3, #64] ; 0x40 + 80021e8: 2101 movs r1, #1 + 80021ea: 4091 lsls r1, r2 + 80021ec: 000a movs r2, r1 + 80021ee: 605a str r2, [r3, #4] + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + 80021f0: 687b ldr r3, [r7, #4] + 80021f2: 2201 movs r2, #1 + 80021f4: 63da str r2, [r3, #60] ; 0x3c + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 80021f6: 687b ldr r3, [r7, #4] + 80021f8: 2225 movs r2, #37 ; 0x25 + 80021fa: 2101 movs r1, #1 + 80021fc: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 80021fe: 687b ldr r3, [r7, #4] + 8002200: 2224 movs r2, #36 ; 0x24 + 8002202: 2100 movs r1, #0 + 8002204: 5499 strb r1, [r3, r2] + + if (hdma->XferErrorCallback != NULL) + 8002206: 687b ldr r3, [r7, #4] + 8002208: 6b5b ldr r3, [r3, #52] ; 0x34 + 800220a: 2b00 cmp r3, #0 + 800220c: d005 beq.n 800221a + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + 800220e: 687b ldr r3, [r7, #4] + 8002210: 6b5b ldr r3, [r3, #52] ; 0x34 + 8002212: 687a ldr r2, [r7, #4] + 8002214: 0010 movs r0, r2 + 8002216: 4798 blx r3 + } + else + { + /* Nothing To Do */ + } + return; + 8002218: 46c0 nop ; (mov r8, r8) + 800221a: 46c0 nop ; (mov r8, r8) +} + 800221c: 46bd mov sp, r7 + 800221e: b004 add sp, #16 + 8002220: bd80 pop {r7, pc} + ... + +08002224 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8002224: b580 push {r7, lr} + 8002226: b086 sub sp, #24 + 8002228: af00 add r7, sp, #0 + 800222a: 6078 str r0, [r7, #4] + 800222c: 6039 str r1, [r7, #0] + uint32_t position = 0x00U; + 800222e: 2300 movs r3, #0 + 8002230: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00U; + 8002232: 2300 movs r3, #0 + 8002234: 60fb str r3, [r7, #12] + uint32_t temp = 0x00U; + 8002236: 2300 movs r3, #0 + 8002238: 613b str r3, [r7, #16] + /* Check the parameters */ + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, (GPIO_Init->Pin))); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 800223a: e149 b.n 80024d0 + { + /* Get the IO position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 800223c: 683b ldr r3, [r7, #0] + 800223e: 681b ldr r3, [r3, #0] + 8002240: 2101 movs r1, #1 + 8002242: 697a ldr r2, [r7, #20] + 8002244: 4091 lsls r1, r2 + 8002246: 000a movs r2, r1 + 8002248: 4013 ands r3, r2 + 800224a: 60fb str r3, [r7, #12] + + if (iocurrent) + 800224c: 68fb ldr r3, [r7, #12] + 800224e: 2b00 cmp r3, #0 + 8002250: d100 bne.n 8002254 + 8002252: e13a b.n 80024ca + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8002254: 683b ldr r3, [r7, #0] + 8002256: 685b ldr r3, [r3, #4] + 8002258: 2203 movs r2, #3 + 800225a: 4013 ands r3, r2 + 800225c: 2b01 cmp r3, #1 + 800225e: d005 beq.n 800226c + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8002260: 683b ldr r3, [r7, #0] + 8002262: 685b ldr r3, [r3, #4] + 8002264: 2203 movs r2, #3 + 8002266: 4013 ands r3, r2 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8002268: 2b02 cmp r3, #2 + 800226a: d130 bne.n 80022ce + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 800226c: 687b ldr r3, [r7, #4] + 800226e: 689b ldr r3, [r3, #8] + 8002270: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U)); + 8002272: 697b ldr r3, [r7, #20] + 8002274: 005b lsls r3, r3, #1 + 8002276: 2203 movs r2, #3 + 8002278: 409a lsls r2, r3 + 800227a: 0013 movs r3, r2 + 800227c: 43da mvns r2, r3 + 800227e: 693b ldr r3, [r7, #16] + 8002280: 4013 ands r3, r2 + 8002282: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2U)); + 8002284: 683b ldr r3, [r7, #0] + 8002286: 68da ldr r2, [r3, #12] + 8002288: 697b ldr r3, [r7, #20] + 800228a: 005b lsls r3, r3, #1 + 800228c: 409a lsls r2, r3 + 800228e: 0013 movs r3, r2 + 8002290: 693a ldr r2, [r7, #16] + 8002292: 4313 orrs r3, r2 + 8002294: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8002296: 687b ldr r3, [r7, #4] + 8002298: 693a ldr r2, [r7, #16] + 800229a: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 800229c: 687b ldr r3, [r7, #4] + 800229e: 685b ldr r3, [r3, #4] + 80022a0: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 80022a2: 2201 movs r2, #1 + 80022a4: 697b ldr r3, [r7, #20] + 80022a6: 409a lsls r2, r3 + 80022a8: 0013 movs r3, r2 + 80022aa: 43da mvns r2, r3 + 80022ac: 693b ldr r3, [r7, #16] + 80022ae: 4013 ands r3, r2 + 80022b0: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 80022b2: 683b ldr r3, [r7, #0] + 80022b4: 685b ldr r3, [r3, #4] + 80022b6: 091b lsrs r3, r3, #4 + 80022b8: 2201 movs r2, #1 + 80022ba: 401a ands r2, r3 + 80022bc: 697b ldr r3, [r7, #20] + 80022be: 409a lsls r2, r3 + 80022c0: 0013 movs r3, r2 + 80022c2: 693a ldr r2, [r7, #16] + 80022c4: 4313 orrs r3, r2 + 80022c6: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 80022c8: 687b ldr r3, [r7, #4] + 80022ca: 693a ldr r2, [r7, #16] + 80022cc: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 80022ce: 683b ldr r3, [r7, #0] + 80022d0: 685b ldr r3, [r3, #4] + 80022d2: 2203 movs r2, #3 + 80022d4: 4013 ands r3, r2 + 80022d6: 2b03 cmp r3, #3 + 80022d8: d017 beq.n 800230a + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 80022da: 687b ldr r3, [r7, #4] + 80022dc: 68db ldr r3, [r3, #12] + 80022de: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 80022e0: 697b ldr r3, [r7, #20] + 80022e2: 005b lsls r3, r3, #1 + 80022e4: 2203 movs r2, #3 + 80022e6: 409a lsls r2, r3 + 80022e8: 0013 movs r3, r2 + 80022ea: 43da mvns r2, r3 + 80022ec: 693b ldr r3, [r7, #16] + 80022ee: 4013 ands r3, r2 + 80022f0: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 80022f2: 683b ldr r3, [r7, #0] + 80022f4: 689a ldr r2, [r3, #8] + 80022f6: 697b ldr r3, [r7, #20] + 80022f8: 005b lsls r3, r3, #1 + 80022fa: 409a lsls r2, r3 + 80022fc: 0013 movs r3, r2 + 80022fe: 693a ldr r2, [r7, #16] + 8002300: 4313 orrs r3, r2 + 8002302: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 8002304: 687b ldr r3, [r7, #4] + 8002306: 693a ldr r2, [r7, #16] + 8002308: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 800230a: 683b ldr r3, [r7, #0] + 800230c: 685b ldr r3, [r3, #4] + 800230e: 2203 movs r2, #3 + 8002310: 4013 ands r3, r2 + 8002312: 2b02 cmp r3, #2 + 8002314: d123 bne.n 800235e + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + 8002316: 697b ldr r3, [r7, #20] + 8002318: 08da lsrs r2, r3, #3 + 800231a: 687b ldr r3, [r7, #4] + 800231c: 3208 adds r2, #8 + 800231e: 0092 lsls r2, r2, #2 + 8002320: 58d3 ldr r3, [r2, r3] + 8002322: 613b str r3, [r7, #16] + temp &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U)); + 8002324: 697b ldr r3, [r7, #20] + 8002326: 2207 movs r2, #7 + 8002328: 4013 ands r3, r2 + 800232a: 009b lsls r3, r3, #2 + 800232c: 220f movs r2, #15 + 800232e: 409a lsls r2, r3 + 8002330: 0013 movs r3, r2 + 8002332: 43da mvns r2, r3 + 8002334: 693b ldr r3, [r7, #16] + 8002336: 4013 ands r3, r2 + 8002338: 613b str r3, [r7, #16] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U)); + 800233a: 683b ldr r3, [r7, #0] + 800233c: 691a ldr r2, [r3, #16] + 800233e: 697b ldr r3, [r7, #20] + 8002340: 2107 movs r1, #7 + 8002342: 400b ands r3, r1 + 8002344: 009b lsls r3, r3, #2 + 8002346: 409a lsls r2, r3 + 8002348: 0013 movs r3, r2 + 800234a: 693a ldr r2, [r7, #16] + 800234c: 4313 orrs r3, r2 + 800234e: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3U] = temp; + 8002350: 697b ldr r3, [r7, #20] + 8002352: 08da lsrs r2, r3, #3 + 8002354: 687b ldr r3, [r7, #4] + 8002356: 3208 adds r2, #8 + 8002358: 0092 lsls r2, r2, #2 + 800235a: 6939 ldr r1, [r7, #16] + 800235c: 50d1 str r1, [r2, r3] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 800235e: 687b ldr r3, [r7, #4] + 8002360: 681b ldr r3, [r3, #0] + 8002362: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 8002364: 697b ldr r3, [r7, #20] + 8002366: 005b lsls r3, r3, #1 + 8002368: 2203 movs r2, #3 + 800236a: 409a lsls r2, r3 + 800236c: 0013 movs r3, r2 + 800236e: 43da mvns r2, r3 + 8002370: 693b ldr r3, [r7, #16] + 8002372: 4013 ands r3, r2 + 8002374: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 8002376: 683b ldr r3, [r7, #0] + 8002378: 685b ldr r3, [r3, #4] + 800237a: 2203 movs r2, #3 + 800237c: 401a ands r2, r3 + 800237e: 697b ldr r3, [r7, #20] + 8002380: 005b lsls r3, r3, #1 + 8002382: 409a lsls r2, r3 + 8002384: 0013 movs r3, r2 + 8002386: 693a ldr r2, [r7, #16] + 8002388: 4313 orrs r3, r2 + 800238a: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 800238c: 687b ldr r3, [r7, #4] + 800238e: 693a ldr r2, [r7, #16] + 8002390: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 8002392: 683b ldr r3, [r7, #0] + 8002394: 685a ldr r2, [r3, #4] + 8002396: 23c0 movs r3, #192 ; 0xc0 + 8002398: 029b lsls r3, r3, #10 + 800239a: 4013 ands r3, r2 + 800239c: d100 bne.n 80023a0 + 800239e: e094 b.n 80024ca + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80023a0: 4b51 ldr r3, [pc, #324] ; (80024e8 ) + 80023a2: 6b5a ldr r2, [r3, #52] ; 0x34 + 80023a4: 4b50 ldr r3, [pc, #320] ; (80024e8 ) + 80023a6: 2101 movs r1, #1 + 80023a8: 430a orrs r2, r1 + 80023aa: 635a str r2, [r3, #52] ; 0x34 + + temp = SYSCFG->EXTICR[position >> 2U]; + 80023ac: 4a4f ldr r2, [pc, #316] ; (80024ec ) + 80023ae: 697b ldr r3, [r7, #20] + 80023b0: 089b lsrs r3, r3, #2 + 80023b2: 3302 adds r3, #2 + 80023b4: 009b lsls r3, r3, #2 + 80023b6: 589b ldr r3, [r3, r2] + 80023b8: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FUL) << (4U * (position & 0x03U))); + 80023ba: 697b ldr r3, [r7, #20] + 80023bc: 2203 movs r2, #3 + 80023be: 4013 ands r3, r2 + 80023c0: 009b lsls r3, r3, #2 + 80023c2: 220f movs r2, #15 + 80023c4: 409a lsls r2, r3 + 80023c6: 0013 movs r3, r2 + 80023c8: 43da mvns r2, r3 + 80023ca: 693b ldr r3, [r7, #16] + 80023cc: 4013 ands r3, r2 + 80023ce: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U))); + 80023d0: 687a ldr r2, [r7, #4] + 80023d2: 23a0 movs r3, #160 ; 0xa0 + 80023d4: 05db lsls r3, r3, #23 + 80023d6: 429a cmp r2, r3 + 80023d8: d013 beq.n 8002402 + 80023da: 687b ldr r3, [r7, #4] + 80023dc: 4a44 ldr r2, [pc, #272] ; (80024f0 ) + 80023de: 4293 cmp r3, r2 + 80023e0: d00d beq.n 80023fe + 80023e2: 687b ldr r3, [r7, #4] + 80023e4: 4a43 ldr r2, [pc, #268] ; (80024f4 ) + 80023e6: 4293 cmp r3, r2 + 80023e8: d007 beq.n 80023fa + 80023ea: 687b ldr r3, [r7, #4] + 80023ec: 4a42 ldr r2, [pc, #264] ; (80024f8 ) + 80023ee: 4293 cmp r3, r2 + 80023f0: d101 bne.n 80023f6 + 80023f2: 2305 movs r3, #5 + 80023f4: e006 b.n 8002404 + 80023f6: 2306 movs r3, #6 + 80023f8: e004 b.n 8002404 + 80023fa: 2302 movs r3, #2 + 80023fc: e002 b.n 8002404 + 80023fe: 2301 movs r3, #1 + 8002400: e000 b.n 8002404 + 8002402: 2300 movs r3, #0 + 8002404: 697a ldr r2, [r7, #20] + 8002406: 2103 movs r1, #3 + 8002408: 400a ands r2, r1 + 800240a: 0092 lsls r2, r2, #2 + 800240c: 4093 lsls r3, r2 + 800240e: 693a ldr r2, [r7, #16] + 8002410: 4313 orrs r3, r2 + 8002412: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2U] = temp; + 8002414: 4935 ldr r1, [pc, #212] ; (80024ec ) + 8002416: 697b ldr r3, [r7, #20] + 8002418: 089b lsrs r3, r3, #2 + 800241a: 3302 adds r3, #2 + 800241c: 009b lsls r3, r3, #2 + 800241e: 693a ldr r2, [r7, #16] + 8002420: 505a str r2, [r3, r1] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8002422: 4b36 ldr r3, [pc, #216] ; (80024fc ) + 8002424: 681b ldr r3, [r3, #0] + 8002426: 613b str r3, [r7, #16] + temp &= ~((uint32_t)iocurrent); + 8002428: 68fb ldr r3, [r7, #12] + 800242a: 43da mvns r2, r3 + 800242c: 693b ldr r3, [r7, #16] + 800242e: 4013 ands r3, r2 + 8002430: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 8002432: 683b ldr r3, [r7, #0] + 8002434: 685a ldr r2, [r3, #4] + 8002436: 2380 movs r3, #128 ; 0x80 + 8002438: 025b lsls r3, r3, #9 + 800243a: 4013 ands r3, r2 + 800243c: d003 beq.n 8002446 + { + temp |= iocurrent; + 800243e: 693a ldr r2, [r7, #16] + 8002440: 68fb ldr r3, [r7, #12] + 8002442: 4313 orrs r3, r2 + 8002444: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 8002446: 4b2d ldr r3, [pc, #180] ; (80024fc ) + 8002448: 693a ldr r2, [r7, #16] + 800244a: 601a str r2, [r3, #0] + + temp = EXTI->EMR; + 800244c: 4b2b ldr r3, [pc, #172] ; (80024fc ) + 800244e: 685b ldr r3, [r3, #4] + 8002450: 613b str r3, [r7, #16] + temp &= ~((uint32_t)iocurrent); + 8002452: 68fb ldr r3, [r7, #12] + 8002454: 43da mvns r2, r3 + 8002456: 693b ldr r3, [r7, #16] + 8002458: 4013 ands r3, r2 + 800245a: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 800245c: 683b ldr r3, [r7, #0] + 800245e: 685a ldr r2, [r3, #4] + 8002460: 2380 movs r3, #128 ; 0x80 + 8002462: 029b lsls r3, r3, #10 + 8002464: 4013 ands r3, r2 + 8002466: d003 beq.n 8002470 + { + temp |= iocurrent; + 8002468: 693a ldr r2, [r7, #16] + 800246a: 68fb ldr r3, [r7, #12] + 800246c: 4313 orrs r3, r2 + 800246e: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8002470: 4b22 ldr r3, [pc, #136] ; (80024fc ) + 8002472: 693a ldr r2, [r7, #16] + 8002474: 605a str r2, [r3, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8002476: 4b21 ldr r3, [pc, #132] ; (80024fc ) + 8002478: 689b ldr r3, [r3, #8] + 800247a: 613b str r3, [r7, #16] + temp &= ~((uint32_t)iocurrent); + 800247c: 68fb ldr r3, [r7, #12] + 800247e: 43da mvns r2, r3 + 8002480: 693b ldr r3, [r7, #16] + 8002482: 4013 ands r3, r2 + 8002484: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 8002486: 683b ldr r3, [r7, #0] + 8002488: 685a ldr r2, [r3, #4] + 800248a: 2380 movs r3, #128 ; 0x80 + 800248c: 035b lsls r3, r3, #13 + 800248e: 4013 ands r3, r2 + 8002490: d003 beq.n 800249a + { + temp |= iocurrent; + 8002492: 693a ldr r2, [r7, #16] + 8002494: 68fb ldr r3, [r7, #12] + 8002496: 4313 orrs r3, r2 + 8002498: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 800249a: 4b18 ldr r3, [pc, #96] ; (80024fc ) + 800249c: 693a ldr r2, [r7, #16] + 800249e: 609a str r2, [r3, #8] + + temp = EXTI->FTSR; + 80024a0: 4b16 ldr r3, [pc, #88] ; (80024fc ) + 80024a2: 68db ldr r3, [r3, #12] + 80024a4: 613b str r3, [r7, #16] + temp &= ~((uint32_t)iocurrent); + 80024a6: 68fb ldr r3, [r7, #12] + 80024a8: 43da mvns r2, r3 + 80024aa: 693b ldr r3, [r7, #16] + 80024ac: 4013 ands r3, r2 + 80024ae: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 80024b0: 683b ldr r3, [r7, #0] + 80024b2: 685a ldr r2, [r3, #4] + 80024b4: 2380 movs r3, #128 ; 0x80 + 80024b6: 039b lsls r3, r3, #14 + 80024b8: 4013 ands r3, r2 + 80024ba: d003 beq.n 80024c4 + { + temp |= iocurrent; + 80024bc: 693a ldr r2, [r7, #16] + 80024be: 68fb ldr r3, [r7, #12] + 80024c0: 4313 orrs r3, r2 + 80024c2: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 80024c4: 4b0d ldr r3, [pc, #52] ; (80024fc ) + 80024c6: 693a ldr r2, [r7, #16] + 80024c8: 60da str r2, [r3, #12] + } + } + position++; + 80024ca: 697b ldr r3, [r7, #20] + 80024cc: 3301 adds r3, #1 + 80024ce: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 80024d0: 683b ldr r3, [r7, #0] + 80024d2: 681a ldr r2, [r3, #0] + 80024d4: 697b ldr r3, [r7, #20] + 80024d6: 40da lsrs r2, r3 + 80024d8: 1e13 subs r3, r2, #0 + 80024da: d000 beq.n 80024de + 80024dc: e6ae b.n 800223c + } +} + 80024de: 46c0 nop ; (mov r8, r8) + 80024e0: 46c0 nop ; (mov r8, r8) + 80024e2: 46bd mov sp, r7 + 80024e4: b006 add sp, #24 + 80024e6: bd80 pop {r7, pc} + 80024e8: 40021000 .word 0x40021000 + 80024ec: 40010000 .word 0x40010000 + 80024f0: 50000400 .word 0x50000400 + 80024f4: 50000800 .word 0x50000800 + 80024f8: 50001c00 .word 0x50001c00 + 80024fc: 40010400 .word 0x40010400 + +08002500 : + * GPIO_PIN_RESET: to clear the port pin + * GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8002500: b580 push {r7, lr} + 8002502: b082 sub sp, #8 + 8002504: af00 add r7, sp, #0 + 8002506: 6078 str r0, [r7, #4] + 8002508: 0008 movs r0, r1 + 800250a: 0011 movs r1, r2 + 800250c: 1cbb adds r3, r7, #2 + 800250e: 1c02 adds r2, r0, #0 + 8002510: 801a strh r2, [r3, #0] + 8002512: 1c7b adds r3, r7, #1 + 8002514: 1c0a adds r2, r1, #0 + 8002516: 701a strb r2, [r3, #0] + /* Check the parameters */ + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8002518: 1c7b adds r3, r7, #1 + 800251a: 781b ldrb r3, [r3, #0] + 800251c: 2b00 cmp r3, #0 + 800251e: d004 beq.n 800252a + { + GPIOx->BSRR = GPIO_Pin; + 8002520: 1cbb adds r3, r7, #2 + 8002522: 881a ldrh r2, [r3, #0] + 8002524: 687b ldr r3, [r7, #4] + 8002526: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = GPIO_Pin ; + } +} + 8002528: e003 b.n 8002532 + GPIOx->BRR = GPIO_Pin ; + 800252a: 1cbb adds r3, r7, #2 + 800252c: 881a ldrh r2, [r3, #0] + 800252e: 687b ldr r3, [r7, #4] + 8002530: 629a str r2, [r3, #40] ; 0x28 +} + 8002532: 46c0 nop ; (mov r8, r8) + 8002534: 46bd mov sp, r7 + 8002536: b002 add sp, #8 + 8002538: bd80 pop {r7, pc} + ... + +0800253c : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected to the EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 800253c: b580 push {r7, lr} + 800253e: b082 sub sp, #8 + 8002540: af00 add r7, sp, #0 + 8002542: 0002 movs r2, r0 + 8002544: 1dbb adds r3, r7, #6 + 8002546: 801a strh r2, [r3, #0] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 8002548: 4b09 ldr r3, [pc, #36] ; (8002570 ) + 800254a: 695b ldr r3, [r3, #20] + 800254c: 1dba adds r2, r7, #6 + 800254e: 8812 ldrh r2, [r2, #0] + 8002550: 4013 ands r3, r2 + 8002552: d008 beq.n 8002566 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 8002554: 4b06 ldr r3, [pc, #24] ; (8002570 ) + 8002556: 1dba adds r2, r7, #6 + 8002558: 8812 ldrh r2, [r2, #0] + 800255a: 615a str r2, [r3, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 800255c: 1dbb adds r3, r7, #6 + 800255e: 881b ldrh r3, [r3, #0] + 8002560: 0018 movs r0, r3 + 8002562: f000 f807 bl 8002574 + } +} + 8002566: 46c0 nop ; (mov r8, r8) + 8002568: 46bd mov sp, r7 + 800256a: b002 add sp, #8 + 800256c: bd80 pop {r7, pc} + 800256e: 46c0 nop ; (mov r8, r8) + 8002570: 40010400 .word 0x40010400 + +08002574 : + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the pins connected to the EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + 8002574: b580 push {r7, lr} + 8002576: b082 sub sp, #8 + 8002578: af00 add r7, sp, #0 + 800257a: 0002 movs r2, r0 + 800257c: 1dbb adds r3, r7, #6 + 800257e: 801a strh r2, [r3, #0] + UNUSED(GPIO_Pin); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + 8002580: 46c0 nop ; (mov r8, r8) + 8002582: 46bd mov sp, r7 + 8002584: b002 add sp, #8 + 8002586: bd80 pop {r7, pc} + +08002588 : + * LPTIM_InitTypeDef and initialize the associated handle. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) +{ + 8002588: b580 push {r7, lr} + 800258a: b084 sub sp, #16 + 800258c: af00 add r7, sp, #0 + 800258e: 6078 str r0, [r7, #4] + uint32_t tmpcfgr; + + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + 8002590: 687b ldr r3, [r7, #4] + 8002592: 2b00 cmp r3, #0 + 8002594: d101 bne.n 800259a + { + return HAL_ERROR; + 8002596: 2301 movs r3, #1 + 8002598: e078 b.n 800268c + } + assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); + assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); + assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); + + if (hlptim->State == HAL_LPTIM_STATE_RESET) + 800259a: 687b ldr r3, [r7, #4] + 800259c: 222e movs r2, #46 ; 0x2e + 800259e: 5c9b ldrb r3, [r3, r2] + 80025a0: b2db uxtb r3, r3 + 80025a2: 2b00 cmp r3, #0 + 80025a4: d107 bne.n 80025b6 + { + /* Allocate lock resource and initialize it */ + hlptim->Lock = HAL_UNLOCKED; + 80025a6: 687b ldr r3, [r7, #4] + 80025a8: 222d movs r2, #45 ; 0x2d + 80025aa: 2100 movs r1, #0 + 80025ac: 5499 strb r1, [r3, r2] + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hlptim->MspInitCallback(hlptim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_LPTIM_MspInit(hlptim); + 80025ae: 687b ldr r3, [r7, #4] + 80025b0: 0018 movs r0, r3 + 80025b2: f7fe fe1f bl 80011f4 +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + 80025b6: 687b ldr r3, [r7, #4] + 80025b8: 222e movs r2, #46 ; 0x2e + 80025ba: 2102 movs r1, #2 + 80025bc: 5499 strb r1, [r3, r2] + + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + 80025be: 687b ldr r3, [r7, #4] + 80025c0: 681b ldr r3, [r3, #0] + 80025c2: 68db ldr r3, [r3, #12] + 80025c4: 60fb str r3, [r7, #12] + + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + 80025c6: 687b ldr r3, [r7, #4] + 80025c8: 685b ldr r3, [r3, #4] + 80025ca: 2b01 cmp r3, #1 + 80025cc: d005 beq.n 80025da + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + 80025ce: 687b ldr r3, [r7, #4] + 80025d0: 6a9a ldr r2, [r3, #40] ; 0x28 + 80025d2: 2380 movs r3, #128 ; 0x80 + 80025d4: 041b lsls r3, r3, #16 + 80025d6: 429a cmp r2, r3 + 80025d8: d103 bne.n 80025e2 + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + 80025da: 68fb ldr r3, [r7, #12] + 80025dc: 221e movs r2, #30 + 80025de: 4393 bics r3, r2 + 80025e0: 60fb str r3, [r7, #12] + } + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + 80025e2: 687b ldr r3, [r7, #4] + 80025e4: 695b ldr r3, [r3, #20] + 80025e6: 4a2b ldr r2, [pc, #172] ; (8002694 ) + 80025e8: 4293 cmp r3, r2 + 80025ea: d003 beq.n 80025f4 + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + 80025ec: 68fb ldr r3, [r7, #12] + 80025ee: 4a2a ldr r2, [pc, #168] ; (8002698 ) + 80025f0: 4013 ands r3, r2 + 80025f2: 60fb str r3, [r7, #12] + } + + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + 80025f4: 68fb ldr r3, [r7, #12] + 80025f6: 4a29 ldr r2, [pc, #164] ; (800269c ) + 80025f8: 4013 ands r3, r2 + 80025fa: 60fb str r3, [r7, #12] + LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); + + /* Set initialization parameters */ + tmpcfgr |= (hlptim->Init.Clock.Source | + 80025fc: 687b ldr r3, [r7, #4] + 80025fe: 685a ldr r2, [r3, #4] + hlptim->Init.Clock.Prescaler | + 8002600: 687b ldr r3, [r7, #4] + 8002602: 689b ldr r3, [r3, #8] + tmpcfgr |= (hlptim->Init.Clock.Source | + 8002604: 431a orrs r2, r3 + hlptim->Init.OutputPolarity | + 8002606: 687b ldr r3, [r7, #4] + 8002608: 6a1b ldr r3, [r3, #32] + hlptim->Init.Clock.Prescaler | + 800260a: 431a orrs r2, r3 + hlptim->Init.UpdateMode | + 800260c: 687b ldr r3, [r7, #4] + 800260e: 6a5b ldr r3, [r3, #36] ; 0x24 + hlptim->Init.OutputPolarity | + 8002610: 431a orrs r2, r3 + hlptim->Init.CounterSource); + 8002612: 687b ldr r3, [r7, #4] + 8002614: 6a9b ldr r3, [r3, #40] ; 0x28 + hlptim->Init.UpdateMode | + 8002616: 4313 orrs r3, r2 + tmpcfgr |= (hlptim->Init.Clock.Source | + 8002618: 68fa ldr r2, [r7, #12] + 800261a: 4313 orrs r3, r2 + 800261c: 60fb str r3, [r7, #12] + + /* Glitch filters for internal triggers and external inputs are configured + * only if an internal clock source is provided to the LPTIM + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + 800261e: 687b ldr r3, [r7, #4] + 8002620: 685b ldr r3, [r3, #4] + 8002622: 2b00 cmp r3, #0 + 8002624: d107 bne.n 8002636 + { + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | + 8002626: 687b ldr r3, [r7, #4] + 8002628: 69da ldr r2, [r3, #28] + hlptim->Init.UltraLowPowerClock.SampleTime); + 800262a: 687b ldr r3, [r7, #4] + 800262c: 691b ldr r3, [r3, #16] + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | + 800262e: 4313 orrs r3, r2 + 8002630: 68fa ldr r2, [r7, #12] + 8002632: 4313 orrs r3, r2 + 8002634: 60fb str r3, [r7, #12] + } + + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + 8002636: 687b ldr r3, [r7, #4] + 8002638: 685b ldr r3, [r3, #4] + 800263a: 2b01 cmp r3, #1 + 800263c: d005 beq.n 800264a + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + 800263e: 687b ldr r3, [r7, #4] + 8002640: 6a9a ldr r2, [r3, #40] ; 0x28 + 8002642: 2380 movs r3, #128 ; 0x80 + 8002644: 041b lsls r3, r3, #16 + 8002646: 429a cmp r2, r3 + 8002648: d107 bne.n 800265a + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + 800264a: 687b ldr r3, [r7, #4] + 800264c: 68da ldr r2, [r3, #12] + hlptim->Init.UltraLowPowerClock.SampleTime); + 800264e: 687b ldr r3, [r7, #4] + 8002650: 691b ldr r3, [r3, #16] + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + 8002652: 4313 orrs r3, r2 + 8002654: 68fa ldr r2, [r7, #12] + 8002656: 4313 orrs r3, r2 + 8002658: 60fb str r3, [r7, #12] + } + + /* Configure LPTIM external trigger */ + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + 800265a: 687b ldr r3, [r7, #4] + 800265c: 695b ldr r3, [r3, #20] + 800265e: 4a0d ldr r2, [pc, #52] ; (8002694 ) + 8002660: 4293 cmp r3, r2 + 8002662: d00a beq.n 800267a + { + /* Enable External trigger and set the trigger source */ + tmpcfgr |= (hlptim->Init.Trigger.Source | + 8002664: 687b ldr r3, [r7, #4] + 8002666: 695a ldr r2, [r3, #20] + hlptim->Init.Trigger.ActiveEdge | + 8002668: 687b ldr r3, [r7, #4] + 800266a: 699b ldr r3, [r3, #24] + tmpcfgr |= (hlptim->Init.Trigger.Source | + 800266c: 431a orrs r2, r3 + hlptim->Init.Trigger.SampleTime); + 800266e: 687b ldr r3, [r7, #4] + 8002670: 69db ldr r3, [r3, #28] + hlptim->Init.Trigger.ActiveEdge | + 8002672: 4313 orrs r3, r2 + tmpcfgr |= (hlptim->Init.Trigger.Source | + 8002674: 68fa ldr r2, [r7, #12] + 8002676: 4313 orrs r3, r2 + 8002678: 60fb str r3, [r7, #12] + } + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + 800267a: 687b ldr r3, [r7, #4] + 800267c: 681b ldr r3, [r3, #0] + 800267e: 68fa ldr r2, [r7, #12] + 8002680: 60da str r2, [r3, #12] + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + 8002682: 687b ldr r3, [r7, #4] + 8002684: 222e movs r2, #46 ; 0x2e + 8002686: 2101 movs r1, #1 + 8002688: 5499 strb r1, [r3, r2] + + /* Return function status */ + return HAL_OK; + 800268a: 2300 movs r3, #0 +} + 800268c: 0018 movs r0, r3 + 800268e: 46bd mov sp, r7 + 8002690: b004 add sp, #16 + 8002692: bd80 pop {r7, pc} + 8002694: 0000ffff .word 0x0000ffff + 8002698: ffff1f3f .word 0xffff1f3f + 800269c: ff19f1fe .word 0xff19f1fe + +080026a0 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 80026a0: b5b0 push {r4, r5, r7, lr} + 80026a2: b08a sub sp, #40 ; 0x28 + 80026a4: af00 add r7, sp, #0 + 80026a6: 6078 str r0, [r7, #4] + uint32_t hsi_state; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 80026a8: 687b ldr r3, [r7, #4] + 80026aa: 2b00 cmp r3, #0 + 80026ac: d102 bne.n 80026b4 + { + return HAL_ERROR; + 80026ae: 2301 movs r3, #1 + 80026b0: f000 fb6c bl 8002d8c + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80026b4: 4bc8 ldr r3, [pc, #800] ; (80029d8 ) + 80026b6: 68db ldr r3, [r3, #12] + 80026b8: 220c movs r2, #12 + 80026ba: 4013 ands r3, r2 + 80026bc: 61fb str r3, [r7, #28] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80026be: 4bc6 ldr r3, [pc, #792] ; (80029d8 ) + 80026c0: 68da ldr r2, [r3, #12] + 80026c2: 2380 movs r3, #128 ; 0x80 + 80026c4: 025b lsls r3, r3, #9 + 80026c6: 4013 ands r3, r2 + 80026c8: 61bb str r3, [r7, #24] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80026ca: 687b ldr r3, [r7, #4] + 80026cc: 681b ldr r3, [r3, #0] + 80026ce: 2201 movs r2, #1 + 80026d0: 4013 ands r3, r2 + 80026d2: d100 bne.n 80026d6 + 80026d4: e07d b.n 80027d2 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 80026d6: 69fb ldr r3, [r7, #28] + 80026d8: 2b08 cmp r3, #8 + 80026da: d007 beq.n 80026ec + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 80026dc: 69fb ldr r3, [r7, #28] + 80026de: 2b0c cmp r3, #12 + 80026e0: d112 bne.n 8002708 + 80026e2: 69ba ldr r2, [r7, #24] + 80026e4: 2380 movs r3, #128 ; 0x80 + 80026e6: 025b lsls r3, r3, #9 + 80026e8: 429a cmp r2, r3 + 80026ea: d10d bne.n 8002708 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80026ec: 4bba ldr r3, [pc, #744] ; (80029d8 ) + 80026ee: 681a ldr r2, [r3, #0] + 80026f0: 2380 movs r3, #128 ; 0x80 + 80026f2: 029b lsls r3, r3, #10 + 80026f4: 4013 ands r3, r2 + 80026f6: d100 bne.n 80026fa + 80026f8: e06a b.n 80027d0 + 80026fa: 687b ldr r3, [r7, #4] + 80026fc: 685b ldr r3, [r3, #4] + 80026fe: 2b00 cmp r3, #0 + 8002700: d166 bne.n 80027d0 + { + return HAL_ERROR; + 8002702: 2301 movs r3, #1 + 8002704: f000 fb42 bl 8002d8c + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8002708: 687b ldr r3, [r7, #4] + 800270a: 685a ldr r2, [r3, #4] + 800270c: 2380 movs r3, #128 ; 0x80 + 800270e: 025b lsls r3, r3, #9 + 8002710: 429a cmp r2, r3 + 8002712: d107 bne.n 8002724 + 8002714: 4bb0 ldr r3, [pc, #704] ; (80029d8 ) + 8002716: 681a ldr r2, [r3, #0] + 8002718: 4baf ldr r3, [pc, #700] ; (80029d8 ) + 800271a: 2180 movs r1, #128 ; 0x80 + 800271c: 0249 lsls r1, r1, #9 + 800271e: 430a orrs r2, r1 + 8002720: 601a str r2, [r3, #0] + 8002722: e027 b.n 8002774 + 8002724: 687b ldr r3, [r7, #4] + 8002726: 685a ldr r2, [r3, #4] + 8002728: 23a0 movs r3, #160 ; 0xa0 + 800272a: 02db lsls r3, r3, #11 + 800272c: 429a cmp r2, r3 + 800272e: d10e bne.n 800274e + 8002730: 4ba9 ldr r3, [pc, #676] ; (80029d8 ) + 8002732: 681a ldr r2, [r3, #0] + 8002734: 4ba8 ldr r3, [pc, #672] ; (80029d8 ) + 8002736: 2180 movs r1, #128 ; 0x80 + 8002738: 02c9 lsls r1, r1, #11 + 800273a: 430a orrs r2, r1 + 800273c: 601a str r2, [r3, #0] + 800273e: 4ba6 ldr r3, [pc, #664] ; (80029d8 ) + 8002740: 681a ldr r2, [r3, #0] + 8002742: 4ba5 ldr r3, [pc, #660] ; (80029d8 ) + 8002744: 2180 movs r1, #128 ; 0x80 + 8002746: 0249 lsls r1, r1, #9 + 8002748: 430a orrs r2, r1 + 800274a: 601a str r2, [r3, #0] + 800274c: e012 b.n 8002774 + 800274e: 4ba2 ldr r3, [pc, #648] ; (80029d8 ) + 8002750: 681a ldr r2, [r3, #0] + 8002752: 4ba1 ldr r3, [pc, #644] ; (80029d8 ) + 8002754: 49a1 ldr r1, [pc, #644] ; (80029dc ) + 8002756: 400a ands r2, r1 + 8002758: 601a str r2, [r3, #0] + 800275a: 4b9f ldr r3, [pc, #636] ; (80029d8 ) + 800275c: 681a ldr r2, [r3, #0] + 800275e: 2380 movs r3, #128 ; 0x80 + 8002760: 025b lsls r3, r3, #9 + 8002762: 4013 ands r3, r2 + 8002764: 60fb str r3, [r7, #12] + 8002766: 68fb ldr r3, [r7, #12] + 8002768: 4b9b ldr r3, [pc, #620] ; (80029d8 ) + 800276a: 681a ldr r2, [r3, #0] + 800276c: 4b9a ldr r3, [pc, #616] ; (80029d8 ) + 800276e: 499c ldr r1, [pc, #624] ; (80029e0 ) + 8002770: 400a ands r2, r1 + 8002772: 601a str r2, [r3, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8002774: 687b ldr r3, [r7, #4] + 8002776: 685b ldr r3, [r3, #4] + 8002778: 2b00 cmp r3, #0 + 800277a: d014 beq.n 80027a6 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800277c: f7ff f80c bl 8001798 + 8002780: 0003 movs r3, r0 + 8002782: 617b str r3, [r7, #20] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8002784: e008 b.n 8002798 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8002786: f7ff f807 bl 8001798 + 800278a: 0002 movs r2, r0 + 800278c: 697b ldr r3, [r7, #20] + 800278e: 1ad3 subs r3, r2, r3 + 8002790: 2b64 cmp r3, #100 ; 0x64 + 8002792: d901 bls.n 8002798 + { + return HAL_TIMEOUT; + 8002794: 2303 movs r3, #3 + 8002796: e2f9 b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8002798: 4b8f ldr r3, [pc, #572] ; (80029d8 ) + 800279a: 681a ldr r2, [r3, #0] + 800279c: 2380 movs r3, #128 ; 0x80 + 800279e: 029b lsls r3, r3, #10 + 80027a0: 4013 ands r3, r2 + 80027a2: d0f0 beq.n 8002786 + 80027a4: e015 b.n 80027d2 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80027a6: f7fe fff7 bl 8001798 + 80027aa: 0003 movs r3, r0 + 80027ac: 617b str r3, [r7, #20] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80027ae: e008 b.n 80027c2 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80027b0: f7fe fff2 bl 8001798 + 80027b4: 0002 movs r2, r0 + 80027b6: 697b ldr r3, [r7, #20] + 80027b8: 1ad3 subs r3, r2, r3 + 80027ba: 2b64 cmp r3, #100 ; 0x64 + 80027bc: d901 bls.n 80027c2 + { + return HAL_TIMEOUT; + 80027be: 2303 movs r3, #3 + 80027c0: e2e4 b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80027c2: 4b85 ldr r3, [pc, #532] ; (80029d8 ) + 80027c4: 681a ldr r2, [r3, #0] + 80027c6: 2380 movs r3, #128 ; 0x80 + 80027c8: 029b lsls r3, r3, #10 + 80027ca: 4013 ands r3, r2 + 80027cc: d1f0 bne.n 80027b0 + 80027ce: e000 b.n 80027d2 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80027d0: 46c0 nop ; (mov r8, r8) + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80027d2: 687b ldr r3, [r7, #4] + 80027d4: 681b ldr r3, [r3, #0] + 80027d6: 2202 movs r2, #2 + 80027d8: 4013 ands r3, r2 + 80027da: d100 bne.n 80027de + 80027dc: e099 b.n 8002912 + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + hsi_state = RCC_OscInitStruct->HSIState; + 80027de: 687b ldr r3, [r7, #4] + 80027e0: 68db ldr r3, [r3, #12] + 80027e2: 627b str r3, [r7, #36] ; 0x24 + +#if defined(RCC_CR_HSIOUTEN) + if((hsi_state & RCC_HSI_OUTEN) != 0U) + 80027e4: 6a7b ldr r3, [r7, #36] ; 0x24 + 80027e6: 2220 movs r2, #32 + 80027e8: 4013 ands r3, r2 + 80027ea: d009 beq.n 8002800 + { + /* HSI Output enable for timer requested */ + SET_BIT(RCC->CR, RCC_CR_HSIOUTEN); + 80027ec: 4b7a ldr r3, [pc, #488] ; (80029d8 ) + 80027ee: 681a ldr r2, [r3, #0] + 80027f0: 4b79 ldr r3, [pc, #484] ; (80029d8 ) + 80027f2: 2120 movs r1, #32 + 80027f4: 430a orrs r2, r1 + 80027f6: 601a str r2, [r3, #0] + + hsi_state &= ~RCC_CR_HSIOUTEN; + 80027f8: 6a7b ldr r3, [r7, #36] ; 0x24 + 80027fa: 2220 movs r2, #32 + 80027fc: 4393 bics r3, r2 + 80027fe: 627b str r3, [r7, #36] ; 0x24 + } +#endif + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 8002800: 69fb ldr r3, [r7, #28] + 8002802: 2b04 cmp r3, #4 + 8002804: d005 beq.n 8002812 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8002806: 69fb ldr r3, [r7, #28] + 8002808: 2b0c cmp r3, #12 + 800280a: d13e bne.n 800288a + 800280c: 69bb ldr r3, [r7, #24] + 800280e: 2b00 cmp r3, #0 + 8002810: d13b bne.n 800288a + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (hsi_state == RCC_HSI_OFF)) + 8002812: 4b71 ldr r3, [pc, #452] ; (80029d8 ) + 8002814: 681b ldr r3, [r3, #0] + 8002816: 2204 movs r2, #4 + 8002818: 4013 ands r3, r2 + 800281a: d004 beq.n 8002826 + 800281c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800281e: 2b00 cmp r3, #0 + 8002820: d101 bne.n 8002826 + { + return HAL_ERROR; + 8002822: 2301 movs r3, #1 + 8002824: e2b2 b.n 8002d8c + } + /* Otherwise, just the calibration and HSI or HSIdiv4 are allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8002826: 4b6c ldr r3, [pc, #432] ; (80029d8 ) + 8002828: 685b ldr r3, [r3, #4] + 800282a: 4a6e ldr r2, [pc, #440] ; (80029e4 ) + 800282c: 4013 ands r3, r2 + 800282e: 0019 movs r1, r3 + 8002830: 687b ldr r3, [r7, #4] + 8002832: 691b ldr r3, [r3, #16] + 8002834: 021a lsls r2, r3, #8 + 8002836: 4b68 ldr r3, [pc, #416] ; (80029d8 ) + 8002838: 430a orrs r2, r1 + 800283a: 605a str r2, [r3, #4] + + /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */ + __HAL_RCC_HSI_CONFIG(hsi_state); + 800283c: 4b66 ldr r3, [pc, #408] ; (80029d8 ) + 800283e: 681b ldr r3, [r3, #0] + 8002840: 2209 movs r2, #9 + 8002842: 4393 bics r3, r2 + 8002844: 0019 movs r1, r3 + 8002846: 4b64 ldr r3, [pc, #400] ; (80029d8 ) + 8002848: 6a7a ldr r2, [r7, #36] ; 0x24 + 800284a: 430a orrs r2, r1 + 800284c: 601a str r2, [r3, #0] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 800284e: f000 fbeb bl 8003028 + 8002852: 0001 movs r1, r0 + 8002854: 4b60 ldr r3, [pc, #384] ; (80029d8 ) + 8002856: 68db ldr r3, [r3, #12] + 8002858: 091b lsrs r3, r3, #4 + 800285a: 220f movs r2, #15 + 800285c: 4013 ands r3, r2 + 800285e: 4a62 ldr r2, [pc, #392] ; (80029e8 ) + 8002860: 5cd3 ldrb r3, [r2, r3] + 8002862: 000a movs r2, r1 + 8002864: 40da lsrs r2, r3 + 8002866: 4b61 ldr r3, [pc, #388] ; (80029ec ) + 8002868: 601a str r2, [r3, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick (uwTickPrio); + 800286a: 4b61 ldr r3, [pc, #388] ; (80029f0 ) + 800286c: 681b ldr r3, [r3, #0] + 800286e: 2513 movs r5, #19 + 8002870: 197c adds r4, r7, r5 + 8002872: 0018 movs r0, r3 + 8002874: f7fe ff4a bl 800170c + 8002878: 0003 movs r3, r0 + 800287a: 7023 strb r3, [r4, #0] + if(status != HAL_OK) + 800287c: 197b adds r3, r7, r5 + 800287e: 781b ldrb r3, [r3, #0] + 8002880: 2b00 cmp r3, #0 + 8002882: d046 beq.n 8002912 + { + return status; + 8002884: 197b adds r3, r7, r5 + 8002886: 781b ldrb r3, [r3, #0] + 8002888: e280 b.n 8002d8c + } + } + else + { + /* Check the HSI State */ + if(hsi_state != RCC_HSI_OFF) + 800288a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800288c: 2b00 cmp r3, #0 + 800288e: d027 beq.n 80028e0 + { + /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */ + __HAL_RCC_HSI_CONFIG(hsi_state); + 8002890: 4b51 ldr r3, [pc, #324] ; (80029d8 ) + 8002892: 681b ldr r3, [r3, #0] + 8002894: 2209 movs r2, #9 + 8002896: 4393 bics r3, r2 + 8002898: 0019 movs r1, r3 + 800289a: 4b4f ldr r3, [pc, #316] ; (80029d8 ) + 800289c: 6a7a ldr r2, [r7, #36] ; 0x24 + 800289e: 430a orrs r2, r1 + 80028a0: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80028a2: f7fe ff79 bl 8001798 + 80028a6: 0003 movs r3, r0 + 80028a8: 617b str r3, [r7, #20] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80028aa: e008 b.n 80028be + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80028ac: f7fe ff74 bl 8001798 + 80028b0: 0002 movs r2, r0 + 80028b2: 697b ldr r3, [r7, #20] + 80028b4: 1ad3 subs r3, r2, r3 + 80028b6: 2b02 cmp r3, #2 + 80028b8: d901 bls.n 80028be + { + return HAL_TIMEOUT; + 80028ba: 2303 movs r3, #3 + 80028bc: e266 b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80028be: 4b46 ldr r3, [pc, #280] ; (80029d8 ) + 80028c0: 681b ldr r3, [r3, #0] + 80028c2: 2204 movs r2, #4 + 80028c4: 4013 ands r3, r2 + 80028c6: d0f1 beq.n 80028ac + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80028c8: 4b43 ldr r3, [pc, #268] ; (80029d8 ) + 80028ca: 685b ldr r3, [r3, #4] + 80028cc: 4a45 ldr r2, [pc, #276] ; (80029e4 ) + 80028ce: 4013 ands r3, r2 + 80028d0: 0019 movs r1, r3 + 80028d2: 687b ldr r3, [r7, #4] + 80028d4: 691b ldr r3, [r3, #16] + 80028d6: 021a lsls r2, r3, #8 + 80028d8: 4b3f ldr r3, [pc, #252] ; (80029d8 ) + 80028da: 430a orrs r2, r1 + 80028dc: 605a str r2, [r3, #4] + 80028de: e018 b.n 8002912 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80028e0: 4b3d ldr r3, [pc, #244] ; (80029d8 ) + 80028e2: 681a ldr r2, [r3, #0] + 80028e4: 4b3c ldr r3, [pc, #240] ; (80029d8 ) + 80028e6: 2101 movs r1, #1 + 80028e8: 438a bics r2, r1 + 80028ea: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80028ec: f7fe ff54 bl 8001798 + 80028f0: 0003 movs r3, r0 + 80028f2: 617b str r3, [r7, #20] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 80028f4: e008 b.n 8002908 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80028f6: f7fe ff4f bl 8001798 + 80028fa: 0002 movs r2, r0 + 80028fc: 697b ldr r3, [r7, #20] + 80028fe: 1ad3 subs r3, r2, r3 + 8002900: 2b02 cmp r3, #2 + 8002902: d901 bls.n 8002908 + { + return HAL_TIMEOUT; + 8002904: 2303 movs r3, #3 + 8002906: e241 b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8002908: 4b33 ldr r3, [pc, #204] ; (80029d8 ) + 800290a: 681b ldr r3, [r3, #0] + 800290c: 2204 movs r2, #4 + 800290e: 4013 ands r3, r2 + 8002910: d1f1 bne.n 80028f6 + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8002912: 687b ldr r3, [r7, #4] + 8002914: 681b ldr r3, [r3, #0] + 8002916: 2210 movs r2, #16 + 8002918: 4013 ands r3, r2 + 800291a: d100 bne.n 800291e + 800291c: e0a1 b.n 8002a62 + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 800291e: 69fb ldr r3, [r7, #28] + 8002920: 2b00 cmp r3, #0 + 8002922: d140 bne.n 80029a6 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 8002924: 4b2c ldr r3, [pc, #176] ; (80029d8 ) + 8002926: 681a ldr r2, [r3, #0] + 8002928: 2380 movs r3, #128 ; 0x80 + 800292a: 009b lsls r3, r3, #2 + 800292c: 4013 ands r3, r2 + 800292e: d005 beq.n 800293c + 8002930: 687b ldr r3, [r7, #4] + 8002932: 699b ldr r3, [r3, #24] + 8002934: 2b00 cmp r3, #0 + 8002936: d101 bne.n 800293c + { + return HAL_ERROR; + 8002938: 2301 movs r3, #1 + 800293a: e227 b.n 8002d8c + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800293c: 4b26 ldr r3, [pc, #152] ; (80029d8 ) + 800293e: 685b ldr r3, [r3, #4] + 8002940: 4a2c ldr r2, [pc, #176] ; (80029f4 ) + 8002942: 4013 ands r3, r2 + 8002944: 0019 movs r1, r3 + 8002946: 687b ldr r3, [r7, #4] + 8002948: 6a1a ldr r2, [r3, #32] + 800294a: 4b23 ldr r3, [pc, #140] ; (80029d8 ) + 800294c: 430a orrs r2, r1 + 800294e: 605a str r2, [r3, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002950: 4b21 ldr r3, [pc, #132] ; (80029d8 ) + 8002952: 685b ldr r3, [r3, #4] + 8002954: 021b lsls r3, r3, #8 + 8002956: 0a19 lsrs r1, r3, #8 + 8002958: 687b ldr r3, [r7, #4] + 800295a: 69db ldr r3, [r3, #28] + 800295c: 061a lsls r2, r3, #24 + 800295e: 4b1e ldr r3, [pc, #120] ; (80029d8 ) + 8002960: 430a orrs r2, r1 + 8002962: 605a str r2, [r3, #4] + + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8002964: 687b ldr r3, [r7, #4] + 8002966: 6a1b ldr r3, [r3, #32] + 8002968: 0b5b lsrs r3, r3, #13 + 800296a: 3301 adds r3, #1 + 800296c: 2280 movs r2, #128 ; 0x80 + 800296e: 0212 lsls r2, r2, #8 + 8002970: 409a lsls r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 8002972: 4b19 ldr r3, [pc, #100] ; (80029d8 ) + 8002974: 68db ldr r3, [r3, #12] + 8002976: 091b lsrs r3, r3, #4 + 8002978: 210f movs r1, #15 + 800297a: 400b ands r3, r1 + 800297c: 491a ldr r1, [pc, #104] ; (80029e8 ) + 800297e: 5ccb ldrb r3, [r1, r3] + 8002980: 40da lsrs r2, r3 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8002982: 4b1a ldr r3, [pc, #104] ; (80029ec ) + 8002984: 601a str r2, [r3, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick (uwTickPrio); + 8002986: 4b1a ldr r3, [pc, #104] ; (80029f0 ) + 8002988: 681b ldr r3, [r3, #0] + 800298a: 2513 movs r5, #19 + 800298c: 197c adds r4, r7, r5 + 800298e: 0018 movs r0, r3 + 8002990: f7fe febc bl 800170c + 8002994: 0003 movs r3, r0 + 8002996: 7023 strb r3, [r4, #0] + if(status != HAL_OK) + 8002998: 197b adds r3, r7, r5 + 800299a: 781b ldrb r3, [r3, #0] + 800299c: 2b00 cmp r3, #0 + 800299e: d060 beq.n 8002a62 + { + return status; + 80029a0: 197b adds r3, r7, r5 + 80029a2: 781b ldrb r3, [r3, #0] + 80029a4: e1f2 b.n 8002d8c + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 80029a6: 687b ldr r3, [r7, #4] + 80029a8: 699b ldr r3, [r3, #24] + 80029aa: 2b00 cmp r3, #0 + 80029ac: d03f beq.n 8002a2e + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 80029ae: 4b0a ldr r3, [pc, #40] ; (80029d8 ) + 80029b0: 681a ldr r2, [r3, #0] + 80029b2: 4b09 ldr r3, [pc, #36] ; (80029d8 ) + 80029b4: 2180 movs r1, #128 ; 0x80 + 80029b6: 0049 lsls r1, r1, #1 + 80029b8: 430a orrs r2, r1 + 80029ba: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80029bc: f7fe feec bl 8001798 + 80029c0: 0003 movs r3, r0 + 80029c2: 617b str r3, [r7, #20] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80029c4: e018 b.n 80029f8 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80029c6: f7fe fee7 bl 8001798 + 80029ca: 0002 movs r2, r0 + 80029cc: 697b ldr r3, [r7, #20] + 80029ce: 1ad3 subs r3, r2, r3 + 80029d0: 2b02 cmp r3, #2 + 80029d2: d911 bls.n 80029f8 + { + return HAL_TIMEOUT; + 80029d4: 2303 movs r3, #3 + 80029d6: e1d9 b.n 8002d8c + 80029d8: 40021000 .word 0x40021000 + 80029dc: fffeffff .word 0xfffeffff + 80029e0: fffbffff .word 0xfffbffff + 80029e4: ffffe0ff .word 0xffffe0ff + 80029e8: 08007884 .word 0x08007884 + 80029ec: 20000000 .word 0x20000000 + 80029f0: 20000004 .word 0x20000004 + 80029f4: ffff1fff .word 0xffff1fff + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80029f8: 4bc9 ldr r3, [pc, #804] ; (8002d20 ) + 80029fa: 681a ldr r2, [r3, #0] + 80029fc: 2380 movs r3, #128 ; 0x80 + 80029fe: 009b lsls r3, r3, #2 + 8002a00: 4013 ands r3, r2 + 8002a02: d0e0 beq.n 80029c6 + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002a04: 4bc6 ldr r3, [pc, #792] ; (8002d20 ) + 8002a06: 685b ldr r3, [r3, #4] + 8002a08: 4ac6 ldr r2, [pc, #792] ; (8002d24 ) + 8002a0a: 4013 ands r3, r2 + 8002a0c: 0019 movs r1, r3 + 8002a0e: 687b ldr r3, [r7, #4] + 8002a10: 6a1a ldr r2, [r3, #32] + 8002a12: 4bc3 ldr r3, [pc, #780] ; (8002d20 ) + 8002a14: 430a orrs r2, r1 + 8002a16: 605a str r2, [r3, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002a18: 4bc1 ldr r3, [pc, #772] ; (8002d20 ) + 8002a1a: 685b ldr r3, [r3, #4] + 8002a1c: 021b lsls r3, r3, #8 + 8002a1e: 0a19 lsrs r1, r3, #8 + 8002a20: 687b ldr r3, [r7, #4] + 8002a22: 69db ldr r3, [r3, #28] + 8002a24: 061a lsls r2, r3, #24 + 8002a26: 4bbe ldr r3, [pc, #760] ; (8002d20 ) + 8002a28: 430a orrs r2, r1 + 8002a2a: 605a str r2, [r3, #4] + 8002a2c: e019 b.n 8002a62 + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 8002a2e: 4bbc ldr r3, [pc, #752] ; (8002d20 ) + 8002a30: 681a ldr r2, [r3, #0] + 8002a32: 4bbb ldr r3, [pc, #748] ; (8002d20 ) + 8002a34: 49bc ldr r1, [pc, #752] ; (8002d28 ) + 8002a36: 400a ands r2, r1 + 8002a38: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002a3a: f7fe fead bl 8001798 + 8002a3e: 0003 movs r3, r0 + 8002a40: 617b str r3, [r7, #20] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 8002a42: e008 b.n 8002a56 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8002a44: f7fe fea8 bl 8001798 + 8002a48: 0002 movs r2, r0 + 8002a4a: 697b ldr r3, [r7, #20] + 8002a4c: 1ad3 subs r3, r2, r3 + 8002a4e: 2b02 cmp r3, #2 + 8002a50: d901 bls.n 8002a56 + { + return HAL_TIMEOUT; + 8002a52: 2303 movs r3, #3 + 8002a54: e19a b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 8002a56: 4bb2 ldr r3, [pc, #712] ; (8002d20 ) + 8002a58: 681a ldr r2, [r3, #0] + 8002a5a: 2380 movs r3, #128 ; 0x80 + 8002a5c: 009b lsls r3, r3, #2 + 8002a5e: 4013 ands r3, r2 + 8002a60: d1f0 bne.n 8002a44 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8002a62: 687b ldr r3, [r7, #4] + 8002a64: 681b ldr r3, [r3, #0] + 8002a66: 2208 movs r2, #8 + 8002a68: 4013 ands r3, r2 + 8002a6a: d036 beq.n 8002ada + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8002a6c: 687b ldr r3, [r7, #4] + 8002a6e: 695b ldr r3, [r3, #20] + 8002a70: 2b00 cmp r3, #0 + 8002a72: d019 beq.n 8002aa8 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8002a74: 4baa ldr r3, [pc, #680] ; (8002d20 ) + 8002a76: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002a78: 4ba9 ldr r3, [pc, #676] ; (8002d20 ) + 8002a7a: 2101 movs r1, #1 + 8002a7c: 430a orrs r2, r1 + 8002a7e: 651a str r2, [r3, #80] ; 0x50 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002a80: f7fe fe8a bl 8001798 + 8002a84: 0003 movs r3, r0 + 8002a86: 617b str r3, [r7, #20] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8002a88: e008 b.n 8002a9c + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8002a8a: f7fe fe85 bl 8001798 + 8002a8e: 0002 movs r2, r0 + 8002a90: 697b ldr r3, [r7, #20] + 8002a92: 1ad3 subs r3, r2, r3 + 8002a94: 2b02 cmp r3, #2 + 8002a96: d901 bls.n 8002a9c + { + return HAL_TIMEOUT; + 8002a98: 2303 movs r3, #3 + 8002a9a: e177 b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8002a9c: 4ba0 ldr r3, [pc, #640] ; (8002d20 ) + 8002a9e: 6d1b ldr r3, [r3, #80] ; 0x50 + 8002aa0: 2202 movs r2, #2 + 8002aa2: 4013 ands r3, r2 + 8002aa4: d0f1 beq.n 8002a8a + 8002aa6: e018 b.n 8002ada + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8002aa8: 4b9d ldr r3, [pc, #628] ; (8002d20 ) + 8002aaa: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002aac: 4b9c ldr r3, [pc, #624] ; (8002d20 ) + 8002aae: 2101 movs r1, #1 + 8002ab0: 438a bics r2, r1 + 8002ab2: 651a str r2, [r3, #80] ; 0x50 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002ab4: f7fe fe70 bl 8001798 + 8002ab8: 0003 movs r3, r0 + 8002aba: 617b str r3, [r7, #20] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8002abc: e008 b.n 8002ad0 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8002abe: f7fe fe6b bl 8001798 + 8002ac2: 0002 movs r2, r0 + 8002ac4: 697b ldr r3, [r7, #20] + 8002ac6: 1ad3 subs r3, r2, r3 + 8002ac8: 2b02 cmp r3, #2 + 8002aca: d901 bls.n 8002ad0 + { + return HAL_TIMEOUT; + 8002acc: 2303 movs r3, #3 + 8002ace: e15d b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8002ad0: 4b93 ldr r3, [pc, #588] ; (8002d20 ) + 8002ad2: 6d1b ldr r3, [r3, #80] ; 0x50 + 8002ad4: 2202 movs r2, #2 + 8002ad6: 4013 ands r3, r2 + 8002ad8: d1f1 bne.n 8002abe + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8002ada: 687b ldr r3, [r7, #4] + 8002adc: 681b ldr r3, [r3, #0] + 8002ade: 2204 movs r2, #4 + 8002ae0: 4013 ands r3, r2 + 8002ae2: d100 bne.n 8002ae6 + 8002ae4: e0ae b.n 8002c44 + { + FlagStatus pwrclkchanged = RESET; + 8002ae6: 2023 movs r0, #35 ; 0x23 + 8002ae8: 183b adds r3, r7, r0 + 8002aea: 2200 movs r2, #0 + 8002aec: 701a strb r2, [r3, #0] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8002aee: 4b8c ldr r3, [pc, #560] ; (8002d20 ) + 8002af0: 6b9a ldr r2, [r3, #56] ; 0x38 + 8002af2: 2380 movs r3, #128 ; 0x80 + 8002af4: 055b lsls r3, r3, #21 + 8002af6: 4013 ands r3, r2 + 8002af8: d109 bne.n 8002b0e + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8002afa: 4b89 ldr r3, [pc, #548] ; (8002d20 ) + 8002afc: 6b9a ldr r2, [r3, #56] ; 0x38 + 8002afe: 4b88 ldr r3, [pc, #544] ; (8002d20 ) + 8002b00: 2180 movs r1, #128 ; 0x80 + 8002b02: 0549 lsls r1, r1, #21 + 8002b04: 430a orrs r2, r1 + 8002b06: 639a str r2, [r3, #56] ; 0x38 + pwrclkchanged = SET; + 8002b08: 183b adds r3, r7, r0 + 8002b0a: 2201 movs r2, #1 + 8002b0c: 701a strb r2, [r3, #0] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002b0e: 4b87 ldr r3, [pc, #540] ; (8002d2c ) + 8002b10: 681a ldr r2, [r3, #0] + 8002b12: 2380 movs r3, #128 ; 0x80 + 8002b14: 005b lsls r3, r3, #1 + 8002b16: 4013 ands r3, r2 + 8002b18: d11a bne.n 8002b50 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8002b1a: 4b84 ldr r3, [pc, #528] ; (8002d2c ) + 8002b1c: 681a ldr r2, [r3, #0] + 8002b1e: 4b83 ldr r3, [pc, #524] ; (8002d2c ) + 8002b20: 2180 movs r1, #128 ; 0x80 + 8002b22: 0049 lsls r1, r1, #1 + 8002b24: 430a orrs r2, r1 + 8002b26: 601a str r2, [r3, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8002b28: f7fe fe36 bl 8001798 + 8002b2c: 0003 movs r3, r0 + 8002b2e: 617b str r3, [r7, #20] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002b30: e008 b.n 8002b44 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8002b32: f7fe fe31 bl 8001798 + 8002b36: 0002 movs r2, r0 + 8002b38: 697b ldr r3, [r7, #20] + 8002b3a: 1ad3 subs r3, r2, r3 + 8002b3c: 2b64 cmp r3, #100 ; 0x64 + 8002b3e: d901 bls.n 8002b44 + { + return HAL_TIMEOUT; + 8002b40: 2303 movs r3, #3 + 8002b42: e123 b.n 8002d8c + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002b44: 4b79 ldr r3, [pc, #484] ; (8002d2c ) + 8002b46: 681a ldr r2, [r3, #0] + 8002b48: 2380 movs r3, #128 ; 0x80 + 8002b4a: 005b lsls r3, r3, #1 + 8002b4c: 4013 ands r3, r2 + 8002b4e: d0f0 beq.n 8002b32 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8002b50: 687b ldr r3, [r7, #4] + 8002b52: 689a ldr r2, [r3, #8] + 8002b54: 2380 movs r3, #128 ; 0x80 + 8002b56: 005b lsls r3, r3, #1 + 8002b58: 429a cmp r2, r3 + 8002b5a: d107 bne.n 8002b6c + 8002b5c: 4b70 ldr r3, [pc, #448] ; (8002d20 ) + 8002b5e: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002b60: 4b6f ldr r3, [pc, #444] ; (8002d20 ) + 8002b62: 2180 movs r1, #128 ; 0x80 + 8002b64: 0049 lsls r1, r1, #1 + 8002b66: 430a orrs r2, r1 + 8002b68: 651a str r2, [r3, #80] ; 0x50 + 8002b6a: e031 b.n 8002bd0 + 8002b6c: 687b ldr r3, [r7, #4] + 8002b6e: 689b ldr r3, [r3, #8] + 8002b70: 2b00 cmp r3, #0 + 8002b72: d10c bne.n 8002b8e + 8002b74: 4b6a ldr r3, [pc, #424] ; (8002d20 ) + 8002b76: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002b78: 4b69 ldr r3, [pc, #420] ; (8002d20 ) + 8002b7a: 496b ldr r1, [pc, #428] ; (8002d28 ) + 8002b7c: 400a ands r2, r1 + 8002b7e: 651a str r2, [r3, #80] ; 0x50 + 8002b80: 4b67 ldr r3, [pc, #412] ; (8002d20 ) + 8002b82: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002b84: 4b66 ldr r3, [pc, #408] ; (8002d20 ) + 8002b86: 496a ldr r1, [pc, #424] ; (8002d30 ) + 8002b88: 400a ands r2, r1 + 8002b8a: 651a str r2, [r3, #80] ; 0x50 + 8002b8c: e020 b.n 8002bd0 + 8002b8e: 687b ldr r3, [r7, #4] + 8002b90: 689a ldr r2, [r3, #8] + 8002b92: 23a0 movs r3, #160 ; 0xa0 + 8002b94: 00db lsls r3, r3, #3 + 8002b96: 429a cmp r2, r3 + 8002b98: d10e bne.n 8002bb8 + 8002b9a: 4b61 ldr r3, [pc, #388] ; (8002d20 ) + 8002b9c: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002b9e: 4b60 ldr r3, [pc, #384] ; (8002d20 ) + 8002ba0: 2180 movs r1, #128 ; 0x80 + 8002ba2: 00c9 lsls r1, r1, #3 + 8002ba4: 430a orrs r2, r1 + 8002ba6: 651a str r2, [r3, #80] ; 0x50 + 8002ba8: 4b5d ldr r3, [pc, #372] ; (8002d20 ) + 8002baa: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002bac: 4b5c ldr r3, [pc, #368] ; (8002d20 ) + 8002bae: 2180 movs r1, #128 ; 0x80 + 8002bb0: 0049 lsls r1, r1, #1 + 8002bb2: 430a orrs r2, r1 + 8002bb4: 651a str r2, [r3, #80] ; 0x50 + 8002bb6: e00b b.n 8002bd0 + 8002bb8: 4b59 ldr r3, [pc, #356] ; (8002d20 ) + 8002bba: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002bbc: 4b58 ldr r3, [pc, #352] ; (8002d20 ) + 8002bbe: 495a ldr r1, [pc, #360] ; (8002d28 ) + 8002bc0: 400a ands r2, r1 + 8002bc2: 651a str r2, [r3, #80] ; 0x50 + 8002bc4: 4b56 ldr r3, [pc, #344] ; (8002d20 ) + 8002bc6: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002bc8: 4b55 ldr r3, [pc, #340] ; (8002d20 ) + 8002bca: 4959 ldr r1, [pc, #356] ; (8002d30 ) + 8002bcc: 400a ands r2, r1 + 8002bce: 651a str r2, [r3, #80] ; 0x50 + + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8002bd0: 687b ldr r3, [r7, #4] + 8002bd2: 689b ldr r3, [r3, #8] + 8002bd4: 2b00 cmp r3, #0 + 8002bd6: d015 beq.n 8002c04 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002bd8: f7fe fdde bl 8001798 + 8002bdc: 0003 movs r3, r0 + 8002bde: 617b str r3, [r7, #20] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8002be0: e009 b.n 8002bf6 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8002be2: f7fe fdd9 bl 8001798 + 8002be6: 0002 movs r2, r0 + 8002be8: 697b ldr r3, [r7, #20] + 8002bea: 1ad3 subs r3, r2, r3 + 8002bec: 4a51 ldr r2, [pc, #324] ; (8002d34 ) + 8002bee: 4293 cmp r3, r2 + 8002bf0: d901 bls.n 8002bf6 + { + return HAL_TIMEOUT; + 8002bf2: 2303 movs r3, #3 + 8002bf4: e0ca b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8002bf6: 4b4a ldr r3, [pc, #296] ; (8002d20 ) + 8002bf8: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002bfa: 2380 movs r3, #128 ; 0x80 + 8002bfc: 009b lsls r3, r3, #2 + 8002bfe: 4013 ands r3, r2 + 8002c00: d0ef beq.n 8002be2 + 8002c02: e014 b.n 8002c2e + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002c04: f7fe fdc8 bl 8001798 + 8002c08: 0003 movs r3, r0 + 8002c0a: 617b str r3, [r7, #20] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8002c0c: e009 b.n 8002c22 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8002c0e: f7fe fdc3 bl 8001798 + 8002c12: 0002 movs r2, r0 + 8002c14: 697b ldr r3, [r7, #20] + 8002c16: 1ad3 subs r3, r2, r3 + 8002c18: 4a46 ldr r2, [pc, #280] ; (8002d34 ) + 8002c1a: 4293 cmp r3, r2 + 8002c1c: d901 bls.n 8002c22 + { + return HAL_TIMEOUT; + 8002c1e: 2303 movs r3, #3 + 8002c20: e0b4 b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8002c22: 4b3f ldr r3, [pc, #252] ; (8002d20 ) + 8002c24: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002c26: 2380 movs r3, #128 ; 0x80 + 8002c28: 009b lsls r3, r3, #2 + 8002c2a: 4013 ands r3, r2 + 8002c2c: d1ef bne.n 8002c0e + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 8002c2e: 2323 movs r3, #35 ; 0x23 + 8002c30: 18fb adds r3, r7, r3 + 8002c32: 781b ldrb r3, [r3, #0] + 8002c34: 2b01 cmp r3, #1 + 8002c36: d105 bne.n 8002c44 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8002c38: 4b39 ldr r3, [pc, #228] ; (8002d20 ) + 8002c3a: 6b9a ldr r2, [r3, #56] ; 0x38 + 8002c3c: 4b38 ldr r3, [pc, #224] ; (8002d20 ) + 8002c3e: 493e ldr r1, [pc, #248] ; (8002d38 ) + 8002c40: 400a ands r2, r1 + 8002c42: 639a str r2, [r3, #56] ; 0x38 +#endif /* RCC_HSI48_SUPPORT */ + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8002c44: 687b ldr r3, [r7, #4] + 8002c46: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002c48: 2b00 cmp r3, #0 + 8002c4a: d100 bne.n 8002c4e + 8002c4c: e09d b.n 8002d8a + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8002c4e: 69fb ldr r3, [r7, #28] + 8002c50: 2b0c cmp r3, #12 + 8002c52: d100 bne.n 8002c56 + 8002c54: e076 b.n 8002d44 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8002c56: 687b ldr r3, [r7, #4] + 8002c58: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002c5a: 2b02 cmp r3, #2 + 8002c5c: d145 bne.n 8002cea + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002c5e: 4b30 ldr r3, [pc, #192] ; (8002d20 ) + 8002c60: 681a ldr r2, [r3, #0] + 8002c62: 4b2f ldr r3, [pc, #188] ; (8002d20 ) + 8002c64: 4935 ldr r1, [pc, #212] ; (8002d3c ) + 8002c66: 400a ands r2, r1 + 8002c68: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002c6a: f7fe fd95 bl 8001798 + 8002c6e: 0003 movs r3, r0 + 8002c70: 617b str r3, [r7, #20] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8002c72: e008 b.n 8002c86 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8002c74: f7fe fd90 bl 8001798 + 8002c78: 0002 movs r2, r0 + 8002c7a: 697b ldr r3, [r7, #20] + 8002c7c: 1ad3 subs r3, r2, r3 + 8002c7e: 2b02 cmp r3, #2 + 8002c80: d901 bls.n 8002c86 + { + return HAL_TIMEOUT; + 8002c82: 2303 movs r3, #3 + 8002c84: e082 b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8002c86: 4b26 ldr r3, [pc, #152] ; (8002d20 ) + 8002c88: 681a ldr r2, [r3, #0] + 8002c8a: 2380 movs r3, #128 ; 0x80 + 8002c8c: 049b lsls r3, r3, #18 + 8002c8e: 4013 ands r3, r2 + 8002c90: d1f0 bne.n 8002c74 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8002c92: 4b23 ldr r3, [pc, #140] ; (8002d20 ) + 8002c94: 68db ldr r3, [r3, #12] + 8002c96: 4a2a ldr r2, [pc, #168] ; (8002d40 ) + 8002c98: 4013 ands r3, r2 + 8002c9a: 0019 movs r1, r3 + 8002c9c: 687b ldr r3, [r7, #4] + 8002c9e: 6a9a ldr r2, [r3, #40] ; 0x28 + 8002ca0: 687b ldr r3, [r7, #4] + 8002ca2: 6adb ldr r3, [r3, #44] ; 0x2c + 8002ca4: 431a orrs r2, r3 + 8002ca6: 687b ldr r3, [r7, #4] + 8002ca8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002caa: 431a orrs r2, r3 + 8002cac: 4b1c ldr r3, [pc, #112] ; (8002d20 ) + 8002cae: 430a orrs r2, r1 + 8002cb0: 60da str r2, [r3, #12] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8002cb2: 4b1b ldr r3, [pc, #108] ; (8002d20 ) + 8002cb4: 681a ldr r2, [r3, #0] + 8002cb6: 4b1a ldr r3, [pc, #104] ; (8002d20 ) + 8002cb8: 2180 movs r1, #128 ; 0x80 + 8002cba: 0449 lsls r1, r1, #17 + 8002cbc: 430a orrs r2, r1 + 8002cbe: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002cc0: f7fe fd6a bl 8001798 + 8002cc4: 0003 movs r3, r0 + 8002cc6: 617b str r3, [r7, #20] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8002cc8: e008 b.n 8002cdc + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8002cca: f7fe fd65 bl 8001798 + 8002cce: 0002 movs r2, r0 + 8002cd0: 697b ldr r3, [r7, #20] + 8002cd2: 1ad3 subs r3, r2, r3 + 8002cd4: 2b02 cmp r3, #2 + 8002cd6: d901 bls.n 8002cdc + { + return HAL_TIMEOUT; + 8002cd8: 2303 movs r3, #3 + 8002cda: e057 b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8002cdc: 4b10 ldr r3, [pc, #64] ; (8002d20 ) + 8002cde: 681a ldr r2, [r3, #0] + 8002ce0: 2380 movs r3, #128 ; 0x80 + 8002ce2: 049b lsls r3, r3, #18 + 8002ce4: 4013 ands r3, r2 + 8002ce6: d0f0 beq.n 8002cca + 8002ce8: e04f b.n 8002d8a + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002cea: 4b0d ldr r3, [pc, #52] ; (8002d20 ) + 8002cec: 681a ldr r2, [r3, #0] + 8002cee: 4b0c ldr r3, [pc, #48] ; (8002d20 ) + 8002cf0: 4912 ldr r1, [pc, #72] ; (8002d3c ) + 8002cf2: 400a ands r2, r1 + 8002cf4: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002cf6: f7fe fd4f bl 8001798 + 8002cfa: 0003 movs r3, r0 + 8002cfc: 617b str r3, [r7, #20] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8002cfe: e008 b.n 8002d12 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8002d00: f7fe fd4a bl 8001798 + 8002d04: 0002 movs r2, r0 + 8002d06: 697b ldr r3, [r7, #20] + 8002d08: 1ad3 subs r3, r2, r3 + 8002d0a: 2b02 cmp r3, #2 + 8002d0c: d901 bls.n 8002d12 + { + return HAL_TIMEOUT; + 8002d0e: 2303 movs r3, #3 + 8002d10: e03c b.n 8002d8c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8002d12: 4b03 ldr r3, [pc, #12] ; (8002d20 ) + 8002d14: 681a ldr r2, [r3, #0] + 8002d16: 2380 movs r3, #128 ; 0x80 + 8002d18: 049b lsls r3, r3, #18 + 8002d1a: 4013 ands r3, r2 + 8002d1c: d1f0 bne.n 8002d00 + 8002d1e: e034 b.n 8002d8a + 8002d20: 40021000 .word 0x40021000 + 8002d24: ffff1fff .word 0xffff1fff + 8002d28: fffffeff .word 0xfffffeff + 8002d2c: 40007000 .word 0x40007000 + 8002d30: fffffbff .word 0xfffffbff + 8002d34: 00001388 .word 0x00001388 + 8002d38: efffffff .word 0xefffffff + 8002d3c: feffffff .word 0xfeffffff + 8002d40: ff02ffff .word 0xff02ffff + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8002d44: 687b ldr r3, [r7, #4] + 8002d46: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002d48: 2b01 cmp r3, #1 + 8002d4a: d101 bne.n 8002d50 + { + return HAL_ERROR; + 8002d4c: 2301 movs r3, #1 + 8002d4e: e01d b.n 8002d8c + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 8002d50: 4b10 ldr r3, [pc, #64] ; (8002d94 ) + 8002d52: 68db ldr r3, [r3, #12] + 8002d54: 61bb str r3, [r7, #24] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8002d56: 69ba ldr r2, [r7, #24] + 8002d58: 2380 movs r3, #128 ; 0x80 + 8002d5a: 025b lsls r3, r3, #9 + 8002d5c: 401a ands r2, r3 + 8002d5e: 687b ldr r3, [r7, #4] + 8002d60: 6a9b ldr r3, [r3, #40] ; 0x28 + 8002d62: 429a cmp r2, r3 + 8002d64: d10f bne.n 8002d86 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8002d66: 69ba ldr r2, [r7, #24] + 8002d68: 23f0 movs r3, #240 ; 0xf0 + 8002d6a: 039b lsls r3, r3, #14 + 8002d6c: 401a ands r2, r3 + 8002d6e: 687b ldr r3, [r7, #4] + 8002d70: 6adb ldr r3, [r3, #44] ; 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8002d72: 429a cmp r2, r3 + 8002d74: d107 bne.n 8002d86 + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 8002d76: 69ba ldr r2, [r7, #24] + 8002d78: 23c0 movs r3, #192 ; 0xc0 + 8002d7a: 041b lsls r3, r3, #16 + 8002d7c: 401a ands r2, r3 + 8002d7e: 687b ldr r3, [r7, #4] + 8002d80: 6b1b ldr r3, [r3, #48] ; 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8002d82: 429a cmp r2, r3 + 8002d84: d001 beq.n 8002d8a + { + return HAL_ERROR; + 8002d86: 2301 movs r3, #1 + 8002d88: e000 b.n 8002d8c + } + } + } + } + return HAL_OK; + 8002d8a: 2300 movs r3, #0 +} + 8002d8c: 0018 movs r0, r3 + 8002d8e: 46bd mov sp, r7 + 8002d90: b00a add sp, #40 ; 0x28 + 8002d92: bdb0 pop {r4, r5, r7, pc} + 8002d94: 40021000 .word 0x40021000 + +08002d98 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8002d98: b5b0 push {r4, r5, r7, lr} + 8002d9a: b084 sub sp, #16 + 8002d9c: af00 add r7, sp, #0 + 8002d9e: 6078 str r0, [r7, #4] + 8002da0: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + 8002da2: 687b ldr r3, [r7, #4] + 8002da4: 2b00 cmp r3, #0 + 8002da6: d101 bne.n 8002dac + { + return HAL_ERROR; + 8002da8: 2301 movs r3, #1 + 8002daa: e128 b.n 8002ffe + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8002dac: 4b96 ldr r3, [pc, #600] ; (8003008 ) + 8002dae: 681b ldr r3, [r3, #0] + 8002db0: 2201 movs r2, #1 + 8002db2: 4013 ands r3, r2 + 8002db4: 683a ldr r2, [r7, #0] + 8002db6: 429a cmp r2, r3 + 8002db8: d91e bls.n 8002df8 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002dba: 4b93 ldr r3, [pc, #588] ; (8003008 ) + 8002dbc: 681b ldr r3, [r3, #0] + 8002dbe: 2201 movs r2, #1 + 8002dc0: 4393 bics r3, r2 + 8002dc2: 0019 movs r1, r3 + 8002dc4: 4b90 ldr r3, [pc, #576] ; (8003008 ) + 8002dc6: 683a ldr r2, [r7, #0] + 8002dc8: 430a orrs r2, r1 + 8002dca: 601a str r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + 8002dcc: f7fe fce4 bl 8001798 + 8002dd0: 0003 movs r3, r0 + 8002dd2: 60fb str r3, [r7, #12] + + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002dd4: e009 b.n 8002dea + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002dd6: f7fe fcdf bl 8001798 + 8002dda: 0002 movs r2, r0 + 8002ddc: 68fb ldr r3, [r7, #12] + 8002dde: 1ad3 subs r3, r2, r3 + 8002de0: 4a8a ldr r2, [pc, #552] ; (800300c ) + 8002de2: 4293 cmp r3, r2 + 8002de4: d901 bls.n 8002dea + { + return HAL_TIMEOUT; + 8002de6: 2303 movs r3, #3 + 8002de8: e109 b.n 8002ffe + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002dea: 4b87 ldr r3, [pc, #540] ; (8003008 ) + 8002dec: 681b ldr r3, [r3, #0] + 8002dee: 2201 movs r2, #1 + 8002df0: 4013 ands r3, r2 + 8002df2: 683a ldr r2, [r7, #0] + 8002df4: 429a cmp r2, r3 + 8002df6: d1ee bne.n 8002dd6 + } + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8002df8: 687b ldr r3, [r7, #4] + 8002dfa: 681b ldr r3, [r3, #0] + 8002dfc: 2202 movs r2, #2 + 8002dfe: 4013 ands r3, r2 + 8002e00: d009 beq.n 8002e16 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8002e02: 4b83 ldr r3, [pc, #524] ; (8003010 ) + 8002e04: 68db ldr r3, [r3, #12] + 8002e06: 22f0 movs r2, #240 ; 0xf0 + 8002e08: 4393 bics r3, r2 + 8002e0a: 0019 movs r1, r3 + 8002e0c: 687b ldr r3, [r7, #4] + 8002e0e: 689a ldr r2, [r3, #8] + 8002e10: 4b7f ldr r3, [pc, #508] ; (8003010 ) + 8002e12: 430a orrs r2, r1 + 8002e14: 60da str r2, [r3, #12] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8002e16: 687b ldr r3, [r7, #4] + 8002e18: 681b ldr r3, [r3, #0] + 8002e1a: 2201 movs r2, #1 + 8002e1c: 4013 ands r3, r2 + 8002e1e: d100 bne.n 8002e22 + 8002e20: e089 b.n 8002f36 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8002e22: 687b ldr r3, [r7, #4] + 8002e24: 685b ldr r3, [r3, #4] + 8002e26: 2b02 cmp r3, #2 + 8002e28: d107 bne.n 8002e3a + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8002e2a: 4b79 ldr r3, [pc, #484] ; (8003010 ) + 8002e2c: 681a ldr r2, [r3, #0] + 8002e2e: 2380 movs r3, #128 ; 0x80 + 8002e30: 029b lsls r3, r3, #10 + 8002e32: 4013 ands r3, r2 + 8002e34: d120 bne.n 8002e78 + { + return HAL_ERROR; + 8002e36: 2301 movs r3, #1 + 8002e38: e0e1 b.n 8002ffe + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8002e3a: 687b ldr r3, [r7, #4] + 8002e3c: 685b ldr r3, [r3, #4] + 8002e3e: 2b03 cmp r3, #3 + 8002e40: d107 bne.n 8002e52 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8002e42: 4b73 ldr r3, [pc, #460] ; (8003010 ) + 8002e44: 681a ldr r2, [r3, #0] + 8002e46: 2380 movs r3, #128 ; 0x80 + 8002e48: 049b lsls r3, r3, #18 + 8002e4a: 4013 ands r3, r2 + 8002e4c: d114 bne.n 8002e78 + { + return HAL_ERROR; + 8002e4e: 2301 movs r3, #1 + 8002e50: e0d5 b.n 8002ffe + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8002e52: 687b ldr r3, [r7, #4] + 8002e54: 685b ldr r3, [r3, #4] + 8002e56: 2b01 cmp r3, #1 + 8002e58: d106 bne.n 8002e68 + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8002e5a: 4b6d ldr r3, [pc, #436] ; (8003010 ) + 8002e5c: 681b ldr r3, [r3, #0] + 8002e5e: 2204 movs r2, #4 + 8002e60: 4013 ands r3, r2 + 8002e62: d109 bne.n 8002e78 + { + return HAL_ERROR; + 8002e64: 2301 movs r3, #1 + 8002e66: e0ca b.n 8002ffe + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8002e68: 4b69 ldr r3, [pc, #420] ; (8003010 ) + 8002e6a: 681a ldr r2, [r3, #0] + 8002e6c: 2380 movs r3, #128 ; 0x80 + 8002e6e: 009b lsls r3, r3, #2 + 8002e70: 4013 ands r3, r2 + 8002e72: d101 bne.n 8002e78 + { + return HAL_ERROR; + 8002e74: 2301 movs r3, #1 + 8002e76: e0c2 b.n 8002ffe + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8002e78: 4b65 ldr r3, [pc, #404] ; (8003010 ) + 8002e7a: 68db ldr r3, [r3, #12] + 8002e7c: 2203 movs r2, #3 + 8002e7e: 4393 bics r3, r2 + 8002e80: 0019 movs r1, r3 + 8002e82: 687b ldr r3, [r7, #4] + 8002e84: 685a ldr r2, [r3, #4] + 8002e86: 4b62 ldr r3, [pc, #392] ; (8003010 ) + 8002e88: 430a orrs r2, r1 + 8002e8a: 60da str r2, [r3, #12] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002e8c: f7fe fc84 bl 8001798 + 8002e90: 0003 movs r3, r0 + 8002e92: 60fb str r3, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8002e94: 687b ldr r3, [r7, #4] + 8002e96: 685b ldr r3, [r3, #4] + 8002e98: 2b02 cmp r3, #2 + 8002e9a: d111 bne.n 8002ec0 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8002e9c: e009 b.n 8002eb2 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002e9e: f7fe fc7b bl 8001798 + 8002ea2: 0002 movs r2, r0 + 8002ea4: 68fb ldr r3, [r7, #12] + 8002ea6: 1ad3 subs r3, r2, r3 + 8002ea8: 4a58 ldr r2, [pc, #352] ; (800300c ) + 8002eaa: 4293 cmp r3, r2 + 8002eac: d901 bls.n 8002eb2 + { + return HAL_TIMEOUT; + 8002eae: 2303 movs r3, #3 + 8002eb0: e0a5 b.n 8002ffe + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8002eb2: 4b57 ldr r3, [pc, #348] ; (8003010 ) + 8002eb4: 68db ldr r3, [r3, #12] + 8002eb6: 220c movs r2, #12 + 8002eb8: 4013 ands r3, r2 + 8002eba: 2b08 cmp r3, #8 + 8002ebc: d1ef bne.n 8002e9e + 8002ebe: e03a b.n 8002f36 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8002ec0: 687b ldr r3, [r7, #4] + 8002ec2: 685b ldr r3, [r3, #4] + 8002ec4: 2b03 cmp r3, #3 + 8002ec6: d111 bne.n 8002eec + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8002ec8: e009 b.n 8002ede + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002eca: f7fe fc65 bl 8001798 + 8002ece: 0002 movs r2, r0 + 8002ed0: 68fb ldr r3, [r7, #12] + 8002ed2: 1ad3 subs r3, r2, r3 + 8002ed4: 4a4d ldr r2, [pc, #308] ; (800300c ) + 8002ed6: 4293 cmp r3, r2 + 8002ed8: d901 bls.n 8002ede + { + return HAL_TIMEOUT; + 8002eda: 2303 movs r3, #3 + 8002edc: e08f b.n 8002ffe + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8002ede: 4b4c ldr r3, [pc, #304] ; (8003010 ) + 8002ee0: 68db ldr r3, [r3, #12] + 8002ee2: 220c movs r2, #12 + 8002ee4: 4013 ands r3, r2 + 8002ee6: 2b0c cmp r3, #12 + 8002ee8: d1ef bne.n 8002eca + 8002eea: e024 b.n 8002f36 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8002eec: 687b ldr r3, [r7, #4] + 8002eee: 685b ldr r3, [r3, #4] + 8002ef0: 2b01 cmp r3, #1 + 8002ef2: d11b bne.n 8002f2c + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8002ef4: e009 b.n 8002f0a + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002ef6: f7fe fc4f bl 8001798 + 8002efa: 0002 movs r2, r0 + 8002efc: 68fb ldr r3, [r7, #12] + 8002efe: 1ad3 subs r3, r2, r3 + 8002f00: 4a42 ldr r2, [pc, #264] ; (800300c ) + 8002f02: 4293 cmp r3, r2 + 8002f04: d901 bls.n 8002f0a + { + return HAL_TIMEOUT; + 8002f06: 2303 movs r3, #3 + 8002f08: e079 b.n 8002ffe + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8002f0a: 4b41 ldr r3, [pc, #260] ; (8003010 ) + 8002f0c: 68db ldr r3, [r3, #12] + 8002f0e: 220c movs r2, #12 + 8002f10: 4013 ands r3, r2 + 8002f12: 2b04 cmp r3, #4 + 8002f14: d1ef bne.n 8002ef6 + 8002f16: e00e b.n 8002f36 + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002f18: f7fe fc3e bl 8001798 + 8002f1c: 0002 movs r2, r0 + 8002f1e: 68fb ldr r3, [r7, #12] + 8002f20: 1ad3 subs r3, r2, r3 + 8002f22: 4a3a ldr r2, [pc, #232] ; (800300c ) + 8002f24: 4293 cmp r3, r2 + 8002f26: d901 bls.n 8002f2c + { + return HAL_TIMEOUT; + 8002f28: 2303 movs r3, #3 + 8002f2a: e068 b.n 8002ffe + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 8002f2c: 4b38 ldr r3, [pc, #224] ; (8003010 ) + 8002f2e: 68db ldr r3, [r3, #12] + 8002f30: 220c movs r2, #12 + 8002f32: 4013 ands r3, r2 + 8002f34: d1f0 bne.n 8002f18 + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8002f36: 4b34 ldr r3, [pc, #208] ; (8003008 ) + 8002f38: 681b ldr r3, [r3, #0] + 8002f3a: 2201 movs r2, #1 + 8002f3c: 4013 ands r3, r2 + 8002f3e: 683a ldr r2, [r7, #0] + 8002f40: 429a cmp r2, r3 + 8002f42: d21e bcs.n 8002f82 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002f44: 4b30 ldr r3, [pc, #192] ; (8003008 ) + 8002f46: 681b ldr r3, [r3, #0] + 8002f48: 2201 movs r2, #1 + 8002f4a: 4393 bics r3, r2 + 8002f4c: 0019 movs r1, r3 + 8002f4e: 4b2e ldr r3, [pc, #184] ; (8003008 ) + 8002f50: 683a ldr r2, [r7, #0] + 8002f52: 430a orrs r2, r1 + 8002f54: 601a str r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + 8002f56: f7fe fc1f bl 8001798 + 8002f5a: 0003 movs r3, r0 + 8002f5c: 60fb str r3, [r7, #12] + + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002f5e: e009 b.n 8002f74 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002f60: f7fe fc1a bl 8001798 + 8002f64: 0002 movs r2, r0 + 8002f66: 68fb ldr r3, [r7, #12] + 8002f68: 1ad3 subs r3, r2, r3 + 8002f6a: 4a28 ldr r2, [pc, #160] ; (800300c ) + 8002f6c: 4293 cmp r3, r2 + 8002f6e: d901 bls.n 8002f74 + { + return HAL_TIMEOUT; + 8002f70: 2303 movs r3, #3 + 8002f72: e044 b.n 8002ffe + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002f74: 4b24 ldr r3, [pc, #144] ; (8003008 ) + 8002f76: 681b ldr r3, [r3, #0] + 8002f78: 2201 movs r2, #1 + 8002f7a: 4013 ands r3, r2 + 8002f7c: 683a ldr r2, [r7, #0] + 8002f7e: 429a cmp r2, r3 + 8002f80: d1ee bne.n 8002f60 + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002f82: 687b ldr r3, [r7, #4] + 8002f84: 681b ldr r3, [r3, #0] + 8002f86: 2204 movs r2, #4 + 8002f88: 4013 ands r3, r2 + 8002f8a: d009 beq.n 8002fa0 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8002f8c: 4b20 ldr r3, [pc, #128] ; (8003010 ) + 8002f8e: 68db ldr r3, [r3, #12] + 8002f90: 4a20 ldr r2, [pc, #128] ; (8003014 ) + 8002f92: 4013 ands r3, r2 + 8002f94: 0019 movs r1, r3 + 8002f96: 687b ldr r3, [r7, #4] + 8002f98: 68da ldr r2, [r3, #12] + 8002f9a: 4b1d ldr r3, [pc, #116] ; (8003010 ) + 8002f9c: 430a orrs r2, r1 + 8002f9e: 60da str r2, [r3, #12] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002fa0: 687b ldr r3, [r7, #4] + 8002fa2: 681b ldr r3, [r3, #0] + 8002fa4: 2208 movs r2, #8 + 8002fa6: 4013 ands r3, r2 + 8002fa8: d00a beq.n 8002fc0 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 8002faa: 4b19 ldr r3, [pc, #100] ; (8003010 ) + 8002fac: 68db ldr r3, [r3, #12] + 8002fae: 4a1a ldr r2, [pc, #104] ; (8003018 ) + 8002fb0: 4013 ands r3, r2 + 8002fb2: 0019 movs r1, r3 + 8002fb4: 687b ldr r3, [r7, #4] + 8002fb6: 691b ldr r3, [r3, #16] + 8002fb8: 00da lsls r2, r3, #3 + 8002fba: 4b15 ldr r3, [pc, #84] ; (8003010 ) + 8002fbc: 430a orrs r2, r1 + 8002fbe: 60da str r2, [r3, #12] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8002fc0: f000 f832 bl 8003028 + 8002fc4: 0001 movs r1, r0 + 8002fc6: 4b12 ldr r3, [pc, #72] ; (8003010 ) + 8002fc8: 68db ldr r3, [r3, #12] + 8002fca: 091b lsrs r3, r3, #4 + 8002fcc: 220f movs r2, #15 + 8002fce: 4013 ands r3, r2 + 8002fd0: 4a12 ldr r2, [pc, #72] ; (800301c ) + 8002fd2: 5cd3 ldrb r3, [r2, r3] + 8002fd4: 000a movs r2, r1 + 8002fd6: 40da lsrs r2, r3 + 8002fd8: 4b11 ldr r3, [pc, #68] ; (8003020 ) + 8002fda: 601a str r2, [r3, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8002fdc: 4b11 ldr r3, [pc, #68] ; (8003024 ) + 8002fde: 681b ldr r3, [r3, #0] + 8002fe0: 250b movs r5, #11 + 8002fe2: 197c adds r4, r7, r5 + 8002fe4: 0018 movs r0, r3 + 8002fe6: f7fe fb91 bl 800170c + 8002fea: 0003 movs r3, r0 + 8002fec: 7023 strb r3, [r4, #0] + if(status != HAL_OK) + 8002fee: 197b adds r3, r7, r5 + 8002ff0: 781b ldrb r3, [r3, #0] + 8002ff2: 2b00 cmp r3, #0 + 8002ff4: d002 beq.n 8002ffc + { + return status; + 8002ff6: 197b adds r3, r7, r5 + 8002ff8: 781b ldrb r3, [r3, #0] + 8002ffa: e000 b.n 8002ffe + } + + return HAL_OK; + 8002ffc: 2300 movs r3, #0 +} + 8002ffe: 0018 movs r0, r3 + 8003000: 46bd mov sp, r7 + 8003002: b004 add sp, #16 + 8003004: bdb0 pop {r4, r5, r7, pc} + 8003006: 46c0 nop ; (mov r8, r8) + 8003008: 40022000 .word 0x40022000 + 800300c: 00001388 .word 0x00001388 + 8003010: 40021000 .word 0x40021000 + 8003014: fffff8ff .word 0xfffff8ff + 8003018: ffffc7ff .word 0xffffc7ff + 800301c: 08007884 .word 0x08007884 + 8003020: 20000000 .word 0x20000000 + 8003024: 20000004 .word 0x20000004 + +08003028 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8003028: b5b0 push {r4, r5, r7, lr} + 800302a: b08e sub sp, #56 ; 0x38 + 800302c: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange; /* no init needed */ + uint32_t sysclockfreq; + + tmpreg = RCC->CFGR; + 800302e: 4b4c ldr r3, [pc, #304] ; (8003160 ) + 8003030: 68db ldr r3, [r3, #12] + 8003032: 62fb str r3, [r7, #44] ; 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8003034: 6afa ldr r2, [r7, #44] ; 0x2c + 8003036: 230c movs r3, #12 + 8003038: 4013 ands r3, r2 + 800303a: 2b0c cmp r3, #12 + 800303c: d014 beq.n 8003068 + 800303e: d900 bls.n 8003042 + 8003040: e07b b.n 800313a + 8003042: 2b04 cmp r3, #4 + 8003044: d002 beq.n 800304c + 8003046: 2b08 cmp r3, #8 + 8003048: d00b beq.n 8003062 + 800304a: e076 b.n 800313a + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + 800304c: 4b44 ldr r3, [pc, #272] ; (8003160 ) + 800304e: 681b ldr r3, [r3, #0] + 8003050: 2210 movs r2, #16 + 8003052: 4013 ands r3, r2 + 8003054: d002 beq.n 800305c + { + sysclockfreq = (HSI_VALUE >> 2); + 8003056: 4b43 ldr r3, [pc, #268] ; (8003164 ) + 8003058: 633b str r3, [r7, #48] ; 0x30 + } + else + { + sysclockfreq = HSI_VALUE; + } + break; + 800305a: e07c b.n 8003156 + sysclockfreq = HSI_VALUE; + 800305c: 4b42 ldr r3, [pc, #264] ; (8003168 ) + 800305e: 633b str r3, [r7, #48] ; 0x30 + break; + 8003060: e079 b.n 8003156 + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8003062: 4b42 ldr r3, [pc, #264] ; (800316c ) + 8003064: 633b str r3, [r7, #48] ; 0x30 + break; + 8003066: e076 b.n 8003156 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8003068: 6afb ldr r3, [r7, #44] ; 0x2c + 800306a: 0c9a lsrs r2, r3, #18 + 800306c: 230f movs r3, #15 + 800306e: 401a ands r2, r3 + 8003070: 4b3f ldr r3, [pc, #252] ; (8003170 ) + 8003072: 5c9b ldrb r3, [r3, r2] + 8003074: 62bb str r3, [r7, #40] ; 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8003076: 6afb ldr r3, [r7, #44] ; 0x2c + 8003078: 0d9a lsrs r2, r3, #22 + 800307a: 2303 movs r3, #3 + 800307c: 4013 ands r3, r2 + 800307e: 3301 adds r3, #1 + 8003080: 627b str r3, [r7, #36] ; 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8003082: 4b37 ldr r3, [pc, #220] ; (8003160 ) + 8003084: 68da ldr r2, [r3, #12] + 8003086: 2380 movs r3, #128 ; 0x80 + 8003088: 025b lsls r3, r3, #9 + 800308a: 4013 ands r3, r2 + 800308c: d01a beq.n 80030c4 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 800308e: 6abb ldr r3, [r7, #40] ; 0x28 + 8003090: 61bb str r3, [r7, #24] + 8003092: 2300 movs r3, #0 + 8003094: 61fb str r3, [r7, #28] + 8003096: 4a35 ldr r2, [pc, #212] ; (800316c ) + 8003098: 2300 movs r3, #0 + 800309a: 69b8 ldr r0, [r7, #24] + 800309c: 69f9 ldr r1, [r7, #28] + 800309e: f7fd f8df bl 8000260 <__aeabi_lmul> + 80030a2: 0002 movs r2, r0 + 80030a4: 000b movs r3, r1 + 80030a6: 0010 movs r0, r2 + 80030a8: 0019 movs r1, r3 + 80030aa: 6a7b ldr r3, [r7, #36] ; 0x24 + 80030ac: 613b str r3, [r7, #16] + 80030ae: 2300 movs r3, #0 + 80030b0: 617b str r3, [r7, #20] + 80030b2: 693a ldr r2, [r7, #16] + 80030b4: 697b ldr r3, [r7, #20] + 80030b6: f7fd f8b3 bl 8000220 <__aeabi_uldivmod> + 80030ba: 0002 movs r2, r0 + 80030bc: 000b movs r3, r1 + 80030be: 0013 movs r3, r2 + 80030c0: 637b str r3, [r7, #52] ; 0x34 + 80030c2: e037 b.n 8003134 + } + else + { + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + 80030c4: 4b26 ldr r3, [pc, #152] ; (8003160 ) + 80030c6: 681b ldr r3, [r3, #0] + 80030c8: 2210 movs r2, #16 + 80030ca: 4013 ands r3, r2 + 80030cc: d01a beq.n 8003104 + { + pllvco = (uint32_t)((((uint64_t)(HSI_VALUE >> 2)) * (uint64_t)pllm) / (uint64_t)plld); + 80030ce: 6abb ldr r3, [r7, #40] ; 0x28 + 80030d0: 60bb str r3, [r7, #8] + 80030d2: 2300 movs r3, #0 + 80030d4: 60fb str r3, [r7, #12] + 80030d6: 4a23 ldr r2, [pc, #140] ; (8003164 ) + 80030d8: 2300 movs r3, #0 + 80030da: 68b8 ldr r0, [r7, #8] + 80030dc: 68f9 ldr r1, [r7, #12] + 80030de: f7fd f8bf bl 8000260 <__aeabi_lmul> + 80030e2: 0002 movs r2, r0 + 80030e4: 000b movs r3, r1 + 80030e6: 0010 movs r0, r2 + 80030e8: 0019 movs r1, r3 + 80030ea: 6a7b ldr r3, [r7, #36] ; 0x24 + 80030ec: 603b str r3, [r7, #0] + 80030ee: 2300 movs r3, #0 + 80030f0: 607b str r3, [r7, #4] + 80030f2: 683a ldr r2, [r7, #0] + 80030f4: 687b ldr r3, [r7, #4] + 80030f6: f7fd f893 bl 8000220 <__aeabi_uldivmod> + 80030fa: 0002 movs r2, r0 + 80030fc: 000b movs r3, r1 + 80030fe: 0013 movs r3, r2 + 8003100: 637b str r3, [r7, #52] ; 0x34 + 8003102: e017 b.n 8003134 + } + else + { + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8003104: 6abb ldr r3, [r7, #40] ; 0x28 + 8003106: 0018 movs r0, r3 + 8003108: 2300 movs r3, #0 + 800310a: 0019 movs r1, r3 + 800310c: 4a16 ldr r2, [pc, #88] ; (8003168 ) + 800310e: 2300 movs r3, #0 + 8003110: f7fd f8a6 bl 8000260 <__aeabi_lmul> + 8003114: 0002 movs r2, r0 + 8003116: 000b movs r3, r1 + 8003118: 0010 movs r0, r2 + 800311a: 0019 movs r1, r3 + 800311c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800311e: 001c movs r4, r3 + 8003120: 2300 movs r3, #0 + 8003122: 001d movs r5, r3 + 8003124: 0022 movs r2, r4 + 8003126: 002b movs r3, r5 + 8003128: f7fd f87a bl 8000220 <__aeabi_uldivmod> + 800312c: 0002 movs r2, r0 + 800312e: 000b movs r3, r1 + 8003130: 0013 movs r3, r2 + 8003132: 637b str r3, [r7, #52] ; 0x34 + } + } + sysclockfreq = pllvco; + 8003134: 6b7b ldr r3, [r7, #52] ; 0x34 + 8003136: 633b str r3, [r7, #48] ; 0x30 + break; + 8003138: e00d b.n 8003156 + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 800313a: 4b09 ldr r3, [pc, #36] ; (8003160 ) + 800313c: 685b ldr r3, [r3, #4] + 800313e: 0b5b lsrs r3, r3, #13 + 8003140: 2207 movs r2, #7 + 8003142: 4013 ands r3, r2 + 8003144: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8003146: 6a3b ldr r3, [r7, #32] + 8003148: 3301 adds r3, #1 + 800314a: 2280 movs r2, #128 ; 0x80 + 800314c: 0212 lsls r2, r2, #8 + 800314e: 409a lsls r2, r3 + 8003150: 0013 movs r3, r2 + 8003152: 633b str r3, [r7, #48] ; 0x30 + break; + 8003154: 46c0 nop ; (mov r8, r8) + } + } + return sysclockfreq; + 8003156: 6b3b ldr r3, [r7, #48] ; 0x30 +} + 8003158: 0018 movs r0, r3 + 800315a: 46bd mov sp, r7 + 800315c: b00e add sp, #56 ; 0x38 + 800315e: bdb0 pop {r4, r5, r7, pc} + 8003160: 40021000 .word 0x40021000 + 8003164: 003d0900 .word 0x003d0900 + 8003168: 00f42400 .word 0x00f42400 + 800316c: 007a1200 .word 0x007a1200 + 8003170: 0800789c .word 0x0800789c + +08003174 : + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8003174: b580 push {r7, lr} + 8003176: af00 add r7, sp, #0 + return SystemCoreClock; + 8003178: 4b02 ldr r3, [pc, #8] ; (8003184 ) + 800317a: 681b ldr r3, [r3, #0] +} + 800317c: 0018 movs r0, r3 + 800317e: 46bd mov sp, r7 + 8003180: bd80 pop {r7, pc} + 8003182: 46c0 nop ; (mov r8, r8) + 8003184: 20000000 .word 0x20000000 + +08003188 : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8003188: b580 push {r7, lr} + 800318a: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + 800318c: f7ff fff2 bl 8003174 + 8003190: 0001 movs r1, r0 + 8003192: 4b06 ldr r3, [pc, #24] ; (80031ac ) + 8003194: 68db ldr r3, [r3, #12] + 8003196: 0a1b lsrs r3, r3, #8 + 8003198: 2207 movs r2, #7 + 800319a: 4013 ands r3, r2 + 800319c: 4a04 ldr r2, [pc, #16] ; (80031b0 ) + 800319e: 5cd3 ldrb r3, [r2, r3] + 80031a0: 40d9 lsrs r1, r3 + 80031a2: 000b movs r3, r1 +} + 80031a4: 0018 movs r0, r3 + 80031a6: 46bd mov sp, r7 + 80031a8: bd80 pop {r7, pc} + 80031aa: 46c0 nop ; (mov r8, r8) + 80031ac: 40021000 .word 0x40021000 + 80031b0: 08007894 .word 0x08007894 + +080031b4 : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 80031b4: b580 push {r7, lr} + 80031b6: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); + 80031b8: f7ff ffdc bl 8003174 + 80031bc: 0001 movs r1, r0 + 80031be: 4b06 ldr r3, [pc, #24] ; (80031d8 ) + 80031c0: 68db ldr r3, [r3, #12] + 80031c2: 0adb lsrs r3, r3, #11 + 80031c4: 2207 movs r2, #7 + 80031c6: 4013 ands r3, r2 + 80031c8: 4a04 ldr r2, [pc, #16] ; (80031dc ) + 80031ca: 5cd3 ldrb r3, [r2, r3] + 80031cc: 40d9 lsrs r1, r3 + 80031ce: 000b movs r3, r1 +} + 80031d0: 0018 movs r0, r3 + 80031d2: 46bd mov sp, r7 + 80031d4: bd80 pop {r7, pc} + 80031d6: 46c0 nop ; (mov r8, r8) + 80031d8: 40021000 .word 0x40021000 + 80031dc: 08007894 .word 0x08007894 + +080031e0 : + * @retval HAL status + * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig() + * to possibly update HSE divider. + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 80031e0: b580 push {r7, lr} + 80031e2: b086 sub sp, #24 + 80031e4: af00 add r7, sp, #0 + 80031e6: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t temp_reg; + FlagStatus pwrclkchanged = RESET; + 80031e8: 2017 movs r0, #23 + 80031ea: 183b adds r3, r7, r0 + 80031ec: 2200 movs r2, #0 + 80031ee: 701a strb r2, [r3, #0] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 80031f0: 687b ldr r3, [r7, #4] + 80031f2: 681b ldr r3, [r3, #0] + 80031f4: 2220 movs r2, #32 + 80031f6: 4013 ands r3, r2 + 80031f8: d100 bne.n 80031fc + 80031fa: e0c2 b.n 8003382 +#endif /* LCD */ + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 80031fc: 4b81 ldr r3, [pc, #516] ; (8003404 ) + 80031fe: 6b9a ldr r2, [r3, #56] ; 0x38 + 8003200: 2380 movs r3, #128 ; 0x80 + 8003202: 055b lsls r3, r3, #21 + 8003204: 4013 ands r3, r2 + 8003206: d109 bne.n 800321c + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8003208: 4b7e ldr r3, [pc, #504] ; (8003404 ) + 800320a: 6b9a ldr r2, [r3, #56] ; 0x38 + 800320c: 4b7d ldr r3, [pc, #500] ; (8003404 ) + 800320e: 2180 movs r1, #128 ; 0x80 + 8003210: 0549 lsls r1, r1, #21 + 8003212: 430a orrs r2, r1 + 8003214: 639a str r2, [r3, #56] ; 0x38 + pwrclkchanged = SET; + 8003216: 183b adds r3, r7, r0 + 8003218: 2201 movs r2, #1 + 800321a: 701a strb r2, [r3, #0] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 800321c: 4b7a ldr r3, [pc, #488] ; (8003408 ) + 800321e: 681a ldr r2, [r3, #0] + 8003220: 2380 movs r3, #128 ; 0x80 + 8003222: 005b lsls r3, r3, #1 + 8003224: 4013 ands r3, r2 + 8003226: d11a bne.n 800325e + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8003228: 4b77 ldr r3, [pc, #476] ; (8003408 ) + 800322a: 681a ldr r2, [r3, #0] + 800322c: 4b76 ldr r3, [pc, #472] ; (8003408 ) + 800322e: 2180 movs r1, #128 ; 0x80 + 8003230: 0049 lsls r1, r1, #1 + 8003232: 430a orrs r2, r1 + 8003234: 601a str r2, [r3, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8003236: f7fe faaf bl 8001798 + 800323a: 0003 movs r3, r0 + 800323c: 613b str r3, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 800323e: e008 b.n 8003252 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8003240: f7fe faaa bl 8001798 + 8003244: 0002 movs r2, r0 + 8003246: 693b ldr r3, [r7, #16] + 8003248: 1ad3 subs r3, r2, r3 + 800324a: 2b64 cmp r3, #100 ; 0x64 + 800324c: d901 bls.n 8003252 + { + return HAL_TIMEOUT; + 800324e: 2303 movs r3, #3 + 8003250: e0d4 b.n 80033fc + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8003252: 4b6d ldr r3, [pc, #436] ; (8003408 ) + 8003254: 681a ldr r2, [r3, #0] + 8003256: 2380 movs r3, #128 ; 0x80 + 8003258: 005b lsls r3, r3, #1 + 800325a: 4013 ands r3, r2 + 800325c: d0f0 beq.n 8003240 + } + } + } + + /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ + temp_reg = (RCC->CR & RCC_CR_RTCPRE); + 800325e: 4b69 ldr r3, [pc, #420] ; (8003404 ) + 8003260: 681a ldr r2, [r3, #0] + 8003262: 23c0 movs r3, #192 ; 0xc0 + 8003264: 039b lsls r3, r3, #14 + 8003266: 4013 ands r3, r2 + 8003268: 60fb str r3, [r7, #12] + if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) + 800326a: 687b ldr r3, [r7, #4] + 800326c: 685a ldr r2, [r3, #4] + 800326e: 23c0 movs r3, #192 ; 0xc0 + 8003270: 039b lsls r3, r3, #14 + 8003272: 4013 ands r3, r2 + 8003274: 68fa ldr r2, [r7, #12] + 8003276: 429a cmp r2, r3 + 8003278: d013 beq.n 80032a2 +#if defined (LCD) + || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) +#endif /* LCD */ + ) + { /* Check HSE State */ + if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) + 800327a: 687b ldr r3, [r7, #4] + 800327c: 685a ldr r2, [r3, #4] + 800327e: 23c0 movs r3, #192 ; 0xc0 + 8003280: 029b lsls r3, r3, #10 + 8003282: 401a ands r2, r3 + 8003284: 23c0 movs r3, #192 ; 0xc0 + 8003286: 029b lsls r3, r3, #10 + 8003288: 429a cmp r2, r3 + 800328a: d10a bne.n 80032a2 + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + 800328c: 4b5d ldr r3, [pc, #372] ; (8003404 ) + 800328e: 681a ldr r2, [r3, #0] + 8003290: 2380 movs r3, #128 ; 0x80 + 8003292: 029b lsls r3, r3, #10 + 8003294: 401a ands r2, r3 + 8003296: 2380 movs r3, #128 ; 0x80 + 8003298: 029b lsls r3, r3, #10 + 800329a: 429a cmp r2, r3 + 800329c: d101 bne.n 80032a2 + { + /* To update HSE divider, first switch-OFF HSE clock oscillator*/ + return HAL_ERROR; + 800329e: 2301 movs r3, #1 + 80032a0: e0ac b.n 80033fc + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); + 80032a2: 4b58 ldr r3, [pc, #352] ; (8003404 ) + 80032a4: 6d1a ldr r2, [r3, #80] ; 0x50 + 80032a6: 23c0 movs r3, #192 ; 0xc0 + 80032a8: 029b lsls r3, r3, #10 + 80032aa: 4013 ands r3, r2 + 80032ac: 60fb str r3, [r7, #12] + + if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ + 80032ae: 68fb ldr r3, [r7, #12] + 80032b0: 2b00 cmp r3, #0 + 80032b2: d03b beq.n 800332c + 80032b4: 687b ldr r3, [r7, #4] + 80032b6: 685a ldr r2, [r3, #4] + 80032b8: 23c0 movs r3, #192 ; 0xc0 + 80032ba: 029b lsls r3, r3, #10 + 80032bc: 4013 ands r3, r2 + 80032be: 68fa ldr r2, [r7, #12] + 80032c0: 429a cmp r2, r3 + 80032c2: d033 beq.n 800332c + && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + 80032c4: 687b ldr r3, [r7, #4] + 80032c6: 681b ldr r3, [r3, #0] + 80032c8: 2220 movs r2, #32 + 80032ca: 4013 ands r3, r2 + 80032cc: d02e beq.n 800332c + && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)) +#endif /* LCD */ + )) + { + /* Store the content of CSR register before the reset of Backup Domain */ + temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + 80032ce: 4b4d ldr r3, [pc, #308] ; (8003404 ) + 80032d0: 6d1b ldr r3, [r3, #80] ; 0x50 + 80032d2: 4a4e ldr r2, [pc, #312] ; (800340c ) + 80032d4: 4013 ands r3, r2 + 80032d6: 60fb str r3, [r7, #12] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 80032d8: 4b4a ldr r3, [pc, #296] ; (8003404 ) + 80032da: 6d1a ldr r2, [r3, #80] ; 0x50 + 80032dc: 4b49 ldr r3, [pc, #292] ; (8003404 ) + 80032de: 2180 movs r1, #128 ; 0x80 + 80032e0: 0309 lsls r1, r1, #12 + 80032e2: 430a orrs r2, r1 + 80032e4: 651a str r2, [r3, #80] ; 0x50 + __HAL_RCC_BACKUPRESET_RELEASE(); + 80032e6: 4b47 ldr r3, [pc, #284] ; (8003404 ) + 80032e8: 6d1a ldr r2, [r3, #80] ; 0x50 + 80032ea: 4b46 ldr r3, [pc, #280] ; (8003404 ) + 80032ec: 4948 ldr r1, [pc, #288] ; (8003410 ) + 80032ee: 400a ands r2, r1 + 80032f0: 651a str r2, [r3, #80] ; 0x50 + + /* Restore the Content of CSR register */ + RCC->CSR = temp_reg; + 80032f2: 4b44 ldr r3, [pc, #272] ; (8003404 ) + 80032f4: 68fa ldr r2, [r7, #12] + 80032f6: 651a str r2, [r3, #80] ; 0x50 + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON)) + 80032f8: 68fa ldr r2, [r7, #12] + 80032fa: 2380 movs r3, #128 ; 0x80 + 80032fc: 005b lsls r3, r3, #1 + 80032fe: 4013 ands r3, r2 + 8003300: d014 beq.n 800332c + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003302: f7fe fa49 bl 8001798 + 8003306: 0003 movs r3, r0 + 8003308: 613b str r3, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800330a: e009 b.n 8003320 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 800330c: f7fe fa44 bl 8001798 + 8003310: 0002 movs r2, r0 + 8003312: 693b ldr r3, [r7, #16] + 8003314: 1ad3 subs r3, r2, r3 + 8003316: 4a3f ldr r2, [pc, #252] ; (8003414 ) + 8003318: 4293 cmp r3, r2 + 800331a: d901 bls.n 8003320 + { + return HAL_TIMEOUT; + 800331c: 2303 movs r3, #3 + 800331e: e06d b.n 80033fc + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8003320: 4b38 ldr r3, [pc, #224] ; (8003404 ) + 8003322: 6d1a ldr r2, [r3, #80] ; 0x50 + 8003324: 2380 movs r3, #128 ; 0x80 + 8003326: 009b lsls r3, r3, #2 + 8003328: 4013 ands r3, r2 + 800332a: d0ef beq.n 800330c + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 800332c: 687b ldr r3, [r7, #4] + 800332e: 685a ldr r2, [r3, #4] + 8003330: 23c0 movs r3, #192 ; 0xc0 + 8003332: 029b lsls r3, r3, #10 + 8003334: 401a ands r2, r3 + 8003336: 23c0 movs r3, #192 ; 0xc0 + 8003338: 029b lsls r3, r3, #10 + 800333a: 429a cmp r2, r3 + 800333c: d10c bne.n 8003358 + 800333e: 4b31 ldr r3, [pc, #196] ; (8003404 ) + 8003340: 681b ldr r3, [r3, #0] + 8003342: 4a35 ldr r2, [pc, #212] ; (8003418 ) + 8003344: 4013 ands r3, r2 + 8003346: 0019 movs r1, r3 + 8003348: 687b ldr r3, [r7, #4] + 800334a: 685a ldr r2, [r3, #4] + 800334c: 23c0 movs r3, #192 ; 0xc0 + 800334e: 039b lsls r3, r3, #14 + 8003350: 401a ands r2, r3 + 8003352: 4b2c ldr r3, [pc, #176] ; (8003404 ) + 8003354: 430a orrs r2, r1 + 8003356: 601a str r2, [r3, #0] + 8003358: 4b2a ldr r3, [pc, #168] ; (8003404 ) + 800335a: 6d19 ldr r1, [r3, #80] ; 0x50 + 800335c: 687b ldr r3, [r7, #4] + 800335e: 685a ldr r2, [r3, #4] + 8003360: 23c0 movs r3, #192 ; 0xc0 + 8003362: 029b lsls r3, r3, #10 + 8003364: 401a ands r2, r3 + 8003366: 4b27 ldr r3, [pc, #156] ; (8003404 ) + 8003368: 430a orrs r2, r1 + 800336a: 651a str r2, [r3, #80] ; 0x50 + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 800336c: 2317 movs r3, #23 + 800336e: 18fb adds r3, r7, r3 + 8003370: 781b ldrb r3, [r3, #0] + 8003372: 2b01 cmp r3, #1 + 8003374: d105 bne.n 8003382 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8003376: 4b23 ldr r3, [pc, #140] ; (8003404 ) + 8003378: 6b9a ldr r2, [r3, #56] ; 0x38 + 800337a: 4b22 ldr r3, [pc, #136] ; (8003404 ) + 800337c: 4927 ldr r1, [pc, #156] ; (800341c ) + 800337e: 400a ands r2, r1 + 8003380: 639a str r2, [r3, #56] ; 0x38 + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } +#endif /* RCC_CCIPR_USART1SEL */ + + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8003382: 687b ldr r3, [r7, #4] + 8003384: 681b ldr r3, [r3, #0] + 8003386: 2202 movs r2, #2 + 8003388: 4013 ands r3, r2 + 800338a: d009 beq.n 80033a0 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 800338c: 4b1d ldr r3, [pc, #116] ; (8003404 ) + 800338e: 6cdb ldr r3, [r3, #76] ; 0x4c + 8003390: 220c movs r2, #12 + 8003392: 4393 bics r3, r2 + 8003394: 0019 movs r1, r3 + 8003396: 687b ldr r3, [r7, #4] + 8003398: 689a ldr r2, [r3, #8] + 800339a: 4b1a ldr r3, [pc, #104] ; (8003404 ) + 800339c: 430a orrs r2, r1 + 800339e: 64da str r2, [r3, #76] ; 0x4c + } + + /*------------------------------ LPUART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 80033a0: 687b ldr r3, [r7, #4] + 80033a2: 681b ldr r3, [r3, #0] + 80033a4: 2204 movs r2, #4 + 80033a6: 4013 ands r3, r2 + 80033a8: d009 beq.n 80033be + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUAR1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 80033aa: 4b16 ldr r3, [pc, #88] ; (8003404 ) + 80033ac: 6cdb ldr r3, [r3, #76] ; 0x4c + 80033ae: 4a1c ldr r2, [pc, #112] ; (8003420 ) + 80033b0: 4013 ands r3, r2 + 80033b2: 0019 movs r1, r3 + 80033b4: 687b ldr r3, [r7, #4] + 80033b6: 68da ldr r2, [r3, #12] + 80033b8: 4b12 ldr r3, [pc, #72] ; (8003404 ) + 80033ba: 430a orrs r2, r1 + 80033bc: 64da str r2, [r3, #76] ; 0x4c + } + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 80033be: 687b ldr r3, [r7, #4] + 80033c0: 681b ldr r3, [r3, #0] + 80033c2: 2208 movs r2, #8 + 80033c4: 4013 ands r3, r2 + 80033c6: d009 beq.n 80033dc + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 80033c8: 4b0e ldr r3, [pc, #56] ; (8003404 ) + 80033ca: 6cdb ldr r3, [r3, #76] ; 0x4c + 80033cc: 4a15 ldr r2, [pc, #84] ; (8003424 ) + 80033ce: 4013 ands r3, r2 + 80033d0: 0019 movs r1, r3 + 80033d2: 687b ldr r3, [r7, #4] + 80033d4: 691a ldr r2, [r3, #16] + 80033d6: 4b0b ldr r3, [pc, #44] ; (8003404 ) + 80033d8: 430a orrs r2, r1 + 80033da: 64da str r2, [r3, #76] ; 0x4c + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } +#endif /* USB */ + + /*---------------------------- LPTIM1 configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 80033dc: 687b ldr r3, [r7, #4] + 80033de: 681b ldr r3, [r3, #0] + 80033e0: 2280 movs r2, #128 ; 0x80 + 80033e2: 4013 ands r3, r2 + 80033e4: d009 beq.n 80033fa + { + assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection); + 80033e6: 4b07 ldr r3, [pc, #28] ; (8003404 ) + 80033e8: 6cdb ldr r3, [r3, #76] ; 0x4c + 80033ea: 4a0f ldr r2, [pc, #60] ; (8003428 ) + 80033ec: 4013 ands r3, r2 + 80033ee: 0019 movs r1, r3 + 80033f0: 687b ldr r3, [r7, #4] + 80033f2: 695a ldr r2, [r3, #20] + 80033f4: 4b03 ldr r3, [pc, #12] ; (8003404 ) + 80033f6: 430a orrs r2, r1 + 80033f8: 64da str r2, [r3, #76] ; 0x4c + } + + return HAL_OK; + 80033fa: 2300 movs r3, #0 +} + 80033fc: 0018 movs r0, r3 + 80033fe: 46bd mov sp, r7 + 8003400: b006 add sp, #24 + 8003402: bd80 pop {r7, pc} + 8003404: 40021000 .word 0x40021000 + 8003408: 40007000 .word 0x40007000 + 800340c: fffcffff .word 0xfffcffff + 8003410: fff7ffff .word 0xfff7ffff + 8003414: 00001388 .word 0x00001388 + 8003418: ffcfffff .word 0xffcfffff + 800341c: efffffff .word 0xefffffff + 8003420: fffff3ff .word 0xfffff3ff + 8003424: ffffcfff .word 0xffffcfff + 8003428: fff3ffff .word 0xfff3ffff + +0800342c : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 800342c: b580 push {r7, lr} + 800342e: b082 sub sp, #8 + 8003430: af00 add r7, sp, #0 + 8003432: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8003434: 687b ldr r3, [r7, #4] + 8003436: 2b00 cmp r3, #0 + 8003438: d101 bne.n 800343e + { + return HAL_ERROR; + 800343a: 2301 movs r3, #1 + 800343c: e032 b.n 80034a4 + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 800343e: 687b ldr r3, [r7, #4] + 8003440: 2239 movs r2, #57 ; 0x39 + 8003442: 5c9b ldrb r3, [r3, r2] + 8003444: b2db uxtb r3, r3 + 8003446: 2b00 cmp r3, #0 + 8003448: d107 bne.n 800345a + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 800344a: 687b ldr r3, [r7, #4] + 800344c: 2238 movs r2, #56 ; 0x38 + 800344e: 2100 movs r1, #0 + 8003450: 5499 strb r1, [r3, r2] + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 8003452: 687b ldr r3, [r7, #4] + 8003454: 0018 movs r0, r3 + 8003456: f7fd ffdd bl 8001414 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 800345a: 687b ldr r3, [r7, #4] + 800345c: 2239 movs r2, #57 ; 0x39 + 800345e: 2102 movs r1, #2 + 8003460: 5499 strb r1, [r3, r2] + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8003462: 687b ldr r3, [r7, #4] + 8003464: 681a ldr r2, [r3, #0] + 8003466: 687b ldr r3, [r7, #4] + 8003468: 3304 adds r3, #4 + 800346a: 0019 movs r1, r3 + 800346c: 0010 movs r0, r2 + 800346e: f000 fa9f bl 80039b0 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8003472: 687b ldr r3, [r7, #4] + 8003474: 223e movs r2, #62 ; 0x3e + 8003476: 2101 movs r1, #1 + 8003478: 5499 strb r1, [r3, r2] + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 800347a: 687b ldr r3, [r7, #4] + 800347c: 223a movs r2, #58 ; 0x3a + 800347e: 2101 movs r1, #1 + 8003480: 5499 strb r1, [r3, r2] + 8003482: 687b ldr r3, [r7, #4] + 8003484: 223b movs r2, #59 ; 0x3b + 8003486: 2101 movs r1, #1 + 8003488: 5499 strb r1, [r3, r2] + 800348a: 687b ldr r3, [r7, #4] + 800348c: 223c movs r2, #60 ; 0x3c + 800348e: 2101 movs r1, #1 + 8003490: 5499 strb r1, [r3, r2] + 8003492: 687b ldr r3, [r7, #4] + 8003494: 223d movs r2, #61 ; 0x3d + 8003496: 2101 movs r1, #1 + 8003498: 5499 strb r1, [r3, r2] + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 800349a: 687b ldr r3, [r7, #4] + 800349c: 2239 movs r2, #57 ; 0x39 + 800349e: 2101 movs r1, #1 + 80034a0: 5499 strb r1, [r3, r2] + + return HAL_OK; + 80034a2: 2300 movs r3, #0 +} + 80034a4: 0018 movs r0, r3 + 80034a6: 46bd mov sp, r7 + 80034a8: b002 add sp, #8 + 80034aa: bd80 pop {r7, pc} + +080034ac : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 80034ac: b580 push {r7, lr} + 80034ae: b082 sub sp, #8 + 80034b0: af00 add r7, sp, #0 + 80034b2: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 80034b4: 687b ldr r3, [r7, #4] + 80034b6: 2b00 cmp r3, #0 + 80034b8: d101 bne.n 80034be + { + return HAL_ERROR; + 80034ba: 2301 movs r3, #1 + 80034bc: e032 b.n 8003524 + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 80034be: 687b ldr r3, [r7, #4] + 80034c0: 2239 movs r2, #57 ; 0x39 + 80034c2: 5c9b ldrb r3, [r3, r2] + 80034c4: b2db uxtb r3, r3 + 80034c6: 2b00 cmp r3, #0 + 80034c8: d107 bne.n 80034da + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 80034ca: 687b ldr r3, [r7, #4] + 80034cc: 2238 movs r2, #56 ; 0x38 + 80034ce: 2100 movs r1, #0 + 80034d0: 5499 strb r1, [r3, r2] + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 80034d2: 687b ldr r3, [r7, #4] + 80034d4: 0018 movs r0, r3 + 80034d6: f000 f829 bl 800352c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 80034da: 687b ldr r3, [r7, #4] + 80034dc: 2239 movs r2, #57 ; 0x39 + 80034de: 2102 movs r1, #2 + 80034e0: 5499 strb r1, [r3, r2] + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 80034e2: 687b ldr r3, [r7, #4] + 80034e4: 681a ldr r2, [r3, #0] + 80034e6: 687b ldr r3, [r7, #4] + 80034e8: 3304 adds r3, #4 + 80034ea: 0019 movs r1, r3 + 80034ec: 0010 movs r0, r2 + 80034ee: f000 fa5f bl 80039b0 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 80034f2: 687b ldr r3, [r7, #4] + 80034f4: 223e movs r2, #62 ; 0x3e + 80034f6: 2101 movs r1, #1 + 80034f8: 5499 strb r1, [r3, r2] + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 80034fa: 687b ldr r3, [r7, #4] + 80034fc: 223a movs r2, #58 ; 0x3a + 80034fe: 2101 movs r1, #1 + 8003500: 5499 strb r1, [r3, r2] + 8003502: 687b ldr r3, [r7, #4] + 8003504: 223b movs r2, #59 ; 0x3b + 8003506: 2101 movs r1, #1 + 8003508: 5499 strb r1, [r3, r2] + 800350a: 687b ldr r3, [r7, #4] + 800350c: 223c movs r2, #60 ; 0x3c + 800350e: 2101 movs r1, #1 + 8003510: 5499 strb r1, [r3, r2] + 8003512: 687b ldr r3, [r7, #4] + 8003514: 223d movs r2, #61 ; 0x3d + 8003516: 2101 movs r1, #1 + 8003518: 5499 strb r1, [r3, r2] + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 800351a: 687b ldr r3, [r7, #4] + 800351c: 2239 movs r2, #57 ; 0x39 + 800351e: 2101 movs r1, #1 + 8003520: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8003522: 2300 movs r3, #0 +} + 8003524: 0018 movs r0, r3 + 8003526: 46bd mov sp, r7 + 8003528: b002 add sp, #8 + 800352a: bd80 pop {r7, pc} + +0800352c : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 800352c: b580 push {r7, lr} + 800352e: b082 sub sp, #8 + 8003530: af00 add r7, sp, #0 + 8003532: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 8003534: 46c0 nop ; (mov r8, r8) + 8003536: 46bd mov sp, r7 + 8003538: b002 add sp, #8 + 800353a: bd80 pop {r7, pc} + +0800353c : + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + 800353c: b580 push {r7, lr} + 800353e: b086 sub sp, #24 + 8003540: af00 add r7, sp, #0 + 8003542: 6078 str r0, [r7, #4] + 8003544: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + 8003546: 687b ldr r3, [r7, #4] + 8003548: 2b00 cmp r3, #0 + 800354a: d101 bne.n 8003550 + { + return HAL_ERROR; + 800354c: 2301 movs r3, #1 + 800354e: e088 b.n 8003662 + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8003550: 687b ldr r3, [r7, #4] + 8003552: 2239 movs r2, #57 ; 0x39 + 8003554: 5c9b ldrb r3, [r3, r2] + 8003556: b2db uxtb r3, r3 + 8003558: 2b00 cmp r3, #0 + 800355a: d107 bne.n 800356c + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 800355c: 687b ldr r3, [r7, #4] + 800355e: 2238 movs r2, #56 ; 0x38 + 8003560: 2100 movs r1, #0 + 8003562: 5499 strb r1, [r3, r2] + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + 8003564: 687b ldr r3, [r7, #4] + 8003566: 0018 movs r0, r3 + 8003568: f7fd ff6a bl 8001440 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 800356c: 687b ldr r3, [r7, #4] + 800356e: 2239 movs r2, #57 ; 0x39 + 8003570: 2102 movs r1, #2 + 8003572: 5499 strb r1, [r3, r2] + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + 8003574: 687b ldr r3, [r7, #4] + 8003576: 681b ldr r3, [r3, #0] + 8003578: 689a ldr r2, [r3, #8] + 800357a: 687b ldr r3, [r7, #4] + 800357c: 681b ldr r3, [r3, #0] + 800357e: 493b ldr r1, [pc, #236] ; (800366c ) + 8003580: 400a ands r2, r1 + 8003582: 609a str r2, [r3, #8] + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8003584: 687b ldr r3, [r7, #4] + 8003586: 681a ldr r2, [r3, #0] + 8003588: 687b ldr r3, [r7, #4] + 800358a: 3304 adds r3, #4 + 800358c: 0019 movs r1, r3 + 800358e: 0010 movs r0, r2 + 8003590: f000 fa0e bl 80039b0 + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8003594: 687b ldr r3, [r7, #4] + 8003596: 681b ldr r3, [r3, #0] + 8003598: 689b ldr r3, [r3, #8] + 800359a: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + 800359c: 687b ldr r3, [r7, #4] + 800359e: 681b ldr r3, [r3, #0] + 80035a0: 699b ldr r3, [r3, #24] + 80035a2: 613b str r3, [r7, #16] + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + 80035a4: 687b ldr r3, [r7, #4] + 80035a6: 681b ldr r3, [r3, #0] + 80035a8: 6a1b ldr r3, [r3, #32] + 80035aa: 60fb str r3, [r7, #12] + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + 80035ac: 683b ldr r3, [r7, #0] + 80035ae: 681b ldr r3, [r3, #0] + 80035b0: 697a ldr r2, [r7, #20] + 80035b2: 4313 orrs r3, r2 + 80035b4: 617b str r3, [r7, #20] + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + 80035b6: 693b ldr r3, [r7, #16] + 80035b8: 4a2d ldr r2, [pc, #180] ; (8003670 ) + 80035ba: 4013 ands r3, r2 + 80035bc: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 80035be: 683b ldr r3, [r7, #0] + 80035c0: 689a ldr r2, [r3, #8] + 80035c2: 683b ldr r3, [r7, #0] + 80035c4: 699b ldr r3, [r3, #24] + 80035c6: 021b lsls r3, r3, #8 + 80035c8: 4313 orrs r3, r2 + 80035ca: 693a ldr r2, [r7, #16] + 80035cc: 4313 orrs r3, r2 + 80035ce: 613b str r3, [r7, #16] + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + 80035d0: 693b ldr r3, [r7, #16] + 80035d2: 4a28 ldr r2, [pc, #160] ; (8003674 ) + 80035d4: 4013 ands r3, r2 + 80035d6: 613b str r3, [r7, #16] + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + 80035d8: 693b ldr r3, [r7, #16] + 80035da: 4a27 ldr r2, [pc, #156] ; (8003678 ) + 80035dc: 4013 ands r3, r2 + 80035de: 613b str r3, [r7, #16] + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 80035e0: 683b ldr r3, [r7, #0] + 80035e2: 68da ldr r2, [r3, #12] + 80035e4: 683b ldr r3, [r7, #0] + 80035e6: 69db ldr r3, [r3, #28] + 80035e8: 021b lsls r3, r3, #8 + 80035ea: 4313 orrs r3, r2 + 80035ec: 693a ldr r2, [r7, #16] + 80035ee: 4313 orrs r3, r2 + 80035f0: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 80035f2: 683b ldr r3, [r7, #0] + 80035f4: 691b ldr r3, [r3, #16] + 80035f6: 011a lsls r2, r3, #4 + 80035f8: 683b ldr r3, [r7, #0] + 80035fa: 6a1b ldr r3, [r3, #32] + 80035fc: 031b lsls r3, r3, #12 + 80035fe: 4313 orrs r3, r2 + 8003600: 693a ldr r2, [r7, #16] + 8003602: 4313 orrs r3, r2 + 8003604: 613b str r3, [r7, #16] + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + 8003606: 68fb ldr r3, [r7, #12] + 8003608: 2222 movs r2, #34 ; 0x22 + 800360a: 4393 bics r3, r2 + 800360c: 60fb str r3, [r7, #12] + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + 800360e: 68fb ldr r3, [r7, #12] + 8003610: 2288 movs r2, #136 ; 0x88 + 8003612: 4393 bics r3, r2 + 8003614: 60fb str r3, [r7, #12] + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + 8003616: 683b ldr r3, [r7, #0] + 8003618: 685a ldr r2, [r3, #4] + 800361a: 683b ldr r3, [r7, #0] + 800361c: 695b ldr r3, [r3, #20] + 800361e: 011b lsls r3, r3, #4 + 8003620: 4313 orrs r3, r2 + 8003622: 68fa ldr r2, [r7, #12] + 8003624: 4313 orrs r3, r2 + 8003626: 60fb str r3, [r7, #12] + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8003628: 687b ldr r3, [r7, #4] + 800362a: 681b ldr r3, [r3, #0] + 800362c: 697a ldr r2, [r7, #20] + 800362e: 609a str r2, [r3, #8] + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + 8003630: 687b ldr r3, [r7, #4] + 8003632: 681b ldr r3, [r3, #0] + 8003634: 693a ldr r2, [r7, #16] + 8003636: 619a str r2, [r3, #24] + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + 8003638: 687b ldr r3, [r7, #4] + 800363a: 681b ldr r3, [r3, #0] + 800363c: 68fa ldr r2, [r7, #12] + 800363e: 621a str r2, [r3, #32] + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8003640: 687b ldr r3, [r7, #4] + 8003642: 223e movs r2, #62 ; 0x3e + 8003644: 2101 movs r1, #1 + 8003646: 5499 strb r1, [r3, r2] + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 8003648: 687b ldr r3, [r7, #4] + 800364a: 223a movs r2, #58 ; 0x3a + 800364c: 2101 movs r1, #1 + 800364e: 5499 strb r1, [r3, r2] + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 8003650: 687b ldr r3, [r7, #4] + 8003652: 223b movs r2, #59 ; 0x3b + 8003654: 2101 movs r1, #1 + 8003656: 5499 strb r1, [r3, r2] + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8003658: 687b ldr r3, [r7, #4] + 800365a: 2239 movs r2, #57 ; 0x39 + 800365c: 2101 movs r1, #1 + 800365e: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8003660: 2300 movs r3, #0 +} + 8003662: 0018 movs r0, r3 + 8003664: 46bd mov sp, r7 + 8003666: b006 add sp, #24 + 8003668: bd80 pop {r7, pc} + 800366a: 46c0 nop ; (mov r8, r8) + 800366c: ffffbff8 .word 0xffffbff8 + 8003670: fffffcfc .word 0xfffffcfc + 8003674: fffff3f3 .word 0xfffff3f3 + 8003678: ffff0f0f .word 0xffff0f0f + +0800367c : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 800367c: b580 push {r7, lr} + 800367e: b086 sub sp, #24 + 8003680: af00 add r7, sp, #0 + 8003682: 60f8 str r0, [r7, #12] + 8003684: 60b9 str r1, [r7, #8] + 8003686: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8003688: 2317 movs r3, #23 + 800368a: 18fb adds r3, r7, r3 + 800368c: 2200 movs r2, #0 + 800368e: 701a strb r2, [r3, #0] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8003690: 68fb ldr r3, [r7, #12] + 8003692: 2238 movs r2, #56 ; 0x38 + 8003694: 5c9b ldrb r3, [r3, r2] + 8003696: 2b01 cmp r3, #1 + 8003698: d101 bne.n 800369e + 800369a: 2302 movs r3, #2 + 800369c: e0ad b.n 80037fa + 800369e: 68fb ldr r3, [r7, #12] + 80036a0: 2238 movs r2, #56 ; 0x38 + 80036a2: 2101 movs r1, #1 + 80036a4: 5499 strb r1, [r3, r2] + + switch (Channel) + 80036a6: 687b ldr r3, [r7, #4] + 80036a8: 2b0c cmp r3, #12 + 80036aa: d100 bne.n 80036ae + 80036ac: e076 b.n 800379c + 80036ae: 687b ldr r3, [r7, #4] + 80036b0: 2b0c cmp r3, #12 + 80036b2: d900 bls.n 80036b6 + 80036b4: e095 b.n 80037e2 + 80036b6: 687b ldr r3, [r7, #4] + 80036b8: 2b08 cmp r3, #8 + 80036ba: d04e beq.n 800375a + 80036bc: 687b ldr r3, [r7, #4] + 80036be: 2b08 cmp r3, #8 + 80036c0: d900 bls.n 80036c4 + 80036c2: e08e b.n 80037e2 + 80036c4: 687b ldr r3, [r7, #4] + 80036c6: 2b00 cmp r3, #0 + 80036c8: d003 beq.n 80036d2 + 80036ca: 687b ldr r3, [r7, #4] + 80036cc: 2b04 cmp r3, #4 + 80036ce: d021 beq.n 8003714 + 80036d0: e087 b.n 80037e2 + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 80036d2: 68fb ldr r3, [r7, #12] + 80036d4: 681b ldr r3, [r3, #0] + 80036d6: 68ba ldr r2, [r7, #8] + 80036d8: 0011 movs r1, r2 + 80036da: 0018 movs r0, r3 + 80036dc: f000 f9b2 bl 8003a44 + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 80036e0: 68fb ldr r3, [r7, #12] + 80036e2: 681b ldr r3, [r3, #0] + 80036e4: 699a ldr r2, [r3, #24] + 80036e6: 68fb ldr r3, [r7, #12] + 80036e8: 681b ldr r3, [r3, #0] + 80036ea: 2108 movs r1, #8 + 80036ec: 430a orrs r2, r1 + 80036ee: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 80036f0: 68fb ldr r3, [r7, #12] + 80036f2: 681b ldr r3, [r3, #0] + 80036f4: 699a ldr r2, [r3, #24] + 80036f6: 68fb ldr r3, [r7, #12] + 80036f8: 681b ldr r3, [r3, #0] + 80036fa: 2104 movs r1, #4 + 80036fc: 438a bics r2, r1 + 80036fe: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 8003700: 68fb ldr r3, [r7, #12] + 8003702: 681b ldr r3, [r3, #0] + 8003704: 6999 ldr r1, [r3, #24] + 8003706: 68bb ldr r3, [r7, #8] + 8003708: 68da ldr r2, [r3, #12] + 800370a: 68fb ldr r3, [r7, #12] + 800370c: 681b ldr r3, [r3, #0] + 800370e: 430a orrs r2, r1 + 8003710: 619a str r2, [r3, #24] + break; + 8003712: e06b b.n 80037ec + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 8003714: 68fb ldr r3, [r7, #12] + 8003716: 681b ldr r3, [r3, #0] + 8003718: 68ba ldr r2, [r7, #8] + 800371a: 0011 movs r1, r2 + 800371c: 0018 movs r0, r3 + 800371e: f000 f9cd bl 8003abc + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 8003722: 68fb ldr r3, [r7, #12] + 8003724: 681b ldr r3, [r3, #0] + 8003726: 699a ldr r2, [r3, #24] + 8003728: 68fb ldr r3, [r7, #12] + 800372a: 681b ldr r3, [r3, #0] + 800372c: 2180 movs r1, #128 ; 0x80 + 800372e: 0109 lsls r1, r1, #4 + 8003730: 430a orrs r2, r1 + 8003732: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 8003734: 68fb ldr r3, [r7, #12] + 8003736: 681b ldr r3, [r3, #0] + 8003738: 699a ldr r2, [r3, #24] + 800373a: 68fb ldr r3, [r7, #12] + 800373c: 681b ldr r3, [r3, #0] + 800373e: 4931 ldr r1, [pc, #196] ; (8003804 ) + 8003740: 400a ands r2, r1 + 8003742: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 8003744: 68fb ldr r3, [r7, #12] + 8003746: 681b ldr r3, [r3, #0] + 8003748: 6999 ldr r1, [r3, #24] + 800374a: 68bb ldr r3, [r7, #8] + 800374c: 68db ldr r3, [r3, #12] + 800374e: 021a lsls r2, r3, #8 + 8003750: 68fb ldr r3, [r7, #12] + 8003752: 681b ldr r3, [r3, #0] + 8003754: 430a orrs r2, r1 + 8003756: 619a str r2, [r3, #24] + break; + 8003758: e048 b.n 80037ec + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 800375a: 68fb ldr r3, [r7, #12] + 800375c: 681b ldr r3, [r3, #0] + 800375e: 68ba ldr r2, [r7, #8] + 8003760: 0011 movs r1, r2 + 8003762: 0018 movs r0, r3 + 8003764: f000 f9ec bl 8003b40 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 8003768: 68fb ldr r3, [r7, #12] + 800376a: 681b ldr r3, [r3, #0] + 800376c: 69da ldr r2, [r3, #28] + 800376e: 68fb ldr r3, [r7, #12] + 8003770: 681b ldr r3, [r3, #0] + 8003772: 2108 movs r1, #8 + 8003774: 430a orrs r2, r1 + 8003776: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 8003778: 68fb ldr r3, [r7, #12] + 800377a: 681b ldr r3, [r3, #0] + 800377c: 69da ldr r2, [r3, #28] + 800377e: 68fb ldr r3, [r7, #12] + 8003780: 681b ldr r3, [r3, #0] + 8003782: 2104 movs r1, #4 + 8003784: 438a bics r2, r1 + 8003786: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 8003788: 68fb ldr r3, [r7, #12] + 800378a: 681b ldr r3, [r3, #0] + 800378c: 69d9 ldr r1, [r3, #28] + 800378e: 68bb ldr r3, [r7, #8] + 8003790: 68da ldr r2, [r3, #12] + 8003792: 68fb ldr r3, [r7, #12] + 8003794: 681b ldr r3, [r3, #0] + 8003796: 430a orrs r2, r1 + 8003798: 61da str r2, [r3, #28] + break; + 800379a: e027 b.n 80037ec + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 800379c: 68fb ldr r3, [r7, #12] + 800379e: 681b ldr r3, [r3, #0] + 80037a0: 68ba ldr r2, [r7, #8] + 80037a2: 0011 movs r1, r2 + 80037a4: 0018 movs r0, r3 + 80037a6: f000 fa0b bl 8003bc0 + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 80037aa: 68fb ldr r3, [r7, #12] + 80037ac: 681b ldr r3, [r3, #0] + 80037ae: 69da ldr r2, [r3, #28] + 80037b0: 68fb ldr r3, [r7, #12] + 80037b2: 681b ldr r3, [r3, #0] + 80037b4: 2180 movs r1, #128 ; 0x80 + 80037b6: 0109 lsls r1, r1, #4 + 80037b8: 430a orrs r2, r1 + 80037ba: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 80037bc: 68fb ldr r3, [r7, #12] + 80037be: 681b ldr r3, [r3, #0] + 80037c0: 69da ldr r2, [r3, #28] + 80037c2: 68fb ldr r3, [r7, #12] + 80037c4: 681b ldr r3, [r3, #0] + 80037c6: 490f ldr r1, [pc, #60] ; (8003804 ) + 80037c8: 400a ands r2, r1 + 80037ca: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 80037cc: 68fb ldr r3, [r7, #12] + 80037ce: 681b ldr r3, [r3, #0] + 80037d0: 69d9 ldr r1, [r3, #28] + 80037d2: 68bb ldr r3, [r7, #8] + 80037d4: 68db ldr r3, [r3, #12] + 80037d6: 021a lsls r2, r3, #8 + 80037d8: 68fb ldr r3, [r7, #12] + 80037da: 681b ldr r3, [r3, #0] + 80037dc: 430a orrs r2, r1 + 80037de: 61da str r2, [r3, #28] + break; + 80037e0: e004 b.n 80037ec + } + + default: + status = HAL_ERROR; + 80037e2: 2317 movs r3, #23 + 80037e4: 18fb adds r3, r7, r3 + 80037e6: 2201 movs r2, #1 + 80037e8: 701a strb r2, [r3, #0] + break; + 80037ea: 46c0 nop ; (mov r8, r8) + } + + __HAL_UNLOCK(htim); + 80037ec: 68fb ldr r3, [r7, #12] + 80037ee: 2238 movs r2, #56 ; 0x38 + 80037f0: 2100 movs r1, #0 + 80037f2: 5499 strb r1, [r3, r2] + + return status; + 80037f4: 2317 movs r3, #23 + 80037f6: 18fb adds r3, r7, r3 + 80037f8: 781b ldrb r3, [r3, #0] +} + 80037fa: 0018 movs r0, r3 + 80037fc: 46bd mov sp, r7 + 80037fe: b006 add sp, #24 + 8003800: bd80 pop {r7, pc} + 8003802: 46c0 nop ; (mov r8, r8) + 8003804: fffffbff .word 0xfffffbff + +08003808 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 8003808: b580 push {r7, lr} + 800380a: b084 sub sp, #16 + 800380c: af00 add r7, sp, #0 + 800380e: 6078 str r0, [r7, #4] + 8003810: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8003812: 230f movs r3, #15 + 8003814: 18fb adds r3, r7, r3 + 8003816: 2200 movs r2, #0 + 8003818: 701a strb r2, [r3, #0] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 800381a: 687b ldr r3, [r7, #4] + 800381c: 2238 movs r2, #56 ; 0x38 + 800381e: 5c9b ldrb r3, [r3, r2] + 8003820: 2b01 cmp r3, #1 + 8003822: d101 bne.n 8003828 + 8003824: 2302 movs r3, #2 + 8003826: e0bc b.n 80039a2 + 8003828: 687b ldr r3, [r7, #4] + 800382a: 2238 movs r2, #56 ; 0x38 + 800382c: 2101 movs r1, #1 + 800382e: 5499 strb r1, [r3, r2] + + htim->State = HAL_TIM_STATE_BUSY; + 8003830: 687b ldr r3, [r7, #4] + 8003832: 2239 movs r2, #57 ; 0x39 + 8003834: 2102 movs r1, #2 + 8003836: 5499 strb r1, [r3, r2] + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 8003838: 687b ldr r3, [r7, #4] + 800383a: 681b ldr r3, [r3, #0] + 800383c: 689b ldr r3, [r3, #8] + 800383e: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 8003840: 68bb ldr r3, [r7, #8] + 8003842: 2277 movs r2, #119 ; 0x77 + 8003844: 4393 bics r3, r2 + 8003846: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8003848: 68bb ldr r3, [r7, #8] + 800384a: 4a58 ldr r2, [pc, #352] ; (80039ac ) + 800384c: 4013 ands r3, r2 + 800384e: 60bb str r3, [r7, #8] + htim->Instance->SMCR = tmpsmcr; + 8003850: 687b ldr r3, [r7, #4] + 8003852: 681b ldr r3, [r3, #0] + 8003854: 68ba ldr r2, [r7, #8] + 8003856: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 8003858: 683b ldr r3, [r7, #0] + 800385a: 681b ldr r3, [r3, #0] + 800385c: 2280 movs r2, #128 ; 0x80 + 800385e: 0192 lsls r2, r2, #6 + 8003860: 4293 cmp r3, r2 + 8003862: d040 beq.n 80038e6 + 8003864: 2280 movs r2, #128 ; 0x80 + 8003866: 0192 lsls r2, r2, #6 + 8003868: 4293 cmp r3, r2 + 800386a: d900 bls.n 800386e + 800386c: e088 b.n 8003980 + 800386e: 2280 movs r2, #128 ; 0x80 + 8003870: 0152 lsls r2, r2, #5 + 8003872: 4293 cmp r3, r2 + 8003874: d100 bne.n 8003878 + 8003876: e088 b.n 800398a + 8003878: 2280 movs r2, #128 ; 0x80 + 800387a: 0152 lsls r2, r2, #5 + 800387c: 4293 cmp r3, r2 + 800387e: d900 bls.n 8003882 + 8003880: e07e b.n 8003980 + 8003882: 2b70 cmp r3, #112 ; 0x70 + 8003884: d018 beq.n 80038b8 + 8003886: d900 bls.n 800388a + 8003888: e07a b.n 8003980 + 800388a: 2b60 cmp r3, #96 ; 0x60 + 800388c: d04f beq.n 800392e + 800388e: d900 bls.n 8003892 + 8003890: e076 b.n 8003980 + 8003892: 2b50 cmp r3, #80 ; 0x50 + 8003894: d03b beq.n 800390e + 8003896: d900 bls.n 800389a + 8003898: e072 b.n 8003980 + 800389a: 2b40 cmp r3, #64 ; 0x40 + 800389c: d057 beq.n 800394e + 800389e: d900 bls.n 80038a2 + 80038a0: e06e b.n 8003980 + 80038a2: 2b30 cmp r3, #48 ; 0x30 + 80038a4: d063 beq.n 800396e + 80038a6: d86b bhi.n 8003980 + 80038a8: 2b20 cmp r3, #32 + 80038aa: d060 beq.n 800396e + 80038ac: d868 bhi.n 8003980 + 80038ae: 2b00 cmp r3, #0 + 80038b0: d05d beq.n 800396e + 80038b2: 2b10 cmp r3, #16 + 80038b4: d05b beq.n 800396e + 80038b6: e063 b.n 8003980 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 80038b8: 687b ldr r3, [r7, #4] + 80038ba: 6818 ldr r0, [r3, #0] + 80038bc: 683b ldr r3, [r7, #0] + 80038be: 6899 ldr r1, [r3, #8] + 80038c0: 683b ldr r3, [r7, #0] + 80038c2: 685a ldr r2, [r3, #4] + 80038c4: 683b ldr r3, [r7, #0] + 80038c6: 68db ldr r3, [r3, #12] + 80038c8: f000 fa3a bl 8003d40 + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + 80038cc: 687b ldr r3, [r7, #4] + 80038ce: 681b ldr r3, [r3, #0] + 80038d0: 689b ldr r3, [r3, #8] + 80038d2: 60bb str r3, [r7, #8] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 80038d4: 68bb ldr r3, [r7, #8] + 80038d6: 2277 movs r2, #119 ; 0x77 + 80038d8: 4313 orrs r3, r2 + 80038da: 60bb str r3, [r7, #8] + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 80038dc: 687b ldr r3, [r7, #4] + 80038de: 681b ldr r3, [r3, #0] + 80038e0: 68ba ldr r2, [r7, #8] + 80038e2: 609a str r2, [r3, #8] + break; + 80038e4: e052 b.n 800398c + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 80038e6: 687b ldr r3, [r7, #4] + 80038e8: 6818 ldr r0, [r3, #0] + 80038ea: 683b ldr r3, [r7, #0] + 80038ec: 6899 ldr r1, [r3, #8] + 80038ee: 683b ldr r3, [r7, #0] + 80038f0: 685a ldr r2, [r3, #4] + 80038f2: 683b ldr r3, [r7, #0] + 80038f4: 68db ldr r3, [r3, #12] + 80038f6: f000 fa23 bl 8003d40 + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + 80038fa: 687b ldr r3, [r7, #4] + 80038fc: 681b ldr r3, [r3, #0] + 80038fe: 689a ldr r2, [r3, #8] + 8003900: 687b ldr r3, [r7, #4] + 8003902: 681b ldr r3, [r3, #0] + 8003904: 2180 movs r1, #128 ; 0x80 + 8003906: 01c9 lsls r1, r1, #7 + 8003908: 430a orrs r2, r1 + 800390a: 609a str r2, [r3, #8] + break; + 800390c: e03e b.n 800398c + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 800390e: 687b ldr r3, [r7, #4] + 8003910: 6818 ldr r0, [r3, #0] + 8003912: 683b ldr r3, [r7, #0] + 8003914: 6859 ldr r1, [r3, #4] + 8003916: 683b ldr r3, [r7, #0] + 8003918: 68db ldr r3, [r3, #12] + 800391a: 001a movs r2, r3 + 800391c: f000 f996 bl 8003c4c + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 8003920: 687b ldr r3, [r7, #4] + 8003922: 681b ldr r3, [r3, #0] + 8003924: 2150 movs r1, #80 ; 0x50 + 8003926: 0018 movs r0, r3 + 8003928: f000 f9f0 bl 8003d0c + break; + 800392c: e02e b.n 800398c + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + 800392e: 687b ldr r3, [r7, #4] + 8003930: 6818 ldr r0, [r3, #0] + 8003932: 683b ldr r3, [r7, #0] + 8003934: 6859 ldr r1, [r3, #4] + 8003936: 683b ldr r3, [r7, #0] + 8003938: 68db ldr r3, [r3, #12] + 800393a: 001a movs r2, r3 + 800393c: f000 f9b4 bl 8003ca8 + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 8003940: 687b ldr r3, [r7, #4] + 8003942: 681b ldr r3, [r3, #0] + 8003944: 2160 movs r1, #96 ; 0x60 + 8003946: 0018 movs r0, r3 + 8003948: f000 f9e0 bl 8003d0c + break; + 800394c: e01e b.n 800398c + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 800394e: 687b ldr r3, [r7, #4] + 8003950: 6818 ldr r0, [r3, #0] + 8003952: 683b ldr r3, [r7, #0] + 8003954: 6859 ldr r1, [r3, #4] + 8003956: 683b ldr r3, [r7, #0] + 8003958: 68db ldr r3, [r3, #12] + 800395a: 001a movs r2, r3 + 800395c: f000 f976 bl 8003c4c + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 8003960: 687b ldr r3, [r7, #4] + 8003962: 681b ldr r3, [r3, #0] + 8003964: 2140 movs r1, #64 ; 0x40 + 8003966: 0018 movs r0, r3 + 8003968: f000 f9d0 bl 8003d0c + break; + 800396c: e00e b.n 800398c + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 800396e: 687b ldr r3, [r7, #4] + 8003970: 681a ldr r2, [r3, #0] + 8003972: 683b ldr r3, [r7, #0] + 8003974: 681b ldr r3, [r3, #0] + 8003976: 0019 movs r1, r3 + 8003978: 0010 movs r0, r2 + 800397a: f000 f9c7 bl 8003d0c + break; + 800397e: e005 b.n 800398c + } + + default: + status = HAL_ERROR; + 8003980: 230f movs r3, #15 + 8003982: 18fb adds r3, r7, r3 + 8003984: 2201 movs r2, #1 + 8003986: 701a strb r2, [r3, #0] + break; + 8003988: e000 b.n 800398c + break; + 800398a: 46c0 nop ; (mov r8, r8) + } + htim->State = HAL_TIM_STATE_READY; + 800398c: 687b ldr r3, [r7, #4] + 800398e: 2239 movs r2, #57 ; 0x39 + 8003990: 2101 movs r1, #1 + 8003992: 5499 strb r1, [r3, r2] + + __HAL_UNLOCK(htim); + 8003994: 687b ldr r3, [r7, #4] + 8003996: 2238 movs r2, #56 ; 0x38 + 8003998: 2100 movs r1, #0 + 800399a: 5499 strb r1, [r3, r2] + + return status; + 800399c: 230f movs r3, #15 + 800399e: 18fb adds r3, r7, r3 + 80039a0: 781b ldrb r3, [r3, #0] +} + 80039a2: 0018 movs r0, r3 + 80039a4: 46bd mov sp, r7 + 80039a6: b004 add sp, #16 + 80039a8: bd80 pop {r7, pc} + 80039aa: 46c0 nop ; (mov r8, r8) + 80039ac: ffff00ff .word 0xffff00ff + +080039b0 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + 80039b0: b580 push {r7, lr} + 80039b2: b084 sub sp, #16 + 80039b4: af00 add r7, sp, #0 + 80039b6: 6078 str r0, [r7, #4] + 80039b8: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 80039ba: 687b ldr r3, [r7, #4] + 80039bc: 681b ldr r3, [r3, #0] + 80039be: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 80039c0: 687a ldr r2, [r7, #4] + 80039c2: 2380 movs r3, #128 ; 0x80 + 80039c4: 05db lsls r3, r3, #23 + 80039c6: 429a cmp r2, r3 + 80039c8: d003 beq.n 80039d2 + 80039ca: 687b ldr r3, [r7, #4] + 80039cc: 4a1b ldr r2, [pc, #108] ; (8003a3c ) + 80039ce: 4293 cmp r3, r2 + 80039d0: d108 bne.n 80039e4 + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 80039d2: 68fb ldr r3, [r7, #12] + 80039d4: 2270 movs r2, #112 ; 0x70 + 80039d6: 4393 bics r3, r2 + 80039d8: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 80039da: 683b ldr r3, [r7, #0] + 80039dc: 685b ldr r3, [r3, #4] + 80039de: 68fa ldr r2, [r7, #12] + 80039e0: 4313 orrs r3, r2 + 80039e2: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 80039e4: 687a ldr r2, [r7, #4] + 80039e6: 2380 movs r3, #128 ; 0x80 + 80039e8: 05db lsls r3, r3, #23 + 80039ea: 429a cmp r2, r3 + 80039ec: d003 beq.n 80039f6 + 80039ee: 687b ldr r3, [r7, #4] + 80039f0: 4a12 ldr r2, [pc, #72] ; (8003a3c ) + 80039f2: 4293 cmp r3, r2 + 80039f4: d108 bne.n 8003a08 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 80039f6: 68fb ldr r3, [r7, #12] + 80039f8: 4a11 ldr r2, [pc, #68] ; (8003a40 ) + 80039fa: 4013 ands r3, r2 + 80039fc: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 80039fe: 683b ldr r3, [r7, #0] + 8003a00: 68db ldr r3, [r3, #12] + 8003a02: 68fa ldr r2, [r7, #12] + 8003a04: 4313 orrs r3, r2 + 8003a06: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8003a08: 68fb ldr r3, [r7, #12] + 8003a0a: 2280 movs r2, #128 ; 0x80 + 8003a0c: 4393 bics r3, r2 + 8003a0e: 001a movs r2, r3 + 8003a10: 683b ldr r3, [r7, #0] + 8003a12: 691b ldr r3, [r3, #16] + 8003a14: 4313 orrs r3, r2 + 8003a16: 60fb str r3, [r7, #12] + + TIMx->CR1 = tmpcr1; + 8003a18: 687b ldr r3, [r7, #4] + 8003a1a: 68fa ldr r2, [r7, #12] + 8003a1c: 601a str r2, [r3, #0] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8003a1e: 683b ldr r3, [r7, #0] + 8003a20: 689a ldr r2, [r3, #8] + 8003a22: 687b ldr r3, [r7, #4] + 8003a24: 62da str r2, [r3, #44] ; 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8003a26: 683b ldr r3, [r7, #0] + 8003a28: 681a ldr r2, [r3, #0] + 8003a2a: 687b ldr r3, [r7, #4] + 8003a2c: 629a str r2, [r3, #40] ; 0x28 + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8003a2e: 687b ldr r3, [r7, #4] + 8003a30: 2201 movs r2, #1 + 8003a32: 615a str r2, [r3, #20] +} + 8003a34: 46c0 nop ; (mov r8, r8) + 8003a36: 46bd mov sp, r7 + 8003a38: b004 add sp, #16 + 8003a3a: bd80 pop {r7, pc} + 8003a3c: 40010800 .word 0x40010800 + 8003a40: fffffcff .word 0xfffffcff + +08003a44 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8003a44: b580 push {r7, lr} + 8003a46: b086 sub sp, #24 + 8003a48: af00 add r7, sp, #0 + 8003a4a: 6078 str r0, [r7, #4] + 8003a4c: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 8003a4e: 687b ldr r3, [r7, #4] + 8003a50: 6a1b ldr r3, [r3, #32] + 8003a52: 2201 movs r2, #1 + 8003a54: 4393 bics r3, r2 + 8003a56: 001a movs r2, r3 + 8003a58: 687b ldr r3, [r7, #4] + 8003a5a: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8003a5c: 687b ldr r3, [r7, #4] + 8003a5e: 6a1b ldr r3, [r3, #32] + 8003a60: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003a62: 687b ldr r3, [r7, #4] + 8003a64: 685b ldr r3, [r3, #4] + 8003a66: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8003a68: 687b ldr r3, [r7, #4] + 8003a6a: 699b ldr r3, [r3, #24] + 8003a6c: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 8003a6e: 68fb ldr r3, [r7, #12] + 8003a70: 2270 movs r2, #112 ; 0x70 + 8003a72: 4393 bics r3, r2 + 8003a74: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 8003a76: 68fb ldr r3, [r7, #12] + 8003a78: 2203 movs r2, #3 + 8003a7a: 4393 bics r3, r2 + 8003a7c: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8003a7e: 683b ldr r3, [r7, #0] + 8003a80: 681b ldr r3, [r3, #0] + 8003a82: 68fa ldr r2, [r7, #12] + 8003a84: 4313 orrs r3, r2 + 8003a86: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 8003a88: 697b ldr r3, [r7, #20] + 8003a8a: 2202 movs r2, #2 + 8003a8c: 4393 bics r3, r2 + 8003a8e: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 8003a90: 683b ldr r3, [r7, #0] + 8003a92: 689b ldr r3, [r3, #8] + 8003a94: 697a ldr r2, [r7, #20] + 8003a96: 4313 orrs r3, r2 + 8003a98: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8003a9a: 687b ldr r3, [r7, #4] + 8003a9c: 693a ldr r2, [r7, #16] + 8003a9e: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8003aa0: 687b ldr r3, [r7, #4] + 8003aa2: 68fa ldr r2, [r7, #12] + 8003aa4: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 8003aa6: 683b ldr r3, [r7, #0] + 8003aa8: 685a ldr r2, [r3, #4] + 8003aaa: 687b ldr r3, [r7, #4] + 8003aac: 635a str r2, [r3, #52] ; 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8003aae: 687b ldr r3, [r7, #4] + 8003ab0: 697a ldr r2, [r7, #20] + 8003ab2: 621a str r2, [r3, #32] +} + 8003ab4: 46c0 nop ; (mov r8, r8) + 8003ab6: 46bd mov sp, r7 + 8003ab8: b006 add sp, #24 + 8003aba: bd80 pop {r7, pc} + +08003abc : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8003abc: b580 push {r7, lr} + 8003abe: b086 sub sp, #24 + 8003ac0: af00 add r7, sp, #0 + 8003ac2: 6078 str r0, [r7, #4] + 8003ac4: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8003ac6: 687b ldr r3, [r7, #4] + 8003ac8: 6a1b ldr r3, [r3, #32] + 8003aca: 2210 movs r2, #16 + 8003acc: 4393 bics r3, r2 + 8003ace: 001a movs r2, r3 + 8003ad0: 687b ldr r3, [r7, #4] + 8003ad2: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8003ad4: 687b ldr r3, [r7, #4] + 8003ad6: 6a1b ldr r3, [r3, #32] + 8003ad8: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003ada: 687b ldr r3, [r7, #4] + 8003adc: 685b ldr r3, [r3, #4] + 8003ade: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8003ae0: 687b ldr r3, [r7, #4] + 8003ae2: 699b ldr r3, [r3, #24] + 8003ae4: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 8003ae6: 68fb ldr r3, [r7, #12] + 8003ae8: 4a13 ldr r2, [pc, #76] ; (8003b38 ) + 8003aea: 4013 ands r3, r2 + 8003aec: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8003aee: 68fb ldr r3, [r7, #12] + 8003af0: 4a12 ldr r2, [pc, #72] ; (8003b3c ) + 8003af2: 4013 ands r3, r2 + 8003af4: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8003af6: 683b ldr r3, [r7, #0] + 8003af8: 681b ldr r3, [r3, #0] + 8003afa: 021b lsls r3, r3, #8 + 8003afc: 68fa ldr r2, [r7, #12] + 8003afe: 4313 orrs r3, r2 + 8003b00: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 8003b02: 697b ldr r3, [r7, #20] + 8003b04: 2220 movs r2, #32 + 8003b06: 4393 bics r3, r2 + 8003b08: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 8003b0a: 683b ldr r3, [r7, #0] + 8003b0c: 689b ldr r3, [r3, #8] + 8003b0e: 011b lsls r3, r3, #4 + 8003b10: 697a ldr r2, [r7, #20] + 8003b12: 4313 orrs r3, r2 + 8003b14: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8003b16: 687b ldr r3, [r7, #4] + 8003b18: 693a ldr r2, [r7, #16] + 8003b1a: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8003b1c: 687b ldr r3, [r7, #4] + 8003b1e: 68fa ldr r2, [r7, #12] + 8003b20: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8003b22: 683b ldr r3, [r7, #0] + 8003b24: 685a ldr r2, [r3, #4] + 8003b26: 687b ldr r3, [r7, #4] + 8003b28: 639a str r2, [r3, #56] ; 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8003b2a: 687b ldr r3, [r7, #4] + 8003b2c: 697a ldr r2, [r7, #20] + 8003b2e: 621a str r2, [r3, #32] +} + 8003b30: 46c0 nop ; (mov r8, r8) + 8003b32: 46bd mov sp, r7 + 8003b34: b006 add sp, #24 + 8003b36: bd80 pop {r7, pc} + 8003b38: ffff8fff .word 0xffff8fff + 8003b3c: fffffcff .word 0xfffffcff + +08003b40 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8003b40: b580 push {r7, lr} + 8003b42: b086 sub sp, #24 + 8003b44: af00 add r7, sp, #0 + 8003b46: 6078 str r0, [r7, #4] + 8003b48: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 8003b4a: 687b ldr r3, [r7, #4] + 8003b4c: 6a1b ldr r3, [r3, #32] + 8003b4e: 4a1a ldr r2, [pc, #104] ; (8003bb8 ) + 8003b50: 401a ands r2, r3 + 8003b52: 687b ldr r3, [r7, #4] + 8003b54: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8003b56: 687b ldr r3, [r7, #4] + 8003b58: 6a1b ldr r3, [r3, #32] + 8003b5a: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003b5c: 687b ldr r3, [r7, #4] + 8003b5e: 685b ldr r3, [r3, #4] + 8003b60: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8003b62: 687b ldr r3, [r7, #4] + 8003b64: 69db ldr r3, [r3, #28] + 8003b66: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8003b68: 68fb ldr r3, [r7, #12] + 8003b6a: 2270 movs r2, #112 ; 0x70 + 8003b6c: 4393 bics r3, r2 + 8003b6e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8003b70: 68fb ldr r3, [r7, #12] + 8003b72: 2203 movs r2, #3 + 8003b74: 4393 bics r3, r2 + 8003b76: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8003b78: 683b ldr r3, [r7, #0] + 8003b7a: 681b ldr r3, [r3, #0] + 8003b7c: 68fa ldr r2, [r7, #12] + 8003b7e: 4313 orrs r3, r2 + 8003b80: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8003b82: 697b ldr r3, [r7, #20] + 8003b84: 4a0d ldr r2, [pc, #52] ; (8003bbc ) + 8003b86: 4013 ands r3, r2 + 8003b88: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 8003b8a: 683b ldr r3, [r7, #0] + 8003b8c: 689b ldr r3, [r3, #8] + 8003b8e: 021b lsls r3, r3, #8 + 8003b90: 697a ldr r2, [r7, #20] + 8003b92: 4313 orrs r3, r2 + 8003b94: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8003b96: 687b ldr r3, [r7, #4] + 8003b98: 693a ldr r2, [r7, #16] + 8003b9a: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8003b9c: 687b ldr r3, [r7, #4] + 8003b9e: 68fa ldr r2, [r7, #12] + 8003ba0: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 8003ba2: 683b ldr r3, [r7, #0] + 8003ba4: 685a ldr r2, [r3, #4] + 8003ba6: 687b ldr r3, [r7, #4] + 8003ba8: 63da str r2, [r3, #60] ; 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8003baa: 687b ldr r3, [r7, #4] + 8003bac: 697a ldr r2, [r7, #20] + 8003bae: 621a str r2, [r3, #32] +} + 8003bb0: 46c0 nop ; (mov r8, r8) + 8003bb2: 46bd mov sp, r7 + 8003bb4: b006 add sp, #24 + 8003bb6: bd80 pop {r7, pc} + 8003bb8: fffffeff .word 0xfffffeff + 8003bbc: fffffdff .word 0xfffffdff + +08003bc0 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8003bc0: b580 push {r7, lr} + 8003bc2: b086 sub sp, #24 + 8003bc4: af00 add r7, sp, #0 + 8003bc6: 6078 str r0, [r7, #4] + 8003bc8: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8003bca: 687b ldr r3, [r7, #4] + 8003bcc: 6a1b ldr r3, [r3, #32] + 8003bce: 4a1b ldr r2, [pc, #108] ; (8003c3c ) + 8003bd0: 401a ands r2, r3 + 8003bd2: 687b ldr r3, [r7, #4] + 8003bd4: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8003bd6: 687b ldr r3, [r7, #4] + 8003bd8: 6a1b ldr r3, [r3, #32] + 8003bda: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003bdc: 687b ldr r3, [r7, #4] + 8003bde: 685b ldr r3, [r3, #4] + 8003be0: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8003be2: 687b ldr r3, [r7, #4] + 8003be4: 69db ldr r3, [r3, #28] + 8003be6: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8003be8: 68fb ldr r3, [r7, #12] + 8003bea: 4a15 ldr r2, [pc, #84] ; (8003c40 ) + 8003bec: 4013 ands r3, r2 + 8003bee: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 8003bf0: 68fb ldr r3, [r7, #12] + 8003bf2: 4a14 ldr r2, [pc, #80] ; (8003c44 ) + 8003bf4: 4013 ands r3, r2 + 8003bf6: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8003bf8: 683b ldr r3, [r7, #0] + 8003bfa: 681b ldr r3, [r3, #0] + 8003bfc: 021b lsls r3, r3, #8 + 8003bfe: 68fa ldr r2, [r7, #12] + 8003c00: 4313 orrs r3, r2 + 8003c02: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8003c04: 697b ldr r3, [r7, #20] + 8003c06: 4a10 ldr r2, [pc, #64] ; (8003c48 ) + 8003c08: 4013 ands r3, r2 + 8003c0a: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8003c0c: 683b ldr r3, [r7, #0] + 8003c0e: 689b ldr r3, [r3, #8] + 8003c10: 031b lsls r3, r3, #12 + 8003c12: 697a ldr r2, [r7, #20] + 8003c14: 4313 orrs r3, r2 + 8003c16: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8003c18: 687b ldr r3, [r7, #4] + 8003c1a: 693a ldr r2, [r7, #16] + 8003c1c: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8003c1e: 687b ldr r3, [r7, #4] + 8003c20: 68fa ldr r2, [r7, #12] + 8003c22: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 8003c24: 683b ldr r3, [r7, #0] + 8003c26: 685a ldr r2, [r3, #4] + 8003c28: 687b ldr r3, [r7, #4] + 8003c2a: 641a str r2, [r3, #64] ; 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8003c2c: 687b ldr r3, [r7, #4] + 8003c2e: 697a ldr r2, [r7, #20] + 8003c30: 621a str r2, [r3, #32] +} + 8003c32: 46c0 nop ; (mov r8, r8) + 8003c34: 46bd mov sp, r7 + 8003c36: b006 add sp, #24 + 8003c38: bd80 pop {r7, pc} + 8003c3a: 46c0 nop ; (mov r8, r8) + 8003c3c: ffffefff .word 0xffffefff + 8003c40: ffff8fff .word 0xffff8fff + 8003c44: fffffcff .word 0xfffffcff + 8003c48: ffffdfff .word 0xffffdfff + +08003c4c : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8003c4c: b580 push {r7, lr} + 8003c4e: b086 sub sp, #24 + 8003c50: af00 add r7, sp, #0 + 8003c52: 60f8 str r0, [r7, #12] + 8003c54: 60b9 str r1, [r7, #8] + 8003c56: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8003c58: 68fb ldr r3, [r7, #12] + 8003c5a: 6a1b ldr r3, [r3, #32] + 8003c5c: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 8003c5e: 68fb ldr r3, [r7, #12] + 8003c60: 6a1b ldr r3, [r3, #32] + 8003c62: 2201 movs r2, #1 + 8003c64: 4393 bics r3, r2 + 8003c66: 001a movs r2, r3 + 8003c68: 68fb ldr r3, [r7, #12] + 8003c6a: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8003c6c: 68fb ldr r3, [r7, #12] + 8003c6e: 699b ldr r3, [r3, #24] + 8003c70: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 8003c72: 693b ldr r3, [r7, #16] + 8003c74: 22f0 movs r2, #240 ; 0xf0 + 8003c76: 4393 bics r3, r2 + 8003c78: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8003c7a: 687b ldr r3, [r7, #4] + 8003c7c: 011b lsls r3, r3, #4 + 8003c7e: 693a ldr r2, [r7, #16] + 8003c80: 4313 orrs r3, r2 + 8003c82: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 8003c84: 697b ldr r3, [r7, #20] + 8003c86: 220a movs r2, #10 + 8003c88: 4393 bics r3, r2 + 8003c8a: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 8003c8c: 697a ldr r2, [r7, #20] + 8003c8e: 68bb ldr r3, [r7, #8] + 8003c90: 4313 orrs r3, r2 + 8003c92: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 8003c94: 68fb ldr r3, [r7, #12] + 8003c96: 693a ldr r2, [r7, #16] + 8003c98: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8003c9a: 68fb ldr r3, [r7, #12] + 8003c9c: 697a ldr r2, [r7, #20] + 8003c9e: 621a str r2, [r3, #32] +} + 8003ca0: 46c0 nop ; (mov r8, r8) + 8003ca2: 46bd mov sp, r7 + 8003ca4: b006 add sp, #24 + 8003ca6: bd80 pop {r7, pc} + +08003ca8 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8003ca8: b580 push {r7, lr} + 8003caa: b086 sub sp, #24 + 8003cac: af00 add r7, sp, #0 + 8003cae: 60f8 str r0, [r7, #12] + 8003cb0: 60b9 str r1, [r7, #8] + 8003cb2: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8003cb4: 68fb ldr r3, [r7, #12] + 8003cb6: 6a1b ldr r3, [r3, #32] + 8003cb8: 2210 movs r2, #16 + 8003cba: 4393 bics r3, r2 + 8003cbc: 001a movs r2, r3 + 8003cbe: 68fb ldr r3, [r7, #12] + 8003cc0: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8003cc2: 68fb ldr r3, [r7, #12] + 8003cc4: 699b ldr r3, [r3, #24] + 8003cc6: 617b str r3, [r7, #20] + tmpccer = TIMx->CCER; + 8003cc8: 68fb ldr r3, [r7, #12] + 8003cca: 6a1b ldr r3, [r3, #32] + 8003ccc: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 8003cce: 697b ldr r3, [r7, #20] + 8003cd0: 4a0d ldr r2, [pc, #52] ; (8003d08 ) + 8003cd2: 4013 ands r3, r2 + 8003cd4: 617b str r3, [r7, #20] + tmpccmr1 |= (TIM_ICFilter << 12U); + 8003cd6: 687b ldr r3, [r7, #4] + 8003cd8: 031b lsls r3, r3, #12 + 8003cda: 697a ldr r2, [r7, #20] + 8003cdc: 4313 orrs r3, r2 + 8003cde: 617b str r3, [r7, #20] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 8003ce0: 693b ldr r3, [r7, #16] + 8003ce2: 22a0 movs r2, #160 ; 0xa0 + 8003ce4: 4393 bics r3, r2 + 8003ce6: 613b str r3, [r7, #16] + tmpccer |= (TIM_ICPolarity << 4U); + 8003ce8: 68bb ldr r3, [r7, #8] + 8003cea: 011b lsls r3, r3, #4 + 8003cec: 693a ldr r2, [r7, #16] + 8003cee: 4313 orrs r3, r2 + 8003cf0: 613b str r3, [r7, #16] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 8003cf2: 68fb ldr r3, [r7, #12] + 8003cf4: 697a ldr r2, [r7, #20] + 8003cf6: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8003cf8: 68fb ldr r3, [r7, #12] + 8003cfa: 693a ldr r2, [r7, #16] + 8003cfc: 621a str r2, [r3, #32] +} + 8003cfe: 46c0 nop ; (mov r8, r8) + 8003d00: 46bd mov sp, r7 + 8003d02: b006 add sp, #24 + 8003d04: bd80 pop {r7, pc} + 8003d06: 46c0 nop ; (mov r8, r8) + 8003d08: ffff0fff .word 0xffff0fff + +08003d0c : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 8003d0c: b580 push {r7, lr} + 8003d0e: b084 sub sp, #16 + 8003d10: af00 add r7, sp, #0 + 8003d12: 6078 str r0, [r7, #4] + 8003d14: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 8003d16: 687b ldr r3, [r7, #4] + 8003d18: 689b ldr r3, [r3, #8] + 8003d1a: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8003d1c: 68fb ldr r3, [r7, #12] + 8003d1e: 2270 movs r2, #112 ; 0x70 + 8003d20: 4393 bics r3, r2 + 8003d22: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8003d24: 683a ldr r2, [r7, #0] + 8003d26: 68fb ldr r3, [r7, #12] + 8003d28: 4313 orrs r3, r2 + 8003d2a: 2207 movs r2, #7 + 8003d2c: 4313 orrs r3, r2 + 8003d2e: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8003d30: 687b ldr r3, [r7, #4] + 8003d32: 68fa ldr r2, [r7, #12] + 8003d34: 609a str r2, [r3, #8] +} + 8003d36: 46c0 nop ; (mov r8, r8) + 8003d38: 46bd mov sp, r7 + 8003d3a: b004 add sp, #16 + 8003d3c: bd80 pop {r7, pc} + ... + +08003d40 : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8003d40: b580 push {r7, lr} + 8003d42: b086 sub sp, #24 + 8003d44: af00 add r7, sp, #0 + 8003d46: 60f8 str r0, [r7, #12] + 8003d48: 60b9 str r1, [r7, #8] + 8003d4a: 607a str r2, [r7, #4] + 8003d4c: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 8003d4e: 68fb ldr r3, [r7, #12] + 8003d50: 689b ldr r3, [r3, #8] + 8003d52: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8003d54: 697b ldr r3, [r7, #20] + 8003d56: 4a09 ldr r2, [pc, #36] ; (8003d7c ) + 8003d58: 4013 ands r3, r2 + 8003d5a: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8003d5c: 683b ldr r3, [r7, #0] + 8003d5e: 021a lsls r2, r3, #8 + 8003d60: 687b ldr r3, [r7, #4] + 8003d62: 431a orrs r2, r3 + 8003d64: 68bb ldr r3, [r7, #8] + 8003d66: 4313 orrs r3, r2 + 8003d68: 697a ldr r2, [r7, #20] + 8003d6a: 4313 orrs r3, r2 + 8003d6c: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8003d6e: 68fb ldr r3, [r7, #12] + 8003d70: 697a ldr r2, [r7, #20] + 8003d72: 609a str r2, [r3, #8] +} + 8003d74: 46c0 nop ; (mov r8, r8) + 8003d76: 46bd mov sp, r7 + 8003d78: b006 add sp, #24 + 8003d7a: bd80 pop {r7, pc} + 8003d7c: ffff00ff .word 0xffff00ff + +08003d80 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + 8003d80: b580 push {r7, lr} + 8003d82: b084 sub sp, #16 + 8003d84: af00 add r7, sp, #0 + 8003d86: 6078 str r0, [r7, #4] + 8003d88: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 8003d8a: 687b ldr r3, [r7, #4] + 8003d8c: 2238 movs r2, #56 ; 0x38 + 8003d8e: 5c9b ldrb r3, [r3, r2] + 8003d90: 2b01 cmp r3, #1 + 8003d92: d101 bne.n 8003d98 + 8003d94: 2302 movs r3, #2 + 8003d96: e03d b.n 8003e14 + 8003d98: 687b ldr r3, [r7, #4] + 8003d9a: 2238 movs r2, #56 ; 0x38 + 8003d9c: 2101 movs r1, #1 + 8003d9e: 5499 strb r1, [r3, r2] + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 8003da0: 687b ldr r3, [r7, #4] + 8003da2: 2239 movs r2, #57 ; 0x39 + 8003da4: 2102 movs r1, #2 + 8003da6: 5499 strb r1, [r3, r2] + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 8003da8: 687b ldr r3, [r7, #4] + 8003daa: 681b ldr r3, [r3, #0] + 8003dac: 685b ldr r3, [r3, #4] + 8003dae: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8003db0: 687b ldr r3, [r7, #4] + 8003db2: 681b ldr r3, [r3, #0] + 8003db4: 689b ldr r3, [r3, #8] + 8003db6: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8003db8: 68fb ldr r3, [r7, #12] + 8003dba: 2270 movs r2, #112 ; 0x70 + 8003dbc: 4393 bics r3, r2 + 8003dbe: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8003dc0: 683b ldr r3, [r7, #0] + 8003dc2: 681b ldr r3, [r3, #0] + 8003dc4: 68fa ldr r2, [r7, #12] + 8003dc6: 4313 orrs r3, r2 + 8003dc8: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 8003dca: 687b ldr r3, [r7, #4] + 8003dcc: 681b ldr r3, [r3, #0] + 8003dce: 68fa ldr r2, [r7, #12] + 8003dd0: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8003dd2: 687b ldr r3, [r7, #4] + 8003dd4: 681a ldr r2, [r3, #0] + 8003dd6: 2380 movs r3, #128 ; 0x80 + 8003dd8: 05db lsls r3, r3, #23 + 8003dda: 429a cmp r2, r3 + 8003ddc: d004 beq.n 8003de8 + 8003dde: 687b ldr r3, [r7, #4] + 8003de0: 681b ldr r3, [r3, #0] + 8003de2: 4a0e ldr r2, [pc, #56] ; (8003e1c ) + 8003de4: 4293 cmp r3, r2 + 8003de6: d10c bne.n 8003e02 + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 8003de8: 68bb ldr r3, [r7, #8] + 8003dea: 2280 movs r2, #128 ; 0x80 + 8003dec: 4393 bics r3, r2 + 8003dee: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8003df0: 683b ldr r3, [r7, #0] + 8003df2: 685b ldr r3, [r3, #4] + 8003df4: 68ba ldr r2, [r7, #8] + 8003df6: 4313 orrs r3, r2 + 8003df8: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8003dfa: 687b ldr r3, [r7, #4] + 8003dfc: 681b ldr r3, [r3, #0] + 8003dfe: 68ba ldr r2, [r7, #8] + 8003e00: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8003e02: 687b ldr r3, [r7, #4] + 8003e04: 2239 movs r2, #57 ; 0x39 + 8003e06: 2101 movs r1, #1 + 8003e08: 5499 strb r1, [r3, r2] + + __HAL_UNLOCK(htim); + 8003e0a: 687b ldr r3, [r7, #4] + 8003e0c: 2238 movs r2, #56 ; 0x38 + 8003e0e: 2100 movs r1, #0 + 8003e10: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8003e12: 2300 movs r3, #0 +} + 8003e14: 0018 movs r0, r3 + 8003e16: 46bd mov sp, r7 + 8003e18: b004 add sp, #16 + 8003e1a: bd80 pop {r7, pc} + 8003e1c: 40010800 .word 0x40010800 + +08003e20 : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 8003e20: b580 push {r7, lr} + 8003e22: b082 sub sp, #8 + 8003e24: af00 add r7, sp, #0 + 8003e26: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 8003e28: 687b ldr r3, [r7, #4] + 8003e2a: 2b00 cmp r3, #0 + 8003e2c: d101 bne.n 8003e32 + { + return HAL_ERROR; + 8003e2e: 2301 movs r3, #1 + 8003e30: e044 b.n 8003ebc + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 8003e32: 687b ldr r3, [r7, #4] + 8003e34: 6f9b ldr r3, [r3, #120] ; 0x78 + 8003e36: 2b00 cmp r3, #0 + 8003e38: d107 bne.n 8003e4a + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 8003e3a: 687b ldr r3, [r7, #4] + 8003e3c: 2274 movs r2, #116 ; 0x74 + 8003e3e: 2100 movs r1, #0 + 8003e40: 5499 strb r1, [r3, r2] + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 8003e42: 687b ldr r3, [r7, #4] + 8003e44: 0018 movs r0, r3 + 8003e46: f7fd fa3b bl 80012c0 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 8003e4a: 687b ldr r3, [r7, #4] + 8003e4c: 2224 movs r2, #36 ; 0x24 + 8003e4e: 679a str r2, [r3, #120] ; 0x78 + + __HAL_UART_DISABLE(huart); + 8003e50: 687b ldr r3, [r7, #4] + 8003e52: 681b ldr r3, [r3, #0] + 8003e54: 681a ldr r2, [r3, #0] + 8003e56: 687b ldr r3, [r7, #4] + 8003e58: 681b ldr r3, [r3, #0] + 8003e5a: 2101 movs r1, #1 + 8003e5c: 438a bics r2, r1 + 8003e5e: 601a str r2, [r3, #0] + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 8003e60: 687b ldr r3, [r7, #4] + 8003e62: 0018 movs r0, r3 + 8003e64: f000 fb26 bl 80044b4 + 8003e68: 0003 movs r3, r0 + 8003e6a: 2b01 cmp r3, #1 + 8003e6c: d101 bne.n 8003e72 + { + return HAL_ERROR; + 8003e6e: 2301 movs r3, #1 + 8003e70: e024 b.n 8003ebc + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 8003e72: 687b ldr r3, [r7, #4] + 8003e74: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003e76: 2b00 cmp r3, #0 + 8003e78: d003 beq.n 8003e82 + { + UART_AdvFeatureConfig(huart); + 8003e7a: 687b ldr r3, [r7, #4] + 8003e7c: 0018 movs r0, r3 + 8003e7e: f000 fd7b bl 8004978 + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 8003e82: 687b ldr r3, [r7, #4] + 8003e84: 681b ldr r3, [r3, #0] + 8003e86: 685a ldr r2, [r3, #4] + 8003e88: 687b ldr r3, [r7, #4] + 8003e8a: 681b ldr r3, [r3, #0] + 8003e8c: 490d ldr r1, [pc, #52] ; (8003ec4 ) + 8003e8e: 400a ands r2, r1 + 8003e90: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 8003e92: 687b ldr r3, [r7, #4] + 8003e94: 681b ldr r3, [r3, #0] + 8003e96: 689a ldr r2, [r3, #8] + 8003e98: 687b ldr r3, [r7, #4] + 8003e9a: 681b ldr r3, [r3, #0] + 8003e9c: 212a movs r1, #42 ; 0x2a + 8003e9e: 438a bics r2, r1 + 8003ea0: 609a str r2, [r3, #8] + + __HAL_UART_ENABLE(huart); + 8003ea2: 687b ldr r3, [r7, #4] + 8003ea4: 681b ldr r3, [r3, #0] + 8003ea6: 681a ldr r2, [r3, #0] + 8003ea8: 687b ldr r3, [r7, #4] + 8003eaa: 681b ldr r3, [r3, #0] + 8003eac: 2101 movs r1, #1 + 8003eae: 430a orrs r2, r1 + 8003eb0: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 8003eb2: 687b ldr r3, [r7, #4] + 8003eb4: 0018 movs r0, r3 + 8003eb6: f000 fe13 bl 8004ae0 + 8003eba: 0003 movs r3, r0 +} + 8003ebc: 0018 movs r0, r3 + 8003ebe: 46bd mov sp, r7 + 8003ec0: b002 add sp, #8 + 8003ec2: bd80 pop {r7, pc} + 8003ec4: ffffb7ff .word 0xffffb7ff + +08003ec8 : + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + 8003ec8: b590 push {r4, r7, lr} + 8003eca: b0ab sub sp, #172 ; 0xac + 8003ecc: af00 add r7, sp, #0 + 8003ece: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8003ed0: 687b ldr r3, [r7, #4] + 8003ed2: 681b ldr r3, [r3, #0] + 8003ed4: 69db ldr r3, [r3, #28] + 8003ed6: 22a4 movs r2, #164 ; 0xa4 + 8003ed8: 18b9 adds r1, r7, r2 + 8003eda: 600b str r3, [r1, #0] + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8003edc: 687b ldr r3, [r7, #4] + 8003ede: 681b ldr r3, [r3, #0] + 8003ee0: 681b ldr r3, [r3, #0] + 8003ee2: 20a0 movs r0, #160 ; 0xa0 + 8003ee4: 1839 adds r1, r7, r0 + 8003ee6: 600b str r3, [r1, #0] + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8003ee8: 687b ldr r3, [r7, #4] + 8003eea: 681b ldr r3, [r3, #0] + 8003eec: 689b ldr r3, [r3, #8] + 8003eee: 219c movs r1, #156 ; 0x9c + 8003ef0: 1879 adds r1, r7, r1 + 8003ef2: 600b str r3, [r1, #0] + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + 8003ef4: 0011 movs r1, r2 + 8003ef6: 18bb adds r3, r7, r2 + 8003ef8: 681b ldr r3, [r3, #0] + 8003efa: 4a99 ldr r2, [pc, #612] ; (8004160 ) + 8003efc: 4013 ands r3, r2 + 8003efe: 2298 movs r2, #152 ; 0x98 + 8003f00: 18bc adds r4, r7, r2 + 8003f02: 6023 str r3, [r4, #0] + if (errorflags == 0U) + 8003f04: 18bb adds r3, r7, r2 + 8003f06: 681b ldr r3, [r3, #0] + 8003f08: 2b00 cmp r3, #0 + 8003f0a: d114 bne.n 8003f36 + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + 8003f0c: 187b adds r3, r7, r1 + 8003f0e: 681b ldr r3, [r3, #0] + 8003f10: 2220 movs r2, #32 + 8003f12: 4013 ands r3, r2 + 8003f14: d00f beq.n 8003f36 + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 8003f16: 183b adds r3, r7, r0 + 8003f18: 681b ldr r3, [r3, #0] + 8003f1a: 2220 movs r2, #32 + 8003f1c: 4013 ands r3, r2 + 8003f1e: d00a beq.n 8003f36 + { + if (huart->RxISR != NULL) + 8003f20: 687b ldr r3, [r7, #4] + 8003f22: 6e5b ldr r3, [r3, #100] ; 0x64 + 8003f24: 2b00 cmp r3, #0 + 8003f26: d100 bne.n 8003f2a + 8003f28: e298 b.n 800445c + { + huart->RxISR(huart); + 8003f2a: 687b ldr r3, [r7, #4] + 8003f2c: 6e5b ldr r3, [r3, #100] ; 0x64 + 8003f2e: 687a ldr r2, [r7, #4] + 8003f30: 0010 movs r0, r2 + 8003f32: 4798 blx r3 + } + return; + 8003f34: e292 b.n 800445c + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + 8003f36: 2398 movs r3, #152 ; 0x98 + 8003f38: 18fb adds r3, r7, r3 + 8003f3a: 681b ldr r3, [r3, #0] + 8003f3c: 2b00 cmp r3, #0 + 8003f3e: d100 bne.n 8003f42 + 8003f40: e114 b.n 800416c + && (((cr3its & USART_CR3_EIE) != 0U) + 8003f42: 239c movs r3, #156 ; 0x9c + 8003f44: 18fb adds r3, r7, r3 + 8003f46: 681b ldr r3, [r3, #0] + 8003f48: 2201 movs r2, #1 + 8003f4a: 4013 ands r3, r2 + 8003f4c: d106 bne.n 8003f5c + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) + 8003f4e: 23a0 movs r3, #160 ; 0xa0 + 8003f50: 18fb adds r3, r7, r3 + 8003f52: 681b ldr r3, [r3, #0] + 8003f54: 4a83 ldr r2, [pc, #524] ; (8004164 ) + 8003f56: 4013 ands r3, r2 + 8003f58: d100 bne.n 8003f5c + 8003f5a: e107 b.n 800416c + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8003f5c: 23a4 movs r3, #164 ; 0xa4 + 8003f5e: 18fb adds r3, r7, r3 + 8003f60: 681b ldr r3, [r3, #0] + 8003f62: 2201 movs r2, #1 + 8003f64: 4013 ands r3, r2 + 8003f66: d012 beq.n 8003f8e + 8003f68: 23a0 movs r3, #160 ; 0xa0 + 8003f6a: 18fb adds r3, r7, r3 + 8003f6c: 681a ldr r2, [r3, #0] + 8003f6e: 2380 movs r3, #128 ; 0x80 + 8003f70: 005b lsls r3, r3, #1 + 8003f72: 4013 ands r3, r2 + 8003f74: d00b beq.n 8003f8e + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8003f76: 687b ldr r3, [r7, #4] + 8003f78: 681b ldr r3, [r3, #0] + 8003f7a: 2201 movs r2, #1 + 8003f7c: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8003f7e: 687b ldr r3, [r7, #4] + 8003f80: 2280 movs r2, #128 ; 0x80 + 8003f82: 589b ldr r3, [r3, r2] + 8003f84: 2201 movs r2, #1 + 8003f86: 431a orrs r2, r3 + 8003f88: 687b ldr r3, [r7, #4] + 8003f8a: 2180 movs r1, #128 ; 0x80 + 8003f8c: 505a str r2, [r3, r1] + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8003f8e: 23a4 movs r3, #164 ; 0xa4 + 8003f90: 18fb adds r3, r7, r3 + 8003f92: 681b ldr r3, [r3, #0] + 8003f94: 2202 movs r2, #2 + 8003f96: 4013 ands r3, r2 + 8003f98: d011 beq.n 8003fbe + 8003f9a: 239c movs r3, #156 ; 0x9c + 8003f9c: 18fb adds r3, r7, r3 + 8003f9e: 681b ldr r3, [r3, #0] + 8003fa0: 2201 movs r2, #1 + 8003fa2: 4013 ands r3, r2 + 8003fa4: d00b beq.n 8003fbe + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8003fa6: 687b ldr r3, [r7, #4] + 8003fa8: 681b ldr r3, [r3, #0] + 8003faa: 2202 movs r2, #2 + 8003fac: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8003fae: 687b ldr r3, [r7, #4] + 8003fb0: 2280 movs r2, #128 ; 0x80 + 8003fb2: 589b ldr r3, [r3, r2] + 8003fb4: 2204 movs r2, #4 + 8003fb6: 431a orrs r2, r3 + 8003fb8: 687b ldr r3, [r7, #4] + 8003fba: 2180 movs r1, #128 ; 0x80 + 8003fbc: 505a str r2, [r3, r1] + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8003fbe: 23a4 movs r3, #164 ; 0xa4 + 8003fc0: 18fb adds r3, r7, r3 + 8003fc2: 681b ldr r3, [r3, #0] + 8003fc4: 2204 movs r2, #4 + 8003fc6: 4013 ands r3, r2 + 8003fc8: d011 beq.n 8003fee + 8003fca: 239c movs r3, #156 ; 0x9c + 8003fcc: 18fb adds r3, r7, r3 + 8003fce: 681b ldr r3, [r3, #0] + 8003fd0: 2201 movs r2, #1 + 8003fd2: 4013 ands r3, r2 + 8003fd4: d00b beq.n 8003fee + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8003fd6: 687b ldr r3, [r7, #4] + 8003fd8: 681b ldr r3, [r3, #0] + 8003fda: 2204 movs r2, #4 + 8003fdc: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8003fde: 687b ldr r3, [r7, #4] + 8003fe0: 2280 movs r2, #128 ; 0x80 + 8003fe2: 589b ldr r3, [r3, r2] + 8003fe4: 2202 movs r2, #2 + 8003fe6: 431a orrs r2, r3 + 8003fe8: 687b ldr r3, [r7, #4] + 8003fea: 2180 movs r1, #128 ; 0x80 + 8003fec: 505a str r2, [r3, r1] + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + 8003fee: 23a4 movs r3, #164 ; 0xa4 + 8003ff0: 18fb adds r3, r7, r3 + 8003ff2: 681b ldr r3, [r3, #0] + 8003ff4: 2208 movs r2, #8 + 8003ff6: 4013 ands r3, r2 + 8003ff8: d017 beq.n 800402a + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 8003ffa: 23a0 movs r3, #160 ; 0xa0 + 8003ffc: 18fb adds r3, r7, r3 + 8003ffe: 681b ldr r3, [r3, #0] + 8004000: 2220 movs r2, #32 + 8004002: 4013 ands r3, r2 + 8004004: d105 bne.n 8004012 + ((cr3its & USART_CR3_EIE) != 0U))) + 8004006: 239c movs r3, #156 ; 0x9c + 8004008: 18fb adds r3, r7, r3 + 800400a: 681b ldr r3, [r3, #0] + 800400c: 2201 movs r2, #1 + 800400e: 4013 ands r3, r2 + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 8004010: d00b beq.n 800402a + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 8004012: 687b ldr r3, [r7, #4] + 8004014: 681b ldr r3, [r3, #0] + 8004016: 2208 movs r2, #8 + 8004018: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + 800401a: 687b ldr r3, [r7, #4] + 800401c: 2280 movs r2, #128 ; 0x80 + 800401e: 589b ldr r3, [r3, r2] + 8004020: 2208 movs r2, #8 + 8004022: 431a orrs r2, r3 + 8004024: 687b ldr r3, [r7, #4] + 8004026: 2180 movs r1, #128 ; 0x80 + 8004028: 505a str r2, [r3, r1] + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + 800402a: 23a4 movs r3, #164 ; 0xa4 + 800402c: 18fb adds r3, r7, r3 + 800402e: 681a ldr r2, [r3, #0] + 8004030: 2380 movs r3, #128 ; 0x80 + 8004032: 011b lsls r3, r3, #4 + 8004034: 4013 ands r3, r2 + 8004036: d013 beq.n 8004060 + 8004038: 23a0 movs r3, #160 ; 0xa0 + 800403a: 18fb adds r3, r7, r3 + 800403c: 681a ldr r2, [r3, #0] + 800403e: 2380 movs r3, #128 ; 0x80 + 8004040: 04db lsls r3, r3, #19 + 8004042: 4013 ands r3, r2 + 8004044: d00c beq.n 8004060 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 8004046: 687b ldr r3, [r7, #4] + 8004048: 681b ldr r3, [r3, #0] + 800404a: 2280 movs r2, #128 ; 0x80 + 800404c: 0112 lsls r2, r2, #4 + 800404e: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + 8004050: 687b ldr r3, [r7, #4] + 8004052: 2280 movs r2, #128 ; 0x80 + 8004054: 589b ldr r3, [r3, r2] + 8004056: 2220 movs r2, #32 + 8004058: 431a orrs r2, r3 + 800405a: 687b ldr r3, [r7, #4] + 800405c: 2180 movs r1, #128 ; 0x80 + 800405e: 505a str r2, [r3, r1] + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8004060: 687b ldr r3, [r7, #4] + 8004062: 2280 movs r2, #128 ; 0x80 + 8004064: 589b ldr r3, [r3, r2] + 8004066: 2b00 cmp r3, #0 + 8004068: d100 bne.n 800406c + 800406a: e1f9 b.n 8004460 + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + 800406c: 23a4 movs r3, #164 ; 0xa4 + 800406e: 18fb adds r3, r7, r3 + 8004070: 681b ldr r3, [r3, #0] + 8004072: 2220 movs r2, #32 + 8004074: 4013 ands r3, r2 + 8004076: d00e beq.n 8004096 + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 8004078: 23a0 movs r3, #160 ; 0xa0 + 800407a: 18fb adds r3, r7, r3 + 800407c: 681b ldr r3, [r3, #0] + 800407e: 2220 movs r2, #32 + 8004080: 4013 ands r3, r2 + 8004082: d008 beq.n 8004096 + { + if (huart->RxISR != NULL) + 8004084: 687b ldr r3, [r7, #4] + 8004086: 6e5b ldr r3, [r3, #100] ; 0x64 + 8004088: 2b00 cmp r3, #0 + 800408a: d004 beq.n 8004096 + { + huart->RxISR(huart); + 800408c: 687b ldr r3, [r7, #4] + 800408e: 6e5b ldr r3, [r3, #100] ; 0x64 + 8004090: 687a ldr r2, [r7, #4] + 8004092: 0010 movs r0, r2 + 8004094: 4798 blx r3 + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + 8004096: 687b ldr r3, [r7, #4] + 8004098: 2280 movs r2, #128 ; 0x80 + 800409a: 589b ldr r3, [r3, r2] + 800409c: 2194 movs r1, #148 ; 0x94 + 800409e: 187a adds r2, r7, r1 + 80040a0: 6013 str r3, [r2, #0] + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 80040a2: 687b ldr r3, [r7, #4] + 80040a4: 681b ldr r3, [r3, #0] + 80040a6: 689b ldr r3, [r3, #8] + 80040a8: 2240 movs r2, #64 ; 0x40 + 80040aa: 4013 ands r3, r2 + 80040ac: 2b40 cmp r3, #64 ; 0x40 + 80040ae: d004 beq.n 80040ba + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 80040b0: 187b adds r3, r7, r1 + 80040b2: 681b ldr r3, [r3, #0] + 80040b4: 2228 movs r2, #40 ; 0x28 + 80040b6: 4013 ands r3, r2 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 80040b8: d047 beq.n 800414a + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + 80040ba: 687b ldr r3, [r7, #4] + 80040bc: 0018 movs r0, r3 + 80040be: f000 fe1b bl 8004cf8 + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 80040c2: 687b ldr r3, [r7, #4] + 80040c4: 681b ldr r3, [r3, #0] + 80040c6: 689b ldr r3, [r3, #8] + 80040c8: 2240 movs r2, #64 ; 0x40 + 80040ca: 4013 ands r3, r2 + 80040cc: 2b40 cmp r3, #64 ; 0x40 + 80040ce: d137 bne.n 8004140 + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80040d0: f3ef 8310 mrs r3, PRIMASK + 80040d4: 663b str r3, [r7, #96] ; 0x60 + return(result); + 80040d6: 6e3b ldr r3, [r7, #96] ; 0x60 + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 80040d8: 2090 movs r0, #144 ; 0x90 + 80040da: 183a adds r2, r7, r0 + 80040dc: 6013 str r3, [r2, #0] + 80040de: 2301 movs r3, #1 + 80040e0: 667b str r3, [r7, #100] ; 0x64 + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80040e2: 6e7b ldr r3, [r7, #100] ; 0x64 + 80040e4: f383 8810 msr PRIMASK, r3 +} + 80040e8: 46c0 nop ; (mov r8, r8) + 80040ea: 687b ldr r3, [r7, #4] + 80040ec: 681b ldr r3, [r3, #0] + 80040ee: 689a ldr r2, [r3, #8] + 80040f0: 687b ldr r3, [r7, #4] + 80040f2: 681b ldr r3, [r3, #0] + 80040f4: 2140 movs r1, #64 ; 0x40 + 80040f6: 438a bics r2, r1 + 80040f8: 609a str r2, [r3, #8] + 80040fa: 183b adds r3, r7, r0 + 80040fc: 681b ldr r3, [r3, #0] + 80040fe: 66bb str r3, [r7, #104] ; 0x68 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004100: 6ebb ldr r3, [r7, #104] ; 0x68 + 8004102: f383 8810 msr PRIMASK, r3 +} + 8004106: 46c0 nop ; (mov r8, r8) + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + 8004108: 687b ldr r3, [r7, #4] + 800410a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800410c: 2b00 cmp r3, #0 + 800410e: d012 beq.n 8004136 + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + 8004110: 687b ldr r3, [r7, #4] + 8004112: 6f1b ldr r3, [r3, #112] ; 0x70 + 8004114: 4a14 ldr r2, [pc, #80] ; (8004168 ) + 8004116: 639a str r2, [r3, #56] ; 0x38 + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 8004118: 687b ldr r3, [r7, #4] + 800411a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800411c: 0018 movs r0, r3 + 800411e: f7fd ff8b bl 8002038 + 8004122: 1e03 subs r3, r0, #0 + 8004124: d01a beq.n 800415c + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + 8004126: 687b ldr r3, [r7, #4] + 8004128: 6f1b ldr r3, [r3, #112] ; 0x70 + 800412a: 6b9a ldr r2, [r3, #56] ; 0x38 + 800412c: 687b ldr r3, [r7, #4] + 800412e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8004130: 0018 movs r0, r3 + 8004132: 4790 blx r2 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004134: e012 b.n 800415c +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004136: 687b ldr r3, [r7, #4] + 8004138: 0018 movs r0, r3 + 800413a: f000 f9a7 bl 800448c + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800413e: e00d b.n 800415c +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004140: 687b ldr r3, [r7, #4] + 8004142: 0018 movs r0, r3 + 8004144: f000 f9a2 bl 800448c + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004148: e008 b.n 800415c +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 800414a: 687b ldr r3, [r7, #4] + 800414c: 0018 movs r0, r3 + 800414e: f000 f99d bl 800448c +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8004152: 687b ldr r3, [r7, #4] + 8004154: 2280 movs r2, #128 ; 0x80 + 8004156: 2100 movs r1, #0 + 8004158: 5099 str r1, [r3, r2] + } + } + return; + 800415a: e181 b.n 8004460 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800415c: 46c0 nop ; (mov r8, r8) + return; + 800415e: e17f b.n 8004460 + 8004160: 0000080f .word 0x0000080f + 8004164: 04000120 .word 0x04000120 + 8004168: 08004dbd .word 0x08004dbd + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 800416c: 687b ldr r3, [r7, #4] + 800416e: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004170: 2b01 cmp r3, #1 + 8004172: d000 beq.n 8004176 + 8004174: e133 b.n 80043de + && ((isrflags & USART_ISR_IDLE) != 0U) + 8004176: 23a4 movs r3, #164 ; 0xa4 + 8004178: 18fb adds r3, r7, r3 + 800417a: 681b ldr r3, [r3, #0] + 800417c: 2210 movs r2, #16 + 800417e: 4013 ands r3, r2 + 8004180: d100 bne.n 8004184 + 8004182: e12c b.n 80043de + && ((cr1its & USART_ISR_IDLE) != 0U)) + 8004184: 23a0 movs r3, #160 ; 0xa0 + 8004186: 18fb adds r3, r7, r3 + 8004188: 681b ldr r3, [r3, #0] + 800418a: 2210 movs r2, #16 + 800418c: 4013 ands r3, r2 + 800418e: d100 bne.n 8004192 + 8004190: e125 b.n 80043de + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8004192: 687b ldr r3, [r7, #4] + 8004194: 681b ldr r3, [r3, #0] + 8004196: 2210 movs r2, #16 + 8004198: 621a str r2, [r3, #32] + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800419a: 687b ldr r3, [r7, #4] + 800419c: 681b ldr r3, [r3, #0] + 800419e: 689b ldr r3, [r3, #8] + 80041a0: 2240 movs r2, #64 ; 0x40 + 80041a2: 4013 ands r3, r2 + 80041a4: 2b40 cmp r3, #64 ; 0x40 + 80041a6: d000 beq.n 80041aa + 80041a8: e09d b.n 80042e6 + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + 80041aa: 687b ldr r3, [r7, #4] + 80041ac: 6f1b ldr r3, [r3, #112] ; 0x70 + 80041ae: 681b ldr r3, [r3, #0] + 80041b0: 685a ldr r2, [r3, #4] + 80041b2: 217e movs r1, #126 ; 0x7e + 80041b4: 187b adds r3, r7, r1 + 80041b6: 801a strh r2, [r3, #0] + if ((nb_remaining_rx_data > 0U) + 80041b8: 187b adds r3, r7, r1 + 80041ba: 881b ldrh r3, [r3, #0] + 80041bc: 2b00 cmp r3, #0 + 80041be: d100 bne.n 80041c2 + 80041c0: e150 b.n 8004464 + && (nb_remaining_rx_data < huart->RxXferSize)) + 80041c2: 687b ldr r3, [r7, #4] + 80041c4: 2258 movs r2, #88 ; 0x58 + 80041c6: 5a9b ldrh r3, [r3, r2] + 80041c8: 187a adds r2, r7, r1 + 80041ca: 8812 ldrh r2, [r2, #0] + 80041cc: 429a cmp r2, r3 + 80041ce: d300 bcc.n 80041d2 + 80041d0: e148 b.n 8004464 + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + 80041d2: 687b ldr r3, [r7, #4] + 80041d4: 187a adds r2, r7, r1 + 80041d6: 215a movs r1, #90 ; 0x5a + 80041d8: 8812 ldrh r2, [r2, #0] + 80041da: 525a strh r2, [r3, r1] + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + 80041dc: 687b ldr r3, [r7, #4] + 80041de: 6f1b ldr r3, [r3, #112] ; 0x70 + 80041e0: 681b ldr r3, [r3, #0] + 80041e2: 681b ldr r3, [r3, #0] + 80041e4: 2220 movs r2, #32 + 80041e6: 4013 ands r3, r2 + 80041e8: d16e bne.n 80042c8 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80041ea: f3ef 8310 mrs r3, PRIMASK + 80041ee: 633b str r3, [r7, #48] ; 0x30 + return(result); + 80041f0: 6b3b ldr r3, [r7, #48] ; 0x30 + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 80041f2: 67bb str r3, [r7, #120] ; 0x78 + 80041f4: 2301 movs r3, #1 + 80041f6: 637b str r3, [r7, #52] ; 0x34 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80041f8: 6b7b ldr r3, [r7, #52] ; 0x34 + 80041fa: f383 8810 msr PRIMASK, r3 +} + 80041fe: 46c0 nop ; (mov r8, r8) + 8004200: 687b ldr r3, [r7, #4] + 8004202: 681b ldr r3, [r3, #0] + 8004204: 681a ldr r2, [r3, #0] + 8004206: 687b ldr r3, [r7, #4] + 8004208: 681b ldr r3, [r3, #0] + 800420a: 499a ldr r1, [pc, #616] ; (8004474 ) + 800420c: 400a ands r2, r1 + 800420e: 601a str r2, [r3, #0] + 8004210: 6fbb ldr r3, [r7, #120] ; 0x78 + 8004212: 63bb str r3, [r7, #56] ; 0x38 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004214: 6bbb ldr r3, [r7, #56] ; 0x38 + 8004216: f383 8810 msr PRIMASK, r3 +} + 800421a: 46c0 nop ; (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800421c: f3ef 8310 mrs r3, PRIMASK + 8004220: 63fb str r3, [r7, #60] ; 0x3c + return(result); + 8004222: 6bfb ldr r3, [r7, #60] ; 0x3c + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8004224: 677b str r3, [r7, #116] ; 0x74 + 8004226: 2301 movs r3, #1 + 8004228: 643b str r3, [r7, #64] ; 0x40 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800422a: 6c3b ldr r3, [r7, #64] ; 0x40 + 800422c: f383 8810 msr PRIMASK, r3 +} + 8004230: 46c0 nop ; (mov r8, r8) + 8004232: 687b ldr r3, [r7, #4] + 8004234: 681b ldr r3, [r3, #0] + 8004236: 689a ldr r2, [r3, #8] + 8004238: 687b ldr r3, [r7, #4] + 800423a: 681b ldr r3, [r3, #0] + 800423c: 2101 movs r1, #1 + 800423e: 438a bics r2, r1 + 8004240: 609a str r2, [r3, #8] + 8004242: 6f7b ldr r3, [r7, #116] ; 0x74 + 8004244: 647b str r3, [r7, #68] ; 0x44 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004246: 6c7b ldr r3, [r7, #68] ; 0x44 + 8004248: f383 8810 msr PRIMASK, r3 +} + 800424c: 46c0 nop ; (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800424e: f3ef 8310 mrs r3, PRIMASK + 8004252: 64bb str r3, [r7, #72] ; 0x48 + return(result); + 8004254: 6cbb ldr r3, [r7, #72] ; 0x48 + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8004256: 673b str r3, [r7, #112] ; 0x70 + 8004258: 2301 movs r3, #1 + 800425a: 64fb str r3, [r7, #76] ; 0x4c + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800425c: 6cfb ldr r3, [r7, #76] ; 0x4c + 800425e: f383 8810 msr PRIMASK, r3 +} + 8004262: 46c0 nop ; (mov r8, r8) + 8004264: 687b ldr r3, [r7, #4] + 8004266: 681b ldr r3, [r3, #0] + 8004268: 689a ldr r2, [r3, #8] + 800426a: 687b ldr r3, [r7, #4] + 800426c: 681b ldr r3, [r3, #0] + 800426e: 2140 movs r1, #64 ; 0x40 + 8004270: 438a bics r2, r1 + 8004272: 609a str r2, [r3, #8] + 8004274: 6f3b ldr r3, [r7, #112] ; 0x70 + 8004276: 653b str r3, [r7, #80] ; 0x50 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004278: 6d3b ldr r3, [r7, #80] ; 0x50 + 800427a: f383 8810 msr PRIMASK, r3 +} + 800427e: 46c0 nop ; (mov r8, r8) + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8004280: 687b ldr r3, [r7, #4] + 8004282: 2220 movs r2, #32 + 8004284: 67da str r2, [r3, #124] ; 0x7c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8004286: 687b ldr r3, [r7, #4] + 8004288: 2200 movs r2, #0 + 800428a: 661a str r2, [r3, #96] ; 0x60 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800428c: f3ef 8310 mrs r3, PRIMASK + 8004290: 657b str r3, [r7, #84] ; 0x54 + return(result); + 8004292: 6d7b ldr r3, [r7, #84] ; 0x54 + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8004294: 66fb str r3, [r7, #108] ; 0x6c + 8004296: 2301 movs r3, #1 + 8004298: 65bb str r3, [r7, #88] ; 0x58 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800429a: 6dbb ldr r3, [r7, #88] ; 0x58 + 800429c: f383 8810 msr PRIMASK, r3 +} + 80042a0: 46c0 nop ; (mov r8, r8) + 80042a2: 687b ldr r3, [r7, #4] + 80042a4: 681b ldr r3, [r3, #0] + 80042a6: 681a ldr r2, [r3, #0] + 80042a8: 687b ldr r3, [r7, #4] + 80042aa: 681b ldr r3, [r3, #0] + 80042ac: 2110 movs r1, #16 + 80042ae: 438a bics r2, r1 + 80042b0: 601a str r2, [r3, #0] + 80042b2: 6efb ldr r3, [r7, #108] ; 0x6c + 80042b4: 65fb str r3, [r7, #92] ; 0x5c + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80042b6: 6dfb ldr r3, [r7, #92] ; 0x5c + 80042b8: f383 8810 msr PRIMASK, r3 +} + 80042bc: 46c0 nop ; (mov r8, r8) + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + 80042be: 687b ldr r3, [r7, #4] + 80042c0: 6f1b ldr r3, [r3, #112] ; 0x70 + 80042c2: 0018 movs r0, r3 + 80042c4: f7fd fe78 bl 8001fb8 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); + 80042c8: 687b ldr r3, [r7, #4] + 80042ca: 2258 movs r2, #88 ; 0x58 + 80042cc: 5a9a ldrh r2, [r3, r2] + 80042ce: 687b ldr r3, [r7, #4] + 80042d0: 215a movs r1, #90 ; 0x5a + 80042d2: 5a5b ldrh r3, [r3, r1] + 80042d4: b29b uxth r3, r3 + 80042d6: 1ad3 subs r3, r2, r3 + 80042d8: b29a uxth r2, r3 + 80042da: 687b ldr r3, [r7, #4] + 80042dc: 0011 movs r1, r2 + 80042de: 0018 movs r0, r3 + 80042e0: f000 f8dc bl 800449c +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + 80042e4: e0be b.n 8004464 + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + 80042e6: 687b ldr r3, [r7, #4] + 80042e8: 2258 movs r2, #88 ; 0x58 + 80042ea: 5a99 ldrh r1, [r3, r2] + 80042ec: 687b ldr r3, [r7, #4] + 80042ee: 225a movs r2, #90 ; 0x5a + 80042f0: 5a9b ldrh r3, [r3, r2] + 80042f2: b29a uxth r2, r3 + 80042f4: 208e movs r0, #142 ; 0x8e + 80042f6: 183b adds r3, r7, r0 + 80042f8: 1a8a subs r2, r1, r2 + 80042fa: 801a strh r2, [r3, #0] + if ((huart->RxXferCount > 0U) + 80042fc: 687b ldr r3, [r7, #4] + 80042fe: 225a movs r2, #90 ; 0x5a + 8004300: 5a9b ldrh r3, [r3, r2] + 8004302: b29b uxth r3, r3 + 8004304: 2b00 cmp r3, #0 + 8004306: d100 bne.n 800430a + 8004308: e0ae b.n 8004468 + && (nb_rx_data > 0U)) + 800430a: 183b adds r3, r7, r0 + 800430c: 881b ldrh r3, [r3, #0] + 800430e: 2b00 cmp r3, #0 + 8004310: d100 bne.n 8004314 + 8004312: e0a9 b.n 8004468 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004314: f3ef 8310 mrs r3, PRIMASK + 8004318: 60fb str r3, [r7, #12] + return(result); + 800431a: 68fb ldr r3, [r7, #12] + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 800431c: 2488 movs r4, #136 ; 0x88 + 800431e: 193a adds r2, r7, r4 + 8004320: 6013 str r3, [r2, #0] + 8004322: 2301 movs r3, #1 + 8004324: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004326: 693b ldr r3, [r7, #16] + 8004328: f383 8810 msr PRIMASK, r3 +} + 800432c: 46c0 nop ; (mov r8, r8) + 800432e: 687b ldr r3, [r7, #4] + 8004330: 681b ldr r3, [r3, #0] + 8004332: 681a ldr r2, [r3, #0] + 8004334: 687b ldr r3, [r7, #4] + 8004336: 681b ldr r3, [r3, #0] + 8004338: 494f ldr r1, [pc, #316] ; (8004478 ) + 800433a: 400a ands r2, r1 + 800433c: 601a str r2, [r3, #0] + 800433e: 193b adds r3, r7, r4 + 8004340: 681b ldr r3, [r3, #0] + 8004342: 617b str r3, [r7, #20] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004344: 697b ldr r3, [r7, #20] + 8004346: f383 8810 msr PRIMASK, r3 +} + 800434a: 46c0 nop ; (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800434c: f3ef 8310 mrs r3, PRIMASK + 8004350: 61bb str r3, [r7, #24] + return(result); + 8004352: 69bb ldr r3, [r7, #24] + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8004354: 2484 movs r4, #132 ; 0x84 + 8004356: 193a adds r2, r7, r4 + 8004358: 6013 str r3, [r2, #0] + 800435a: 2301 movs r3, #1 + 800435c: 61fb str r3, [r7, #28] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800435e: 69fb ldr r3, [r7, #28] + 8004360: f383 8810 msr PRIMASK, r3 +} + 8004364: 46c0 nop ; (mov r8, r8) + 8004366: 687b ldr r3, [r7, #4] + 8004368: 681b ldr r3, [r3, #0] + 800436a: 689a ldr r2, [r3, #8] + 800436c: 687b ldr r3, [r7, #4] + 800436e: 681b ldr r3, [r3, #0] + 8004370: 2101 movs r1, #1 + 8004372: 438a bics r2, r1 + 8004374: 609a str r2, [r3, #8] + 8004376: 193b adds r3, r7, r4 + 8004378: 681b ldr r3, [r3, #0] + 800437a: 623b str r3, [r7, #32] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800437c: 6a3b ldr r3, [r7, #32] + 800437e: f383 8810 msr PRIMASK, r3 +} + 8004382: 46c0 nop ; (mov r8, r8) + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8004384: 687b ldr r3, [r7, #4] + 8004386: 2220 movs r2, #32 + 8004388: 67da str r2, [r3, #124] ; 0x7c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 800438a: 687b ldr r3, [r7, #4] + 800438c: 2200 movs r2, #0 + 800438e: 661a str r2, [r3, #96] ; 0x60 + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8004390: 687b ldr r3, [r7, #4] + 8004392: 2200 movs r2, #0 + 8004394: 665a str r2, [r3, #100] ; 0x64 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004396: f3ef 8310 mrs r3, PRIMASK + 800439a: 627b str r3, [r7, #36] ; 0x24 + return(result); + 800439c: 6a7b ldr r3, [r7, #36] ; 0x24 + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 800439e: 2480 movs r4, #128 ; 0x80 + 80043a0: 193a adds r2, r7, r4 + 80043a2: 6013 str r3, [r2, #0] + 80043a4: 2301 movs r3, #1 + 80043a6: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80043a8: 6abb ldr r3, [r7, #40] ; 0x28 + 80043aa: f383 8810 msr PRIMASK, r3 +} + 80043ae: 46c0 nop ; (mov r8, r8) + 80043b0: 687b ldr r3, [r7, #4] + 80043b2: 681b ldr r3, [r3, #0] + 80043b4: 681a ldr r2, [r3, #0] + 80043b6: 687b ldr r3, [r7, #4] + 80043b8: 681b ldr r3, [r3, #0] + 80043ba: 2110 movs r1, #16 + 80043bc: 438a bics r2, r1 + 80043be: 601a str r2, [r3, #0] + 80043c0: 193b adds r3, r7, r4 + 80043c2: 681b ldr r3, [r3, #0] + 80043c4: 62fb str r3, [r7, #44] ; 0x2c + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80043c6: 6afb ldr r3, [r7, #44] ; 0x2c + 80043c8: f383 8810 msr PRIMASK, r3 +} + 80043cc: 46c0 nop ; (mov r8, r8) +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); + 80043ce: 183b adds r3, r7, r0 + 80043d0: 881a ldrh r2, [r3, #0] + 80043d2: 687b ldr r3, [r7, #4] + 80043d4: 0011 movs r1, r2 + 80043d6: 0018 movs r0, r3 + 80043d8: f000 f860 bl 800449c +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + 80043dc: e044 b.n 8004468 + } + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + 80043de: 23a4 movs r3, #164 ; 0xa4 + 80043e0: 18fb adds r3, r7, r3 + 80043e2: 681a ldr r2, [r3, #0] + 80043e4: 2380 movs r3, #128 ; 0x80 + 80043e6: 035b lsls r3, r3, #13 + 80043e8: 4013 ands r3, r2 + 80043ea: d010 beq.n 800440e + 80043ec: 239c movs r3, #156 ; 0x9c + 80043ee: 18fb adds r3, r7, r3 + 80043f0: 681a ldr r2, [r3, #0] + 80043f2: 2380 movs r3, #128 ; 0x80 + 80043f4: 03db lsls r3, r3, #15 + 80043f6: 4013 ands r3, r2 + 80043f8: d009 beq.n 800440e + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + 80043fa: 687b ldr r3, [r7, #4] + 80043fc: 681b ldr r3, [r3, #0] + 80043fe: 2280 movs r2, #128 ; 0x80 + 8004400: 0352 lsls r2, r2, #13 + 8004402: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); + 8004404: 687b ldr r3, [r7, #4] + 8004406: 0018 movs r0, r3 + 8004408: f000 fd1a bl 8004e40 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 800440c: e02f b.n 800446e + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + 800440e: 23a4 movs r3, #164 ; 0xa4 + 8004410: 18fb adds r3, r7, r3 + 8004412: 681b ldr r3, [r3, #0] + 8004414: 2280 movs r2, #128 ; 0x80 + 8004416: 4013 ands r3, r2 + 8004418: d00f beq.n 800443a + && ((cr1its & USART_CR1_TXEIE) != 0U)) + 800441a: 23a0 movs r3, #160 ; 0xa0 + 800441c: 18fb adds r3, r7, r3 + 800441e: 681b ldr r3, [r3, #0] + 8004420: 2280 movs r2, #128 ; 0x80 + 8004422: 4013 ands r3, r2 + 8004424: d009 beq.n 800443a + { + if (huart->TxISR != NULL) + 8004426: 687b ldr r3, [r7, #4] + 8004428: 6e9b ldr r3, [r3, #104] ; 0x68 + 800442a: 2b00 cmp r3, #0 + 800442c: d01e beq.n 800446c + { + huart->TxISR(huart); + 800442e: 687b ldr r3, [r7, #4] + 8004430: 6e9b ldr r3, [r3, #104] ; 0x68 + 8004432: 687a ldr r2, [r7, #4] + 8004434: 0010 movs r0, r2 + 8004436: 4798 blx r3 + } + return; + 8004438: e018 b.n 800446c + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + 800443a: 23a4 movs r3, #164 ; 0xa4 + 800443c: 18fb adds r3, r7, r3 + 800443e: 681b ldr r3, [r3, #0] + 8004440: 2240 movs r2, #64 ; 0x40 + 8004442: 4013 ands r3, r2 + 8004444: d013 beq.n 800446e + 8004446: 23a0 movs r3, #160 ; 0xa0 + 8004448: 18fb adds r3, r7, r3 + 800444a: 681b ldr r3, [r3, #0] + 800444c: 2240 movs r2, #64 ; 0x40 + 800444e: 4013 ands r3, r2 + 8004450: d00d beq.n 800446e + { + UART_EndTransmit_IT(huart); + 8004452: 687b ldr r3, [r7, #4] + 8004454: 0018 movs r0, r3 + 8004456: f000 fcc8 bl 8004dea + return; + 800445a: e008 b.n 800446e + return; + 800445c: 46c0 nop ; (mov r8, r8) + 800445e: e006 b.n 800446e + return; + 8004460: 46c0 nop ; (mov r8, r8) + 8004462: e004 b.n 800446e + return; + 8004464: 46c0 nop ; (mov r8, r8) + 8004466: e002 b.n 800446e + return; + 8004468: 46c0 nop ; (mov r8, r8) + 800446a: e000 b.n 800446e + return; + 800446c: 46c0 nop ; (mov r8, r8) + } + +} + 800446e: 46bd mov sp, r7 + 8004470: b02b add sp, #172 ; 0xac + 8004472: bd90 pop {r4, r7, pc} + 8004474: fffffeff .word 0xfffffeff + 8004478: fffffedf .word 0xfffffedf + +0800447c : + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + 800447c: b580 push {r7, lr} + 800447e: b082 sub sp, #8 + 8004480: af00 add r7, sp, #0 + 8004482: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + 8004484: 46c0 nop ; (mov r8, r8) + 8004486: 46bd mov sp, r7 + 8004488: b002 add sp, #8 + 800448a: bd80 pop {r7, pc} + +0800448c : + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 800448c: b580 push {r7, lr} + 800448e: b082 sub sp, #8 + 8004490: af00 add r7, sp, #0 + 8004492: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + 8004494: 46c0 nop ; (mov r8, r8) + 8004496: 46bd mov sp, r7 + 8004498: b002 add sp, #8 + 800449a: bd80 pop {r7, pc} + +0800449c : + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + 800449c: b580 push {r7, lr} + 800449e: b082 sub sp, #8 + 80044a0: af00 add r7, sp, #0 + 80044a2: 6078 str r0, [r7, #4] + 80044a4: 000a movs r2, r1 + 80044a6: 1cbb adds r3, r7, #2 + 80044a8: 801a strh r2, [r3, #0] + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + 80044aa: 46c0 nop ; (mov r8, r8) + 80044ac: 46bd mov sp, r7 + 80044ae: b002 add sp, #8 + 80044b0: bd80 pop {r7, pc} + ... + +080044b4 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 80044b4: b5b0 push {r4, r5, r7, lr} + 80044b6: b08e sub sp, #56 ; 0x38 + 80044b8: af00 add r7, sp, #0 + 80044ba: 61f8 str r0, [r7, #28] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + 80044bc: 231a movs r3, #26 + 80044be: 2218 movs r2, #24 + 80044c0: 4694 mov ip, r2 + 80044c2: 44bc add ip, r7 + 80044c4: 4463 add r3, ip + 80044c6: 2200 movs r2, #0 + 80044c8: 701a strb r2, [r3, #0] + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 80044ca: 69fb ldr r3, [r7, #28] + 80044cc: 689a ldr r2, [r3, #8] + 80044ce: 69fb ldr r3, [r7, #28] + 80044d0: 691b ldr r3, [r3, #16] + 80044d2: 431a orrs r2, r3 + 80044d4: 69fb ldr r3, [r7, #28] + 80044d6: 695b ldr r3, [r3, #20] + 80044d8: 431a orrs r2, r3 + 80044da: 69fb ldr r3, [r7, #28] + 80044dc: 69db ldr r3, [r3, #28] + 80044de: 4313 orrs r3, r2 + 80044e0: 637b str r3, [r7, #52] ; 0x34 + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 80044e2: 69fb ldr r3, [r7, #28] + 80044e4: 681b ldr r3, [r3, #0] + 80044e6: 681b ldr r3, [r3, #0] + 80044e8: 4abc ldr r2, [pc, #752] ; (80047dc ) + 80044ea: 4013 ands r3, r2 + 80044ec: 0019 movs r1, r3 + 80044ee: 69fb ldr r3, [r7, #28] + 80044f0: 681b ldr r3, [r3, #0] + 80044f2: 6b7a ldr r2, [r7, #52] ; 0x34 + 80044f4: 430a orrs r2, r1 + 80044f6: 601a str r2, [r3, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 80044f8: 69fb ldr r3, [r7, #28] + 80044fa: 681b ldr r3, [r3, #0] + 80044fc: 685b ldr r3, [r3, #4] + 80044fe: 4ab8 ldr r2, [pc, #736] ; (80047e0 ) + 8004500: 4013 ands r3, r2 + 8004502: 0019 movs r1, r3 + 8004504: 69fb ldr r3, [r7, #28] + 8004506: 68da ldr r2, [r3, #12] + 8004508: 69fb ldr r3, [r7, #28] + 800450a: 681b ldr r3, [r3, #0] + 800450c: 430a orrs r2, r1 + 800450e: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8004510: 69fb ldr r3, [r7, #28] + 8004512: 699b ldr r3, [r3, #24] + 8004514: 637b str r3, [r7, #52] ; 0x34 + + if (!(UART_INSTANCE_LOWPOWER(huart))) + 8004516: 69fb ldr r3, [r7, #28] + 8004518: 681b ldr r3, [r3, #0] + 800451a: 4ab2 ldr r2, [pc, #712] ; (80047e4 ) + 800451c: 4293 cmp r3, r2 + 800451e: d004 beq.n 800452a + { + tmpreg |= huart->Init.OneBitSampling; + 8004520: 69fb ldr r3, [r7, #28] + 8004522: 6a1b ldr r3, [r3, #32] + 8004524: 6b7a ldr r2, [r7, #52] ; 0x34 + 8004526: 4313 orrs r3, r2 + 8004528: 637b str r3, [r7, #52] ; 0x34 + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 800452a: 69fb ldr r3, [r7, #28] + 800452c: 681b ldr r3, [r3, #0] + 800452e: 689b ldr r3, [r3, #8] + 8004530: 4aad ldr r2, [pc, #692] ; (80047e8 ) + 8004532: 4013 ands r3, r2 + 8004534: 0019 movs r1, r3 + 8004536: 69fb ldr r3, [r7, #28] + 8004538: 681b ldr r3, [r3, #0] + 800453a: 6b7a ldr r2, [r7, #52] ; 0x34 + 800453c: 430a orrs r2, r1 + 800453e: 609a str r2, [r3, #8] + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 8004540: 69fb ldr r3, [r7, #28] + 8004542: 681b ldr r3, [r3, #0] + 8004544: 4aa9 ldr r2, [pc, #676] ; (80047ec ) + 8004546: 4293 cmp r3, r2 + 8004548: d136 bne.n 80045b8 + 800454a: 4ba9 ldr r3, [pc, #676] ; (80047f0 ) + 800454c: 6cdb ldr r3, [r3, #76] ; 0x4c + 800454e: 220c movs r2, #12 + 8004550: 4013 ands r3, r2 + 8004552: 2b0c cmp r3, #12 + 8004554: d020 beq.n 8004598 + 8004556: d827 bhi.n 80045a8 + 8004558: 2b08 cmp r3, #8 + 800455a: d00d beq.n 8004578 + 800455c: d824 bhi.n 80045a8 + 800455e: 2b00 cmp r3, #0 + 8004560: d002 beq.n 8004568 + 8004562: 2b04 cmp r3, #4 + 8004564: d010 beq.n 8004588 + 8004566: e01f b.n 80045a8 + 8004568: 231b movs r3, #27 + 800456a: 2218 movs r2, #24 + 800456c: 4694 mov ip, r2 + 800456e: 44bc add ip, r7 + 8004570: 4463 add r3, ip + 8004572: 2200 movs r2, #0 + 8004574: 701a strb r2, [r3, #0] + 8004576: e06f b.n 8004658 + 8004578: 231b movs r3, #27 + 800457a: 2218 movs r2, #24 + 800457c: 4694 mov ip, r2 + 800457e: 44bc add ip, r7 + 8004580: 4463 add r3, ip + 8004582: 2202 movs r2, #2 + 8004584: 701a strb r2, [r3, #0] + 8004586: e067 b.n 8004658 + 8004588: 231b movs r3, #27 + 800458a: 2218 movs r2, #24 + 800458c: 4694 mov ip, r2 + 800458e: 44bc add ip, r7 + 8004590: 4463 add r3, ip + 8004592: 2204 movs r2, #4 + 8004594: 701a strb r2, [r3, #0] + 8004596: e05f b.n 8004658 + 8004598: 231b movs r3, #27 + 800459a: 2218 movs r2, #24 + 800459c: 4694 mov ip, r2 + 800459e: 44bc add ip, r7 + 80045a0: 4463 add r3, ip + 80045a2: 2208 movs r2, #8 + 80045a4: 701a strb r2, [r3, #0] + 80045a6: e057 b.n 8004658 + 80045a8: 231b movs r3, #27 + 80045aa: 2218 movs r2, #24 + 80045ac: 4694 mov ip, r2 + 80045ae: 44bc add ip, r7 + 80045b0: 4463 add r3, ip + 80045b2: 2210 movs r2, #16 + 80045b4: 701a strb r2, [r3, #0] + 80045b6: e04f b.n 8004658 + 80045b8: 69fb ldr r3, [r7, #28] + 80045ba: 681b ldr r3, [r3, #0] + 80045bc: 4a89 ldr r2, [pc, #548] ; (80047e4 ) + 80045be: 4293 cmp r3, r2 + 80045c0: d143 bne.n 800464a + 80045c2: 4b8b ldr r3, [pc, #556] ; (80047f0 ) + 80045c4: 6cda ldr r2, [r3, #76] ; 0x4c + 80045c6: 23c0 movs r3, #192 ; 0xc0 + 80045c8: 011b lsls r3, r3, #4 + 80045ca: 4013 ands r3, r2 + 80045cc: 22c0 movs r2, #192 ; 0xc0 + 80045ce: 0112 lsls r2, r2, #4 + 80045d0: 4293 cmp r3, r2 + 80045d2: d02a beq.n 800462a + 80045d4: 22c0 movs r2, #192 ; 0xc0 + 80045d6: 0112 lsls r2, r2, #4 + 80045d8: 4293 cmp r3, r2 + 80045da: d82e bhi.n 800463a + 80045dc: 2280 movs r2, #128 ; 0x80 + 80045de: 0112 lsls r2, r2, #4 + 80045e0: 4293 cmp r3, r2 + 80045e2: d012 beq.n 800460a + 80045e4: 2280 movs r2, #128 ; 0x80 + 80045e6: 0112 lsls r2, r2, #4 + 80045e8: 4293 cmp r3, r2 + 80045ea: d826 bhi.n 800463a + 80045ec: 2b00 cmp r3, #0 + 80045ee: d004 beq.n 80045fa + 80045f0: 2280 movs r2, #128 ; 0x80 + 80045f2: 00d2 lsls r2, r2, #3 + 80045f4: 4293 cmp r3, r2 + 80045f6: d010 beq.n 800461a + 80045f8: e01f b.n 800463a + 80045fa: 231b movs r3, #27 + 80045fc: 2218 movs r2, #24 + 80045fe: 4694 mov ip, r2 + 8004600: 44bc add ip, r7 + 8004602: 4463 add r3, ip + 8004604: 2200 movs r2, #0 + 8004606: 701a strb r2, [r3, #0] + 8004608: e026 b.n 8004658 + 800460a: 231b movs r3, #27 + 800460c: 2218 movs r2, #24 + 800460e: 4694 mov ip, r2 + 8004610: 44bc add ip, r7 + 8004612: 4463 add r3, ip + 8004614: 2202 movs r2, #2 + 8004616: 701a strb r2, [r3, #0] + 8004618: e01e b.n 8004658 + 800461a: 231b movs r3, #27 + 800461c: 2218 movs r2, #24 + 800461e: 4694 mov ip, r2 + 8004620: 44bc add ip, r7 + 8004622: 4463 add r3, ip + 8004624: 2204 movs r2, #4 + 8004626: 701a strb r2, [r3, #0] + 8004628: e016 b.n 8004658 + 800462a: 231b movs r3, #27 + 800462c: 2218 movs r2, #24 + 800462e: 4694 mov ip, r2 + 8004630: 44bc add ip, r7 + 8004632: 4463 add r3, ip + 8004634: 2208 movs r2, #8 + 8004636: 701a strb r2, [r3, #0] + 8004638: e00e b.n 8004658 + 800463a: 231b movs r3, #27 + 800463c: 2218 movs r2, #24 + 800463e: 4694 mov ip, r2 + 8004640: 44bc add ip, r7 + 8004642: 4463 add r3, ip + 8004644: 2210 movs r2, #16 + 8004646: 701a strb r2, [r3, #0] + 8004648: e006 b.n 8004658 + 800464a: 231b movs r3, #27 + 800464c: 2218 movs r2, #24 + 800464e: 4694 mov ip, r2 + 8004650: 44bc add ip, r7 + 8004652: 4463 add r3, ip + 8004654: 2210 movs r2, #16 + 8004656: 701a strb r2, [r3, #0] + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + 8004658: 69fb ldr r3, [r7, #28] + 800465a: 681b ldr r3, [r3, #0] + 800465c: 4a61 ldr r2, [pc, #388] ; (80047e4 ) + 800465e: 4293 cmp r3, r2 + 8004660: d000 beq.n 8004664 + 8004662: e088 b.n 8004776 + { + /* Retrieve frequency clock */ + switch (clocksource) + 8004664: 231b movs r3, #27 + 8004666: 2218 movs r2, #24 + 8004668: 4694 mov ip, r2 + 800466a: 44bc add ip, r7 + 800466c: 4463 add r3, ip + 800466e: 781b ldrb r3, [r3, #0] + 8004670: 2b08 cmp r3, #8 + 8004672: d01d beq.n 80046b0 + 8004674: dc20 bgt.n 80046b8 + 8004676: 2b04 cmp r3, #4 + 8004678: d015 beq.n 80046a6 + 800467a: dc1d bgt.n 80046b8 + 800467c: 2b00 cmp r3, #0 + 800467e: d002 beq.n 8004686 + 8004680: 2b02 cmp r3, #2 + 8004682: d005 beq.n 8004690 + 8004684: e018 b.n 80046b8 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8004686: f7fe fd7f bl 8003188 + 800468a: 0003 movs r3, r0 + 800468c: 62fb str r3, [r7, #44] ; 0x2c + break; + 800468e: e01d b.n 80046cc + case UART_CLOCKSOURCE_HSI: + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + 8004690: 4b57 ldr r3, [pc, #348] ; (80047f0 ) + 8004692: 681b ldr r3, [r3, #0] + 8004694: 2210 movs r2, #16 + 8004696: 4013 ands r3, r2 + 8004698: d002 beq.n 80046a0 + { + pclk = (uint32_t)(HSI_VALUE >> 2U); + 800469a: 4b56 ldr r3, [pc, #344] ; (80047f4 ) + 800469c: 62fb str r3, [r7, #44] ; 0x2c + } + else + { + pclk = (uint32_t) HSI_VALUE; + } + break; + 800469e: e015 b.n 80046cc + pclk = (uint32_t) HSI_VALUE; + 80046a0: 4b55 ldr r3, [pc, #340] ; (80047f8 ) + 80046a2: 62fb str r3, [r7, #44] ; 0x2c + break; + 80046a4: e012 b.n 80046cc + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 80046a6: f7fe fcbf bl 8003028 + 80046aa: 0003 movs r3, r0 + 80046ac: 62fb str r3, [r7, #44] ; 0x2c + break; + 80046ae: e00d b.n 80046cc + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 80046b0: 2380 movs r3, #128 ; 0x80 + 80046b2: 021b lsls r3, r3, #8 + 80046b4: 62fb str r3, [r7, #44] ; 0x2c + break; + 80046b6: e009 b.n 80046cc + default: + pclk = 0U; + 80046b8: 2300 movs r3, #0 + 80046ba: 62fb str r3, [r7, #44] ; 0x2c + ret = HAL_ERROR; + 80046bc: 231a movs r3, #26 + 80046be: 2218 movs r2, #24 + 80046c0: 4694 mov ip, r2 + 80046c2: 44bc add ip, r7 + 80046c4: 4463 add r3, ip + 80046c6: 2201 movs r2, #1 + 80046c8: 701a strb r2, [r3, #0] + break; + 80046ca: 46c0 nop ; (mov r8, r8) + } + + /* If proper clock source reported */ + if (pclk != 0U) + 80046cc: 6afb ldr r3, [r7, #44] ; 0x2c + 80046ce: 2b00 cmp r3, #0 + 80046d0: d100 bne.n 80046d4 + 80046d2: e139 b.n 8004948 + { + /* No Prescaler applicable */ + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((pclk < (3U * huart->Init.BaudRate)) || + 80046d4: 69fb ldr r3, [r7, #28] + 80046d6: 685a ldr r2, [r3, #4] + 80046d8: 0013 movs r3, r2 + 80046da: 005b lsls r3, r3, #1 + 80046dc: 189b adds r3, r3, r2 + 80046de: 6afa ldr r2, [r7, #44] ; 0x2c + 80046e0: 429a cmp r2, r3 + 80046e2: d305 bcc.n 80046f0 + (pclk > (4096U * huart->Init.BaudRate))) + 80046e4: 69fb ldr r3, [r7, #28] + 80046e6: 685b ldr r3, [r3, #4] + 80046e8: 031b lsls r3, r3, #12 + if ((pclk < (3U * huart->Init.BaudRate)) || + 80046ea: 6afa ldr r2, [r7, #44] ; 0x2c + 80046ec: 429a cmp r2, r3 + 80046ee: d907 bls.n 8004700 + { + ret = HAL_ERROR; + 80046f0: 231a movs r3, #26 + 80046f2: 2218 movs r2, #24 + 80046f4: 4694 mov ip, r2 + 80046f6: 44bc add ip, r7 + 80046f8: 4463 add r3, ip + 80046fa: 2201 movs r2, #1 + 80046fc: 701a strb r2, [r3, #0] + 80046fe: e123 b.n 8004948 + } + else + { + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate)); + 8004700: 6afb ldr r3, [r7, #44] ; 0x2c + 8004702: 613b str r3, [r7, #16] + 8004704: 2300 movs r3, #0 + 8004706: 617b str r3, [r7, #20] + 8004708: 6939 ldr r1, [r7, #16] + 800470a: 697a ldr r2, [r7, #20] + 800470c: 000b movs r3, r1 + 800470e: 0e1b lsrs r3, r3, #24 + 8004710: 0010 movs r0, r2 + 8004712: 0205 lsls r5, r0, #8 + 8004714: 431d orrs r5, r3 + 8004716: 000b movs r3, r1 + 8004718: 021c lsls r4, r3, #8 + 800471a: 69fb ldr r3, [r7, #28] + 800471c: 685b ldr r3, [r3, #4] + 800471e: 085b lsrs r3, r3, #1 + 8004720: 60bb str r3, [r7, #8] + 8004722: 2300 movs r3, #0 + 8004724: 60fb str r3, [r7, #12] + 8004726: 68b8 ldr r0, [r7, #8] + 8004728: 68f9 ldr r1, [r7, #12] + 800472a: 1900 adds r0, r0, r4 + 800472c: 4169 adcs r1, r5 + 800472e: 69fb ldr r3, [r7, #28] + 8004730: 685b ldr r3, [r3, #4] + 8004732: 603b str r3, [r7, #0] + 8004734: 2300 movs r3, #0 + 8004736: 607b str r3, [r7, #4] + 8004738: 683a ldr r2, [r7, #0] + 800473a: 687b ldr r3, [r7, #4] + 800473c: f7fb fd70 bl 8000220 <__aeabi_uldivmod> + 8004740: 0002 movs r2, r0 + 8004742: 000b movs r3, r1 + 8004744: 0013 movs r3, r2 + 8004746: 62bb str r3, [r7, #40] ; 0x28 + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + 8004748: 6aba ldr r2, [r7, #40] ; 0x28 + 800474a: 23c0 movs r3, #192 ; 0xc0 + 800474c: 009b lsls r3, r3, #2 + 800474e: 429a cmp r2, r3 + 8004750: d309 bcc.n 8004766 + 8004752: 6aba ldr r2, [r7, #40] ; 0x28 + 8004754: 2380 movs r3, #128 ; 0x80 + 8004756: 035b lsls r3, r3, #13 + 8004758: 429a cmp r2, r3 + 800475a: d204 bcs.n 8004766 + { + huart->Instance->BRR = usartdiv; + 800475c: 69fb ldr r3, [r7, #28] + 800475e: 681b ldr r3, [r3, #0] + 8004760: 6aba ldr r2, [r7, #40] ; 0x28 + 8004762: 60da str r2, [r3, #12] + 8004764: e0f0 b.n 8004948 + } + else + { + ret = HAL_ERROR; + 8004766: 231a movs r3, #26 + 8004768: 2218 movs r2, #24 + 800476a: 4694 mov ip, r2 + 800476c: 44bc add ip, r7 + 800476e: 4463 add r3, ip + 8004770: 2201 movs r2, #1 + 8004772: 701a strb r2, [r3, #0] + 8004774: e0e8 b.n 8004948 + } + } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 8004776: 69fb ldr r3, [r7, #28] + 8004778: 69da ldr r2, [r3, #28] + 800477a: 2380 movs r3, #128 ; 0x80 + 800477c: 021b lsls r3, r3, #8 + 800477e: 429a cmp r2, r3 + 8004780: d000 beq.n 8004784 + 8004782: e087 b.n 8004894 + { + switch (clocksource) + 8004784: 231b movs r3, #27 + 8004786: 2218 movs r2, #24 + 8004788: 4694 mov ip, r2 + 800478a: 44bc add ip, r7 + 800478c: 4463 add r3, ip + 800478e: 781b ldrb r3, [r3, #0] + 8004790: 2b08 cmp r3, #8 + 8004792: d835 bhi.n 8004800 + 8004794: 009a lsls r2, r3, #2 + 8004796: 4b19 ldr r3, [pc, #100] ; (80047fc ) + 8004798: 18d3 adds r3, r2, r3 + 800479a: 681b ldr r3, [r3, #0] + 800479c: 469f mov pc, r3 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 800479e: f7fe fcf3 bl 8003188 + 80047a2: 0003 movs r3, r0 + 80047a4: 62fb str r3, [r7, #44] ; 0x2c + break; + 80047a6: e035 b.n 8004814 + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 80047a8: f7fe fd04 bl 80031b4 + 80047ac: 0003 movs r3, r0 + 80047ae: 62fb str r3, [r7, #44] ; 0x2c + break; + 80047b0: e030 b.n 8004814 + case UART_CLOCKSOURCE_HSI: + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + 80047b2: 4b0f ldr r3, [pc, #60] ; (80047f0 ) + 80047b4: 681b ldr r3, [r3, #0] + 80047b6: 2210 movs r2, #16 + 80047b8: 4013 ands r3, r2 + 80047ba: d002 beq.n 80047c2 + { + pclk = (uint32_t)(HSI_VALUE >> 2U); + 80047bc: 4b0d ldr r3, [pc, #52] ; (80047f4 ) + 80047be: 62fb str r3, [r7, #44] ; 0x2c + } + else + { + pclk = (uint32_t) HSI_VALUE; + } + break; + 80047c0: e028 b.n 8004814 + pclk = (uint32_t) HSI_VALUE; + 80047c2: 4b0d ldr r3, [pc, #52] ; (80047f8 ) + 80047c4: 62fb str r3, [r7, #44] ; 0x2c + break; + 80047c6: e025 b.n 8004814 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 80047c8: f7fe fc2e bl 8003028 + 80047cc: 0003 movs r3, r0 + 80047ce: 62fb str r3, [r7, #44] ; 0x2c + break; + 80047d0: e020 b.n 8004814 + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 80047d2: 2380 movs r3, #128 ; 0x80 + 80047d4: 021b lsls r3, r3, #8 + 80047d6: 62fb str r3, [r7, #44] ; 0x2c + break; + 80047d8: e01c b.n 8004814 + 80047da: 46c0 nop ; (mov r8, r8) + 80047dc: efff69f3 .word 0xefff69f3 + 80047e0: ffffcfff .word 0xffffcfff + 80047e4: 40004800 .word 0x40004800 + 80047e8: fffff4ff .word 0xfffff4ff + 80047ec: 40004400 .word 0x40004400 + 80047f0: 40021000 .word 0x40021000 + 80047f4: 003d0900 .word 0x003d0900 + 80047f8: 00f42400 .word 0x00f42400 + 80047fc: 080078a8 .word 0x080078a8 + default: + pclk = 0U; + 8004800: 2300 movs r3, #0 + 8004802: 62fb str r3, [r7, #44] ; 0x2c + ret = HAL_ERROR; + 8004804: 231a movs r3, #26 + 8004806: 2218 movs r2, #24 + 8004808: 4694 mov ip, r2 + 800480a: 44bc add ip, r7 + 800480c: 4463 add r3, ip + 800480e: 2201 movs r2, #1 + 8004810: 701a strb r2, [r3, #0] + break; + 8004812: 46c0 nop ; (mov r8, r8) + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + 8004814: 6afb ldr r3, [r7, #44] ; 0x2c + 8004816: 2b00 cmp r3, #0 + 8004818: d100 bne.n 800481c + 800481a: e095 b.n 8004948 + { + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + 800481c: 6afb ldr r3, [r7, #44] ; 0x2c + 800481e: 005a lsls r2, r3, #1 + 8004820: 69fb ldr r3, [r7, #28] + 8004822: 685b ldr r3, [r3, #4] + 8004824: 085b lsrs r3, r3, #1 + 8004826: 18d2 adds r2, r2, r3 + 8004828: 69fb ldr r3, [r7, #28] + 800482a: 685b ldr r3, [r3, #4] + 800482c: 0019 movs r1, r3 + 800482e: 0010 movs r0, r2 + 8004830: f7fb fc6a bl 8000108 <__udivsi3> + 8004834: 0003 movs r3, r0 + 8004836: b29b uxth r3, r3 + 8004838: 62bb str r3, [r7, #40] ; 0x28 + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 800483a: 6abb ldr r3, [r7, #40] ; 0x28 + 800483c: 2b0f cmp r3, #15 + 800483e: d921 bls.n 8004884 + 8004840: 6aba ldr r2, [r7, #40] ; 0x28 + 8004842: 2380 movs r3, #128 ; 0x80 + 8004844: 025b lsls r3, r3, #9 + 8004846: 429a cmp r2, r3 + 8004848: d21c bcs.n 8004884 + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 800484a: 6abb ldr r3, [r7, #40] ; 0x28 + 800484c: b29a uxth r2, r3 + 800484e: 200e movs r0, #14 + 8004850: 2418 movs r4, #24 + 8004852: 193b adds r3, r7, r4 + 8004854: 181b adds r3, r3, r0 + 8004856: 210f movs r1, #15 + 8004858: 438a bics r2, r1 + 800485a: 801a strh r2, [r3, #0] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 800485c: 6abb ldr r3, [r7, #40] ; 0x28 + 800485e: 085b lsrs r3, r3, #1 + 8004860: b29b uxth r3, r3 + 8004862: 2207 movs r2, #7 + 8004864: 4013 ands r3, r2 + 8004866: b299 uxth r1, r3 + 8004868: 193b adds r3, r7, r4 + 800486a: 181b adds r3, r3, r0 + 800486c: 193a adds r2, r7, r4 + 800486e: 1812 adds r2, r2, r0 + 8004870: 8812 ldrh r2, [r2, #0] + 8004872: 430a orrs r2, r1 + 8004874: 801a strh r2, [r3, #0] + huart->Instance->BRR = brrtemp; + 8004876: 69fb ldr r3, [r7, #28] + 8004878: 681b ldr r3, [r3, #0] + 800487a: 193a adds r2, r7, r4 + 800487c: 1812 adds r2, r2, r0 + 800487e: 8812 ldrh r2, [r2, #0] + 8004880: 60da str r2, [r3, #12] + 8004882: e061 b.n 8004948 + } + else + { + ret = HAL_ERROR; + 8004884: 231a movs r3, #26 + 8004886: 2218 movs r2, #24 + 8004888: 4694 mov ip, r2 + 800488a: 44bc add ip, r7 + 800488c: 4463 add r3, ip + 800488e: 2201 movs r2, #1 + 8004890: 701a strb r2, [r3, #0] + 8004892: e059 b.n 8004948 + } + } + } + else + { + switch (clocksource) + 8004894: 231b movs r3, #27 + 8004896: 2218 movs r2, #24 + 8004898: 4694 mov ip, r2 + 800489a: 44bc add ip, r7 + 800489c: 4463 add r3, ip + 800489e: 781b ldrb r3, [r3, #0] + 80048a0: 2b08 cmp r3, #8 + 80048a2: d822 bhi.n 80048ea + 80048a4: 009a lsls r2, r3, #2 + 80048a6: 4b30 ldr r3, [pc, #192] ; (8004968 ) + 80048a8: 18d3 adds r3, r2, r3 + 80048aa: 681b ldr r3, [r3, #0] + 80048ac: 469f mov pc, r3 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 80048ae: f7fe fc6b bl 8003188 + 80048b2: 0003 movs r3, r0 + 80048b4: 62fb str r3, [r7, #44] ; 0x2c + break; + 80048b6: e022 b.n 80048fe + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 80048b8: f7fe fc7c bl 80031b4 + 80048bc: 0003 movs r3, r0 + 80048be: 62fb str r3, [r7, #44] ; 0x2c + break; + 80048c0: e01d b.n 80048fe + case UART_CLOCKSOURCE_HSI: + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + 80048c2: 4b2a ldr r3, [pc, #168] ; (800496c ) + 80048c4: 681b ldr r3, [r3, #0] + 80048c6: 2210 movs r2, #16 + 80048c8: 4013 ands r3, r2 + 80048ca: d002 beq.n 80048d2 + { + pclk = (uint32_t)(HSI_VALUE >> 2U); + 80048cc: 4b28 ldr r3, [pc, #160] ; (8004970 ) + 80048ce: 62fb str r3, [r7, #44] ; 0x2c + } + else + { + pclk = (uint32_t) HSI_VALUE; + } + break; + 80048d0: e015 b.n 80048fe + pclk = (uint32_t) HSI_VALUE; + 80048d2: 4b28 ldr r3, [pc, #160] ; (8004974 ) + 80048d4: 62fb str r3, [r7, #44] ; 0x2c + break; + 80048d6: e012 b.n 80048fe + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 80048d8: f7fe fba6 bl 8003028 + 80048dc: 0003 movs r3, r0 + 80048de: 62fb str r3, [r7, #44] ; 0x2c + break; + 80048e0: e00d b.n 80048fe + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 80048e2: 2380 movs r3, #128 ; 0x80 + 80048e4: 021b lsls r3, r3, #8 + 80048e6: 62fb str r3, [r7, #44] ; 0x2c + break; + 80048e8: e009 b.n 80048fe + default: + pclk = 0U; + 80048ea: 2300 movs r3, #0 + 80048ec: 62fb str r3, [r7, #44] ; 0x2c + ret = HAL_ERROR; + 80048ee: 231a movs r3, #26 + 80048f0: 2218 movs r2, #24 + 80048f2: 4694 mov ip, r2 + 80048f4: 44bc add ip, r7 + 80048f6: 4463 add r3, ip + 80048f8: 2201 movs r2, #1 + 80048fa: 701a strb r2, [r3, #0] + break; + 80048fc: 46c0 nop ; (mov r8, r8) + } + + if (pclk != 0U) + 80048fe: 6afb ldr r3, [r7, #44] ; 0x2c + 8004900: 2b00 cmp r3, #0 + 8004902: d021 beq.n 8004948 + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + 8004904: 69fb ldr r3, [r7, #28] + 8004906: 685b ldr r3, [r3, #4] + 8004908: 085a lsrs r2, r3, #1 + 800490a: 6afb ldr r3, [r7, #44] ; 0x2c + 800490c: 18d2 adds r2, r2, r3 + 800490e: 69fb ldr r3, [r7, #28] + 8004910: 685b ldr r3, [r3, #4] + 8004912: 0019 movs r1, r3 + 8004914: 0010 movs r0, r2 + 8004916: f7fb fbf7 bl 8000108 <__udivsi3> + 800491a: 0003 movs r3, r0 + 800491c: b29b uxth r3, r3 + 800491e: 62bb str r3, [r7, #40] ; 0x28 + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8004920: 6abb ldr r3, [r7, #40] ; 0x28 + 8004922: 2b0f cmp r3, #15 + 8004924: d909 bls.n 800493a + 8004926: 6aba ldr r2, [r7, #40] ; 0x28 + 8004928: 2380 movs r3, #128 ; 0x80 + 800492a: 025b lsls r3, r3, #9 + 800492c: 429a cmp r2, r3 + 800492e: d204 bcs.n 800493a + { + huart->Instance->BRR = usartdiv; + 8004930: 69fb ldr r3, [r7, #28] + 8004932: 681b ldr r3, [r3, #0] + 8004934: 6aba ldr r2, [r7, #40] ; 0x28 + 8004936: 60da str r2, [r3, #12] + 8004938: e006 b.n 8004948 + } + else + { + ret = HAL_ERROR; + 800493a: 231a movs r3, #26 + 800493c: 2218 movs r2, #24 + 800493e: 4694 mov ip, r2 + 8004940: 44bc add ip, r7 + 8004942: 4463 add r3, ip + 8004944: 2201 movs r2, #1 + 8004946: 701a strb r2, [r3, #0] + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 8004948: 69fb ldr r3, [r7, #28] + 800494a: 2200 movs r2, #0 + 800494c: 665a str r2, [r3, #100] ; 0x64 + huart->TxISR = NULL; + 800494e: 69fb ldr r3, [r7, #28] + 8004950: 2200 movs r2, #0 + 8004952: 669a str r2, [r3, #104] ; 0x68 + + return ret; + 8004954: 231a movs r3, #26 + 8004956: 2218 movs r2, #24 + 8004958: 4694 mov ip, r2 + 800495a: 44bc add ip, r7 + 800495c: 4463 add r3, ip + 800495e: 781b ldrb r3, [r3, #0] +} + 8004960: 0018 movs r0, r3 + 8004962: 46bd mov sp, r7 + 8004964: b00e add sp, #56 ; 0x38 + 8004966: bdb0 pop {r4, r5, r7, pc} + 8004968: 080078cc .word 0x080078cc + 800496c: 40021000 .word 0x40021000 + 8004970: 003d0900 .word 0x003d0900 + 8004974: 00f42400 .word 0x00f42400 + +08004978 : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 8004978: b580 push {r7, lr} + 800497a: b082 sub sp, #8 + 800497c: af00 add r7, sp, #0 + 800497e: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 8004980: 687b ldr r3, [r7, #4] + 8004982: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004984: 2201 movs r2, #1 + 8004986: 4013 ands r3, r2 + 8004988: d00b beq.n 80049a2 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 800498a: 687b ldr r3, [r7, #4] + 800498c: 681b ldr r3, [r3, #0] + 800498e: 685b ldr r3, [r3, #4] + 8004990: 4a4a ldr r2, [pc, #296] ; (8004abc ) + 8004992: 4013 ands r3, r2 + 8004994: 0019 movs r1, r3 + 8004996: 687b ldr r3, [r7, #4] + 8004998: 6a9a ldr r2, [r3, #40] ; 0x28 + 800499a: 687b ldr r3, [r7, #4] + 800499c: 681b ldr r3, [r3, #0] + 800499e: 430a orrs r2, r1 + 80049a0: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 80049a2: 687b ldr r3, [r7, #4] + 80049a4: 6a5b ldr r3, [r3, #36] ; 0x24 + 80049a6: 2202 movs r2, #2 + 80049a8: 4013 ands r3, r2 + 80049aa: d00b beq.n 80049c4 + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 80049ac: 687b ldr r3, [r7, #4] + 80049ae: 681b ldr r3, [r3, #0] + 80049b0: 685b ldr r3, [r3, #4] + 80049b2: 4a43 ldr r2, [pc, #268] ; (8004ac0 ) + 80049b4: 4013 ands r3, r2 + 80049b6: 0019 movs r1, r3 + 80049b8: 687b ldr r3, [r7, #4] + 80049ba: 6ada ldr r2, [r3, #44] ; 0x2c + 80049bc: 687b ldr r3, [r7, #4] + 80049be: 681b ldr r3, [r3, #0] + 80049c0: 430a orrs r2, r1 + 80049c2: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 80049c4: 687b ldr r3, [r7, #4] + 80049c6: 6a5b ldr r3, [r3, #36] ; 0x24 + 80049c8: 2204 movs r2, #4 + 80049ca: 4013 ands r3, r2 + 80049cc: d00b beq.n 80049e6 + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 80049ce: 687b ldr r3, [r7, #4] + 80049d0: 681b ldr r3, [r3, #0] + 80049d2: 685b ldr r3, [r3, #4] + 80049d4: 4a3b ldr r2, [pc, #236] ; (8004ac4 ) + 80049d6: 4013 ands r3, r2 + 80049d8: 0019 movs r1, r3 + 80049da: 687b ldr r3, [r7, #4] + 80049dc: 6b1a ldr r2, [r3, #48] ; 0x30 + 80049de: 687b ldr r3, [r7, #4] + 80049e0: 681b ldr r3, [r3, #0] + 80049e2: 430a orrs r2, r1 + 80049e4: 605a str r2, [r3, #4] + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 80049e6: 687b ldr r3, [r7, #4] + 80049e8: 6a5b ldr r3, [r3, #36] ; 0x24 + 80049ea: 2208 movs r2, #8 + 80049ec: 4013 ands r3, r2 + 80049ee: d00b beq.n 8004a08 + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 80049f0: 687b ldr r3, [r7, #4] + 80049f2: 681b ldr r3, [r3, #0] + 80049f4: 685b ldr r3, [r3, #4] + 80049f6: 4a34 ldr r2, [pc, #208] ; (8004ac8 ) + 80049f8: 4013 ands r3, r2 + 80049fa: 0019 movs r1, r3 + 80049fc: 687b ldr r3, [r7, #4] + 80049fe: 6b5a ldr r2, [r3, #52] ; 0x34 + 8004a00: 687b ldr r3, [r7, #4] + 8004a02: 681b ldr r3, [r3, #0] + 8004a04: 430a orrs r2, r1 + 8004a06: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 8004a08: 687b ldr r3, [r7, #4] + 8004a0a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a0c: 2210 movs r2, #16 + 8004a0e: 4013 ands r3, r2 + 8004a10: d00b beq.n 8004a2a + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 8004a12: 687b ldr r3, [r7, #4] + 8004a14: 681b ldr r3, [r3, #0] + 8004a16: 689b ldr r3, [r3, #8] + 8004a18: 4a2c ldr r2, [pc, #176] ; (8004acc ) + 8004a1a: 4013 ands r3, r2 + 8004a1c: 0019 movs r1, r3 + 8004a1e: 687b ldr r3, [r7, #4] + 8004a20: 6b9a ldr r2, [r3, #56] ; 0x38 + 8004a22: 687b ldr r3, [r7, #4] + 8004a24: 681b ldr r3, [r3, #0] + 8004a26: 430a orrs r2, r1 + 8004a28: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 8004a2a: 687b ldr r3, [r7, #4] + 8004a2c: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a2e: 2220 movs r2, #32 + 8004a30: 4013 ands r3, r2 + 8004a32: d00b beq.n 8004a4c + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 8004a34: 687b ldr r3, [r7, #4] + 8004a36: 681b ldr r3, [r3, #0] + 8004a38: 689b ldr r3, [r3, #8] + 8004a3a: 4a25 ldr r2, [pc, #148] ; (8004ad0 ) + 8004a3c: 4013 ands r3, r2 + 8004a3e: 0019 movs r1, r3 + 8004a40: 687b ldr r3, [r7, #4] + 8004a42: 6bda ldr r2, [r3, #60] ; 0x3c + 8004a44: 687b ldr r3, [r7, #4] + 8004a46: 681b ldr r3, [r3, #0] + 8004a48: 430a orrs r2, r1 + 8004a4a: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 8004a4c: 687b ldr r3, [r7, #4] + 8004a4e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a50: 2240 movs r2, #64 ; 0x40 + 8004a52: 4013 ands r3, r2 + 8004a54: d01d beq.n 8004a92 + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 8004a56: 687b ldr r3, [r7, #4] + 8004a58: 681b ldr r3, [r3, #0] + 8004a5a: 685b ldr r3, [r3, #4] + 8004a5c: 4a1d ldr r2, [pc, #116] ; (8004ad4 ) + 8004a5e: 4013 ands r3, r2 + 8004a60: 0019 movs r1, r3 + 8004a62: 687b ldr r3, [r7, #4] + 8004a64: 6c1a ldr r2, [r3, #64] ; 0x40 + 8004a66: 687b ldr r3, [r7, #4] + 8004a68: 681b ldr r3, [r3, #0] + 8004a6a: 430a orrs r2, r1 + 8004a6c: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 8004a6e: 687b ldr r3, [r7, #4] + 8004a70: 6c1a ldr r2, [r3, #64] ; 0x40 + 8004a72: 2380 movs r3, #128 ; 0x80 + 8004a74: 035b lsls r3, r3, #13 + 8004a76: 429a cmp r2, r3 + 8004a78: d10b bne.n 8004a92 + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 8004a7a: 687b ldr r3, [r7, #4] + 8004a7c: 681b ldr r3, [r3, #0] + 8004a7e: 685b ldr r3, [r3, #4] + 8004a80: 4a15 ldr r2, [pc, #84] ; (8004ad8 ) + 8004a82: 4013 ands r3, r2 + 8004a84: 0019 movs r1, r3 + 8004a86: 687b ldr r3, [r7, #4] + 8004a88: 6c5a ldr r2, [r3, #68] ; 0x44 + 8004a8a: 687b ldr r3, [r7, #4] + 8004a8c: 681b ldr r3, [r3, #0] + 8004a8e: 430a orrs r2, r1 + 8004a90: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 8004a92: 687b ldr r3, [r7, #4] + 8004a94: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a96: 2280 movs r2, #128 ; 0x80 + 8004a98: 4013 ands r3, r2 + 8004a9a: d00b beq.n 8004ab4 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 8004a9c: 687b ldr r3, [r7, #4] + 8004a9e: 681b ldr r3, [r3, #0] + 8004aa0: 685b ldr r3, [r3, #4] + 8004aa2: 4a0e ldr r2, [pc, #56] ; (8004adc ) + 8004aa4: 4013 ands r3, r2 + 8004aa6: 0019 movs r1, r3 + 8004aa8: 687b ldr r3, [r7, #4] + 8004aaa: 6c9a ldr r2, [r3, #72] ; 0x48 + 8004aac: 687b ldr r3, [r7, #4] + 8004aae: 681b ldr r3, [r3, #0] + 8004ab0: 430a orrs r2, r1 + 8004ab2: 605a str r2, [r3, #4] + } +} + 8004ab4: 46c0 nop ; (mov r8, r8) + 8004ab6: 46bd mov sp, r7 + 8004ab8: b002 add sp, #8 + 8004aba: bd80 pop {r7, pc} + 8004abc: fffdffff .word 0xfffdffff + 8004ac0: fffeffff .word 0xfffeffff + 8004ac4: fffbffff .word 0xfffbffff + 8004ac8: ffff7fff .word 0xffff7fff + 8004acc: ffffefff .word 0xffffefff + 8004ad0: ffffdfff .word 0xffffdfff + 8004ad4: ffefffff .word 0xffefffff + 8004ad8: ff9fffff .word 0xff9fffff + 8004adc: fff7ffff .word 0xfff7ffff + +08004ae0 : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 8004ae0: b580 push {r7, lr} + 8004ae2: b086 sub sp, #24 + 8004ae4: af02 add r7, sp, #8 + 8004ae6: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8004ae8: 687b ldr r3, [r7, #4] + 8004aea: 2280 movs r2, #128 ; 0x80 + 8004aec: 2100 movs r1, #0 + 8004aee: 5099 str r1, [r3, r2] + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8004af0: f7fc fe52 bl 8001798 + 8004af4: 0003 movs r3, r0 + 8004af6: 60fb str r3, [r7, #12] + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 8004af8: 687b ldr r3, [r7, #4] + 8004afa: 681b ldr r3, [r3, #0] + 8004afc: 681b ldr r3, [r3, #0] + 8004afe: 2208 movs r2, #8 + 8004b00: 4013 ands r3, r2 + 8004b02: 2b08 cmp r3, #8 + 8004b04: d10c bne.n 8004b20 + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 8004b06: 68fb ldr r3, [r7, #12] + 8004b08: 2280 movs r2, #128 ; 0x80 + 8004b0a: 0391 lsls r1, r2, #14 + 8004b0c: 6878 ldr r0, [r7, #4] + 8004b0e: 4a17 ldr r2, [pc, #92] ; (8004b6c ) + 8004b10: 9200 str r2, [sp, #0] + 8004b12: 2200 movs r2, #0 + 8004b14: f000 f82c bl 8004b70 + 8004b18: 1e03 subs r3, r0, #0 + 8004b1a: d001 beq.n 8004b20 + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 8004b1c: 2303 movs r3, #3 + 8004b1e: e021 b.n 8004b64 + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + 8004b20: 687b ldr r3, [r7, #4] + 8004b22: 681b ldr r3, [r3, #0] + 8004b24: 681b ldr r3, [r3, #0] + 8004b26: 2204 movs r2, #4 + 8004b28: 4013 ands r3, r2 + 8004b2a: 2b04 cmp r3, #4 + 8004b2c: d10c bne.n 8004b48 + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 8004b2e: 68fb ldr r3, [r7, #12] + 8004b30: 2280 movs r2, #128 ; 0x80 + 8004b32: 03d1 lsls r1, r2, #15 + 8004b34: 6878 ldr r0, [r7, #4] + 8004b36: 4a0d ldr r2, [pc, #52] ; (8004b6c ) + 8004b38: 9200 str r2, [sp, #0] + 8004b3a: 2200 movs r2, #0 + 8004b3c: f000 f818 bl 8004b70 + 8004b40: 1e03 subs r3, r0, #0 + 8004b42: d001 beq.n 8004b48 + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 8004b44: 2303 movs r3, #3 + 8004b46: e00d b.n 8004b64 + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 8004b48: 687b ldr r3, [r7, #4] + 8004b4a: 2220 movs r2, #32 + 8004b4c: 679a str r2, [r3, #120] ; 0x78 + huart->RxState = HAL_UART_STATE_READY; + 8004b4e: 687b ldr r3, [r7, #4] + 8004b50: 2220 movs r2, #32 + 8004b52: 67da str r2, [r3, #124] ; 0x7c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8004b54: 687b ldr r3, [r7, #4] + 8004b56: 2200 movs r2, #0 + 8004b58: 661a str r2, [r3, #96] ; 0x60 + + __HAL_UNLOCK(huart); + 8004b5a: 687b ldr r3, [r7, #4] + 8004b5c: 2274 movs r2, #116 ; 0x74 + 8004b5e: 2100 movs r1, #0 + 8004b60: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8004b62: 2300 movs r3, #0 +} + 8004b64: 0018 movs r0, r3 + 8004b66: 46bd mov sp, r7 + 8004b68: b004 add sp, #16 + 8004b6a: bd80 pop {r7, pc} + 8004b6c: 01ffffff .word 0x01ffffff + +08004b70 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + 8004b70: b580 push {r7, lr} + 8004b72: b094 sub sp, #80 ; 0x50 + 8004b74: af00 add r7, sp, #0 + 8004b76: 60f8 str r0, [r7, #12] + 8004b78: 60b9 str r1, [r7, #8] + 8004b7a: 603b str r3, [r7, #0] + 8004b7c: 1dfb adds r3, r7, #7 + 8004b7e: 701a strb r2, [r3, #0] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8004b80: e0a3 b.n 8004cca + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8004b82: 6dbb ldr r3, [r7, #88] ; 0x58 + 8004b84: 3301 adds r3, #1 + 8004b86: d100 bne.n 8004b8a + 8004b88: e09f b.n 8004cca + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8004b8a: f7fc fe05 bl 8001798 + 8004b8e: 0002 movs r2, r0 + 8004b90: 683b ldr r3, [r7, #0] + 8004b92: 1ad3 subs r3, r2, r3 + 8004b94: 6dba ldr r2, [r7, #88] ; 0x58 + 8004b96: 429a cmp r2, r3 + 8004b98: d302 bcc.n 8004ba0 + 8004b9a: 6dbb ldr r3, [r7, #88] ; 0x58 + 8004b9c: 2b00 cmp r3, #0 + 8004b9e: d13d bne.n 8004c1c + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004ba0: f3ef 8310 mrs r3, PRIMASK + 8004ba4: 62bb str r3, [r7, #40] ; 0x28 + return(result); + 8004ba6: 6abb ldr r3, [r7, #40] ; 0x28 + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 8004ba8: 647b str r3, [r7, #68] ; 0x44 + 8004baa: 2301 movs r3, #1 + 8004bac: 62fb str r3, [r7, #44] ; 0x2c + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004bae: 6afb ldr r3, [r7, #44] ; 0x2c + 8004bb0: f383 8810 msr PRIMASK, r3 +} + 8004bb4: 46c0 nop ; (mov r8, r8) + 8004bb6: 68fb ldr r3, [r7, #12] + 8004bb8: 681b ldr r3, [r3, #0] + 8004bba: 681a ldr r2, [r3, #0] + 8004bbc: 68fb ldr r3, [r7, #12] + 8004bbe: 681b ldr r3, [r3, #0] + 8004bc0: 494c ldr r1, [pc, #304] ; (8004cf4 ) + 8004bc2: 400a ands r2, r1 + 8004bc4: 601a str r2, [r3, #0] + 8004bc6: 6c7b ldr r3, [r7, #68] ; 0x44 + 8004bc8: 633b str r3, [r7, #48] ; 0x30 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004bca: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004bcc: f383 8810 msr PRIMASK, r3 +} + 8004bd0: 46c0 nop ; (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004bd2: f3ef 8310 mrs r3, PRIMASK + 8004bd6: 637b str r3, [r7, #52] ; 0x34 + return(result); + 8004bd8: 6b7b ldr r3, [r7, #52] ; 0x34 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8004bda: 643b str r3, [r7, #64] ; 0x40 + 8004bdc: 2301 movs r3, #1 + 8004bde: 63bb str r3, [r7, #56] ; 0x38 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004be0: 6bbb ldr r3, [r7, #56] ; 0x38 + 8004be2: f383 8810 msr PRIMASK, r3 +} + 8004be6: 46c0 nop ; (mov r8, r8) + 8004be8: 68fb ldr r3, [r7, #12] + 8004bea: 681b ldr r3, [r3, #0] + 8004bec: 689a ldr r2, [r3, #8] + 8004bee: 68fb ldr r3, [r7, #12] + 8004bf0: 681b ldr r3, [r3, #0] + 8004bf2: 2101 movs r1, #1 + 8004bf4: 438a bics r2, r1 + 8004bf6: 609a str r2, [r3, #8] + 8004bf8: 6c3b ldr r3, [r7, #64] ; 0x40 + 8004bfa: 63fb str r3, [r7, #60] ; 0x3c + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004bfc: 6bfb ldr r3, [r7, #60] ; 0x3c + 8004bfe: f383 8810 msr PRIMASK, r3 +} + 8004c02: 46c0 nop ; (mov r8, r8) + + huart->gState = HAL_UART_STATE_READY; + 8004c04: 68fb ldr r3, [r7, #12] + 8004c06: 2220 movs r2, #32 + 8004c08: 679a str r2, [r3, #120] ; 0x78 + huart->RxState = HAL_UART_STATE_READY; + 8004c0a: 68fb ldr r3, [r7, #12] + 8004c0c: 2220 movs r2, #32 + 8004c0e: 67da str r2, [r3, #124] ; 0x7c + + __HAL_UNLOCK(huart); + 8004c10: 68fb ldr r3, [r7, #12] + 8004c12: 2274 movs r2, #116 ; 0x74 + 8004c14: 2100 movs r1, #0 + 8004c16: 5499 strb r1, [r3, r2] + + return HAL_TIMEOUT; + 8004c18: 2303 movs r3, #3 + 8004c1a: e067 b.n 8004cec + } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + 8004c1c: 68fb ldr r3, [r7, #12] + 8004c1e: 681b ldr r3, [r3, #0] + 8004c20: 681b ldr r3, [r3, #0] + 8004c22: 2204 movs r2, #4 + 8004c24: 4013 ands r3, r2 + 8004c26: d050 beq.n 8004cca + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + 8004c28: 68fb ldr r3, [r7, #12] + 8004c2a: 681b ldr r3, [r3, #0] + 8004c2c: 69da ldr r2, [r3, #28] + 8004c2e: 2380 movs r3, #128 ; 0x80 + 8004c30: 011b lsls r3, r3, #4 + 8004c32: 401a ands r2, r3 + 8004c34: 2380 movs r3, #128 ; 0x80 + 8004c36: 011b lsls r3, r3, #4 + 8004c38: 429a cmp r2, r3 + 8004c3a: d146 bne.n 8004cca + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 8004c3c: 68fb ldr r3, [r7, #12] + 8004c3e: 681b ldr r3, [r3, #0] + 8004c40: 2280 movs r2, #128 ; 0x80 + 8004c42: 0112 lsls r2, r2, #4 + 8004c44: 621a str r2, [r3, #32] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004c46: f3ef 8310 mrs r3, PRIMASK + 8004c4a: 613b str r3, [r7, #16] + return(result); + 8004c4c: 693b ldr r3, [r7, #16] + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 8004c4e: 64fb str r3, [r7, #76] ; 0x4c + 8004c50: 2301 movs r3, #1 + 8004c52: 617b str r3, [r7, #20] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004c54: 697b ldr r3, [r7, #20] + 8004c56: f383 8810 msr PRIMASK, r3 +} + 8004c5a: 46c0 nop ; (mov r8, r8) + 8004c5c: 68fb ldr r3, [r7, #12] + 8004c5e: 681b ldr r3, [r3, #0] + 8004c60: 681a ldr r2, [r3, #0] + 8004c62: 68fb ldr r3, [r7, #12] + 8004c64: 681b ldr r3, [r3, #0] + 8004c66: 4923 ldr r1, [pc, #140] ; (8004cf4 ) + 8004c68: 400a ands r2, r1 + 8004c6a: 601a str r2, [r3, #0] + 8004c6c: 6cfb ldr r3, [r7, #76] ; 0x4c + 8004c6e: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004c70: 69bb ldr r3, [r7, #24] + 8004c72: f383 8810 msr PRIMASK, r3 +} + 8004c76: 46c0 nop ; (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004c78: f3ef 8310 mrs r3, PRIMASK + 8004c7c: 61fb str r3, [r7, #28] + return(result); + 8004c7e: 69fb ldr r3, [r7, #28] + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8004c80: 64bb str r3, [r7, #72] ; 0x48 + 8004c82: 2301 movs r3, #1 + 8004c84: 623b str r3, [r7, #32] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004c86: 6a3b ldr r3, [r7, #32] + 8004c88: f383 8810 msr PRIMASK, r3 +} + 8004c8c: 46c0 nop ; (mov r8, r8) + 8004c8e: 68fb ldr r3, [r7, #12] + 8004c90: 681b ldr r3, [r3, #0] + 8004c92: 689a ldr r2, [r3, #8] + 8004c94: 68fb ldr r3, [r7, #12] + 8004c96: 681b ldr r3, [r3, #0] + 8004c98: 2101 movs r1, #1 + 8004c9a: 438a bics r2, r1 + 8004c9c: 609a str r2, [r3, #8] + 8004c9e: 6cbb ldr r3, [r7, #72] ; 0x48 + 8004ca0: 627b str r3, [r7, #36] ; 0x24 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004ca2: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004ca4: f383 8810 msr PRIMASK, r3 +} + 8004ca8: 46c0 nop ; (mov r8, r8) + + huart->gState = HAL_UART_STATE_READY; + 8004caa: 68fb ldr r3, [r7, #12] + 8004cac: 2220 movs r2, #32 + 8004cae: 679a str r2, [r3, #120] ; 0x78 + huart->RxState = HAL_UART_STATE_READY; + 8004cb0: 68fb ldr r3, [r7, #12] + 8004cb2: 2220 movs r2, #32 + 8004cb4: 67da str r2, [r3, #124] ; 0x7c + huart->ErrorCode = HAL_UART_ERROR_RTO; + 8004cb6: 68fb ldr r3, [r7, #12] + 8004cb8: 2280 movs r2, #128 ; 0x80 + 8004cba: 2120 movs r1, #32 + 8004cbc: 5099 str r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8004cbe: 68fb ldr r3, [r7, #12] + 8004cc0: 2274 movs r2, #116 ; 0x74 + 8004cc2: 2100 movs r1, #0 + 8004cc4: 5499 strb r1, [r3, r2] + + return HAL_TIMEOUT; + 8004cc6: 2303 movs r3, #3 + 8004cc8: e010 b.n 8004cec + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8004cca: 68fb ldr r3, [r7, #12] + 8004ccc: 681b ldr r3, [r3, #0] + 8004cce: 69db ldr r3, [r3, #28] + 8004cd0: 68ba ldr r2, [r7, #8] + 8004cd2: 4013 ands r3, r2 + 8004cd4: 68ba ldr r2, [r7, #8] + 8004cd6: 1ad3 subs r3, r2, r3 + 8004cd8: 425a negs r2, r3 + 8004cda: 4153 adcs r3, r2 + 8004cdc: b2db uxtb r3, r3 + 8004cde: 001a movs r2, r3 + 8004ce0: 1dfb adds r3, r7, #7 + 8004ce2: 781b ldrb r3, [r3, #0] + 8004ce4: 429a cmp r2, r3 + 8004ce6: d100 bne.n 8004cea + 8004ce8: e74b b.n 8004b82 + } + } + } + } + return HAL_OK; + 8004cea: 2300 movs r3, #0 +} + 8004cec: 0018 movs r0, r3 + 8004cee: 46bd mov sp, r7 + 8004cf0: b014 add sp, #80 ; 0x50 + 8004cf2: bd80 pop {r7, pc} + 8004cf4: fffffe5f .word 0xfffffe5f + +08004cf8 : + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + 8004cf8: b580 push {r7, lr} + 8004cfa: b08e sub sp, #56 ; 0x38 + 8004cfc: af00 add r7, sp, #0 + 8004cfe: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004d00: f3ef 8310 mrs r3, PRIMASK + 8004d04: 617b str r3, [r7, #20] + return(result); + 8004d06: 697b ldr r3, [r7, #20] + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8004d08: 637b str r3, [r7, #52] ; 0x34 + 8004d0a: 2301 movs r3, #1 + 8004d0c: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004d0e: 69bb ldr r3, [r7, #24] + 8004d10: f383 8810 msr PRIMASK, r3 +} + 8004d14: 46c0 nop ; (mov r8, r8) + 8004d16: 687b ldr r3, [r7, #4] + 8004d18: 681b ldr r3, [r3, #0] + 8004d1a: 681a ldr r2, [r3, #0] + 8004d1c: 687b ldr r3, [r7, #4] + 8004d1e: 681b ldr r3, [r3, #0] + 8004d20: 4925 ldr r1, [pc, #148] ; (8004db8 ) + 8004d22: 400a ands r2, r1 + 8004d24: 601a str r2, [r3, #0] + 8004d26: 6b7b ldr r3, [r7, #52] ; 0x34 + 8004d28: 61fb str r3, [r7, #28] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004d2a: 69fb ldr r3, [r7, #28] + 8004d2c: f383 8810 msr PRIMASK, r3 +} + 8004d30: 46c0 nop ; (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004d32: f3ef 8310 mrs r3, PRIMASK + 8004d36: 623b str r3, [r7, #32] + return(result); + 8004d38: 6a3b ldr r3, [r7, #32] + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8004d3a: 633b str r3, [r7, #48] ; 0x30 + 8004d3c: 2301 movs r3, #1 + 8004d3e: 627b str r3, [r7, #36] ; 0x24 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004d40: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004d42: f383 8810 msr PRIMASK, r3 +} + 8004d46: 46c0 nop ; (mov r8, r8) + 8004d48: 687b ldr r3, [r7, #4] + 8004d4a: 681b ldr r3, [r3, #0] + 8004d4c: 689a ldr r2, [r3, #8] + 8004d4e: 687b ldr r3, [r7, #4] + 8004d50: 681b ldr r3, [r3, #0] + 8004d52: 2101 movs r1, #1 + 8004d54: 438a bics r2, r1 + 8004d56: 609a str r2, [r3, #8] + 8004d58: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004d5a: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004d5c: 6abb ldr r3, [r7, #40] ; 0x28 + 8004d5e: f383 8810 msr PRIMASK, r3 +} + 8004d62: 46c0 nop ; (mov r8, r8) + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8004d64: 687b ldr r3, [r7, #4] + 8004d66: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004d68: 2b01 cmp r3, #1 + 8004d6a: d118 bne.n 8004d9e + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004d6c: f3ef 8310 mrs r3, PRIMASK + 8004d70: 60bb str r3, [r7, #8] + return(result); + 8004d72: 68bb ldr r3, [r7, #8] + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8004d74: 62fb str r3, [r7, #44] ; 0x2c + 8004d76: 2301 movs r3, #1 + 8004d78: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004d7a: 68fb ldr r3, [r7, #12] + 8004d7c: f383 8810 msr PRIMASK, r3 +} + 8004d80: 46c0 nop ; (mov r8, r8) + 8004d82: 687b ldr r3, [r7, #4] + 8004d84: 681b ldr r3, [r3, #0] + 8004d86: 681a ldr r2, [r3, #0] + 8004d88: 687b ldr r3, [r7, #4] + 8004d8a: 681b ldr r3, [r3, #0] + 8004d8c: 2110 movs r1, #16 + 8004d8e: 438a bics r2, r1 + 8004d90: 601a str r2, [r3, #0] + 8004d92: 6afb ldr r3, [r7, #44] ; 0x2c + 8004d94: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004d96: 693b ldr r3, [r7, #16] + 8004d98: f383 8810 msr PRIMASK, r3 +} + 8004d9c: 46c0 nop ; (mov r8, r8) + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8004d9e: 687b ldr r3, [r7, #4] + 8004da0: 2220 movs r2, #32 + 8004da2: 67da str r2, [r3, #124] ; 0x7c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8004da4: 687b ldr r3, [r7, #4] + 8004da6: 2200 movs r2, #0 + 8004da8: 661a str r2, [r3, #96] ; 0x60 + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; + 8004daa: 687b ldr r3, [r7, #4] + 8004dac: 2200 movs r2, #0 + 8004dae: 665a str r2, [r3, #100] ; 0x64 +} + 8004db0: 46c0 nop ; (mov r8, r8) + 8004db2: 46bd mov sp, r7 + 8004db4: b00e add sp, #56 ; 0x38 + 8004db6: bd80 pop {r7, pc} + 8004db8: fffffedf .word 0xfffffedf + +08004dbc : + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 8004dbc: b580 push {r7, lr} + 8004dbe: b084 sub sp, #16 + 8004dc0: af00 add r7, sp, #0 + 8004dc2: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 8004dc4: 687b ldr r3, [r7, #4] + 8004dc6: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004dc8: 60fb str r3, [r7, #12] + huart->RxXferCount = 0U; + 8004dca: 68fb ldr r3, [r7, #12] + 8004dcc: 225a movs r2, #90 ; 0x5a + 8004dce: 2100 movs r1, #0 + 8004dd0: 5299 strh r1, [r3, r2] + huart->TxXferCount = 0U; + 8004dd2: 68fb ldr r3, [r7, #12] + 8004dd4: 2252 movs r2, #82 ; 0x52 + 8004dd6: 2100 movs r1, #0 + 8004dd8: 5299 strh r1, [r3, r2] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004dda: 68fb ldr r3, [r7, #12] + 8004ddc: 0018 movs r0, r3 + 8004dde: f7ff fb55 bl 800448c +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8004de2: 46c0 nop ; (mov r8, r8) + 8004de4: 46bd mov sp, r7 + 8004de6: b004 add sp, #16 + 8004de8: bd80 pop {r7, pc} + +08004dea : + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + 8004dea: b580 push {r7, lr} + 8004dec: b086 sub sp, #24 + 8004dee: af00 add r7, sp, #0 + 8004df0: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004df2: f3ef 8310 mrs r3, PRIMASK + 8004df6: 60bb str r3, [r7, #8] + return(result); + 8004df8: 68bb ldr r3, [r7, #8] + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 8004dfa: 617b str r3, [r7, #20] + 8004dfc: 2301 movs r3, #1 + 8004dfe: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004e00: 68fb ldr r3, [r7, #12] + 8004e02: f383 8810 msr PRIMASK, r3 +} + 8004e06: 46c0 nop ; (mov r8, r8) + 8004e08: 687b ldr r3, [r7, #4] + 8004e0a: 681b ldr r3, [r3, #0] + 8004e0c: 681a ldr r2, [r3, #0] + 8004e0e: 687b ldr r3, [r7, #4] + 8004e10: 681b ldr r3, [r3, #0] + 8004e12: 2140 movs r1, #64 ; 0x40 + 8004e14: 438a bics r2, r1 + 8004e16: 601a str r2, [r3, #0] + 8004e18: 697b ldr r3, [r7, #20] + 8004e1a: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004e1c: 693b ldr r3, [r7, #16] + 8004e1e: f383 8810 msr PRIMASK, r3 +} + 8004e22: 46c0 nop ; (mov r8, r8) + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8004e24: 687b ldr r3, [r7, #4] + 8004e26: 2220 movs r2, #32 + 8004e28: 679a str r2, [r3, #120] ; 0x78 + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + 8004e2a: 687b ldr r3, [r7, #4] + 8004e2c: 2200 movs r2, #0 + 8004e2e: 669a str r2, [r3, #104] ; 0x68 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + 8004e30: 687b ldr r3, [r7, #4] + 8004e32: 0018 movs r0, r3 + 8004e34: f7ff fb22 bl 800447c +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8004e38: 46c0 nop ; (mov r8, r8) + 8004e3a: 46bd mov sp, r7 + 8004e3c: b006 add sp, #24 + 8004e3e: bd80 pop {r7, pc} + +08004e40 : + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + 8004e40: b580 push {r7, lr} + 8004e42: b082 sub sp, #8 + 8004e44: af00 add r7, sp, #0 + 8004e46: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + 8004e48: 46c0 nop ; (mov r8, r8) + 8004e4a: 46bd mov sp, r7 + 8004e4c: b002 add sp, #8 + 8004e4e: bd80 pop {r7, pc} + +08004e50 : +#endif /* SysTick */ + +/* + Setup SVC to reset value. +*/ +__STATIC_INLINE void SVC_Setup (void) { + 8004e50: b580 push {r7, lr} + 8004e52: af00 add r7, sp, #0 + * The issue was logged under:https://github.com/ARM-software/CMSIS-FreeRTOS/issues/35 + * until it is correctly fixed, the code below is commented + */ +/* NVIC_SetPriority (SVCall_IRQn, 0U); */ +#endif +} + 8004e54: 46c0 nop ; (mov r8, r8) + 8004e56: 46bd mov sp, r7 + 8004e58: bd80 pop {r7, pc} + ... + +08004e5c : + +/*---------------------------------------------------------------------------*/ + +osStatus_t osKernelInitialize (void) { + 8004e5c: b580 push {r7, lr} + 8004e5e: b084 sub sp, #16 + 8004e60: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8004e62: f3ef 8305 mrs r3, IPSR + 8004e66: 60bb str r3, [r7, #8] + return(result); + 8004e68: 68bb ldr r3, [r7, #8] + osStatus_t stat; + + if (IS_IRQ()) { + 8004e6a: 2b00 cmp r3, #0 + 8004e6c: d109 bne.n 8004e82 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004e6e: f3ef 8310 mrs r3, PRIMASK + 8004e72: 607b str r3, [r7, #4] + return(result); + 8004e74: 687b ldr r3, [r7, #4] + 8004e76: 2b00 cmp r3, #0 + 8004e78: d007 beq.n 8004e8a + 8004e7a: 4b0d ldr r3, [pc, #52] ; (8004eb0 ) + 8004e7c: 681b ldr r3, [r3, #0] + 8004e7e: 2b02 cmp r3, #2 + 8004e80: d103 bne.n 8004e8a + stat = osErrorISR; + 8004e82: 2306 movs r3, #6 + 8004e84: 425b negs r3, r3 + 8004e86: 60fb str r3, [r7, #12] + 8004e88: e00c b.n 8004ea4 + } + else { + if (KernelState == osKernelInactive) { + 8004e8a: 4b09 ldr r3, [pc, #36] ; (8004eb0 ) + 8004e8c: 681b ldr r3, [r3, #0] + 8004e8e: 2b00 cmp r3, #0 + 8004e90: d105 bne.n 8004e9e + #if defined(USE_FREERTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) + vPortDefineHeapRegions (configHEAP_5_REGIONS); + #endif + KernelState = osKernelReady; + 8004e92: 4b07 ldr r3, [pc, #28] ; (8004eb0 ) + 8004e94: 2201 movs r2, #1 + 8004e96: 601a str r2, [r3, #0] + stat = osOK; + 8004e98: 2300 movs r3, #0 + 8004e9a: 60fb str r3, [r7, #12] + 8004e9c: e002 b.n 8004ea4 + } else { + stat = osError; + 8004e9e: 2301 movs r3, #1 + 8004ea0: 425b negs r3, r3 + 8004ea2: 60fb str r3, [r7, #12] + } + } + + return (stat); + 8004ea4: 68fb ldr r3, [r7, #12] +} + 8004ea6: 0018 movs r0, r3 + 8004ea8: 46bd mov sp, r7 + 8004eaa: b004 add sp, #16 + 8004eac: bd80 pop {r7, pc} + 8004eae: 46c0 nop ; (mov r8, r8) + 8004eb0: 20000030 .word 0x20000030 + +08004eb4 : + } + + return (state); +} + +osStatus_t osKernelStart (void) { + 8004eb4: b580 push {r7, lr} + 8004eb6: b084 sub sp, #16 + 8004eb8: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8004eba: f3ef 8305 mrs r3, IPSR + 8004ebe: 60bb str r3, [r7, #8] + return(result); + 8004ec0: 68bb ldr r3, [r7, #8] + osStatus_t stat; + + if (IS_IRQ()) { + 8004ec2: 2b00 cmp r3, #0 + 8004ec4: d109 bne.n 8004eda + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004ec6: f3ef 8310 mrs r3, PRIMASK + 8004eca: 607b str r3, [r7, #4] + return(result); + 8004ecc: 687b ldr r3, [r7, #4] + 8004ece: 2b00 cmp r3, #0 + 8004ed0: d007 beq.n 8004ee2 + 8004ed2: 4b0f ldr r3, [pc, #60] ; (8004f10 ) + 8004ed4: 681b ldr r3, [r3, #0] + 8004ed6: 2b02 cmp r3, #2 + 8004ed8: d103 bne.n 8004ee2 + stat = osErrorISR; + 8004eda: 2306 movs r3, #6 + 8004edc: 425b negs r3, r3 + 8004ede: 60fb str r3, [r7, #12] + 8004ee0: e010 b.n 8004f04 + } + else { + if (KernelState == osKernelReady) { + 8004ee2: 4b0b ldr r3, [pc, #44] ; (8004f10 ) + 8004ee4: 681b ldr r3, [r3, #0] + 8004ee6: 2b01 cmp r3, #1 + 8004ee8: d109 bne.n 8004efe + /* Ensure SVC priority is at the reset value */ + SVC_Setup(); + 8004eea: f7ff ffb1 bl 8004e50 + /* Change state to enable IRQ masking check */ + KernelState = osKernelRunning; + 8004eee: 4b08 ldr r3, [pc, #32] ; (8004f10 ) + 8004ef0: 2202 movs r2, #2 + 8004ef2: 601a str r2, [r3, #0] + /* Start the kernel scheduler */ + vTaskStartScheduler(); + 8004ef4: f001 f80e bl 8005f14 + stat = osOK; + 8004ef8: 2300 movs r3, #0 + 8004efa: 60fb str r3, [r7, #12] + 8004efc: e002 b.n 8004f04 + } else { + stat = osError; + 8004efe: 2301 movs r3, #1 + 8004f00: 425b negs r3, r3 + 8004f02: 60fb str r3, [r7, #12] + } + } + + return (stat); + 8004f04: 68fb ldr r3, [r7, #12] +} + 8004f06: 0018 movs r0, r3 + 8004f08: 46bd mov sp, r7 + 8004f0a: b004 add sp, #16 + 8004f0c: bd80 pop {r7, pc} + 8004f0e: 46c0 nop ; (mov r8, r8) + 8004f10: 20000030 .word 0x20000030 + +08004f14 : + return (configCPU_CLOCK_HZ); +} + +/*---------------------------------------------------------------------------*/ + +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + 8004f14: b5b0 push {r4, r5, r7, lr} + 8004f16: b090 sub sp, #64 ; 0x40 + 8004f18: af04 add r7, sp, #16 + 8004f1a: 60f8 str r0, [r7, #12] + 8004f1c: 60b9 str r1, [r7, #8] + 8004f1e: 607a str r2, [r7, #4] + uint32_t stack; + TaskHandle_t hTask; + UBaseType_t prio; + int32_t mem; + + hTask = NULL; + 8004f20: 2300 movs r3, #0 + 8004f22: 617b str r3, [r7, #20] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8004f24: f3ef 8305 mrs r3, IPSR + 8004f28: 61fb str r3, [r7, #28] + return(result); + 8004f2a: 69fb ldr r3, [r7, #28] + + if (!IS_IRQ() && (func != NULL)) { + 8004f2c: 2b00 cmp r3, #0 + 8004f2e: d000 beq.n 8004f32 + 8004f30: e08c b.n 800504c + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8004f32: f3ef 8310 mrs r3, PRIMASK + 8004f36: 61bb str r3, [r7, #24] + return(result); + 8004f38: 69bb ldr r3, [r7, #24] + 8004f3a: 2b00 cmp r3, #0 + 8004f3c: d004 beq.n 8004f48 + 8004f3e: 4b46 ldr r3, [pc, #280] ; (8005058 ) + 8004f40: 681b ldr r3, [r3, #0] + 8004f42: 2b02 cmp r3, #2 + 8004f44: d100 bne.n 8004f48 + 8004f46: e081 b.n 800504c + 8004f48: 68fb ldr r3, [r7, #12] + 8004f4a: 2b00 cmp r3, #0 + 8004f4c: d100 bne.n 8004f50 + 8004f4e: e07d b.n 800504c + stack = configMINIMAL_STACK_SIZE; + 8004f50: 2380 movs r3, #128 ; 0x80 + 8004f52: 62bb str r3, [r7, #40] ; 0x28 + prio = (UBaseType_t)osPriorityNormal; + 8004f54: 2318 movs r3, #24 + 8004f56: 627b str r3, [r7, #36] ; 0x24 + + name = NULL; + 8004f58: 2300 movs r3, #0 + 8004f5a: 62fb str r3, [r7, #44] ; 0x2c + mem = -1; + 8004f5c: 2301 movs r3, #1 + 8004f5e: 425b negs r3, r3 + 8004f60: 623b str r3, [r7, #32] + + if (attr != NULL) { + 8004f62: 687b ldr r3, [r7, #4] + 8004f64: 2b00 cmp r3, #0 + 8004f66: d044 beq.n 8004ff2 + if (attr->name != NULL) { + 8004f68: 687b ldr r3, [r7, #4] + 8004f6a: 681b ldr r3, [r3, #0] + 8004f6c: 2b00 cmp r3, #0 + 8004f6e: d002 beq.n 8004f76 + name = attr->name; + 8004f70: 687b ldr r3, [r7, #4] + 8004f72: 681b ldr r3, [r3, #0] + 8004f74: 62fb str r3, [r7, #44] ; 0x2c + } + if (attr->priority != osPriorityNone) { + 8004f76: 687b ldr r3, [r7, #4] + 8004f78: 699b ldr r3, [r3, #24] + 8004f7a: 2b00 cmp r3, #0 + 8004f7c: d002 beq.n 8004f84 + prio = (UBaseType_t)attr->priority; + 8004f7e: 687b ldr r3, [r7, #4] + 8004f80: 699b ldr r3, [r3, #24] + 8004f82: 627b str r3, [r7, #36] ; 0x24 + } + + if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { + 8004f84: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004f86: 2b00 cmp r3, #0 + 8004f88: d007 beq.n 8004f9a + 8004f8a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004f8c: 2b38 cmp r3, #56 ; 0x38 + 8004f8e: d804 bhi.n 8004f9a + 8004f90: 687b ldr r3, [r7, #4] + 8004f92: 685b ldr r3, [r3, #4] + 8004f94: 2201 movs r2, #1 + 8004f96: 4013 ands r3, r2 + 8004f98: d001 beq.n 8004f9e + return (NULL); + 8004f9a: 2300 movs r3, #0 + 8004f9c: e057 b.n 800504e + } + + if (attr->stack_size > 0U) { + 8004f9e: 687b ldr r3, [r7, #4] + 8004fa0: 695b ldr r3, [r3, #20] + 8004fa2: 2b00 cmp r3, #0 + 8004fa4: d003 beq.n 8004fae + /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ + /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ + stack = attr->stack_size / sizeof(StackType_t); + 8004fa6: 687b ldr r3, [r7, #4] + 8004fa8: 695b ldr r3, [r3, #20] + 8004faa: 089b lsrs r3, r3, #2 + 8004fac: 62bb str r3, [r7, #40] ; 0x28 + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + 8004fae: 687b ldr r3, [r7, #4] + 8004fb0: 689b ldr r3, [r3, #8] + 8004fb2: 2b00 cmp r3, #0 + 8004fb4: d00e beq.n 8004fd4 + 8004fb6: 687b ldr r3, [r7, #4] + 8004fb8: 68db ldr r3, [r3, #12] + 8004fba: 2b5b cmp r3, #91 ; 0x5b + 8004fbc: d90a bls.n 8004fd4 + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + 8004fbe: 687b ldr r3, [r7, #4] + 8004fc0: 691b ldr r3, [r3, #16] + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + 8004fc2: 2b00 cmp r3, #0 + 8004fc4: d006 beq.n 8004fd4 + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + 8004fc6: 687b ldr r3, [r7, #4] + 8004fc8: 695b ldr r3, [r3, #20] + 8004fca: 2b00 cmp r3, #0 + 8004fcc: d002 beq.n 8004fd4 + mem = 1; + 8004fce: 2301 movs r3, #1 + 8004fd0: 623b str r3, [r7, #32] + 8004fd2: e010 b.n 8004ff6 + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { + 8004fd4: 687b ldr r3, [r7, #4] + 8004fd6: 689b ldr r3, [r3, #8] + 8004fd8: 2b00 cmp r3, #0 + 8004fda: d10c bne.n 8004ff6 + 8004fdc: 687b ldr r3, [r7, #4] + 8004fde: 68db ldr r3, [r3, #12] + 8004fe0: 2b00 cmp r3, #0 + 8004fe2: d108 bne.n 8004ff6 + 8004fe4: 687b ldr r3, [r7, #4] + 8004fe6: 691b ldr r3, [r3, #16] + 8004fe8: 2b00 cmp r3, #0 + 8004fea: d104 bne.n 8004ff6 + mem = 0; + 8004fec: 2300 movs r3, #0 + 8004fee: 623b str r3, [r7, #32] + 8004ff0: e001 b.n 8004ff6 + } + } + } + else { + mem = 0; + 8004ff2: 2300 movs r3, #0 + 8004ff4: 623b str r3, [r7, #32] + } + + if (mem == 1) { + 8004ff6: 6a3b ldr r3, [r7, #32] + 8004ff8: 2b01 cmp r3, #1 + 8004ffa: d112 bne.n 8005022 + hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, + 8004ffc: 687b ldr r3, [r7, #4] + 8004ffe: 691a ldr r2, [r3, #16] + (StaticTask_t *)attr->cb_mem); + 8005000: 687b ldr r3, [r7, #4] + 8005002: 689b ldr r3, [r3, #8] + hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, + 8005004: 68bd ldr r5, [r7, #8] + 8005006: 6abc ldr r4, [r7, #40] ; 0x28 + 8005008: 6af9 ldr r1, [r7, #44] ; 0x2c + 800500a: 68f8 ldr r0, [r7, #12] + 800500c: 9302 str r3, [sp, #8] + 800500e: 9201 str r2, [sp, #4] + 8005010: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005012: 9300 str r3, [sp, #0] + 8005014: 002b movs r3, r5 + 8005016: 0022 movs r2, r4 + 8005018: f000 fd5b bl 8005ad2 + 800501c: 0003 movs r3, r0 + 800501e: 617b str r3, [r7, #20] + 8005020: e014 b.n 800504c + } + else { + if (mem == 0) { + 8005022: 6a3b ldr r3, [r7, #32] + 8005024: 2b00 cmp r3, #0 + 8005026: d111 bne.n 800504c + if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { + 8005028: 6abb ldr r3, [r7, #40] ; 0x28 + 800502a: b29a uxth r2, r3 + 800502c: 68bc ldr r4, [r7, #8] + 800502e: 6af9 ldr r1, [r7, #44] ; 0x2c + 8005030: 68f8 ldr r0, [r7, #12] + 8005032: 2314 movs r3, #20 + 8005034: 18fb adds r3, r7, r3 + 8005036: 9301 str r3, [sp, #4] + 8005038: 6a7b ldr r3, [r7, #36] ; 0x24 + 800503a: 9300 str r3, [sp, #0] + 800503c: 0023 movs r3, r4 + 800503e: f000 fd8c bl 8005b5a + 8005042: 0003 movs r3, r0 + 8005044: 2b01 cmp r3, #1 + 8005046: d001 beq.n 800504c + hTask = NULL; + 8005048: 2300 movs r3, #0 + 800504a: 617b str r3, [r7, #20] + } + } + } + } + + return ((osThreadId_t)hTask); + 800504c: 697b ldr r3, [r7, #20] +} + 800504e: 0018 movs r0, r3 + 8005050: 46bd mov sp, r7 + 8005052: b00c add sp, #48 ; 0x30 + 8005054: bdb0 pop {r4, r5, r7, pc} + 8005056: 46c0 nop ; (mov r8, r8) + 8005058: 20000030 .word 0x20000030 + +0800505c : + +/* + vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { + 800505c: b580 push {r7, lr} + 800505e: b084 sub sp, #16 + 8005060: af00 add r7, sp, #0 + 8005062: 60f8 str r0, [r7, #12] + 8005064: 60b9 str r1, [r7, #8] + 8005066: 607a str r2, [r7, #4] + *ppxIdleTaskTCBBuffer = &Idle_TCB; + 8005068: 68fb ldr r3, [r7, #12] + 800506a: 4a06 ldr r2, [pc, #24] ; (8005084 ) + 800506c: 601a str r2, [r3, #0] + *ppxIdleTaskStackBuffer = &Idle_Stack[0]; + 800506e: 68bb ldr r3, [r7, #8] + 8005070: 4a05 ldr r2, [pc, #20] ; (8005088 ) + 8005072: 601a str r2, [r3, #0] + *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; + 8005074: 687b ldr r3, [r7, #4] + 8005076: 2280 movs r2, #128 ; 0x80 + 8005078: 601a str r2, [r3, #0] +} + 800507a: 46c0 nop ; (mov r8, r8) + 800507c: 46bd mov sp, r7 + 800507e: b004 add sp, #16 + 8005080: bd80 pop {r7, pc} + 8005082: 46c0 nop ; (mov r8, r8) + 8005084: 20000034 .word 0x20000034 + 8005088: 20000090 .word 0x20000090 + +0800508c : + +/* + vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { + 800508c: b580 push {r7, lr} + 800508e: b084 sub sp, #16 + 8005090: af00 add r7, sp, #0 + 8005092: 60f8 str r0, [r7, #12] + 8005094: 60b9 str r1, [r7, #8] + 8005096: 607a str r2, [r7, #4] + *ppxTimerTaskTCBBuffer = &Timer_TCB; + 8005098: 68fb ldr r3, [r7, #12] + 800509a: 4a06 ldr r2, [pc, #24] ; (80050b4 ) + 800509c: 601a str r2, [r3, #0] + *ppxTimerTaskStackBuffer = &Timer_Stack[0]; + 800509e: 68bb ldr r3, [r7, #8] + 80050a0: 4a05 ldr r2, [pc, #20] ; (80050b8 ) + 80050a2: 601a str r2, [r3, #0] + *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; + 80050a4: 687b ldr r3, [r7, #4] + 80050a6: 2280 movs r2, #128 ; 0x80 + 80050a8: 0052 lsls r2, r2, #1 + 80050aa: 601a str r2, [r3, #0] +} + 80050ac: 46c0 nop ; (mov r8, r8) + 80050ae: 46bd mov sp, r7 + 80050b0: b004 add sp, #16 + 80050b2: bd80 pop {r7, pc} + 80050b4: 20000290 .word 0x20000290 + 80050b8: 200002ec .word 0x200002ec + +080050bc : +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + 80050bc: b580 push {r7, lr} + 80050be: b082 sub sp, #8 + 80050c0: af00 add r7, sp, #0 + 80050c2: 6078 str r0, [r7, #4] + /* The list structure contains a list item which is used to mark the + end of the list. To initialise the list the list end is inserted + as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 80050c4: 687b ldr r3, [r7, #4] + 80050c6: 3308 adds r3, #8 + 80050c8: 001a movs r2, r3 + 80050ca: 687b ldr r3, [r7, #4] + 80050cc: 605a str r2, [r3, #4] + + /* The list end value is the highest possible value in the list to + ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + 80050ce: 687b ldr r3, [r7, #4] + 80050d0: 2201 movs r2, #1 + 80050d2: 4252 negs r2, r2 + 80050d4: 609a str r2, [r3, #8] + + /* The list end next and previous pointers point to itself so we know + when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 80050d6: 687b ldr r3, [r7, #4] + 80050d8: 3308 adds r3, #8 + 80050da: 001a movs r2, r3 + 80050dc: 687b ldr r3, [r7, #4] + 80050de: 60da str r2, [r3, #12] + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 80050e0: 687b ldr r3, [r7, #4] + 80050e2: 3308 adds r3, #8 + 80050e4: 001a movs r2, r3 + 80050e6: 687b ldr r3, [r7, #4] + 80050e8: 611a str r2, [r3, #16] + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + 80050ea: 687b ldr r3, [r7, #4] + 80050ec: 2200 movs r2, #0 + 80050ee: 601a str r2, [r3, #0] + + /* Write known values into the list if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} + 80050f0: 46c0 nop ; (mov r8, r8) + 80050f2: 46bd mov sp, r7 + 80050f4: b002 add sp, #8 + 80050f6: bd80 pop {r7, pc} + +080050f8 : +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + 80050f8: b580 push {r7, lr} + 80050fa: b082 sub sp, #8 + 80050fc: af00 add r7, sp, #0 + 80050fe: 6078 str r0, [r7, #4] + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + 8005100: 687b ldr r3, [r7, #4] + 8005102: 2200 movs r2, #0 + 8005104: 611a str r2, [r3, #16] + + /* Write known values into the list item if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} + 8005106: 46c0 nop ; (mov r8, r8) + 8005108: 46bd mov sp, r7 + 800510a: b002 add sp, #8 + 800510c: bd80 pop {r7, pc} + +0800510e : +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 800510e: b580 push {r7, lr} + 8005110: b084 sub sp, #16 + 8005112: af00 add r7, sp, #0 + 8005114: 6078 str r0, [r7, #4] + 8005116: 6039 str r1, [r7, #0] +ListItem_t * const pxIndex = pxList->pxIndex; + 8005118: 687b ldr r3, [r7, #4] + 800511a: 685b ldr r3, [r3, #4] + 800511c: 60fb str r3, [r7, #12] + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + makes the new list item the last item to be removed by a call to + listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + 800511e: 683b ldr r3, [r7, #0] + 8005120: 68fa ldr r2, [r7, #12] + 8005122: 605a str r2, [r3, #4] + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + 8005124: 68fb ldr r3, [r7, #12] + 8005126: 689a ldr r2, [r3, #8] + 8005128: 683b ldr r3, [r7, #0] + 800512a: 609a str r2, [r3, #8] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + 800512c: 68fb ldr r3, [r7, #12] + 800512e: 689b ldr r3, [r3, #8] + 8005130: 683a ldr r2, [r7, #0] + 8005132: 605a str r2, [r3, #4] + pxIndex->pxPrevious = pxNewListItem; + 8005134: 68fb ldr r3, [r7, #12] + 8005136: 683a ldr r2, [r7, #0] + 8005138: 609a str r2, [r3, #8] + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + 800513a: 683b ldr r3, [r7, #0] + 800513c: 687a ldr r2, [r7, #4] + 800513e: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 8005140: 687b ldr r3, [r7, #4] + 8005142: 681b ldr r3, [r3, #0] + 8005144: 1c5a adds r2, r3, #1 + 8005146: 687b ldr r3, [r7, #4] + 8005148: 601a str r2, [r3, #0] +} + 800514a: 46c0 nop ; (mov r8, r8) + 800514c: 46bd mov sp, r7 + 800514e: b004 add sp, #16 + 8005150: bd80 pop {r7, pc} + +08005152 : +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 8005152: b580 push {r7, lr} + 8005154: b084 sub sp, #16 + 8005156: af00 add r7, sp, #0 + 8005158: 6078 str r0, [r7, #4] + 800515a: 6039 str r1, [r7, #0] +ListItem_t *pxIterator; +const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + 800515c: 683b ldr r3, [r7, #0] + 800515e: 681b ldr r3, [r3, #0] + 8005160: 60bb str r3, [r7, #8] + new list item should be placed after it. This ensures that TCBs which are + stored in ready lists (all of which have the same xItemValue value) get a + share of the CPU. However, if the xItemValue is the same as the back marker + the iteration loop below will not end. Therefore the value is checked + first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + 8005162: 68bb ldr r3, [r7, #8] + 8005164: 3301 adds r3, #1 + 8005166: d103 bne.n 8005170 + { + pxIterator = pxList->xListEnd.pxPrevious; + 8005168: 687b ldr r3, [r7, #4] + 800516a: 691b ldr r3, [r3, #16] + 800516c: 60fb str r3, [r7, #12] + 800516e: e00c b.n 800518a + 4) Using a queue or semaphore before it has been initialised or + before the scheduler has been started (are interrupts firing + before vTaskStartScheduler() has been called?). + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + 8005170: 687b ldr r3, [r7, #4] + 8005172: 3308 adds r3, #8 + 8005174: 60fb str r3, [r7, #12] + 8005176: e002 b.n 800517e + 8005178: 68fb ldr r3, [r7, #12] + 800517a: 685b ldr r3, [r3, #4] + 800517c: 60fb str r3, [r7, #12] + 800517e: 68fb ldr r3, [r7, #12] + 8005180: 685b ldr r3, [r3, #4] + 8005182: 681b ldr r3, [r3, #0] + 8005184: 68ba ldr r2, [r7, #8] + 8005186: 429a cmp r2, r3 + 8005188: d2f6 bcs.n 8005178 + /* There is nothing to do here, just iterating to the wanted + insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + 800518a: 68fb ldr r3, [r7, #12] + 800518c: 685a ldr r2, [r3, #4] + 800518e: 683b ldr r3, [r7, #0] + 8005190: 605a str r2, [r3, #4] + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + 8005192: 683b ldr r3, [r7, #0] + 8005194: 685b ldr r3, [r3, #4] + 8005196: 683a ldr r2, [r7, #0] + 8005198: 609a str r2, [r3, #8] + pxNewListItem->pxPrevious = pxIterator; + 800519a: 683b ldr r3, [r7, #0] + 800519c: 68fa ldr r2, [r7, #12] + 800519e: 609a str r2, [r3, #8] + pxIterator->pxNext = pxNewListItem; + 80051a0: 68fb ldr r3, [r7, #12] + 80051a2: 683a ldr r2, [r7, #0] + 80051a4: 605a str r2, [r3, #4] + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + pxNewListItem->pxContainer = pxList; + 80051a6: 683b ldr r3, [r7, #0] + 80051a8: 687a ldr r2, [r7, #4] + 80051aa: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 80051ac: 687b ldr r3, [r7, #4] + 80051ae: 681b ldr r3, [r3, #0] + 80051b0: 1c5a adds r2, r3, #1 + 80051b2: 687b ldr r3, [r7, #4] + 80051b4: 601a str r2, [r3, #0] +} + 80051b6: 46c0 nop ; (mov r8, r8) + 80051b8: 46bd mov sp, r7 + 80051ba: b004 add sp, #16 + 80051bc: bd80 pop {r7, pc} + +080051be : +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ + 80051be: b580 push {r7, lr} + 80051c0: b084 sub sp, #16 + 80051c2: af00 add r7, sp, #0 + 80051c4: 6078 str r0, [r7, #4] +/* The list item knows which list it is in. Obtain the list from the list +item. */ +List_t * const pxList = pxItemToRemove->pxContainer; + 80051c6: 687b ldr r3, [r7, #4] + 80051c8: 691b ldr r3, [r3, #16] + 80051ca: 60fb str r3, [r7, #12] + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + 80051cc: 687b ldr r3, [r7, #4] + 80051ce: 685b ldr r3, [r3, #4] + 80051d0: 687a ldr r2, [r7, #4] + 80051d2: 6892 ldr r2, [r2, #8] + 80051d4: 609a str r2, [r3, #8] + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + 80051d6: 687b ldr r3, [r7, #4] + 80051d8: 689b ldr r3, [r3, #8] + 80051da: 687a ldr r2, [r7, #4] + 80051dc: 6852 ldr r2, [r2, #4] + 80051de: 605a str r2, [r3, #4] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + 80051e0: 68fb ldr r3, [r7, #12] + 80051e2: 685b ldr r3, [r3, #4] + 80051e4: 687a ldr r2, [r7, #4] + 80051e6: 429a cmp r2, r3 + 80051e8: d103 bne.n 80051f2 + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + 80051ea: 687b ldr r3, [r7, #4] + 80051ec: 689a ldr r2, [r3, #8] + 80051ee: 68fb ldr r3, [r7, #12] + 80051f0: 605a str r2, [r3, #4] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + 80051f2: 687b ldr r3, [r7, #4] + 80051f4: 2200 movs r2, #0 + 80051f6: 611a str r2, [r3, #16] + ( pxList->uxNumberOfItems )--; + 80051f8: 68fb ldr r3, [r7, #12] + 80051fa: 681b ldr r3, [r3, #0] + 80051fc: 1e5a subs r2, r3, #1 + 80051fe: 68fb ldr r3, [r7, #12] + 8005200: 601a str r2, [r3, #0] + + return pxList->uxNumberOfItems; + 8005202: 68fb ldr r3, [r7, #12] + 8005204: 681b ldr r3, [r3, #0] +} + 8005206: 0018 movs r0, r3 + 8005208: 46bd mov sp, r7 + 800520a: b004 add sp, #16 + 800520c: bd80 pop {r7, pc} + +0800520e : + } \ + taskEXIT_CRITICAL() +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) +{ + 800520e: b580 push {r7, lr} + 8005210: b084 sub sp, #16 + 8005212: af00 add r7, sp, #0 + 8005214: 6078 str r0, [r7, #4] + 8005216: 6039 str r1, [r7, #0] +Queue_t * const pxQueue = xQueue; + 8005218: 687b ldr r3, [r7, #4] + 800521a: 60fb str r3, [r7, #12] + + configASSERT( pxQueue ); + 800521c: 68fb ldr r3, [r7, #12] + 800521e: 2b00 cmp r3, #0 + 8005220: d101 bne.n 8005226 + 8005222: b672 cpsid i + 8005224: e7fe b.n 8005224 + + taskENTER_CRITICAL(); + 8005226: f001 ff7b bl 8007120 + { + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 800522a: 68fb ldr r3, [r7, #12] + 800522c: 681a ldr r2, [r3, #0] + 800522e: 68fb ldr r3, [r7, #12] + 8005230: 6bd9 ldr r1, [r3, #60] ; 0x3c + 8005232: 68fb ldr r3, [r7, #12] + 8005234: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005236: 434b muls r3, r1 + 8005238: 18d2 adds r2, r2, r3 + 800523a: 68fb ldr r3, [r7, #12] + 800523c: 609a str r2, [r3, #8] + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + 800523e: 68fb ldr r3, [r7, #12] + 8005240: 2200 movs r2, #0 + 8005242: 639a str r2, [r3, #56] ; 0x38 + pxQueue->pcWriteTo = pxQueue->pcHead; + 8005244: 68fb ldr r3, [r7, #12] + 8005246: 681a ldr r2, [r3, #0] + 8005248: 68fb ldr r3, [r7, #12] + 800524a: 605a str r2, [r3, #4] + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 800524c: 68fb ldr r3, [r7, #12] + 800524e: 681a ldr r2, [r3, #0] + 8005250: 68fb ldr r3, [r7, #12] + 8005252: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005254: 1e59 subs r1, r3, #1 + 8005256: 68fb ldr r3, [r7, #12] + 8005258: 6c1b ldr r3, [r3, #64] ; 0x40 + 800525a: 434b muls r3, r1 + 800525c: 18d2 adds r2, r2, r3 + 800525e: 68fb ldr r3, [r7, #12] + 8005260: 60da str r2, [r3, #12] + pxQueue->cRxLock = queueUNLOCKED; + 8005262: 68fb ldr r3, [r7, #12] + 8005264: 2244 movs r2, #68 ; 0x44 + 8005266: 21ff movs r1, #255 ; 0xff + 8005268: 5499 strb r1, [r3, r2] + pxQueue->cTxLock = queueUNLOCKED; + 800526a: 68fb ldr r3, [r7, #12] + 800526c: 2245 movs r2, #69 ; 0x45 + 800526e: 21ff movs r1, #255 ; 0xff + 8005270: 5499 strb r1, [r3, r2] + + if( xNewQueue == pdFALSE ) + 8005272: 683b ldr r3, [r7, #0] + 8005274: 2b00 cmp r3, #0 + 8005276: d10d bne.n 8005294 + /* If there are tasks blocked waiting to read from the queue, then + the tasks will remain blocked as after this function exits the queue + will still be empty. If there are tasks blocked waiting to write to + the queue, then one should be unblocked as after this function exits + it will be possible to write to it. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 8005278: 68fb ldr r3, [r7, #12] + 800527a: 691b ldr r3, [r3, #16] + 800527c: 2b00 cmp r3, #0 + 800527e: d013 beq.n 80052a8 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 8005280: 68fb ldr r3, [r7, #12] + 8005282: 3310 adds r3, #16 + 8005284: 0018 movs r0, r3 + 8005286: f001 f8d7 bl 8006438 + 800528a: 1e03 subs r3, r0, #0 + 800528c: d00c beq.n 80052a8 + { + queueYIELD_IF_USING_PREEMPTION(); + 800528e: f001 ff37 bl 8007100 + 8005292: e009 b.n 80052a8 + } + } + else + { + /* Ensure the event queues start in the correct state. */ + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + 8005294: 68fb ldr r3, [r7, #12] + 8005296: 3310 adds r3, #16 + 8005298: 0018 movs r0, r3 + 800529a: f7ff ff0f bl 80050bc + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + 800529e: 68fb ldr r3, [r7, #12] + 80052a0: 3324 adds r3, #36 ; 0x24 + 80052a2: 0018 movs r0, r3 + 80052a4: f7ff ff0a bl 80050bc + } + } + taskEXIT_CRITICAL(); + 80052a8: f001 ff4c bl 8007144 + + /* A value is returned for calling semantic consistency with previous + versions. */ + return pdPASS; + 80052ac: 2301 movs r3, #1 +} + 80052ae: 0018 movs r0, r3 + 80052b0: 46bd mov sp, r7 + 80052b2: b004 add sp, #16 + 80052b4: bd80 pop {r7, pc} + +080052b6 : +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) + { + 80052b6: b590 push {r4, r7, lr} + 80052b8: b089 sub sp, #36 ; 0x24 + 80052ba: af02 add r7, sp, #8 + 80052bc: 60f8 str r0, [r7, #12] + 80052be: 60b9 str r1, [r7, #8] + 80052c0: 607a str r2, [r7, #4] + 80052c2: 603b str r3, [r7, #0] + Queue_t *pxNewQueue; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + 80052c4: 68fb ldr r3, [r7, #12] + 80052c6: 2b00 cmp r3, #0 + 80052c8: d101 bne.n 80052ce + 80052ca: b672 cpsid i + 80052cc: e7fe b.n 80052cc + + /* The StaticQueue_t structure and the queue storage area must be + supplied. */ + configASSERT( pxStaticQueue != NULL ); + 80052ce: 683b ldr r3, [r7, #0] + 80052d0: 2b00 cmp r3, #0 + 80052d2: d101 bne.n 80052d8 + 80052d4: b672 cpsid i + 80052d6: e7fe b.n 80052d6 + + /* A queue storage area should be provided if the item size is not 0, and + should not be provided if the item size is 0. */ + configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); + 80052d8: 687b ldr r3, [r7, #4] + 80052da: 2b00 cmp r3, #0 + 80052dc: d002 beq.n 80052e4 + 80052de: 68bb ldr r3, [r7, #8] + 80052e0: 2b00 cmp r3, #0 + 80052e2: d001 beq.n 80052e8 + 80052e4: 2301 movs r3, #1 + 80052e6: e000 b.n 80052ea + 80052e8: 2300 movs r3, #0 + 80052ea: 2b00 cmp r3, #0 + 80052ec: d101 bne.n 80052f2 + 80052ee: b672 cpsid i + 80052f0: e7fe b.n 80052f0 + configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); + 80052f2: 687b ldr r3, [r7, #4] + 80052f4: 2b00 cmp r3, #0 + 80052f6: d102 bne.n 80052fe + 80052f8: 68bb ldr r3, [r7, #8] + 80052fa: 2b00 cmp r3, #0 + 80052fc: d101 bne.n 8005302 + 80052fe: 2301 movs r3, #1 + 8005300: e000 b.n 8005304 + 8005302: 2300 movs r3, #0 + 8005304: 2b00 cmp r3, #0 + 8005306: d101 bne.n 800530c + 8005308: b672 cpsid i + 800530a: e7fe b.n 800530a + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticQueue_t or StaticSemaphore_t equals the size of + the real queue and semaphore structures. */ + volatile size_t xSize = sizeof( StaticQueue_t ); + 800530c: 2350 movs r3, #80 ; 0x50 + 800530e: 613b str r3, [r7, #16] + configASSERT( xSize == sizeof( Queue_t ) ); + 8005310: 693b ldr r3, [r7, #16] + 8005312: 2b50 cmp r3, #80 ; 0x50 + 8005314: d001 beq.n 800531a + 8005316: b672 cpsid i + 8005318: e7fe b.n 8005318 + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + 800531a: 693b ldr r3, [r7, #16] + #endif /* configASSERT_DEFINED */ + + /* The address of a statically allocated queue was passed in, use it. + The address of a statically allocated storage area was also passed in + but is already set. */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + 800531c: 683b ldr r3, [r7, #0] + 800531e: 617b str r3, [r7, #20] + + if( pxNewQueue != NULL ) + 8005320: 697b ldr r3, [r7, #20] + 8005322: 2b00 cmp r3, #0 + 8005324: d00e beq.n 8005344 + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Queues can be allocated wither statically or dynamically, so + note this queue was allocated statically in case the queue is + later deleted. */ + pxNewQueue->ucStaticallyAllocated = pdTRUE; + 8005326: 697b ldr r3, [r7, #20] + 8005328: 2246 movs r2, #70 ; 0x46 + 800532a: 2101 movs r1, #1 + 800532c: 5499 strb r1, [r3, r2] + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + 800532e: 2328 movs r3, #40 ; 0x28 + 8005330: 18fb adds r3, r7, r3 + 8005332: 781c ldrb r4, [r3, #0] + 8005334: 687a ldr r2, [r7, #4] + 8005336: 68b9 ldr r1, [r7, #8] + 8005338: 68f8 ldr r0, [r7, #12] + 800533a: 697b ldr r3, [r7, #20] + 800533c: 9300 str r3, [sp, #0] + 800533e: 0023 movs r3, r4 + 8005340: f000 f83d bl 80053be + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + 8005344: 697b ldr r3, [r7, #20] + } + 8005346: 0018 movs r0, r3 + 8005348: 46bd mov sp, r7 + 800534a: b007 add sp, #28 + 800534c: bd90 pop {r4, r7, pc} + +0800534e : +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) + { + 800534e: b590 push {r4, r7, lr} + 8005350: b08b sub sp, #44 ; 0x2c + 8005352: af02 add r7, sp, #8 + 8005354: 60f8 str r0, [r7, #12] + 8005356: 60b9 str r1, [r7, #8] + 8005358: 1dfb adds r3, r7, #7 + 800535a: 701a strb r2, [r3, #0] + Queue_t *pxNewQueue; + size_t xQueueSizeInBytes; + uint8_t *pucQueueStorage; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + 800535c: 68fb ldr r3, [r7, #12] + 800535e: 2b00 cmp r3, #0 + 8005360: d101 bne.n 8005366 + 8005362: b672 cpsid i + 8005364: e7fe b.n 8005364 + + if( uxItemSize == ( UBaseType_t ) 0 ) + 8005366: 68bb ldr r3, [r7, #8] + 8005368: 2b00 cmp r3, #0 + 800536a: d102 bne.n 8005372 + { + /* There is not going to be a queue storage area. */ + xQueueSizeInBytes = ( size_t ) 0; + 800536c: 2300 movs r3, #0 + 800536e: 61fb str r3, [r7, #28] + 8005370: e003 b.n 800537a + } + else + { + /* Allocate enough space to hold the maximum number of items that + can be in the queue at any time. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8005372: 68fb ldr r3, [r7, #12] + 8005374: 68ba ldr r2, [r7, #8] + 8005376: 4353 muls r3, r2 + 8005378: 61fb str r3, [r7, #28] + alignment requirements of the Queue_t structure - which in this case + is an int8_t *. Therefore, whenever the stack alignment requirements + are greater than or equal to the pointer to char requirements the cast + is safe. In other cases alignment requirements are not strict (one or + two bytes). */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ + 800537a: 69fb ldr r3, [r7, #28] + 800537c: 3350 adds r3, #80 ; 0x50 + 800537e: 0018 movs r0, r3 + 8005380: f002 f84a bl 8007418 + 8005384: 0003 movs r3, r0 + 8005386: 61bb str r3, [r7, #24] + + if( pxNewQueue != NULL ) + 8005388: 69bb ldr r3, [r7, #24] + 800538a: 2b00 cmp r3, #0 + 800538c: d012 beq.n 80053b4 + { + /* Jump past the queue structure to find the location of the queue + storage area. */ + pucQueueStorage = ( uint8_t * ) pxNewQueue; + 800538e: 69bb ldr r3, [r7, #24] + 8005390: 617b str r3, [r7, #20] + pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 8005392: 697b ldr r3, [r7, #20] + 8005394: 3350 adds r3, #80 ; 0x50 + 8005396: 617b str r3, [r7, #20] + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Queues can be created either statically or dynamically, so + note this task was created dynamically in case it is later + deleted. */ + pxNewQueue->ucStaticallyAllocated = pdFALSE; + 8005398: 69bb ldr r3, [r7, #24] + 800539a: 2246 movs r2, #70 ; 0x46 + 800539c: 2100 movs r1, #0 + 800539e: 5499 strb r1, [r3, r2] + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + 80053a0: 1dfb adds r3, r7, #7 + 80053a2: 781c ldrb r4, [r3, #0] + 80053a4: 697a ldr r2, [r7, #20] + 80053a6: 68b9 ldr r1, [r7, #8] + 80053a8: 68f8 ldr r0, [r7, #12] + 80053aa: 69bb ldr r3, [r7, #24] + 80053ac: 9300 str r3, [sp, #0] + 80053ae: 0023 movs r3, r4 + 80053b0: f000 f805 bl 80053be + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + 80053b4: 69bb ldr r3, [r7, #24] + } + 80053b6: 0018 movs r0, r3 + 80053b8: 46bd mov sp, r7 + 80053ba: b009 add sp, #36 ; 0x24 + 80053bc: bd90 pop {r4, r7, pc} + +080053be : + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) +{ + 80053be: b580 push {r7, lr} + 80053c0: b084 sub sp, #16 + 80053c2: af00 add r7, sp, #0 + 80053c4: 60f8 str r0, [r7, #12] + 80053c6: 60b9 str r1, [r7, #8] + 80053c8: 607a str r2, [r7, #4] + 80053ca: 001a movs r2, r3 + 80053cc: 1cfb adds r3, r7, #3 + 80053ce: 701a strb r2, [r3, #0] + /* Remove compiler warnings about unused parameters should + configUSE_TRACE_FACILITY not be set to 1. */ + ( void ) ucQueueType; + + if( uxItemSize == ( UBaseType_t ) 0 ) + 80053d0: 68bb ldr r3, [r7, #8] + 80053d2: 2b00 cmp r3, #0 + 80053d4: d103 bne.n 80053de + { + /* No RAM was allocated for the queue storage area, but PC head cannot + be set to NULL because NULL is used as a key to say the queue is used as + a mutex. Therefore just set pcHead to point to the queue as a benign + value that is known to be within the memory map. */ + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + 80053d6: 69bb ldr r3, [r7, #24] + 80053d8: 69ba ldr r2, [r7, #24] + 80053da: 601a str r2, [r3, #0] + 80053dc: e002 b.n 80053e4 + } + else + { + /* Set the head to the start of the queue storage area. */ + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + 80053de: 69bb ldr r3, [r7, #24] + 80053e0: 687a ldr r2, [r7, #4] + 80053e2: 601a str r2, [r3, #0] + } + + /* Initialise the queue members as described where the queue type is + defined. */ + pxNewQueue->uxLength = uxQueueLength; + 80053e4: 69bb ldr r3, [r7, #24] + 80053e6: 68fa ldr r2, [r7, #12] + 80053e8: 63da str r2, [r3, #60] ; 0x3c + pxNewQueue->uxItemSize = uxItemSize; + 80053ea: 69bb ldr r3, [r7, #24] + 80053ec: 68ba ldr r2, [r7, #8] + 80053ee: 641a str r2, [r3, #64] ; 0x40 + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + 80053f0: 69bb ldr r3, [r7, #24] + 80053f2: 2101 movs r1, #1 + 80053f4: 0018 movs r0, r3 + 80053f6: f7ff ff0a bl 800520e + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxNewQueue->ucQueueType = ucQueueType; + 80053fa: 69bb ldr r3, [r7, #24] + 80053fc: 1cfa adds r2, r7, #3 + 80053fe: 214c movs r1, #76 ; 0x4c + 8005400: 7812 ldrb r2, [r2, #0] + 8005402: 545a strb r2, [r3, r1] + pxNewQueue->pxQueueSetContainer = NULL; + } + #endif /* configUSE_QUEUE_SETS */ + + traceQUEUE_CREATE( pxNewQueue ); +} + 8005404: 46c0 nop ; (mov r8, r8) + 8005406: 46bd mov sp, r7 + 8005408: b004 add sp, #16 + 800540a: bd80 pop {r7, pc} + +0800540c : + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) +{ + 800540c: b580 push {r7, lr} + 800540e: b08a sub sp, #40 ; 0x28 + 8005410: af00 add r7, sp, #0 + 8005412: 60f8 str r0, [r7, #12] + 8005414: 60b9 str r1, [r7, #8] + 8005416: 607a str r2, [r7, #4] + 8005418: 603b str r3, [r7, #0] +BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; + 800541a: 2300 movs r3, #0 + 800541c: 627b str r3, [r7, #36] ; 0x24 +TimeOut_t xTimeOut; +Queue_t * const pxQueue = xQueue; + 800541e: 68fb ldr r3, [r7, #12] + 8005420: 623b str r3, [r7, #32] + + configASSERT( pxQueue ); + 8005422: 6a3b ldr r3, [r7, #32] + 8005424: 2b00 cmp r3, #0 + 8005426: d101 bne.n 800542c + 8005428: b672 cpsid i + 800542a: e7fe b.n 800542a + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 800542c: 68bb ldr r3, [r7, #8] + 800542e: 2b00 cmp r3, #0 + 8005430: d103 bne.n 800543a + 8005432: 6a3b ldr r3, [r7, #32] + 8005434: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005436: 2b00 cmp r3, #0 + 8005438: d101 bne.n 800543e + 800543a: 2301 movs r3, #1 + 800543c: e000 b.n 8005440 + 800543e: 2300 movs r3, #0 + 8005440: 2b00 cmp r3, #0 + 8005442: d101 bne.n 8005448 + 8005444: b672 cpsid i + 8005446: e7fe b.n 8005446 + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + 8005448: 683b ldr r3, [r7, #0] + 800544a: 2b02 cmp r3, #2 + 800544c: d103 bne.n 8005456 + 800544e: 6a3b ldr r3, [r7, #32] + 8005450: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005452: 2b01 cmp r3, #1 + 8005454: d101 bne.n 800545a + 8005456: 2301 movs r3, #1 + 8005458: e000 b.n 800545c + 800545a: 2300 movs r3, #0 + 800545c: 2b00 cmp r3, #0 + 800545e: d101 bne.n 8005464 + 8005460: b672 cpsid i + 8005462: e7fe b.n 8005462 + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 8005464: f001 f9e0 bl 8006828 + 8005468: 1e03 subs r3, r0, #0 + 800546a: d102 bne.n 8005472 + 800546c: 687b ldr r3, [r7, #4] + 800546e: 2b00 cmp r3, #0 + 8005470: d101 bne.n 8005476 + 8005472: 2301 movs r3, #1 + 8005474: e000 b.n 8005478 + 8005476: 2300 movs r3, #0 + 8005478: 2b00 cmp r3, #0 + 800547a: d101 bne.n 8005480 + 800547c: b672 cpsid i + 800547e: e7fe b.n 800547e + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ + for( ;; ) + { + taskENTER_CRITICAL(); + 8005480: f001 fe4e bl 8007120 + { + /* Is there room on the queue now? The running task must be the + highest priority task wanting to access the queue. If the head item + in the queue is to be overwritten then it does not matter if the + queue is full. */ + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + 8005484: 6a3b ldr r3, [r7, #32] + 8005486: 6b9a ldr r2, [r3, #56] ; 0x38 + 8005488: 6a3b ldr r3, [r7, #32] + 800548a: 6bdb ldr r3, [r3, #60] ; 0x3c + 800548c: 429a cmp r2, r3 + 800548e: d302 bcc.n 8005496 + 8005490: 683b ldr r3, [r7, #0] + 8005492: 2b02 cmp r3, #2 + 8005494: d11e bne.n 80054d4 + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 8005496: 683a ldr r2, [r7, #0] + 8005498: 68b9 ldr r1, [r7, #8] + 800549a: 6a3b ldr r3, [r7, #32] + 800549c: 0018 movs r0, r3 + 800549e: f000 f99f bl 80057e0 + 80054a2: 0003 movs r3, r0 + 80054a4: 61fb str r3, [r7, #28] + + /* If there was a task waiting for data to arrive on the + queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 80054a6: 6a3b ldr r3, [r7, #32] + 80054a8: 6a5b ldr r3, [r3, #36] ; 0x24 + 80054aa: 2b00 cmp r3, #0 + 80054ac: d009 beq.n 80054c2 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 80054ae: 6a3b ldr r3, [r7, #32] + 80054b0: 3324 adds r3, #36 ; 0x24 + 80054b2: 0018 movs r0, r3 + 80054b4: f000 ffc0 bl 8006438 + 80054b8: 1e03 subs r3, r0, #0 + 80054ba: d007 beq.n 80054cc + { + /* The unblocked task has a priority higher than + our own so yield immediately. Yes it is ok to do + this from within the critical section - the kernel + takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + 80054bc: f001 fe20 bl 8007100 + 80054c0: e004 b.n 80054cc + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + 80054c2: 69fb ldr r3, [r7, #28] + 80054c4: 2b00 cmp r3, #0 + 80054c6: d001 beq.n 80054cc + { + /* This path is a special case that will only get + executed if the task was holding multiple mutexes and + the mutexes were given back in an order that is + different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + 80054c8: f001 fe1a bl 8007100 + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + + taskEXIT_CRITICAL(); + 80054cc: f001 fe3a bl 8007144 + return pdPASS; + 80054d0: 2301 movs r3, #1 + 80054d2: e05b b.n 800558c + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + 80054d4: 687b ldr r3, [r7, #4] + 80054d6: 2b00 cmp r3, #0 + 80054d8: d103 bne.n 80054e2 + { + /* The queue was full and no block time is specified (or + the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + 80054da: f001 fe33 bl 8007144 + + /* Return to the original privilege level before exiting + the function. */ + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + 80054de: 2300 movs r3, #0 + 80054e0: e054 b.n 800558c + } + else if( xEntryTimeSet == pdFALSE ) + 80054e2: 6a7b ldr r3, [r7, #36] ; 0x24 + 80054e4: 2b00 cmp r3, #0 + 80054e6: d106 bne.n 80054f6 + { + /* The queue was full and a block time was specified so + configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + 80054e8: 2314 movs r3, #20 + 80054ea: 18fb adds r3, r7, r3 + 80054ec: 0018 movs r0, r3 + 80054ee: f001 f801 bl 80064f4 + xEntryTimeSet = pdTRUE; + 80054f2: 2301 movs r3, #1 + 80054f4: 627b str r3, [r7, #36] ; 0x24 + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + 80054f6: f001 fe25 bl 8007144 + + /* Interrupts and other tasks can send to and receive from the queue + now the critical section has been exited. */ + + vTaskSuspendAll(); + 80054fa: f000 fd5f bl 8005fbc + prvLockQueue( pxQueue ); + 80054fe: f001 fe0f bl 8007120 + 8005502: 6a3b ldr r3, [r7, #32] + 8005504: 2244 movs r2, #68 ; 0x44 + 8005506: 5c9b ldrb r3, [r3, r2] + 8005508: b25b sxtb r3, r3 + 800550a: 3301 adds r3, #1 + 800550c: d103 bne.n 8005516 + 800550e: 6a3b ldr r3, [r7, #32] + 8005510: 2244 movs r2, #68 ; 0x44 + 8005512: 2100 movs r1, #0 + 8005514: 5499 strb r1, [r3, r2] + 8005516: 6a3b ldr r3, [r7, #32] + 8005518: 2245 movs r2, #69 ; 0x45 + 800551a: 5c9b ldrb r3, [r3, r2] + 800551c: b25b sxtb r3, r3 + 800551e: 3301 adds r3, #1 + 8005520: d103 bne.n 800552a + 8005522: 6a3b ldr r3, [r7, #32] + 8005524: 2245 movs r2, #69 ; 0x45 + 8005526: 2100 movs r1, #0 + 8005528: 5499 strb r1, [r3, r2] + 800552a: f001 fe0b bl 8007144 + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 800552e: 1d3a adds r2, r7, #4 + 8005530: 2314 movs r3, #20 + 8005532: 18fb adds r3, r7, r3 + 8005534: 0011 movs r1, r2 + 8005536: 0018 movs r0, r3 + 8005538: f000 fff0 bl 800651c + 800553c: 1e03 subs r3, r0, #0 + 800553e: d11e bne.n 800557e + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + 8005540: 6a3b ldr r3, [r7, #32] + 8005542: 0018 movs r0, r3 + 8005544: f000 fa51 bl 80059ea + 8005548: 1e03 subs r3, r0, #0 + 800554a: d011 beq.n 8005570 + { + traceBLOCKING_ON_QUEUE_SEND( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + 800554c: 6a3b ldr r3, [r7, #32] + 800554e: 3310 adds r3, #16 + 8005550: 687a ldr r2, [r7, #4] + 8005552: 0011 movs r1, r2 + 8005554: 0018 movs r0, r3 + 8005556: f000 ff2b bl 80063b0 + /* Unlocking the queue means queue events can effect the + event list. It is possible that interrupts occurring now + remove this task from the event list again - but as the + scheduler is suspended the task will go onto the pending + ready last instead of the actual ready list. */ + prvUnlockQueue( pxQueue ); + 800555a: 6a3b ldr r3, [r7, #32] + 800555c: 0018 movs r0, r3 + 800555e: f000 f9d0 bl 8005902 + /* Resuming the scheduler will move tasks from the pending + ready list into the ready list - so it is feasible that this + task is already in a ready list before it yields - in which + case the yield will not cause a context switch unless there + is also a higher priority task in the pending ready list. */ + if( xTaskResumeAll() == pdFALSE ) + 8005562: f000 fd6d bl 8006040 + 8005566: 1e03 subs r3, r0, #0 + 8005568: d18a bne.n 8005480 + { + portYIELD_WITHIN_API(); + 800556a: f001 fdc9 bl 8007100 + 800556e: e787 b.n 8005480 + } + } + else + { + /* Try again. */ + prvUnlockQueue( pxQueue ); + 8005570: 6a3b ldr r3, [r7, #32] + 8005572: 0018 movs r0, r3 + 8005574: f000 f9c5 bl 8005902 + ( void ) xTaskResumeAll(); + 8005578: f000 fd62 bl 8006040 + 800557c: e780 b.n 8005480 + } + } + else + { + /* The timeout has expired. */ + prvUnlockQueue( pxQueue ); + 800557e: 6a3b ldr r3, [r7, #32] + 8005580: 0018 movs r0, r3 + 8005582: f000 f9be bl 8005902 + ( void ) xTaskResumeAll(); + 8005586: f000 fd5b bl 8006040 + + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + 800558a: 2300 movs r3, #0 + } + } /*lint -restore */ +} + 800558c: 0018 movs r0, r3 + 800558e: 46bd mov sp, r7 + 8005590: b00a add sp, #40 ; 0x28 + 8005592: bd80 pop {r7, pc} + +08005594 : +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) +{ + 8005594: b590 push {r4, r7, lr} + 8005596: b089 sub sp, #36 ; 0x24 + 8005598: af00 add r7, sp, #0 + 800559a: 60f8 str r0, [r7, #12] + 800559c: 60b9 str r1, [r7, #8] + 800559e: 607a str r2, [r7, #4] + 80055a0: 603b str r3, [r7, #0] +BaseType_t xReturn; +UBaseType_t uxSavedInterruptStatus; +Queue_t * const pxQueue = xQueue; + 80055a2: 68fb ldr r3, [r7, #12] + 80055a4: 61bb str r3, [r7, #24] + + configASSERT( pxQueue ); + 80055a6: 69bb ldr r3, [r7, #24] + 80055a8: 2b00 cmp r3, #0 + 80055aa: d101 bne.n 80055b0 + 80055ac: b672 cpsid i + 80055ae: e7fe b.n 80055ae + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 80055b0: 68bb ldr r3, [r7, #8] + 80055b2: 2b00 cmp r3, #0 + 80055b4: d103 bne.n 80055be + 80055b6: 69bb ldr r3, [r7, #24] + 80055b8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80055ba: 2b00 cmp r3, #0 + 80055bc: d101 bne.n 80055c2 + 80055be: 2301 movs r3, #1 + 80055c0: e000 b.n 80055c4 + 80055c2: 2300 movs r3, #0 + 80055c4: 2b00 cmp r3, #0 + 80055c6: d101 bne.n 80055cc + 80055c8: b672 cpsid i + 80055ca: e7fe b.n 80055ca + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + 80055cc: 683b ldr r3, [r7, #0] + 80055ce: 2b02 cmp r3, #2 + 80055d0: d103 bne.n 80055da + 80055d2: 69bb ldr r3, [r7, #24] + 80055d4: 6bdb ldr r3, [r3, #60] ; 0x3c + 80055d6: 2b01 cmp r3, #1 + 80055d8: d101 bne.n 80055de + 80055da: 2301 movs r3, #1 + 80055dc: e000 b.n 80055e0 + 80055de: 2300 movs r3, #0 + 80055e0: 2b00 cmp r3, #0 + 80055e2: d101 bne.n 80055e8 + 80055e4: b672 cpsid i + 80055e6: e7fe b.n 80055e6 + /* Similar to xQueueGenericSend, except without blocking if there is no room + in the queue. Also don't directly wake a task that was blocked on a queue + read, instead return a flag to say whether a context switch is required or + not (i.e. has a task with a higher priority than us been woken by this + post). */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + 80055e8: f001 fdc4 bl 8007174 + 80055ec: 0003 movs r3, r0 + 80055ee: 617b str r3, [r7, #20] + { + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + 80055f0: 69bb ldr r3, [r7, #24] + 80055f2: 6b9a ldr r2, [r3, #56] ; 0x38 + 80055f4: 69bb ldr r3, [r7, #24] + 80055f6: 6bdb ldr r3, [r3, #60] ; 0x3c + 80055f8: 429a cmp r2, r3 + 80055fa: d302 bcc.n 8005602 + 80055fc: 683b ldr r3, [r7, #0] + 80055fe: 2b02 cmp r3, #2 + 8005600: d12e bne.n 8005660 + { + const int8_t cTxLock = pxQueue->cTxLock; + 8005602: 2413 movs r4, #19 + 8005604: 193b adds r3, r7, r4 + 8005606: 69ba ldr r2, [r7, #24] + 8005608: 2145 movs r1, #69 ; 0x45 + 800560a: 5c52 ldrb r2, [r2, r1] + 800560c: 701a strb r2, [r3, #0] + /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a + semaphore or mutex. That means prvCopyDataToQueue() cannot result + in a task disinheriting a priority and prvCopyDataToQueue() can be + called here even though the disinherit function does not check if + the scheduler is suspended before accessing the ready lists. */ + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 800560e: 683a ldr r2, [r7, #0] + 8005610: 68b9 ldr r1, [r7, #8] + 8005612: 69bb ldr r3, [r7, #24] + 8005614: 0018 movs r0, r3 + 8005616: f000 f8e3 bl 80057e0 + + /* The event list is not altered if the queue is locked. This will + be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + 800561a: 193b adds r3, r7, r4 + 800561c: 781b ldrb r3, [r3, #0] + 800561e: b25b sxtb r3, r3 + 8005620: 3301 adds r3, #1 + 8005622: d111 bne.n 8005648 + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 8005624: 69bb ldr r3, [r7, #24] + 8005626: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005628: 2b00 cmp r3, #0 + 800562a: d016 beq.n 800565a + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 800562c: 69bb ldr r3, [r7, #24] + 800562e: 3324 adds r3, #36 ; 0x24 + 8005630: 0018 movs r0, r3 + 8005632: f000 ff01 bl 8006438 + 8005636: 1e03 subs r3, r0, #0 + 8005638: d00f beq.n 800565a + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + 800563a: 687b ldr r3, [r7, #4] + 800563c: 2b00 cmp r3, #0 + 800563e: d00c beq.n 800565a + { + *pxHigherPriorityTaskWoken = pdTRUE; + 8005640: 687b ldr r3, [r7, #4] + 8005642: 2201 movs r2, #1 + 8005644: 601a str r2, [r3, #0] + 8005646: e008 b.n 800565a + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was posted while it was locked. */ + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + 8005648: 2313 movs r3, #19 + 800564a: 18fb adds r3, r7, r3 + 800564c: 781b ldrb r3, [r3, #0] + 800564e: 3301 adds r3, #1 + 8005650: b2db uxtb r3, r3 + 8005652: b259 sxtb r1, r3 + 8005654: 69bb ldr r3, [r7, #24] + 8005656: 2245 movs r2, #69 ; 0x45 + 8005658: 5499 strb r1, [r3, r2] + } + + xReturn = pdPASS; + 800565a: 2301 movs r3, #1 + 800565c: 61fb str r3, [r7, #28] + { + 800565e: e001 b.n 8005664 + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + 8005660: 2300 movs r3, #0 + 8005662: 61fb str r3, [r7, #28] + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + 8005664: 697b ldr r3, [r7, #20] + 8005666: 0018 movs r0, r3 + 8005668: f001 fd8a bl 8007180 + + return xReturn; + 800566c: 69fb ldr r3, [r7, #28] +} + 800566e: 0018 movs r0, r3 + 8005670: 46bd mov sp, r7 + 8005672: b009 add sp, #36 ; 0x24 + 8005674: bd90 pop {r4, r7, pc} + +08005676 : + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) +{ + 8005676: b580 push {r7, lr} + 8005678: b08a sub sp, #40 ; 0x28 + 800567a: af00 add r7, sp, #0 + 800567c: 60f8 str r0, [r7, #12] + 800567e: 60b9 str r1, [r7, #8] + 8005680: 607a str r2, [r7, #4] +BaseType_t xEntryTimeSet = pdFALSE; + 8005682: 2300 movs r3, #0 + 8005684: 627b str r3, [r7, #36] ; 0x24 +TimeOut_t xTimeOut; +Queue_t * const pxQueue = xQueue; + 8005686: 68fb ldr r3, [r7, #12] + 8005688: 623b str r3, [r7, #32] + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + 800568a: 6a3b ldr r3, [r7, #32] + 800568c: 2b00 cmp r3, #0 + 800568e: d101 bne.n 8005694 + 8005690: b672 cpsid i + 8005692: e7fe b.n 8005692 + + /* The buffer into which data is received can only be NULL if the data size + is zero (so no data is copied into the buffer. */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 8005694: 68bb ldr r3, [r7, #8] + 8005696: 2b00 cmp r3, #0 + 8005698: d103 bne.n 80056a2 + 800569a: 6a3b ldr r3, [r7, #32] + 800569c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800569e: 2b00 cmp r3, #0 + 80056a0: d101 bne.n 80056a6 + 80056a2: 2301 movs r3, #1 + 80056a4: e000 b.n 80056a8 + 80056a6: 2300 movs r3, #0 + 80056a8: 2b00 cmp r3, #0 + 80056aa: d101 bne.n 80056b0 + 80056ac: b672 cpsid i + 80056ae: e7fe b.n 80056ae + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 80056b0: f001 f8ba bl 8006828 + 80056b4: 1e03 subs r3, r0, #0 + 80056b6: d102 bne.n 80056be + 80056b8: 687b ldr r3, [r7, #4] + 80056ba: 2b00 cmp r3, #0 + 80056bc: d101 bne.n 80056c2 + 80056be: 2301 movs r3, #1 + 80056c0: e000 b.n 80056c4 + 80056c2: 2300 movs r3, #0 + 80056c4: 2b00 cmp r3, #0 + 80056c6: d101 bne.n 80056cc + 80056c8: b672 cpsid i + 80056ca: e7fe b.n 80056ca + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ + for( ;; ) + { + taskENTER_CRITICAL(); + 80056cc: f001 fd28 bl 8007120 + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 80056d0: 6a3b ldr r3, [r7, #32] + 80056d2: 6b9b ldr r3, [r3, #56] ; 0x38 + 80056d4: 61fb str r3, [r7, #28] + + /* Is there data in the queue now? To be running the calling task + must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 80056d6: 69fb ldr r3, [r7, #28] + 80056d8: 2b00 cmp r3, #0 + 80056da: d01a beq.n 8005712 + { + /* Data available, remove one item. */ + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 80056dc: 68ba ldr r2, [r7, #8] + 80056de: 6a3b ldr r3, [r7, #32] + 80056e0: 0011 movs r1, r2 + 80056e2: 0018 movs r0, r3 + 80056e4: f000 f8e7 bl 80058b6 + traceQUEUE_RECEIVE( pxQueue ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + 80056e8: 69fb ldr r3, [r7, #28] + 80056ea: 1e5a subs r2, r3, #1 + 80056ec: 6a3b ldr r3, [r7, #32] + 80056ee: 639a str r2, [r3, #56] ; 0x38 + + /* There is now space in the queue, were any tasks waiting to + post to the queue? If so, unblock the highest priority waiting + task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 80056f0: 6a3b ldr r3, [r7, #32] + 80056f2: 691b ldr r3, [r3, #16] + 80056f4: 2b00 cmp r3, #0 + 80056f6: d008 beq.n 800570a + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 80056f8: 6a3b ldr r3, [r7, #32] + 80056fa: 3310 adds r3, #16 + 80056fc: 0018 movs r0, r3 + 80056fe: f000 fe9b bl 8006438 + 8005702: 1e03 subs r3, r0, #0 + 8005704: d001 beq.n 800570a + { + queueYIELD_IF_USING_PREEMPTION(); + 8005706: f001 fcfb bl 8007100 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + 800570a: f001 fd1b bl 8007144 + return pdPASS; + 800570e: 2301 movs r3, #1 + 8005710: e062 b.n 80057d8 + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + 8005712: 687b ldr r3, [r7, #4] + 8005714: 2b00 cmp r3, #0 + 8005716: d103 bne.n 8005720 + { + /* The queue was empty and no block time is specified (or + the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + 8005718: f001 fd14 bl 8007144 + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 800571c: 2300 movs r3, #0 + 800571e: e05b b.n 80057d8 + } + else if( xEntryTimeSet == pdFALSE ) + 8005720: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005722: 2b00 cmp r3, #0 + 8005724: d106 bne.n 8005734 + { + /* The queue was empty and a block time was specified so + configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + 8005726: 2314 movs r3, #20 + 8005728: 18fb adds r3, r7, r3 + 800572a: 0018 movs r0, r3 + 800572c: f000 fee2 bl 80064f4 + xEntryTimeSet = pdTRUE; + 8005730: 2301 movs r3, #1 + 8005732: 627b str r3, [r7, #36] ; 0x24 + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + 8005734: f001 fd06 bl 8007144 + + /* Interrupts and other tasks can send to and receive from the queue + now the critical section has been exited. */ + + vTaskSuspendAll(); + 8005738: f000 fc40 bl 8005fbc + prvLockQueue( pxQueue ); + 800573c: f001 fcf0 bl 8007120 + 8005740: 6a3b ldr r3, [r7, #32] + 8005742: 2244 movs r2, #68 ; 0x44 + 8005744: 5c9b ldrb r3, [r3, r2] + 8005746: b25b sxtb r3, r3 + 8005748: 3301 adds r3, #1 + 800574a: d103 bne.n 8005754 + 800574c: 6a3b ldr r3, [r7, #32] + 800574e: 2244 movs r2, #68 ; 0x44 + 8005750: 2100 movs r1, #0 + 8005752: 5499 strb r1, [r3, r2] + 8005754: 6a3b ldr r3, [r7, #32] + 8005756: 2245 movs r2, #69 ; 0x45 + 8005758: 5c9b ldrb r3, [r3, r2] + 800575a: b25b sxtb r3, r3 + 800575c: 3301 adds r3, #1 + 800575e: d103 bne.n 8005768 + 8005760: 6a3b ldr r3, [r7, #32] + 8005762: 2245 movs r2, #69 ; 0x45 + 8005764: 2100 movs r1, #0 + 8005766: 5499 strb r1, [r3, r2] + 8005768: f001 fcec bl 8007144 + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 800576c: 1d3a adds r2, r7, #4 + 800576e: 2314 movs r3, #20 + 8005770: 18fb adds r3, r7, r3 + 8005772: 0011 movs r1, r2 + 8005774: 0018 movs r0, r3 + 8005776: f000 fed1 bl 800651c + 800577a: 1e03 subs r3, r0, #0 + 800577c: d11e bne.n 80057bc + { + /* The timeout has not expired. If the queue is still empty place + the task on the list of tasks waiting to receive from the queue. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 800577e: 6a3b ldr r3, [r7, #32] + 8005780: 0018 movs r0, r3 + 8005782: f000 f91c bl 80059be + 8005786: 1e03 subs r3, r0, #0 + 8005788: d011 beq.n 80057ae + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + 800578a: 6a3b ldr r3, [r7, #32] + 800578c: 3324 adds r3, #36 ; 0x24 + 800578e: 687a ldr r2, [r7, #4] + 8005790: 0011 movs r1, r2 + 8005792: 0018 movs r0, r3 + 8005794: f000 fe0c bl 80063b0 + prvUnlockQueue( pxQueue ); + 8005798: 6a3b ldr r3, [r7, #32] + 800579a: 0018 movs r0, r3 + 800579c: f000 f8b1 bl 8005902 + if( xTaskResumeAll() == pdFALSE ) + 80057a0: f000 fc4e bl 8006040 + 80057a4: 1e03 subs r3, r0, #0 + 80057a6: d191 bne.n 80056cc + { + portYIELD_WITHIN_API(); + 80057a8: f001 fcaa bl 8007100 + 80057ac: e78e b.n 80056cc + } + else + { + /* The queue contains data again. Loop back to try and read the + data. */ + prvUnlockQueue( pxQueue ); + 80057ae: 6a3b ldr r3, [r7, #32] + 80057b0: 0018 movs r0, r3 + 80057b2: f000 f8a6 bl 8005902 + ( void ) xTaskResumeAll(); + 80057b6: f000 fc43 bl 8006040 + 80057ba: e787 b.n 80056cc + } + else + { + /* Timed out. If there is no data in the queue exit, otherwise loop + back and attempt to read the data. */ + prvUnlockQueue( pxQueue ); + 80057bc: 6a3b ldr r3, [r7, #32] + 80057be: 0018 movs r0, r3 + 80057c0: f000 f89f bl 8005902 + ( void ) xTaskResumeAll(); + 80057c4: f000 fc3c bl 8006040 + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 80057c8: 6a3b ldr r3, [r7, #32] + 80057ca: 0018 movs r0, r3 + 80057cc: f000 f8f7 bl 80059be + 80057d0: 1e03 subs r3, r0, #0 + 80057d2: d100 bne.n 80057d6 + 80057d4: e77a b.n 80056cc + { + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 80057d6: 2300 movs r3, #0 + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} + 80057d8: 0018 movs r0, r3 + 80057da: 46bd mov sp, r7 + 80057dc: b00a add sp, #40 ; 0x28 + 80057de: bd80 pop {r7, pc} + +080057e0 : + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) +{ + 80057e0: b580 push {r7, lr} + 80057e2: b086 sub sp, #24 + 80057e4: af00 add r7, sp, #0 + 80057e6: 60f8 str r0, [r7, #12] + 80057e8: 60b9 str r1, [r7, #8] + 80057ea: 607a str r2, [r7, #4] +BaseType_t xReturn = pdFALSE; + 80057ec: 2300 movs r3, #0 + 80057ee: 617b str r3, [r7, #20] +UBaseType_t uxMessagesWaiting; + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 80057f0: 68fb ldr r3, [r7, #12] + 80057f2: 6b9b ldr r3, [r3, #56] ; 0x38 + 80057f4: 613b str r3, [r7, #16] + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + 80057f6: 68fb ldr r3, [r7, #12] + 80057f8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80057fa: 2b00 cmp r3, #0 + 80057fc: d10e bne.n 800581c + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 80057fe: 68fb ldr r3, [r7, #12] + 8005800: 681b ldr r3, [r3, #0] + 8005802: 2b00 cmp r3, #0 + 8005804: d14e bne.n 80058a4 + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + 8005806: 68fb ldr r3, [r7, #12] + 8005808: 689b ldr r3, [r3, #8] + 800580a: 0018 movs r0, r3 + 800580c: f001 f828 bl 8006860 + 8005810: 0003 movs r3, r0 + 8005812: 617b str r3, [r7, #20] + pxQueue->u.xSemaphore.xMutexHolder = NULL; + 8005814: 68fb ldr r3, [r7, #12] + 8005816: 2200 movs r2, #0 + 8005818: 609a str r2, [r3, #8] + 800581a: e043 b.n 80058a4 + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + } + else if( xPosition == queueSEND_TO_BACK ) + 800581c: 687b ldr r3, [r7, #4] + 800581e: 2b00 cmp r3, #0 + 8005820: d119 bne.n 8005856 + { + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + 8005822: 68fb ldr r3, [r7, #12] + 8005824: 6858 ldr r0, [r3, #4] + 8005826: 68fb ldr r3, [r7, #12] + 8005828: 6c1a ldr r2, [r3, #64] ; 0x40 + 800582a: 68bb ldr r3, [r7, #8] + 800582c: 0019 movs r1, r3 + 800582e: f001 ffbd bl 80077ac + pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + 8005832: 68fb ldr r3, [r7, #12] + 8005834: 685a ldr r2, [r3, #4] + 8005836: 68fb ldr r3, [r7, #12] + 8005838: 6c1b ldr r3, [r3, #64] ; 0x40 + 800583a: 18d2 adds r2, r2, r3 + 800583c: 68fb ldr r3, [r7, #12] + 800583e: 605a str r2, [r3, #4] + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 8005840: 68fb ldr r3, [r7, #12] + 8005842: 685a ldr r2, [r3, #4] + 8005844: 68fb ldr r3, [r7, #12] + 8005846: 689b ldr r3, [r3, #8] + 8005848: 429a cmp r2, r3 + 800584a: d32b bcc.n 80058a4 + { + pxQueue->pcWriteTo = pxQueue->pcHead; + 800584c: 68fb ldr r3, [r7, #12] + 800584e: 681a ldr r2, [r3, #0] + 8005850: 68fb ldr r3, [r7, #12] + 8005852: 605a str r2, [r3, #4] + 8005854: e026 b.n 80058a4 + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + 8005856: 68fb ldr r3, [r7, #12] + 8005858: 68d8 ldr r0, [r3, #12] + 800585a: 68fb ldr r3, [r7, #12] + 800585c: 6c1a ldr r2, [r3, #64] ; 0x40 + 800585e: 68bb ldr r3, [r7, #8] + 8005860: 0019 movs r1, r3 + 8005862: f001 ffa3 bl 80077ac + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + 8005866: 68fb ldr r3, [r7, #12] + 8005868: 68da ldr r2, [r3, #12] + 800586a: 68fb ldr r3, [r7, #12] + 800586c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800586e: 425b negs r3, r3 + 8005870: 18d2 adds r2, r2, r3 + 8005872: 68fb ldr r3, [r7, #12] + 8005874: 60da str r2, [r3, #12] + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 8005876: 68fb ldr r3, [r7, #12] + 8005878: 68da ldr r2, [r3, #12] + 800587a: 68fb ldr r3, [r7, #12] + 800587c: 681b ldr r3, [r3, #0] + 800587e: 429a cmp r2, r3 + 8005880: d207 bcs.n 8005892 + { + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); + 8005882: 68fb ldr r3, [r7, #12] + 8005884: 689a ldr r2, [r3, #8] + 8005886: 68fb ldr r3, [r7, #12] + 8005888: 6c1b ldr r3, [r3, #64] ; 0x40 + 800588a: 425b negs r3, r3 + 800588c: 18d2 adds r2, r2, r3 + 800588e: 68fb ldr r3, [r7, #12] + 8005890: 60da str r2, [r3, #12] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xPosition == queueOVERWRITE ) + 8005892: 687b ldr r3, [r7, #4] + 8005894: 2b02 cmp r3, #2 + 8005896: d105 bne.n 80058a4 + { + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 8005898: 693b ldr r3, [r7, #16] + 800589a: 2b00 cmp r3, #0 + 800589c: d002 beq.n 80058a4 + { + /* An item is not being added but overwritten, so subtract + one from the recorded number of items in the queue so when + one is added again below the number of recorded items remains + correct. */ + --uxMessagesWaiting; + 800589e: 693b ldr r3, [r7, #16] + 80058a0: 3b01 subs r3, #1 + 80058a2: 613b str r3, [r7, #16] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + 80058a4: 693b ldr r3, [r7, #16] + 80058a6: 1c5a adds r2, r3, #1 + 80058a8: 68fb ldr r3, [r7, #12] + 80058aa: 639a str r2, [r3, #56] ; 0x38 + + return xReturn; + 80058ac: 697b ldr r3, [r7, #20] +} + 80058ae: 0018 movs r0, r3 + 80058b0: 46bd mov sp, r7 + 80058b2: b006 add sp, #24 + 80058b4: bd80 pop {r7, pc} + +080058b6 : +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) +{ + 80058b6: b580 push {r7, lr} + 80058b8: b082 sub sp, #8 + 80058ba: af00 add r7, sp, #0 + 80058bc: 6078 str r0, [r7, #4] + 80058be: 6039 str r1, [r7, #0] + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + 80058c0: 687b ldr r3, [r7, #4] + 80058c2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80058c4: 2b00 cmp r3, #0 + 80058c6: d018 beq.n 80058fa + { + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + 80058c8: 687b ldr r3, [r7, #4] + 80058ca: 68da ldr r2, [r3, #12] + 80058cc: 687b ldr r3, [r7, #4] + 80058ce: 6c1b ldr r3, [r3, #64] ; 0x40 + 80058d0: 18d2 adds r2, r2, r3 + 80058d2: 687b ldr r3, [r7, #4] + 80058d4: 60da str r2, [r3, #12] + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + 80058d6: 687b ldr r3, [r7, #4] + 80058d8: 68da ldr r2, [r3, #12] + 80058da: 687b ldr r3, [r7, #4] + 80058dc: 689b ldr r3, [r3, #8] + 80058de: 429a cmp r2, r3 + 80058e0: d303 bcc.n 80058ea + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + 80058e2: 687b ldr r3, [r7, #4] + 80058e4: 681a ldr r2, [r3, #0] + 80058e6: 687b ldr r3, [r7, #4] + 80058e8: 60da str r2, [r3, #12] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + 80058ea: 687b ldr r3, [r7, #4] + 80058ec: 68d9 ldr r1, [r3, #12] + 80058ee: 687b ldr r3, [r7, #4] + 80058f0: 6c1a ldr r2, [r3, #64] ; 0x40 + 80058f2: 683b ldr r3, [r7, #0] + 80058f4: 0018 movs r0, r3 + 80058f6: f001 ff59 bl 80077ac + } +} + 80058fa: 46c0 nop ; (mov r8, r8) + 80058fc: 46bd mov sp, r7 + 80058fe: b002 add sp, #8 + 8005900: bd80 pop {r7, pc} + +08005902 : +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + 8005902: b580 push {r7, lr} + 8005904: b084 sub sp, #16 + 8005906: af00 add r7, sp, #0 + 8005908: 6078 str r0, [r7, #4] + + /* The lock counts contains the number of extra data items placed or + removed from the queue while the queue was locked. When a queue is + locked items can be added or removed, but the event lists cannot be + updated. */ + taskENTER_CRITICAL(); + 800590a: f001 fc09 bl 8007120 + { + int8_t cTxLock = pxQueue->cTxLock; + 800590e: 230f movs r3, #15 + 8005910: 18fb adds r3, r7, r3 + 8005912: 687a ldr r2, [r7, #4] + 8005914: 2145 movs r1, #69 ; 0x45 + 8005916: 5c52 ldrb r2, [r2, r1] + 8005918: 701a strb r2, [r3, #0] + + /* See if data was added to the queue while it was locked. */ + while( cTxLock > queueLOCKED_UNMODIFIED ) + 800591a: e013 b.n 8005944 + } + #else /* configUSE_QUEUE_SETS */ + { + /* Tasks that are removed from the event list will get added to + the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800591c: 687b ldr r3, [r7, #4] + 800591e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005920: 2b00 cmp r3, #0 + 8005922: d016 beq.n 8005952 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 8005924: 687b ldr r3, [r7, #4] + 8005926: 3324 adds r3, #36 ; 0x24 + 8005928: 0018 movs r0, r3 + 800592a: f000 fd85 bl 8006438 + 800592e: 1e03 subs r3, r0, #0 + 8005930: d001 beq.n 8005936 + { + /* The task waiting has a higher priority so record that + a context switch is required. */ + vTaskMissedYield(); + 8005932: f000 fe53 bl 80065dc + break; + } + } + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + 8005936: 210f movs r1, #15 + 8005938: 187b adds r3, r7, r1 + 800593a: 781b ldrb r3, [r3, #0] + 800593c: 3b01 subs r3, #1 + 800593e: b2da uxtb r2, r3 + 8005940: 187b adds r3, r7, r1 + 8005942: 701a strb r2, [r3, #0] + while( cTxLock > queueLOCKED_UNMODIFIED ) + 8005944: 230f movs r3, #15 + 8005946: 18fb adds r3, r7, r3 + 8005948: 781b ldrb r3, [r3, #0] + 800594a: b25b sxtb r3, r3 + 800594c: 2b00 cmp r3, #0 + 800594e: dce5 bgt.n 800591c + 8005950: e000 b.n 8005954 + break; + 8005952: 46c0 nop ; (mov r8, r8) + } + + pxQueue->cTxLock = queueUNLOCKED; + 8005954: 687b ldr r3, [r7, #4] + 8005956: 2245 movs r2, #69 ; 0x45 + 8005958: 21ff movs r1, #255 ; 0xff + 800595a: 5499 strb r1, [r3, r2] + } + taskEXIT_CRITICAL(); + 800595c: f001 fbf2 bl 8007144 + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + 8005960: f001 fbde bl 8007120 + { + int8_t cRxLock = pxQueue->cRxLock; + 8005964: 230e movs r3, #14 + 8005966: 18fb adds r3, r7, r3 + 8005968: 687a ldr r2, [r7, #4] + 800596a: 2144 movs r1, #68 ; 0x44 + 800596c: 5c52 ldrb r2, [r2, r1] + 800596e: 701a strb r2, [r3, #0] + + while( cRxLock > queueLOCKED_UNMODIFIED ) + 8005970: e013 b.n 800599a + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 8005972: 687b ldr r3, [r7, #4] + 8005974: 691b ldr r3, [r3, #16] + 8005976: 2b00 cmp r3, #0 + 8005978: d016 beq.n 80059a8 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 800597a: 687b ldr r3, [r7, #4] + 800597c: 3310 adds r3, #16 + 800597e: 0018 movs r0, r3 + 8005980: f000 fd5a bl 8006438 + 8005984: 1e03 subs r3, r0, #0 + 8005986: d001 beq.n 800598c + { + vTaskMissedYield(); + 8005988: f000 fe28 bl 80065dc + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --cRxLock; + 800598c: 210e movs r1, #14 + 800598e: 187b adds r3, r7, r1 + 8005990: 781b ldrb r3, [r3, #0] + 8005992: 3b01 subs r3, #1 + 8005994: b2da uxtb r2, r3 + 8005996: 187b adds r3, r7, r1 + 8005998: 701a strb r2, [r3, #0] + while( cRxLock > queueLOCKED_UNMODIFIED ) + 800599a: 230e movs r3, #14 + 800599c: 18fb adds r3, r7, r3 + 800599e: 781b ldrb r3, [r3, #0] + 80059a0: b25b sxtb r3, r3 + 80059a2: 2b00 cmp r3, #0 + 80059a4: dce5 bgt.n 8005972 + 80059a6: e000 b.n 80059aa + } + else + { + break; + 80059a8: 46c0 nop ; (mov r8, r8) + } + } + + pxQueue->cRxLock = queueUNLOCKED; + 80059aa: 687b ldr r3, [r7, #4] + 80059ac: 2244 movs r2, #68 ; 0x44 + 80059ae: 21ff movs r1, #255 ; 0xff + 80059b0: 5499 strb r1, [r3, r2] + } + taskEXIT_CRITICAL(); + 80059b2: f001 fbc7 bl 8007144 +} + 80059b6: 46c0 nop ; (mov r8, r8) + 80059b8: 46bd mov sp, r7 + 80059ba: b004 add sp, #16 + 80059bc: bd80 pop {r7, pc} + +080059be : +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) +{ + 80059be: b580 push {r7, lr} + 80059c0: b084 sub sp, #16 + 80059c2: af00 add r7, sp, #0 + 80059c4: 6078 str r0, [r7, #4] +BaseType_t xReturn; + + taskENTER_CRITICAL(); + 80059c6: f001 fbab bl 8007120 + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + 80059ca: 687b ldr r3, [r7, #4] + 80059cc: 6b9b ldr r3, [r3, #56] ; 0x38 + 80059ce: 2b00 cmp r3, #0 + 80059d0: d102 bne.n 80059d8 + { + xReturn = pdTRUE; + 80059d2: 2301 movs r3, #1 + 80059d4: 60fb str r3, [r7, #12] + 80059d6: e001 b.n 80059dc + } + else + { + xReturn = pdFALSE; + 80059d8: 2300 movs r3, #0 + 80059da: 60fb str r3, [r7, #12] + } + } + taskEXIT_CRITICAL(); + 80059dc: f001 fbb2 bl 8007144 + + return xReturn; + 80059e0: 68fb ldr r3, [r7, #12] +} + 80059e2: 0018 movs r0, r3 + 80059e4: 46bd mov sp, r7 + 80059e6: b004 add sp, #16 + 80059e8: bd80 pop {r7, pc} + +080059ea : + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) +{ + 80059ea: b580 push {r7, lr} + 80059ec: b084 sub sp, #16 + 80059ee: af00 add r7, sp, #0 + 80059f0: 6078 str r0, [r7, #4] +BaseType_t xReturn; + + taskENTER_CRITICAL(); + 80059f2: f001 fb95 bl 8007120 + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + 80059f6: 687b ldr r3, [r7, #4] + 80059f8: 6b9a ldr r2, [r3, #56] ; 0x38 + 80059fa: 687b ldr r3, [r7, #4] + 80059fc: 6bdb ldr r3, [r3, #60] ; 0x3c + 80059fe: 429a cmp r2, r3 + 8005a00: d102 bne.n 8005a08 + { + xReturn = pdTRUE; + 8005a02: 2301 movs r3, #1 + 8005a04: 60fb str r3, [r7, #12] + 8005a06: e001 b.n 8005a0c + } + else + { + xReturn = pdFALSE; + 8005a08: 2300 movs r3, #0 + 8005a0a: 60fb str r3, [r7, #12] + } + } + taskEXIT_CRITICAL(); + 8005a0c: f001 fb9a bl 8007144 + + return xReturn; + 8005a10: 68fb ldr r3, [r7, #12] +} + 8005a12: 0018 movs r0, r3 + 8005a14: 46bd mov sp, r7 + 8005a16: b004 add sp, #16 + 8005a18: bd80 pop {r7, pc} + ... + +08005a1c : +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + 8005a1c: b580 push {r7, lr} + 8005a1e: b084 sub sp, #16 + 8005a20: af00 add r7, sp, #0 + 8005a22: 6078 str r0, [r7, #4] + 8005a24: 6039 str r1, [r7, #0] + UBaseType_t ux; + + /* See if there is an empty space in the registry. A NULL name denotes + a free slot. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + 8005a26: 2300 movs r3, #0 + 8005a28: 60fb str r3, [r7, #12] + 8005a2a: e015 b.n 8005a58 + { + if( xQueueRegistry[ ux ].pcQueueName == NULL ) + 8005a2c: 4b0e ldr r3, [pc, #56] ; (8005a68 ) + 8005a2e: 68fa ldr r2, [r7, #12] + 8005a30: 00d2 lsls r2, r2, #3 + 8005a32: 58d3 ldr r3, [r2, r3] + 8005a34: 2b00 cmp r3, #0 + 8005a36: d10c bne.n 8005a52 + { + /* Store the information on this queue. */ + xQueueRegistry[ ux ].pcQueueName = pcQueueName; + 8005a38: 4b0b ldr r3, [pc, #44] ; (8005a68 ) + 8005a3a: 68fa ldr r2, [r7, #12] + 8005a3c: 00d2 lsls r2, r2, #3 + 8005a3e: 6839 ldr r1, [r7, #0] + 8005a40: 50d1 str r1, [r2, r3] + xQueueRegistry[ ux ].xHandle = xQueue; + 8005a42: 4a09 ldr r2, [pc, #36] ; (8005a68 ) + 8005a44: 68fb ldr r3, [r7, #12] + 8005a46: 00db lsls r3, r3, #3 + 8005a48: 18d3 adds r3, r2, r3 + 8005a4a: 3304 adds r3, #4 + 8005a4c: 687a ldr r2, [r7, #4] + 8005a4e: 601a str r2, [r3, #0] + + traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); + break; + 8005a50: e006 b.n 8005a60 + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + 8005a52: 68fb ldr r3, [r7, #12] + 8005a54: 3301 adds r3, #1 + 8005a56: 60fb str r3, [r7, #12] + 8005a58: 68fb ldr r3, [r7, #12] + 8005a5a: 2b07 cmp r3, #7 + 8005a5c: d9e6 bls.n 8005a2c + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + 8005a5e: 46c0 nop ; (mov r8, r8) + 8005a60: 46c0 nop ; (mov r8, r8) + 8005a62: 46bd mov sp, r7 + 8005a64: b004 add sp, #16 + 8005a66: bd80 pop {r7, pc} + 8005a68: 2000196c .word 0x2000196c + +08005a6c : +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) + { + 8005a6c: b580 push {r7, lr} + 8005a6e: b086 sub sp, #24 + 8005a70: af00 add r7, sp, #0 + 8005a72: 60f8 str r0, [r7, #12] + 8005a74: 60b9 str r1, [r7, #8] + 8005a76: 607a str r2, [r7, #4] + Queue_t * const pxQueue = xQueue; + 8005a78: 68fb ldr r3, [r7, #12] + 8005a7a: 617b str r3, [r7, #20] + will not actually cause the task to block, just place it on a blocked + list. It will not block until the scheduler is unlocked - at which + time a yield will be performed. If an item is added to the queue while + the queue is locked, and the calling task blocks on the queue, then the + calling task will be immediately unblocked when the queue is unlocked. */ + prvLockQueue( pxQueue ); + 8005a7c: f001 fb50 bl 8007120 + 8005a80: 697b ldr r3, [r7, #20] + 8005a82: 2244 movs r2, #68 ; 0x44 + 8005a84: 5c9b ldrb r3, [r3, r2] + 8005a86: b25b sxtb r3, r3 + 8005a88: 3301 adds r3, #1 + 8005a8a: d103 bne.n 8005a94 + 8005a8c: 697b ldr r3, [r7, #20] + 8005a8e: 2244 movs r2, #68 ; 0x44 + 8005a90: 2100 movs r1, #0 + 8005a92: 5499 strb r1, [r3, r2] + 8005a94: 697b ldr r3, [r7, #20] + 8005a96: 2245 movs r2, #69 ; 0x45 + 8005a98: 5c9b ldrb r3, [r3, r2] + 8005a9a: b25b sxtb r3, r3 + 8005a9c: 3301 adds r3, #1 + 8005a9e: d103 bne.n 8005aa8 + 8005aa0: 697b ldr r3, [r7, #20] + 8005aa2: 2245 movs r2, #69 ; 0x45 + 8005aa4: 2100 movs r1, #0 + 8005aa6: 5499 strb r1, [r3, r2] + 8005aa8: f001 fb4c bl 8007144 + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) + 8005aac: 697b ldr r3, [r7, #20] + 8005aae: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005ab0: 2b00 cmp r3, #0 + 8005ab2: d106 bne.n 8005ac2 + { + /* There is nothing in the queue, block for the specified period. */ + vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); + 8005ab4: 697b ldr r3, [r7, #20] + 8005ab6: 3324 adds r3, #36 ; 0x24 + 8005ab8: 687a ldr r2, [r7, #4] + 8005aba: 68b9 ldr r1, [r7, #8] + 8005abc: 0018 movs r0, r3 + 8005abe: f000 fc95 bl 80063ec + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + prvUnlockQueue( pxQueue ); + 8005ac2: 697b ldr r3, [r7, #20] + 8005ac4: 0018 movs r0, r3 + 8005ac6: f7ff ff1c bl 8005902 + } + 8005aca: 46c0 nop ; (mov r8, r8) + 8005acc: 46bd mov sp, r7 + 8005ace: b006 add sp, #24 + 8005ad0: bd80 pop {r7, pc} + +08005ad2 : + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + 8005ad2: b590 push {r4, r7, lr} + 8005ad4: b08d sub sp, #52 ; 0x34 + 8005ad6: af04 add r7, sp, #16 + 8005ad8: 60f8 str r0, [r7, #12] + 8005ada: 60b9 str r1, [r7, #8] + 8005adc: 607a str r2, [r7, #4] + 8005ade: 603b str r3, [r7, #0] + TCB_t *pxNewTCB; + TaskHandle_t xReturn; + + configASSERT( puxStackBuffer != NULL ); + 8005ae0: 6b7b ldr r3, [r7, #52] ; 0x34 + 8005ae2: 2b00 cmp r3, #0 + 8005ae4: d101 bne.n 8005aea + 8005ae6: b672 cpsid i + 8005ae8: e7fe b.n 8005ae8 + configASSERT( pxTaskBuffer != NULL ); + 8005aea: 6bbb ldr r3, [r7, #56] ; 0x38 + 8005aec: 2b00 cmp r3, #0 + 8005aee: d101 bne.n 8005af4 + 8005af0: b672 cpsid i + 8005af2: e7fe b.n 8005af2 + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticTask_t equals the size of the real task + structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + 8005af4: 235c movs r3, #92 ; 0x5c + 8005af6: 617b str r3, [r7, #20] + configASSERT( xSize == sizeof( TCB_t ) ); + 8005af8: 697b ldr r3, [r7, #20] + 8005afa: 2b5c cmp r3, #92 ; 0x5c + 8005afc: d001 beq.n 8005b02 + 8005afe: b672 cpsid i + 8005b00: e7fe b.n 8005b00 + ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ + 8005b02: 697b ldr r3, [r7, #20] + } + #endif /* configASSERT_DEFINED */ + + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + 8005b04: 6bbb ldr r3, [r7, #56] ; 0x38 + 8005b06: 2b00 cmp r3, #0 + 8005b08: d020 beq.n 8005b4c + 8005b0a: 6b7b ldr r3, [r7, #52] ; 0x34 + 8005b0c: 2b00 cmp r3, #0 + 8005b0e: d01d beq.n 8005b4c + { + /* The memory used for the task's TCB and stack are passed into this + function - use them. */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + 8005b10: 6bbb ldr r3, [r7, #56] ; 0x38 + 8005b12: 61fb str r3, [r7, #28] + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + 8005b14: 69fb ldr r3, [r7, #28] + 8005b16: 6b7a ldr r2, [r7, #52] ; 0x34 + 8005b18: 631a str r2, [r3, #48] ; 0x30 + + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + 8005b1a: 69fb ldr r3, [r7, #28] + 8005b1c: 2259 movs r2, #89 ; 0x59 + 8005b1e: 2102 movs r1, #2 + 8005b20: 5499 strb r1, [r3, r2] + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); + 8005b22: 683c ldr r4, [r7, #0] + 8005b24: 687a ldr r2, [r7, #4] + 8005b26: 68b9 ldr r1, [r7, #8] + 8005b28: 68f8 ldr r0, [r7, #12] + 8005b2a: 2300 movs r3, #0 + 8005b2c: 9303 str r3, [sp, #12] + 8005b2e: 69fb ldr r3, [r7, #28] + 8005b30: 9302 str r3, [sp, #8] + 8005b32: 2318 movs r3, #24 + 8005b34: 18fb adds r3, r7, r3 + 8005b36: 9301 str r3, [sp, #4] + 8005b38: 6b3b ldr r3, [r7, #48] ; 0x30 + 8005b3a: 9300 str r3, [sp, #0] + 8005b3c: 0023 movs r3, r4 + 8005b3e: f000 f859 bl 8005bf4 + prvAddNewTaskToReadyList( pxNewTCB ); + 8005b42: 69fb ldr r3, [r7, #28] + 8005b44: 0018 movs r0, r3 + 8005b46: f000 f8e3 bl 8005d10 + 8005b4a: e001 b.n 8005b50 + } + else + { + xReturn = NULL; + 8005b4c: 2300 movs r3, #0 + 8005b4e: 61bb str r3, [r7, #24] + } + + return xReturn; + 8005b50: 69bb ldr r3, [r7, #24] + } + 8005b52: 0018 movs r0, r3 + 8005b54: 46bd mov sp, r7 + 8005b56: b009 add sp, #36 ; 0x24 + 8005b58: bd90 pop {r4, r7, pc} + +08005b5a : + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + 8005b5a: b590 push {r4, r7, lr} + 8005b5c: b08d sub sp, #52 ; 0x34 + 8005b5e: af04 add r7, sp, #16 + 8005b60: 60f8 str r0, [r7, #12] + 8005b62: 60b9 str r1, [r7, #8] + 8005b64: 603b str r3, [r7, #0] + 8005b66: 1dbb adds r3, r7, #6 + 8005b68: 801a strh r2, [r3, #0] + #else /* portSTACK_GROWTH */ + { + StackType_t *pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + 8005b6a: 1dbb adds r3, r7, #6 + 8005b6c: 881b ldrh r3, [r3, #0] + 8005b6e: 009b lsls r3, r3, #2 + 8005b70: 0018 movs r0, r3 + 8005b72: f001 fc51 bl 8007418 + 8005b76: 0003 movs r3, r0 + 8005b78: 617b str r3, [r7, #20] + + if( pxStack != NULL ) + 8005b7a: 697b ldr r3, [r7, #20] + 8005b7c: 2b00 cmp r3, #0 + 8005b7e: d010 beq.n 8005ba2 + { + /* Allocate space for the TCB. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + 8005b80: 205c movs r0, #92 ; 0x5c + 8005b82: f001 fc49 bl 8007418 + 8005b86: 0003 movs r3, r0 + 8005b88: 61fb str r3, [r7, #28] + + if( pxNewTCB != NULL ) + 8005b8a: 69fb ldr r3, [r7, #28] + 8005b8c: 2b00 cmp r3, #0 + 8005b8e: d003 beq.n 8005b98 + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + 8005b90: 69fb ldr r3, [r7, #28] + 8005b92: 697a ldr r2, [r7, #20] + 8005b94: 631a str r2, [r3, #48] ; 0x30 + 8005b96: e006 b.n 8005ba6 + } + else + { + /* The stack cannot be used as the TCB was not created. Free + it again. */ + vPortFree( pxStack ); + 8005b98: 697b ldr r3, [r7, #20] + 8005b9a: 0018 movs r0, r3 + 8005b9c: f001 fce2 bl 8007564 + 8005ba0: e001 b.n 8005ba6 + } + } + else + { + pxNewTCB = NULL; + 8005ba2: 2300 movs r3, #0 + 8005ba4: 61fb str r3, [r7, #28] + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + 8005ba6: 69fb ldr r3, [r7, #28] + 8005ba8: 2b00 cmp r3, #0 + 8005baa: d01a beq.n 8005be2 + { + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + 8005bac: 69fb ldr r3, [r7, #28] + 8005bae: 2259 movs r2, #89 ; 0x59 + 8005bb0: 2100 movs r1, #0 + 8005bb2: 5499 strb r1, [r3, r2] + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + 8005bb4: 1dbb adds r3, r7, #6 + 8005bb6: 881a ldrh r2, [r3, #0] + 8005bb8: 683c ldr r4, [r7, #0] + 8005bba: 68b9 ldr r1, [r7, #8] + 8005bbc: 68f8 ldr r0, [r7, #12] + 8005bbe: 2300 movs r3, #0 + 8005bc0: 9303 str r3, [sp, #12] + 8005bc2: 69fb ldr r3, [r7, #28] + 8005bc4: 9302 str r3, [sp, #8] + 8005bc6: 6b7b ldr r3, [r7, #52] ; 0x34 + 8005bc8: 9301 str r3, [sp, #4] + 8005bca: 6b3b ldr r3, [r7, #48] ; 0x30 + 8005bcc: 9300 str r3, [sp, #0] + 8005bce: 0023 movs r3, r4 + 8005bd0: f000 f810 bl 8005bf4 + prvAddNewTaskToReadyList( pxNewTCB ); + 8005bd4: 69fb ldr r3, [r7, #28] + 8005bd6: 0018 movs r0, r3 + 8005bd8: f000 f89a bl 8005d10 + xReturn = pdPASS; + 8005bdc: 2301 movs r3, #1 + 8005bde: 61bb str r3, [r7, #24] + 8005be0: e002 b.n 8005be8 + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + 8005be2: 2301 movs r3, #1 + 8005be4: 425b negs r3, r3 + 8005be6: 61bb str r3, [r7, #24] + } + + return xReturn; + 8005be8: 69bb ldr r3, [r7, #24] + } + 8005bea: 0018 movs r0, r3 + 8005bec: 46bd mov sp, r7 + 8005bee: b009 add sp, #36 ; 0x24 + 8005bf0: bd90 pop {r4, r7, pc} + ... + +08005bf4 : + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t *pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + 8005bf4: b580 push {r7, lr} + 8005bf6: b086 sub sp, #24 + 8005bf8: af00 add r7, sp, #0 + 8005bfa: 60f8 str r0, [r7, #12] + 8005bfc: 60b9 str r1, [r7, #8] + 8005bfe: 607a str r2, [r7, #4] + 8005c00: 603b str r3, [r7, #0] + + /* Avoid dependency on memset() if it is not required. */ + #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) + { + /* Fill the stack with a known value to assist debugging. */ + ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); + 8005c02: 6abb ldr r3, [r7, #40] ; 0x28 + 8005c04: 6b18 ldr r0, [r3, #48] ; 0x30 + 8005c06: 687b ldr r3, [r7, #4] + 8005c08: 009b lsls r3, r3, #2 + 8005c0a: 001a movs r2, r3 + 8005c0c: 21a5 movs r1, #165 ; 0xa5 + 8005c0e: f001 fdd6 bl 80077be + grows from high memory to low (as per the 80x86) or vice versa. + portSTACK_GROWTH is used to make the result positive or negative as required + by the port. */ + #if( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); + 8005c12: 6abb ldr r3, [r7, #40] ; 0x28 + 8005c14: 6b1a ldr r2, [r3, #48] ; 0x30 + 8005c16: 687b ldr r3, [r7, #4] + 8005c18: 493c ldr r1, [pc, #240] ; (8005d0c ) + 8005c1a: 468c mov ip, r1 + 8005c1c: 4463 add r3, ip + 8005c1e: 009b lsls r3, r3, #2 + 8005c20: 18d3 adds r3, r2, r3 + 8005c22: 613b str r3, [r7, #16] + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + 8005c24: 693b ldr r3, [r7, #16] + 8005c26: 2207 movs r2, #7 + 8005c28: 4393 bics r3, r2 + 8005c2a: 613b str r3, [r7, #16] + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + 8005c2c: 693b ldr r3, [r7, #16] + 8005c2e: 2207 movs r2, #7 + 8005c30: 4013 ands r3, r2 + 8005c32: d001 beq.n 8005c38 + 8005c34: b672 cpsid i + 8005c36: e7fe b.n 8005c36 + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if( pcName != NULL ) + 8005c38: 68bb ldr r3, [r7, #8] + 8005c3a: 2b00 cmp r3, #0 + 8005c3c: d020 beq.n 8005c80 + { + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 8005c3e: 2300 movs r3, #0 + 8005c40: 617b str r3, [r7, #20] + 8005c42: e013 b.n 8005c6c + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + 8005c44: 68ba ldr r2, [r7, #8] + 8005c46: 697b ldr r3, [r7, #20] + 8005c48: 18d3 adds r3, r2, r3 + 8005c4a: 7818 ldrb r0, [r3, #0] + 8005c4c: 6aba ldr r2, [r7, #40] ; 0x28 + 8005c4e: 2134 movs r1, #52 ; 0x34 + 8005c50: 697b ldr r3, [r7, #20] + 8005c52: 18d3 adds r3, r2, r3 + 8005c54: 185b adds r3, r3, r1 + 8005c56: 1c02 adds r2, r0, #0 + 8005c58: 701a strb r2, [r3, #0] + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + configMAX_TASK_NAME_LEN characters just in case the memory after the + string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + 8005c5a: 68ba ldr r2, [r7, #8] + 8005c5c: 697b ldr r3, [r7, #20] + 8005c5e: 18d3 adds r3, r2, r3 + 8005c60: 781b ldrb r3, [r3, #0] + 8005c62: 2b00 cmp r3, #0 + 8005c64: d006 beq.n 8005c74 + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 8005c66: 697b ldr r3, [r7, #20] + 8005c68: 3301 adds r3, #1 + 8005c6a: 617b str r3, [r7, #20] + 8005c6c: 697b ldr r3, [r7, #20] + 8005c6e: 2b0f cmp r3, #15 + 8005c70: d9e8 bls.n 8005c44 + 8005c72: e000 b.n 8005c76 + { + break; + 8005c74: 46c0 nop ; (mov r8, r8) + } + } + + /* Ensure the name string is terminated in the case that the string length + was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + 8005c76: 6abb ldr r3, [r7, #40] ; 0x28 + 8005c78: 2243 movs r2, #67 ; 0x43 + 8005c7a: 2100 movs r1, #0 + 8005c7c: 5499 strb r1, [r3, r2] + 8005c7e: e003 b.n 8005c88 + } + else + { + /* The task has not been given a name, so just ensure there is a NULL + terminator when it is read out. */ + pxNewTCB->pcTaskName[ 0 ] = 0x00; + 8005c80: 6abb ldr r3, [r7, #40] ; 0x28 + 8005c82: 2234 movs r2, #52 ; 0x34 + 8005c84: 2100 movs r1, #0 + 8005c86: 5499 strb r1, [r3, r2] + } + + /* This is used as an array index so must ensure it's not too large. First + remove the privilege bit if one is present. */ + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + 8005c88: 6a3b ldr r3, [r7, #32] + 8005c8a: 2b37 cmp r3, #55 ; 0x37 + 8005c8c: d901 bls.n 8005c92 + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + 8005c8e: 2337 movs r3, #55 ; 0x37 + 8005c90: 623b str r3, [r7, #32] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + 8005c92: 6abb ldr r3, [r7, #40] ; 0x28 + 8005c94: 6a3a ldr r2, [r7, #32] + 8005c96: 62da str r2, [r3, #44] ; 0x2c + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + 8005c98: 6abb ldr r3, [r7, #40] ; 0x28 + 8005c9a: 6a3a ldr r2, [r7, #32] + 8005c9c: 64da str r2, [r3, #76] ; 0x4c + pxNewTCB->uxMutexesHeld = 0; + 8005c9e: 6abb ldr r3, [r7, #40] ; 0x28 + 8005ca0: 2200 movs r2, #0 + 8005ca2: 651a str r2, [r3, #80] ; 0x50 + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + 8005ca4: 6abb ldr r3, [r7, #40] ; 0x28 + 8005ca6: 3304 adds r3, #4 + 8005ca8: 0018 movs r0, r3 + 8005caa: f7ff fa25 bl 80050f8 + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + 8005cae: 6abb ldr r3, [r7, #40] ; 0x28 + 8005cb0: 3318 adds r3, #24 + 8005cb2: 0018 movs r0, r3 + 8005cb4: f7ff fa20 bl 80050f8 + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + 8005cb8: 6abb ldr r3, [r7, #40] ; 0x28 + 8005cba: 6aba ldr r2, [r7, #40] ; 0x28 + 8005cbc: 611a str r2, [r3, #16] + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8005cbe: 6a3b ldr r3, [r7, #32] + 8005cc0: 2238 movs r2, #56 ; 0x38 + 8005cc2: 1ad2 subs r2, r2, r3 + 8005cc4: 6abb ldr r3, [r7, #40] ; 0x28 + 8005cc6: 619a str r2, [r3, #24] + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + 8005cc8: 6abb ldr r3, [r7, #40] ; 0x28 + 8005cca: 6aba ldr r2, [r7, #40] ; 0x28 + 8005ccc: 625a str r2, [r3, #36] ; 0x24 + } + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + pxNewTCB->ulNotifiedValue = 0; + 8005cce: 6abb ldr r3, [r7, #40] ; 0x28 + 8005cd0: 2200 movs r2, #0 + 8005cd2: 655a str r2, [r3, #84] ; 0x54 + pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; + 8005cd4: 6abb ldr r3, [r7, #40] ; 0x28 + 8005cd6: 2258 movs r2, #88 ; 0x58 + 8005cd8: 2100 movs r1, #0 + 8005cda: 5499 strb r1, [r3, r2] + } + #endif + + #if( INCLUDE_xTaskAbortDelay == 1 ) + { + pxNewTCB->ucDelayAborted = pdFALSE; + 8005cdc: 6abb ldr r3, [r7, #40] ; 0x28 + 8005cde: 225a movs r2, #90 ; 0x5a + 8005ce0: 2100 movs r1, #0 + 8005ce2: 5499 strb r1, [r3, r2] + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + 8005ce4: 683a ldr r2, [r7, #0] + 8005ce6: 68f9 ldr r1, [r7, #12] + 8005ce8: 693b ldr r3, [r7, #16] + 8005cea: 0018 movs r0, r3 + 8005cec: f001 f980 bl 8006ff0 + 8005cf0: 0002 movs r2, r0 + 8005cf2: 6abb ldr r3, [r7, #40] ; 0x28 + 8005cf4: 601a str r2, [r3, #0] + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #endif /* portUSING_MPU_WRAPPERS */ + + if( pxCreatedTask != NULL ) + 8005cf6: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005cf8: 2b00 cmp r3, #0 + 8005cfa: d002 beq.n 8005d02 + { + /* Pass the handle out in an anonymous way. The handle can be used to + change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + 8005cfc: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005cfe: 6aba ldr r2, [r7, #40] ; 0x28 + 8005d00: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 8005d02: 46c0 nop ; (mov r8, r8) + 8005d04: 46bd mov sp, r7 + 8005d06: b006 add sp, #24 + 8005d08: bd80 pop {r7, pc} + 8005d0a: 46c0 nop ; (mov r8, r8) + 8005d0c: 3fffffff .word 0x3fffffff + +08005d10 : +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) +{ + 8005d10: b580 push {r7, lr} + 8005d12: b082 sub sp, #8 + 8005d14: af00 add r7, sp, #0 + 8005d16: 6078 str r0, [r7, #4] + /* Ensure interrupts don't access the task lists while the lists are being + updated. */ + taskENTER_CRITICAL(); + 8005d18: f001 fa02 bl 8007120 + { + uxCurrentNumberOfTasks++; + 8005d1c: 4b2a ldr r3, [pc, #168] ; (8005dc8 ) + 8005d1e: 681b ldr r3, [r3, #0] + 8005d20: 1c5a adds r2, r3, #1 + 8005d22: 4b29 ldr r3, [pc, #164] ; (8005dc8 ) + 8005d24: 601a str r2, [r3, #0] + if( pxCurrentTCB == NULL ) + 8005d26: 4b29 ldr r3, [pc, #164] ; (8005dcc ) + 8005d28: 681b ldr r3, [r3, #0] + 8005d2a: 2b00 cmp r3, #0 + 8005d2c: d109 bne.n 8005d42 + { + /* There are no other tasks, or all the other tasks are in + the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + 8005d2e: 4b27 ldr r3, [pc, #156] ; (8005dcc ) + 8005d30: 687a ldr r2, [r7, #4] + 8005d32: 601a str r2, [r3, #0] + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + 8005d34: 4b24 ldr r3, [pc, #144] ; (8005dc8 ) + 8005d36: 681b ldr r3, [r3, #0] + 8005d38: 2b01 cmp r3, #1 + 8005d3a: d110 bne.n 8005d5e + { + /* This is the first task to be created so do the preliminary + initialisation required. We will not recover if this call + fails, but we will report the failure. */ + prvInitialiseTaskLists(); + 8005d3c: f000 fcbc bl 80066b8 + 8005d40: e00d b.n 8005d5e + else + { + /* If the scheduler is not already running, make this task the + current task if it is the highest priority task to be created + so far. */ + if( xSchedulerRunning == pdFALSE ) + 8005d42: 4b23 ldr r3, [pc, #140] ; (8005dd0 ) + 8005d44: 681b ldr r3, [r3, #0] + 8005d46: 2b00 cmp r3, #0 + 8005d48: d109 bne.n 8005d5e + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + 8005d4a: 4b20 ldr r3, [pc, #128] ; (8005dcc ) + 8005d4c: 681b ldr r3, [r3, #0] + 8005d4e: 6ada ldr r2, [r3, #44] ; 0x2c + 8005d50: 687b ldr r3, [r7, #4] + 8005d52: 6adb ldr r3, [r3, #44] ; 0x2c + 8005d54: 429a cmp r2, r3 + 8005d56: d802 bhi.n 8005d5e + { + pxCurrentTCB = pxNewTCB; + 8005d58: 4b1c ldr r3, [pc, #112] ; (8005dcc ) + 8005d5a: 687a ldr r2, [r7, #4] + 8005d5c: 601a str r2, [r3, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + 8005d5e: 4b1d ldr r3, [pc, #116] ; (8005dd4 ) + 8005d60: 681b ldr r3, [r3, #0] + 8005d62: 1c5a adds r2, r3, #1 + 8005d64: 4b1b ldr r3, [pc, #108] ; (8005dd4 ) + 8005d66: 601a str r2, [r3, #0] + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + 8005d68: 4b1a ldr r3, [pc, #104] ; (8005dd4 ) + 8005d6a: 681a ldr r2, [r3, #0] + 8005d6c: 687b ldr r3, [r7, #4] + 8005d6e: 645a str r2, [r3, #68] ; 0x44 + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + 8005d70: 687b ldr r3, [r7, #4] + 8005d72: 6ada ldr r2, [r3, #44] ; 0x2c + 8005d74: 4b18 ldr r3, [pc, #96] ; (8005dd8 ) + 8005d76: 681b ldr r3, [r3, #0] + 8005d78: 429a cmp r2, r3 + 8005d7a: d903 bls.n 8005d84 + 8005d7c: 687b ldr r3, [r7, #4] + 8005d7e: 6ada ldr r2, [r3, #44] ; 0x2c + 8005d80: 4b15 ldr r3, [pc, #84] ; (8005dd8 ) + 8005d82: 601a str r2, [r3, #0] + 8005d84: 687b ldr r3, [r7, #4] + 8005d86: 6ada ldr r2, [r3, #44] ; 0x2c + 8005d88: 0013 movs r3, r2 + 8005d8a: 009b lsls r3, r3, #2 + 8005d8c: 189b adds r3, r3, r2 + 8005d8e: 009b lsls r3, r3, #2 + 8005d90: 4a12 ldr r2, [pc, #72] ; (8005ddc ) + 8005d92: 189a adds r2, r3, r2 + 8005d94: 687b ldr r3, [r7, #4] + 8005d96: 3304 adds r3, #4 + 8005d98: 0019 movs r1, r3 + 8005d9a: 0010 movs r0, r2 + 8005d9c: f7ff f9b7 bl 800510e + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + 8005da0: f001 f9d0 bl 8007144 + + if( xSchedulerRunning != pdFALSE ) + 8005da4: 4b0a ldr r3, [pc, #40] ; (8005dd0 ) + 8005da6: 681b ldr r3, [r3, #0] + 8005da8: 2b00 cmp r3, #0 + 8005daa: d008 beq.n 8005dbe + { + /* If the created task is of a higher priority than the current task + then it should run now. */ + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + 8005dac: 4b07 ldr r3, [pc, #28] ; (8005dcc ) + 8005dae: 681b ldr r3, [r3, #0] + 8005db0: 6ada ldr r2, [r3, #44] ; 0x2c + 8005db2: 687b ldr r3, [r7, #4] + 8005db4: 6adb ldr r3, [r3, #44] ; 0x2c + 8005db6: 429a cmp r2, r3 + 8005db8: d201 bcs.n 8005dbe + { + taskYIELD_IF_USING_PREEMPTION(); + 8005dba: f001 f9a1 bl 8007100 + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 8005dbe: 46c0 nop ; (mov r8, r8) + 8005dc0: 46bd mov sp, r7 + 8005dc2: b002 add sp, #8 + 8005dc4: bd80 pop {r7, pc} + 8005dc6: 46c0 nop ; (mov r8, r8) + 8005dc8: 20000bc0 .word 0x20000bc0 + 8005dcc: 200006ec .word 0x200006ec + 8005dd0: 20000bcc .word 0x20000bcc + 8005dd4: 20000bdc .word 0x20000bdc + 8005dd8: 20000bc8 .word 0x20000bc8 + 8005ddc: 200006f0 .word 0x200006f0 + +08005de0 : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + 8005de0: b580 push {r7, lr} + 8005de2: b084 sub sp, #16 + 8005de4: af00 add r7, sp, #0 + 8005de6: 6078 str r0, [r7, #4] + BaseType_t xAlreadyYielded = pdFALSE; + 8005de8: 2300 movs r3, #0 + 8005dea: 60fb str r3, [r7, #12] + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + 8005dec: 687b ldr r3, [r7, #4] + 8005dee: 2b00 cmp r3, #0 + 8005df0: d010 beq.n 8005e14 + { + configASSERT( uxSchedulerSuspended == 0 ); + 8005df2: 4b0d ldr r3, [pc, #52] ; (8005e28 ) + 8005df4: 681b ldr r3, [r3, #0] + 8005df6: 2b00 cmp r3, #0 + 8005df8: d001 beq.n 8005dfe + 8005dfa: b672 cpsid i + 8005dfc: e7fe b.n 8005dfc + vTaskSuspendAll(); + 8005dfe: f000 f8dd bl 8005fbc + list or removed from the blocked list until the scheduler + is resumed. + + This task cannot be in an event list as it is the currently + executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + 8005e02: 687b ldr r3, [r7, #4] + 8005e04: 2100 movs r1, #0 + 8005e06: 0018 movs r0, r3 + 8005e08: f000 fd86 bl 8006918 + } + xAlreadyYielded = xTaskResumeAll(); + 8005e0c: f000 f918 bl 8006040 + 8005e10: 0003 movs r3, r0 + 8005e12: 60fb str r3, [r7, #12] + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + 8005e14: 68fb ldr r3, [r7, #12] + 8005e16: 2b00 cmp r3, #0 + 8005e18: d101 bne.n 8005e1e + { + portYIELD_WITHIN_API(); + 8005e1a: f001 f971 bl 8007100 + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + 8005e1e: 46c0 nop ; (mov r8, r8) + 8005e20: 46bd mov sp, r7 + 8005e22: b004 add sp, #16 + 8005e24: bd80 pop {r7, pc} + 8005e26: 46c0 nop ; (mov r8, r8) + 8005e28: 20000be8 .word 0x20000be8 + +08005e2c : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) + { + 8005e2c: b580 push {r7, lr} + 8005e2e: b084 sub sp, #16 + 8005e30: af00 add r7, sp, #0 + 8005e32: 6078 str r0, [r7, #4] + BaseType_t xReturn = pdFALSE; + 8005e34: 2300 movs r3, #0 + 8005e36: 60fb str r3, [r7, #12] + const TCB_t * const pxTCB = xTask; + 8005e38: 687b ldr r3, [r7, #4] + 8005e3a: 60bb str r3, [r7, #8] + + /* Accesses xPendingReadyList so must be called from a critical + section. */ + + /* It does not make sense to check if the calling task is suspended. */ + configASSERT( xTask ); + 8005e3c: 687b ldr r3, [r7, #4] + 8005e3e: 2b00 cmp r3, #0 + 8005e40: d101 bne.n 8005e46 + 8005e42: b672 cpsid i + 8005e44: e7fe b.n 8005e44 + + /* Is the task being resumed actually in the suspended list? */ + if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE ) + 8005e46: 68bb ldr r3, [r7, #8] + 8005e48: 695a ldr r2, [r3, #20] + 8005e4a: 4b09 ldr r3, [pc, #36] ; (8005e70 ) + 8005e4c: 429a cmp r2, r3 + 8005e4e: d10a bne.n 8005e66 + { + /* Has the task already been resumed from within an ISR? */ + if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE ) + 8005e50: 68bb ldr r3, [r7, #8] + 8005e52: 6a9a ldr r2, [r3, #40] ; 0x28 + 8005e54: 4b07 ldr r3, [pc, #28] ; (8005e74 ) + 8005e56: 429a cmp r2, r3 + 8005e58: d005 beq.n 8005e66 + { + /* Is it in the suspended list because it is in the Suspended + state, or because is is blocked with no timeout? */ + if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961. The cast is only redundant when NULL is used. */ + 8005e5a: 68bb ldr r3, [r7, #8] + 8005e5c: 6a9b ldr r3, [r3, #40] ; 0x28 + 8005e5e: 2b00 cmp r3, #0 + 8005e60: d101 bne.n 8005e66 + { + xReturn = pdTRUE; + 8005e62: 2301 movs r3, #1 + 8005e64: 60fb str r3, [r7, #12] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + 8005e66: 68fb ldr r3, [r7, #12] + } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + 8005e68: 0018 movs r0, r3 + 8005e6a: 46bd mov sp, r7 + 8005e6c: b004 add sp, #16 + 8005e6e: bd80 pop {r7, pc} + 8005e70: 20000bac .word 0x20000bac + 8005e74: 20000b80 .word 0x20000b80 + +08005e78 : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskResume( TaskHandle_t xTaskToResume ) + { + 8005e78: b580 push {r7, lr} + 8005e7a: b084 sub sp, #16 + 8005e7c: af00 add r7, sp, #0 + 8005e7e: 6078 str r0, [r7, #4] + TCB_t * const pxTCB = xTaskToResume; + 8005e80: 687b ldr r3, [r7, #4] + 8005e82: 60fb str r3, [r7, #12] + + /* It does not make sense to resume the calling task. */ + configASSERT( xTaskToResume ); + 8005e84: 687b ldr r3, [r7, #4] + 8005e86: 2b00 cmp r3, #0 + 8005e88: d101 bne.n 8005e8e + 8005e8a: b672 cpsid i + 8005e8c: e7fe b.n 8005e8c + + /* The parameter cannot be NULL as it is impossible to resume the + currently executing task. */ + if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) ) + 8005e8e: 4b1e ldr r3, [pc, #120] ; (8005f08 ) + 8005e90: 681b ldr r3, [r3, #0] + 8005e92: 68fa ldr r2, [r7, #12] + 8005e94: 429a cmp r2, r3 + 8005e96: d032 beq.n 8005efe + 8005e98: 68fb ldr r3, [r7, #12] + 8005e9a: 2b00 cmp r3, #0 + 8005e9c: d02f beq.n 8005efe + { + taskENTER_CRITICAL(); + 8005e9e: f001 f93f bl 8007120 + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + 8005ea2: 68fb ldr r3, [r7, #12] + 8005ea4: 0018 movs r0, r3 + 8005ea6: f7ff ffc1 bl 8005e2c + 8005eaa: 1e03 subs r3, r0, #0 + 8005eac: d025 beq.n 8005efa + { + traceTASK_RESUME( pxTCB ); + + /* The ready list can be accessed even if the scheduler is + suspended because this is inside a critical section. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8005eae: 68fb ldr r3, [r7, #12] + 8005eb0: 3304 adds r3, #4 + 8005eb2: 0018 movs r0, r3 + 8005eb4: f7ff f983 bl 80051be + prvAddTaskToReadyList( pxTCB ); + 8005eb8: 68fb ldr r3, [r7, #12] + 8005eba: 6ada ldr r2, [r3, #44] ; 0x2c + 8005ebc: 4b13 ldr r3, [pc, #76] ; (8005f0c ) + 8005ebe: 681b ldr r3, [r3, #0] + 8005ec0: 429a cmp r2, r3 + 8005ec2: d903 bls.n 8005ecc + 8005ec4: 68fb ldr r3, [r7, #12] + 8005ec6: 6ada ldr r2, [r3, #44] ; 0x2c + 8005ec8: 4b10 ldr r3, [pc, #64] ; (8005f0c ) + 8005eca: 601a str r2, [r3, #0] + 8005ecc: 68fb ldr r3, [r7, #12] + 8005ece: 6ada ldr r2, [r3, #44] ; 0x2c + 8005ed0: 0013 movs r3, r2 + 8005ed2: 009b lsls r3, r3, #2 + 8005ed4: 189b adds r3, r3, r2 + 8005ed6: 009b lsls r3, r3, #2 + 8005ed8: 4a0d ldr r2, [pc, #52] ; (8005f10 ) + 8005eda: 189a adds r2, r3, r2 + 8005edc: 68fb ldr r3, [r7, #12] + 8005ede: 3304 adds r3, #4 + 8005ee0: 0019 movs r1, r3 + 8005ee2: 0010 movs r0, r2 + 8005ee4: f7ff f913 bl 800510e + + /* A higher priority task may have just been resumed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 8005ee8: 68fb ldr r3, [r7, #12] + 8005eea: 6ada ldr r2, [r3, #44] ; 0x2c + 8005eec: 4b06 ldr r3, [pc, #24] ; (8005f08 ) + 8005eee: 681b ldr r3, [r3, #0] + 8005ef0: 6adb ldr r3, [r3, #44] ; 0x2c + 8005ef2: 429a cmp r2, r3 + 8005ef4: d301 bcc.n 8005efa + { + /* This yield may not cause the task just resumed to run, + but will leave the lists in the correct state for the + next yield. */ + taskYIELD_IF_USING_PREEMPTION(); + 8005ef6: f001 f903 bl 8007100 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + 8005efa: f001 f923 bl 8007144 + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + 8005efe: 46c0 nop ; (mov r8, r8) + 8005f00: 46bd mov sp, r7 + 8005f02: b004 add sp, #16 + 8005f04: bd80 pop {r7, pc} + 8005f06: 46c0 nop ; (mov r8, r8) + 8005f08: 200006ec .word 0x200006ec + 8005f0c: 20000bc8 .word 0x20000bc8 + 8005f10: 200006f0 .word 0x200006f0 + +08005f14 : + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler( void ) +{ + 8005f14: b590 push {r4, r7, lr} + 8005f16: b089 sub sp, #36 ; 0x24 + 8005f18: af04 add r7, sp, #16 +BaseType_t xReturn; + + /* Add the idle task at the lowest priority. */ + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t *pxIdleTaskTCBBuffer = NULL; + 8005f1a: 2300 movs r3, #0 + 8005f1c: 60bb str r3, [r7, #8] + StackType_t *pxIdleTaskStackBuffer = NULL; + 8005f1e: 2300 movs r3, #0 + 8005f20: 607b str r3, [r7, #4] + uint32_t ulIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + address of the RAM then create the idle task. */ + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); + 8005f22: 003a movs r2, r7 + 8005f24: 1d39 adds r1, r7, #4 + 8005f26: 2308 movs r3, #8 + 8005f28: 18fb adds r3, r7, r3 + 8005f2a: 0018 movs r0, r3 + 8005f2c: f7ff f896 bl 800505c + xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, + 8005f30: 683c ldr r4, [r7, #0] + 8005f32: 687b ldr r3, [r7, #4] + 8005f34: 68ba ldr r2, [r7, #8] + 8005f36: 491b ldr r1, [pc, #108] ; (8005fa4 ) + 8005f38: 481b ldr r0, [pc, #108] ; (8005fa8 ) + 8005f3a: 9202 str r2, [sp, #8] + 8005f3c: 9301 str r3, [sp, #4] + 8005f3e: 2300 movs r3, #0 + 8005f40: 9300 str r3, [sp, #0] + 8005f42: 2300 movs r3, #0 + 8005f44: 0022 movs r2, r4 + 8005f46: f7ff fdc4 bl 8005ad2 + 8005f4a: 0002 movs r2, r0 + 8005f4c: 4b17 ldr r3, [pc, #92] ; (8005fac ) + 8005f4e: 601a str r2, [r3, #0] + ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + + if( xIdleTaskHandle != NULL ) + 8005f50: 4b16 ldr r3, [pc, #88] ; (8005fac ) + 8005f52: 681b ldr r3, [r3, #0] + 8005f54: 2b00 cmp r3, #0 + 8005f56: d002 beq.n 8005f5e + { + xReturn = pdPASS; + 8005f58: 2301 movs r3, #1 + 8005f5a: 60fb str r3, [r7, #12] + 8005f5c: e001 b.n 8005f62 + } + else + { + xReturn = pdFAIL; + 8005f5e: 2300 movs r3, #0 + 8005f60: 60fb str r3, [r7, #12] + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + #if ( configUSE_TIMERS == 1 ) + { + if( xReturn == pdPASS ) + 8005f62: 68fb ldr r3, [r7, #12] + 8005f64: 2b01 cmp r3, #1 + 8005f66: d103 bne.n 8005f70 + { + xReturn = xTimerCreateTimerTask(); + 8005f68: f000 fd30 bl 80069cc + 8005f6c: 0003 movs r3, r0 + 8005f6e: 60fb str r3, [r7, #12] + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TIMERS */ + + if( xReturn == pdPASS ) + 8005f70: 68fb ldr r3, [r7, #12] + 8005f72: 2b01 cmp r3, #1 + 8005f74: d10d bne.n 8005f92 + /* Interrupts are turned off here, to ensure a tick does not occur + before or during the call to xPortStartScheduler(). The stacks of + the created tasks contain a status word with interrupts switched on + so interrupts will automatically get re-enabled when the first task + starts to run. */ + portDISABLE_INTERRUPTS(); + 8005f76: b672 cpsid i + structure specific to the task that will run first. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + + xNextTaskUnblockTime = portMAX_DELAY; + 8005f78: 4b0d ldr r3, [pc, #52] ; (8005fb0 ) + 8005f7a: 2201 movs r2, #1 + 8005f7c: 4252 negs r2, r2 + 8005f7e: 601a str r2, [r3, #0] + xSchedulerRunning = pdTRUE; + 8005f80: 4b0c ldr r3, [pc, #48] ; (8005fb4 ) + 8005f82: 2201 movs r2, #1 + 8005f84: 601a str r2, [r3, #0] + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; + 8005f86: 4b0c ldr r3, [pc, #48] ; (8005fb8 ) + 8005f88: 2200 movs r2, #0 + 8005f8a: 601a str r2, [r3, #0] + + traceTASK_SWITCHED_IN(); + + /* Setting up the timer tick is hardware specific and thus in the + portable interface. */ + if( xPortStartScheduler() != pdFALSE ) + 8005f8c: f001 f894 bl 80070b8 + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + meaning xIdleTaskHandle is not used anywhere else. */ + ( void ) xIdleTaskHandle; +} + 8005f90: e004 b.n 8005f9c + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + 8005f92: 68fb ldr r3, [r7, #12] + 8005f94: 3301 adds r3, #1 + 8005f96: d101 bne.n 8005f9c + 8005f98: b672 cpsid i + 8005f9a: e7fe b.n 8005f9a +} + 8005f9c: 46c0 nop ; (mov r8, r8) + 8005f9e: 46bd mov sp, r7 + 8005fa0: b005 add sp, #20 + 8005fa2: bd90 pop {r4, r7, pc} + 8005fa4: 08007804 .word 0x08007804 + 8005fa8: 080065f1 .word 0x080065f1 + 8005fac: 20000be4 .word 0x20000be4 + 8005fb0: 20000be0 .word 0x20000be0 + 8005fb4: 20000bcc .word 0x20000bcc + 8005fb8: 20000bc4 .word 0x20000bc4 + +08005fbc : + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + 8005fbc: b580 push {r7, lr} + 8005fbe: af00 add r7, sp, #0 + /* A critical section is not required as the variable is of type + BaseType_t. Please read Richard Barry's reply in the following link to a + post in the FreeRTOS support forum before reporting this as a bug! - + http://goo.gl/wu4acr */ + ++uxSchedulerSuspended; + 8005fc0: 4b03 ldr r3, [pc, #12] ; (8005fd0 ) + 8005fc2: 681b ldr r3, [r3, #0] + 8005fc4: 1c5a adds r2, r3, #1 + 8005fc6: 4b02 ldr r3, [pc, #8] ; (8005fd0 ) + 8005fc8: 601a str r2, [r3, #0] + portMEMORY_BARRIER(); +} + 8005fca: 46c0 nop ; (mov r8, r8) + 8005fcc: 46bd mov sp, r7 + 8005fce: bd80 pop {r7, pc} + 8005fd0: 20000be8 .word 0x20000be8 + +08005fd4 : +/*----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) + { + 8005fd4: b580 push {r7, lr} + 8005fd6: b082 sub sp, #8 + 8005fd8: af00 add r7, sp, #0 + TickType_t xReturn; + UBaseType_t uxHigherPriorityReadyTasks = pdFALSE; + 8005fda: 2300 movs r3, #0 + 8005fdc: 603b str r3, [r7, #0] + configUSE_PREEMPTION is 0, so there may be tasks above the idle priority + task that are in the Ready state, even though the idle task is + running. */ + #if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + { + if( uxTopReadyPriority > tskIDLE_PRIORITY ) + 8005fde: 4b13 ldr r3, [pc, #76] ; (800602c ) + 8005fe0: 681b ldr r3, [r3, #0] + 8005fe2: 2b00 cmp r3, #0 + 8005fe4: d001 beq.n 8005fea + { + uxHigherPriorityReadyTasks = pdTRUE; + 8005fe6: 2301 movs r3, #1 + 8005fe8: 603b str r3, [r7, #0] + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #endif + + if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY ) + 8005fea: 4b11 ldr r3, [pc, #68] ; (8006030 ) + 8005fec: 681b ldr r3, [r3, #0] + 8005fee: 6adb ldr r3, [r3, #44] ; 0x2c + 8005ff0: 2b00 cmp r3, #0 + 8005ff2: d002 beq.n 8005ffa + { + xReturn = 0; + 8005ff4: 2300 movs r3, #0 + 8005ff6: 607b str r3, [r7, #4] + 8005ff8: e012 b.n 8006020 + } + else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 ) + 8005ffa: 4b0e ldr r3, [pc, #56] ; (8006034 ) + 8005ffc: 681b ldr r3, [r3, #0] + 8005ffe: 2b01 cmp r3, #1 + 8006000: d902 bls.n 8006008 + { + /* There are other idle priority tasks in the ready state. If + time slicing is used then the very next tick interrupt must be + processed. */ + xReturn = 0; + 8006002: 2300 movs r3, #0 + 8006004: 607b str r3, [r7, #4] + 8006006: e00b b.n 8006020 + } + else if( uxHigherPriorityReadyTasks != pdFALSE ) + 8006008: 683b ldr r3, [r7, #0] + 800600a: 2b00 cmp r3, #0 + 800600c: d002 beq.n 8006014 + { + /* There are tasks in the Ready state that have a priority above the + idle priority. This path can only be reached if + configUSE_PREEMPTION is 0. */ + xReturn = 0; + 800600e: 2300 movs r3, #0 + 8006010: 607b str r3, [r7, #4] + 8006012: e005 b.n 8006020 + } + else + { + xReturn = xNextTaskUnblockTime - xTickCount; + 8006014: 4b08 ldr r3, [pc, #32] ; (8006038 ) + 8006016: 681a ldr r2, [r3, #0] + 8006018: 4b08 ldr r3, [pc, #32] ; (800603c ) + 800601a: 681b ldr r3, [r3, #0] + 800601c: 1ad3 subs r3, r2, r3 + 800601e: 607b str r3, [r7, #4] + } + + return xReturn; + 8006020: 687b ldr r3, [r7, #4] + } + 8006022: 0018 movs r0, r3 + 8006024: 46bd mov sp, r7 + 8006026: b002 add sp, #8 + 8006028: bd80 pop {r7, pc} + 800602a: 46c0 nop ; (mov r8, r8) + 800602c: 20000bc8 .word 0x20000bc8 + 8006030: 200006ec .word 0x200006ec + 8006034: 200006f0 .word 0x200006f0 + 8006038: 20000be0 .word 0x20000be0 + 800603c: 20000bc4 .word 0x20000bc4 + +08006040 : + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + 8006040: b580 push {r7, lr} + 8006042: b084 sub sp, #16 + 8006044: af00 add r7, sp, #0 +TCB_t *pxTCB = NULL; + 8006046: 2300 movs r3, #0 + 8006048: 60fb str r3, [r7, #12] +BaseType_t xAlreadyYielded = pdFALSE; + 800604a: 2300 movs r3, #0 + 800604c: 60bb str r3, [r7, #8] + + /* If uxSchedulerSuspended is zero then this function does not match a + previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended ); + 800604e: 4b3a ldr r3, [pc, #232] ; (8006138 ) + 8006050: 681b ldr r3, [r3, #0] + 8006052: 2b00 cmp r3, #0 + 8006054: d101 bne.n 800605a + 8006056: b672 cpsid i + 8006058: e7fe b.n 8006058 + /* It is possible that an ISR caused a task to be removed from an event + list while the scheduler was suspended. If this was the case then the + removed task will have been added to the xPendingReadyList. Once the + scheduler has been resumed it is safe to move all the pending ready + tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + 800605a: f001 f861 bl 8007120 + { + --uxSchedulerSuspended; + 800605e: 4b36 ldr r3, [pc, #216] ; (8006138 ) + 8006060: 681b ldr r3, [r3, #0] + 8006062: 1e5a subs r2, r3, #1 + 8006064: 4b34 ldr r3, [pc, #208] ; (8006138 ) + 8006066: 601a str r2, [r3, #0] + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 8006068: 4b33 ldr r3, [pc, #204] ; (8006138 ) + 800606a: 681b ldr r3, [r3, #0] + 800606c: 2b00 cmp r3, #0 + 800606e: d15b bne.n 8006128 + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + 8006070: 4b32 ldr r3, [pc, #200] ; (800613c ) + 8006072: 681b ldr r3, [r3, #0] + 8006074: 2b00 cmp r3, #0 + 8006076: d057 beq.n 8006128 + { + /* Move any readied tasks from the pending list into the + appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 8006078: e02f b.n 80060da + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800607a: 4b31 ldr r3, [pc, #196] ; (8006140 ) + 800607c: 68db ldr r3, [r3, #12] + 800607e: 68db ldr r3, [r3, #12] + 8006080: 60fb str r3, [r7, #12] + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 8006082: 68fb ldr r3, [r7, #12] + 8006084: 3318 adds r3, #24 + 8006086: 0018 movs r0, r3 + 8006088: f7ff f899 bl 80051be + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 800608c: 68fb ldr r3, [r7, #12] + 800608e: 3304 adds r3, #4 + 8006090: 0018 movs r0, r3 + 8006092: f7ff f894 bl 80051be + prvAddTaskToReadyList( pxTCB ); + 8006096: 68fb ldr r3, [r7, #12] + 8006098: 6ada ldr r2, [r3, #44] ; 0x2c + 800609a: 4b2a ldr r3, [pc, #168] ; (8006144 ) + 800609c: 681b ldr r3, [r3, #0] + 800609e: 429a cmp r2, r3 + 80060a0: d903 bls.n 80060aa + 80060a2: 68fb ldr r3, [r7, #12] + 80060a4: 6ada ldr r2, [r3, #44] ; 0x2c + 80060a6: 4b27 ldr r3, [pc, #156] ; (8006144 ) + 80060a8: 601a str r2, [r3, #0] + 80060aa: 68fb ldr r3, [r7, #12] + 80060ac: 6ada ldr r2, [r3, #44] ; 0x2c + 80060ae: 0013 movs r3, r2 + 80060b0: 009b lsls r3, r3, #2 + 80060b2: 189b adds r3, r3, r2 + 80060b4: 009b lsls r3, r3, #2 + 80060b6: 4a24 ldr r2, [pc, #144] ; (8006148 ) + 80060b8: 189a adds r2, r3, r2 + 80060ba: 68fb ldr r3, [r7, #12] + 80060bc: 3304 adds r3, #4 + 80060be: 0019 movs r1, r3 + 80060c0: 0010 movs r0, r2 + 80060c2: f7ff f824 bl 800510e + + /* If the moved task has a priority higher than the current + task then a yield must be performed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 80060c6: 68fb ldr r3, [r7, #12] + 80060c8: 6ada ldr r2, [r3, #44] ; 0x2c + 80060ca: 4b20 ldr r3, [pc, #128] ; (800614c ) + 80060cc: 681b ldr r3, [r3, #0] + 80060ce: 6adb ldr r3, [r3, #44] ; 0x2c + 80060d0: 429a cmp r2, r3 + 80060d2: d302 bcc.n 80060da + { + xYieldPending = pdTRUE; + 80060d4: 4b1e ldr r3, [pc, #120] ; (8006150 ) + 80060d6: 2201 movs r2, #1 + 80060d8: 601a str r2, [r3, #0] + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 80060da: 4b19 ldr r3, [pc, #100] ; (8006140 ) + 80060dc: 681b ldr r3, [r3, #0] + 80060de: 2b00 cmp r3, #0 + 80060e0: d1cb bne.n 800607a + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( pxTCB != NULL ) + 80060e2: 68fb ldr r3, [r7, #12] + 80060e4: 2b00 cmp r3, #0 + 80060e6: d001 beq.n 80060ec + which may have prevented the next unblock time from being + re-calculated, in which case re-calculate it now. Mainly + important for low power tickless implementations, where + this can prevent an unnecessary exit from low power + state. */ + prvResetNextTaskUnblockTime(); + 80060e8: f000 fb80 bl 80067ec + /* If any ticks occurred while the scheduler was suspended then + they should be processed now. This ensures the tick count does + not slip, and that any delayed tasks are resumed at the correct + time. */ + { + UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */ + 80060ec: 4b19 ldr r3, [pc, #100] ; (8006154 ) + 80060ee: 681b ldr r3, [r3, #0] + 80060f0: 607b str r3, [r7, #4] + + if( uxPendedCounts > ( UBaseType_t ) 0U ) + 80060f2: 687b ldr r3, [r7, #4] + 80060f4: 2b00 cmp r3, #0 + 80060f6: d00f beq.n 8006118 + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + 80060f8: f000 f858 bl 80061ac + 80060fc: 1e03 subs r3, r0, #0 + 80060fe: d002 beq.n 8006106 + { + xYieldPending = pdTRUE; + 8006100: 4b13 ldr r3, [pc, #76] ; (8006150 ) + 8006102: 2201 movs r2, #1 + 8006104: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + --uxPendedCounts; + 8006106: 687b ldr r3, [r7, #4] + 8006108: 3b01 subs r3, #1 + 800610a: 607b str r3, [r7, #4] + } while( uxPendedCounts > ( UBaseType_t ) 0U ); + 800610c: 687b ldr r3, [r7, #4] + 800610e: 2b00 cmp r3, #0 + 8006110: d1f2 bne.n 80060f8 + + uxPendedTicks = 0; + 8006112: 4b10 ldr r3, [pc, #64] ; (8006154 ) + 8006114: 2200 movs r2, #0 + 8006116: 601a str r2, [r3, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPending != pdFALSE ) + 8006118: 4b0d ldr r3, [pc, #52] ; (8006150 ) + 800611a: 681b ldr r3, [r3, #0] + 800611c: 2b00 cmp r3, #0 + 800611e: d003 beq.n 8006128 + { + #if( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + 8006120: 2301 movs r3, #1 + 8006122: 60bb str r3, [r7, #8] + } + #endif + taskYIELD_IF_USING_PREEMPTION(); + 8006124: f000 ffec bl 8007100 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + 8006128: f001 f80c bl 8007144 + + return xAlreadyYielded; + 800612c: 68bb ldr r3, [r7, #8] +} + 800612e: 0018 movs r0, r3 + 8006130: 46bd mov sp, r7 + 8006132: b004 add sp, #16 + 8006134: bd80 pop {r7, pc} + 8006136: 46c0 nop ; (mov r8, r8) + 8006138: 20000be8 .word 0x20000be8 + 800613c: 20000bc0 .word 0x20000bc0 + 8006140: 20000b80 .word 0x20000b80 + 8006144: 20000bc8 .word 0x20000bc8 + 8006148: 200006f0 .word 0x200006f0 + 800614c: 200006ec .word 0x200006ec + 8006150: 20000bd4 .word 0x20000bd4 + 8006154: 20000bd0 .word 0x20000bd0 + +08006158 : +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCount( void ) +{ + 8006158: b580 push {r7, lr} + 800615a: b082 sub sp, #8 + 800615c: af00 add r7, sp, #0 +TickType_t xTicks; + + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + 800615e: 4b04 ldr r3, [pc, #16] ; (8006170 ) + 8006160: 681b ldr r3, [r3, #0] + 8006162: 607b str r3, [r7, #4] + } + portTICK_TYPE_EXIT_CRITICAL(); + + return xTicks; + 8006164: 687b ldr r3, [r7, #4] +} + 8006166: 0018 movs r0, r3 + 8006168: 46bd mov sp, r7 + 800616a: b002 add sp, #8 + 800616c: bd80 pop {r7, pc} + 800616e: 46c0 nop ; (mov r8, r8) + 8006170: 20000bc4 .word 0x20000bc4 + +08006174 : +implementations require configUSE_TICKLESS_IDLE to be set to a value other than +1. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + void vTaskStepTick( const TickType_t xTicksToJump ) + { + 8006174: b580 push {r7, lr} + 8006176: b082 sub sp, #8 + 8006178: af00 add r7, sp, #0 + 800617a: 6078 str r0, [r7, #4] + /* Correct the tick count value after a period during which the tick + was suppressed. Note this does *not* call the tick hook function for + each stepped tick. */ + configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime ); + 800617c: 4b09 ldr r3, [pc, #36] ; (80061a4 ) + 800617e: 681a ldr r2, [r3, #0] + 8006180: 687b ldr r3, [r7, #4] + 8006182: 18d2 adds r2, r2, r3 + 8006184: 4b08 ldr r3, [pc, #32] ; (80061a8 ) + 8006186: 681b ldr r3, [r3, #0] + 8006188: 429a cmp r2, r3 + 800618a: d901 bls.n 8006190 + 800618c: b672 cpsid i + 800618e: e7fe b.n 800618e + xTickCount += xTicksToJump; + 8006190: 4b04 ldr r3, [pc, #16] ; (80061a4 ) + 8006192: 681a ldr r2, [r3, #0] + 8006194: 687b ldr r3, [r7, #4] + 8006196: 18d2 adds r2, r2, r3 + 8006198: 4b02 ldr r3, [pc, #8] ; (80061a4 ) + 800619a: 601a str r2, [r3, #0] + traceINCREASE_TICK_COUNT( xTicksToJump ); + } + 800619c: 46c0 nop ; (mov r8, r8) + 800619e: 46bd mov sp, r7 + 80061a0: b002 add sp, #8 + 80061a2: bd80 pop {r7, pc} + 80061a4: 20000bc4 .word 0x20000bc4 + 80061a8: 20000be0 .word 0x20000be0 + +080061ac : + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + 80061ac: b580 push {r7, lr} + 80061ae: b086 sub sp, #24 + 80061b0: af00 add r7, sp, #0 +TCB_t * pxTCB; +TickType_t xItemValue; +BaseType_t xSwitchRequired = pdFALSE; + 80061b2: 2300 movs r3, #0 + 80061b4: 617b str r3, [r7, #20] + + /* Called by the portable layer each time a tick interrupt occurs. + Increments the tick then checks to see if the new tick value will cause any + tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 80061b6: 4b4a ldr r3, [pc, #296] ; (80062e0 ) + 80061b8: 681b ldr r3, [r3, #0] + 80061ba: 2b00 cmp r3, #0 + 80061bc: d000 beq.n 80061c0 + 80061be: e07e b.n 80062be + { + /* Minor optimisation. The tick count cannot change in this + block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + 80061c0: 4b48 ldr r3, [pc, #288] ; (80062e4 ) + 80061c2: 681b ldr r3, [r3, #0] + 80061c4: 3301 adds r3, #1 + 80061c6: 613b str r3, [r7, #16] + + /* Increment the RTOS tick, switching the delayed and overflowed + delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + 80061c8: 4b46 ldr r3, [pc, #280] ; (80062e4 ) + 80061ca: 693a ldr r2, [r7, #16] + 80061cc: 601a str r2, [r3, #0] + + if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + 80061ce: 693b ldr r3, [r7, #16] + 80061d0: 2b00 cmp r3, #0 + 80061d2: d117 bne.n 8006204 + { + taskSWITCH_DELAYED_LISTS(); + 80061d4: 4b44 ldr r3, [pc, #272] ; (80062e8 ) + 80061d6: 681b ldr r3, [r3, #0] + 80061d8: 681b ldr r3, [r3, #0] + 80061da: 2b00 cmp r3, #0 + 80061dc: d001 beq.n 80061e2 + 80061de: b672 cpsid i + 80061e0: e7fe b.n 80061e0 + 80061e2: 4b41 ldr r3, [pc, #260] ; (80062e8 ) + 80061e4: 681b ldr r3, [r3, #0] + 80061e6: 60fb str r3, [r7, #12] + 80061e8: 4b40 ldr r3, [pc, #256] ; (80062ec ) + 80061ea: 681a ldr r2, [r3, #0] + 80061ec: 4b3e ldr r3, [pc, #248] ; (80062e8 ) + 80061ee: 601a str r2, [r3, #0] + 80061f0: 4b3e ldr r3, [pc, #248] ; (80062ec ) + 80061f2: 68fa ldr r2, [r7, #12] + 80061f4: 601a str r2, [r3, #0] + 80061f6: 4b3e ldr r3, [pc, #248] ; (80062f0 ) + 80061f8: 681b ldr r3, [r3, #0] + 80061fa: 1c5a adds r2, r3, #1 + 80061fc: 4b3c ldr r3, [pc, #240] ; (80062f0 ) + 80061fe: 601a str r2, [r3, #0] + 8006200: f000 faf4 bl 80067ec + + /* See if this tick has made a timeout expire. Tasks are stored in + the queue in the order of their wake time - meaning once one task + has been found whose block time has not expired there is no need to + look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + 8006204: 4b3b ldr r3, [pc, #236] ; (80062f4 ) + 8006206: 681b ldr r3, [r3, #0] + 8006208: 693a ldr r2, [r7, #16] + 800620a: 429a cmp r2, r3 + 800620c: d349 bcc.n 80062a2 + { + for( ;; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800620e: 4b36 ldr r3, [pc, #216] ; (80062e8 ) + 8006210: 681b ldr r3, [r3, #0] + 8006212: 681b ldr r3, [r3, #0] + 8006214: 2b00 cmp r3, #0 + 8006216: d104 bne.n 8006222 + /* The delayed list is empty. Set xNextTaskUnblockTime + to the maximum possible value so it is extremely + unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass + next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8006218: 4b36 ldr r3, [pc, #216] ; (80062f4 ) + 800621a: 2201 movs r2, #1 + 800621c: 4252 negs r2, r2 + 800621e: 601a str r2, [r3, #0] + break; + 8006220: e03f b.n 80062a2 + { + /* The delayed list is not empty, get the value of the + item at the head of the delayed list. This is the time + at which the task at the head of the delayed list must + be removed from the Blocked state. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8006222: 4b31 ldr r3, [pc, #196] ; (80062e8 ) + 8006224: 681b ldr r3, [r3, #0] + 8006226: 68db ldr r3, [r3, #12] + 8006228: 68db ldr r3, [r3, #12] + 800622a: 60bb str r3, [r7, #8] + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + 800622c: 68bb ldr r3, [r7, #8] + 800622e: 685b ldr r3, [r3, #4] + 8006230: 607b str r3, [r7, #4] + + if( xConstTickCount < xItemValue ) + 8006232: 693a ldr r2, [r7, #16] + 8006234: 687b ldr r3, [r7, #4] + 8006236: 429a cmp r2, r3 + 8006238: d203 bcs.n 8006242 + /* It is not time to unblock this item yet, but the + item value is the time at which the task at the head + of the blocked list must be removed from the Blocked + state - so record the item value in + xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + 800623a: 4b2e ldr r3, [pc, #184] ; (80062f4 ) + 800623c: 687a ldr r2, [r7, #4] + 800623e: 601a str r2, [r3, #0] + break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ + 8006240: e02f b.n 80062a2 + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8006242: 68bb ldr r3, [r7, #8] + 8006244: 3304 adds r3, #4 + 8006246: 0018 movs r0, r3 + 8006248: f7fe ffb9 bl 80051be + + /* Is the task waiting on an event also? If so remove + it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + 800624c: 68bb ldr r3, [r7, #8] + 800624e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006250: 2b00 cmp r3, #0 + 8006252: d004 beq.n 800625e + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 8006254: 68bb ldr r3, [r7, #8] + 8006256: 3318 adds r3, #24 + 8006258: 0018 movs r0, r3 + 800625a: f7fe ffb0 bl 80051be + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + list. */ + prvAddTaskToReadyList( pxTCB ); + 800625e: 68bb ldr r3, [r7, #8] + 8006260: 6ada ldr r2, [r3, #44] ; 0x2c + 8006262: 4b25 ldr r3, [pc, #148] ; (80062f8 ) + 8006264: 681b ldr r3, [r3, #0] + 8006266: 429a cmp r2, r3 + 8006268: d903 bls.n 8006272 + 800626a: 68bb ldr r3, [r7, #8] + 800626c: 6ada ldr r2, [r3, #44] ; 0x2c + 800626e: 4b22 ldr r3, [pc, #136] ; (80062f8 ) + 8006270: 601a str r2, [r3, #0] + 8006272: 68bb ldr r3, [r7, #8] + 8006274: 6ada ldr r2, [r3, #44] ; 0x2c + 8006276: 0013 movs r3, r2 + 8006278: 009b lsls r3, r3, #2 + 800627a: 189b adds r3, r3, r2 + 800627c: 009b lsls r3, r3, #2 + 800627e: 4a1f ldr r2, [pc, #124] ; (80062fc ) + 8006280: 189a adds r2, r3, r2 + 8006282: 68bb ldr r3, [r7, #8] + 8006284: 3304 adds r3, #4 + 8006286: 0019 movs r1, r3 + 8006288: 0010 movs r0, r2 + 800628a: f7fe ff40 bl 800510e + { + /* Preemption is on, but a context switch should + only be performed if the unblocked task has a + priority that is equal to or higher than the + currently executing task. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 800628e: 68bb ldr r3, [r7, #8] + 8006290: 6ada ldr r2, [r3, #44] ; 0x2c + 8006292: 4b1b ldr r3, [pc, #108] ; (8006300 ) + 8006294: 681b ldr r3, [r3, #0] + 8006296: 6adb ldr r3, [r3, #44] ; 0x2c + 8006298: 429a cmp r2, r3 + 800629a: d3b8 bcc.n 800620e + { + xSwitchRequired = pdTRUE; + 800629c: 2301 movs r3, #1 + 800629e: 617b str r3, [r7, #20] + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 80062a0: e7b5 b.n 800620e + /* Tasks of equal priority to the currently running task will share + processing time (time slice) if preemption is on, and the application + writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + 80062a2: 4b17 ldr r3, [pc, #92] ; (8006300 ) + 80062a4: 681b ldr r3, [r3, #0] + 80062a6: 6ada ldr r2, [r3, #44] ; 0x2c + 80062a8: 4914 ldr r1, [pc, #80] ; (80062fc ) + 80062aa: 0013 movs r3, r2 + 80062ac: 009b lsls r3, r3, #2 + 80062ae: 189b adds r3, r3, r2 + 80062b0: 009b lsls r3, r3, #2 + 80062b2: 585b ldr r3, [r3, r1] + 80062b4: 2b01 cmp r3, #1 + 80062b6: d907 bls.n 80062c8 + { + xSwitchRequired = pdTRUE; + 80062b8: 2301 movs r3, #1 + 80062ba: 617b str r3, [r7, #20] + 80062bc: e004 b.n 80062c8 + } + #endif /* configUSE_TICK_HOOK */ + } + else + { + ++uxPendedTicks; + 80062be: 4b11 ldr r3, [pc, #68] ; (8006304 ) + 80062c0: 681b ldr r3, [r3, #0] + 80062c2: 1c5a adds r2, r3, #1 + 80062c4: 4b0f ldr r3, [pc, #60] ; (8006304 ) + 80062c6: 601a str r2, [r3, #0] + #endif + } + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + 80062c8: 4b0f ldr r3, [pc, #60] ; (8006308 ) + 80062ca: 681b ldr r3, [r3, #0] + 80062cc: 2b00 cmp r3, #0 + 80062ce: d001 beq.n 80062d4 + { + xSwitchRequired = pdTRUE; + 80062d0: 2301 movs r3, #1 + 80062d2: 617b str r3, [r7, #20] + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + + return xSwitchRequired; + 80062d4: 697b ldr r3, [r7, #20] +} + 80062d6: 0018 movs r0, r3 + 80062d8: 46bd mov sp, r7 + 80062da: b006 add sp, #24 + 80062dc: bd80 pop {r7, pc} + 80062de: 46c0 nop ; (mov r8, r8) + 80062e0: 20000be8 .word 0x20000be8 + 80062e4: 20000bc4 .word 0x20000bc4 + 80062e8: 20000b78 .word 0x20000b78 + 80062ec: 20000b7c .word 0x20000b7c + 80062f0: 20000bd8 .word 0x20000bd8 + 80062f4: 20000be0 .word 0x20000be0 + 80062f8: 20000bc8 .word 0x20000bc8 + 80062fc: 200006f0 .word 0x200006f0 + 8006300: 200006ec .word 0x200006ec + 8006304: 20000bd0 .word 0x20000bd0 + 8006308: 20000bd4 .word 0x20000bd4 + +0800630c : + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + 800630c: b580 push {r7, lr} + 800630e: b082 sub sp, #8 + 8006310: af00 add r7, sp, #0 + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + 8006312: 4b22 ldr r3, [pc, #136] ; (800639c ) + 8006314: 681b ldr r3, [r3, #0] + 8006316: 2b00 cmp r3, #0 + 8006318: d003 beq.n 8006322 + { + /* The scheduler is currently suspended - do not allow a context + switch. */ + xYieldPending = pdTRUE; + 800631a: 4b21 ldr r3, [pc, #132] ; (80063a0 ) + 800631c: 2201 movs r2, #1 + 800631e: 601a str r2, [r3, #0] + structure specific to this task. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + } +} + 8006320: e037 b.n 8006392 + xYieldPending = pdFALSE; + 8006322: 4b1f ldr r3, [pc, #124] ; (80063a0 ) + 8006324: 2200 movs r2, #0 + 8006326: 601a str r2, [r3, #0] + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8006328: 4b1e ldr r3, [pc, #120] ; (80063a4 ) + 800632a: 681b ldr r3, [r3, #0] + 800632c: 607b str r3, [r7, #4] + 800632e: e007 b.n 8006340 + 8006330: 687b ldr r3, [r7, #4] + 8006332: 2b00 cmp r3, #0 + 8006334: d101 bne.n 800633a + 8006336: b672 cpsid i + 8006338: e7fe b.n 8006338 + 800633a: 687b ldr r3, [r7, #4] + 800633c: 3b01 subs r3, #1 + 800633e: 607b str r3, [r7, #4] + 8006340: 4919 ldr r1, [pc, #100] ; (80063a8 ) + 8006342: 687a ldr r2, [r7, #4] + 8006344: 0013 movs r3, r2 + 8006346: 009b lsls r3, r3, #2 + 8006348: 189b adds r3, r3, r2 + 800634a: 009b lsls r3, r3, #2 + 800634c: 585b ldr r3, [r3, r1] + 800634e: 2b00 cmp r3, #0 + 8006350: d0ee beq.n 8006330 + 8006352: 687a ldr r2, [r7, #4] + 8006354: 0013 movs r3, r2 + 8006356: 009b lsls r3, r3, #2 + 8006358: 189b adds r3, r3, r2 + 800635a: 009b lsls r3, r3, #2 + 800635c: 4a12 ldr r2, [pc, #72] ; (80063a8 ) + 800635e: 189b adds r3, r3, r2 + 8006360: 603b str r3, [r7, #0] + 8006362: 683b ldr r3, [r7, #0] + 8006364: 685b ldr r3, [r3, #4] + 8006366: 685a ldr r2, [r3, #4] + 8006368: 683b ldr r3, [r7, #0] + 800636a: 605a str r2, [r3, #4] + 800636c: 683b ldr r3, [r7, #0] + 800636e: 685a ldr r2, [r3, #4] + 8006370: 683b ldr r3, [r7, #0] + 8006372: 3308 adds r3, #8 + 8006374: 429a cmp r2, r3 + 8006376: d104 bne.n 8006382 + 8006378: 683b ldr r3, [r7, #0] + 800637a: 685b ldr r3, [r3, #4] + 800637c: 685a ldr r2, [r3, #4] + 800637e: 683b ldr r3, [r7, #0] + 8006380: 605a str r2, [r3, #4] + 8006382: 683b ldr r3, [r7, #0] + 8006384: 685b ldr r3, [r3, #4] + 8006386: 68da ldr r2, [r3, #12] + 8006388: 4b08 ldr r3, [pc, #32] ; (80063ac ) + 800638a: 601a str r2, [r3, #0] + 800638c: 4b05 ldr r3, [pc, #20] ; (80063a4 ) + 800638e: 687a ldr r2, [r7, #4] + 8006390: 601a str r2, [r3, #0] +} + 8006392: 46c0 nop ; (mov r8, r8) + 8006394: 46bd mov sp, r7 + 8006396: b002 add sp, #8 + 8006398: bd80 pop {r7, pc} + 800639a: 46c0 nop ; (mov r8, r8) + 800639c: 20000be8 .word 0x20000be8 + 80063a0: 20000bd4 .word 0x20000bd4 + 80063a4: 20000bc8 .word 0x20000bc8 + 80063a8: 200006f0 .word 0x200006f0 + 80063ac: 200006ec .word 0x200006ec + +080063b0 : +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) +{ + 80063b0: b580 push {r7, lr} + 80063b2: b082 sub sp, #8 + 80063b4: af00 add r7, sp, #0 + 80063b6: 6078 str r0, [r7, #4] + 80063b8: 6039 str r1, [r7, #0] + configASSERT( pxEventList ); + 80063ba: 687b ldr r3, [r7, #4] + 80063bc: 2b00 cmp r3, #0 + 80063be: d101 bne.n 80063c4 + 80063c0: b672 cpsid i + 80063c2: e7fe b.n 80063c2 + + /* Place the event list item of the TCB in the appropriate event list. + This is placed in the list in priority order so the highest priority task + is the first to be woken by the event. The queue that contains the event + list is locked, preventing simultaneous access from interrupts. */ + vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + 80063c4: 4b08 ldr r3, [pc, #32] ; (80063e8 ) + 80063c6: 681b ldr r3, [r3, #0] + 80063c8: 3318 adds r3, #24 + 80063ca: 001a movs r2, r3 + 80063cc: 687b ldr r3, [r7, #4] + 80063ce: 0011 movs r1, r2 + 80063d0: 0018 movs r0, r3 + 80063d2: f7fe febe bl 8005152 + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + 80063d6: 683b ldr r3, [r7, #0] + 80063d8: 2101 movs r1, #1 + 80063da: 0018 movs r0, r3 + 80063dc: f000 fa9c bl 8006918 +} + 80063e0: 46c0 nop ; (mov r8, r8) + 80063e2: 46bd mov sp, r7 + 80063e4: b002 add sp, #8 + 80063e6: bd80 pop {r7, pc} + 80063e8: 200006ec .word 0x200006ec + +080063ec : +/*-----------------------------------------------------------*/ + +#if( configUSE_TIMERS == 1 ) + + void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) + { + 80063ec: b580 push {r7, lr} + 80063ee: b084 sub sp, #16 + 80063f0: af00 add r7, sp, #0 + 80063f2: 60f8 str r0, [r7, #12] + 80063f4: 60b9 str r1, [r7, #8] + 80063f6: 607a str r2, [r7, #4] + configASSERT( pxEventList ); + 80063f8: 68fb ldr r3, [r7, #12] + 80063fa: 2b00 cmp r3, #0 + 80063fc: d101 bne.n 8006402 + 80063fe: b672 cpsid i + 8006400: e7fe b.n 8006400 + + /* Place the event list item of the TCB in the appropriate event list. + In this case it is assume that this is the only task that is going to + be waiting on this event list, so the faster vListInsertEnd() function + can be used in place of vListInsert. */ + vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + 8006402: 4b0c ldr r3, [pc, #48] ; (8006434 ) + 8006404: 681b ldr r3, [r3, #0] + 8006406: 3318 adds r3, #24 + 8006408: 001a movs r2, r3 + 800640a: 68fb ldr r3, [r7, #12] + 800640c: 0011 movs r1, r2 + 800640e: 0018 movs r0, r3 + 8006410: f7fe fe7d bl 800510e + + /* If the task should block indefinitely then set the block time to a + value that will be recognised as an indefinite delay inside the + prvAddCurrentTaskToDelayedList() function. */ + if( xWaitIndefinitely != pdFALSE ) + 8006414: 687b ldr r3, [r7, #4] + 8006416: 2b00 cmp r3, #0 + 8006418: d002 beq.n 8006420 + { + xTicksToWait = portMAX_DELAY; + 800641a: 2301 movs r3, #1 + 800641c: 425b negs r3, r3 + 800641e: 60bb str r3, [r7, #8] + } + + traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); + prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); + 8006420: 687a ldr r2, [r7, #4] + 8006422: 68bb ldr r3, [r7, #8] + 8006424: 0011 movs r1, r2 + 8006426: 0018 movs r0, r3 + 8006428: f000 fa76 bl 8006918 + } + 800642c: 46c0 nop ; (mov r8, r8) + 800642e: 46bd mov sp, r7 + 8006430: b004 add sp, #16 + 8006432: bd80 pop {r7, pc} + 8006434: 200006ec .word 0x200006ec + +08006438 : + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) +{ + 8006438: b580 push {r7, lr} + 800643a: b084 sub sp, #16 + 800643c: af00 add r7, sp, #0 + 800643e: 6078 str r0, [r7, #4] + get called - the lock count on the queue will get modified instead. This + means exclusive access to the event list is guaranteed here. + + This function assumes that a check has already been made to ensure that + pxEventList is not empty. */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8006440: 687b ldr r3, [r7, #4] + 8006442: 68db ldr r3, [r3, #12] + 8006444: 68db ldr r3, [r3, #12] + 8006446: 60bb str r3, [r7, #8] + configASSERT( pxUnblockedTCB ); + 8006448: 68bb ldr r3, [r7, #8] + 800644a: 2b00 cmp r3, #0 + 800644c: d101 bne.n 8006452 + 800644e: b672 cpsid i + 8006450: e7fe b.n 8006450 + ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); + 8006452: 68bb ldr r3, [r7, #8] + 8006454: 3318 adds r3, #24 + 8006456: 0018 movs r0, r3 + 8006458: f7fe feb1 bl 80051be + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800645c: 4b1f ldr r3, [pc, #124] ; (80064dc ) + 800645e: 681b ldr r3, [r3, #0] + 8006460: 2b00 cmp r3, #0 + 8006462: d11f bne.n 80064a4 + { + ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); + 8006464: 68bb ldr r3, [r7, #8] + 8006466: 3304 adds r3, #4 + 8006468: 0018 movs r0, r3 + 800646a: f7fe fea8 bl 80051be + prvAddTaskToReadyList( pxUnblockedTCB ); + 800646e: 68bb ldr r3, [r7, #8] + 8006470: 6ada ldr r2, [r3, #44] ; 0x2c + 8006472: 4b1b ldr r3, [pc, #108] ; (80064e0 ) + 8006474: 681b ldr r3, [r3, #0] + 8006476: 429a cmp r2, r3 + 8006478: d903 bls.n 8006482 + 800647a: 68bb ldr r3, [r7, #8] + 800647c: 6ada ldr r2, [r3, #44] ; 0x2c + 800647e: 4b18 ldr r3, [pc, #96] ; (80064e0 ) + 8006480: 601a str r2, [r3, #0] + 8006482: 68bb ldr r3, [r7, #8] + 8006484: 6ada ldr r2, [r3, #44] ; 0x2c + 8006486: 0013 movs r3, r2 + 8006488: 009b lsls r3, r3, #2 + 800648a: 189b adds r3, r3, r2 + 800648c: 009b lsls r3, r3, #2 + 800648e: 4a15 ldr r2, [pc, #84] ; (80064e4 ) + 8006490: 189a adds r2, r3, r2 + 8006492: 68bb ldr r3, [r7, #8] + 8006494: 3304 adds r3, #4 + 8006496: 0019 movs r1, r3 + 8006498: 0010 movs r0, r2 + 800649a: f7fe fe38 bl 800510e + normally left unchanged, because it is automatically reset to a new + value when the tick count equals xNextTaskUnblockTime. However if + tickless idling is used it might be more important to enter sleep mode + at the earliest possible time - so reset xNextTaskUnblockTime here to + ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + 800649e: f000 f9a5 bl 80067ec + 80064a2: e007 b.n 80064b4 + } + else + { + /* The delayed and ready lists cannot be accessed, so hold this task + pending until the scheduler is resumed. */ + vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + 80064a4: 68bb ldr r3, [r7, #8] + 80064a6: 3318 adds r3, #24 + 80064a8: 001a movs r2, r3 + 80064aa: 4b0f ldr r3, [pc, #60] ; (80064e8 ) + 80064ac: 0011 movs r1, r2 + 80064ae: 0018 movs r0, r3 + 80064b0: f7fe fe2d bl 800510e + } + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + 80064b4: 68bb ldr r3, [r7, #8] + 80064b6: 6ada ldr r2, [r3, #44] ; 0x2c + 80064b8: 4b0c ldr r3, [pc, #48] ; (80064ec ) + 80064ba: 681b ldr r3, [r3, #0] + 80064bc: 6adb ldr r3, [r3, #44] ; 0x2c + 80064be: 429a cmp r2, r3 + 80064c0: d905 bls.n 80064ce + { + /* Return true if the task removed from the event list has a higher + priority than the calling task. This allows the calling task to know if + it should force a context switch now. */ + xReturn = pdTRUE; + 80064c2: 2301 movs r3, #1 + 80064c4: 60fb str r3, [r7, #12] + + /* Mark that a yield is pending in case the user is not using the + "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPending = pdTRUE; + 80064c6: 4b0a ldr r3, [pc, #40] ; (80064f0 ) + 80064c8: 2201 movs r2, #1 + 80064ca: 601a str r2, [r3, #0] + 80064cc: e001 b.n 80064d2 + } + else + { + xReturn = pdFALSE; + 80064ce: 2300 movs r3, #0 + 80064d0: 60fb str r3, [r7, #12] + } + + return xReturn; + 80064d2: 68fb ldr r3, [r7, #12] +} + 80064d4: 0018 movs r0, r3 + 80064d6: 46bd mov sp, r7 + 80064d8: b004 add sp, #16 + 80064da: bd80 pop {r7, pc} + 80064dc: 20000be8 .word 0x20000be8 + 80064e0: 20000bc8 .word 0x20000bc8 + 80064e4: 200006f0 .word 0x200006f0 + 80064e8: 20000b80 .word 0x20000b80 + 80064ec: 200006ec .word 0x200006ec + 80064f0: 20000bd4 .word 0x20000bd4 + +080064f4 : + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + 80064f4: b580 push {r7, lr} + 80064f6: b082 sub sp, #8 + 80064f8: af00 add r7, sp, #0 + 80064fa: 6078 str r0, [r7, #4] + /* For internal use only as it does not use a critical section. */ + pxTimeOut->xOverflowCount = xNumOfOverflows; + 80064fc: 4b05 ldr r3, [pc, #20] ; (8006514 ) + 80064fe: 681a ldr r2, [r3, #0] + 8006500: 687b ldr r3, [r7, #4] + 8006502: 601a str r2, [r3, #0] + pxTimeOut->xTimeOnEntering = xTickCount; + 8006504: 4b04 ldr r3, [pc, #16] ; (8006518 ) + 8006506: 681a ldr r2, [r3, #0] + 8006508: 687b ldr r3, [r7, #4] + 800650a: 605a str r2, [r3, #4] +} + 800650c: 46c0 nop ; (mov r8, r8) + 800650e: 46bd mov sp, r7 + 8006510: b002 add sp, #8 + 8006512: bd80 pop {r7, pc} + 8006514: 20000bd8 .word 0x20000bd8 + 8006518: 20000bc4 .word 0x20000bc4 + +0800651c : +/*-----------------------------------------------------------*/ + +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) +{ + 800651c: b580 push {r7, lr} + 800651e: b086 sub sp, #24 + 8006520: af00 add r7, sp, #0 + 8006522: 6078 str r0, [r7, #4] + 8006524: 6039 str r1, [r7, #0] +BaseType_t xReturn; + + configASSERT( pxTimeOut ); + 8006526: 687b ldr r3, [r7, #4] + 8006528: 2b00 cmp r3, #0 + 800652a: d101 bne.n 8006530 + 800652c: b672 cpsid i + 800652e: e7fe b.n 800652e + configASSERT( pxTicksToWait ); + 8006530: 683b ldr r3, [r7, #0] + 8006532: 2b00 cmp r3, #0 + 8006534: d101 bne.n 800653a + 8006536: b672 cpsid i + 8006538: e7fe b.n 8006538 + + taskENTER_CRITICAL(); + 800653a: f000 fdf1 bl 8007120 + { + /* Minor optimisation. The tick count cannot change in this block. */ + const TickType_t xConstTickCount = xTickCount; + 800653e: 4b24 ldr r3, [pc, #144] ; (80065d0 ) + 8006540: 681b ldr r3, [r3, #0] + 8006542: 613b str r3, [r7, #16] + const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; + 8006544: 687b ldr r3, [r7, #4] + 8006546: 685b ldr r3, [r3, #4] + 8006548: 693a ldr r2, [r7, #16] + 800654a: 1ad3 subs r3, r2, r3 + 800654c: 60fb str r3, [r7, #12] + + #if( INCLUDE_xTaskAbortDelay == 1 ) + if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE ) + 800654e: 4b21 ldr r3, [pc, #132] ; (80065d4 ) + 8006550: 681b ldr r3, [r3, #0] + 8006552: 225a movs r2, #90 ; 0x5a + 8006554: 5c9b ldrb r3, [r3, r2] + 8006556: 2b00 cmp r3, #0 + 8006558: d007 beq.n 800656a + { + /* The delay was aborted, which is not the same as a time out, + but has the same result. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + 800655a: 4b1e ldr r3, [pc, #120] ; (80065d4 ) + 800655c: 681b ldr r3, [r3, #0] + 800655e: 225a movs r2, #90 ; 0x5a + 8006560: 2100 movs r1, #0 + 8006562: 5499 strb r1, [r3, r2] + xReturn = pdTRUE; + 8006564: 2301 movs r3, #1 + 8006566: 617b str r3, [r7, #20] + 8006568: e02b b.n 80065c2 + } + else + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + if( *pxTicksToWait == portMAX_DELAY ) + 800656a: 683b ldr r3, [r7, #0] + 800656c: 681b ldr r3, [r3, #0] + 800656e: 3301 adds r3, #1 + 8006570: d102 bne.n 8006578 + { + /* If INCLUDE_vTaskSuspend is set to 1 and the block time + specified is the maximum block time then the task should block + indefinitely, and therefore never time out. */ + xReturn = pdFALSE; + 8006572: 2300 movs r3, #0 + 8006574: 617b str r3, [r7, #20] + 8006576: e024 b.n 80065c2 + } + else + #endif + + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + 8006578: 687b ldr r3, [r7, #4] + 800657a: 681a ldr r2, [r3, #0] + 800657c: 4b16 ldr r3, [pc, #88] ; (80065d8 ) + 800657e: 681b ldr r3, [r3, #0] + 8006580: 429a cmp r2, r3 + 8006582: d007 beq.n 8006594 + 8006584: 687b ldr r3, [r7, #4] + 8006586: 685b ldr r3, [r3, #4] + 8006588: 693a ldr r2, [r7, #16] + 800658a: 429a cmp r2, r3 + 800658c: d302 bcc.n 8006594 + /* The tick count is greater than the time at which + vTaskSetTimeout() was called, but has also overflowed since + vTaskSetTimeOut() was called. It must have wrapped all the way + around and gone past again. This passed since vTaskSetTimeout() + was called. */ + xReturn = pdTRUE; + 800658e: 2301 movs r3, #1 + 8006590: 617b str r3, [r7, #20] + 8006592: e016 b.n 80065c2 + } + else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + 8006594: 683b ldr r3, [r7, #0] + 8006596: 681b ldr r3, [r3, #0] + 8006598: 68fa ldr r2, [r7, #12] + 800659a: 429a cmp r2, r3 + 800659c: d20c bcs.n 80065b8 + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= xElapsedTime; + 800659e: 683b ldr r3, [r7, #0] + 80065a0: 681a ldr r2, [r3, #0] + 80065a2: 68fb ldr r3, [r7, #12] + 80065a4: 1ad2 subs r2, r2, r3 + 80065a6: 683b ldr r3, [r7, #0] + 80065a8: 601a str r2, [r3, #0] + vTaskInternalSetTimeOutState( pxTimeOut ); + 80065aa: 687b ldr r3, [r7, #4] + 80065ac: 0018 movs r0, r3 + 80065ae: f7ff ffa1 bl 80064f4 + xReturn = pdFALSE; + 80065b2: 2300 movs r3, #0 + 80065b4: 617b str r3, [r7, #20] + 80065b6: e004 b.n 80065c2 + } + else + { + *pxTicksToWait = 0; + 80065b8: 683b ldr r3, [r7, #0] + 80065ba: 2200 movs r2, #0 + 80065bc: 601a str r2, [r3, #0] + xReturn = pdTRUE; + 80065be: 2301 movs r3, #1 + 80065c0: 617b str r3, [r7, #20] + } + } + taskEXIT_CRITICAL(); + 80065c2: f000 fdbf bl 8007144 + + return xReturn; + 80065c6: 697b ldr r3, [r7, #20] +} + 80065c8: 0018 movs r0, r3 + 80065ca: 46bd mov sp, r7 + 80065cc: b006 add sp, #24 + 80065ce: bd80 pop {r7, pc} + 80065d0: 20000bc4 .word 0x20000bc4 + 80065d4: 200006ec .word 0x200006ec + 80065d8: 20000bd8 .word 0x20000bd8 + +080065dc : +/*-----------------------------------------------------------*/ + +void vTaskMissedYield( void ) +{ + 80065dc: b580 push {r7, lr} + 80065de: af00 add r7, sp, #0 + xYieldPending = pdTRUE; + 80065e0: 4b02 ldr r3, [pc, #8] ; (80065ec ) + 80065e2: 2201 movs r2, #1 + 80065e4: 601a str r2, [r3, #0] +} + 80065e6: 46c0 nop ; (mov r8, r8) + 80065e8: 46bd mov sp, r7 + 80065ea: bd80 pop {r7, pc} + 80065ec: 20000bd4 .word 0x20000bd4 + +080065f0 : + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + 80065f0: b580 push {r7, lr} + 80065f2: b084 sub sp, #16 + 80065f4: af00 add r7, sp, #0 + 80065f6: 6078 str r0, [r7, #4] + + for( ;; ) + { + /* See if any tasks have deleted themselves - if so then the idle task + is responsible for freeing the deleted task's TCB and stack. */ + prvCheckTasksWaitingTermination(); + 80065f8: f000 f8a2 bl 8006740 + + A critical region is not required here as we are just reading from + the list, and an occasional incorrect value will not matter. If + the ready list at the idle priority contains more than one task + then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + 80065fc: 4b12 ldr r3, [pc, #72] ; (8006648 ) + 80065fe: 681b ldr r3, [r3, #0] + 8006600: 2b01 cmp r3, #1 + 8006602: d901 bls.n 8006608 + { + taskYIELD(); + 8006604: f000 fd7c bl 8007100 + /* It is not desirable to suspend then resume the scheduler on + each iteration of the idle task. Therefore, a preliminary + test of the expected idle time is performed without the + scheduler suspended. The result here is not necessarily + valid. */ + xExpectedIdleTime = prvGetExpectedIdleTime(); + 8006608: f7ff fce4 bl 8005fd4 + 800660c: 0003 movs r3, r0 + 800660e: 60fb str r3, [r7, #12] + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + 8006610: 68fb ldr r3, [r7, #12] + 8006612: 2b01 cmp r3, #1 + 8006614: d9f0 bls.n 80065f8 + { + vTaskSuspendAll(); + 8006616: f7ff fcd1 bl 8005fbc + { + /* Now the scheduler is suspended, the expected idle + time can be sampled again, and this time its value can + be used. */ + configASSERT( xNextTaskUnblockTime >= xTickCount ); + 800661a: 4b0c ldr r3, [pc, #48] ; (800664c ) + 800661c: 681a ldr r2, [r3, #0] + 800661e: 4b0c ldr r3, [pc, #48] ; (8006650 ) + 8006620: 681b ldr r3, [r3, #0] + 8006622: 429a cmp r2, r3 + 8006624: d201 bcs.n 800662a + 8006626: b672 cpsid i + 8006628: e7fe b.n 8006628 + xExpectedIdleTime = prvGetExpectedIdleTime(); + 800662a: f7ff fcd3 bl 8005fd4 + 800662e: 0003 movs r3, r0 + 8006630: 60fb str r3, [r7, #12] + /* Define the following macro to set xExpectedIdleTime to 0 + if the application does not want + portSUPPRESS_TICKS_AND_SLEEP() to be called. */ + configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime ); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + 8006632: 68fb ldr r3, [r7, #12] + 8006634: 2b01 cmp r3, #1 + 8006636: d903 bls.n 8006640 + { + traceLOW_POWER_IDLE_BEGIN(); + portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ); + 8006638: 68fb ldr r3, [r7, #12] + 800663a: 0018 movs r0, r3 + 800663c: f000 fde6 bl 800720c + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + 8006640: f7ff fcfe bl 8006040 + prvCheckTasksWaitingTermination(); + 8006644: e7d8 b.n 80065f8 + 8006646: 46c0 nop ; (mov r8, r8) + 8006648: 200006f0 .word 0x200006f0 + 800664c: 20000be0 .word 0x20000be0 + 8006650: 20000bc4 .word 0x20000bc4 + +08006654 : +/*-----------------------------------------------------------*/ + +#if( configUSE_TICKLESS_IDLE != 0 ) + + eSleepModeStatus eTaskConfirmSleepModeStatus( void ) + { + 8006654: b580 push {r7, lr} + 8006656: b082 sub sp, #8 + 8006658: af00 add r7, sp, #0 + /* The idle task exists in addition to the application tasks. */ + const UBaseType_t uxNonApplicationTasks = 1; + 800665a: 2301 movs r3, #1 + 800665c: 603b str r3, [r7, #0] + eSleepModeStatus eReturn = eStandardSleep; + 800665e: 1dfb adds r3, r7, #7 + 8006660: 2201 movs r2, #1 + 8006662: 701a strb r2, [r3, #0] + + if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 ) + 8006664: 4b10 ldr r3, [pc, #64] ; (80066a8 ) + 8006666: 681b ldr r3, [r3, #0] + 8006668: 2b00 cmp r3, #0 + 800666a: d003 beq.n 8006674 + { + /* A task was made ready while the scheduler was suspended. */ + eReturn = eAbortSleep; + 800666c: 1dfb adds r3, r7, #7 + 800666e: 2200 movs r2, #0 + 8006670: 701a strb r2, [r3, #0] + 8006672: e012 b.n 800669a + } + else if( xYieldPending != pdFALSE ) + 8006674: 4b0d ldr r3, [pc, #52] ; (80066ac ) + 8006676: 681b ldr r3, [r3, #0] + 8006678: 2b00 cmp r3, #0 + 800667a: d003 beq.n 8006684 + { + /* A yield was pended while the scheduler was suspended. */ + eReturn = eAbortSleep; + 800667c: 1dfb adds r3, r7, #7 + 800667e: 2200 movs r2, #0 + 8006680: 701a strb r2, [r3, #0] + 8006682: e00a b.n 800669a + { + /* If all the tasks are in the suspended list (which might mean they + have an infinite block time rather than actually being suspended) + then it is safe to turn all clocks off and just wait for external + interrupts. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) ) + 8006684: 4b0a ldr r3, [pc, #40] ; (80066b0 ) + 8006686: 681a ldr r2, [r3, #0] + 8006688: 4b0a ldr r3, [pc, #40] ; (80066b4 ) + 800668a: 6819 ldr r1, [r3, #0] + 800668c: 683b ldr r3, [r7, #0] + 800668e: 1acb subs r3, r1, r3 + 8006690: 429a cmp r2, r3 + 8006692: d102 bne.n 800669a + { + eReturn = eNoTasksWaitingTimeout; + 8006694: 1dfb adds r3, r7, #7 + 8006696: 2202 movs r2, #2 + 8006698: 701a strb r2, [r3, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return eReturn; + 800669a: 1dfb adds r3, r7, #7 + 800669c: 781b ldrb r3, [r3, #0] + } + 800669e: 0018 movs r0, r3 + 80066a0: 46bd mov sp, r7 + 80066a2: b002 add sp, #8 + 80066a4: bd80 pop {r7, pc} + 80066a6: 46c0 nop ; (mov r8, r8) + 80066a8: 20000b80 .word 0x20000b80 + 80066ac: 20000bd4 .word 0x20000bd4 + 80066b0: 20000bac .word 0x20000bac + 80066b4: 20000bc0 .word 0x20000bc0 + +080066b8 : + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + 80066b8: b580 push {r7, lr} + 80066ba: b082 sub sp, #8 + 80066bc: af00 add r7, sp, #0 +UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 80066be: 2300 movs r3, #0 + 80066c0: 607b str r3, [r7, #4] + 80066c2: e00c b.n 80066de + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + 80066c4: 687a ldr r2, [r7, #4] + 80066c6: 0013 movs r3, r2 + 80066c8: 009b lsls r3, r3, #2 + 80066ca: 189b adds r3, r3, r2 + 80066cc: 009b lsls r3, r3, #2 + 80066ce: 4a14 ldr r2, [pc, #80] ; (8006720 ) + 80066d0: 189b adds r3, r3, r2 + 80066d2: 0018 movs r0, r3 + 80066d4: f7fe fcf2 bl 80050bc + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 80066d8: 687b ldr r3, [r7, #4] + 80066da: 3301 adds r3, #1 + 80066dc: 607b str r3, [r7, #4] + 80066de: 687b ldr r3, [r7, #4] + 80066e0: 2b37 cmp r3, #55 ; 0x37 + 80066e2: d9ef bls.n 80066c4 + } + + vListInitialise( &xDelayedTaskList1 ); + 80066e4: 4b0f ldr r3, [pc, #60] ; (8006724 ) + 80066e6: 0018 movs r0, r3 + 80066e8: f7fe fce8 bl 80050bc + vListInitialise( &xDelayedTaskList2 ); + 80066ec: 4b0e ldr r3, [pc, #56] ; (8006728 ) + 80066ee: 0018 movs r0, r3 + 80066f0: f7fe fce4 bl 80050bc + vListInitialise( &xPendingReadyList ); + 80066f4: 4b0d ldr r3, [pc, #52] ; (800672c ) + 80066f6: 0018 movs r0, r3 + 80066f8: f7fe fce0 bl 80050bc + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + 80066fc: 4b0c ldr r3, [pc, #48] ; (8006730 ) + 80066fe: 0018 movs r0, r3 + 8006700: f7fe fcdc bl 80050bc + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + 8006704: 4b0b ldr r3, [pc, #44] ; (8006734 ) + 8006706: 0018 movs r0, r3 + 8006708: f7fe fcd8 bl 80050bc + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + 800670c: 4b0a ldr r3, [pc, #40] ; (8006738 ) + 800670e: 4a05 ldr r2, [pc, #20] ; (8006724 ) + 8006710: 601a str r2, [r3, #0] + pxOverflowDelayedTaskList = &xDelayedTaskList2; + 8006712: 4b0a ldr r3, [pc, #40] ; (800673c ) + 8006714: 4a04 ldr r2, [pc, #16] ; (8006728 ) + 8006716: 601a str r2, [r3, #0] +} + 8006718: 46c0 nop ; (mov r8, r8) + 800671a: 46bd mov sp, r7 + 800671c: b002 add sp, #8 + 800671e: bd80 pop {r7, pc} + 8006720: 200006f0 .word 0x200006f0 + 8006724: 20000b50 .word 0x20000b50 + 8006728: 20000b64 .word 0x20000b64 + 800672c: 20000b80 .word 0x20000b80 + 8006730: 20000b94 .word 0x20000b94 + 8006734: 20000bac .word 0x20000bac + 8006738: 20000b78 .word 0x20000b78 + 800673c: 20000b7c .word 0x20000b7c + +08006740 : +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + 8006740: b580 push {r7, lr} + 8006742: b082 sub sp, #8 + 8006744: af00 add r7, sp, #0 + { + TCB_t *pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + being called too often in the idle task. */ + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 8006746: e01a b.n 800677e + { + taskENTER_CRITICAL(); + 8006748: f000 fcea bl 8007120 + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800674c: 4b10 ldr r3, [pc, #64] ; (8006790 ) + 800674e: 68db ldr r3, [r3, #12] + 8006750: 68db ldr r3, [r3, #12] + 8006752: 607b str r3, [r7, #4] + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8006754: 687b ldr r3, [r7, #4] + 8006756: 3304 adds r3, #4 + 8006758: 0018 movs r0, r3 + 800675a: f7fe fd30 bl 80051be + --uxCurrentNumberOfTasks; + 800675e: 4b0d ldr r3, [pc, #52] ; (8006794 ) + 8006760: 681b ldr r3, [r3, #0] + 8006762: 1e5a subs r2, r3, #1 + 8006764: 4b0b ldr r3, [pc, #44] ; (8006794 ) + 8006766: 601a str r2, [r3, #0] + --uxDeletedTasksWaitingCleanUp; + 8006768: 4b0b ldr r3, [pc, #44] ; (8006798 ) + 800676a: 681b ldr r3, [r3, #0] + 800676c: 1e5a subs r2, r3, #1 + 800676e: 4b0a ldr r3, [pc, #40] ; (8006798 ) + 8006770: 601a str r2, [r3, #0] + } + taskEXIT_CRITICAL(); + 8006772: f000 fce7 bl 8007144 + + prvDeleteTCB( pxTCB ); + 8006776: 687b ldr r3, [r7, #4] + 8006778: 0018 movs r0, r3 + 800677a: f000 f80f bl 800679c + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 800677e: 4b06 ldr r3, [pc, #24] ; (8006798 ) + 8006780: 681b ldr r3, [r3, #0] + 8006782: 2b00 cmp r3, #0 + 8006784: d1e0 bne.n 8006748 + } + } + #endif /* INCLUDE_vTaskDelete */ +} + 8006786: 46c0 nop ; (mov r8, r8) + 8006788: 46c0 nop ; (mov r8, r8) + 800678a: 46bd mov sp, r7 + 800678c: b002 add sp, #8 + 800678e: bd80 pop {r7, pc} + 8006790: 20000b94 .word 0x20000b94 + 8006794: 20000bc0 .word 0x20000bc0 + 8006798: 20000ba8 .word 0x20000ba8 + +0800679c : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t *pxTCB ) + { + 800679c: b580 push {r7, lr} + 800679e: b082 sub sp, #8 + 80067a0: af00 add r7, sp, #0 + 80067a2: 6078 str r0, [r7, #4] + #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* The task could have been allocated statically or dynamically, so + check what was statically allocated before trying to free the + memory. */ + if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) + 80067a4: 687b ldr r3, [r7, #4] + 80067a6: 2259 movs r2, #89 ; 0x59 + 80067a8: 5c9b ldrb r3, [r3, r2] + 80067aa: 2b00 cmp r3, #0 + 80067ac: d109 bne.n 80067c2 + { + /* Both the stack and TCB were allocated dynamically, so both + must be freed. */ + vPortFree( pxTCB->pxStack ); + 80067ae: 687b ldr r3, [r7, #4] + 80067b0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80067b2: 0018 movs r0, r3 + 80067b4: f000 fed6 bl 8007564 + vPortFree( pxTCB ); + 80067b8: 687b ldr r3, [r7, #4] + 80067ba: 0018 movs r0, r3 + 80067bc: f000 fed2 bl 8007564 + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + 80067c0: e010 b.n 80067e4 + else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) + 80067c2: 687b ldr r3, [r7, #4] + 80067c4: 2259 movs r2, #89 ; 0x59 + 80067c6: 5c9b ldrb r3, [r3, r2] + 80067c8: 2b01 cmp r3, #1 + 80067ca: d104 bne.n 80067d6 + vPortFree( pxTCB ); + 80067cc: 687b ldr r3, [r7, #4] + 80067ce: 0018 movs r0, r3 + 80067d0: f000 fec8 bl 8007564 + } + 80067d4: e006 b.n 80067e4 + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + 80067d6: 687b ldr r3, [r7, #4] + 80067d8: 2259 movs r2, #89 ; 0x59 + 80067da: 5c9b ldrb r3, [r3, r2] + 80067dc: 2b02 cmp r3, #2 + 80067de: d001 beq.n 80067e4 + 80067e0: b672 cpsid i + 80067e2: e7fe b.n 80067e2 + } + 80067e4: 46c0 nop ; (mov r8, r8) + 80067e6: 46bd mov sp, r7 + 80067e8: b002 add sp, #8 + 80067ea: bd80 pop {r7, pc} + +080067ec : + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + 80067ec: b580 push {r7, lr} + 80067ee: b082 sub sp, #8 + 80067f0: af00 add r7, sp, #0 +TCB_t *pxTCB; + + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 80067f2: 4b0b ldr r3, [pc, #44] ; (8006820 ) + 80067f4: 681b ldr r3, [r3, #0] + 80067f6: 681b ldr r3, [r3, #0] + 80067f8: 2b00 cmp r3, #0 + 80067fa: d104 bne.n 8006806 + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + the maximum possible value so it is extremely unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass until + there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + 80067fc: 4b09 ldr r3, [pc, #36] ; (8006824 ) + 80067fe: 2201 movs r2, #1 + 8006800: 4252 negs r2, r2 + 8006802: 601a str r2, [r3, #0] + which the task at the head of the delayed list should be removed + from the Blocked state. */ + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + } +} + 8006804: e008 b.n 8006818 + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8006806: 4b06 ldr r3, [pc, #24] ; (8006820 ) + 8006808: 681b ldr r3, [r3, #0] + 800680a: 68db ldr r3, [r3, #12] + 800680c: 68db ldr r3, [r3, #12] + 800680e: 607b str r3, [r7, #4] + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + 8006810: 687b ldr r3, [r7, #4] + 8006812: 685a ldr r2, [r3, #4] + 8006814: 4b03 ldr r3, [pc, #12] ; (8006824 ) + 8006816: 601a str r2, [r3, #0] +} + 8006818: 46c0 nop ; (mov r8, r8) + 800681a: 46bd mov sp, r7 + 800681c: b002 add sp, #8 + 800681e: bd80 pop {r7, pc} + 8006820: 20000b78 .word 0x20000b78 + 8006824: 20000be0 .word 0x20000be0 + +08006828 : +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + + BaseType_t xTaskGetSchedulerState( void ) + { + 8006828: b580 push {r7, lr} + 800682a: b082 sub sp, #8 + 800682c: af00 add r7, sp, #0 + BaseType_t xReturn; + + if( xSchedulerRunning == pdFALSE ) + 800682e: 4b0a ldr r3, [pc, #40] ; (8006858 ) + 8006830: 681b ldr r3, [r3, #0] + 8006832: 2b00 cmp r3, #0 + 8006834: d102 bne.n 800683c + { + xReturn = taskSCHEDULER_NOT_STARTED; + 8006836: 2301 movs r3, #1 + 8006838: 607b str r3, [r7, #4] + 800683a: e008 b.n 800684e + } + else + { + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800683c: 4b07 ldr r3, [pc, #28] ; (800685c ) + 800683e: 681b ldr r3, [r3, #0] + 8006840: 2b00 cmp r3, #0 + 8006842: d102 bne.n 800684a + { + xReturn = taskSCHEDULER_RUNNING; + 8006844: 2302 movs r3, #2 + 8006846: 607b str r3, [r7, #4] + 8006848: e001 b.n 800684e + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + 800684a: 2300 movs r3, #0 + 800684c: 607b str r3, [r7, #4] + } + } + + return xReturn; + 800684e: 687b ldr r3, [r7, #4] + } + 8006850: 0018 movs r0, r3 + 8006852: 46bd mov sp, r7 + 8006854: b002 add sp, #8 + 8006856: bd80 pop {r7, pc} + 8006858: 20000bcc .word 0x20000bcc + 800685c: 20000be8 .word 0x20000be8 + +08006860 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) + { + 8006860: b580 push {r7, lr} + 8006862: b084 sub sp, #16 + 8006864: af00 add r7, sp, #0 + 8006866: 6078 str r0, [r7, #4] + TCB_t * const pxTCB = pxMutexHolder; + 8006868: 687b ldr r3, [r7, #4] + 800686a: 60bb str r3, [r7, #8] + BaseType_t xReturn = pdFALSE; + 800686c: 2300 movs r3, #0 + 800686e: 60fb str r3, [r7, #12] + + if( pxMutexHolder != NULL ) + 8006870: 687b ldr r3, [r7, #4] + 8006872: 2b00 cmp r3, #0 + 8006874: d044 beq.n 8006900 + { + /* A task can only have an inherited priority if it holds the mutex. + If the mutex is held by a task then it cannot be given from an + interrupt, and if a mutex is given by the holding task then it must + be the running state task. */ + configASSERT( pxTCB == pxCurrentTCB ); + 8006876: 4b25 ldr r3, [pc, #148] ; (800690c ) + 8006878: 681b ldr r3, [r3, #0] + 800687a: 68ba ldr r2, [r7, #8] + 800687c: 429a cmp r2, r3 + 800687e: d001 beq.n 8006884 + 8006880: b672 cpsid i + 8006882: e7fe b.n 8006882 + configASSERT( pxTCB->uxMutexesHeld ); + 8006884: 68bb ldr r3, [r7, #8] + 8006886: 6d1b ldr r3, [r3, #80] ; 0x50 + 8006888: 2b00 cmp r3, #0 + 800688a: d101 bne.n 8006890 + 800688c: b672 cpsid i + 800688e: e7fe b.n 800688e + ( pxTCB->uxMutexesHeld )--; + 8006890: 68bb ldr r3, [r7, #8] + 8006892: 6d1b ldr r3, [r3, #80] ; 0x50 + 8006894: 1e5a subs r2, r3, #1 + 8006896: 68bb ldr r3, [r7, #8] + 8006898: 651a str r2, [r3, #80] ; 0x50 + + /* Has the holder of the mutex inherited the priority of another + task? */ + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + 800689a: 68bb ldr r3, [r7, #8] + 800689c: 6ada ldr r2, [r3, #44] ; 0x2c + 800689e: 68bb ldr r3, [r7, #8] + 80068a0: 6cdb ldr r3, [r3, #76] ; 0x4c + 80068a2: 429a cmp r2, r3 + 80068a4: d02c beq.n 8006900 + { + /* Only disinherit if no other mutexes are held. */ + if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) + 80068a6: 68bb ldr r3, [r7, #8] + 80068a8: 6d1b ldr r3, [r3, #80] ; 0x50 + 80068aa: 2b00 cmp r3, #0 + 80068ac: d128 bne.n 8006900 + /* A task can only have an inherited priority if it holds + the mutex. If the mutex is held by a task then it cannot be + given from an interrupt, and if a mutex is given by the + holding task then it must be the running state task. Remove + the holding task from the ready list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 80068ae: 68bb ldr r3, [r7, #8] + 80068b0: 3304 adds r3, #4 + 80068b2: 0018 movs r0, r3 + 80068b4: f7fe fc83 bl 80051be + } + + /* Disinherit the priority before adding the task into the + new ready list. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + pxTCB->uxPriority = pxTCB->uxBasePriority; + 80068b8: 68bb ldr r3, [r7, #8] + 80068ba: 6cda ldr r2, [r3, #76] ; 0x4c + 80068bc: 68bb ldr r3, [r7, #8] + 80068be: 62da str r2, [r3, #44] ; 0x2c + + /* Reset the event list item value. It cannot be in use for + any other purpose if this task is running, and it must be + running to give back the mutex. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 80068c0: 68bb ldr r3, [r7, #8] + 80068c2: 6adb ldr r3, [r3, #44] ; 0x2c + 80068c4: 2238 movs r2, #56 ; 0x38 + 80068c6: 1ad2 subs r2, r2, r3 + 80068c8: 68bb ldr r3, [r7, #8] + 80068ca: 619a str r2, [r3, #24] + prvAddTaskToReadyList( pxTCB ); + 80068cc: 68bb ldr r3, [r7, #8] + 80068ce: 6ada ldr r2, [r3, #44] ; 0x2c + 80068d0: 4b0f ldr r3, [pc, #60] ; (8006910 ) + 80068d2: 681b ldr r3, [r3, #0] + 80068d4: 429a cmp r2, r3 + 80068d6: d903 bls.n 80068e0 + 80068d8: 68bb ldr r3, [r7, #8] + 80068da: 6ada ldr r2, [r3, #44] ; 0x2c + 80068dc: 4b0c ldr r3, [pc, #48] ; (8006910 ) + 80068de: 601a str r2, [r3, #0] + 80068e0: 68bb ldr r3, [r7, #8] + 80068e2: 6ada ldr r2, [r3, #44] ; 0x2c + 80068e4: 0013 movs r3, r2 + 80068e6: 009b lsls r3, r3, #2 + 80068e8: 189b adds r3, r3, r2 + 80068ea: 009b lsls r3, r3, #2 + 80068ec: 4a09 ldr r2, [pc, #36] ; (8006914 ) + 80068ee: 189a adds r2, r3, r2 + 80068f0: 68bb ldr r3, [r7, #8] + 80068f2: 3304 adds r3, #4 + 80068f4: 0019 movs r1, r3 + 80068f6: 0010 movs r0, r2 + 80068f8: f7fe fc09 bl 800510e + in an order different to that in which they were taken. + If a context switch did not occur when the first mutex was + returned, even if a task was waiting on it, then a context + switch should occur when the last mutex is returned whether + a task is waiting on it or not. */ + xReturn = pdTRUE; + 80068fc: 2301 movs r3, #1 + 80068fe: 60fb str r3, [r7, #12] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + 8006900: 68fb ldr r3, [r7, #12] + } + 8006902: 0018 movs r0, r3 + 8006904: 46bd mov sp, r7 + 8006906: b004 add sp, #16 + 8006908: bd80 pop {r7, pc} + 800690a: 46c0 nop ; (mov r8, r8) + 800690c: 200006ec .word 0x200006ec + 8006910: 20000bc8 .word 0x20000bc8 + 8006914: 200006f0 .word 0x200006f0 + +08006918 : + } +#endif +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) +{ + 8006918: b580 push {r7, lr} + 800691a: b084 sub sp, #16 + 800691c: af00 add r7, sp, #0 + 800691e: 6078 str r0, [r7, #4] + 8006920: 6039 str r1, [r7, #0] +TickType_t xTimeToWake; +const TickType_t xConstTickCount = xTickCount; + 8006922: 4b24 ldr r3, [pc, #144] ; (80069b4 ) + 8006924: 681b ldr r3, [r3, #0] + 8006926: 60fb str r3, [r7, #12] + #if( INCLUDE_xTaskAbortDelay == 1 ) + { + /* About to enter a delayed list, so ensure the ucDelayAborted flag is + reset to pdFALSE so it can be detected as having been set to pdTRUE + when the task leaves the Blocked state. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + 8006928: 4b23 ldr r3, [pc, #140] ; (80069b8 ) + 800692a: 681b ldr r3, [r3, #0] + 800692c: 225a movs r2, #90 ; 0x5a + 800692e: 2100 movs r1, #0 + 8006930: 5499 strb r1, [r3, r2] + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 8006932: 4b21 ldr r3, [pc, #132] ; (80069b8 ) + 8006934: 681b ldr r3, [r3, #0] + 8006936: 3304 adds r3, #4 + 8006938: 0018 movs r0, r3 + 800693a: f7fe fc40 bl 80051be + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + 800693e: 687b ldr r3, [r7, #4] + 8006940: 3301 adds r3, #1 + 8006942: d10b bne.n 800695c + 8006944: 683b ldr r3, [r7, #0] + 8006946: 2b00 cmp r3, #0 + 8006948: d008 beq.n 800695c + { + /* Add the task to the suspended task list instead of a delayed task + list to ensure it is not woken by a timing event. It will block + indefinitely. */ + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 800694a: 4b1b ldr r3, [pc, #108] ; (80069b8 ) + 800694c: 681b ldr r3, [r3, #0] + 800694e: 1d1a adds r2, r3, #4 + 8006950: 4b1a ldr r3, [pc, #104] ; (80069bc ) + 8006952: 0011 movs r1, r2 + 8006954: 0018 movs r0, r3 + 8006956: f7fe fbda bl 800510e + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + 800695a: e026 b.n 80069aa + xTimeToWake = xConstTickCount + xTicksToWait; + 800695c: 68fa ldr r2, [r7, #12] + 800695e: 687b ldr r3, [r7, #4] + 8006960: 18d3 adds r3, r2, r3 + 8006962: 60bb str r3, [r7, #8] + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + 8006964: 4b14 ldr r3, [pc, #80] ; (80069b8 ) + 8006966: 681b ldr r3, [r3, #0] + 8006968: 68ba ldr r2, [r7, #8] + 800696a: 605a str r2, [r3, #4] + if( xTimeToWake < xConstTickCount ) + 800696c: 68ba ldr r2, [r7, #8] + 800696e: 68fb ldr r3, [r7, #12] + 8006970: 429a cmp r2, r3 + 8006972: d209 bcs.n 8006988 + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8006974: 4b12 ldr r3, [pc, #72] ; (80069c0 ) + 8006976: 681a ldr r2, [r3, #0] + 8006978: 4b0f ldr r3, [pc, #60] ; (80069b8 ) + 800697a: 681b ldr r3, [r3, #0] + 800697c: 3304 adds r3, #4 + 800697e: 0019 movs r1, r3 + 8006980: 0010 movs r0, r2 + 8006982: f7fe fbe6 bl 8005152 +} + 8006986: e010 b.n 80069aa + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8006988: 4b0e ldr r3, [pc, #56] ; (80069c4 ) + 800698a: 681a ldr r2, [r3, #0] + 800698c: 4b0a ldr r3, [pc, #40] ; (80069b8 ) + 800698e: 681b ldr r3, [r3, #0] + 8006990: 3304 adds r3, #4 + 8006992: 0019 movs r1, r3 + 8006994: 0010 movs r0, r2 + 8006996: f7fe fbdc bl 8005152 + if( xTimeToWake < xNextTaskUnblockTime ) + 800699a: 4b0b ldr r3, [pc, #44] ; (80069c8 ) + 800699c: 681b ldr r3, [r3, #0] + 800699e: 68ba ldr r2, [r7, #8] + 80069a0: 429a cmp r2, r3 + 80069a2: d202 bcs.n 80069aa + xNextTaskUnblockTime = xTimeToWake; + 80069a4: 4b08 ldr r3, [pc, #32] ; (80069c8 ) + 80069a6: 68ba ldr r2, [r7, #8] + 80069a8: 601a str r2, [r3, #0] +} + 80069aa: 46c0 nop ; (mov r8, r8) + 80069ac: 46bd mov sp, r7 + 80069ae: b004 add sp, #16 + 80069b0: bd80 pop {r7, pc} + 80069b2: 46c0 nop ; (mov r8, r8) + 80069b4: 20000bc4 .word 0x20000bc4 + 80069b8: 200006ec .word 0x200006ec + 80069bc: 20000bac .word 0x20000bac + 80069c0: 20000b7c .word 0x20000b7c + 80069c4: 20000b78 .word 0x20000b78 + 80069c8: 20000be0 .word 0x20000be0 + +080069cc : + TimerCallbackFunction_t pxCallbackFunction, + Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +BaseType_t xTimerCreateTimerTask( void ) +{ + 80069cc: b590 push {r4, r7, lr} + 80069ce: b089 sub sp, #36 ; 0x24 + 80069d0: af04 add r7, sp, #16 +BaseType_t xReturn = pdFAIL; + 80069d2: 2300 movs r3, #0 + 80069d4: 60fb str r3, [r7, #12] + + /* This function is called when the scheduler is started if + configUSE_TIMERS is set to 1. Check that the infrastructure used by the + timer service task has been created/initialised. If timers have already + been created then the initialisation will already have been performed. */ + prvCheckForValidListAndQueue(); + 80069d6: f000 fac9 bl 8006f6c + + if( xTimerQueue != NULL ) + 80069da: 4b17 ldr r3, [pc, #92] ; (8006a38 ) + 80069dc: 681b ldr r3, [r3, #0] + 80069de: 2b00 cmp r3, #0 + 80069e0: d020 beq.n 8006a24 + { + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t *pxTimerTaskTCBBuffer = NULL; + 80069e2: 2300 movs r3, #0 + 80069e4: 60bb str r3, [r7, #8] + StackType_t *pxTimerTaskStackBuffer = NULL; + 80069e6: 2300 movs r3, #0 + 80069e8: 607b str r3, [r7, #4] + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + 80069ea: 003a movs r2, r7 + 80069ec: 1d39 adds r1, r7, #4 + 80069ee: 2308 movs r3, #8 + 80069f0: 18fb adds r3, r7, r3 + 80069f2: 0018 movs r0, r3 + 80069f4: f7fe fb4a bl 800508c + xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + 80069f8: 683c ldr r4, [r7, #0] + 80069fa: 687b ldr r3, [r7, #4] + 80069fc: 68ba ldr r2, [r7, #8] + 80069fe: 490f ldr r1, [pc, #60] ; (8006a3c ) + 8006a00: 480f ldr r0, [pc, #60] ; (8006a40 ) + 8006a02: 9202 str r2, [sp, #8] + 8006a04: 9301 str r3, [sp, #4] + 8006a06: 2302 movs r3, #2 + 8006a08: 9300 str r3, [sp, #0] + 8006a0a: 2300 movs r3, #0 + 8006a0c: 0022 movs r2, r4 + 8006a0e: f7ff f860 bl 8005ad2 + 8006a12: 0002 movs r2, r0 + 8006a14: 4b0b ldr r3, [pc, #44] ; (8006a44 ) + 8006a16: 601a str r2, [r3, #0] + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + 8006a18: 4b0a ldr r3, [pc, #40] ; (8006a44 ) + 8006a1a: 681b ldr r3, [r3, #0] + 8006a1c: 2b00 cmp r3, #0 + 8006a1e: d001 beq.n 8006a24 + { + xReturn = pdPASS; + 8006a20: 2301 movs r3, #1 + 8006a22: 60fb str r3, [r7, #12] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + configASSERT( xReturn ); + 8006a24: 68fb ldr r3, [r7, #12] + 8006a26: 2b00 cmp r3, #0 + 8006a28: d101 bne.n 8006a2e + 8006a2a: b672 cpsid i + 8006a2c: e7fe b.n 8006a2c + return xReturn; + 8006a2e: 68fb ldr r3, [r7, #12] +} + 8006a30: 0018 movs r0, r3 + 8006a32: 46bd mov sp, r7 + 8006a34: b005 add sp, #20 + 8006a36: bd90 pop {r4, r7, pc} + 8006a38: 20000c1c .word 0x20000c1c + 8006a3c: 0800780c .word 0x0800780c + 8006a40: 08006b65 .word 0x08006b65 + 8006a44: 20000c20 .word 0x20000c20 + +08006a48 : + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) +{ + 8006a48: b590 push {r4, r7, lr} + 8006a4a: b08b sub sp, #44 ; 0x2c + 8006a4c: af00 add r7, sp, #0 + 8006a4e: 60f8 str r0, [r7, #12] + 8006a50: 60b9 str r1, [r7, #8] + 8006a52: 607a str r2, [r7, #4] + 8006a54: 603b str r3, [r7, #0] +BaseType_t xReturn = pdFAIL; + 8006a56: 2300 movs r3, #0 + 8006a58: 627b str r3, [r7, #36] ; 0x24 +DaemonTaskMessage_t xMessage; + + configASSERT( xTimer ); + 8006a5a: 68fb ldr r3, [r7, #12] + 8006a5c: 2b00 cmp r3, #0 + 8006a5e: d101 bne.n 8006a64 + 8006a60: b672 cpsid i + 8006a62: e7fe b.n 8006a62 + + /* Send a message to the timer service task to perform a particular action + on a particular timer definition. */ + if( xTimerQueue != NULL ) + 8006a64: 4b1c ldr r3, [pc, #112] ; (8006ad8 ) + 8006a66: 681b ldr r3, [r3, #0] + 8006a68: 2b00 cmp r3, #0 + 8006a6a: d030 beq.n 8006ace + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + 8006a6c: 2414 movs r4, #20 + 8006a6e: 193b adds r3, r7, r4 + 8006a70: 68ba ldr r2, [r7, #8] + 8006a72: 601a str r2, [r3, #0] + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + 8006a74: 193b adds r3, r7, r4 + 8006a76: 687a ldr r2, [r7, #4] + 8006a78: 605a str r2, [r3, #4] + xMessage.u.xTimerParameters.pxTimer = xTimer; + 8006a7a: 193b adds r3, r7, r4 + 8006a7c: 68fa ldr r2, [r7, #12] + 8006a7e: 609a str r2, [r3, #8] + + if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) + 8006a80: 68bb ldr r3, [r7, #8] + 8006a82: 2b05 cmp r3, #5 + 8006a84: dc19 bgt.n 8006aba + { + if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) + 8006a86: f7ff fecf bl 8006828 + 8006a8a: 0003 movs r3, r0 + 8006a8c: 2b02 cmp r3, #2 + 8006a8e: d109 bne.n 8006aa4 + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + 8006a90: 4b11 ldr r3, [pc, #68] ; (8006ad8 ) + 8006a92: 6818 ldr r0, [r3, #0] + 8006a94: 6bba ldr r2, [r7, #56] ; 0x38 + 8006a96: 1939 adds r1, r7, r4 + 8006a98: 2300 movs r3, #0 + 8006a9a: f7fe fcb7 bl 800540c + 8006a9e: 0003 movs r3, r0 + 8006aa0: 627b str r3, [r7, #36] ; 0x24 + 8006aa2: e014 b.n 8006ace + } + else + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); + 8006aa4: 4b0c ldr r3, [pc, #48] ; (8006ad8 ) + 8006aa6: 6818 ldr r0, [r3, #0] + 8006aa8: 2314 movs r3, #20 + 8006aaa: 18f9 adds r1, r7, r3 + 8006aac: 2300 movs r3, #0 + 8006aae: 2200 movs r2, #0 + 8006ab0: f7fe fcac bl 800540c + 8006ab4: 0003 movs r3, r0 + 8006ab6: 627b str r3, [r7, #36] ; 0x24 + 8006ab8: e009 b.n 8006ace + } + } + else + { + xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + 8006aba: 4b07 ldr r3, [pc, #28] ; (8006ad8 ) + 8006abc: 6818 ldr r0, [r3, #0] + 8006abe: 683a ldr r2, [r7, #0] + 8006ac0: 2314 movs r3, #20 + 8006ac2: 18f9 adds r1, r7, r3 + 8006ac4: 2300 movs r3, #0 + 8006ac6: f7fe fd65 bl 8005594 + 8006aca: 0003 movs r3, r0 + 8006acc: 627b str r3, [r7, #36] ; 0x24 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + 8006ace: 6a7b ldr r3, [r7, #36] ; 0x24 +} + 8006ad0: 0018 movs r0, r3 + 8006ad2: 46bd mov sp, r7 + 8006ad4: b00b add sp, #44 ; 0x2c + 8006ad6: bd90 pop {r4, r7, pc} + 8006ad8: 20000c1c .word 0x20000c1c + +08006adc : + return pxTimer->pcTimerName; +} +/*-----------------------------------------------------------*/ + +static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) +{ + 8006adc: b580 push {r7, lr} + 8006ade: b086 sub sp, #24 + 8006ae0: af02 add r7, sp, #8 + 8006ae2: 6078 str r0, [r7, #4] + 8006ae4: 6039 str r1, [r7, #0] +BaseType_t xResult; +Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8006ae6: 4b1e ldr r3, [pc, #120] ; (8006b60 ) + 8006ae8: 681b ldr r3, [r3, #0] + 8006aea: 68db ldr r3, [r3, #12] + 8006aec: 68db ldr r3, [r3, #12] + 8006aee: 60fb str r3, [r7, #12] + + /* Remove the timer from the list of active timers. A check has already + been performed to ensure the list is not empty. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + 8006af0: 68fb ldr r3, [r7, #12] + 8006af2: 3304 adds r3, #4 + 8006af4: 0018 movs r0, r3 + 8006af6: f7fe fb62 bl 80051be + traceTIMER_EXPIRED( pxTimer ); + + /* If the timer is an auto reload timer then calculate the next + expiry time and re-insert the timer in the list of active timers. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + 8006afa: 68fb ldr r3, [r7, #12] + 8006afc: 2228 movs r2, #40 ; 0x28 + 8006afe: 5c9b ldrb r3, [r3, r2] + 8006b00: 001a movs r2, r3 + 8006b02: 2304 movs r3, #4 + 8006b04: 4013 ands r3, r2 + 8006b06: d019 beq.n 8006b3c + { + /* The timer is inserted into a list using a time relative to anything + other than the current time. It will therefore be inserted into the + correct list relative to the time this task thinks it is now. */ + if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) + 8006b08: 68fb ldr r3, [r7, #12] + 8006b0a: 699a ldr r2, [r3, #24] + 8006b0c: 687b ldr r3, [r7, #4] + 8006b0e: 18d1 adds r1, r2, r3 + 8006b10: 687b ldr r3, [r7, #4] + 8006b12: 683a ldr r2, [r7, #0] + 8006b14: 68f8 ldr r0, [r7, #12] + 8006b16: f000 f8c3 bl 8006ca0 + 8006b1a: 1e03 subs r3, r0, #0 + 8006b1c: d017 beq.n 8006b4e + { + /* The timer expired before it was added to the active timer + list. Reload it now. */ + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); + 8006b1e: 687a ldr r2, [r7, #4] + 8006b20: 68f8 ldr r0, [r7, #12] + 8006b22: 2300 movs r3, #0 + 8006b24: 9300 str r3, [sp, #0] + 8006b26: 2300 movs r3, #0 + 8006b28: 2100 movs r1, #0 + 8006b2a: f7ff ff8d bl 8006a48 + 8006b2e: 0003 movs r3, r0 + 8006b30: 60bb str r3, [r7, #8] + configASSERT( xResult ); + 8006b32: 68bb ldr r3, [r7, #8] + 8006b34: 2b00 cmp r3, #0 + 8006b36: d10a bne.n 8006b4e + 8006b38: b672 cpsid i + 8006b3a: e7fe b.n 8006b3a + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + 8006b3c: 68fb ldr r3, [r7, #12] + 8006b3e: 2228 movs r2, #40 ; 0x28 + 8006b40: 5c9b ldrb r3, [r3, r2] + 8006b42: 2201 movs r2, #1 + 8006b44: 4393 bics r3, r2 + 8006b46: b2d9 uxtb r1, r3 + 8006b48: 68fb ldr r3, [r7, #12] + 8006b4a: 2228 movs r2, #40 ; 0x28 + 8006b4c: 5499 strb r1, [r3, r2] + mtCOVERAGE_TEST_MARKER(); + } + + /* Call the timer callback. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + 8006b4e: 68fb ldr r3, [r7, #12] + 8006b50: 6a1b ldr r3, [r3, #32] + 8006b52: 68fa ldr r2, [r7, #12] + 8006b54: 0010 movs r0, r2 + 8006b56: 4798 blx r3 +} + 8006b58: 46c0 nop ; (mov r8, r8) + 8006b5a: 46bd mov sp, r7 + 8006b5c: b004 add sp, #16 + 8006b5e: bd80 pop {r7, pc} + 8006b60: 20000c14 .word 0x20000c14 + +08006b64 : +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( prvTimerTask, pvParameters ) +{ + 8006b64: b580 push {r7, lr} + 8006b66: b084 sub sp, #16 + 8006b68: af00 add r7, sp, #0 + 8006b6a: 6078 str r0, [r7, #4] + + for( ;; ) + { + /* Query the timers list to see if it contains any timers, and if so, + obtain the time at which the next timer will expire. */ + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + 8006b6c: 2308 movs r3, #8 + 8006b6e: 18fb adds r3, r7, r3 + 8006b70: 0018 movs r0, r3 + 8006b72: f000 f853 bl 8006c1c + 8006b76: 0003 movs r3, r0 + 8006b78: 60fb str r3, [r7, #12] + + /* If a timer has expired, process it. Otherwise, block this task + until either a timer does expire, or a command is received. */ + prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); + 8006b7a: 68ba ldr r2, [r7, #8] + 8006b7c: 68fb ldr r3, [r7, #12] + 8006b7e: 0011 movs r1, r2 + 8006b80: 0018 movs r0, r3 + 8006b82: f000 f803 bl 8006b8c + + /* Empty the command queue. */ + prvProcessReceivedCommands(); + 8006b86: f000 f8cd bl 8006d24 + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + 8006b8a: e7ef b.n 8006b6c + +08006b8c : + } +} +/*-----------------------------------------------------------*/ + +static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) +{ + 8006b8c: b580 push {r7, lr} + 8006b8e: b084 sub sp, #16 + 8006b90: af00 add r7, sp, #0 + 8006b92: 6078 str r0, [r7, #4] + 8006b94: 6039 str r1, [r7, #0] +TickType_t xTimeNow; +BaseType_t xTimerListsWereSwitched; + + vTaskSuspendAll(); + 8006b96: f7ff fa11 bl 8005fbc + /* Obtain the time now to make an assessment as to whether the timer + has expired or not. If obtaining the time causes the lists to switch + then don't process this timer as any timers that remained in the list + when the lists were switched will have been processed within the + prvSampleTimeNow() function. */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + 8006b9a: 2308 movs r3, #8 + 8006b9c: 18fb adds r3, r7, r3 + 8006b9e: 0018 movs r0, r3 + 8006ba0: f000 f85e bl 8006c60 + 8006ba4: 0003 movs r3, r0 + 8006ba6: 60fb str r3, [r7, #12] + if( xTimerListsWereSwitched == pdFALSE ) + 8006ba8: 68bb ldr r3, [r7, #8] + 8006baa: 2b00 cmp r3, #0 + 8006bac: d12b bne.n 8006c06 + { + /* The tick count has not overflowed, has the timer expired? */ + if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) + 8006bae: 683b ldr r3, [r7, #0] + 8006bb0: 2b00 cmp r3, #0 + 8006bb2: d10c bne.n 8006bce + 8006bb4: 687a ldr r2, [r7, #4] + 8006bb6: 68fb ldr r3, [r7, #12] + 8006bb8: 429a cmp r2, r3 + 8006bba: d808 bhi.n 8006bce + { + ( void ) xTaskResumeAll(); + 8006bbc: f7ff fa40 bl 8006040 + prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); + 8006bc0: 68fa ldr r2, [r7, #12] + 8006bc2: 687b ldr r3, [r7, #4] + 8006bc4: 0011 movs r1, r2 + 8006bc6: 0018 movs r0, r3 + 8006bc8: f7ff ff88 bl 8006adc + else + { + ( void ) xTaskResumeAll(); + } + } +} + 8006bcc: e01d b.n 8006c0a + if( xListWasEmpty != pdFALSE ) + 8006bce: 683b ldr r3, [r7, #0] + 8006bd0: 2b00 cmp r3, #0 + 8006bd2: d008 beq.n 8006be6 + xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); + 8006bd4: 4b0f ldr r3, [pc, #60] ; (8006c14 ) + 8006bd6: 681b ldr r3, [r3, #0] + 8006bd8: 681b ldr r3, [r3, #0] + 8006bda: 2b00 cmp r3, #0 + 8006bdc: d101 bne.n 8006be2 + 8006bde: 2301 movs r3, #1 + 8006be0: e000 b.n 8006be4 + 8006be2: 2300 movs r3, #0 + 8006be4: 603b str r3, [r7, #0] + vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); + 8006be6: 4b0c ldr r3, [pc, #48] ; (8006c18 ) + 8006be8: 6818 ldr r0, [r3, #0] + 8006bea: 687a ldr r2, [r7, #4] + 8006bec: 68fb ldr r3, [r7, #12] + 8006bee: 1ad3 subs r3, r2, r3 + 8006bf0: 683a ldr r2, [r7, #0] + 8006bf2: 0019 movs r1, r3 + 8006bf4: f7fe ff3a bl 8005a6c + if( xTaskResumeAll() == pdFALSE ) + 8006bf8: f7ff fa22 bl 8006040 + 8006bfc: 1e03 subs r3, r0, #0 + 8006bfe: d104 bne.n 8006c0a + portYIELD_WITHIN_API(); + 8006c00: f000 fa7e bl 8007100 +} + 8006c04: e001 b.n 8006c0a + ( void ) xTaskResumeAll(); + 8006c06: f7ff fa1b bl 8006040 +} + 8006c0a: 46c0 nop ; (mov r8, r8) + 8006c0c: 46bd mov sp, r7 + 8006c0e: b004 add sp, #16 + 8006c10: bd80 pop {r7, pc} + 8006c12: 46c0 nop ; (mov r8, r8) + 8006c14: 20000c18 .word 0x20000c18 + 8006c18: 20000c1c .word 0x20000c1c + +08006c1c : +/*-----------------------------------------------------------*/ + +static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) +{ + 8006c1c: b580 push {r7, lr} + 8006c1e: b084 sub sp, #16 + 8006c20: af00 add r7, sp, #0 + 8006c22: 6078 str r0, [r7, #4] + the timer with the nearest expiry time will expire. If there are no + active timers then just set the next expire time to 0. That will cause + this task to unblock when the tick count overflows, at which point the + timer lists will be switched and the next expiry time can be + re-assessed. */ + *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); + 8006c24: 4b0d ldr r3, [pc, #52] ; (8006c5c ) + 8006c26: 681b ldr r3, [r3, #0] + 8006c28: 681b ldr r3, [r3, #0] + 8006c2a: 2b00 cmp r3, #0 + 8006c2c: d101 bne.n 8006c32 + 8006c2e: 2201 movs r2, #1 + 8006c30: e000 b.n 8006c34 + 8006c32: 2200 movs r2, #0 + 8006c34: 687b ldr r3, [r7, #4] + 8006c36: 601a str r2, [r3, #0] + if( *pxListWasEmpty == pdFALSE ) + 8006c38: 687b ldr r3, [r7, #4] + 8006c3a: 681b ldr r3, [r3, #0] + 8006c3c: 2b00 cmp r3, #0 + 8006c3e: d105 bne.n 8006c4c + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + 8006c40: 4b06 ldr r3, [pc, #24] ; (8006c5c ) + 8006c42: 681b ldr r3, [r3, #0] + 8006c44: 68db ldr r3, [r3, #12] + 8006c46: 681b ldr r3, [r3, #0] + 8006c48: 60fb str r3, [r7, #12] + 8006c4a: e001 b.n 8006c50 + } + else + { + /* Ensure the task unblocks when the tick count rolls over. */ + xNextExpireTime = ( TickType_t ) 0U; + 8006c4c: 2300 movs r3, #0 + 8006c4e: 60fb str r3, [r7, #12] + } + + return xNextExpireTime; + 8006c50: 68fb ldr r3, [r7, #12] +} + 8006c52: 0018 movs r0, r3 + 8006c54: 46bd mov sp, r7 + 8006c56: b004 add sp, #16 + 8006c58: bd80 pop {r7, pc} + 8006c5a: 46c0 nop ; (mov r8, r8) + 8006c5c: 20000c14 .word 0x20000c14 + +08006c60 : +/*-----------------------------------------------------------*/ + +static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) +{ + 8006c60: b580 push {r7, lr} + 8006c62: b084 sub sp, #16 + 8006c64: af00 add r7, sp, #0 + 8006c66: 6078 str r0, [r7, #4] +TickType_t xTimeNow; +PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ + + xTimeNow = xTaskGetTickCount(); + 8006c68: f7ff fa76 bl 8006158 + 8006c6c: 0003 movs r3, r0 + 8006c6e: 60fb str r3, [r7, #12] + + if( xTimeNow < xLastTime ) + 8006c70: 4b0a ldr r3, [pc, #40] ; (8006c9c ) + 8006c72: 681b ldr r3, [r3, #0] + 8006c74: 68fa ldr r2, [r7, #12] + 8006c76: 429a cmp r2, r3 + 8006c78: d205 bcs.n 8006c86 + { + prvSwitchTimerLists(); + 8006c7a: f000 f919 bl 8006eb0 + *pxTimerListsWereSwitched = pdTRUE; + 8006c7e: 687b ldr r3, [r7, #4] + 8006c80: 2201 movs r2, #1 + 8006c82: 601a str r2, [r3, #0] + 8006c84: e002 b.n 8006c8c + } + else + { + *pxTimerListsWereSwitched = pdFALSE; + 8006c86: 687b ldr r3, [r7, #4] + 8006c88: 2200 movs r2, #0 + 8006c8a: 601a str r2, [r3, #0] + } + + xLastTime = xTimeNow; + 8006c8c: 4b03 ldr r3, [pc, #12] ; (8006c9c ) + 8006c8e: 68fa ldr r2, [r7, #12] + 8006c90: 601a str r2, [r3, #0] + + return xTimeNow; + 8006c92: 68fb ldr r3, [r7, #12] +} + 8006c94: 0018 movs r0, r3 + 8006c96: 46bd mov sp, r7 + 8006c98: b004 add sp, #16 + 8006c9a: bd80 pop {r7, pc} + 8006c9c: 20000c24 .word 0x20000c24 + +08006ca0 : +/*-----------------------------------------------------------*/ + +static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) +{ + 8006ca0: b580 push {r7, lr} + 8006ca2: b086 sub sp, #24 + 8006ca4: af00 add r7, sp, #0 + 8006ca6: 60f8 str r0, [r7, #12] + 8006ca8: 60b9 str r1, [r7, #8] + 8006caa: 607a str r2, [r7, #4] + 8006cac: 603b str r3, [r7, #0] +BaseType_t xProcessTimerNow = pdFALSE; + 8006cae: 2300 movs r3, #0 + 8006cb0: 617b str r3, [r7, #20] + + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); + 8006cb2: 68fb ldr r3, [r7, #12] + 8006cb4: 68ba ldr r2, [r7, #8] + 8006cb6: 605a str r2, [r3, #4] + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + 8006cb8: 68fb ldr r3, [r7, #12] + 8006cba: 68fa ldr r2, [r7, #12] + 8006cbc: 611a str r2, [r3, #16] + + if( xNextExpiryTime <= xTimeNow ) + 8006cbe: 68ba ldr r2, [r7, #8] + 8006cc0: 687b ldr r3, [r7, #4] + 8006cc2: 429a cmp r2, r3 + 8006cc4: d812 bhi.n 8006cec + { + /* Has the expiry time elapsed between the command to start/reset a + timer was issued, and the time the command was processed? */ + if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8006cc6: 687a ldr r2, [r7, #4] + 8006cc8: 683b ldr r3, [r7, #0] + 8006cca: 1ad2 subs r2, r2, r3 + 8006ccc: 68fb ldr r3, [r7, #12] + 8006cce: 699b ldr r3, [r3, #24] + 8006cd0: 429a cmp r2, r3 + 8006cd2: d302 bcc.n 8006cda + { + /* The time between a command being issued and the command being + processed actually exceeds the timers period. */ + xProcessTimerNow = pdTRUE; + 8006cd4: 2301 movs r3, #1 + 8006cd6: 617b str r3, [r7, #20] + 8006cd8: e01b b.n 8006d12 + } + else + { + vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); + 8006cda: 4b10 ldr r3, [pc, #64] ; (8006d1c ) + 8006cdc: 681a ldr r2, [r3, #0] + 8006cde: 68fb ldr r3, [r7, #12] + 8006ce0: 3304 adds r3, #4 + 8006ce2: 0019 movs r1, r3 + 8006ce4: 0010 movs r0, r2 + 8006ce6: f7fe fa34 bl 8005152 + 8006cea: e012 b.n 8006d12 + } + } + else + { + if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) + 8006cec: 687a ldr r2, [r7, #4] + 8006cee: 683b ldr r3, [r7, #0] + 8006cf0: 429a cmp r2, r3 + 8006cf2: d206 bcs.n 8006d02 + 8006cf4: 68ba ldr r2, [r7, #8] + 8006cf6: 683b ldr r3, [r7, #0] + 8006cf8: 429a cmp r2, r3 + 8006cfa: d302 bcc.n 8006d02 + { + /* If, since the command was issued, the tick count has overflowed + but the expiry time has not, then the timer must have already passed + its expiry time and should be processed immediately. */ + xProcessTimerNow = pdTRUE; + 8006cfc: 2301 movs r3, #1 + 8006cfe: 617b str r3, [r7, #20] + 8006d00: e007 b.n 8006d12 + } + else + { + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + 8006d02: 4b07 ldr r3, [pc, #28] ; (8006d20 ) + 8006d04: 681a ldr r2, [r3, #0] + 8006d06: 68fb ldr r3, [r7, #12] + 8006d08: 3304 adds r3, #4 + 8006d0a: 0019 movs r1, r3 + 8006d0c: 0010 movs r0, r2 + 8006d0e: f7fe fa20 bl 8005152 + } + } + + return xProcessTimerNow; + 8006d12: 697b ldr r3, [r7, #20] +} + 8006d14: 0018 movs r0, r3 + 8006d16: 46bd mov sp, r7 + 8006d18: b006 add sp, #24 + 8006d1a: bd80 pop {r7, pc} + 8006d1c: 20000c18 .word 0x20000c18 + 8006d20: 20000c14 .word 0x20000c14 + +08006d24 : +/*-----------------------------------------------------------*/ + +static void prvProcessReceivedCommands( void ) +{ + 8006d24: b590 push {r4, r7, lr} + 8006d26: b08d sub sp, #52 ; 0x34 + 8006d28: af02 add r7, sp, #8 +DaemonTaskMessage_t xMessage; +Timer_t *pxTimer; +BaseType_t xTimerListsWereSwitched, xResult; +TickType_t xTimeNow; + + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + 8006d2a: e0ac b.n 8006e86 + { + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + { + /* Negative commands are pended function calls rather than timer + commands. */ + if( xMessage.xMessageID < ( BaseType_t ) 0 ) + 8006d2c: 2208 movs r2, #8 + 8006d2e: 18bb adds r3, r7, r2 + 8006d30: 681b ldr r3, [r3, #0] + 8006d32: 2b00 cmp r3, #0 + 8006d34: da0f bge.n 8006d56 + { + const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); + 8006d36: 18bb adds r3, r7, r2 + 8006d38: 3304 adds r3, #4 + 8006d3a: 627b str r3, [r7, #36] ; 0x24 + + /* The timer uses the xCallbackParameters member to request a + callback be executed. Check the callback is not NULL. */ + configASSERT( pxCallback ); + 8006d3c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006d3e: 2b00 cmp r3, #0 + 8006d40: d101 bne.n 8006d46 + 8006d42: b672 cpsid i + 8006d44: e7fe b.n 8006d44 + + /* Call the function. */ + pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); + 8006d46: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006d48: 681a ldr r2, [r3, #0] + 8006d4a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006d4c: 6858 ldr r0, [r3, #4] + 8006d4e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006d50: 689b ldr r3, [r3, #8] + 8006d52: 0019 movs r1, r3 + 8006d54: 4790 blx r2 + } + #endif /* INCLUDE_xTimerPendFunctionCall */ + + /* Commands that are positive are timer commands rather than pended + function calls. */ + if( xMessage.xMessageID >= ( BaseType_t ) 0 ) + 8006d56: 2208 movs r2, #8 + 8006d58: 18bb adds r3, r7, r2 + 8006d5a: 681b ldr r3, [r3, #0] + 8006d5c: 2b00 cmp r3, #0 + 8006d5e: da00 bge.n 8006d62 + 8006d60: e090 b.n 8006e84 + { + /* The messages uses the xTimerParameters member to work on a + software timer. */ + pxTimer = xMessage.u.xTimerParameters.pxTimer; + 8006d62: 18bb adds r3, r7, r2 + 8006d64: 689b ldr r3, [r3, #8] + 8006d66: 623b str r3, [r7, #32] + + if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ + 8006d68: 6a3b ldr r3, [r7, #32] + 8006d6a: 695b ldr r3, [r3, #20] + 8006d6c: 2b00 cmp r3, #0 + 8006d6e: d004 beq.n 8006d7a + { + /* The timer is in a list, remove it. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + 8006d70: 6a3b ldr r3, [r7, #32] + 8006d72: 3304 adds r3, #4 + 8006d74: 0018 movs r0, r3 + 8006d76: f7fe fa22 bl 80051be + it must be present in the function call. prvSampleTimeNow() must be + called after the message is received from xTimerQueue so there is no + possibility of a higher priority task adding a message to the message + queue with a time that is ahead of the timer daemon task (because it + pre-empted the timer daemon task after the xTimeNow value was set). */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + 8006d7a: 1d3b adds r3, r7, #4 + 8006d7c: 0018 movs r0, r3 + 8006d7e: f7ff ff6f bl 8006c60 + 8006d82: 0003 movs r3, r0 + 8006d84: 61fb str r3, [r7, #28] + + switch( xMessage.xMessageID ) + 8006d86: 2308 movs r3, #8 + 8006d88: 18fb adds r3, r7, r3 + 8006d8a: 681b ldr r3, [r3, #0] + 8006d8c: 2b09 cmp r3, #9 + 8006d8e: d900 bls.n 8006d92 + 8006d90: e079 b.n 8006e86 + 8006d92: 009a lsls r2, r3, #2 + 8006d94: 4b44 ldr r3, [pc, #272] ; (8006ea8 ) + 8006d96: 18d3 adds r3, r2, r3 + 8006d98: 681b ldr r3, [r3, #0] + 8006d9a: 469f mov pc, r3 + case tmrCOMMAND_START_FROM_ISR : + case tmrCOMMAND_RESET : + case tmrCOMMAND_RESET_FROM_ISR : + case tmrCOMMAND_START_DONT_TRACE : + /* Start or restart a timer. */ + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + 8006d9c: 6a3b ldr r3, [r7, #32] + 8006d9e: 2228 movs r2, #40 ; 0x28 + 8006da0: 5c9b ldrb r3, [r3, r2] + 8006da2: 2201 movs r2, #1 + 8006da4: 4313 orrs r3, r2 + 8006da6: b2d9 uxtb r1, r3 + 8006da8: 6a3b ldr r3, [r7, #32] + 8006daa: 2228 movs r2, #40 ; 0x28 + 8006dac: 5499 strb r1, [r3, r2] + if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) + 8006dae: 2408 movs r4, #8 + 8006db0: 193b adds r3, r7, r4 + 8006db2: 685a ldr r2, [r3, #4] + 8006db4: 6a3b ldr r3, [r7, #32] + 8006db6: 699b ldr r3, [r3, #24] + 8006db8: 18d1 adds r1, r2, r3 + 8006dba: 193b adds r3, r7, r4 + 8006dbc: 685b ldr r3, [r3, #4] + 8006dbe: 69fa ldr r2, [r7, #28] + 8006dc0: 6a38 ldr r0, [r7, #32] + 8006dc2: f7ff ff6d bl 8006ca0 + 8006dc6: 1e03 subs r3, r0, #0 + 8006dc8: d05d beq.n 8006e86 + { + /* The timer expired before it was added to the active + timer list. Process it now. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + 8006dca: 6a3b ldr r3, [r7, #32] + 8006dcc: 6a1b ldr r3, [r3, #32] + 8006dce: 6a3a ldr r2, [r7, #32] + 8006dd0: 0010 movs r0, r2 + 8006dd2: 4798 blx r3 + traceTIMER_EXPIRED( pxTimer ); + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + 8006dd4: 6a3b ldr r3, [r7, #32] + 8006dd6: 2228 movs r2, #40 ; 0x28 + 8006dd8: 5c9b ldrb r3, [r3, r2] + 8006dda: 001a movs r2, r3 + 8006ddc: 2304 movs r3, #4 + 8006dde: 4013 ands r3, r2 + 8006de0: d051 beq.n 8006e86 + { + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); + 8006de2: 193b adds r3, r7, r4 + 8006de4: 685a ldr r2, [r3, #4] + 8006de6: 6a3b ldr r3, [r7, #32] + 8006de8: 699b ldr r3, [r3, #24] + 8006dea: 18d2 adds r2, r2, r3 + 8006dec: 6a38 ldr r0, [r7, #32] + 8006dee: 2300 movs r3, #0 + 8006df0: 9300 str r3, [sp, #0] + 8006df2: 2300 movs r3, #0 + 8006df4: 2100 movs r1, #0 + 8006df6: f7ff fe27 bl 8006a48 + 8006dfa: 0003 movs r3, r0 + 8006dfc: 61bb str r3, [r7, #24] + configASSERT( xResult ); + 8006dfe: 69bb ldr r3, [r7, #24] + 8006e00: 2b00 cmp r3, #0 + 8006e02: d140 bne.n 8006e86 + 8006e04: b672 cpsid i + 8006e06: e7fe b.n 8006e06 + break; + + case tmrCOMMAND_STOP : + case tmrCOMMAND_STOP_FROM_ISR : + /* The timer has already been removed from the active list. */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + 8006e08: 6a3b ldr r3, [r7, #32] + 8006e0a: 2228 movs r2, #40 ; 0x28 + 8006e0c: 5c9b ldrb r3, [r3, r2] + 8006e0e: 2201 movs r2, #1 + 8006e10: 4393 bics r3, r2 + 8006e12: b2d9 uxtb r1, r3 + 8006e14: 6a3b ldr r3, [r7, #32] + 8006e16: 2228 movs r2, #40 ; 0x28 + 8006e18: 5499 strb r1, [r3, r2] + break; + 8006e1a: e034 b.n 8006e86 + + case tmrCOMMAND_CHANGE_PERIOD : + case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + 8006e1c: 6a3b ldr r3, [r7, #32] + 8006e1e: 2228 movs r2, #40 ; 0x28 + 8006e20: 5c9b ldrb r3, [r3, r2] + 8006e22: 2201 movs r2, #1 + 8006e24: 4313 orrs r3, r2 + 8006e26: b2d9 uxtb r1, r3 + 8006e28: 6a3b ldr r3, [r7, #32] + 8006e2a: 2228 movs r2, #40 ; 0x28 + 8006e2c: 5499 strb r1, [r3, r2] + pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; + 8006e2e: 2308 movs r3, #8 + 8006e30: 18fb adds r3, r7, r3 + 8006e32: 685a ldr r2, [r3, #4] + 8006e34: 6a3b ldr r3, [r7, #32] + 8006e36: 619a str r2, [r3, #24] + configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); + 8006e38: 6a3b ldr r3, [r7, #32] + 8006e3a: 699b ldr r3, [r3, #24] + 8006e3c: 2b00 cmp r3, #0 + 8006e3e: d101 bne.n 8006e44 + 8006e40: b672 cpsid i + 8006e42: e7fe b.n 8006e42 + be longer or shorter than the old one. The command time is + therefore set to the current time, and as the period cannot + be zero the next expiry time can only be in the future, + meaning (unlike for the xTimerStart() case above) there is + no fail case that needs to be handled here. */ + ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); + 8006e44: 6a3b ldr r3, [r7, #32] + 8006e46: 699a ldr r2, [r3, #24] + 8006e48: 69fb ldr r3, [r7, #28] + 8006e4a: 18d1 adds r1, r2, r3 + 8006e4c: 69fb ldr r3, [r7, #28] + 8006e4e: 69fa ldr r2, [r7, #28] + 8006e50: 6a38 ldr r0, [r7, #32] + 8006e52: f7ff ff25 bl 8006ca0 + break; + 8006e56: e016 b.n 8006e86 + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* The timer has already been removed from the active list, + just free up the memory if the memory was dynamically + allocated. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) + 8006e58: 6a3b ldr r3, [r7, #32] + 8006e5a: 2228 movs r2, #40 ; 0x28 + 8006e5c: 5c9b ldrb r3, [r3, r2] + 8006e5e: 001a movs r2, r3 + 8006e60: 2302 movs r3, #2 + 8006e62: 4013 ands r3, r2 + 8006e64: d104 bne.n 8006e70 + { + vPortFree( pxTimer ); + 8006e66: 6a3b ldr r3, [r7, #32] + 8006e68: 0018 movs r0, r3 + 8006e6a: f000 fb7b bl 8007564 + 8006e6e: e00a b.n 8006e86 + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + 8006e70: 6a3b ldr r3, [r7, #32] + 8006e72: 2228 movs r2, #40 ; 0x28 + 8006e74: 5c9b ldrb r3, [r3, r2] + 8006e76: 2201 movs r2, #1 + 8006e78: 4393 bics r3, r2 + 8006e7a: b2d9 uxtb r1, r3 + 8006e7c: 6a3b ldr r3, [r7, #32] + 8006e7e: 2228 movs r2, #40 ; 0x28 + 8006e80: 5499 strb r1, [r3, r2] + no need to free the memory - just mark the timer as + "not active". */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + break; + 8006e82: e000 b.n 8006e86 + + default : + /* Don't expect to get here. */ + break; + } + } + 8006e84: 46c0 nop ; (mov r8, r8) + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + 8006e86: 4b09 ldr r3, [pc, #36] ; (8006eac ) + 8006e88: 681b ldr r3, [r3, #0] + 8006e8a: 2208 movs r2, #8 + 8006e8c: 18b9 adds r1, r7, r2 + 8006e8e: 2200 movs r2, #0 + 8006e90: 0018 movs r0, r3 + 8006e92: f7fe fbf0 bl 8005676 + 8006e96: 1e03 subs r3, r0, #0 + 8006e98: d000 beq.n 8006e9c + 8006e9a: e747 b.n 8006d2c + } +} + 8006e9c: 46c0 nop ; (mov r8, r8) + 8006e9e: 46c0 nop ; (mov r8, r8) + 8006ea0: 46bd mov sp, r7 + 8006ea2: b00b add sp, #44 ; 0x2c + 8006ea4: bd90 pop {r4, r7, pc} + 8006ea6: 46c0 nop ; (mov r8, r8) + 8006ea8: 080078f0 .word 0x080078f0 + 8006eac: 20000c1c .word 0x20000c1c + +08006eb0 : +/*-----------------------------------------------------------*/ + +static void prvSwitchTimerLists( void ) +{ + 8006eb0: b580 push {r7, lr} + 8006eb2: b088 sub sp, #32 + 8006eb4: af02 add r7, sp, #8 + + /* The tick count has overflowed. The timer lists must be switched. + If there are any timers still referenced from the current timer list + then they must have expired and should be processed before the lists + are switched. */ + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + 8006eb6: e041 b.n 8006f3c + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + 8006eb8: 4b2a ldr r3, [pc, #168] ; (8006f64 ) + 8006eba: 681b ldr r3, [r3, #0] + 8006ebc: 68db ldr r3, [r3, #12] + 8006ebe: 681b ldr r3, [r3, #0] + 8006ec0: 613b str r3, [r7, #16] + + /* Remove the timer from the list. */ + pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8006ec2: 4b28 ldr r3, [pc, #160] ; (8006f64 ) + 8006ec4: 681b ldr r3, [r3, #0] + 8006ec6: 68db ldr r3, [r3, #12] + 8006ec8: 68db ldr r3, [r3, #12] + 8006eca: 60fb str r3, [r7, #12] + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + 8006ecc: 68fb ldr r3, [r7, #12] + 8006ece: 3304 adds r3, #4 + 8006ed0: 0018 movs r0, r3 + 8006ed2: f7fe f974 bl 80051be + traceTIMER_EXPIRED( pxTimer ); + + /* Execute its callback, then send a command to restart the timer if + it is an auto-reload timer. It cannot be restarted here as the lists + have not yet been switched. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + 8006ed6: 68fb ldr r3, [r7, #12] + 8006ed8: 6a1b ldr r3, [r3, #32] + 8006eda: 68fa ldr r2, [r7, #12] + 8006edc: 0010 movs r0, r2 + 8006ede: 4798 blx r3 + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + 8006ee0: 68fb ldr r3, [r7, #12] + 8006ee2: 2228 movs r2, #40 ; 0x28 + 8006ee4: 5c9b ldrb r3, [r3, r2] + 8006ee6: 001a movs r2, r3 + 8006ee8: 2304 movs r3, #4 + 8006eea: 4013 ands r3, r2 + 8006eec: d026 beq.n 8006f3c + the timer going into the same timer list then it has already expired + and the timer should be re-inserted into the current list so it is + processed again within this loop. Otherwise a command should be sent + to restart the timer to ensure it is only inserted into a list after + the lists have been swapped. */ + xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); + 8006eee: 68fb ldr r3, [r7, #12] + 8006ef0: 699b ldr r3, [r3, #24] + 8006ef2: 693a ldr r2, [r7, #16] + 8006ef4: 18d3 adds r3, r2, r3 + 8006ef6: 60bb str r3, [r7, #8] + if( xReloadTime > xNextExpireTime ) + 8006ef8: 68ba ldr r2, [r7, #8] + 8006efa: 693b ldr r3, [r7, #16] + 8006efc: 429a cmp r2, r3 + 8006efe: d90e bls.n 8006f1e + { + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); + 8006f00: 68fb ldr r3, [r7, #12] + 8006f02: 68ba ldr r2, [r7, #8] + 8006f04: 605a str r2, [r3, #4] + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + 8006f06: 68fb ldr r3, [r7, #12] + 8006f08: 68fa ldr r2, [r7, #12] + 8006f0a: 611a str r2, [r3, #16] + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + 8006f0c: 4b15 ldr r3, [pc, #84] ; (8006f64 ) + 8006f0e: 681a ldr r2, [r3, #0] + 8006f10: 68fb ldr r3, [r7, #12] + 8006f12: 3304 adds r3, #4 + 8006f14: 0019 movs r1, r3 + 8006f16: 0010 movs r0, r2 + 8006f18: f7fe f91b bl 8005152 + 8006f1c: e00e b.n 8006f3c + } + else + { + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); + 8006f1e: 693a ldr r2, [r7, #16] + 8006f20: 68f8 ldr r0, [r7, #12] + 8006f22: 2300 movs r3, #0 + 8006f24: 9300 str r3, [sp, #0] + 8006f26: 2300 movs r3, #0 + 8006f28: 2100 movs r1, #0 + 8006f2a: f7ff fd8d bl 8006a48 + 8006f2e: 0003 movs r3, r0 + 8006f30: 607b str r3, [r7, #4] + configASSERT( xResult ); + 8006f32: 687b ldr r3, [r7, #4] + 8006f34: 2b00 cmp r3, #0 + 8006f36: d101 bne.n 8006f3c + 8006f38: b672 cpsid i + 8006f3a: e7fe b.n 8006f3a + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + 8006f3c: 4b09 ldr r3, [pc, #36] ; (8006f64 ) + 8006f3e: 681b ldr r3, [r3, #0] + 8006f40: 681b ldr r3, [r3, #0] + 8006f42: 2b00 cmp r3, #0 + 8006f44: d1b8 bne.n 8006eb8 + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxTemp = pxCurrentTimerList; + 8006f46: 4b07 ldr r3, [pc, #28] ; (8006f64 ) + 8006f48: 681b ldr r3, [r3, #0] + 8006f4a: 617b str r3, [r7, #20] + pxCurrentTimerList = pxOverflowTimerList; + 8006f4c: 4b06 ldr r3, [pc, #24] ; (8006f68 ) + 8006f4e: 681a ldr r2, [r3, #0] + 8006f50: 4b04 ldr r3, [pc, #16] ; (8006f64 ) + 8006f52: 601a str r2, [r3, #0] + pxOverflowTimerList = pxTemp; + 8006f54: 4b04 ldr r3, [pc, #16] ; (8006f68 ) + 8006f56: 697a ldr r2, [r7, #20] + 8006f58: 601a str r2, [r3, #0] +} + 8006f5a: 46c0 nop ; (mov r8, r8) + 8006f5c: 46bd mov sp, r7 + 8006f5e: b006 add sp, #24 + 8006f60: bd80 pop {r7, pc} + 8006f62: 46c0 nop ; (mov r8, r8) + 8006f64: 20000c14 .word 0x20000c14 + 8006f68: 20000c18 .word 0x20000c18 + +08006f6c : +/*-----------------------------------------------------------*/ + +static void prvCheckForValidListAndQueue( void ) +{ + 8006f6c: b580 push {r7, lr} + 8006f6e: b082 sub sp, #8 + 8006f70: af02 add r7, sp, #8 + /* Check that the list from which active timers are referenced, and the + queue used to communicate with the timer service, have been + initialised. */ + taskENTER_CRITICAL(); + 8006f72: f000 f8d5 bl 8007120 + { + if( xTimerQueue == NULL ) + 8006f76: 4b16 ldr r3, [pc, #88] ; (8006fd0 ) + 8006f78: 681b ldr r3, [r3, #0] + 8006f7a: 2b00 cmp r3, #0 + 8006f7c: d123 bne.n 8006fc6 + { + vListInitialise( &xActiveTimerList1 ); + 8006f7e: 4b15 ldr r3, [pc, #84] ; (8006fd4 ) + 8006f80: 0018 movs r0, r3 + 8006f82: f7fe f89b bl 80050bc + vListInitialise( &xActiveTimerList2 ); + 8006f86: 4b14 ldr r3, [pc, #80] ; (8006fd8 ) + 8006f88: 0018 movs r0, r3 + 8006f8a: f7fe f897 bl 80050bc + pxCurrentTimerList = &xActiveTimerList1; + 8006f8e: 4b13 ldr r3, [pc, #76] ; (8006fdc ) + 8006f90: 4a10 ldr r2, [pc, #64] ; (8006fd4 ) + 8006f92: 601a str r2, [r3, #0] + pxOverflowTimerList = &xActiveTimerList2; + 8006f94: 4b12 ldr r3, [pc, #72] ; (8006fe0 ) + 8006f96: 4a10 ldr r2, [pc, #64] ; (8006fd8 ) + 8006f98: 601a str r2, [r3, #0] + /* The timer queue is allocated statically in case + configSUPPORT_DYNAMIC_ALLOCATION is 0. */ + static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + + xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); + 8006f9a: 4b12 ldr r3, [pc, #72] ; (8006fe4 ) + 8006f9c: 4a12 ldr r2, [pc, #72] ; (8006fe8 ) + 8006f9e: 2100 movs r1, #0 + 8006fa0: 9100 str r1, [sp, #0] + 8006fa2: 2110 movs r1, #16 + 8006fa4: 200a movs r0, #10 + 8006fa6: f7fe f986 bl 80052b6 + 8006faa: 0002 movs r2, r0 + 8006fac: 4b08 ldr r3, [pc, #32] ; (8006fd0 ) + 8006fae: 601a str r2, [r3, #0] + } + #endif + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + if( xTimerQueue != NULL ) + 8006fb0: 4b07 ldr r3, [pc, #28] ; (8006fd0 ) + 8006fb2: 681b ldr r3, [r3, #0] + 8006fb4: 2b00 cmp r3, #0 + 8006fb6: d006 beq.n 8006fc6 + { + vQueueAddToRegistry( xTimerQueue, "TmrQ" ); + 8006fb8: 4b05 ldr r3, [pc, #20] ; (8006fd0 ) + 8006fba: 681b ldr r3, [r3, #0] + 8006fbc: 4a0b ldr r2, [pc, #44] ; (8006fec ) + 8006fbe: 0011 movs r1, r2 + 8006fc0: 0018 movs r0, r3 + 8006fc2: f7fe fd2b bl 8005a1c + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + 8006fc6: f000 f8bd bl 8007144 +} + 8006fca: 46c0 nop ; (mov r8, r8) + 8006fcc: 46bd mov sp, r7 + 8006fce: bd80 pop {r7, pc} + 8006fd0: 20000c1c .word 0x20000c1c + 8006fd4: 20000bec .word 0x20000bec + 8006fd8: 20000c00 .word 0x20000c00 + 8006fdc: 20000c14 .word 0x20000c14 + 8006fe0: 20000c18 .word 0x20000c18 + 8006fe4: 20000cc8 .word 0x20000cc8 + 8006fe8: 20000c28 .word 0x20000c28 + 8006fec: 08007814 .word 0x08007814 + +08006ff0 : + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + 8006ff0: b580 push {r7, lr} + 8006ff2: b084 sub sp, #16 + 8006ff4: af00 add r7, sp, #0 + 8006ff6: 60f8 str r0, [r7, #12] + 8006ff8: 60b9 str r1, [r7, #8] + 8006ffa: 607a str r2, [r7, #4] + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + 8006ffc: 68fb ldr r3, [r7, #12] + 8006ffe: 3b04 subs r3, #4 + 8007000: 60fb str r3, [r7, #12] + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + 8007002: 68fb ldr r3, [r7, #12] + 8007004: 2280 movs r2, #128 ; 0x80 + 8007006: 0452 lsls r2, r2, #17 + 8007008: 601a str r2, [r3, #0] + pxTopOfStack--; + 800700a: 68fb ldr r3, [r7, #12] + 800700c: 3b04 subs r3, #4 + 800700e: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + 8007010: 68ba ldr r2, [r7, #8] + 8007012: 68fb ldr r3, [r7, #12] + 8007014: 601a str r2, [r3, #0] + pxTopOfStack--; + 8007016: 68fb ldr r3, [r7, #12] + 8007018: 3b04 subs r3, #4 + 800701a: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + 800701c: 4a08 ldr r2, [pc, #32] ; (8007040 ) + 800701e: 68fb ldr r3, [r7, #12] + 8007020: 601a str r2, [r3, #0] + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + 8007022: 68fb ldr r3, [r7, #12] + 8007024: 3b14 subs r3, #20 + 8007026: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + 8007028: 687a ldr r2, [r7, #4] + 800702a: 68fb ldr r3, [r7, #12] + 800702c: 601a str r2, [r3, #0] + pxTopOfStack -= 8; /* R11..R4. */ + 800702e: 68fb ldr r3, [r7, #12] + 8007030: 3b20 subs r3, #32 + 8007032: 60fb str r3, [r7, #12] + + return pxTopOfStack; + 8007034: 68fb ldr r3, [r7, #12] +} + 8007036: 0018 movs r0, r3 + 8007038: 46bd mov sp, r7 + 800703a: b004 add sp, #16 + 800703c: bd80 pop {r7, pc} + 800703e: 46c0 nop ; (mov r8, r8) + 8007040: 08007045 .word 0x08007045 + +08007044 : +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + 8007044: b580 push {r7, lr} + 8007046: b082 sub sp, #8 + 8007048: af00 add r7, sp, #0 +volatile uint32_t ulDummy = 0UL; + 800704a: 2300 movs r3, #0 + 800704c: 607b str r3, [r7, #4] + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + 800704e: 4b08 ldr r3, [pc, #32] ; (8007070 ) + 8007050: 681b ldr r3, [r3, #0] + 8007052: 3301 adds r3, #1 + 8007054: d001 beq.n 800705a + 8007056: b672 cpsid i + 8007058: e7fe b.n 8007058 + portDISABLE_INTERRUPTS(); + 800705a: b672 cpsid i + while( ulDummy == 0 ) + 800705c: 46c0 nop ; (mov r8, r8) + 800705e: 687b ldr r3, [r7, #4] + 8007060: 2b00 cmp r3, #0 + 8007062: d0fc beq.n 800705e + about code appearing after this function is called - making ulDummy + volatile makes the compiler think the function could return and + therefore not output an 'unreachable code' warning for code that appears + after it. */ + } +} + 8007064: 46c0 nop ; (mov r8, r8) + 8007066: 46c0 nop ; (mov r8, r8) + 8007068: 46bd mov sp, r7 + 800706a: b002 add sp, #8 + 800706c: bd80 pop {r7, pc} + 800706e: 46c0 nop ; (mov r8, r8) + 8007070: 2000000c .word 0x2000000c + +08007074 : +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + 8007074: b580 push {r7, lr} + 8007076: af00 add r7, sp, #0 + /* This function is no longer used, but retained for backward + compatibility. */ +} + 8007078: 46c0 nop ; (mov r8, r8) + 800707a: 46bd mov sp, r7 + 800707c: bd80 pop {r7, pc} + ... + +08007080 : +void vPortStartFirstTask( void ) +{ + /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector + table offset register that can be used to locate the initial stack value. + Not all M0 parts have the application vector table at address 0. */ + __asm volatile( + 8007080: 4a0b ldr r2, [pc, #44] ; (80070b0 ) + 8007082: 6813 ldr r3, [r2, #0] + 8007084: 6818 ldr r0, [r3, #0] + 8007086: 3020 adds r0, #32 + 8007088: f380 8809 msr PSP, r0 + 800708c: 2002 movs r0, #2 + 800708e: f380 8814 msr CONTROL, r0 + 8007092: f3bf 8f6f isb sy + 8007096: bc3f pop {r0, r1, r2, r3, r4, r5} + 8007098: 46ae mov lr, r5 + 800709a: bc08 pop {r3} + 800709c: bc04 pop {r2} + 800709e: b662 cpsie i + 80070a0: 4718 bx r3 + 80070a2: 46c0 nop ; (mov r8, r8) + 80070a4: 46c0 nop ; (mov r8, r8) + 80070a6: 46c0 nop ; (mov r8, r8) + 80070a8: 46c0 nop ; (mov r8, r8) + 80070aa: 46c0 nop ; (mov r8, r8) + 80070ac: 46c0 nop ; (mov r8, r8) + 80070ae: 46c0 nop ; (mov r8, r8) + +080070b0 : + 80070b0: 200006ec .word 0x200006ec + " bx r3 \n" /* Finally, jump to the user defined task code. */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB " + ); +} + 80070b4: 46c0 nop ; (mov r8, r8) + 80070b6: 46c0 nop ; (mov r8, r8) + +080070b8 : + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + 80070b8: b580 push {r7, lr} + 80070ba: af00 add r7, sp, #0 + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; + 80070bc: 4b0e ldr r3, [pc, #56] ; (80070f8 ) + 80070be: 681a ldr r2, [r3, #0] + 80070c0: 4b0d ldr r3, [pc, #52] ; (80070f8 ) + 80070c2: 21ff movs r1, #255 ; 0xff + 80070c4: 0409 lsls r1, r1, #16 + 80070c6: 430a orrs r2, r1 + 80070c8: 601a str r2, [r3, #0] + *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; + 80070ca: 4b0b ldr r3, [pc, #44] ; (80070f8 ) + 80070cc: 681a ldr r2, [r3, #0] + 80070ce: 4b0a ldr r3, [pc, #40] ; (80070f8 ) + 80070d0: 21ff movs r1, #255 ; 0xff + 80070d2: 0609 lsls r1, r1, #24 + 80070d4: 430a orrs r2, r1 + 80070d6: 601a str r2, [r3, #0] + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + 80070d8: f000 f95e bl 8007398 + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + 80070dc: 4b07 ldr r3, [pc, #28] ; (80070fc ) + 80070de: 2200 movs r2, #0 + 80070e0: 601a str r2, [r3, #0] + + /* Start the first task. */ + vPortStartFirstTask(); + 80070e2: f7ff ffcd bl 8007080 + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. Call + vTaskSwitchContext() so link time optimisation does not remove the + symbol. */ + vTaskSwitchContext(); + 80070e6: f7ff f911 bl 800630c + prvTaskExitError(); + 80070ea: f7ff ffab bl 8007044 + + /* Should not get here! */ + return 0; + 80070ee: 2300 movs r3, #0 +} + 80070f0: 0018 movs r0, r3 + 80070f2: 46bd mov sp, r7 + 80070f4: bd80 pop {r7, pc} + 80070f6: 46c0 nop ; (mov r8, r8) + 80070f8: e000ed20 .word 0xe000ed20 + 80070fc: 2000000c .word 0x2000000c + +08007100 : + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + 8007100: b580 push {r7, lr} + 8007102: af00 add r7, sp, #0 + /* Set a PendSV to request a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + 8007104: 4b05 ldr r3, [pc, #20] ; (800711c ) + 8007106: 2280 movs r2, #128 ; 0x80 + 8007108: 0552 lsls r2, r2, #21 + 800710a: 601a str r2, [r3, #0] + + /* Barriers are normally not required but do ensure the code is completely + within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + 800710c: f3bf 8f4f dsb sy + __asm volatile( "isb" ); + 8007110: f3bf 8f6f isb sy +} + 8007114: 46c0 nop ; (mov r8, r8) + 8007116: 46bd mov sp, r7 + 8007118: bd80 pop {r7, pc} + 800711a: 46c0 nop ; (mov r8, r8) + 800711c: e000ed04 .word 0xe000ed04 + +08007120 : +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + 8007120: b580 push {r7, lr} + 8007122: af00 add r7, sp, #0 + portDISABLE_INTERRUPTS(); + 8007124: b672 cpsid i + uxCriticalNesting++; + 8007126: 4b06 ldr r3, [pc, #24] ; (8007140 ) + 8007128: 681b ldr r3, [r3, #0] + 800712a: 1c5a adds r2, r3, #1 + 800712c: 4b04 ldr r3, [pc, #16] ; (8007140 ) + 800712e: 601a str r2, [r3, #0] + __asm volatile( "dsb" ::: "memory" ); + 8007130: f3bf 8f4f dsb sy + __asm volatile( "isb" ); + 8007134: f3bf 8f6f isb sy +} + 8007138: 46c0 nop ; (mov r8, r8) + 800713a: 46bd mov sp, r7 + 800713c: bd80 pop {r7, pc} + 800713e: 46c0 nop ; (mov r8, r8) + 8007140: 2000000c .word 0x2000000c + +08007144 : +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + 8007144: b580 push {r7, lr} + 8007146: af00 add r7, sp, #0 + configASSERT( uxCriticalNesting ); + 8007148: 4b09 ldr r3, [pc, #36] ; (8007170 ) + 800714a: 681b ldr r3, [r3, #0] + 800714c: 2b00 cmp r3, #0 + 800714e: d101 bne.n 8007154 + 8007150: b672 cpsid i + 8007152: e7fe b.n 8007152 + uxCriticalNesting--; + 8007154: 4b06 ldr r3, [pc, #24] ; (8007170 ) + 8007156: 681b ldr r3, [r3, #0] + 8007158: 1e5a subs r2, r3, #1 + 800715a: 4b05 ldr r3, [pc, #20] ; (8007170 ) + 800715c: 601a str r2, [r3, #0] + if( uxCriticalNesting == 0 ) + 800715e: 4b04 ldr r3, [pc, #16] ; (8007170 ) + 8007160: 681b ldr r3, [r3, #0] + 8007162: 2b00 cmp r3, #0 + 8007164: d100 bne.n 8007168 + { + portENABLE_INTERRUPTS(); + 8007166: b662 cpsie i + } +} + 8007168: 46c0 nop ; (mov r8, r8) + 800716a: 46bd mov sp, r7 + 800716c: bd80 pop {r7, pc} + 800716e: 46c0 nop ; (mov r8, r8) + 8007170: 2000000c .word 0x2000000c + +08007174 : +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMaskFromISR( void ) +{ + __asm volatile( + 8007174: f3ef 8010 mrs r0, PRIMASK + 8007178: b672 cpsid i + 800717a: 4770 bx lr + /* To avoid compiler warnings. The return statement will nevere be reached, + but some compilers warn if it is not included, while others won't compile if + it is. */ + return 0; +#endif +} + 800717c: 46c0 nop ; (mov r8, r8) + 800717e: 0018 movs r0, r3 + +08007180 : +/*-----------------------------------------------------------*/ + +void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) +{ + __asm volatile( + 8007180: f380 8810 msr PRIMASK, r0 + 8007184: 4770 bx lr + /* Just to avoid compiler warning. ulMask is used from the asm code but + the compiler can't see that. Some compilers generate warnings without the + following line, while others generate warnings if the line is included. */ + ( void ) ulMask; +#endif +} + 8007186: 46c0 nop ; (mov r8, r8) + ... + +08007190 : + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + 8007190: f3ef 8009 mrs r0, PSP + 8007194: 4b0e ldr r3, [pc, #56] ; (80071d0 ) + 8007196: 681a ldr r2, [r3, #0] + 8007198: 3820 subs r0, #32 + 800719a: 6010 str r0, [r2, #0] + 800719c: c0f0 stmia r0!, {r4, r5, r6, r7} + 800719e: 4644 mov r4, r8 + 80071a0: 464d mov r5, r9 + 80071a2: 4656 mov r6, sl + 80071a4: 465f mov r7, fp + 80071a6: c0f0 stmia r0!, {r4, r5, r6, r7} + 80071a8: b508 push {r3, lr} + 80071aa: b672 cpsid i + 80071ac: f7ff f8ae bl 800630c + 80071b0: b662 cpsie i + 80071b2: bc0c pop {r2, r3} + 80071b4: 6811 ldr r1, [r2, #0] + 80071b6: 6808 ldr r0, [r1, #0] + 80071b8: 3010 adds r0, #16 + 80071ba: c8f0 ldmia r0!, {r4, r5, r6, r7} + 80071bc: 46a0 mov r8, r4 + 80071be: 46a9 mov r9, r5 + 80071c0: 46b2 mov sl, r6 + 80071c2: 46bb mov fp, r7 + 80071c4: f380 8809 msr PSP, r0 + 80071c8: 3820 subs r0, #32 + 80071ca: c8f0 ldmia r0!, {r4, r5, r6, r7} + 80071cc: 4718 bx r3 + 80071ce: 46c0 nop ; (mov r8, r8) + +080071d0 : + 80071d0: 200006ec .word 0x200006ec + " bx r3 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB " + ); +} + 80071d4: 46c0 nop ; (mov r8, r8) + 80071d6: 46c0 nop ; (mov r8, r8) + +080071d8 : +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + 80071d8: b580 push {r7, lr} + 80071da: b082 sub sp, #8 + 80071dc: af00 add r7, sp, #0 +uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + 80071de: f7ff ffc9 bl 8007174 + 80071e2: 0003 movs r3, r0 + 80071e4: 607b str r3, [r7, #4] + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + 80071e6: f7fe ffe1 bl 80061ac + 80071ea: 1e03 subs r3, r0, #0 + 80071ec: d003 beq.n 80071f6 + { + /* Pend a context switch. */ + *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; + 80071ee: 4b06 ldr r3, [pc, #24] ; (8007208 ) + 80071f0: 2280 movs r2, #128 ; 0x80 + 80071f2: 0552 lsls r2, r2, #21 + 80071f4: 601a str r2, [r3, #0] + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); + 80071f6: 687b ldr r3, [r7, #4] + 80071f8: 0018 movs r0, r3 + 80071fa: f7ff ffc1 bl 8007180 +} + 80071fe: 46c0 nop ; (mov r8, r8) + 8007200: 46bd mov sp, r7 + 8007202: b002 add sp, #8 + 8007204: bd80 pop {r7, pc} + 8007206: 46c0 nop ; (mov r8, r8) + 8007208: e000ed04 .word 0xe000ed04 + +0800720c : +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + 800720c: b580 push {r7, lr} + 800720e: b088 sub sp, #32 + 8007210: af00 add r7, sp, #0 + 8007212: 6078 str r0, [r7, #4] + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + 8007214: 687a ldr r2, [r7, #4] + 8007216: 4b5a ldr r3, [pc, #360] ; (8007380 ) + 8007218: 681b ldr r3, [r3, #0] + 800721a: 429a cmp r2, r3 + 800721c: d902 bls.n 8007224 + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + 800721e: 4b58 ldr r3, [pc, #352] ; (8007380 ) + 8007220: 681b ldr r3, [r3, #0] + 8007222: 607b str r3, [r7, #4] + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + is accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL &= ~portNVIC_SYSTICK_ENABLE; + 8007224: 4b57 ldr r3, [pc, #348] ; (8007384 ) + 8007226: 681a ldr r2, [r3, #0] + 8007228: 4b56 ldr r3, [pc, #344] ; (8007384 ) + 800722a: 2101 movs r1, #1 + 800722c: 438a bics r2, r1 + 800722e: 601a str r2, [r3, #0] + + /* Calculate the reload value required to wait xExpectedIdleTime + tick periods. -1 is used because this code will execute part way + through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + 8007230: 4b55 ldr r3, [pc, #340] ; (8007388 ) + 8007232: 681a ldr r2, [r3, #0] + 8007234: 687b ldr r3, [r7, #4] + 8007236: 1e59 subs r1, r3, #1 + 8007238: 4b54 ldr r3, [pc, #336] ; (800738c ) + 800723a: 681b ldr r3, [r3, #0] + 800723c: 434b muls r3, r1 + 800723e: 18d3 adds r3, r2, r3 + 8007240: 61fb str r3, [r7, #28] + if( ulReloadValue > ulStoppedTimerCompensation ) + 8007242: 4b53 ldr r3, [pc, #332] ; (8007390 ) + 8007244: 681b ldr r3, [r3, #0] + 8007246: 69fa ldr r2, [r7, #28] + 8007248: 429a cmp r2, r3 + 800724a: d904 bls.n 8007256 + { + ulReloadValue -= ulStoppedTimerCompensation; + 800724c: 4b50 ldr r3, [pc, #320] ; (8007390 ) + 800724e: 681b ldr r3, [r3, #0] + 8007250: 69fa ldr r2, [r7, #28] + 8007252: 1ad3 subs r3, r2, r3 + 8007254: 61fb str r3, [r7, #28] + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + method as that will mask interrupts that should exit sleep mode. */ + __asm volatile( "cpsid i" ); + 8007256: b672 cpsid i + + /* If a context switch is pending or a task is waiting for the scheduler + to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + 8007258: f7ff f9fc bl 8006654 + 800725c: 1e03 subs r3, r0, #0 + 800725e: d110 bne.n 8007282 + { + /* Restart from whatever is left in the count register to complete + this tick period. */ + portNVIC_SYSTICK_LOAD = portNVIC_SYSTICK_CURRENT_VALUE; + 8007260: 4a49 ldr r2, [pc, #292] ; (8007388 ) + 8007262: 4b4c ldr r3, [pc, #304] ; (8007394 ) + 8007264: 6812 ldr r2, [r2, #0] + 8007266: 601a str r2, [r3, #0] + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL |= portNVIC_SYSTICK_ENABLE; + 8007268: 4b46 ldr r3, [pc, #280] ; (8007384 ) + 800726a: 681a ldr r2, [r3, #0] + 800726c: 4b45 ldr r3, [pc, #276] ; (8007384 ) + 800726e: 2101 movs r1, #1 + 8007270: 430a orrs r2, r1 + 8007272: 601a str r2, [r3, #0] + + /* Reset the reload register to the value required for normal tick + periods. */ + portNVIC_SYSTICK_LOAD = ulTimerCountsForOneTick - 1UL; + 8007274: 4b45 ldr r3, [pc, #276] ; (800738c ) + 8007276: 681a ldr r2, [r3, #0] + 8007278: 4b46 ldr r3, [pc, #280] ; (8007394 ) + 800727a: 3a01 subs r2, #1 + 800727c: 601a str r2, [r3, #0] + + /* Re-enable interrupts - see comments above the cpsid instruction() + above. */ + __asm volatile( "cpsie i" ); + 800727e: b662 cpsie i + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD = ulTimerCountsForOneTick - 1UL; + } + portEXIT_CRITICAL(); + } + } + 8007280: e07a b.n 8007378 + portNVIC_SYSTICK_LOAD = ulReloadValue; + 8007282: 4b44 ldr r3, [pc, #272] ; (8007394 ) + 8007284: 69fa ldr r2, [r7, #28] + 8007286: 601a str r2, [r3, #0] + portNVIC_SYSTICK_CURRENT_VALUE = 0UL; + 8007288: 4b3f ldr r3, [pc, #252] ; (8007388 ) + 800728a: 2200 movs r2, #0 + 800728c: 601a str r2, [r3, #0] + portNVIC_SYSTICK_CTRL |= portNVIC_SYSTICK_ENABLE; + 800728e: 4b3d ldr r3, [pc, #244] ; (8007384 ) + 8007290: 681a ldr r2, [r3, #0] + 8007292: 4b3c ldr r3, [pc, #240] ; (8007384 ) + 8007294: 2101 movs r1, #1 + 8007296: 430a orrs r2, r1 + 8007298: 601a str r2, [r3, #0] + xModifiableIdleTime = xExpectedIdleTime; + 800729a: 687b ldr r3, [r7, #4] + 800729c: 60bb str r3, [r7, #8] + configPRE_SLEEP_PROCESSING( &xModifiableIdleTime ); + 800729e: 2308 movs r3, #8 + 80072a0: 18fb adds r3, r7, r3 + 80072a2: 0018 movs r0, r3 + 80072a4: f7f9 f8fa bl 800049c + if( xModifiableIdleTime > 0 ) + 80072a8: 68bb ldr r3, [r7, #8] + 80072aa: 2b00 cmp r3, #0 + 80072ac: d004 beq.n 80072b8 + __asm volatile( "dsb" ); + 80072ae: f3bf 8f4f dsb sy + __asm volatile( "wfi" ); + 80072b2: bf30 wfi + __asm volatile( "isb" ); + 80072b4: f3bf 8f6f isb sy + configPOST_SLEEP_PROCESSING( &xExpectedIdleTime ); + 80072b8: 1d3b adds r3, r7, #4 + 80072ba: 0018 movs r0, r3 + 80072bc: f7f9 f8f6 bl 80004ac + ulSysTickCTRL = portNVIC_SYSTICK_CTRL; + 80072c0: 4b30 ldr r3, [pc, #192] ; (8007384 ) + 80072c2: 681b ldr r3, [r3, #0] + 80072c4: 613b str r3, [r7, #16] + portNVIC_SYSTICK_CTRL = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE ); + 80072c6: 4b2f ldr r3, [pc, #188] ; (8007384 ) + 80072c8: 693a ldr r2, [r7, #16] + 80072ca: 2101 movs r1, #1 + 80072cc: 438a bics r2, r1 + 80072ce: 601a str r2, [r3, #0] + __asm volatile( "cpsie i" ); + 80072d0: b662 cpsie i + if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG ) != 0 ) + 80072d2: 693a ldr r2, [r7, #16] + 80072d4: 2380 movs r3, #128 ; 0x80 + 80072d6: 025b lsls r3, r3, #9 + 80072d8: 4013 ands r3, r2 + 80072da: d01d beq.n 8007318 + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE ); + 80072dc: 4b2b ldr r3, [pc, #172] ; (800738c ) + 80072de: 681a ldr r2, [r3, #0] + 80072e0: 4b29 ldr r3, [pc, #164] ; (8007388 ) + 80072e2: 6819 ldr r1, [r3, #0] + 80072e4: 69fb ldr r3, [r7, #28] + 80072e6: 1acb subs r3, r1, r3 + 80072e8: 18d3 adds r3, r2, r3 + 80072ea: 3b01 subs r3, #1 + 80072ec: 617b str r3, [r7, #20] + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + 80072ee: 4b28 ldr r3, [pc, #160] ; (8007390 ) + 80072f0: 681b ldr r3, [r3, #0] + 80072f2: 697a ldr r2, [r7, #20] + 80072f4: 429a cmp r2, r3 + 80072f6: d304 bcc.n 8007302 + 80072f8: 4b24 ldr r3, [pc, #144] ; (800738c ) + 80072fa: 681b ldr r3, [r3, #0] + 80072fc: 697a ldr r2, [r7, #20] + 80072fe: 429a cmp r2, r3 + 8007300: d903 bls.n 800730a + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + 8007302: 4b22 ldr r3, [pc, #136] ; (800738c ) + 8007304: 681b ldr r3, [r3, #0] + 8007306: 3b01 subs r3, #1 + 8007308: 617b str r3, [r7, #20] + portNVIC_SYSTICK_LOAD = ulCalculatedLoadValue; + 800730a: 4b22 ldr r3, [pc, #136] ; (8007394 ) + 800730c: 697a ldr r2, [r7, #20] + 800730e: 601a str r2, [r3, #0] + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + 8007310: 687b ldr r3, [r7, #4] + 8007312: 3b01 subs r3, #1 + 8007314: 61bb str r3, [r7, #24] + 8007316: e019 b.n 800734c + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE; + 8007318: 687a ldr r2, [r7, #4] + 800731a: 4b1c ldr r3, [pc, #112] ; (800738c ) + 800731c: 681b ldr r3, [r3, #0] + 800731e: 435a muls r2, r3 + 8007320: 4b19 ldr r3, [pc, #100] ; (8007388 ) + 8007322: 681b ldr r3, [r3, #0] + 8007324: 1ad3 subs r3, r2, r3 + 8007326: 60fb str r3, [r7, #12] + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + 8007328: 4b18 ldr r3, [pc, #96] ; (800738c ) + 800732a: 681b ldr r3, [r3, #0] + 800732c: 0019 movs r1, r3 + 800732e: 68f8 ldr r0, [r7, #12] + 8007330: f7f8 feea bl 8000108 <__udivsi3> + 8007334: 0003 movs r3, r0 + 8007336: 61bb str r3, [r7, #24] + portNVIC_SYSTICK_LOAD = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + 8007338: 69bb ldr r3, [r7, #24] + 800733a: 1c5a adds r2, r3, #1 + 800733c: 4b13 ldr r3, [pc, #76] ; (800738c ) + 800733e: 681b ldr r3, [r3, #0] + 8007340: 4353 muls r3, r2 + 8007342: 0019 movs r1, r3 + 8007344: 4b13 ldr r3, [pc, #76] ; (8007394 ) + 8007346: 68fa ldr r2, [r7, #12] + 8007348: 1a8a subs r2, r1, r2 + 800734a: 601a str r2, [r3, #0] + portNVIC_SYSTICK_CURRENT_VALUE = 0UL; + 800734c: 4b0e ldr r3, [pc, #56] ; (8007388 ) + 800734e: 2200 movs r2, #0 + 8007350: 601a str r2, [r3, #0] + portENTER_CRITICAL(); + 8007352: f7ff fee5 bl 8007120 + portNVIC_SYSTICK_CTRL |= portNVIC_SYSTICK_ENABLE; + 8007356: 4b0b ldr r3, [pc, #44] ; (8007384 ) + 8007358: 681a ldr r2, [r3, #0] + 800735a: 4b0a ldr r3, [pc, #40] ; (8007384 ) + 800735c: 2101 movs r1, #1 + 800735e: 430a orrs r2, r1 + 8007360: 601a str r2, [r3, #0] + vTaskStepTick( ulCompleteTickPeriods ); + 8007362: 69bb ldr r3, [r7, #24] + 8007364: 0018 movs r0, r3 + 8007366: f7fe ff05 bl 8006174 + portNVIC_SYSTICK_LOAD = ulTimerCountsForOneTick - 1UL; + 800736a: 4b08 ldr r3, [pc, #32] ; (800738c ) + 800736c: 681a ldr r2, [r3, #0] + 800736e: 4b09 ldr r3, [pc, #36] ; (8007394 ) + 8007370: 3a01 subs r2, #1 + 8007372: 601a str r2, [r3, #0] + portEXIT_CRITICAL(); + 8007374: f7ff fee6 bl 8007144 + } + 8007378: 46c0 nop ; (mov r8, r8) + 800737a: 46bd mov sp, r7 + 800737c: b008 add sp, #32 + 800737e: bd80 pop {r7, pc} + 8007380: 20000d1c .word 0x20000d1c + 8007384: e000e010 .word 0xe000e010 + 8007388: e000e018 .word 0xe000e018 + 800738c: 20000d18 .word 0x20000d18 + 8007390: 20000d20 .word 0x20000d20 + 8007394: e000e014 .word 0xe000e014 + +08007398 : +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + 8007398: b580 push {r7, lr} + 800739a: af00 add r7, sp, #0 + /* Calculate the constants required to configure the tick interrupt. */ + #if configUSE_TICKLESS_IDLE == 1 + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + 800739c: 4b16 ldr r3, [pc, #88] ; (80073f8 ) + 800739e: 681b ldr r3, [r3, #0] + 80073a0: 2164 movs r1, #100 ; 0x64 + 80073a2: 0018 movs r0, r3 + 80073a4: f7f8 feb0 bl 8000108 <__udivsi3> + 80073a8: 0003 movs r3, r0 + 80073aa: 001a movs r2, r3 + 80073ac: 4b13 ldr r3, [pc, #76] ; (80073fc ) + 80073ae: 601a str r2, [r3, #0] + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + 80073b0: 4b12 ldr r3, [pc, #72] ; (80073fc ) + 80073b2: 681b ldr r3, [r3, #0] + 80073b4: 0019 movs r1, r3 + 80073b6: 4812 ldr r0, [pc, #72] ; (8007400 ) + 80073b8: f7f8 fea6 bl 8000108 <__udivsi3> + 80073bc: 0003 movs r3, r0 + 80073be: 001a movs r2, r3 + 80073c0: 4b10 ldr r3, [pc, #64] ; (8007404 ) + 80073c2: 601a str r2, [r3, #0] + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + 80073c4: 4b10 ldr r3, [pc, #64] ; (8007408 ) + 80073c6: 222d movs r2, #45 ; 0x2d + 80073c8: 601a str r2, [r3, #0] + } + #endif /* configUSE_TICKLESS_IDLE */ + +/* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL = 0UL; + 80073ca: 4b10 ldr r3, [pc, #64] ; (800740c ) + 80073cc: 2200 movs r2, #0 + 80073ce: 601a str r2, [r3, #0] + portNVIC_SYSTICK_CURRENT_VALUE = 0UL; + 80073d0: 4b0f ldr r3, [pc, #60] ; (8007410 ) + 80073d2: 2200 movs r2, #0 + 80073d4: 601a str r2, [r3, #0] + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + 80073d6: 4b08 ldr r3, [pc, #32] ; (80073f8 ) + 80073d8: 681b ldr r3, [r3, #0] + 80073da: 2164 movs r1, #100 ; 0x64 + 80073dc: 0018 movs r0, r3 + 80073de: f7f8 fe93 bl 8000108 <__udivsi3> + 80073e2: 0003 movs r3, r0 + 80073e4: 001a movs r2, r3 + 80073e6: 4b0b ldr r3, [pc, #44] ; (8007414 ) + 80073e8: 3a01 subs r2, #1 + 80073ea: 601a str r2, [r3, #0] + portNVIC_SYSTICK_CTRL = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; + 80073ec: 4b07 ldr r3, [pc, #28] ; (800740c ) + 80073ee: 2207 movs r2, #7 + 80073f0: 601a str r2, [r3, #0] +} + 80073f2: 46c0 nop ; (mov r8, r8) + 80073f4: 46bd mov sp, r7 + 80073f6: bd80 pop {r7, pc} + 80073f8: 20000000 .word 0x20000000 + 80073fc: 20000d18 .word 0x20000d18 + 8007400: 00ffffff .word 0x00ffffff + 8007404: 20000d1c .word 0x20000d1c + 8007408: 20000d20 .word 0x20000d20 + 800740c: e000e010 .word 0xe000e010 + 8007410: e000e018 .word 0xe000e018 + 8007414: e000e014 .word 0xe000e014 + +08007418 : +static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ + 8007418: b580 push {r7, lr} + 800741a: b086 sub sp, #24 + 800741c: af00 add r7, sp, #0 + 800741e: 6078 str r0, [r7, #4] +BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +void *pvReturn = NULL; + 8007420: 2300 movs r3, #0 + 8007422: 60fb str r3, [r7, #12] + + vTaskSuspendAll(); + 8007424: f7fe fdca bl 8005fbc + { + /* If this is the first call to malloc then the heap will require + initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + 8007428: 4b49 ldr r3, [pc, #292] ; (8007550 ) + 800742a: 681b ldr r3, [r3, #0] + 800742c: 2b00 cmp r3, #0 + 800742e: d101 bne.n 8007434 + { + prvHeapInit(); + 8007430: f000 f8e0 bl 80075f4 + + /* Check the requested block size is not so large that the top bit is + set. The top bit of the block size member of the BlockLink_t structure + is used to determine who owns the block - the application or the + kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + 8007434: 4b47 ldr r3, [pc, #284] ; (8007554 ) + 8007436: 681b ldr r3, [r3, #0] + 8007438: 687a ldr r2, [r7, #4] + 800743a: 4013 ands r3, r2 + 800743c: d000 beq.n 8007440 + 800743e: e079 b.n 8007534 + { + /* The wanted size is increased so it can contain a BlockLink_t + structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + 8007440: 687b ldr r3, [r7, #4] + 8007442: 2b00 cmp r3, #0 + 8007444: d012 beq.n 800746c + { + xWantedSize += xHeapStructSize; + 8007446: 2208 movs r2, #8 + 8007448: 687b ldr r3, [r7, #4] + 800744a: 189b adds r3, r3, r2 + 800744c: 607b str r3, [r7, #4] + + /* Ensure that blocks are always aligned to the required number + of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + 800744e: 687b ldr r3, [r7, #4] + 8007450: 2207 movs r2, #7 + 8007452: 4013 ands r3, r2 + 8007454: d00a beq.n 800746c + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + 8007456: 687b ldr r3, [r7, #4] + 8007458: 2207 movs r2, #7 + 800745a: 4393 bics r3, r2 + 800745c: 3308 adds r3, #8 + 800745e: 607b str r3, [r7, #4] + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + 8007460: 687b ldr r3, [r7, #4] + 8007462: 2207 movs r2, #7 + 8007464: 4013 ands r3, r2 + 8007466: d001 beq.n 800746c + 8007468: b672 cpsid i + 800746a: e7fe b.n 800746a + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + 800746c: 687b ldr r3, [r7, #4] + 800746e: 2b00 cmp r3, #0 + 8007470: d060 beq.n 8007534 + 8007472: 4b39 ldr r3, [pc, #228] ; (8007558 ) + 8007474: 681b ldr r3, [r3, #0] + 8007476: 687a ldr r2, [r7, #4] + 8007478: 429a cmp r2, r3 + 800747a: d85b bhi.n 8007534 + { + /* Traverse the list from the start (lowest address) block until + one of adequate size is found. */ + pxPreviousBlock = &xStart; + 800747c: 4b37 ldr r3, [pc, #220] ; (800755c ) + 800747e: 613b str r3, [r7, #16] + pxBlock = xStart.pxNextFreeBlock; + 8007480: 4b36 ldr r3, [pc, #216] ; (800755c ) + 8007482: 681b ldr r3, [r3, #0] + 8007484: 617b str r3, [r7, #20] + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 8007486: e004 b.n 8007492 + { + pxPreviousBlock = pxBlock; + 8007488: 697b ldr r3, [r7, #20] + 800748a: 613b str r3, [r7, #16] + pxBlock = pxBlock->pxNextFreeBlock; + 800748c: 697b ldr r3, [r7, #20] + 800748e: 681b ldr r3, [r3, #0] + 8007490: 617b str r3, [r7, #20] + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 8007492: 697b ldr r3, [r7, #20] + 8007494: 685b ldr r3, [r3, #4] + 8007496: 687a ldr r2, [r7, #4] + 8007498: 429a cmp r2, r3 + 800749a: d903 bls.n 80074a4 + 800749c: 697b ldr r3, [r7, #20] + 800749e: 681b ldr r3, [r3, #0] + 80074a0: 2b00 cmp r3, #0 + 80074a2: d1f1 bne.n 8007488 + } + + /* If the end marker was reached then a block of adequate size + was not found. */ + if( pxBlock != pxEnd ) + 80074a4: 4b2a ldr r3, [pc, #168] ; (8007550 ) + 80074a6: 681b ldr r3, [r3, #0] + 80074a8: 697a ldr r2, [r7, #20] + 80074aa: 429a cmp r2, r3 + 80074ac: d042 beq.n 8007534 + { + /* Return the memory space pointed to - jumping over the + BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + 80074ae: 693b ldr r3, [r7, #16] + 80074b0: 681b ldr r3, [r3, #0] + 80074b2: 2208 movs r2, #8 + 80074b4: 189b adds r3, r3, r2 + 80074b6: 60fb str r3, [r7, #12] + + /* This block is being returned for use so must be taken out + of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + 80074b8: 697b ldr r3, [r7, #20] + 80074ba: 681a ldr r2, [r3, #0] + 80074bc: 693b ldr r3, [r7, #16] + 80074be: 601a str r2, [r3, #0] + + /* If the block is larger than required it can be split into + two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + 80074c0: 697b ldr r3, [r7, #20] + 80074c2: 685a ldr r2, [r3, #4] + 80074c4: 687b ldr r3, [r7, #4] + 80074c6: 1ad2 subs r2, r2, r3 + 80074c8: 2308 movs r3, #8 + 80074ca: 005b lsls r3, r3, #1 + 80074cc: 429a cmp r2, r3 + 80074ce: d916 bls.n 80074fe + { + /* This block is to be split into two. Create a new + block following the number of bytes requested. The void + cast is used to prevent byte alignment warnings from the + compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + 80074d0: 697a ldr r2, [r7, #20] + 80074d2: 687b ldr r3, [r7, #4] + 80074d4: 18d3 adds r3, r2, r3 + 80074d6: 60bb str r3, [r7, #8] + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + 80074d8: 68bb ldr r3, [r7, #8] + 80074da: 2207 movs r2, #7 + 80074dc: 4013 ands r3, r2 + 80074de: d001 beq.n 80074e4 + 80074e0: b672 cpsid i + 80074e2: e7fe b.n 80074e2 + + /* Calculate the sizes of two blocks split from the + single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + 80074e4: 697b ldr r3, [r7, #20] + 80074e6: 685a ldr r2, [r3, #4] + 80074e8: 687b ldr r3, [r7, #4] + 80074ea: 1ad2 subs r2, r2, r3 + 80074ec: 68bb ldr r3, [r7, #8] + 80074ee: 605a str r2, [r3, #4] + pxBlock->xBlockSize = xWantedSize; + 80074f0: 697b ldr r3, [r7, #20] + 80074f2: 687a ldr r2, [r7, #4] + 80074f4: 605a str r2, [r3, #4] + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + 80074f6: 68bb ldr r3, [r7, #8] + 80074f8: 0018 movs r0, r3 + 80074fa: f000 f8db bl 80076b4 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + 80074fe: 4b16 ldr r3, [pc, #88] ; (8007558 ) + 8007500: 681a ldr r2, [r3, #0] + 8007502: 697b ldr r3, [r7, #20] + 8007504: 685b ldr r3, [r3, #4] + 8007506: 1ad2 subs r2, r2, r3 + 8007508: 4b13 ldr r3, [pc, #76] ; (8007558 ) + 800750a: 601a str r2, [r3, #0] + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + 800750c: 4b12 ldr r3, [pc, #72] ; (8007558 ) + 800750e: 681a ldr r2, [r3, #0] + 8007510: 4b13 ldr r3, [pc, #76] ; (8007560 ) + 8007512: 681b ldr r3, [r3, #0] + 8007514: 429a cmp r2, r3 + 8007516: d203 bcs.n 8007520 + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + 8007518: 4b0f ldr r3, [pc, #60] ; (8007558 ) + 800751a: 681a ldr r2, [r3, #0] + 800751c: 4b10 ldr r3, [pc, #64] ; (8007560 ) + 800751e: 601a str r2, [r3, #0] + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + 8007520: 697b ldr r3, [r7, #20] + 8007522: 685a ldr r2, [r3, #4] + 8007524: 4b0b ldr r3, [pc, #44] ; (8007554 ) + 8007526: 681b ldr r3, [r3, #0] + 8007528: 431a orrs r2, r3 + 800752a: 697b ldr r3, [r7, #20] + 800752c: 605a str r2, [r3, #4] + pxBlock->pxNextFreeBlock = NULL; + 800752e: 697b ldr r3, [r7, #20] + 8007530: 2200 movs r2, #0 + 8007532: 601a str r2, [r3, #0] + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + 8007534: f7fe fd84 bl 8006040 + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + 8007538: 68fb ldr r3, [r7, #12] + 800753a: 2207 movs r2, #7 + 800753c: 4013 ands r3, r2 + 800753e: d001 beq.n 8007544 + 8007540: b672 cpsid i + 8007542: e7fe b.n 8007542 + return pvReturn; + 8007544: 68fb ldr r3, [r7, #12] +} + 8007546: 0018 movs r0, r3 + 8007548: 46bd mov sp, r7 + 800754a: b006 add sp, #24 + 800754c: bd80 pop {r7, pc} + 800754e: 46c0 nop ; (mov r8, r8) + 8007550: 2000152c .word 0x2000152c + 8007554: 20001538 .word 0x20001538 + 8007558: 20001530 .word 0x20001530 + 800755c: 20001524 .word 0x20001524 + 8007560: 20001534 .word 0x20001534 + +08007564 : +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + 8007564: b580 push {r7, lr} + 8007566: b084 sub sp, #16 + 8007568: af00 add r7, sp, #0 + 800756a: 6078 str r0, [r7, #4] +uint8_t *puc = ( uint8_t * ) pv; + 800756c: 687b ldr r3, [r7, #4] + 800756e: 60fb str r3, [r7, #12] +BlockLink_t *pxLink; + + if( pv != NULL ) + 8007570: 687b ldr r3, [r7, #4] + 8007572: 2b00 cmp r3, #0 + 8007574: d035 beq.n 80075e2 + { + /* The memory being freed will have an BlockLink_t structure immediately + before it. */ + puc -= xHeapStructSize; + 8007576: 2308 movs r3, #8 + 8007578: 425b negs r3, r3 + 800757a: 68fa ldr r2, [r7, #12] + 800757c: 18d3 adds r3, r2, r3 + 800757e: 60fb str r3, [r7, #12] + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + 8007580: 68fb ldr r3, [r7, #12] + 8007582: 60bb str r3, [r7, #8] + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + 8007584: 68bb ldr r3, [r7, #8] + 8007586: 685a ldr r2, [r3, #4] + 8007588: 4b18 ldr r3, [pc, #96] ; (80075ec ) + 800758a: 681b ldr r3, [r3, #0] + 800758c: 4013 ands r3, r2 + 800758e: d101 bne.n 8007594 + 8007590: b672 cpsid i + 8007592: e7fe b.n 8007592 + configASSERT( pxLink->pxNextFreeBlock == NULL ); + 8007594: 68bb ldr r3, [r7, #8] + 8007596: 681b ldr r3, [r3, #0] + 8007598: 2b00 cmp r3, #0 + 800759a: d001 beq.n 80075a0 + 800759c: b672 cpsid i + 800759e: e7fe b.n 800759e + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + 80075a0: 68bb ldr r3, [r7, #8] + 80075a2: 685a ldr r2, [r3, #4] + 80075a4: 4b11 ldr r3, [pc, #68] ; (80075ec ) + 80075a6: 681b ldr r3, [r3, #0] + 80075a8: 4013 ands r3, r2 + 80075aa: d01a beq.n 80075e2 + { + if( pxLink->pxNextFreeBlock == NULL ) + 80075ac: 68bb ldr r3, [r7, #8] + 80075ae: 681b ldr r3, [r3, #0] + 80075b0: 2b00 cmp r3, #0 + 80075b2: d116 bne.n 80075e2 + { + /* The block is being returned to the heap - it is no longer + allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + 80075b4: 68bb ldr r3, [r7, #8] + 80075b6: 685a ldr r2, [r3, #4] + 80075b8: 4b0c ldr r3, [pc, #48] ; (80075ec ) + 80075ba: 681b ldr r3, [r3, #0] + 80075bc: 43db mvns r3, r3 + 80075be: 401a ands r2, r3 + 80075c0: 68bb ldr r3, [r7, #8] + 80075c2: 605a str r2, [r3, #4] + + vTaskSuspendAll(); + 80075c4: f7fe fcfa bl 8005fbc + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + 80075c8: 68bb ldr r3, [r7, #8] + 80075ca: 685a ldr r2, [r3, #4] + 80075cc: 4b08 ldr r3, [pc, #32] ; (80075f0 ) + 80075ce: 681b ldr r3, [r3, #0] + 80075d0: 18d2 adds r2, r2, r3 + 80075d2: 4b07 ldr r3, [pc, #28] ; (80075f0 ) + 80075d4: 601a str r2, [r3, #0] + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + 80075d6: 68bb ldr r3, [r7, #8] + 80075d8: 0018 movs r0, r3 + 80075da: f000 f86b bl 80076b4 + } + ( void ) xTaskResumeAll(); + 80075de: f7fe fd2f bl 8006040 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} + 80075e2: 46c0 nop ; (mov r8, r8) + 80075e4: 46bd mov sp, r7 + 80075e6: b004 add sp, #16 + 80075e8: bd80 pop {r7, pc} + 80075ea: 46c0 nop ; (mov r8, r8) + 80075ec: 20001538 .word 0x20001538 + 80075f0: 20001530 .word 0x20001530 + +080075f4 : + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + 80075f4: b580 push {r7, lr} + 80075f6: b084 sub sp, #16 + 80075f8: af00 add r7, sp, #0 +BlockLink_t *pxFirstFreeBlock; +uint8_t *pucAlignedHeap; +size_t uxAddress; +size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + 80075fa: 2380 movs r3, #128 ; 0x80 + 80075fc: 011b lsls r3, r3, #4 + 80075fe: 60bb str r3, [r7, #8] + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + 8007600: 4b26 ldr r3, [pc, #152] ; (800769c ) + 8007602: 60fb str r3, [r7, #12] + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + 8007604: 68fb ldr r3, [r7, #12] + 8007606: 2207 movs r2, #7 + 8007608: 4013 ands r3, r2 + 800760a: d00c beq.n 8007626 + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + 800760c: 68fb ldr r3, [r7, #12] + 800760e: 3307 adds r3, #7 + 8007610: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 8007612: 68fb ldr r3, [r7, #12] + 8007614: 2207 movs r2, #7 + 8007616: 4393 bics r3, r2 + 8007618: 60fb str r3, [r7, #12] + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + 800761a: 68ba ldr r2, [r7, #8] + 800761c: 68fb ldr r3, [r7, #12] + 800761e: 1ad2 subs r2, r2, r3 + 8007620: 4b1e ldr r3, [pc, #120] ; (800769c ) + 8007622: 18d3 adds r3, r2, r3 + 8007624: 60bb str r3, [r7, #8] + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + 8007626: 68fb ldr r3, [r7, #12] + 8007628: 607b str r3, [r7, #4] + + /* xStart is used to hold a pointer to the first item in the list of free + blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + 800762a: 4b1d ldr r3, [pc, #116] ; (80076a0 ) + 800762c: 687a ldr r2, [r7, #4] + 800762e: 601a str r2, [r3, #0] + xStart.xBlockSize = ( size_t ) 0; + 8007630: 4b1b ldr r3, [pc, #108] ; (80076a0 ) + 8007632: 2200 movs r2, #0 + 8007634: 605a str r2, [r3, #4] + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + 8007636: 687b ldr r3, [r7, #4] + 8007638: 68ba ldr r2, [r7, #8] + 800763a: 18d3 adds r3, r2, r3 + 800763c: 60fb str r3, [r7, #12] + uxAddress -= xHeapStructSize; + 800763e: 2208 movs r2, #8 + 8007640: 68fb ldr r3, [r7, #12] + 8007642: 1a9b subs r3, r3, r2 + 8007644: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 8007646: 68fb ldr r3, [r7, #12] + 8007648: 2207 movs r2, #7 + 800764a: 4393 bics r3, r2 + 800764c: 60fb str r3, [r7, #12] + pxEnd = ( void * ) uxAddress; + 800764e: 68fa ldr r2, [r7, #12] + 8007650: 4b14 ldr r3, [pc, #80] ; (80076a4 ) + 8007652: 601a str r2, [r3, #0] + pxEnd->xBlockSize = 0; + 8007654: 4b13 ldr r3, [pc, #76] ; (80076a4 ) + 8007656: 681b ldr r3, [r3, #0] + 8007658: 2200 movs r2, #0 + 800765a: 605a str r2, [r3, #4] + pxEnd->pxNextFreeBlock = NULL; + 800765c: 4b11 ldr r3, [pc, #68] ; (80076a4 ) + 800765e: 681b ldr r3, [r3, #0] + 8007660: 2200 movs r2, #0 + 8007662: 601a str r2, [r3, #0] + + /* To start with there is a single free block that is sized to take up the + entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + 8007664: 687b ldr r3, [r7, #4] + 8007666: 603b str r3, [r7, #0] + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + 8007668: 683b ldr r3, [r7, #0] + 800766a: 68fa ldr r2, [r7, #12] + 800766c: 1ad2 subs r2, r2, r3 + 800766e: 683b ldr r3, [r7, #0] + 8007670: 605a str r2, [r3, #4] + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + 8007672: 4b0c ldr r3, [pc, #48] ; (80076a4 ) + 8007674: 681a ldr r2, [r3, #0] + 8007676: 683b ldr r3, [r7, #0] + 8007678: 601a str r2, [r3, #0] + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 800767a: 683b ldr r3, [r7, #0] + 800767c: 685a ldr r2, [r3, #4] + 800767e: 4b0a ldr r3, [pc, #40] ; (80076a8 ) + 8007680: 601a str r2, [r3, #0] + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 8007682: 683b ldr r3, [r7, #0] + 8007684: 685a ldr r2, [r3, #4] + 8007686: 4b09 ldr r3, [pc, #36] ; (80076ac ) + 8007688: 601a str r2, [r3, #0] + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); + 800768a: 4b09 ldr r3, [pc, #36] ; (80076b0 ) + 800768c: 2280 movs r2, #128 ; 0x80 + 800768e: 0612 lsls r2, r2, #24 + 8007690: 601a str r2, [r3, #0] +} + 8007692: 46c0 nop ; (mov r8, r8) + 8007694: 46bd mov sp, r7 + 8007696: b004 add sp, #16 + 8007698: bd80 pop {r7, pc} + 800769a: 46c0 nop ; (mov r8, r8) + 800769c: 20000d24 .word 0x20000d24 + 80076a0: 20001524 .word 0x20001524 + 80076a4: 2000152c .word 0x2000152c + 80076a8: 20001534 .word 0x20001534 + 80076ac: 20001530 .word 0x20001530 + 80076b0: 20001538 .word 0x20001538 + +080076b4 : +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) +{ + 80076b4: b580 push {r7, lr} + 80076b6: b084 sub sp, #16 + 80076b8: af00 add r7, sp, #0 + 80076ba: 6078 str r0, [r7, #4] +BlockLink_t *pxIterator; +uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + 80076bc: 4b27 ldr r3, [pc, #156] ; (800775c ) + 80076be: 60fb str r3, [r7, #12] + 80076c0: e002 b.n 80076c8 + 80076c2: 68fb ldr r3, [r7, #12] + 80076c4: 681b ldr r3, [r3, #0] + 80076c6: 60fb str r3, [r7, #12] + 80076c8: 68fb ldr r3, [r7, #12] + 80076ca: 681b ldr r3, [r3, #0] + 80076cc: 687a ldr r2, [r7, #4] + 80076ce: 429a cmp r2, r3 + 80076d0: d8f7 bhi.n 80076c2 + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + 80076d2: 68fb ldr r3, [r7, #12] + 80076d4: 60bb str r3, [r7, #8] + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + 80076d6: 68fb ldr r3, [r7, #12] + 80076d8: 685b ldr r3, [r3, #4] + 80076da: 68ba ldr r2, [r7, #8] + 80076dc: 18d3 adds r3, r2, r3 + 80076de: 687a ldr r2, [r7, #4] + 80076e0: 429a cmp r2, r3 + 80076e2: d108 bne.n 80076f6 + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + 80076e4: 68fb ldr r3, [r7, #12] + 80076e6: 685a ldr r2, [r3, #4] + 80076e8: 687b ldr r3, [r7, #4] + 80076ea: 685b ldr r3, [r3, #4] + 80076ec: 18d2 adds r2, r2, r3 + 80076ee: 68fb ldr r3, [r7, #12] + 80076f0: 605a str r2, [r3, #4] + pxBlockToInsert = pxIterator; + 80076f2: 68fb ldr r3, [r7, #12] + 80076f4: 607b str r3, [r7, #4] + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + 80076f6: 687b ldr r3, [r7, #4] + 80076f8: 60bb str r3, [r7, #8] + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + 80076fa: 687b ldr r3, [r7, #4] + 80076fc: 685b ldr r3, [r3, #4] + 80076fe: 68ba ldr r2, [r7, #8] + 8007700: 18d2 adds r2, r2, r3 + 8007702: 68fb ldr r3, [r7, #12] + 8007704: 681b ldr r3, [r3, #0] + 8007706: 429a cmp r2, r3 + 8007708: d118 bne.n 800773c + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + 800770a: 68fb ldr r3, [r7, #12] + 800770c: 681a ldr r2, [r3, #0] + 800770e: 4b14 ldr r3, [pc, #80] ; (8007760 ) + 8007710: 681b ldr r3, [r3, #0] + 8007712: 429a cmp r2, r3 + 8007714: d00d beq.n 8007732 + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + 8007716: 687b ldr r3, [r7, #4] + 8007718: 685a ldr r2, [r3, #4] + 800771a: 68fb ldr r3, [r7, #12] + 800771c: 681b ldr r3, [r3, #0] + 800771e: 685b ldr r3, [r3, #4] + 8007720: 18d2 adds r2, r2, r3 + 8007722: 687b ldr r3, [r7, #4] + 8007724: 605a str r2, [r3, #4] + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + 8007726: 68fb ldr r3, [r7, #12] + 8007728: 681b ldr r3, [r3, #0] + 800772a: 681a ldr r2, [r3, #0] + 800772c: 687b ldr r3, [r7, #4] + 800772e: 601a str r2, [r3, #0] + 8007730: e008 b.n 8007744 + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + 8007732: 4b0b ldr r3, [pc, #44] ; (8007760 ) + 8007734: 681a ldr r2, [r3, #0] + 8007736: 687b ldr r3, [r7, #4] + 8007738: 601a str r2, [r3, #0] + 800773a: e003 b.n 8007744 + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + 800773c: 68fb ldr r3, [r7, #12] + 800773e: 681a ldr r2, [r3, #0] + 8007740: 687b ldr r3, [r7, #4] + 8007742: 601a str r2, [r3, #0] + + /* If the block being inserted plugged a gab, so was merged with the block + before and the block after, then it's pxNextFreeBlock pointer will have + already been set, and should not be set here as that would make it point + to itself. */ + if( pxIterator != pxBlockToInsert ) + 8007744: 68fa ldr r2, [r7, #12] + 8007746: 687b ldr r3, [r7, #4] + 8007748: 429a cmp r2, r3 + 800774a: d002 beq.n 8007752 + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + 800774c: 68fb ldr r3, [r7, #12] + 800774e: 687a ldr r2, [r7, #4] + 8007750: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 8007752: 46c0 nop ; (mov r8, r8) + 8007754: 46bd mov sp, r7 + 8007756: b004 add sp, #16 + 8007758: bd80 pop {r7, pc} + 800775a: 46c0 nop ; (mov r8, r8) + 800775c: 20001524 .word 0x20001524 + 8007760: 2000152c .word 0x2000152c + +08007764 <__libc_init_array>: + 8007764: b570 push {r4, r5, r6, lr} + 8007766: 2600 movs r6, #0 + 8007768: 4d0c ldr r5, [pc, #48] ; (800779c <__libc_init_array+0x38>) + 800776a: 4c0d ldr r4, [pc, #52] ; (80077a0 <__libc_init_array+0x3c>) + 800776c: 1b64 subs r4, r4, r5 + 800776e: 10a4 asrs r4, r4, #2 + 8007770: 42a6 cmp r6, r4 + 8007772: d109 bne.n 8007788 <__libc_init_array+0x24> + 8007774: 2600 movs r6, #0 + 8007776: f000 f82b bl 80077d0 <_init> + 800777a: 4d0a ldr r5, [pc, #40] ; (80077a4 <__libc_init_array+0x40>) + 800777c: 4c0a ldr r4, [pc, #40] ; (80077a8 <__libc_init_array+0x44>) + 800777e: 1b64 subs r4, r4, r5 + 8007780: 10a4 asrs r4, r4, #2 + 8007782: 42a6 cmp r6, r4 + 8007784: d105 bne.n 8007792 <__libc_init_array+0x2e> + 8007786: bd70 pop {r4, r5, r6, pc} + 8007788: 00b3 lsls r3, r6, #2 + 800778a: 58eb ldr r3, [r5, r3] + 800778c: 4798 blx r3 + 800778e: 3601 adds r6, #1 + 8007790: e7ee b.n 8007770 <__libc_init_array+0xc> + 8007792: 00b3 lsls r3, r6, #2 + 8007794: 58eb ldr r3, [r5, r3] + 8007796: 4798 blx r3 + 8007798: 3601 adds r6, #1 + 800779a: e7f2 b.n 8007782 <__libc_init_array+0x1e> + 800779c: 08007920 .word 0x08007920 + 80077a0: 08007920 .word 0x08007920 + 80077a4: 08007920 .word 0x08007920 + 80077a8: 08007924 .word 0x08007924 + +080077ac : + 80077ac: 2300 movs r3, #0 + 80077ae: b510 push {r4, lr} + 80077b0: 429a cmp r2, r3 + 80077b2: d100 bne.n 80077b6 + 80077b4: bd10 pop {r4, pc} + 80077b6: 5ccc ldrb r4, [r1, r3] + 80077b8: 54c4 strb r4, [r0, r3] + 80077ba: 3301 adds r3, #1 + 80077bc: e7f8 b.n 80077b0 + +080077be : + 80077be: 0003 movs r3, r0 + 80077c0: 1882 adds r2, r0, r2 + 80077c2: 4293 cmp r3, r2 + 80077c4: d100 bne.n 80077c8 + 80077c6: 4770 bx lr + 80077c8: 7019 strb r1, [r3, #0] + 80077ca: 3301 adds r3, #1 + 80077cc: e7f9 b.n 80077c2 + ... + +080077d0 <_init>: + 80077d0: b5f8 push {r3, r4, r5, r6, r7, lr} + 80077d2: 46c0 nop ; (mov r8, r8) + 80077d4: bcf8 pop {r3, r4, r5, r6, r7} + 80077d6: bc08 pop {r3} + 80077d8: 469e mov lr, r3 + 80077da: 4770 bx lr + +080077dc <_fini>: + 80077dc: b5f8 push {r3, r4, r5, r6, r7, lr} + 80077de: 46c0 nop ; (mov r8, r8) + 80077e0: bcf8 pop {r3, r4, r5, r6, r7} + 80077e2: bc08 pop {r3} + 80077e4: 469e mov lr, r3 + 80077e6: 4770 bx lr diff --git a/software/dumber3/Debug/Dumber3.map b/software/dumber3/Debug/Dumber3.map new file mode 100644 index 0000000..20dbc87 --- /dev/null +++ b/software/dumber3/Debug/Dumber3.map @@ -0,0 +1,6594 @@ +Archive member included to satisfy reference by file (symbol) + +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + ./Core/Src/syscalls.o (__errno) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (exit) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) (_global_impure_ptr) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (__libc_init_array) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o (memcpy) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (memset) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-strlen.o) + ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o (strlen) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + ./Core/Src/main.o (__aeabi_uidiv) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o (__aeabi_uldivmod) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o (__aeabi_lmul) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) (__clzdi2) +/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) (__clzsi2) + +Allocating common symbols +Common symbol size file + +defaultTaskHandle 0x4 ./Core/Src/main.o +MOTEUR_NBImpulsionsD + 0x2 ./Core/Src/moteurs.o +XBEE_Mailbox 0x4 ./Core/Src/messages.o +MOTEUR_DerniereValEncodeursD + 0x2 ./Core/Src/moteurs.o +uwTick 0x4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o +xQueueRegistry 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o +pFlash 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o +hlpuart1 0x84 ./Core/Src/main.o +MOTEUR_DerniereValEncodeursG + 0x2 ./Core/Src/moteurs.o +MOTEUR_CmdMoteurD 0x2 ./Core/Src/moteurs.o +MOTEUR_ConsigneMoteurG + 0x2 ./Core/Src/moteurs.o +MOTEURS_Mailbox 0x4 ./Core/Src/messages.o +LEDS_Animation 0x1 ./Core/Src/leds.o +hlptim1 0x30 ./Core/Src/main.o +MOTEUR_NBImpulsionsG + 0x2 ./Core/Src/moteurs.o +BATTERIE_Mailbox 0x4 ./Core/Src/messages.o +MOTEUR_ConsigneMoteurD + 0x2 ./Core/Src/moteurs.o +hdma_lpuart1_tx 0x48 ./Core/Src/main.o +hdma_lpuart1_rx 0x48 ./Core/Src/main.o +xStackLeds 0x190 ./Core/Src/leds.o +htim2 0x40 ./Core/Src/main.o +MOTEUR_CmdMoteurG 0x2 ./Core/Src/moteurs.o +SEQUENCEUR_Mailbox 0x4 ./Core/Src/messages.o +LEDS_Mailbox 0x4 ./Core/Src/messages.o +hadc 0x5c ./Core/Src/main.o +LEDS_AnimationAncien + 0x1 ./Core/Src/leds.o +xTaskLeds 0x5c ./Core/Src/leds.o +htim21 0x40 ./Core/Src/main.o + +Discarded input sections + + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .data 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x0000000000000000 0x80 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.extab 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.exidx 0x0000000000000000 0x10 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.attributes + 0x0000000000000000 0x1b /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .group 0x0000000000000000 0xc ./Core/Src/batterie.o + .text 0x0000000000000000 0x0 ./Core/Src/batterie.o + .data 0x0000000000000000 0x0 ./Core/Src/batterie.o + .bss 0x0000000000000000 0x0 ./Core/Src/batterie.o + .debug_info 0x0000000000000000 0x21 ./Core/Src/batterie.o + .debug_abbrev 0x0000000000000000 0x13 ./Core/Src/batterie.o + .debug_aranges + 0x0000000000000000 0x18 ./Core/Src/batterie.o + .debug_macro 0x0000000000000000 0x11 ./Core/Src/batterie.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/batterie.o + .debug_line 0x0000000000000000 0x37 ./Core/Src/batterie.o + .debug_str 0x0000000000000000 0x2cc9 ./Core/Src/batterie.o + .comment 0x0000000000000000 0x54 ./Core/Src/batterie.o + .ARM.attributes + 0x0000000000000000 0x32 ./Core/Src/batterie.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .text 0x0000000000000000 0x0 ./Core/Src/freertos.o + .data 0x0000000000000000 0x0 ./Core/Src/freertos.o + .bss 0x0000000000000000 0x0 ./Core/Src/freertos.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/leds.o + .text 0x0000000000000000 0x0 ./Core/Src/leds.o + .data 0x0000000000000000 0x0 ./Core/Src/leds.o + .bss 0x0000000000000000 0x0 ./Core/Src/leds.o + .text.LEDS_RegleAnimation + 0x0000000000000000 0x20 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x131 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x3ad ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x7a29 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x3555 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x8a0 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x42e ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x18a ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x13f ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xff ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x82 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x24f ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x4da ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x6b ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x129 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x1c6 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x25c ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xb6 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x773 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x6c ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x5ba ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x100 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x140 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x15a ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xb2 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x26 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x48d ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xaa ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x74 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xdd ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x87 ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0x4c ./Core/Src/leds.o + .debug_macro 0x0000000000000000 0xee ./Core/Src/leds.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .text 0x0000000000000000 0x0 ./Core/Src/main.o + .data 0x0000000000000000 0x0 ./Core/Src/main.o + .bss 0x0000000000000000 0x0 ./Core/Src/main.o + .text.msToTicks + 0x0000000000000000 0x44 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x131 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x3ad ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x7a29 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x3555 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x8a0 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x42e ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x18a ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x13f ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xff ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x82 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x24f ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x4da ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x6b ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x129 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x1c6 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x25c ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xb6 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x773 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x6c ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x5ba ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x100 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x140 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x15a ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xb2 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x26 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x48d ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xaa ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x74 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xdd ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x87 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x4c ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xee ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/messages.o + .text 0x0000000000000000 0x0 ./Core/Src/messages.o + .data 0x0000000000000000 0x0 ./Core/Src/messages.o + .bss 0x0000000000000000 0x0 ./Core/Src/messages.o + .text.MESSAGE_ReadMailbox + 0x0000000000000000 0x66 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x131 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x3ad ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x7a29 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x3555 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x8a0 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x42e ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x18a ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x13f ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xff ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x82 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x24f ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x4da ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x6b ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x129 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x1c6 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x25c ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xb6 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x773 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x6c ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x5ba ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x100 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x140 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x15a ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xb2 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x26 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x48d ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xaa ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x74 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xdd ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0xee ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x87 ./Core/Src/messages.o + .debug_macro 0x0000000000000000 0x4c ./Core/Src/messages.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/moteurs.o + .text 0x0000000000000000 0x0 ./Core/Src/moteurs.o + .data 0x0000000000000000 0x0 ./Core/Src/moteurs.o + .bss 0x0000000000000000 0x0 ./Core/Src/moteurs.o + .text.MOTEURS_DesactiveAlim + 0x0000000000000000 0x2c ./Core/Src/moteurs.o + .text.MOTEURS_ActiveAlim + 0x0000000000000000 0x2c ./Core/Src/moteurs.o + .text.MOTEURS_EtatAlim + 0x0000000000000000 0x20 ./Core/Src/moteurs.o + .text.MOTEUR_LireEncodeursGauche + 0x0000000000000000 0x78 ./Core/Src/moteurs.o + .text.MOTEUR_LireEncodeursDroit + 0x0000000000000000 0x78 ./Core/Src/moteurs.o + .text.MOTEURS_Init + 0x0000000000000000 0xdc ./Core/Src/moteurs.o + .text.MOTEURS_Set + 0x0000000000000000 0xe8 ./Core/Src/moteurs.o + .text.MOTEURS_Test + 0x0000000000000000 0x1b8 ./Core/Src/moteurs.o + .debug_info 0x0000000000000000 0xc93 ./Core/Src/moteurs.o + .debug_abbrev 0x0000000000000000 0x201 ./Core/Src/moteurs.o + .debug_aranges + 0x0000000000000000 0x58 ./Core/Src/moteurs.o + .debug_ranges 0x0000000000000000 0x48 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x2f9 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x131 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x3ad ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x7a29 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x3555 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x8a0 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x42e ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x18a ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x13f ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xff ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x82 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x24f ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x4da ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x6b ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x129 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x1c6 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x25c ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xb6 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x773 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x6c ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x5ba ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x100 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x140 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x15a ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xb2 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x26 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x48d ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xaa ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x74 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xdd ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x87 ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0x4c ./Core/Src/moteurs.o + .debug_macro 0x0000000000000000 0xee ./Core/Src/moteurs.o + .debug_line 0x0000000000000000 0xb9f ./Core/Src/moteurs.o + .debug_str 0x0000000000000000 0x6eb31 ./Core/Src/moteurs.o + .comment 0x0000000000000000 0x54 ./Core/Src/moteurs.o + .debug_frame 0x0000000000000000 0x100 ./Core/Src/moteurs.o + .ARM.attributes + 0x0000000000000000 0x2c ./Core/Src/moteurs.o + COMMON 0x0000000000000000 0x10 ./Core/Src/moteurs.o + .group 0x0000000000000000 0xc ./Core/Src/sequenceur.o + .text 0x0000000000000000 0x0 ./Core/Src/sequenceur.o + .data 0x0000000000000000 0x0 ./Core/Src/sequenceur.o + .bss 0x0000000000000000 0x0 ./Core/Src/sequenceur.o + .debug_info 0x0000000000000000 0x21 ./Core/Src/sequenceur.o + .debug_abbrev 0x0000000000000000 0x13 ./Core/Src/sequenceur.o + .debug_aranges + 0x0000000000000000 0x18 ./Core/Src/sequenceur.o + .debug_macro 0x0000000000000000 0x11 ./Core/Src/sequenceur.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/sequenceur.o + .debug_line 0x0000000000000000 0x39 ./Core/Src/sequenceur.o + .debug_str 0x0000000000000000 0x2ccb ./Core/Src/sequenceur.o + .comment 0x0000000000000000 0x54 ./Core/Src/sequenceur.o + .ARM.attributes + 0x0000000000000000 0x32 ./Core/Src/sequenceur.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_hal_msp.o + .text 0x0000000000000000 0x0 ./Core/Src/stm32l0xx_hal_msp.o + .data 0x0000000000000000 0x0 ./Core/Src/stm32l0xx_hal_msp.o + .bss 0x0000000000000000 0x0 ./Core/Src/stm32l0xx_hal_msp.o + .text.HAL_ADC_MspDeInit + 0x0000000000000000 0x44 ./Core/Src/stm32l0xx_hal_msp.o + .text.HAL_LPTIM_MspDeInit + 0x0000000000000000 0x48 ./Core/Src/stm32l0xx_hal_msp.o + .text.HAL_UART_MspDeInit + 0x0000000000000000 0x60 ./Core/Src/stm32l0xx_hal_msp.o + .text.HAL_TIM_Base_MspDeInit + 0x0000000000000000 0x2c ./Core/Src/stm32l0xx_hal_msp.o + .text.HAL_TIM_Encoder_MspDeInit + 0x0000000000000000 0x3c ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x131 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3ad ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x7a29 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3555 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x8a0 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x42e ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x18a ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x13f ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xff ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x82 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x24f ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x4da ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x6b ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x129 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1c6 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x25c ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xb6 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x773 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x6c ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x5ba ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x100 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x140 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x15a ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xb2 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x26 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x48d ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xaa ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x74 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xdd ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x87 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x4c ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xee ./Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l0xx_it.o + .text 0x0000000000000000 0x0 ./Core/Src/stm32l0xx_it.o + .data 0x0000000000000000 0x0 ./Core/Src/stm32l0xx_it.o + .bss 0x0000000000000000 0x0 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x131 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x3ad ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x7a29 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x3555 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x8a0 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x42e ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x18a ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x13f ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xff ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x82 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x24f ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x4da ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x6b ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x129 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x1c6 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x25c ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xb6 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x773 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x6c ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x5ba ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x100 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x140 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x15a ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xb2 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x26 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x48d ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xaa ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x74 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xdd ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x87 ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x4c ./Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xee ./Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/syscalls.o + .text 0x0000000000000000 0x0 ./Core/Src/syscalls.o + .data 0x0000000000000000 0x0 ./Core/Src/syscalls.o + .bss 0x0000000000000000 0x0 ./Core/Src/syscalls.o + .bss.__env 0x0000000000000000 0x4 ./Core/Src/syscalls.o + .data.environ 0x0000000000000000 0x4 ./Core/Src/syscalls.o + .text.initialise_monitor_handles + 0x0000000000000000 0xa ./Core/Src/syscalls.o + .text._getpid 0x0000000000000000 0xc ./Core/Src/syscalls.o + .text._kill 0x0000000000000000 0x20 ./Core/Src/syscalls.o + .text._exit 0x0000000000000000 0x18 ./Core/Src/syscalls.o + .text._read 0x0000000000000000 0x3a ./Core/Src/syscalls.o + .text._write 0x0000000000000000 0x38 ./Core/Src/syscalls.o + .text._close 0x0000000000000000 0x14 ./Core/Src/syscalls.o + .text._fstat 0x0000000000000000 0x1c ./Core/Src/syscalls.o + .text._isatty 0x0000000000000000 0x12 ./Core/Src/syscalls.o + .text._lseek 0x0000000000000000 0x16 ./Core/Src/syscalls.o + .text._open 0x0000000000000000 0x1c ./Core/Src/syscalls.o + .text._wait 0x0000000000000000 0x1e ./Core/Src/syscalls.o + .text._unlink 0x0000000000000000 0x1e ./Core/Src/syscalls.o + .text._times 0x0000000000000000 0x14 ./Core/Src/syscalls.o + .text._stat 0x0000000000000000 0x1c ./Core/Src/syscalls.o + .text._link 0x0000000000000000 0x20 ./Core/Src/syscalls.o + .text._fork 0x0000000000000000 0x18 ./Core/Src/syscalls.o + .text._execve 0x0000000000000000 0x22 ./Core/Src/syscalls.o + .debug_info 0x0000000000000000 0xfa8 ./Core/Src/syscalls.o + .debug_abbrev 0x0000000000000000 0x286 ./Core/Src/syscalls.o + .debug_aranges + 0x0000000000000000 0xa8 ./Core/Src/syscalls.o + .debug_ranges 0x0000000000000000 0x98 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x24c ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x4c ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x18 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x94 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x3c ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x34 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x57 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x339 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x43 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x34 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x58 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x71 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x12a ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x35 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x52 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x40 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0xd5 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x3d ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x35 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x12c ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x29 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x241 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x145 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x189 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0xce ./Core/Src/syscalls.o + .debug_line 0x0000000000000000 0x7d5 ./Core/Src/syscalls.o + .debug_str 0x0000000000000000 0x8dde ./Core/Src/syscalls.o + .comment 0x0000000000000000 0x54 ./Core/Src/syscalls.o + .debug_frame 0x0000000000000000 0x244 ./Core/Src/syscalls.o + .ARM.attributes + 0x0000000000000000 0x2c ./Core/Src/syscalls.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/sysmem.o + .text 0x0000000000000000 0x0 ./Core/Src/sysmem.o + .data 0x0000000000000000 0x0 ./Core/Src/sysmem.o + .bss 0x0000000000000000 0x0 ./Core/Src/sysmem.o + .bss.__sbrk_heap_end + 0x0000000000000000 0x4 ./Core/Src/sysmem.o + .text._sbrk 0x0000000000000000 0x6c ./Core/Src/sysmem.o + .debug_info 0x0000000000000000 0xa25 ./Core/Src/sysmem.o + .debug_abbrev 0x0000000000000000 0x1bf ./Core/Src/sysmem.o + .debug_aranges + 0x0000000000000000 0x20 ./Core/Src/sysmem.o + .debug_ranges 0x0000000000000000 0x10 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0xff ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x4c ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x18 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x94 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x3c ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x34 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x43 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x57 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x34 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x10 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x58 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x71 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x12a ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x23b ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/sysmem.o + .debug_line 0x0000000000000000 0x4cb ./Core/Src/sysmem.o + .debug_str 0x0000000000000000 0x61b1 ./Core/Src/sysmem.o + .comment 0x0000000000000000 0x54 ./Core/Src/sysmem.o + .debug_frame 0x0000000000000000 0x30 ./Core/Src/sysmem.o + .ARM.attributes + 0x0000000000000000 0x2c ./Core/Src/sysmem.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l0xx.o + .text 0x0000000000000000 0x0 ./Core/Src/system_stm32l0xx.o + .data 0x0000000000000000 0x0 ./Core/Src/system_stm32l0xx.o + .bss 0x0000000000000000 0x0 ./Core/Src/system_stm32l0xx.o + .text.SystemCoreClockUpdate + 0x0000000000000000 0x170 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xb5 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x3ad ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x7a29 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x66 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x131 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x3555 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x8a0 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x42e ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x18a ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x13f ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xff ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x82 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x24f ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x4da ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x6b ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x129 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x1c6 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x5b ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x25c ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xb6 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x16 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x773 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x6c ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x5ba ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x100 ./Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc ./Core/Src/xbee.o + .text 0x0000000000000000 0x0 ./Core/Src/xbee.o + .data 0x0000000000000000 0x0 ./Core/Src/xbee.o + .bss 0x0000000000000000 0x0 ./Core/Src/xbee.o + .debug_info 0x0000000000000000 0x21 ./Core/Src/xbee.o + .debug_abbrev 0x0000000000000000 0x13 ./Core/Src/xbee.o + .debug_aranges + 0x0000000000000000 0x18 ./Core/Src/xbee.o + .debug_macro 0x0000000000000000 0x11 ./Core/Src/xbee.o + .debug_macro 0x0000000000000000 0xa7e ./Core/Src/xbee.o + .debug_line 0x0000000000000000 0x33 ./Core/Src/xbee.o + .debug_str 0x0000000000000000 0x2cc5 ./Core/Src/xbee.o + .comment 0x0000000000000000 0x54 ./Core/Src/xbee.o + .ARM.attributes + 0x0000000000000000 0x32 ./Core/Src/xbee.o + .text 0x0000000000000000 0x14 ./Core/Startup/startup_stm32l010c6tx.o + .data 0x0000000000000000 0x0 ./Core/Startup/startup_stm32l010c6tx.o + .bss 0x0000000000000000 0x0 ./Core/Startup/startup_stm32l010c6tx.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DeInit + 0x0000000000000000 0x4c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_MspInit + 0x0000000000000000 0xa ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_MspDeInit + 0x0000000000000000 0xa ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetTickPrio + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SetTickFreq + 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetTickFreq + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_Delay + 0x0000000000000000 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SuspendTick + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_ResumeTick + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetHalVersion + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetREVID + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetDEVID + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetUIDw0 + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetUIDw1 + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetUIDw2 + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_EnableDBGSleepMode + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DisableDBGSleepMode + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStopMode + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStopMode + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStandbyMode + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DBG_EnableLowPowerConfig + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DBG_DisableLowPowerConfig + 0x0000000000000000 0x24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SYSCFG_GetBootMode + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SYSCFG_VREFINT_OutputSelect + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SYSCFG_Enable_Lock_VREFINT + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SYSCFG_Disable_Lock_VREFINT + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_DeInit + 0x0000000000000000 0x138 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_Start + 0x0000000000000000 0xa8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_Stop + 0x0000000000000000 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_PollForConversion + 0x0000000000000000 0x138 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_PollForEvent + 0x0000000000000000 0xc2 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_Start_IT + 0x0000000000000000 0xe4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_Stop_IT + 0x0000000000000000 0x94 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_Start_DMA + 0x0000000000000000 0x104 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_Stop_DMA + 0x0000000000000000 0xec ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_GetValue + 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_ConvHalfCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_AnalogWDGConfig + 0x0000000000000000 0x11c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_GetState + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.HAL_ADC_GetError + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.ADC_Enable + 0x0000000000000000 0xd0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.ADC_Disable + 0x0000000000000000 0xce ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.ADC_ConversionStop + 0x0000000000000000 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.ADC_DMAConvCplt + 0x0000000000000000 0xb4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.ADC_DMAHalfConvCplt + 0x0000000000000000 0x1e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.ADC_DMAError + 0x0000000000000000 0x36 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .text.ADC_DelayMicroSecond + 0x0000000000000000 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .text.HAL_ADCEx_Calibration_Start + 0x0000000000000000 0x13c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .text.HAL_ADCEx_Calibration_GetValue + 0x0000000000000000 0x1e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .text.HAL_ADCEx_Calibration_SetValue + 0x0000000000000000 0xbc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .text.HAL_ADCEx_EnableVREFINT + 0x0000000000000000 0x5c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .text.HAL_ADCEx_DisableVREFINT + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .text.HAL_ADCEx_EnableVREFINTTempSensor + 0x0000000000000000 0x5c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .text.HAL_ADCEx_DisableVREFINTTempSensor + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_info 0x0000000000000000 0x8bc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_abbrev 0x0000000000000000 0x1ee ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_aranges + 0x0000000000000000 0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_ranges 0x0000000000000000 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x1f3 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_line 0x0000000000000000 0x8e9 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_str 0x0000000000000000 0x6932e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .debug_frame 0x0000000000000000 0xe8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.__NVIC_DisableIRQ + 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.__NVIC_GetPendingIRQ + 0x0000000000000000 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.__NVIC_SetPendingIRQ + 0x0000000000000000 0x38 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.__NVIC_ClearPendingIRQ + 0x0000000000000000 0x38 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.__NVIC_GetPriority + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.__NVIC_SystemReset + 0x0000000000000000 0x24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_DisableIRQ + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_SystemReset + 0x0000000000000000 0x8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_GetPriority + 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_SetPendingIRQ + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_GetPendingIRQ + 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_ClearPendingIRQ + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_SYSTICK_CLKSourceConfig + 0x0000000000000000 0x34 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_SYSTICK_IRQHandler + 0x0000000000000000 0xe ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_SYSTICK_Callback + 0x0000000000000000 0xa ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_DeInit + 0x0000000000000000 0xbc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_Start + 0x0000000000000000 0x92 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_Start_IT + 0x0000000000000000 0xcc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_PollForTransfer + 0x0000000000000000 0x154 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_RegisterCallback + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_UnRegisterCallback + 0x0000000000000000 0xb0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .rodata.HAL_DMA_UnRegisterCallback + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_GetError + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.DMA_SetConfig + 0x0000000000000000 0x5c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_SetConfigLine + 0x0000000000000000 0x148 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_GetConfigLine + 0x0000000000000000 0xec ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_ClearConfigLine + 0x0000000000000000 0xc0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_RegisterCallback + 0x0000000000000000 0x42 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_GetHandle + 0x0000000000000000 0x24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_IRQHandler + 0x0000000000000000 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_GetPending + 0x0000000000000000 0x3c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_ClearPending + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_GenerateSWI + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_info 0x0000000000000000 0x63d ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_abbrev 0x0000000000000000 0x1e2 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_aranges + 0x0000000000000000 0x60 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_ranges 0x0000000000000000 0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_line 0x0000000000000000 0x9e7 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_str 0x0000000000000000 0x68f98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_frame 0x0000000000000000 0x130 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_Program + 0x0000000000000000 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_Program_IT + 0x0000000000000000 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_IRQHandler + 0x0000000000000000 0x1a8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_EndOfOperationCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_OperationErrorCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_Unlock + 0x0000000000000000 0xa8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_Lock + 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_OB_Unlock + 0x0000000000000000 0x74 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_OB_Lock + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_OB_Launch + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_GetError + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.FLASH_WaitForLastOperation + 0x0000000000000000 0xe4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.FLASH_SetErrorCode + 0x0000000000000000 0x138 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_info 0x0000000000000000 0x66d ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_abbrev 0x0000000000000000 0x2a8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_aranges + 0x0000000000000000 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_ranges 0x0000000000000000 0x70 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1e2 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_line 0x0000000000000000 0xae0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_str 0x0000000000000000 0x69032 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_frame 0x0000000000000000 0x1a4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + COMMON 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase + 0x0000000000000000 0xcc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase_IT + 0x0000000000000000 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBProgram + 0x0000000000000000 0x140 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetConfig + 0x0000000000000000 0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_AdvOBProgram + 0x0000000000000000 0x3e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_AdvOBGetConfig + 0x0000000000000000 0x3c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OB_SelectPCROP + 0x0000000000000000 0xa4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OB_DeSelectPCROP + 0x0000000000000000 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_Unlock + 0x0000000000000000 0x5c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_Lock + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_Erase + 0x0000000000000000 0x58 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_Program + 0x0000000000000000 0xb0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_RDPConfig + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_BORConfig + 0x0000000000000000 0x94 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_BOOTBit1Config + 0x0000000000000000 0x94 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_GetUser + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_GetRDP + 0x0000000000000000 0x34 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_GetBOR + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_GetBOOTBit1 + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_GetWRP + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_ProtectedSectorsConfig + 0x0000000000000000 0xb4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_UserConfig + 0x0000000000000000 0xcc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_PageErase + 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_info 0x0000000000000000 0xafe ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_abbrev 0x0000000000000000 0x2ee ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_aranges + 0x0000000000000000 0xe0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_ranges 0x0000000000000000 0xd0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_line 0x0000000000000000 0xd5a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_str 0x0000000000000000 0x69311 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_frame 0x0000000000000000 0x344 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .RamFunc 0x0000000000000000 0x338 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_info 0x0000000000000000 0x446 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_abbrev 0x0000000000000000 0x1ac ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_aranges + 0x0000000000000000 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_ranges 0x0000000000000000 0x38 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_line 0x0000000000000000 0x865 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_str 0x0000000000000000 0x68f7d ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_frame 0x0000000000000000 0xcc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_DeInit + 0x0000000000000000 0x1a4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_ReadPin + 0x0000000000000000 0x3a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_TogglePin + 0x0000000000000000 0x36 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_LockPin + 0x0000000000000000 0x52 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Init + 0x0000000000000000 0x12c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_DeInit + 0x0000000000000000 0x60 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit + 0x0000000000000000 0x210 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive + 0x0000000000000000 0x210 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit + 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive + 0x0000000000000000 0x214 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_IT + 0x0000000000000000 0xf8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_IT + 0x0000000000000000 0xf8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_IT + 0x0000000000000000 0xac ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_IT + 0x0000000000000000 0xac ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_DMA + 0x0000000000000000 0x20c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_DMA + 0x0000000000000000 0x20c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_DMA + 0x0000000000000000 0x180 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_DMA + 0x0000000000000000 0x180 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write + 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read + 0x0000000000000000 0x268 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_IT + 0x0000000000000000 0x150 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_IT + 0x0000000000000000 0x154 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_DMA + 0x0000000000000000 0x21c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_DMA + 0x0000000000000000 0x220 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_IsDeviceReady + 0x0000000000000000 0x234 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_IT + 0x0000000000000000 0x124 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_DMA + 0x0000000000000000 0x234 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_IT + 0x0000000000000000 0x124 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_DMA + 0x0000000000000000 0x234 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_IT + 0x0000000000000000 0x160 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_DMA + 0x0000000000000000 0x298 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_IT + 0x0000000000000000 0x164 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_DMA + 0x0000000000000000 0x294 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_EnableListen_IT + 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_DisableListen_IT + 0x0000000000000000 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Abort_IT + 0x0000000000000000 0xac ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_EV_IRQHandler + 0x0000000000000000 0x34 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_ER_IRQHandler + 0x0000000000000000 0xc4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MasterTxCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MasterRxCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_SlaveTxCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_SlaveRxCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_AddrCallback + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_ListenCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MemTxCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MemRxCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_ErrorCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_AbortCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_GetMode + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_GetError + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Master_ISR_IT + 0x0000000000000000 0x284 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Slave_ISR_IT + 0x0000000000000000 0x228 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Master_ISR_DMA + 0x0000000000000000 0x218 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Slave_ISR_DMA + 0x0000000000000000 0x1ec ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_RequestMemoryWrite + 0x0000000000000000 0xc8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_RequestMemoryRead + 0x0000000000000000 0xc4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITAddrCplt + 0x0000000000000000 0x148 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITMasterSeqCplt + 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITSlaveSeqCplt + 0x0000000000000000 0xcc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITMasterCplt + 0x0000000000000000 0x1a4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITSlaveCplt + 0x0000000000000000 0x248 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITListenCplt + 0x0000000000000000 0xb4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITError + 0x0000000000000000 0x1c4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_TreatErrorCallback + 0x0000000000000000 0x52 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Flush_TXDR + 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMAMasterTransmitCplt + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMASlaveTransmitCplt + 0x0000000000000000 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMAMasterReceiveCplt + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMASlaveReceiveCplt + 0x0000000000000000 0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMAError + 0x0000000000000000 0x32 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMAAbort + 0x0000000000000000 0x3e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_WaitOnFlagUntilTimeout + 0x0000000000000000 0x7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_WaitOnTXISFlagUntilTimeout + 0x0000000000000000 0x7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_WaitOnSTOPFlagUntilTimeout + 0x0000000000000000 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_WaitOnRXNEFlagUntilTimeout + 0x0000000000000000 0xd8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_IsAcknowledgeFailed + 0x0000000000000000 0xf4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_TransferConfig + 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Enable_IRQ + 0x0000000000000000 0xd0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Disable_IRQ + 0x0000000000000000 0xc6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ConvertOtherXferOptions + 0x0000000000000000 0x34 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_info 0x0000000000000000 0x21c3 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_abbrev 0x0000000000000000 0x267 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_aranges + 0x0000000000000000 0x290 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_ranges 0x0000000000000000 0x280 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x2a6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_line 0x0000000000000000 0x32de ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_str 0x0000000000000000 0x6a077 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_frame 0x0000000000000000 0xa24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigAnalogFilter + 0x0000000000000000 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigDigitalFilter + 0x0000000000000000 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_EnableWakeUp + 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_DisableWakeUp + 0x0000000000000000 0x84 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_info 0x0000000000000000 0x7b1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_abbrev 0x0000000000000000 0x1a7 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_aranges + 0x0000000000000000 0x38 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_ranges 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_line 0x0000000000000000 0x8ff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_str 0x0000000000000000 0x692a3 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_frame 0x0000000000000000 0x90 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_DeInit + 0x0000000000000000 0x56 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_PWM_Start + 0x0000000000000000 0xa4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_PWM_Stop + 0x0000000000000000 0x3c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_PWM_Start_IT + 0x0000000000000000 0x12c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_PWM_Stop_IT + 0x0000000000000000 0x9c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_OnePulse_Start + 0x0000000000000000 0xa4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_OnePulse_Stop + 0x0000000000000000 0x3c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_OnePulse_Start_IT + 0x0000000000000000 0x12c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_OnePulse_Stop_IT + 0x0000000000000000 0x9c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_SetOnce_Start + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_SetOnce_Stop + 0x0000000000000000 0x3c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_SetOnce_Start_IT + 0x0000000000000000 0x128 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_SetOnce_Stop_IT + 0x0000000000000000 0x9c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_Encoder_Start + 0x0000000000000000 0x9c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_Encoder_Stop + 0x0000000000000000 0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_Encoder_Start_IT + 0x0000000000000000 0xe6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_Encoder_Stop_IT + 0x0000000000000000 0x70 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_TimeOut_Start + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_TimeOut_Stop + 0x0000000000000000 0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_TimeOut_Start_IT + 0x0000000000000000 0xec ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_TimeOut_Stop_IT + 0x0000000000000000 0x74 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_Counter_Start + 0x0000000000000000 0x90 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_Counter_Stop + 0x0000000000000000 0x3c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_Counter_Start_IT + 0x0000000000000000 0xec ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_Counter_Stop_IT + 0x0000000000000000 0x70 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_ReadCounter + 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_ReadAutoReload + 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_ReadCompare + 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_IRQHandler + 0x0000000000000000 0x144 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_CompareMatchCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_AutoReloadMatchCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_TriggerCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_CompareWriteCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_AutoReloadWriteCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_DirectionUpCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_DirectionDownCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.HAL_LPTIM_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.LPTIM_WaitForFlag + 0x0000000000000000 0x70 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .text.LPTIM_Disable + 0x0000000000000000 0x178 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DeInit + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnableBkUpAccess + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisableBkUpAccess + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnableWakeUpPin + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisableWakeUpPin + 0x0000000000000000 0x24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnterSLEEPMode + 0x0000000000000000 0xb0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnterSTOPMode + 0x0000000000000000 0xb8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnterSTANDBYMode + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnableSleepOnExit + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisableSleepOnExit + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnableSEVOnPend + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisableSEVOnPend + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_info 0x0000000000000000 0x5d4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_abbrev 0x0000000000000000 0x150 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_aranges + 0x0000000000000000 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_ranges 0x0000000000000000 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_line 0x0000000000000000 0x8b2 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_str 0x0000000000000000 0x68fae ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_frame 0x0000000000000000 0x170 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_GetVoltageRange + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableFastWakeUp + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableFastWakeUp + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableUltraLowPower + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableUltraLowPower + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableLowPowerRunMode + 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableLowPowerRunMode + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_info 0x0000000000000000 0x27a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_abbrev 0x0000000000000000 0x132 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_aranges + 0x0000000000000000 0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_ranges 0x0000000000000000 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1e7 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_line 0x0000000000000000 0x7e5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_str 0x0000000000000000 0x68e8d ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .comment 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_frame 0x0000000000000000 0xd8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .ARM.attributes + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_DeInit + 0x0000000000000000 0x148 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_MCOConfig + 0x0000000000000000 0xc8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_EnableCSS + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_GetOscConfig + 0x0000000000000000 0x160 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_GetClockConfig + 0x0000000000000000 0x64 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_NMI_IRQHandler + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_CSSCallback + 0x0000000000000000 0xa ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKConfig + 0x0000000000000000 0x90 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKFreq + 0x0000000000000000 0x298 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnableLSECSS + 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_DisableLSECSS + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnableLSECSS_IT + 0x0000000000000000 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_LSECSS_IRQHandler + 0x0000000000000000 0x24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_LSECSS_Callback + 0x0000000000000000 0xa ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_DeInit + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_Start + 0x0000000000000000 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_Stop + 0x0000000000000000 0x3c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_Start_IT + 0x0000000000000000 0x88 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_Stop_IT + 0x0000000000000000 0x4c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_Start_DMA + 0x0000000000000000 0xf8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_Stop_DMA + 0x0000000000000000 0x58 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_Init + 0x0000000000000000 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_DeInit + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_Start + 0x0000000000000000 0x108 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_Stop + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_Start_IT + 0x0000000000000000 0x198 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_Stop_IT + 0x0000000000000000 0x108 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_Start_DMA + 0x0000000000000000 0x304 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_Stop_DMA + 0x0000000000000000 0x140 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_DeInit + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_Start + 0x0000000000000000 0x108 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_Stop + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_Start_IT + 0x0000000000000000 0x198 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_Stop_IT + 0x0000000000000000 0x108 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_Start_DMA + 0x0000000000000000 0x304 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_Stop_DMA + 0x0000000000000000 0x140 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_Init + 0x0000000000000000 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_DeInit + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_Start + 0x0000000000000000 0xf4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_Stop + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_Start_IT + 0x0000000000000000 0x180 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_Stop_IT + 0x0000000000000000 0x108 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_Start_DMA + 0x0000000000000000 0x294 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_Stop_DMA + 0x0000000000000000 0x140 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_Init + 0x0000000000000000 0x92 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_DeInit + 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_Start + 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_Stop + 0x0000000000000000 0x60 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_Start_IT + 0x0000000000000000 0x8c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_Stop_IT + 0x0000000000000000 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_DeInit + 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_Start + 0x0000000000000000 0xea ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop + 0x0000000000000000 0xd8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_Start_IT + 0x0000000000000000 0x12a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop_IT + 0x0000000000000000 0x114 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_Start_DMA + 0x0000000000000000 0x2bc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop_DMA + 0x0000000000000000 0x144 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IRQHandler + 0x0000000000000000 0x1d0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_ConfigChannel + 0x0000000000000000 0xb0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_ConfigChannel + 0x0000000000000000 0x148 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_ConfigChannel + 0x0000000000000000 0x1ac ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_DMABurst_WriteStart + 0x0000000000000000 0x4e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_DMABurst_MultiWriteStart + 0x0000000000000000 0x268 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_DMABurst_WriteStop + 0x0000000000000000 0xfc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_DMABurst_ReadStart + 0x0000000000000000 0x4e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_DMABurst_MultiReadStart + 0x0000000000000000 0x268 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_DMABurst_ReadStop + 0x0000000000000000 0xfc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_GenerateEvent + 0x0000000000000000 0x4a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_ConfigOCrefClear + 0x0000000000000000 0x1a4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_ConfigTI1Input + 0x0000000000000000 0x34 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_SlaveConfigSynchro + 0x0000000000000000 0x8c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_SlaveConfigSynchro_IT + 0x0000000000000000 0x8c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_ReadCapturedValue + 0x0000000000000000 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PeriodElapsedCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PeriodElapsedHalfCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_DelayElapsedCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_CaptureCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_CaptureHalfCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_PulseFinishedCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_TriggerCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_TriggerHalfCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_ErrorCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Base_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OC_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_PWM_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_IC_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_OnePulse_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_Encoder_GetState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_GetActiveChannel + 0x0000000000000000 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_GetChannelState + 0x0000000000000000 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIM_DMABurstState + 0x0000000000000000 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMAError + 0x0000000000000000 0x94 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMADelayPulseCplt + 0x0000000000000000 0xaa ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMADelayPulseHalfCplt + 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMACaptureCplt + 0x0000000000000000 0xaa ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMACaptureHalfCplt + 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMAPeriodElapsedCplt + 0x0000000000000000 0x30 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMAPeriodElapsedHalfCplt + 0x0000000000000000 0x1e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMATriggerCplt + 0x0000000000000000 0x30 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_DMATriggerHalfCplt + 0x0000000000000000 0x1e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_SlaveTimer_SetConfig + 0x0000000000000000 0x124 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_TI1_SetConfig + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_TI2_SetConfig + 0x0000000000000000 0x84 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_TI3_SetConfig + 0x0000000000000000 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_TI4_SetConfig + 0x0000000000000000 0x8c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_CCxChannelCmd + 0x0000000000000000 0x46 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .text.HAL_TIMEx_RemapConfig + 0x0000000000000000 0x3a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_HalfDuplex_Init + 0x0000000000000000 0xb8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_LIN_Init + 0x0000000000000000 0xf0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_MultiProcessor_Init + 0x0000000000000000 0xf0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_DeInit + 0x0000000000000000 0x74 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_MspInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_MspDeInit + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_Transmit + 0x0000000000000000 0x150 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_Receive + 0x0000000000000000 0x1dc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_Transmit_IT + 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_Receive_IT + 0x0000000000000000 0xd0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_Transmit_DMA + 0x0000000000000000 0x144 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_Receive_DMA + 0x0000000000000000 0xd0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_DMAPause + 0x0000000000000000 0x130 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_DMAResume + 0x0000000000000000 0x112 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_DMAStop + 0x0000000000000000 0x11e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_Abort + 0x0000000000000000 0x1ec ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_AbortTransmit + 0x0000000000000000 0xcc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_AbortReceive + 0x0000000000000000 0x15c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_Abort_IT + 0x0000000000000000 0x238 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_AbortTransmit_IT + 0x0000000000000000 0xf0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_AbortReceive_IT + 0x0000000000000000 0x18c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_TxHalfCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_RxCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_RxHalfCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_AbortCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_AbortTransmitCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_AbortReceiveCpltCallback + 0x0000000000000000 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_ReceiverTimeout_Config + 0x0000000000000000 0x34 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_EnableReceiverTimeout + 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_DisableReceiverTimeout + 0x0000000000000000 0x70 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_MultiProcessor_EnableMuteMode + 0x0000000000000000 0x70 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_MultiProcessor_DisableMuteMode + 0x0000000000000000 0x74 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_MultiProcessor_EnterMuteMode + 0x0000000000000000 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_HalfDuplex_EnableTransmitter + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_HalfDuplex_EnableReceiver + 0x0000000000000000 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_LIN_SendBreak + 0x0000000000000000 0x4c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_GetState + 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UART_GetError + 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_Start_Receive_IT + 0x0000000000000000 0x160 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_Start_Receive_DMA + 0x0000000000000000 0x144 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_EndTxTransfer + 0x0000000000000000 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMATransmitCplt + 0x0000000000000000 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMATxHalfCplt + 0x0000000000000000 0x1e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMAReceiveCplt + 0x0000000000000000 0x128 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMARxHalfCplt + 0x0000000000000000 0x3c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMAError + 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMATxAbortCallback + 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMARxAbortCallback + 0x0000000000000000 0x7c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMATxOnlyAbortCallback + 0x0000000000000000 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMARxOnlyAbortCallback + 0x0000000000000000 0x4a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_TxISR_8BIT + 0x0000000000000000 0xb2 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_TxISR_16BIT + 0x0000000000000000 0xbc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_RxISR_8BIT + 0x0000000000000000 0x168 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_RxISR_16BIT + 0x0000000000000000 0x168 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .data 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_RS485Ex_Init + 0x0000000000000000 0xe0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_UARTEx_EnableClockStopMode + 0x0000000000000000 0x64 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_UARTEx_DisableClockStopMode + 0x0000000000000000 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_MultiProcessorEx_AddressLength_Set + 0x0000000000000000 0x62 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_UARTEx_StopModeWakeUpSourceConfig + 0x0000000000000000 0xcc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_UARTEx_EnableStopMode + 0x0000000000000000 0x62 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_UARTEx_DisableStopMode + 0x0000000000000000 0x62 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle + 0x0000000000000000 0x248 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle_IT + 0x0000000000000000 0xde ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle_DMA + 0x0000000000000000 0xde ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .text.UARTEx_Wakeup_AddressConfig + 0x0000000000000000 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xa7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x131 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x51 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x103 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x6a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x1df ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x1c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xb5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x3ad ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x7a29 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x66 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x3555 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x174 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x8a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x42e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x18a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x13f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xff ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x24f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x4da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x6b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x129 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x1c6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x5b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x25c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xb6 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x773 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x5ba ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .rodata 0x0000000000000000 0x11 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelGetInfo + 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelGetState + 0x0000000000000000 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelLock + 0x0000000000000000 0x64 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelUnlock + 0x0000000000000000 0x78 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelRestoreLock + 0x0000000000000000 0x8c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelGetTickCount + 0x0000000000000000 0x48 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelGetTickFreq + 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelGetSysTimerCount + 0x0000000000000000 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osKernelGetSysTimerFreq + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadGetName + 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadGetId + 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadGetState + 0x0000000000000000 0x8c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadGetStackSpace + 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadSetPriority + 0x0000000000000000 0x70 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadGetPriority + 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadYield + 0x0000000000000000 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadSuspend + 0x0000000000000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadResume + 0x0000000000000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadExit + 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadTerminate + 0x0000000000000000 0x7c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadGetCount + 0x0000000000000000 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadEnumerate + 0x0000000000000000 0xc8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadFlagsSet + 0x0000000000000000 0xac ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadFlagsClear + 0x0000000000000000 0x98 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadFlagsGet + 0x0000000000000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osThreadFlagsWait + 0x0000000000000000 0x118 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osDelay 0x0000000000000000 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osDelayUntil + 0x0000000000000000 0x74 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.TimerCallback + 0x0000000000000000 0x2e ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osTimerNew + 0x0000000000000000 0x110 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osTimerGetName + 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osTimerStart + 0x0000000000000000 0x74 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osTimerStop + 0x0000000000000000 0x88 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osTimerIsRunning + 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osTimerDelete + 0x0000000000000000 0x88 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osEventFlagsNew + 0x0000000000000000 0x9c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osEventFlagsSet + 0x0000000000000000 0x9c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osEventFlagsClear + 0x0000000000000000 0x88 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osEventFlagsGet + 0x0000000000000000 0x64 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osEventFlagsWait + 0x0000000000000000 0xdc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osEventFlagsDelete + 0x0000000000000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMutexNew + 0x0000000000000000 0x134 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMutexAcquire + 0x0000000000000000 0xb8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMutexRelease + 0x0000000000000000 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMutexGetOwner + 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMutexDelete + 0x0000000000000000 0x68 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osSemaphoreNew + 0x0000000000000000 0x144 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osSemaphoreAcquire + 0x0000000000000000 0xbc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osSemaphoreRelease + 0x0000000000000000 0x9c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osSemaphoreGetCount + 0x0000000000000000 0x60 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osSemaphoreDelete + 0x0000000000000000 0x64 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueueNew + 0x0000000000000000 0x10c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueuePut + 0x0000000000000000 0xd4 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueueGet + 0x0000000000000000 0xd0 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueueGetCapacity + 0x0000000000000000 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueueGetMsgSize + 0x0000000000000000 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueueGetCount + 0x0000000000000000 0x60 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueueGetSpace + 0x0000000000000000 0x70 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueueReset + 0x0000000000000000 0x60 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osMessageQueueDelete + 0x0000000000000000 0x64 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x174 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x71 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x12a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x339 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x35 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x74 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_info 0x0000000000000000 0x9a ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_abbrev 0x0000000000000000 0x4b ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_aranges + 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xe3 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x174 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x8e ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x51 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_line 0x0000000000000000 0x499 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_str 0x0000000000000000 0x7fe3 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .comment 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .ARM.attributes + 0x0000000000000000 0x32 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupCreateStatic + 0x0000000000000000 0x4a ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupCreate + 0x0000000000000000 0x36 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupSync + 0x0000000000000000 0x11c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupWaitBits + 0x0000000000000000 0x14c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupClearBits + 0x0000000000000000 0x4a ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupClearBitsFromISR + 0x0000000000000000 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupGetBitsFromISR + 0x0000000000000000 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupSetBits + 0x0000000000000000 0xf2 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.vEventGroupDelete + 0x0000000000000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.vEventGroupSetBitsCallback + 0x0000000000000000 0x1e ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.vEventGroupClearBitsCallback + 0x0000000000000000 0x1e ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.prvTestWaitCondition + 0x0000000000000000 0x3e ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupSetBitsFromISR + 0x0000000000000000 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.uxEventGroupGetNumber + 0x0000000000000000 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.vEventGroupSetNumber + 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_info 0x0000000000000000 0x11e7 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_abbrev 0x0000000000000000 0x27c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_aranges + 0x0000000000000000 0x90 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_ranges 0x0000000000000000 0x80 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1e2 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x10e ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x8d ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x71 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x12a ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x339 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x29 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x91 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_line 0x0000000000000000 0xa1e ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_str 0x0000000000000000 0xba99 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .comment 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_frame 0x0000000000000000 0x1f0 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .ARM.attributes + 0x0000000000000000 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x10e ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x8d ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x71 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x12a ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x339 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x29 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvInitialiseMutex + 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueCreateMutex + 0x0000000000000000 0x38 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueCreateMutexStatic + 0x0000000000000000 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGetMutexHolder + 0x0000000000000000 0x32 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGetMutexHolderFromISR + 0x0000000000000000 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGiveMutexRecursive + 0x0000000000000000 0x56 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueTakeMutexRecursive + 0x0000000000000000 0x60 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueCreateCountingSemaphoreStatic + 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueCreateCountingSemaphore + 0x0000000000000000 0x46 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGiveFromISR + 0x0000000000000000 0xca ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueSemaphoreTake + 0x0000000000000000 0x1b4 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueuePeek + 0x0000000000000000 0x16e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueReceiveFromISR + 0x0000000000000000 0xc6 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueuePeekFromISR + 0x0000000000000000 0x84 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.uxQueueMessagesWaiting + 0x0000000000000000 0x2a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.uxQueueSpacesAvailable + 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.uxQueueMessagesWaitingFromISR + 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.vQueueDelete + 0x0000000000000000 0x38 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.uxQueueGetQueueNumber + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.vQueueSetQueueNumber + 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.ucQueueGetQueueType + 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvGetDisinheritPriorityAfterTimeout + 0x0000000000000000 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueIsQueueEmptyFromISR + 0x0000000000000000 0x32 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueIsQueueFullFromISR + 0x0000000000000000 0x36 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.pcQueueGetName + 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.vQueueUnregisterQueue + 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x10e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x8d ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x71 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x12a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x339 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x29 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x35 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x87 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferGenericCreate + 0x0000000000000000 0x8a ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferGenericCreateStatic + 0x0000000000000000 0xb0 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.vStreamBufferDelete + 0x0000000000000000 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferReset + 0x0000000000000000 0x66 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSetTriggerLevel + 0x0000000000000000 0x46 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSpacesAvailable + 0x0000000000000000 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferBytesAvailable + 0x0000000000000000 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSend + 0x0000000000000000 0x12e ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSendFromISR + 0x0000000000000000 0xb0 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvWriteMessageToBuffer + 0x0000000000000000 0x7c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferReceive + 0x0000000000000000 0x104 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferNextMessageLengthBytes + 0x0000000000000000 0x72 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferReceiveFromISR + 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvReadMessageFromBuffer + 0x0000000000000000 0x66 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferIsEmpty + 0x0000000000000000 0x3a ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferIsFull + 0x0000000000000000 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSendCompletedFromISR + 0x0000000000000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferReceiveCompletedFromISR + 0x0000000000000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvWriteBytesToBuffer + 0x0000000000000000 0xae ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvReadBytesFromBuffer + 0x0000000000000000 0xbe ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvBytesInBuffer + 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvInitialiseNewStreamBuffer + 0x0000000000000000 0x5a ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.uxStreamBufferGetStreamBufferNumber + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.vStreamBufferSetStreamBufferNumber + 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.ucStreamBufferGetStreamBufferType + 0x0000000000000000 0x1a ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_info 0x0000000000000000 0x164d ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_abbrev 0x0000000000000000 0x2d1 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_aranges + 0x0000000000000000 0xe0 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_ranges 0x0000000000000000 0xd0 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1e0 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x8e ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x51 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x52 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x174 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x71 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x12a ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x339 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x35 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_line 0x0000000000000000 0xd4a ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_str 0x0000000000000000 0xbb3d ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .comment 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_frame 0x0000000000000000 0x330 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .ARM.attributes + 0x0000000000000000 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskDelete + 0x0000000000000000 0xc8 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskDelayUntil + 0x0000000000000000 0xb8 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.eTaskGetState + 0x0000000000000000 0xdc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskPriorityGet + 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskPriorityGetFromISR + 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskPrioritySet + 0x0000000000000000 0x118 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskSuspend + 0x0000000000000000 0xcc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskResumeFromISR + 0x0000000000000000 0xbc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskEndScheduler + 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetTickCountFromISR + 0x0000000000000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskGetNumberOfTasks + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.pcTaskGetName + 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvSearchForNameWithinSingleList + 0x0000000000000000 0xe4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetHandle + 0x0000000000000000 0xd4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskGetSystemState + 0x0000000000000000 0x11c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskAbortDelay + 0x0000000000000000 0xc0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskPlaceOnUnorderedEventList + 0x0000000000000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskRemoveFromUnorderedEventList + 0x0000000000000000 0xa4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskSetTimeOutState + 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskGetTaskNumber + 0x0000000000000000 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskSetTaskNumber + 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskGetInfo + 0x0000000000000000 0xd8 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvListTasksWithinSingleList + 0x0000000000000000 0xa6 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvTaskCheckFreeStackSpace + 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskGetStackHighWaterMark + 0x0000000000000000 0x38 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetCurrentTaskHandle + 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskPriorityInherit + 0x0000000000000000 0xd0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskPriorityDisinheritAfterTimeout + 0x0000000000000000 0xe0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskResetEventItemValue + 0x0000000000000000 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.pvTaskIncrementMutexHeldCount + 0x0000000000000000 0x24 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.ulTaskNotifyTake + 0x0000000000000000 0x84 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskNotifyWait + 0x0000000000000000 0xa8 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGenericNotify + 0x0000000000000000 0x12c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .rodata.xTaskGenericNotify + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGenericNotifyFromISR + 0x0000000000000000 0x164 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .rodata.xTaskGenericNotifyFromISR + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskNotifyGiveFromISR + 0x0000000000000000 0xf0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskNotifyStateClear + 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x10e ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x8d ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x71 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x12a ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x339 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x29 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x35 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x91 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.xTimerCreate + 0x0000000000000000 0x46 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.xTimerCreateStatic + 0x0000000000000000 0x5a ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvInitialiseNewTimer + 0x0000000000000000 0x64 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.xTimerGetTimerDaemonTaskHandle + 0x0000000000000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.xTimerGetPeriod + 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.vTimerSetReloadMode + 0x0000000000000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.xTimerGetExpiryTime + 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.pcTimerGetName + 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.xTimerIsTimerActive + 0x0000000000000000 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.pvTimerGetTimerID + 0x0000000000000000 0x2e ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.vTimerSetTimerID + 0x0000000000000000 0x2e ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.xTimerPendFunctionCallFromISR + 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.xTimerPendFunctionCall + 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.uxTimerGetTimerNumber + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.vTimerSetTimerNumber + 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x10e ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x8d ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x71 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x12a ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x339 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x29 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x87 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .text.vPortEndScheduler + 0x0000000000000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x174 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x8e ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x51 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .rodata.xHeapStructSize + 0x0000000000000000 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.xPortGetFreeHeapSize + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.xPortGetMinimumEverFreeHeapSize + 0x0000000000000000 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.vPortInitialiseBlocks + 0x0000000000000000 0xa ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xa7e ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x10e ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x8d ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x71 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x12a ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x339 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x29 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x140 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x15a ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xb2 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x26 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x48d ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xb5 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .text.__errno 0x0000000000000000 0xc /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .debug_frame 0x0000000000000000 0x20 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .text.exit 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .debug_frame 0x0000000000000000 0x28 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .data._impure_ptr + 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .data.impure_data + 0x0000000000000000 0x60 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .rodata._global_impure_ptr + 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .text 0x0000000000000000 0xe /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-strlen.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-strlen.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-strlen.o) + .ARM.attributes + 0x0000000000000000 0x1c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-strlen.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.extab 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .eh_frame 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x0000000020000000 0x0000000000002000 xrw +FLASH 0x0000000008000000 0x0000000000008000 xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +LOAD ./Core/Src/batterie.o +LOAD ./Core/Src/freertos.o +LOAD ./Core/Src/leds.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/messages.o +LOAD ./Core/Src/moteurs.o +LOAD ./Core/Src/sequenceur.o +LOAD ./Core/Src/stm32l0xx_hal_msp.o +LOAD ./Core/Src/stm32l0xx_it.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32l0xx.o +LOAD ./Core/Src/xbee.o +LOAD ./Core/Startup/startup_stm32l010c6tx.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o +LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/list.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/queue.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/timers.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o +START GROUP +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a +END GROUP +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + 0x0000000020002000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0xc0 + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0xc0 ./Core/Startup/startup_stm32l010c6tx.o + 0x0000000008000000 g_pfnVectors + 0x00000000080000c0 . = ALIGN (0x4) + +.text 0x00000000080000c0 0x7728 + 0x00000000080000c0 . = ALIGN (0x4) + *(.text) + .text 0x00000000080000c0 0x48 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x0000000008000108 0x114 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + 0x0000000008000108 __udivsi3 + 0x0000000008000108 __aeabi_uidiv + 0x0000000008000214 __aeabi_uidivmod + .text 0x000000000800021c 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + 0x000000000800021c __aeabi_ldiv0 + 0x000000000800021c __aeabi_idiv0 + .text 0x0000000008000220 0x40 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x0000000008000220 __aeabi_uldivmod + .text 0x0000000008000260 0x50 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + 0x0000000008000260 __aeabi_lmul + 0x0000000008000260 __muldi3 + .text 0x00000000080002b0 0x198 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + 0x00000000080002b0 __udivmoddi4 + .text 0x0000000008000448 0x18 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + 0x0000000008000448 __clzdi2 + .text 0x0000000008000460 0x3c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + 0x0000000008000460 __clzsi2 + *(.text*) + .text.PreSleepProcessing + 0x000000000800049c 0x10 ./Core/Src/freertos.o + 0x000000000800049c PreSleepProcessing + .text.PostSleepProcessing + 0x00000000080004ac 0x10 ./Core/Src/freertos.o + 0x00000000080004ac PostSleepProcessing + .text.LEDS_Init + 0x00000000080004bc 0x80 ./Core/Src/leds.o + 0x00000000080004bc LEDS_Init + .text.LEDS_AnimationThread + 0x000000000800053c 0x474 ./Core/Src/leds.o + 0x000000000800053c LEDS_AnimationThread + .text.main 0x00000000080009b0 0x58 ./Core/Src/main.o + 0x00000000080009b0 main + .text.SystemClock_Config + 0x0000000008000a08 0xe8 ./Core/Src/main.o + 0x0000000008000a08 SystemClock_Config + .text.MX_ADC_Init + 0x0000000008000af0 0xc8 ./Core/Src/main.o + .text.MX_LPTIM1_Init + 0x0000000008000bb8 0x60 ./Core/Src/main.o + .text.MX_LPUART1_UART_Init + 0x0000000008000c18 0x5c ./Core/Src/main.o + .text.MX_TIM2_Init + 0x0000000008000c74 0x138 ./Core/Src/main.o + .text.MX_TIM21_Init + 0x0000000008000dac 0xc8 ./Core/Src/main.o + .text.MX_DMA_Init + 0x0000000008000e74 0x3c ./Core/Src/main.o + .text.MX_GPIO_Init + 0x0000000008000eb0 0x130 ./Core/Src/main.o + .text.StartDefaultTask + 0x0000000008000fe0 0x54 ./Core/Src/main.o + 0x0000000008000fe0 StartDefaultTask + .text.Error_Handler + 0x0000000008001034 0xa ./Core/Src/main.o + 0x0000000008001034 Error_Handler + *fill* 0x000000000800103e 0x2 + .text.MESSAGE_Init + 0x0000000008001040 0x70 ./Core/Src/messages.o + 0x0000000008001040 MESSAGE_Init + .text.MESSAGE_ReadMailboxNoDelay + 0x00000000080010b0 0x44 ./Core/Src/messages.o + 0x00000000080010b0 MESSAGE_ReadMailboxNoDelay + .text.MESSAGE_SendMailbox + 0x00000000080010f4 0x3e ./Core/Src/messages.o + 0x00000000080010f4 MESSAGE_SendMailbox + *fill* 0x0000000008001132 0x2 + .text.HAL_MspInit + 0x0000000008001134 0x38 ./Core/Src/stm32l0xx_hal_msp.o + 0x0000000008001134 HAL_MspInit + .text.HAL_ADC_MspInit + 0x000000000800116c 0x88 ./Core/Src/stm32l0xx_hal_msp.o + 0x000000000800116c HAL_ADC_MspInit + .text.HAL_LPTIM_MspInit + 0x00000000080011f4 0xcc ./Core/Src/stm32l0xx_hal_msp.o + 0x00000000080011f4 HAL_LPTIM_MspInit + .text.HAL_UART_MspInit + 0x00000000080012c0 0x154 ./Core/Src/stm32l0xx_hal_msp.o + 0x00000000080012c0 HAL_UART_MspInit + .text.HAL_TIM_Base_MspInit + 0x0000000008001414 0x2c ./Core/Src/stm32l0xx_hal_msp.o + 0x0000000008001414 HAL_TIM_Base_MspInit + .text.HAL_TIM_Encoder_MspInit + 0x0000000008001440 0x84 ./Core/Src/stm32l0xx_hal_msp.o + 0x0000000008001440 HAL_TIM_Encoder_MspInit + .text.HAL_TIM_MspPostInit + 0x00000000080014c4 0xec ./Core/Src/stm32l0xx_hal_msp.o + 0x00000000080014c4 HAL_TIM_MspPostInit + .text.NMI_Handler + 0x00000000080015b0 0x6 ./Core/Src/stm32l0xx_it.o + 0x00000000080015b0 NMI_Handler + .text.HardFault_Handler + 0x00000000080015b6 0x6 ./Core/Src/stm32l0xx_it.o + 0x00000000080015b6 HardFault_Handler + .text.SysTick_Handler + 0x00000000080015bc 0x1c ./Core/Src/stm32l0xx_it.o + 0x00000000080015bc SysTick_Handler + .text.EXTI2_3_IRQHandler + 0x00000000080015d8 0x10 ./Core/Src/stm32l0xx_it.o + 0x00000000080015d8 EXTI2_3_IRQHandler + .text.DMA1_Channel2_3_IRQHandler + 0x00000000080015e8 0x24 ./Core/Src/stm32l0xx_it.o + 0x00000000080015e8 DMA1_Channel2_3_IRQHandler + .text.ADC1_IRQHandler + 0x000000000800160c 0x18 ./Core/Src/stm32l0xx_it.o + 0x000000000800160c ADC1_IRQHandler + .text.LPUART1_IRQHandler + 0x0000000008001624 0x18 ./Core/Src/stm32l0xx_it.o + 0x0000000008001624 LPUART1_IRQHandler + .text.SystemInit + 0x000000000800163c 0xa ./Core/Src/system_stm32l0xx.o + 0x000000000800163c SystemInit + *fill* 0x0000000008001646 0x2 + .text.Reset_Handler + 0x0000000008001648 0x80 ./Core/Startup/startup_stm32l010c6tx.o + 0x0000000008001648 Reset_Handler + .text.Default_Handler + 0x00000000080016c8 0x2 ./Core/Startup/startup_stm32l010c6tx.o + 0x00000000080016c8 I2C1_IRQHandler + 0x00000000080016c8 SPI1_IRQHandler + 0x00000000080016c8 RTC_IRQHandler + 0x00000000080016c8 DMA1_Channel4_5_6_7_IRQHandler + 0x00000000080016c8 EXTI4_15_IRQHandler + 0x00000000080016c8 RCC_IRQHandler + 0x00000000080016c8 DMA1_Channel1_IRQHandler + 0x00000000080016c8 Default_Handler + 0x00000000080016c8 EXTI0_1_IRQHandler + 0x00000000080016c8 TIM21_IRQHandler + 0x00000000080016c8 WWDG_IRQHandler + 0x00000000080016c8 TIM2_IRQHandler + 0x00000000080016c8 USART2_IRQHandler + 0x00000000080016c8 FLASH_IRQHandler + 0x00000000080016c8 LPTIM1_IRQHandler + *fill* 0x00000000080016ca 0x2 + .text.HAL_Init + 0x00000000080016cc 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x00000000080016cc HAL_Init + .text.HAL_InitTick + 0x000000000800170c 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x000000000800170c HAL_InitTick + .text.HAL_IncTick + 0x0000000008001774 0x24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000008001774 HAL_IncTick + .text.HAL_GetTick + 0x0000000008001798 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000008001798 HAL_GetTick + .text.HAL_ADC_Init + 0x00000000080017ac 0x2e8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + 0x00000000080017ac HAL_ADC_Init + .text.HAL_ADC_IRQHandler + 0x0000000008001a94 0x178 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + 0x0000000008001a94 HAL_ADC_IRQHandler + .text.HAL_ADC_ConvCpltCallback + 0x0000000008001c0c 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + 0x0000000008001c0c HAL_ADC_ConvCpltCallback + .text.HAL_ADC_LevelOutOfWindowCallback + 0x0000000008001c1c 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + 0x0000000008001c1c HAL_ADC_LevelOutOfWindowCallback + .text.HAL_ADC_ErrorCallback + 0x0000000008001c2c 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + 0x0000000008001c2c HAL_ADC_ErrorCallback + .text.HAL_ADC_ConfigChannel + 0x0000000008001c3c 0xd0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + 0x0000000008001c3c HAL_ADC_ConfigChannel + .text.__NVIC_EnableIRQ + 0x0000000008001d0c 0x34 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.__NVIC_SetPriority + 0x0000000008001d40 0xdc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.SysTick_Config + 0x0000000008001e1c 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_SetPriority + 0x0000000008001e64 0x2a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + 0x0000000008001e64 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x0000000008001e8e 0x20 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + 0x0000000008001e8e HAL_NVIC_EnableIRQ + .text.HAL_SYSTICK_Config + 0x0000000008001eae 0x1a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + 0x0000000008001eae HAL_SYSTICK_Config + .text.HAL_DMA_Init + 0x0000000008001ec8 0xf0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + 0x0000000008001ec8 HAL_DMA_Init + .text.HAL_DMA_Abort + 0x0000000008001fb8 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + 0x0000000008001fb8 HAL_DMA_Abort + .text.HAL_DMA_Abort_IT + 0x0000000008002038 0x8e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + 0x0000000008002038 HAL_DMA_Abort_IT + .text.HAL_DMA_IRQHandler + 0x00000000080020c6 0x15c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + 0x00000000080020c6 HAL_DMA_IRQHandler + *fill* 0x0000000008002222 0x2 + .text.HAL_GPIO_Init + 0x0000000008002224 0x2dc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + 0x0000000008002224 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x0000000008002500 0x3a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + 0x0000000008002500 HAL_GPIO_WritePin + *fill* 0x000000000800253a 0x2 + .text.HAL_GPIO_EXTI_IRQHandler + 0x000000000800253c 0x38 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + 0x000000000800253c HAL_GPIO_EXTI_IRQHandler + .text.HAL_GPIO_EXTI_Callback + 0x0000000008002574 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + 0x0000000008002574 HAL_GPIO_EXTI_Callback + .text.HAL_LPTIM_Init + 0x0000000008002588 0x118 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + 0x0000000008002588 HAL_LPTIM_Init + .text.HAL_RCC_OscConfig + 0x00000000080026a0 0x6f8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x00000000080026a0 HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x0000000008002d98 0x290 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x0000000008002d98 HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x0000000008003028 0x14c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x0000000008003028 HAL_RCC_GetSysClockFreq + .text.HAL_RCC_GetHCLKFreq + 0x0000000008003174 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x0000000008003174 HAL_RCC_GetHCLKFreq + .text.HAL_RCC_GetPCLK1Freq + 0x0000000008003188 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x0000000008003188 HAL_RCC_GetPCLK1Freq + .text.HAL_RCC_GetPCLK2Freq + 0x00000000080031b4 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x00000000080031b4 HAL_RCC_GetPCLK2Freq + .text.HAL_RCCEx_PeriphCLKConfig + 0x00000000080031e0 0x24c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + 0x00000000080031e0 HAL_RCCEx_PeriphCLKConfig + .text.HAL_TIM_Base_Init + 0x000000000800342c 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + 0x000000000800342c HAL_TIM_Base_Init + .text.HAL_TIM_PWM_Init + 0x00000000080034ac 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + 0x00000000080034ac HAL_TIM_PWM_Init + .text.HAL_TIM_PWM_MspInit + 0x000000000800352c 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + 0x000000000800352c HAL_TIM_PWM_MspInit + .text.HAL_TIM_Encoder_Init + 0x000000000800353c 0x140 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + 0x000000000800353c HAL_TIM_Encoder_Init + .text.HAL_TIM_PWM_ConfigChannel + 0x000000000800367c 0x18c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + 0x000000000800367c HAL_TIM_PWM_ConfigChannel + .text.HAL_TIM_ConfigClockSource + 0x0000000008003808 0x1a8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + 0x0000000008003808 HAL_TIM_ConfigClockSource + .text.TIM_Base_SetConfig + 0x00000000080039b0 0x94 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_OC1_SetConfig + 0x0000000008003a44 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_OC2_SetConfig + 0x0000000008003abc 0x84 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_OC3_SetConfig + 0x0000000008003b40 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_OC4_SetConfig + 0x0000000008003bc0 0x8c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_TI1_ConfigInputStage + 0x0000000008003c4c 0x5c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_TI2_ConfigInputStage + 0x0000000008003ca8 0x64 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.TIM_ITRx_SetConfig + 0x0000000008003d0c 0x32 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + *fill* 0x0000000008003d3e 0x2 + .text.TIM_ETR_SetConfig + 0x0000000008003d40 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text.HAL_TIMEx_MasterConfigSynchronization + 0x0000000008003d80 0xa0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + 0x0000000008003d80 HAL_TIMEx_MasterConfigSynchronization + .text.HAL_UART_Init + 0x0000000008003e20 0xa8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x0000000008003e20 HAL_UART_Init + .text.HAL_UART_IRQHandler + 0x0000000008003ec8 0x5b4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x0000000008003ec8 HAL_UART_IRQHandler + .text.HAL_UART_TxCpltCallback + 0x000000000800447c 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x000000000800447c HAL_UART_TxCpltCallback + .text.HAL_UART_ErrorCallback + 0x000000000800448c 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x000000000800448c HAL_UART_ErrorCallback + .text.HAL_UARTEx_RxEventCallback + 0x000000000800449c 0x16 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x000000000800449c HAL_UARTEx_RxEventCallback + *fill* 0x00000000080044b2 0x2 + .text.UART_SetConfig + 0x00000000080044b4 0x4c4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x00000000080044b4 UART_SetConfig + .text.UART_AdvFeatureConfig + 0x0000000008004978 0x168 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x0000000008004978 UART_AdvFeatureConfig + .text.UART_CheckIdleState + 0x0000000008004ae0 0x90 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x0000000008004ae0 UART_CheckIdleState + .text.UART_WaitOnFlagUntilTimeout + 0x0000000008004b70 0x188 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x0000000008004b70 UART_WaitOnFlagUntilTimeout + .text.UART_EndRxTransfer + 0x0000000008004cf8 0xc4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_DMAAbortOnError + 0x0000000008004dbc 0x2e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.UART_EndTransmit_IT + 0x0000000008004dea 0x56 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .text.HAL_UARTEx_WakeupCallback + 0x0000000008004e40 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + 0x0000000008004e40 HAL_UARTEx_WakeupCallback + .text.SVC_Setup + 0x0000000008004e50 0xa ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + *fill* 0x0000000008004e5a 0x2 + .text.osKernelInitialize + 0x0000000008004e5c 0x58 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x0000000008004e5c osKernelInitialize + .text.osKernelStart + 0x0000000008004eb4 0x60 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x0000000008004eb4 osKernelStart + .text.osThreadNew + 0x0000000008004f14 0x148 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x0000000008004f14 osThreadNew + .text.vApplicationGetIdleTaskMemory + 0x000000000800505c 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x000000000800505c vApplicationGetIdleTaskMemory + .text.vApplicationGetTimerTaskMemory + 0x000000000800508c 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x000000000800508c vApplicationGetTimerTaskMemory + .text.vListInitialise + 0x00000000080050bc 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x00000000080050bc vListInitialise + .text.vListInitialiseItem + 0x00000000080050f8 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x00000000080050f8 vListInitialiseItem + .text.vListInsertEnd + 0x000000000800510e 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x000000000800510e vListInsertEnd + .text.vListInsert + 0x0000000008005152 0x6c ./Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x0000000008005152 vListInsert + .text.uxListRemove + 0x00000000080051be 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x00000000080051be uxListRemove + .text.xQueueGenericReset + 0x000000000800520e 0xa8 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x000000000800520e xQueueGenericReset + .text.xQueueGenericCreateStatic + 0x00000000080052b6 0x98 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x00000000080052b6 xQueueGenericCreateStatic + .text.xQueueGenericCreate + 0x000000000800534e 0x70 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x000000000800534e xQueueGenericCreate + .text.prvInitialiseNewQueue + 0x00000000080053be 0x4e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGenericSend + 0x000000000800540c 0x188 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x000000000800540c xQueueGenericSend + .text.xQueueGenericSendFromISR + 0x0000000008005594 0xe2 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x0000000008005594 xQueueGenericSendFromISR + .text.xQueueReceive + 0x0000000008005676 0x16a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x0000000008005676 xQueueReceive + .text.prvCopyDataToQueue + 0x00000000080057e0 0xd6 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvCopyDataFromQueue + 0x00000000080058b6 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvUnlockQueue + 0x0000000008005902 0xbc ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvIsQueueEmpty + 0x00000000080059be 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvIsQueueFull + 0x00000000080059ea 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + *fill* 0x0000000008005a1a 0x2 + .text.vQueueAddToRegistry + 0x0000000008005a1c 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x0000000008005a1c vQueueAddToRegistry + .text.vQueueWaitForMessageRestricted + 0x0000000008005a6c 0x66 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x0000000008005a6c vQueueWaitForMessageRestricted + .text.xTaskCreateStatic + 0x0000000008005ad2 0x88 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008005ad2 xTaskCreateStatic + .text.xTaskCreate + 0x0000000008005b5a 0x98 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008005b5a xTaskCreate + *fill* 0x0000000008005bf2 0x2 + .text.prvInitialiseNewTask + 0x0000000008005bf4 0x11c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvAddNewTaskToReadyList + 0x0000000008005d10 0xd0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskDelay + 0x0000000008005de0 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008005de0 vTaskDelay + .text.prvTaskIsTaskSuspended + 0x0000000008005e2c 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskResume + 0x0000000008005e78 0x9c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008005e78 vTaskResume + .text.vTaskStartScheduler + 0x0000000008005f14 0xa8 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008005f14 vTaskStartScheduler + .text.vTaskSuspendAll + 0x0000000008005fbc 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008005fbc vTaskSuspendAll + .text.prvGetExpectedIdleTime + 0x0000000008005fd4 0x6c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskResumeAll + 0x0000000008006040 0x118 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008006040 xTaskResumeAll + .text.xTaskGetTickCount + 0x0000000008006158 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008006158 xTaskGetTickCount + .text.vTaskStepTick + 0x0000000008006174 0x38 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008006174 vTaskStepTick + .text.xTaskIncrementTick + 0x00000000080061ac 0x160 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x00000000080061ac xTaskIncrementTick + .text.vTaskSwitchContext + 0x000000000800630c 0xa4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800630c vTaskSwitchContext + .text.vTaskPlaceOnEventList + 0x00000000080063b0 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x00000000080063b0 vTaskPlaceOnEventList + .text.vTaskPlaceOnEventListRestricted + 0x00000000080063ec 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x00000000080063ec vTaskPlaceOnEventListRestricted + .text.xTaskRemoveFromEventList + 0x0000000008006438 0xbc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008006438 xTaskRemoveFromEventList + .text.vTaskInternalSetTimeOutState + 0x00000000080064f4 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x00000000080064f4 vTaskInternalSetTimeOutState + .text.xTaskCheckForTimeOut + 0x000000000800651c 0xc0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800651c xTaskCheckForTimeOut + .text.vTaskMissedYield + 0x00000000080065dc 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x00000000080065dc vTaskMissedYield + .text.prvIdleTask + 0x00000000080065f0 0x64 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.eTaskConfirmSleepModeStatus + 0x0000000008006654 0x64 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008006654 eTaskConfirmSleepModeStatus + .text.prvInitialiseTaskLists + 0x00000000080066b8 0x88 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvCheckTasksWaitingTermination + 0x0000000008006740 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvDeleteTCB + 0x000000000800679c 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvResetNextTaskUnblockTime + 0x00000000080067ec 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetSchedulerState + 0x0000000008006828 0x38 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008006828 xTaskGetSchedulerState + .text.xTaskPriorityDisinherit + 0x0000000008006860 0xb8 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x0000000008006860 xTaskPriorityDisinherit + .text.prvAddCurrentTaskToDelayedList + 0x0000000008006918 0xb4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTimerCreateTimerTask + 0x00000000080069cc 0x7c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + 0x00000000080069cc xTimerCreateTimerTask + .text.xTimerGenericCommand + 0x0000000008006a48 0x94 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + 0x0000000008006a48 xTimerGenericCommand + .text.prvProcessExpiredTimer + 0x0000000008006adc 0x88 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvTimerTask + 0x0000000008006b64 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvProcessTimerOrBlockTask + 0x0000000008006b8c 0x90 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvGetNextExpireTime + 0x0000000008006c1c 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvSampleTimeNow + 0x0000000008006c60 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvInsertTimerInActiveList + 0x0000000008006ca0 0x84 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvProcessReceivedCommands + 0x0000000008006d24 0x18c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvSwitchTimerLists + 0x0000000008006eb0 0xbc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.prvCheckForValidListAndQueue + 0x0000000008006f6c 0x84 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text.pxPortInitialiseStack + 0x0000000008006ff0 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x0000000008006ff0 pxPortInitialiseStack + .text.prvTaskExitError + 0x0000000008007044 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .text.SVC_Handler + 0x0000000008007074 0xa ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x0000000008007074 SVC_Handler + *fill* 0x000000000800707e 0x2 + .text.vPortStartFirstTask + 0x0000000008007080 0x38 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .text.xPortStartScheduler + 0x00000000080070b8 0x48 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x00000000080070b8 xPortStartScheduler + .text.vPortYield + 0x0000000008007100 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x0000000008007100 vPortYield + .text.vPortEnterCritical + 0x0000000008007120 0x24 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x0000000008007120 vPortEnterCritical + .text.vPortExitCritical + 0x0000000008007144 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x0000000008007144 vPortExitCritical + .text.ulSetInterruptMaskFromISR + 0x0000000008007174 0xc ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x0000000008007174 ulSetInterruptMaskFromISR + .text.vClearInterruptMaskFromISR + 0x0000000008007180 0x8 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x0000000008007180 vClearInterruptMaskFromISR + *fill* 0x0000000008007188 0x8 + .text.PendSV_Handler + 0x0000000008007190 0x48 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x0000000008007190 PendSV_Handler + .text.xPortSysTickHandler + 0x00000000080071d8 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x00000000080071d8 xPortSysTickHandler + .text.vPortSuppressTicksAndSleep + 0x000000000800720c 0x18c ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x000000000800720c vPortSuppressTicksAndSleep + .text.prvSetupTimerInterrupt + 0x0000000008007398 0x80 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .text.pvPortMalloc + 0x0000000008007418 0x14c ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x0000000008007418 pvPortMalloc + .text.vPortFree + 0x0000000008007564 0x90 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x0000000008007564 vPortFree + .text.prvHeapInit + 0x00000000080075f4 0xc0 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.prvInsertBlockIntoFreeList + 0x00000000080076b4 0xb0 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.__libc_init_array + 0x0000000008007764 0x48 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + 0x0000000008007764 __libc_init_array + .text.memcpy 0x00000000080077ac 0x12 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + 0x00000000080077ac memcpy + .text.memset 0x00000000080077be 0x10 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + 0x00000000080077be memset + *(.glue_7) + .glue_7 0x00000000080077ce 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x00000000080077ce 0x0 linker stubs + *(.eh_frame) + *fill* 0x00000000080077ce 0x2 + .eh_frame 0x00000000080077d0 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + *(.init) + .init 0x00000000080077d0 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + 0x00000000080077d0 _init + .init 0x00000000080077d4 0x8 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + *(.fini) + .fini 0x00000000080077dc 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + 0x00000000080077dc _fini + .fini 0x00000000080077e0 0x8 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + 0x00000000080077e8 . = ALIGN (0x4) + 0x00000000080077e8 _etext = . + +.vfp11_veneer 0x00000000080077e8 0x0 + .vfp11_veneer 0x00000000080077e8 0x0 linker stubs + +.v4_bx 0x00000000080077e8 0x0 + .v4_bx 0x00000000080077e8 0x0 linker stubs + +.iplt 0x00000000080077e8 0x0 + .iplt 0x00000000080077e8 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + +.rodata 0x00000000080077e8 0x130 + 0x00000000080077e8 . = ALIGN (0x4) + *(.rodata) + .rodata 0x00000000080077e8 0xf ./Core/Src/leds.o + *fill* 0x00000000080077f7 0x1 + .rodata 0x00000000080077f8 0xc ./Core/Src/main.o + .rodata 0x0000000008007804 0x5 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + *fill* 0x0000000008007809 0x3 + .rodata 0x000000000800780c 0xd ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + *(.rodata*) + *fill* 0x0000000008007819 0x3 + .rodata.LEDS_AnimationThread + 0x000000000800781c 0x44 ./Core/Src/leds.o + .rodata.defaultTask_attributes + 0x0000000008007860 0x24 ./Core/Src/main.o + 0x0000000008007860 defaultTask_attributes + .rodata.AHBPrescTable + 0x0000000008007884 0x10 ./Core/Src/system_stm32l0xx.o + 0x0000000008007884 AHBPrescTable + .rodata.APBPrescTable + 0x0000000008007894 0x8 ./Core/Src/system_stm32l0xx.o + 0x0000000008007894 APBPrescTable + .rodata.PLLMulTable + 0x000000000800789c 0x9 ./Core/Src/system_stm32l0xx.o + 0x000000000800789c PLLMulTable + *fill* 0x00000000080078a5 0x3 + .rodata.UART_SetConfig + 0x00000000080078a8 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .rodata.prvProcessReceivedCommands + 0x00000000080078f0 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + 0x0000000008007918 . = ALIGN (0x4) + +.ARM.extab 0x0000000008007918 0x0 + 0x0000000008007918 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0000000008007918 . = ALIGN (0x4) + +.ARM 0x0000000008007918 0x8 + 0x0000000008007918 . = ALIGN (0x4) + 0x0000000008007918 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x0000000008007918 0x8 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + 0x0000000008007920 __exidx_end = . + 0x0000000008007920 . = ALIGN (0x4) + +.rel.dyn 0x0000000008007920 0x0 + .rel.iplt 0x0000000008007920 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + +.preinit_array 0x0000000008007920 0x0 + 0x0000000008007920 . = ALIGN (0x4) + 0x0000000008007920 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x0000000008007920 PROVIDE (__preinit_array_end = .) + 0x0000000008007920 . = ALIGN (0x4) + +.init_array 0x0000000008007920 0x4 + 0x0000000008007920 . = ALIGN (0x4) + 0x0000000008007920 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x0000000008007920 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + 0x0000000008007924 PROVIDE (__init_array_end = .) + 0x0000000008007924 . = ALIGN (0x4) + +.fini_array 0x0000000008007924 0x4 + 0x0000000008007924 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0000000008007924 0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x0000000008007928 . = ALIGN (0x4) + 0x0000000008007928 _sidata = LOADADDR (.data) + +.data 0x0000000020000000 0x10 load address 0x0000000008007928 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x0000000020000000 0x4 ./Core/Src/system_stm32l0xx.o + 0x0000000020000000 SystemCoreClock + .data.uwTickPrio + 0x0000000020000004 0x4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000020000004 uwTickPrio + .data.uwTickFreq + 0x0000000020000008 0x1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000020000008 uwTickFreq + *fill* 0x0000000020000009 0x3 + .data.uxCriticalNesting + 0x000000002000000c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + *(.RamFunc) + *(.RamFunc*) + 0x0000000020000010 . = ALIGN (0x4) + 0x0000000020000010 _edata = . + +.igot.plt 0x0000000020000010 0x0 load address 0x0000000008007938 + .igot.plt 0x0000000020000010 0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + 0x0000000020000010 . = ALIGN (0x4) + +.bss 0x0000000020000010 0x199c load address 0x0000000008007938 + 0x0000000020000010 _sbss = . + 0x0000000020000010 __bss_start__ = _sbss + *(.bss) + .bss 0x0000000020000010 0x1c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + *(.bss*) + .bss.xHandleLeds + 0x000000002000002c 0x4 ./Core/Src/leds.o + 0x000000002000002c xHandleLeds + .bss.KernelState + 0x0000000020000030 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .bss.Idle_TCB 0x0000000020000034 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .bss.Idle_Stack + 0x0000000020000090 0x200 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .bss.Timer_TCB + 0x0000000020000290 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .bss.Timer_Stack + 0x00000000200002ec 0x400 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .bss.pxCurrentTCB + 0x00000000200006ec 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x00000000200006ec pxCurrentTCB + .bss.pxReadyTasksLists + 0x00000000200006f0 0x460 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xDelayedTaskList1 + 0x0000000020000b50 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xDelayedTaskList2 + 0x0000000020000b64 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.pxDelayedTaskList + 0x0000000020000b78 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.pxOverflowDelayedTaskList + 0x0000000020000b7c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xPendingReadyList + 0x0000000020000b80 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xTasksWaitingTermination + 0x0000000020000b94 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxDeletedTasksWaitingCleanUp + 0x0000000020000ba8 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xSuspendedTaskList + 0x0000000020000bac 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxCurrentNumberOfTasks + 0x0000000020000bc0 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xTickCount + 0x0000000020000bc4 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxTopReadyPriority + 0x0000000020000bc8 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xSchedulerRunning + 0x0000000020000bcc 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxPendedTicks + 0x0000000020000bd0 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xYieldPending + 0x0000000020000bd4 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xNumOfOverflows + 0x0000000020000bd8 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxTaskNumber + 0x0000000020000bdc 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xNextTaskUnblockTime + 0x0000000020000be0 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xIdleTaskHandle + 0x0000000020000be4 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxSchedulerSuspended + 0x0000000020000be8 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xActiveTimerList1 + 0x0000000020000bec 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.xActiveTimerList2 + 0x0000000020000c00 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.pxCurrentTimerList + 0x0000000020000c14 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.pxOverflowTimerList + 0x0000000020000c18 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.xTimerQueue + 0x0000000020000c1c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.xTimerTaskHandle + 0x0000000020000c20 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.xLastTime.5532 + 0x0000000020000c24 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.ucStaticTimerQueueStorage.5583 + 0x0000000020000c28 0xa0 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.xStaticTimerQueue.5582 + 0x0000000020000cc8 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss.ulTimerCountsForOneTick + 0x0000000020000d18 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .bss.xMaximumPossibleSuppressedTicks + 0x0000000020000d1c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .bss.ulStoppedTimerCompensation + 0x0000000020000d20 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .bss.ucHeap 0x0000000020000d24 0x800 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.xStart 0x0000000020001524 0x8 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.pxEnd 0x000000002000152c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.xFreeBytesRemaining + 0x0000000020001530 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.xMinimumEverFreeBytesRemaining + 0x0000000020001534 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.xBlockAllocatedBit + 0x0000000020001538 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + *(COMMON) + COMMON 0x000000002000153c 0x1f4 ./Core/Src/leds.o + 0x000000002000153c LEDS_Animation + 0x0000000020001540 xStackLeds + 0x00000000200016d0 LEDS_AnimationAncien + 0x00000000200016d4 xTaskLeds + COMMON 0x0000000020001730 0x224 ./Core/Src/main.o + 0x0000000020001730 defaultTaskHandle + 0x0000000020001734 hlpuart1 + 0x00000000200017b8 hlptim1 + 0x00000000200017e8 hdma_lpuart1_tx + 0x0000000020001830 hdma_lpuart1_rx + 0x0000000020001878 htim2 + 0x00000000200018b8 hadc + 0x0000000020001914 htim21 + COMMON 0x0000000020001954 0x14 ./Core/Src/messages.o + 0x0000000020001954 XBEE_Mailbox + 0x0000000020001958 MOTEURS_Mailbox + 0x000000002000195c BATTERIE_Mailbox + 0x0000000020001960 SEQUENCEUR_Mailbox + 0x0000000020001964 LEDS_Mailbox + COMMON 0x0000000020001968 0x4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000020001968 uwTick + COMMON 0x000000002000196c 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x000000002000196c xQueueRegistry + 0x00000000200019ac . = ALIGN (0x4) + 0x00000000200019ac _ebss = . + 0x00000000200019ac __bss_end__ = _ebss + +._user_heap_stack + 0x00000000200019ac 0x604 load address 0x0000000008007938 + 0x00000000200019b0 . = ALIGN (0x8) + *fill* 0x00000000200019ac 0x4 + [!provide] PROVIDE (end = .) + 0x00000000200019b0 PROVIDE (_end = .) + 0x0000000020001bb0 . = (. + _Min_Heap_Size) + *fill* 0x00000000200019b0 0x200 + 0x0000000020001fb0 . = (. + _Min_Stack_Size) + *fill* 0x0000000020001bb0 0x400 + 0x0000000020001fb0 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x28 + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .ARM.attributes + 0x000000000000001e 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .ARM.attributes + 0x000000000000004a 0x2c ./Core/Src/freertos.o + .ARM.attributes + 0x0000000000000076 0x2c ./Core/Src/leds.o + .ARM.attributes + 0x00000000000000a2 0x2c ./Core/Src/main.o + .ARM.attributes + 0x00000000000000ce 0x2c ./Core/Src/messages.o + .ARM.attributes + 0x00000000000000fa 0x2c ./Core/Src/stm32l0xx_hal_msp.o + .ARM.attributes + 0x0000000000000126 0x2c ./Core/Src/stm32l0xx_it.o + .ARM.attributes + 0x0000000000000152 0x2c ./Core/Src/system_stm32l0xx.o + .ARM.attributes + 0x000000000000017e 0x22 ./Core/Startup/startup_stm32l010c6tx.o + .ARM.attributes + 0x00000000000001a0 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .ARM.attributes + 0x00000000000001cc 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .ARM.attributes + 0x00000000000001f8 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .ARM.attributes + 0x0000000000000224 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .ARM.attributes + 0x0000000000000250 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .ARM.attributes + 0x000000000000027c 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .ARM.attributes + 0x00000000000002a8 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .ARM.attributes + 0x00000000000002d4 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .ARM.attributes + 0x0000000000000300 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .ARM.attributes + 0x000000000000032c 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .ARM.attributes + 0x0000000000000358 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .ARM.attributes + 0x0000000000000384 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .ARM.attributes + 0x00000000000003b0 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .ARM.attributes + 0x00000000000003dc 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .ARM.attributes + 0x0000000000000408 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .ARM.attributes + 0x0000000000000434 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .ARM.attributes + 0x0000000000000460 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .ARM.attributes + 0x000000000000048c 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .ARM.attributes + 0x00000000000004b8 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .ARM.attributes + 0x00000000000004e4 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x0000000000000510 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + .ARM.attributes + 0x000000000000053c 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x0000000000000568 0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .ARM.attributes + 0x0000000000000586 0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x00000000000005a4 0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x00000000000005c2 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + .ARM.attributes + 0x00000000000005ee 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x000000000000061a 0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + .ARM.attributes + 0x0000000000000638 0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + .ARM.attributes + 0x0000000000000656 0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o +OUTPUT(Dumber3.elf elf32-littlearm) +LOAD linker stubs +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc.a +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a +LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a + +.debug_info 0x0000000000000000 0x1c98c + .debug_info 0x0000000000000000 0x222 ./Core/Src/freertos.o + .debug_info 0x0000000000000222 0x5c8 ./Core/Src/leds.o + .debug_info 0x00000000000007ea 0x1b91 ./Core/Src/main.o + .debug_info 0x000000000000237b 0xc27 ./Core/Src/messages.o + .debug_info 0x0000000000002fa2 0x1556 ./Core/Src/stm32l0xx_hal_msp.o + .debug_info 0x00000000000044f8 0xac5 ./Core/Src/stm32l0xx_it.o + .debug_info 0x0000000000004fbd 0x363 ./Core/Src/system_stm32l0xx.o + .debug_info 0x0000000000005320 0x22 ./Core/Startup/startup_stm32l010c6tx.o + .debug_info 0x0000000000005342 0x8a5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_info 0x0000000000005be7 0xe01 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_info 0x00000000000069e8 0x7b3 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_info 0x000000000000719b 0x834 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_info 0x00000000000079cf 0x77c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_info 0x000000000000814b 0xee5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_info 0x0000000000009030 0x98e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_info 0x00000000000099be 0x567 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_info 0x0000000000009f25 0x2a96 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_info 0x000000000000c9bb 0x7d8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_info 0x000000000000d193 0x3ca7 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_info 0x0000000000010e3a 0xdcd ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_info 0x0000000000011c07 0x35df ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_info 0x00000000000151e6 0xb82 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_info 0x0000000000015d68 0x1d2e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_info 0x0000000000017a96 0x2630 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_info 0x000000000001a0c6 0x1984 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_info 0x000000000001ba4a 0x371 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_info 0x000000000001bdbb 0xbd1 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_abbrev 0x0000000000000000 0x3b25 + .debug_abbrev 0x0000000000000000 0xf7 ./Core/Src/freertos.o + .debug_abbrev 0x00000000000000f7 0x1a0 ./Core/Src/leds.o + .debug_abbrev 0x0000000000000297 0x2f7 ./Core/Src/main.o + .debug_abbrev 0x000000000000058e 0x244 ./Core/Src/messages.o + .debug_abbrev 0x00000000000007d2 0x23c ./Core/Src/stm32l0xx_hal_msp.o + .debug_abbrev 0x0000000000000a0e 0x18e ./Core/Src/stm32l0xx_it.o + .debug_abbrev 0x0000000000000b9c 0x145 ./Core/Src/system_stm32l0xx.o + .debug_abbrev 0x0000000000000ce1 0x12 ./Core/Startup/startup_stm32l010c6tx.o + .debug_abbrev 0x0000000000000cf3 0x267 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_abbrev 0x0000000000000f5a 0x222 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_abbrev 0x000000000000117c 0x28b ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_abbrev 0x0000000000001407 0x1f0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_abbrev 0x00000000000015f7 0x1e8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_abbrev 0x00000000000017df 0x235 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_abbrev 0x0000000000001a14 0x246 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_abbrev 0x0000000000001c5a 0x1ef ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_abbrev 0x0000000000001e49 0x26f ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_abbrev 0x00000000000020b8 0x1c2 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_abbrev 0x000000000000227a 0x2c2 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_abbrev 0x000000000000253c 0x2a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_abbrev 0x00000000000027dc 0x3e9 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_abbrev 0x0000000000002bc5 0x1f7 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_abbrev 0x0000000000002dbc 0x2f1 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_abbrev 0x00000000000030ad 0x343 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_abbrev 0x00000000000033f0 0x2db ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_abbrev 0x00000000000036cb 0x1e9 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_abbrev 0x00000000000038b4 0x271 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_aranges 0x0000000000000000 0x1650 + .debug_aranges + 0x0000000000000000 0x28 ./Core/Src/freertos.o + .debug_aranges + 0x0000000000000028 0x30 ./Core/Src/leds.o + .debug_aranges + 0x0000000000000058 0x78 ./Core/Src/main.o + .debug_aranges + 0x00000000000000d0 0x38 ./Core/Src/messages.o + .debug_aranges + 0x0000000000000108 0x78 ./Core/Src/stm32l0xx_hal_msp.o + .debug_aranges + 0x0000000000000180 0x50 ./Core/Src/stm32l0xx_it.o + .debug_aranges + 0x00000000000001d0 0x28 ./Core/Src/system_stm32l0xx.o + .debug_aranges + 0x00000000000001f8 0x28 ./Core/Startup/startup_stm32l010c6tx.o + .debug_aranges + 0x0000000000000220 0x110 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_aranges + 0x0000000000000330 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_aranges + 0x0000000000000430 0xc0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_aranges + 0x00000000000004f0 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_aranges + 0x0000000000000570 0x58 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_aranges + 0x00000000000005c8 0x168 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_aranges + 0x0000000000000730 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_aranges + 0x00000000000007b0 0x58 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_aranges + 0x0000000000000808 0x3d0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_aranges + 0x0000000000000bd8 0x28 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_aranges + 0x0000000000000c00 0x228 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_aranges + 0x0000000000000e28 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_aranges + 0x0000000000000ea0 0x228 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_aranges + 0x00000000000010c8 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_aranges + 0x0000000000001108 0x158 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_aranges + 0x0000000000001260 0x228 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_aranges + 0x0000000000001488 0xe8 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_aranges + 0x0000000000001570 0x90 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_aranges + 0x0000000000001600 0x50 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_ranges 0x0000000000000000 0x14d8 + .debug_ranges 0x0000000000000000 0x18 ./Core/Src/freertos.o + .debug_ranges 0x0000000000000018 0x20 ./Core/Src/leds.o + .debug_ranges 0x0000000000000038 0x68 ./Core/Src/main.o + .debug_ranges 0x00000000000000a0 0x28 ./Core/Src/messages.o + .debug_ranges 0x00000000000000c8 0x68 ./Core/Src/stm32l0xx_hal_msp.o + .debug_ranges 0x0000000000000130 0x40 ./Core/Src/stm32l0xx_it.o + .debug_ranges 0x0000000000000170 0x18 ./Core/Src/system_stm32l0xx.o + .debug_ranges 0x0000000000000188 0x20 ./Core/Startup/startup_stm32l010c6tx.o + .debug_ranges 0x00000000000001a8 0x100 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_ranges 0x00000000000002a8 0xf0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_ranges 0x0000000000000398 0xb0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_ranges 0x0000000000000448 0x70 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_ranges 0x00000000000004b8 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_ranges 0x0000000000000500 0x158 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_ranges 0x0000000000000658 0x70 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_ranges 0x00000000000006c8 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_ranges 0x0000000000000710 0x3c0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_ranges 0x0000000000000ad0 0x18 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_ranges 0x0000000000000ae8 0x248 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_ranges 0x0000000000000d30 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_ranges 0x0000000000000d98 0x218 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_ranges 0x0000000000000fb0 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_ranges 0x0000000000000fe0 0x148 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_ranges 0x0000000000001128 0x218 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_ranges 0x0000000000001340 0xd8 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_ranges 0x0000000000001418 0x80 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_ranges 0x0000000000001498 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_macro 0x0000000000000000 0x13dc2 + .debug_macro 0x0000000000000000 0x2db ./Core/Src/freertos.o + .debug_macro 0x00000000000002db 0x174 ./Core/Src/freertos.o + .debug_macro 0x000000000000044f 0x22 ./Core/Src/freertos.o + .debug_macro 0x0000000000000471 0x8e ./Core/Src/freertos.o + .debug_macro 0x00000000000004ff 0x51 ./Core/Src/freertos.o + .debug_macro 0x0000000000000550 0x103 ./Core/Src/freertos.o + .debug_macro 0x0000000000000653 0x6a ./Core/Src/freertos.o + .debug_macro 0x00000000000006bd 0x1df ./Core/Src/freertos.o + .debug_macro 0x000000000000089c 0x140 ./Core/Src/freertos.o + .debug_macro 0x00000000000009dc 0x15a ./Core/Src/freertos.o + .debug_macro 0x0000000000000b36 0xb2 ./Core/Src/freertos.o + .debug_macro 0x0000000000000be8 0x1c ./Core/Src/freertos.o + .debug_macro 0x0000000000000c04 0x26 ./Core/Src/freertos.o + .debug_macro 0x0000000000000c2a 0x48d ./Core/Src/freertos.o + .debug_macro 0x00000000000010b7 0xb5 ./Core/Src/freertos.o + .debug_macro 0x000000000000116c 0xaa ./Core/Src/freertos.o + .debug_macro 0x0000000000001216 0x131 ./Core/Src/freertos.o + .debug_macro 0x0000000000001347 0x2e ./Core/Src/freertos.o + .debug_macro 0x0000000000001375 0x28 ./Core/Src/freertos.o + .debug_macro 0x000000000000139d 0x1c ./Core/Src/freertos.o + .debug_macro 0x00000000000013b9 0x22 ./Core/Src/freertos.o + .debug_macro 0x00000000000013db 0xb5 ./Core/Src/freertos.o + .debug_macro 0x0000000000001490 0x3ad ./Core/Src/freertos.o + .debug_macro 0x000000000000183d 0x7a29 ./Core/Src/freertos.o + .debug_macro 0x0000000000009266 0x66 ./Core/Src/freertos.o + .debug_macro 0x00000000000092cc 0x3555 ./Core/Src/freertos.o + .debug_macro 0x000000000000c821 0x5b ./Core/Src/freertos.o + .debug_macro 0x000000000000c87c 0x8a0 ./Core/Src/freertos.o + .debug_macro 0x000000000000d11c 0x42e ./Core/Src/freertos.o + .debug_macro 0x000000000000d54a 0x18a ./Core/Src/freertos.o + .debug_macro 0x000000000000d6d4 0x13f ./Core/Src/freertos.o + .debug_macro 0x000000000000d813 0xff ./Core/Src/freertos.o + .debug_macro 0x000000000000d912 0x82 ./Core/Src/freertos.o + .debug_macro 0x000000000000d994 0x24f ./Core/Src/freertos.o + .debug_macro 0x000000000000dbe3 0x28 ./Core/Src/freertos.o + .debug_macro 0x000000000000dc0b 0x4da ./Core/Src/freertos.o + .debug_macro 0x000000000000e0e5 0x6b ./Core/Src/freertos.o + .debug_macro 0x000000000000e150 0x129 ./Core/Src/freertos.o + .debug_macro 0x000000000000e279 0x1c6 ./Core/Src/freertos.o + .debug_macro 0x000000000000e43f 0x22c ./Core/Src/freertos.o + .debug_macro 0x000000000000e66b 0x5b ./Core/Src/freertos.o + .debug_macro 0x000000000000e6c6 0xa5 ./Core/Src/freertos.o + .debug_macro 0x000000000000e76b 0x25c ./Core/Src/freertos.o + .debug_macro 0x000000000000e9c7 0xb6 ./Core/Src/freertos.o + .debug_macro 0x000000000000ea7d 0x16 ./Core/Src/freertos.o + .debug_macro 0x000000000000ea93 0x773 ./Core/Src/freertos.o + .debug_macro 0x000000000000f206 0x6c ./Core/Src/freertos.o + .debug_macro 0x000000000000f272 0x5ba ./Core/Src/freertos.o + .debug_macro 0x000000000000f82c 0x44 ./Core/Src/freertos.o + .debug_macro 0x000000000000f870 0x100 ./Core/Src/freertos.o + .debug_macro 0x000000000000f970 0x6c ./Core/Src/freertos.o + .debug_macro 0x000000000000f9dc 0x74 ./Core/Src/freertos.o + .debug_macro 0x000000000000fa50 0xdd ./Core/Src/freertos.o + .debug_macro 0x000000000000fb2d 0x28 ./Core/Src/freertos.o + .debug_macro 0x000000000000fb55 0x87 ./Core/Src/freertos.o + .debug_macro 0x000000000000fbdc 0x4c ./Core/Src/freertos.o + .debug_macro 0x000000000000fc28 0xee ./Core/Src/freertos.o + .debug_macro 0x000000000000fd16 0x305 ./Core/Src/leds.o + .debug_macro 0x000000000001001b 0x66 ./Core/Src/leds.o + .debug_macro 0x0000000000010081 0x2f9 ./Core/Src/main.o + .debug_macro 0x000000000001037a 0x3b3 ./Core/Src/messages.o + .debug_macro 0x000000000001072d 0x18 ./Core/Src/messages.o + .debug_macro 0x0000000000010745 0x52 ./Core/Src/messages.o + .debug_macro 0x0000000000010797 0x3c ./Core/Src/messages.o + .debug_macro 0x00000000000107d3 0x34 ./Core/Src/messages.o + .debug_macro 0x0000000000010807 0x16 ./Core/Src/messages.o + .debug_macro 0x000000000001081d 0x35 ./Core/Src/messages.o + .debug_macro 0x0000000000010852 0x16 ./Core/Src/messages.o + .debug_macro 0x0000000000010868 0x43 ./Core/Src/messages.o + .debug_macro 0x00000000000108ab 0x34 ./Core/Src/messages.o + .debug_macro 0x00000000000108df 0x10 ./Core/Src/messages.o + .debug_macro 0x00000000000108ef 0x58 ./Core/Src/messages.o + .debug_macro 0x0000000000010947 0x71 ./Core/Src/messages.o + .debug_macro 0x00000000000109b8 0x1c ./Core/Src/messages.o + .debug_macro 0x00000000000109d4 0x12a ./Core/Src/messages.o + .debug_macro 0x0000000000010afe 0x333 ./Core/Src/messages.o + .debug_macro 0x0000000000010e31 0x16 ./Core/Src/messages.o + .debug_macro 0x0000000000010e47 0x29 ./Core/Src/messages.o + .debug_macro 0x0000000000010e70 0x2e1 ./Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000011151 0x2eb ./Core/Src/stm32l0xx_it.o + .debug_macro 0x000000000001143c 0x1e1 ./Core/Src/system_stm32l0xx.o + .debug_macro 0x000000000001161d 0x205 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000011822 0x1f0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_macro 0x0000000000011a12 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000011bf3 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000011dd4 0x1e8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000011fbc 0x1e9 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_macro 0x00000000000121a5 0x205 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x00000000000123aa 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x000000000001258b 0x1e2 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x000000000001276d 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x000000000001294e 0x20c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_macro 0x0000000000012b5a 0x1e1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_macro 0x0000000000012d3b 0x247 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000012f82 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000012f92 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000012fb2 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000012fc2 0xa9 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x000000000001306b 0x91 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x00000000000130fc 0x8d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000013189 0x9a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000013223 0x187 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x00000000000133aa 0x216 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x00000000000135c0 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x00000000000135d6 0x27f ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000013855 0x10 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000013865 0x1dc ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000013a41 0x97 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000013ad8 0x13c ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_macro 0x0000000000013c14 0x1ae ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_line 0x0000000000000000 0x19121 + .debug_line 0x0000000000000000 0x8d2 ./Core/Src/freertos.o + .debug_line 0x00000000000008d2 0xa45 ./Core/Src/leds.o + .debug_line 0x0000000000001317 0xbe5 ./Core/Src/main.o + .debug_line 0x0000000000001efc 0xa97 ./Core/Src/messages.o + .debug_line 0x0000000000002993 0xaeb ./Core/Src/stm32l0xx_hal_msp.o + .debug_line 0x000000000000347e 0x978 ./Core/Src/stm32l0xx_it.o + .debug_line 0x0000000000003df6 0x7c4 ./Core/Src/system_stm32l0xx.o + .debug_line 0x00000000000045ba 0x9b ./Core/Startup/startup_stm32l010c6tx.o + .debug_line 0x0000000000004655 0xa67 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_line 0x00000000000050bc 0x1143 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_line 0x00000000000061ff 0xa3e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_line 0x0000000000006c3d 0xc56 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_line 0x0000000000007893 0xae3 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_line 0x0000000000008376 0x1107 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_line 0x000000000000947d 0xe9e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_line 0x000000000000a31b 0xa87 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_line 0x000000000000ada2 0x2ea4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_line 0x000000000000dc46 0x7da ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_line 0x000000000000e420 0x2d82 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_line 0x00000000000111a2 0xcde ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_line 0x0000000000011e80 0x201e ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_line 0x0000000000013e9e 0x6dd ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_line 0x000000000001457b 0x13ed ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_line 0x0000000000015968 0x1bf4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_line 0x000000000001755c 0xbea ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_line 0x0000000000018146 0x774 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_line 0x00000000000188ba 0x867 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_str 0x0000000000000000 0x7a4cb + .debug_str 0x0000000000000000 0x6df91 ./Core/Src/freertos.o + 0x6e2b7 (size before relaxing) + .debug_str 0x000000000006df91 0x4ae ./Core/Src/leds.o + 0x6e749 (size before relaxing) + .debug_str 0x000000000006e43f 0x13bd ./Core/Src/main.o + 0x6f971 (size before relaxing) + .debug_str 0x000000000006f7fc 0x327e ./Core/Src/messages.o + 0x715bd (size before relaxing) + .debug_str 0x0000000000072a7a 0x133 ./Core/Src/stm32l0xx_hal_msp.o + 0x6f074 (size before relaxing) + .debug_str 0x0000000000072bad 0x89 ./Core/Src/stm32l0xx_it.o + 0x6e947 (size before relaxing) + .debug_str 0x0000000000072c36 0x61 ./Core/Src/system_stm32l0xx.o + 0x68e0a (size before relaxing) + .debug_str 0x0000000000072c97 0x36 ./Core/Startup/startup_stm32l010c6tx.o + 0x6f (size before relaxing) + .debug_str 0x0000000000072ccd 0x3f8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x6941c (size before relaxing) + .debug_str 0x00000000000730c5 0x33e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + 0x694f5 (size before relaxing) + .debug_str 0x0000000000073403 0x1d8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + 0x69134 (size before relaxing) + .debug_str 0x00000000000735db 0x267 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + 0x691bc (size before relaxing) + .debug_str 0x0000000000073842 0x137 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + 0x68ff4 (size before relaxing) + .debug_str 0x0000000000073979 0x460 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + 0x6948c (size before relaxing) + .debug_str 0x0000000000073dd9 0x284 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x69280 (size before relaxing) + .debug_str 0x000000000007405d 0x13a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + 0x6900d (size before relaxing) + .debug_str 0x0000000000074197 0xc98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + 0x6a0fa (size before relaxing) + .debug_str 0x0000000000074e2f 0x7d ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + 0x692d1 (size before relaxing) + .debug_str 0x0000000000074eac 0x8c3 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + 0x69b31 (size before relaxing) + .debug_str 0x000000000007576f 0x1dd ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + 0x693cb (size before relaxing) + .debug_str 0x000000000007594c 0x1fa8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0xe0bd (size before relaxing) + .debug_str 0x00000000000778f4 0x12d ./Middlewares/Third_Party/FreeRTOS/Source/list.o + 0xa76f (size before relaxing) + .debug_str 0x0000000000077a21 0x91c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0xc06f (size before relaxing) + .debug_str 0x000000000007833d 0x13af ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0xccff (size before relaxing) + .debug_str 0x00000000000796ec 0x60b ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + 0xc636 (size before relaxing) + .debug_str 0x0000000000079cf7 0x583 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + 0x8012 (size before relaxing) + .debug_str 0x000000000007a27a 0x251 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0xaf43 (size before relaxing) + +.comment 0x0000000000000000 0x53 + .comment 0x0000000000000000 0x53 ./Core/Src/freertos.o + 0x54 (size before relaxing) + .comment 0x0000000000000053 0x54 ./Core/Src/leds.o + .comment 0x0000000000000053 0x54 ./Core/Src/main.o + .comment 0x0000000000000053 0x54 ./Core/Src/messages.o + .comment 0x0000000000000053 0x54 ./Core/Src/stm32l0xx_hal_msp.o + .comment 0x0000000000000053 0x54 ./Core/Src/stm32l0xx_it.o + .comment 0x0000000000000053 0x54 ./Core/Src/system_stm32l0xx.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .comment 0x0000000000000053 0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .comment 0x0000000000000053 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .comment 0x0000000000000053 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .comment 0x0000000000000053 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .comment 0x0000000000000053 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .comment 0x0000000000000053 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .comment 0x0000000000000053 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .comment 0x0000000000000053 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_frame 0x0000000000000000 0x5064 + .debug_frame 0x0000000000000000 0x50 ./Core/Src/freertos.o + .debug_frame 0x0000000000000050 0x74 ./Core/Src/leds.o + .debug_frame 0x00000000000000c4 0x180 ./Core/Src/main.o + .debug_frame 0x0000000000000244 0x8c ./Core/Src/messages.o + .debug_frame 0x00000000000002d0 0x18c ./Core/Src/stm32l0xx_hal_msp.o + .debug_frame 0x000000000000045c 0xd4 ./Core/Src/stm32l0xx_it.o + .debug_frame 0x0000000000000530 0x4c ./Core/Src/system_stm32l0xx.o + .debug_frame 0x000000000000057c 0x394 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_frame 0x0000000000000910 0x3c0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o + .debug_frame 0x0000000000000cd0 0x2a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_frame 0x0000000000000f70 0x1b0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_frame 0x0000000000001120 0x110 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_frame 0x0000000000001230 0x550 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o + .debug_frame 0x0000000000001780 0x1a8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_frame 0x0000000000001928 0xfc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_frame 0x0000000000001a24 0xef8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_frame 0x000000000000291c 0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_frame 0x000000000000296c 0x854 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o + .debug_frame 0x00000000000031c0 0x198 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o + .debug_frame 0x0000000000003358 0x848 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_frame 0x0000000000003ba0 0xb0 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_frame 0x0000000000003c50 0x510 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_frame 0x0000000000004160 0x83c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_frame 0x000000000000499c 0x34c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_frame 0x0000000000004ce8 0x194 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + .debug_frame 0x0000000000004e7c 0xe4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_frame 0x0000000000004f60 0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .debug_frame 0x0000000000004f8c 0x28 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + .debug_frame 0x0000000000004fb4 0x20 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .debug_frame 0x0000000000004fd4 0x20 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .debug_frame 0x0000000000004ff4 0x34 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + .debug_frame 0x0000000000005028 0x3c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su new file mode 100644 index 0000000..2e82ff7 --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su @@ -0,0 +1,66 @@ +cmsis_os2.c:168:22:SVC_Setup 8 static +cmsis_os2.c:185:12:osKernelInitialize 24 static,ignoring_inline_asm +cmsis_os2.c:206:12:osKernelGetInfo 24 static +cmsis_os2.c:224:17:osKernelGetState 16 static +cmsis_os2.c:249:12:osKernelStart 24 static,ignoring_inline_asm +cmsis_os2.c:272:9:osKernelLock 24 static,ignoring_inline_asm +cmsis_os2.c:299:9:osKernelUnlock 24 static,ignoring_inline_asm +cmsis_os2.c:331:9:osKernelRestoreLock 24 static,ignoring_inline_asm +cmsis_os2.c:367:10:osKernelGetTickCount 24 static,ignoring_inline_asm +cmsis_os2.c:379:10:osKernelGetTickFreq 8 static +cmsis_os2.c:383:10:osKernelGetSysTimerCount 24 static,ignoring_inline_asm +cmsis_os2.c:400:10:osKernelGetSysTimerFreq 8 static +cmsis_os2.c:406:14:osThreadNew 80 static,ignoring_inline_asm +cmsis_os2.c:470:13:osThreadGetName 32 static,ignoring_inline_asm +cmsis_os2.c:483:14:osThreadGetId 16 static +cmsis_os2.c:491:17:osThreadGetState 32 static,ignoring_inline_asm +cmsis_os2.c:513:10:osThreadGetStackSpace 32 static,ignoring_inline_asm +cmsis_os2.c:526:12:osThreadSetPriority 32 static,ignoring_inline_asm +cmsis_os2.c:544:14:osThreadGetPriority 32 static,ignoring_inline_asm +cmsis_os2.c:557:12:osThreadYield 24 static,ignoring_inline_asm +cmsis_os2.c:570:12:osThreadSuspend 32 static,ignoring_inline_asm +cmsis_os2.c:588:12:osThreadResume 32 static,ignoring_inline_asm +cmsis_os2.c:606:18:osThreadExit 8 static +cmsis_os2.c:613:12:osThreadTerminate 48 static,ignoring_inline_asm +cmsis_os2.c:642:10:osThreadGetCount 24 static,ignoring_inline_asm +cmsis_os2.c:654:10:osThreadEnumerate 40 static,ignoring_inline_asm +cmsis_os2.c:682:10:osThreadFlagsSet 48 static,ignoring_inline_asm +cmsis_os2.c:710:10:osThreadFlagsClear 40 static,ignoring_inline_asm +cmsis_os2.c:740:10:osThreadFlagsGet 24 static,ignoring_inline_asm +cmsis_os2.c:758:10:osThreadFlagsWait 64 static,ignoring_inline_asm +cmsis_os2.c:833:12:osDelay 32 static,ignoring_inline_asm +cmsis_os2.c:850:12:osDelayUntil 40 static,ignoring_inline_asm +cmsis_os2.c:880:13:TimerCallback 24 static +cmsis_os2.c:890:13:osTimerNew 64 static,ignoring_inline_asm +cmsis_os2.c:948:13:osTimerGetName 32 static,ignoring_inline_asm +cmsis_os2.c:961:12:osTimerStart 40 static,ignoring_inline_asm +cmsis_os2.c:982:12:osTimerStop 40 static,ignoring_inline_asm +cmsis_os2.c:1008:10:osTimerIsRunning 32 static,ignoring_inline_asm +cmsis_os2.c:1021:12:osTimerDelete 48 static,ignoring_inline_asm +cmsis_os2.c:1052:18:osEventFlagsNew 32 static,ignoring_inline_asm +cmsis_os2.c:1088:10:osEventFlagsSet 40 static,ignoring_inline_asm +cmsis_os2.c:1113:10:osEventFlagsClear 32 static,ignoring_inline_asm +cmsis_os2.c:1134:10:osEventFlagsGet 32 static,ignoring_inline_asm +cmsis_os2.c:1151:10:osEventFlagsWait 64 static,ignoring_inline_asm +cmsis_os2.c:1201:12:osEventFlagsDelete 32 static,ignoring_inline_asm +cmsis_os2.c:1225:13:osMutexNew 48 static,ignoring_inline_asm +cmsis_os2.c:1304:12:osMutexAcquire 40 static,ignoring_inline_asm +cmsis_os2.c:1345:12:osMutexRelease 40 static,ignoring_inline_asm +cmsis_os2.c:1378:14:osMutexGetOwner 32 static,ignoring_inline_asm +cmsis_os2.c:1393:12:osMutexDelete 32 static,ignoring_inline_asm +cmsis_os2.c:1422:17:osSemaphoreNew 56 static,ignoring_inline_asm +cmsis_os2.c:1489:12:osSemaphoreAcquire 40 static,ignoring_inline_asm +cmsis_os2.c:1526:12:osSemaphoreRelease 40 static,ignoring_inline_asm +cmsis_os2.c:1554:10:osSemaphoreGetCount 32 static,ignoring_inline_asm +cmsis_os2.c:1570:12:osSemaphoreDelete 32 static,ignoring_inline_asm +cmsis_os2.c:1598:20:osMessageQueueNew 64 static,ignoring_inline_asm +cmsis_os2.c:1651:12:osMessageQueuePut 48 static,ignoring_inline_asm +cmsis_os2.c:1692:12:osMessageQueueGet 48 static,ignoring_inline_asm +cmsis_os2.c:1733:10:osMessageQueueGetCapacity 24 static +cmsis_os2.c:1747:10:osMessageQueueGetMsgSize 24 static +cmsis_os2.c:1761:10:osMessageQueueGetCount 32 static,ignoring_inline_asm +cmsis_os2.c:1778:10:osMessageQueueGetSpace 40 static,ignoring_inline_asm +cmsis_os2.c:1801:12:osMessageQueueReset 32 static,ignoring_inline_asm +cmsis_os2.c:1819:12:osMessageQueueDelete 32 static,ignoring_inline_asm +cmsis_os2.c:1910:6:vApplicationGetIdleTaskMemory 24 static +cmsis_os2.c:1920:6:vApplicationGetTimerTaskMemory 24 static diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk new file mode 100644 index 0000000..c277b0a --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su new file mode 100644 index 0000000..e69de29 diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su new file mode 100644 index 0000000..cada37b --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su @@ -0,0 +1,15 @@ +event_groups.c:93:21:xEventGroupCreateStatic 24 static,ignoring_inline_asm +event_groups.c:145:21:xEventGroupCreate 16 static +event_groups.c:191:13:xEventGroupSync 48 static,ignoring_inline_asm +event_groups.c:311:13:xEventGroupWaitBits 56 static,ignoring_inline_asm +event_groups.c:461:13:xEventGroupClearBits 24 static,ignoring_inline_asm +event_groups.c:490:13:xEventGroupClearBitsFromISR 24 static +event_groups.c:503:13:xEventGroupGetBitsFromISR 32 static +event_groups.c:519:13:xEventGroupSetBits 56 static,ignoring_inline_asm +event_groups.c:613:6:vEventGroupDelete 24 static,ignoring_inline_asm +event_groups.c:657:6:vEventGroupSetBitsCallback 16 static +event_groups.c:665:6:vEventGroupClearBitsCallback 16 static +event_groups.c:671:19:prvTestWaitCondition 32 static +event_groups.c:708:13:xEventGroupSetBitsFromISR 32 static +event_groups.c:723:14:uxEventGroupGetNumber 24 static +event_groups.c:745:7:vEventGroupSetNumber 16 static diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su new file mode 100644 index 0000000..e840c82 --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su @@ -0,0 +1,5 @@ +list.c:37:6:vListInitialise 16 static +list.c:62:6:vListInitialiseItem 16 static +list.c:74:6:vListInsertEnd 24 static +list.c:103:6:vListInsert 24 static +list.c:170:13:uxListRemove 24 static diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.su new file mode 100644 index 0000000..54cd2bd --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.su @@ -0,0 +1,15 @@ +port.c:133:14:pxPortInitialiseStack 24 static +port.c:151:13:prvTaskExitError 16 static,ignoring_inline_asm +port.c:176:6:SVC_Handler 8 static +port.c:183:6:vPortStartFirstTask 0 static,ignoring_inline_asm +port.c:214:12:xPortStartScheduler 8 static +port.c:244:6:vPortEndScheduler 8 static,ignoring_inline_asm +port.c:252:6:vPortYield 8 static,ignoring_inline_asm +port.c:264:6:vPortEnterCritical 8 static,ignoring_inline_asm +port.c:273:6:vPortExitCritical 8 static,ignoring_inline_asm +port.c:284:10:ulSetInterruptMaskFromISR 0 static,ignoring_inline_asm +port.c:302:6:vClearInterruptMaskFromISR 0 static,ignoring_inline_asm +port.c:319:6:PendSV_Handler 0 static,ignoring_inline_asm +port.c:368:6:xPortSysTickHandler 16 static +port.c:387:29:vPortSuppressTicksAndSleep 40 static,ignoring_inline_asm +port.c:541:6:prvSetupTimerInterrupt 8 static diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk new file mode 100644 index 0000000..ef52c34 --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/%.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su new file mode 100644 index 0000000..34bb535 --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su @@ -0,0 +1,7 @@ +heap_4.c:113:7:pvPortMalloc 32 static,ignoring_inline_asm +heap_4.c:263:6:vPortFree 24 static,ignoring_inline_asm +heap_4.c:311:8:xPortGetFreeHeapSize 8 static +heap_4.c:317:8:xPortGetMinimumEverFreeHeapSize 8 static +heap_4.c:323:6:vPortInitialiseBlocks 8 static +heap_4.c:329:13:prvHeapInit 24 static +heap_4.c:377:13:prvInsertBlockIntoFreeList 24 static diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk new file mode 100644 index 0000000..407be28 --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su new file mode 100644 index 0000000..9df0fdc --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su @@ -0,0 +1,40 @@ +queue.c:255:12:xQueueGenericReset 24 static,ignoring_inline_asm +queue.c:310:16:xQueueGenericCreateStatic 48 static,ignoring_inline_asm +queue.c:368:16:xQueueGenericCreate 56 static,ignoring_inline_asm +queue.c:429:13:prvInitialiseNewQueue 24 static +queue.c:473:14:prvInitialiseMutex 16 static +queue.c:503:16:xQueueCreateMutex 32 static +queue.c:519:16:xQueueCreateMutexStatic 40 static +queue.c:539:15:xQueueGetMutexHolder 24 static +queue.c:570:15:xQueueGetMutexHolderFromISR 24 static,ignoring_inline_asm +queue.c:596:13:xQueueGiveMutexRecursive 32 static,ignoring_inline_asm +queue.c:651:13:xQueueTakeMutexRecursive 32 static,ignoring_inline_asm +queue.c:693:16:xQueueCreateCountingSemaphoreStatic 40 static,ignoring_inline_asm +queue.c:721:16:xQueueCreateCountingSemaphore 24 static,ignoring_inline_asm +queue.c:747:12:xQueueGenericSend 48 static,ignoring_inline_asm +queue.c:957:12:xQueueGenericSendFromISR 48 static,ignoring_inline_asm +queue.c:1108:12:xQueueGiveFromISR 40 static,ignoring_inline_asm +queue.c:1273:12:xQueueReceive 48 static,ignoring_inline_asm +queue.c:1414:12:xQueueSemaphoreTake 48 static,ignoring_inline_asm +queue.c:1632:12:xQueuePeek 48 static,ignoring_inline_asm +queue.c:1781:12:xQueueReceiveFromISR 56 static,ignoring_inline_asm +queue.c:1872:12:xQueuePeekFromISR 32 static,ignoring_inline_asm +queue.c:1926:13:uxQueueMessagesWaiting 24 static,ignoring_inline_asm +queue.c:1942:13:uxQueueSpacesAvailable 24 static,ignoring_inline_asm +queue.c:1959:13:uxQueueMessagesWaitingFromISR 24 static,ignoring_inline_asm +queue.c:1971:6:vQueueDelete 24 static,ignoring_inline_asm +queue.c:2015:14:uxQueueGetQueueNumber 16 static +queue.c:2025:7:vQueueSetQueueNumber 16 static +queue.c:2035:10:ucQueueGetQueueType 16 static +queue.c:2045:21:prvGetDisinheritPriorityAfterTimeout 24 static +queue.c:2070:19:prvCopyDataToQueue 32 static +queue.c:2149:13:prvCopyDataFromQueue 16 static +queue.c:2167:13:prvUnlockQueue 24 static +queue.c:2287:19:prvIsQueueEmpty 24 static +queue.c:2308:12:xQueueIsQueueEmptyFromISR 24 static,ignoring_inline_asm +queue.c:2327:19:prvIsQueueFull 24 static +queue.c:2348:12:xQueueIsQueueFullFromISR 24 static,ignoring_inline_asm +queue.c:2644:7:vQueueAddToRegistry 24 static +queue.c:2673:14:pcQueueGetName 24 static +queue.c:2701:7:vQueueUnregisterQueue 24 static +queue.c:2733:7:vQueueWaitForMessageRestricted 32 static diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su new file mode 100644 index 0000000..cb2f2ed --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su @@ -0,0 +1,25 @@ +stream_buffer.c:219:23:xStreamBufferGenericCreate 48 static,ignoring_inline_asm +stream_buffer.c:283:23:xStreamBufferGenericCreateStatic 56 static,ignoring_inline_asm +stream_buffer.c:359:6:vStreamBufferDelete 24 static,ignoring_inline_asm +stream_buffer.c:392:12:xStreamBufferReset 48 static,ignoring_inline_asm +stream_buffer.c:441:12:xStreamBufferSetTriggerLevel 24 static,ignoring_inline_asm +stream_buffer.c:470:8:xStreamBufferSpacesAvailable 24 static,ignoring_inline_asm +stream_buffer.c:494:8:xStreamBufferBytesAvailable 24 static,ignoring_inline_asm +stream_buffer.c:506:8:xStreamBufferSend 64 static,ignoring_inline_asm +stream_buffer.c:610:8:xStreamBufferSendFromISR 64 static,ignoring_inline_asm +stream_buffer.c:661:15:prvWriteMessageToBuffer 32 static +stream_buffer.c:713:8:xStreamBufferReceive 56 static,ignoring_inline_asm +stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes 40 static,ignoring_inline_asm +stream_buffer.c:861:8:xStreamBufferReceiveFromISR 64 static,ignoring_inline_asm +stream_buffer.c:918:15:prvReadMessageFromBuffer 40 static +stream_buffer.c:970:12:xStreamBufferIsEmpty 32 static,ignoring_inline_asm +stream_buffer.c:993:12:xStreamBufferIsFull 32 static,ignoring_inline_asm +stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR 40 static,ignoring_inline_asm +stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR 40 static,ignoring_inline_asm +stream_buffer.c:1088:15:prvWriteBytesToBuffer 32 static,ignoring_inline_asm +stream_buffer.c:1134:15:prvReadBytesFromBuffer 40 static,ignoring_inline_asm +stream_buffer.c:1189:15:prvBytesInBuffer 24 static +stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer 32 static,ignoring_inline_asm +stream_buffer.c:1237:14:uxStreamBufferGetStreamBufferNumber 16 static +stream_buffer.c:1247:7:vStreamBufferSetStreamBufferNumber 16 static +stream_buffer.c:1257:10:ucStreamBufferGetStreamBufferType 16 static diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk new file mode 100644 index 0000000..83df1cc --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk @@ -0,0 +1,38 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ +../Middlewares/Third_Party/FreeRTOS/Source/list.c \ +../Middlewares/Third_Party/FreeRTOS/Source/queue.c \ +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \ +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ +../Middlewares/Third_Party/FreeRTOS/Source/timers.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.o \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o \ +./Middlewares/Third_Party/FreeRTOS/Source/list.o \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.o \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.o \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.d \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d \ +./Middlewares/Third_Party/FreeRTOS/Source/list.d \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.d \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.d \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/%.o: ../Middlewares/Third_Party/FreeRTOS/Source/%.c Middlewares/Third_Party/FreeRTOS/Source/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su new file mode 100644 index 0000000..5422d3b --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su @@ -0,0 +1,66 @@ +tasks.c:578:15:xTaskCreateStatic 64 static,ignoring_inline_asm +tasks.c:730:13:xTaskCreate 64 static +tasks.c:821:13:prvInitialiseNewTask 32 static,ignoring_inline_asm +tasks.c:1072:13:prvAddNewTaskToReadyList 16 static +tasks.c:1157:7:vTaskDelete 24 static,ignoring_inline_asm +tasks.c:1249:7:vTaskDelayUntil 32 static,ignoring_inline_asm +tasks.c:1333:7:vTaskDelay 24 static,ignoring_inline_asm +tasks.c:1378:13:eTaskGetState 40 static,ignoring_inline_asm +tasks.c:1470:14:uxTaskPriorityGet 24 static +tasks.c:1492:14:uxTaskPriorityGetFromISR 32 static +tasks.c:1532:7:vTaskPrioritySet 32 static,ignoring_inline_asm +tasks.c:1696:7:vTaskSuspend 24 static,ignoring_inline_asm +tasks.c:1797:20:prvTaskIsTaskSuspended 24 static,ignoring_inline_asm +tasks.c:1843:7:vTaskResume 24 static,ignoring_inline_asm +tasks.c:1897:13:xTaskResumeFromISR 32 static,ignoring_inline_asm +tasks.c:1967:6:vTaskStartScheduler 48 static,ignoring_inline_asm +tasks.c:2089:6:vTaskEndScheduler 8 static,ignoring_inline_asm +tasks.c:2100:6:vTaskSuspendAll 8 static,ignoring_inline_asm +tasks.c:2113:20:prvGetExpectedIdleTime 16 static +tasks.c:2174:12:xTaskResumeAll 24 static,ignoring_inline_asm +tasks.c:2284:12:xTaskGetTickCount 16 static +tasks.c:2299:12:xTaskGetTickCountFromISR 16 static +tasks.c:2330:13:uxTaskGetNumberOfTasks 8 static +tasks.c:2338:7:pcTaskGetName 24 static,ignoring_inline_asm +tasks.c:2352:16:prvSearchForNameWithinSingleList 56 static +tasks.c:2420:15:xTaskGetHandle 24 static,ignoring_inline_asm +tasks.c:2485:14:uxTaskGetSystemState 32 static +tasks.c:2576:7:vTaskStepTick 16 static,ignoring_inline_asm +tasks.c:2591:13:xTaskAbortDelay 24 static,ignoring_inline_asm +tasks.c:2665:12:xTaskIncrementTick 32 static,ignoring_inline_asm +tasks.c:2947:6:vTaskSwitchContext 16 static,ignoring_inline_asm +tasks.c:3020:6:vTaskPlaceOnEventList 16 static,ignoring_inline_asm +tasks.c:3037:6:vTaskPlaceOnUnorderedEventList 24 static,ignoring_inline_asm +tasks.c:3063:7:vTaskPlaceOnEventListRestricted 24 static,ignoring_inline_asm +tasks.c:3094:12:xTaskRemoveFromEventList 24 static,ignoring_inline_asm +tasks.c:3162:6:vTaskRemoveFromUnorderedEventList 24 static,ignoring_inline_asm +tasks.c:3196:6:vTaskSetTimeOutState 16 static,ignoring_inline_asm +tasks.c:3208:6:vTaskInternalSetTimeOutState 16 static +tasks.c:3216:12:xTaskCheckForTimeOut 32 static,ignoring_inline_asm +tasks.c:3279:6:vTaskMissedYield 8 static +tasks.c:3287:14:uxTaskGetTaskNumber 24 static +tasks.c:3310:7:vTaskSetTaskNumber 24 static +tasks.c:3334:8:prvIdleTask 24 static,ignoring_inline_asm +tasks.c:3453:19:eTaskConfirmSleepModeStatus 16 static +tasks.c:3546:13:prvInitialiseTaskLists 16 static +tasks.c:3578:13:prvCheckTasksWaitingTermination 16 static +tasks.c:3609:7:vTaskGetInfo 32 static +tasks.c:3705:21:prvListTasksWithinSingleList 48 static +tasks.c:3738:32:prvTaskCheckFreeStackSpace 24 static +tasks.c:3798:14:uxTaskGetStackHighWaterMark 32 static +tasks.c:3826:14:prvDeleteTCB 16 static,ignoring_inline_asm +tasks.c:3880:13:prvResetNextTaskUnblockTime 16 static +tasks.c:3906:15:xTaskGetCurrentTaskHandle 16 static +tasks.c:3923:13:xTaskGetSchedulerState 16 static +tasks.c:3951:13:xTaskPriorityInherit 24 static +tasks.c:4038:13:xTaskPriorityDisinherit 24 static,ignoring_inline_asm +tasks.c:4118:7:vTaskPriorityDisinheritAfterTimeout 32 static,ignoring_inline_asm +tasks.c:4533:12:uxTaskResetEventItemValue 16 static +tasks.c:4549:15:pvTaskIncrementMutexHeldCount 8 static +tasks.c:4566:11:ulTaskNotifyTake 24 static +tasks.c:4634:13:xTaskNotifyWait 32 static +tasks.c:4714:13:xTaskGenericNotify 40 static,ignoring_inline_asm +tasks.c:4828:13:xTaskGenericNotifyFromISR 40 static,ignoring_inline_asm +tasks.c:4957:7:vTaskNotifyGiveFromISR 32 static,ignoring_inline_asm +tasks.c:5044:13:xTaskNotifyStateClear 24 static +tasks.c:5081:13:prvAddCurrentTaskToDelayedList 24 static diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su new file mode 100644 index 0000000..c32c525 --- /dev/null +++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su @@ -0,0 +1,26 @@ +timers.c:227:12:xTimerCreateTimerTask 48 static,ignoring_inline_asm +timers.c:282:16:xTimerCreate 48 static +timers.c:309:16:xTimerCreateStatic 48 static,ignoring_inline_asm +timers.c:349:13:prvInitialiseNewTimer 24 static,ignoring_inline_asm +timers.c:381:12:xTimerGenericCommand 56 static,ignoring_inline_asm +timers.c:424:14:xTimerGetTimerDaemonTaskHandle 8 static,ignoring_inline_asm +timers.c:433:12:xTimerGetPeriod 24 static,ignoring_inline_asm +timers.c:442:6:vTimerSetReloadMode 24 static,ignoring_inline_asm +timers.c:462:12:xTimerGetExpiryTime 24 static,ignoring_inline_asm +timers.c:473:14:pcTimerGetName 24 static,ignoring_inline_asm +timers.c:482:13:prvProcessExpiredTimer 32 static,ignoring_inline_asm +timers.c:523:8:prvTimerTask 24 static +timers.c:559:13:prvProcessTimerOrBlockTask 24 static +timers.c:619:19:prvGetNextExpireTime 24 static +timers.c:645:19:prvSampleTimeNow 24 static +timers.c:668:19:prvInsertTimerInActiveList 32 static +timers.c:709:13:prvProcessReceivedCommands 64 static,ignoring_inline_asm +timers.c:857:13:prvSwitchTimerLists 40 static,ignoring_inline_asm +timers.c:916:13:prvCheckForValidListAndQueue 16 static +timers.c:967:12:xTimerIsTimerActive 24 static,ignoring_inline_asm +timers.c:992:7:pvTimerGetTimerID 24 static,ignoring_inline_asm +timers.c:1009:6:vTimerSetTimerID 24 static,ignoring_inline_asm +timers.c:1025:13:xTimerPendFunctionCallFromISR 48 static +timers.c:1049:13:xTimerPendFunctionCall 48 static,ignoring_inline_asm +timers.c:1078:14:uxTimerGetTimerNumber 16 static +timers.c:1088:7:vTimerSetTimerNumber 16 static diff --git a/software/dumber3/Debug/makefile b/software/dumber3/Debug/makefile new file mode 100644 index 0000000..5bc3254 --- /dev/null +++ b/software/dumber3/Debug/makefile @@ -0,0 +1,104 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/subdir.mk +-include Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := Dumber3 +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +Dumber3.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +Dumber3.list \ + +OBJCOPY_BIN += \ +Dumber3.bin \ + + +# All Target +all: main-build + +# Main-build Target +main-build: Dumber3.elf secondary-outputs + +# Tool invocations +Dumber3.elf: $(OBJS) $(USER_OBJS) /home/dimercur/Travail/git/dumber/software/dumber3/STM32L010C6TX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "Dumber3.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0plus -T"/home/dimercur/Travail/git/dumber/software/dumber3/STM32L010C6TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="Dumber3.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +Dumber3.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "Dumber3.list" + @echo 'Finished building: $@' + @echo ' ' + +Dumber3.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "Dumber3.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(SIZE_OUTPUT)$(OBJDUMP_LIST)$(EXECUTABLES)$(OBJS)$(S_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(OBJCOPY_BIN) Dumber3.elf + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/software/dumber3/Debug/objects.list b/software/dumber3/Debug/objects.list new file mode 100644 index 0000000..ee00853 --- /dev/null +++ b/software/dumber3/Debug/objects.list @@ -0,0 +1,45 @@ +"./Core/Src/batterie.o" +"./Core/Src/freertos.o" +"./Core/Src/leds.o" +"./Core/Src/main.o" +"./Core/Src/messages.o" +"./Core/Src/moteurs.o" +"./Core/Src/sequenceur.o" +"./Core/Src/stm32l0xx_hal_msp.o" +"./Core/Src/stm32l0xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32l0xx.o" +"./Core/Src/xbee.o" +"./Core/Startup/startup_stm32l010c6tx.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o" +"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o" +"./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o" +"./Middlewares/Third_Party/FreeRTOS/Source/croutine.o" +"./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o" +"./Middlewares/Third_Party/FreeRTOS/Source/list.o" +"./Middlewares/Third_Party/FreeRTOS/Source/queue.o" +"./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o" +"./Middlewares/Third_Party/FreeRTOS/Source/tasks.o" +"./Middlewares/Third_Party/FreeRTOS/Source/timers.o" +"./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o" +"./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o" diff --git a/software/dumber3/Debug/objects.mk b/software/dumber3/Debug/objects.mk new file mode 100644 index 0000000..e12976d --- /dev/null +++ b/software/dumber3/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/software/dumber3/Debug/sources.mk b/software/dumber3/Debug/sources.mk new file mode 100644 index 0000000..1160961 --- /dev/null +++ b/software/dumber3/Debug/sources.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +SIZE_OUTPUT := +OBJDUMP_LIST := +EXECUTABLES := +OBJS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := +OBJCOPY_BIN := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32L0xx_HAL_Driver/Src \ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 \ +Middlewares/Third_Party/FreeRTOS/Source \ +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 \ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang \ + diff --git a/software/dumber3/Dumber3 Debug.launch b/software/dumber3/Dumber3 Debug.launch new file mode 100644 index 0000000..85840ce --- /dev/null +++ b/software/dumber3/Dumber3 Debug.launch @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/dumber3/Dumber3.ioc b/software/dumber3/Dumber3.ioc index f260514..35f5cab 100644 --- a/software/dumber3/Dumber3.ioc +++ b/software/dumber3/Dumber3.ioc @@ -1,5 +1,6 @@ #MicroXplorer Configuration settings - do not modify -ADC.IPParameters=SamplingTime +ADC.IPParameters=SamplingTime,Resolution +ADC.Resolution=ADC_RESOLUTION_8B ADC.SamplingTime=ADC_SAMPLETIME_160CYCLES_5 Dma.LPUART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY Dma.LPUART1_RX.0.Instance=DMA1_Channel3 @@ -27,9 +28,10 @@ FREERTOS.INCLUDE_xEventGroupSetBitFromISR=1 FREERTOS.INCLUDE_xTaskAbortDelay=1 FREERTOS.INCLUDE_xTaskGetCurrentTaskHandle=1 FREERTOS.INCLUDE_xTaskGetHandle=1 -FREERTOS.IPParameters=Tasks01,configTICK_RATE_HZ,configUSE_TICKLESS_IDLE,INCLUDE_xTaskGetHandle,INCLUDE_xTaskAbortDelay,INCLUDE_xEventGroupSetBitFromISR,INCLUDE_pcTaskGetTaskName,INCLUDE_xTaskGetCurrentTaskHandle +FREERTOS.IPParameters=Tasks01,configTICK_RATE_HZ,configUSE_TICKLESS_IDLE,INCLUDE_xTaskGetHandle,INCLUDE_xTaskAbortDelay,INCLUDE_xEventGroupSetBitFromISR,INCLUDE_pcTaskGetTaskName,INCLUDE_xTaskGetCurrentTaskHandle,configTOTAL_HEAP_SIZE FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL FREERTOS.configTICK_RATE_HZ=100 +FREERTOS.configTOTAL_HEAP_SIZE=2048 FREERTOS.configUSE_TICKLESS_IDLE=1 File.Version=6 GPIO.groupedBy=Group By Peripherals @@ -85,7 +87,7 @@ MxCube.Version=6.3.0 MxDb.Version=DB.6.0.30 NVIC.ADC1_IRQn=true\:3\:0\:false\:false\:true\:true\:true\:true NVIC.DMA1_Channel2_3_IRQn=true\:3\:0\:false\:false\:true\:true\:false\:true -NVIC.EXTI2_3_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.EXTI2_3_IRQn=true\:3\:0\:false\:false\:true\:false\:true\:true NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.LPUART1_IRQn=true\:3\:0\:false\:false\:true\:true\:true\:true @@ -130,16 +132,19 @@ PB10.Mode=Asynchronous PB10.Signal=LPUART1_TX PB11.Mode=Asynchronous PB11.Signal=LPUART1_RX -PB12.GPIOParameters=GPIO_Label +PB12.GPIOParameters=GPIO_Speed,GPIO_Label PB12.GPIO_Label=LED_ROUGE +PB12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PB12.Locked=true PB12.Signal=GPIO_Output -PB13.GPIOParameters=GPIO_Label +PB13.GPIOParameters=GPIO_Speed,GPIO_Label PB13.GPIO_Label=LED_ORANGE +PB13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PB13.Locked=true PB13.Signal=GPIO_Output -PB14.GPIOParameters=GPIO_Label +PB14.GPIOParameters=GPIO_Speed,GPIO_Label PB14.GPIO_Label=LED_VERTE +PB14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PB14.Signal=GPIO_Output PB15.GPIOParameters=GPIO_Label PB15.GPIO_Label=SHUTDOWN_ENCODERS @@ -165,9 +170,10 @@ PB8.GPIOParameters=GPIO_Label PB8.GPIO_Label=SHUTDOWN_5V PB8.Locked=true PB8.Signal=GPIO_Output -PB9.GPIOParameters=GPIO_Label +PB9.GPIOParameters=PinState,GPIO_Label PB9.GPIO_Label=SHUTDOWN PB9.Locked=true +PB9.PinState=GPIO_PIN_SET PB9.Signal=GPIO_Output PC0.GPIOParameters=GPIO_Label PC0.GPIO_Label=ENC_PHA_GAUCHE @@ -202,31 +208,39 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_LPTIM1_Init-LPTIM1-false-HAL-true,5-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_TIM21_Init-TIM21-false-HAL-true -RCC.AHBFreq_Value=2097000 -RCC.APB1Freq_Value=2097000 -RCC.APB1TimFreq_Value=2097000 -RCC.APB2Freq_Value=2097000 -RCC.APB2TimFreq_Value=2097000 +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_LPTIM1_Init-LPTIM1-false-HAL-true,5-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_TIM21_Init-TIM21-false-HAL-true,8-MX_ADC_Init-ADC-false-HAL-true +RCC.ADCFreq_Value=4000000 +RCC.AHBFreq_Value=6000000 +RCC.APB1Freq_Value=6000000 +RCC.APB1TimFreq_Value=6000000 +RCC.APB2Freq_Value=6000000 +RCC.APB2TimFreq_Value=6000000 +RCC.FCLKCortexFreq_Value=6000000 RCC.FamilyName=M +RCC.HCLKFreq_Value=6000000 RCC.HSE_VALUE=8000000 RCC.HSI16_VALUE=16000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=2097000 -RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FamilyName,HSE_VALUE,HSI16_VALUE,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSE_VALUE,LSI_VALUE,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,TIMFreq_Value,USART2Freq_Value,VCOOutputFreq_Value,WatchDogFreq_Value -RCC.LPTIMFreq_Value=2097000 -RCC.LPUARTFreq_Value=2097000 +RCC.HSIRCDiv=4 +RCC.HSI_VALUE=4000000 +RCC.I2C1Freq_Value=6000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI16_VALUE,HSIRCDiv,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSE_VALUE,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,WatchDogFreq_Value +RCC.LPTIMFreq_Value=6000000 +RCC.LPUARTFreq_Value=6000000 RCC.LSE_VALUE=32768 RCC.LSI_VALUE=37000 +RCC.MCOPinFreq_Value=6000000 RCC.MSI_VALUE=2097000 -RCC.PLLCLKFreq_Value=24000000 -RCC.PWRFreq_Value=2097000 +RCC.PLLCLKFreq_Value=6000000 +RCC.PWRFreq_Value=6000000 RCC.RTCFreq_Value=37000 RCC.RTCHSEDivFreq_Value=4000000 -RCC.SYSCLKFreq_VALUE=2097000 -RCC.TIMFreq_Value=2097000 -RCC.USART2Freq_Value=2097000 -RCC.VCOOutputFreq_Value=48000000 +RCC.SYSCLKFreq_VALUE=6000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.TIMFreq_Value=6000000 +RCC.TimerFreq_Value=6000000 +RCC.USART2Freq_Value=6000000 +RCC.VCOInputFreq_Value=4000000 +RCC.VCOOutputFreq_Value=12000000 RCC.WatchDogFreq_Value=37000 SH.GPXTI3.0=GPIO_EXTI3 SH.GPXTI3.ConfNb=1 @@ -248,7 +262,8 @@ TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 TIM2.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 -TIM2.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 +TIM2.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4,Period +TIM2.Period=255 VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 VP_SYS_VS_Systick.Mode=SysTick