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index 0000000..19746e0
--- /dev/null
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Courtyard.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Courtyard.gbr
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index 0000000..c34f808
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Courtyard.gbr
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Cu.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Cu.gbr
new file mode 100644
index 0000000..9b1109d
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Cu.gbr
@@ -0,0 +1,16455 @@
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+%TO.N,/Power_Charge/Sense_BATT*%
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+%TO.N,+BATT*%
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+%TO.N,/Cpu/SHUTDOWN*%
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+D42*
+%TO.N,+BATT*%
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new file mode 100644
index 0000000..2ee5494
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new file mode 100644
index 0000000..ca533b1
--- /dev/null
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Paste.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Paste.gbr
new file mode 100644
index 0000000..39e113d
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Paste.gbr
@@ -0,0 +1,605 @@
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Silkscreen.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Silkscreen.gbr
new file mode 100644
index 0000000..efee736
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-B_Silkscreen.gbr
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Courtyard.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Courtyard.gbr
new file mode 100644
index 0000000..acd8446
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Courtyard.gbr
@@ -0,0 +1,414 @@
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Cu.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Cu.gbr
new file mode 100644
index 0000000..7b541e4
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Cu.gbr
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+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
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+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
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+1,1,$1+$1,$8,$9*
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+0 Add horizontal line*
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+X155235150Y-97028000D01*
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+X163576000Y-97028000D01*
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+X164084000Y-97536000D01*
+D28*
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+D31*
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+D30*
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+X139700000Y-89535000D02*
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Fab.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Fab.gbr
new file mode 100644
index 0000000..bfad127
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Fab.gbr
@@ -0,0 +1,2405 @@
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Mask.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Mask.gbr
new file mode 100644
index 0000000..a4b0ecc
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Mask.gbr
@@ -0,0 +1,330 @@
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+G04 Aperture macros list*
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+0 Rectangle with rounded corners*
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+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
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+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
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+0 Rectangle, with rotation*
+0 The origin of the aperture is its center*
+0 $1 length*
+0 $2 width*
+0 $3 Rotation angle, in degrees counterclockwise*
+0 Add horizontal line*
+21,1,$1,$2,0,0,$3*%
+G04 Aperture macros list end*
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Paste.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Paste.gbr
new file mode 100644
index 0000000..a759076
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Paste.gbr
@@ -0,0 +1,268 @@
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+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 Aperture macros list*
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+0 Rectangle with rounded corners*
+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
+1,1,$1+$1,$4,$5*
+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
+20,1,$1+$1,$2,$3,$4,$5,0*
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+0 Rectangle, with rotation*
+0 The origin of the aperture is its center*
+0 $1 length*
+0 $2 width*
+0 $3 Rotation angle, in degrees counterclockwise*
+0 Add horizontal line*
+21,1,$1,$2,0,0,$3*%
+G04 Aperture macros list end*
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Silkscreen.gbr b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Silkscreen.gbr
new file mode 100644
index 0000000..11dc53b
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-F_Silkscreen.gbr
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diff --git a/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-job.gbrjob b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-job.gbrjob
new file mode 100644
index 0000000..6cf94a2
--- /dev/null
+++ b/hardware/pcb/Dumber-v3/dumber-v3/Gerber/dumber-v3-job.gbrjob
@@ -0,0 +1,147 @@
+{
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+    },
+    "CreationDate": "2022-08-31T16:11:48+02:00"
+  },
+  "GeneralSpecs": {
+    "ProjectId": {
+      "Name": "dumber-v3",
+      "GUID": "64756d62-6572-42d7-9633-2e6b69636164",
+      "Revision": "1.1"
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+    {
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+      "FileFunction": "Copper,L2,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "dumber-v3-F_Adhesive.gbr",
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+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "dumber-v3-B_Adhesive.gbr",
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+    },
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+    },
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+      "FilePolarity": "Positive"
+    },
+    {
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+      "FileFunction": "Legend,Top",
+      "FilePolarity": "Positive"
+    },
+    {
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+      "FilePolarity": "Positive"
+    },
+    {
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+      "FilePolarity": "Negative"
+    },
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+      "FileFunction": "SolderMask,Bot",
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+    },
+    {
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+      "FileFunction": "Profile",
+      "FilePolarity": "Positive"
+    },
+    {
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+      "FileFunction": "AssemblyDrawing,Top",
+      "FilePolarity": "Positive"
+    },
+    {
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+      "FileFunction": "AssemblyDrawing,Bot",
+      "FilePolarity": "Positive"
+    }
+  ],
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+      "Name": "Top Silk Screen"
+    },
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+      "Name": "Top Solder Paste"
+    },
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+      "Name": "Top Solder Mask"
+    },
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+      "Name": "F.Cu"
+    },
+    {
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+      "Thickness": 1.51,
+      "Material": "FR4",
+      "Name": "F.Cu/B.Cu",
+      "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "B.Cu"
+    },
+    {
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+      "Thickness": 0.01,
+      "Name": "Bottom Solder Mask"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Bottom Solder Paste"
+    },
+    {
+      "Type": "Legend",
+      "Name": "Bottom Silk Screen"
+    }
+  ]
+}
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/cpu.kicad_sch b/hardware/pcb/Dumber-v3/dumber-v3/cpu.kicad_sch
index 652a157..7c31009 100644
--- a/hardware/pcb/Dumber-v3/dumber-v3/cpu.kicad_sch
+++ b/hardware/pcb/Dumber-v3/dumber-v3/cpu.kicad_sch
@@ -737,71 +737,6 @@
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-        )
-      )
-      (symbol "Jumper_3_Bridged12_1_1"
-        (pin passive line (at -6.35 0 0) (length 2.54)
-          (name "A" (effects (font (size 1.27 1.27))))
-          (number "1" (effects (font (size 1.27 1.27))))
-        )
-        (pin passive line (at 0 -3.81 90) (length 2.54)
-          (name "C" (effects (font (size 1.27 1.27))))
-          (number "2" (effects (font (size 1.27 1.27))))
-        )
-        (pin passive line (at 6.35 0 180) (length 2.54)
-          (name "B" (effects (font (size 1.27 1.27))))
-          (number "3" (effects (font (size 1.27 1.27))))
-        )
-      )
-    )
     (symbol "MCU_ST_STM32L0:STM32L031C6Tx" (in_bom yes) (on_board yes)
       (property "Reference" "U" (id 0) (at -12.7 36.83 0)
         (effects (font (size 1.27 1.27)) (justify left))
@@ -1442,10 +1377,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 40d90da6-2b0f-4b61-a452-39aaaee37955)
   )
-  (wire (pts (xy 93.98 50.8) (xy 93.98 53.34))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 426ffd8f-0543-411e-9727-6263781275e0)
-  )
   (wire (pts (xy 147.32 93.98) (xy 170.18 93.98))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 42fd8cbf-0fe9-4e6d-8428-a36d8919f760)
@@ -1719,10 +1650,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid c1c46e33-32c0-4fc1-a0b3-9216c005d19d)
   )
-  (wire (pts (xy 106.68 53.34) (xy 109.22 53.34))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid c1cdc35c-e86c-4b62-bb8d-3dfe9782b16b)
-  )
   (wire (pts (xy 266.7 82.55) (xy 275.59 82.55))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid c1f7c763-984e-4e36-b1ae-fa83a87a1e36)
@@ -2032,7 +1959,7 @@
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid f18092e7-4590-44e1-bbc5-69dd11a9374c)
   )
-  (label "RESET" (at 99.06 43.18 0)
+  (label "RESET" (at 105.41 43.18 0)
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid fb6fdd3b-b29a-47d5-a1d0-5ece548815c1)
   )
@@ -2066,17 +1993,17 @@
     (uuid b5fb48a3-6f50-4aaf-a7a9-38328e800948)
   )
 
-  (symbol (lib_id "power:GND") (at 109.22 53.34 0) (unit 1)
+  (symbol (lib_id "power:GND") (at 100.33 49.53 0) (unit 1)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 0e54446f-aeb2-4641-9a9e-b60cb11a5233)
-    (property "Reference" "#PWR030" (id 0) (at 109.22 59.69 0)
+    (property "Reference" "#PWR030" (id 0) (at 100.33 55.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 109.22 57.7834 0))
-    (property "Footprint" "" (id 2) (at 109.22 53.34 0)
+    (property "Value" "GND" (id 1) (at 100.33 53.9734 0))
+    (property "Footprint" "" (id 2) (at 100.33 49.53 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 109.22 53.34 0)
+    (property "Datasheet" "" (id 3) (at 100.33 49.53 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid de3d1d97-8822-41a3-92e9-9fa0f1046d38))
@@ -2314,24 +2241,6 @@
     (pin "2" (uuid 335869f0-0f98-4c01-b6aa-c1702876cd96))
   )
 
-  (symbol (lib_id "Jumper:Jumper_3_Bridged12") (at 100.33 53.34 180) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid 55f864fb-4849-4d8d-9e04-3291044a27a8)
-    (property "Reference" "JP1" (id 0) (at 100.33 56.2346 0))
-    (property "Value" "Jumper_3_Bridged12" (id 1) (at 100.33 58.7715 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Footprint" "Jumper:SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm_NumberLabels" (id 2) (at 100.33 53.34 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "~" (id 3) (at 100.33 53.34 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid 679254ce-c54c-4d81-b7ef-fd967a56b22f))
-    (pin "2" (uuid 9fbda050-17ec-465c-9a6e-df43f77d341f))
-    (pin "3" (uuid 092d651d-050f-4034-a6e9-32349e68b22a))
-  )
-
   (symbol (lib_id "power:GND") (at 250.19 48.26 0) (unit 1)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 58bfb7a0-de14-4c9a-b46c-85ecf6fcb60e)
@@ -2373,7 +2282,7 @@
     (property "Reference" "R16" (id 0) (at 36.068 60.1253 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "1.5K" (id 1) (at 36.068 62.6622 0)
+    (property "Value" "1K" (id 1) (at 36.068 62.6622 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
     (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 32.512 60.96 90)
@@ -2411,7 +2320,7 @@
     (property "Reference" "R22" (id 0) (at 47.498 60.1253 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "1.5K" (id 1) (at 47.498 62.6622 0)
+    (property "Value" "1K" (id 1) (at 47.498 62.6622 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
     (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 43.942 60.96 90)
@@ -2554,10 +2463,10 @@
   )
 
   (symbol (lib_id "Device:R") (at 109.22 48.26 90) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (in_bom yes) (on_board yes)
     (uuid 847724be-a104-4b2b-97ba-095b66aec5e9)
-    (property "Reference" "R26" (id 0) (at 109.22 43.5442 90))
-    (property "Value" "10K" (id 1) (at 109.22 46.0811 90))
+    (property "Reference" "R26" (id 0) (at 106.68 45.72 90))
+    (property "Value" "10K" (id 1) (at 111.76 45.72 90))
     (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 109.22 50.038 90)
       (effects (font (size 1.27 1.27)) hide)
     )
@@ -2625,7 +2534,7 @@
     (property "Reference" "R23" (id 0) (at 57.658 60.1253 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "1.5K" (id 1) (at 57.658 62.6622 0)
+    (property "Value" "820" (id 1) (at 57.658 62.6622 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
     (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 54.102 60.96 90)
@@ -2658,7 +2567,7 @@
   )
 
   (symbol (lib_id "Insa:XBEE-3") (at 49.53 171.45 0) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (in_bom yes) (on_board yes)
     (uuid a2266a25-f3f8-4b9b-b976-3534cc857ce9)
     (property "Reference" "U1" (id 0) (at 51.5494 130.971 0)
       (effects (font (size 1.27 1.27)) (justify left))
@@ -2692,22 +2601,6 @@
     (pin "9" (uuid e5e29027-3740-4aab-97f4-71a560e76d6b))
   )
 
-  (symbol (lib_id "power:+2V5") (at 93.98 50.8 0) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid a9030619-07d6-40a1-a218-b160d5d918d4)
-    (property "Reference" "#PWR029" (id 0) (at 93.98 54.61 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Value" "+2V5" (id 1) (at 93.98 47.2242 0))
-    (property "Footprint" "" (id 2) (at 93.98 50.8 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "" (id 3) (at 93.98 50.8 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid 3fc1f7b9-a825-439b-a9a7-1f24dc593a8f))
-  )
-
   (symbol (lib_id "Connector_Generic:Conn_02x03_Odd_Even") (at 240.03 29.21 0) (unit 1)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid ad90e2d3-97b9-46c2-8dd0-1f06ea84ef6b)
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-B_Cu.pdf b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-B_Cu.pdf
new file mode 100644
index 0000000..9f1e777
Binary files /dev/null and b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-B_Cu.pdf differ
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-Edge_Cuts.pdf b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-Edge_Cuts.pdf
new file mode 100644
index 0000000..f3086a7
Binary files /dev/null and b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3-Edge_Cuts.pdf differ
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_pcb b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_pcb
index 3d5b315..00cd256 100644
--- a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_pcb
+++ b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_pcb
@@ -60,8 +60,9 @@
     )
     (pad_to_mask_clearance 0)
     (aux_axis_origin 110 149.5)
+    (grid_origin 188.468 107.188)
     (pcbplotparams
-      (layerselection 0x0000000_fffffffe)
+      (layerselection 0x003d0ff_ffffffff)
       (disableapertmacros false)
       (usegerberextensions false)
       (usegerberattributes true)
@@ -87,11 +88,11 @@
       (plotinvisibletext false)
       (sketchpadsonfab false)
       (subtractmaskfromsilk false)
-      (outputformat 4)
+      (outputformat 1)
       (mirror false)
       (drillshape 0)
       (scaleselection 1)
-      (outputdirectory "./")
+      (outputdirectory "Gerber/")
     )
   )
 
@@ -114,80 +115,78 @@
   (net 16 "Net-(D2-Pad2)")
   (net 17 "/Cpu/RESET")
   (net 18 "Net-(J1-Pad3)")
-  (net 19 "Net-(R24-Pad2)")
-  (net 20 "Net-(R7-Pad1)")
+  (net 19 "Net-(C21-Pad1)")
+  (net 20 "Net-(Q2-Pad3)")
   (net 21 "Net-(R7-Pad2)")
   (net 22 "Net-(R10-Pad1)")
   (net 23 "Net-(R12-Pad1)")
   (net 24 "Net-(R13-Pad1)")
   (net 25 "Net-(R14-Pad1)")
-  (net 26 "Net-(R21-Pad1)")
-  (net 27 "/Cpu/OUTGAUCHE_A")
-  (net 28 "/Cpu/OUTGAUCHE_B")
-  (net 29 "/Cpu/OUTDROIT_A")
-  (net 30 "unconnected-(U1-Pad4)")
-  (net 31 "/Cpu/OUTDROIT_B")
-  (net 32 "unconnected-(U1-Pad6)")
-  (net 33 "unconnected-(U1-Pad7)")
-  (net 34 "Net-(SW1-Pad2)")
-  (net 35 "unconnected-(U1-Pad9)")
-  (net 36 "Net-(D3-Pad2)")
-  (net 37 "unconnected-(U1-Pad11)")
-  (net 38 "unconnected-(U1-Pad12)")
-  (net 39 "unconnected-(U1-Pad13)")
-  (net 40 "Net-(D4-Pad2)")
-  (net 41 "unconnected-(U1-Pad15)")
-  (net 42 "unconnected-(U1-Pad16)")
-  (net 43 "unconnected-(U1-Pad17)")
-  (net 44 "unconnected-(U1-Pad18)")
-  (net 45 "unconnected-(U1-Pad19)")
-  (net 46 "unconnected-(U1-Pad20)")
-  (net 47 "Net-(D5-Pad2)")
-  (net 48 "/Cpu/ENCGAUCHE_A")
-  (net 49 "/Cpu/ENCGAUCHE_B")
-  (net 50 "/Cpu/ENCDROIT_A")
-  (net 51 "/Cpu/ENCDROIT_B")
-  (net 52 "/Cpu/LED_ROUGE")
-  (net 53 "/Cpu/LED_ORANGE")
-  (net 54 "/Cpu/LED_VERTE")
-  (net 55 "/Cpu/USART_RX")
-  (net 56 "unconnected-(U2-Pad2)")
-  (net 57 "unconnected-(U2-Pad3)")
-  (net 58 "unconnected-(U2-Pad4)")
-  (net 59 "unconnected-(U2-Pad5)")
-  (net 60 "unconnected-(U2-Pad6)")
-  (net 61 "unconnected-(J3-Pad6)")
-  (net 62 "/Cpu/USART_TX")
-  (net 63 "/Cpu/XBEE_RESET")
-  (net 64 "unconnected-(J3-Pad7)")
-  (net 65 "unconnected-(J3-Pad8)")
-  (net 66 "unconnected-(U2-Pad14)")
-  (net 67 "Net-(JP1-Pad2)")
-  (net 68 "unconnected-(U2-Pad16)")
-  (net 69 "unconnected-(U2-Pad17)")
-  (net 70 "Net-(R1-Pad1)")
-  (net 71 "/Cpu/CHARGER_ST1")
-  (net 72 "unconnected-(U2-Pad20)")
-  (net 73 "/Cpu/SHUTDOWN")
-  (net 74 "/Cpu/CHARGER_ST2")
-  (net 75 "/Cpu/PWM_GAUCHE_A")
-  (net 76 "/Cpu/PWM_GAUCHE_B")
-  (net 77 "/Cpu/BUTTON_SENSE")
-  (net 78 "/Cpu/USB_SENSE")
-  (net 79 "/Cpu/BATTERY_SENSE")
-  (net 80 "/Cpu/SHUTDOWN_ENC")
-  (net 81 "Net-(R26-Pad2)")
-  (net 82 "unconnected-(U2-Pad30)")
-  (net 83 "unconnected-(U2-Pad31)")
-  (net 84 "unconnected-(U2-Pad32)")
-  (net 85 "unconnected-(U2-Pad33)")
-  (net 86 "/Cpu/SWDIO")
-  (net 87 "/Cpu/PWM_DROIT_A")
-  (net 88 "/Cpu/PWM_DROIT_B")
-  (net 89 "/Cpu/SWCLK")
-  (net 90 "/Cpu/SHUTDOWN_5V")
-  (net 91 "unconnected-(U2-Pad41)")
-  (net 92 "Net-(C6-Pad1)")
+  (net 26 "/Cpu/OUTGAUCHE_A")
+  (net 27 "/Cpu/OUTGAUCHE_B")
+  (net 28 "/Cpu/OUTDROIT_A")
+  (net 29 "unconnected-(U1-Pad4)")
+  (net 30 "/Cpu/OUTDROIT_B")
+  (net 31 "unconnected-(U1-Pad6)")
+  (net 32 "unconnected-(U1-Pad7)")
+  (net 33 "Net-(SW1-Pad2)")
+  (net 34 "unconnected-(U1-Pad9)")
+  (net 35 "Net-(D3-Pad2)")
+  (net 36 "unconnected-(U1-Pad11)")
+  (net 37 "unconnected-(U1-Pad12)")
+  (net 38 "unconnected-(U1-Pad13)")
+  (net 39 "Net-(D4-Pad2)")
+  (net 40 "unconnected-(U1-Pad15)")
+  (net 41 "unconnected-(U1-Pad16)")
+  (net 42 "unconnected-(U1-Pad17)")
+  (net 43 "unconnected-(U1-Pad18)")
+  (net 44 "unconnected-(U1-Pad19)")
+  (net 45 "unconnected-(U1-Pad20)")
+  (net 46 "Net-(D5-Pad2)")
+  (net 47 "/Cpu/ENCGAUCHE_A")
+  (net 48 "/Cpu/ENCGAUCHE_B")
+  (net 49 "/Cpu/ENCDROIT_A")
+  (net 50 "/Cpu/ENCDROIT_B")
+  (net 51 "/Cpu/LED_ROUGE")
+  (net 52 "/Cpu/LED_ORANGE")
+  (net 53 "/Cpu/LED_VERTE")
+  (net 54 "/Cpu/USART_RX")
+  (net 55 "unconnected-(U2-Pad2)")
+  (net 56 "unconnected-(U2-Pad3)")
+  (net 57 "unconnected-(U2-Pad4)")
+  (net 58 "unconnected-(U2-Pad5)")
+  (net 59 "unconnected-(U2-Pad6)")
+  (net 60 "unconnected-(J3-Pad6)")
+  (net 61 "/Cpu/USART_TX")
+  (net 62 "/Cpu/XBEE_RESET")
+  (net 63 "unconnected-(J3-Pad7)")
+  (net 64 "unconnected-(J3-Pad8)")
+  (net 65 "unconnected-(U2-Pad14)")
+  (net 66 "unconnected-(U2-Pad16)")
+  (net 67 "unconnected-(U2-Pad17)")
+  (net 68 "Net-(R1-Pad1)")
+  (net 69 "/Cpu/CHARGER_ST1")
+  (net 70 "unconnected-(U2-Pad20)")
+  (net 71 "/Cpu/SHUTDOWN")
+  (net 72 "/Cpu/CHARGER_ST2")
+  (net 73 "/Cpu/PWM_GAUCHE_A")
+  (net 74 "/Cpu/PWM_GAUCHE_B")
+  (net 75 "/Cpu/BUTTON_SENSE")
+  (net 76 "/Cpu/USB_SENSE")
+  (net 77 "/Cpu/BATTERY_SENSE")
+  (net 78 "/Cpu/SHUTDOWN_ENC")
+  (net 79 "Net-(R26-Pad2)")
+  (net 80 "unconnected-(U2-Pad30)")
+  (net 81 "unconnected-(U2-Pad31)")
+  (net 82 "unconnected-(U2-Pad32)")
+  (net 83 "unconnected-(U2-Pad33)")
+  (net 84 "/Cpu/SWDIO")
+  (net 85 "/Cpu/PWM_DROIT_A")
+  (net 86 "/Cpu/PWM_DROIT_B")
+  (net 87 "/Cpu/SWCLK")
+  (net 88 "/Cpu/SHUTDOWN_5V")
+  (net 89 "unconnected-(U2-Pad41)")
+  (net 90 "Net-(C6-Pad1)")
 
   (footprint "INSA:Motor Pololu HPCB with encoder" locked (layer "F.Cu")
     (tedit 0) (tstamp 171397a2-0fdc-4f75-94fc-fc53063305d3)
@@ -288,9 +287,9 @@
     (pad "1" smd rect locked (at -2.625 -0.85 243) (size 1.55 1) (layers "F.Cu" "F.Paste" "F.Mask")
       (net 2 "GND") (pinfunction "1") (pintype "passive") (tstamp eaa1c1c9-c781-494e-a6d5-11835e9fd470))
     (pad "2" smd rect locked (at 2.625 0.85 243) (size 1.55 1) (layers "F.Cu" "F.Paste" "F.Mask")
-      (net 34 "Net-(SW1-Pad2)") (pinfunction "2") (pintype "passive") (tstamp 774d3398-a10c-4837-b579-b064c492006f))
+      (net 33 "Net-(SW1-Pad2)") (pinfunction "2") (pintype "passive") (tstamp 774d3398-a10c-4837-b579-b064c492006f))
     (pad "2" smd rect locked (at -2.625 0.85 243) (size 1.55 1) (layers "F.Cu" "F.Paste" "F.Mask")
-      (net 34 "Net-(SW1-Pad2)") (pinfunction "2") (pintype "passive") (tstamp 894f74a8-08ed-4434-a70a-70eb66a25624))
+      (net 33 "Net-(SW1-Pad2)") (pinfunction "2") (pintype "passive") (tstamp 894f74a8-08ed-4434-a70a-70eb66a25624))
     (model "${KICAD6_3DMODEL_DIR}/Button_Switch_SMD.3dshapes/Panasonic_EVQPUJ_EVQPUA.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -357,15 +356,15 @@
     (fp_line (start -3.18 -4.1) (end -2.18 -5.1) (layer "F.Fab") (width 0.1) (tstamp f9ed10f6-e113-4e03-865d-59f60e4a649a))
     (fp_line (start -2.18 -5.1) (end 5.72 -5.1) (layer "F.Fab") (width 0.1) (tstamp fb349134-fdba-4930-8d6a-de2d04f5d485))
     (pad "1" thru_hole roundrect locked (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.1470588235)
-      (net 27 "/Cpu/OUTGAUCHE_A") (pinfunction "Pin_1") (pintype "passive") (tstamp 15084e93-418a-4ae8-a940-b8e9a55548b1))
+      (net 26 "/Cpu/OUTGAUCHE_A") (pinfunction "Pin_1") (pintype "passive") (tstamp 15084e93-418a-4ae8-a940-b8e9a55548b1))
     (pad "2" thru_hole circle locked (at 2.54 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
-      (net 28 "/Cpu/OUTGAUCHE_B") (pinfunction "Pin_2") (pintype "passive") (tstamp 224fe2b6-03f0-4973-98d3-fee0a0e06522))
+      (net 27 "/Cpu/OUTGAUCHE_B") (pinfunction "Pin_2") (pintype "passive") (tstamp 224fe2b6-03f0-4973-98d3-fee0a0e06522))
     (pad "3" thru_hole circle locked (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
       (net 18 "Net-(J1-Pad3)") (pinfunction "Pin_3") (pintype "passive") (tstamp 3c64b12f-cdde-48b6-a5a4-3e989812b61d))
     (pad "4" thru_hole circle locked (at 2.54 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
-      (net 48 "/Cpu/ENCGAUCHE_A") (pinfunction "Pin_4") (pintype "passive") (tstamp c1918d0d-d398-4353-b584-a28572f92c81))
+      (net 47 "/Cpu/ENCGAUCHE_A") (pinfunction "Pin_4") (pintype "passive") (tstamp c1918d0d-d398-4353-b584-a28572f92c81))
     (pad "5" thru_hole circle locked (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
-      (net 49 "/Cpu/ENCGAUCHE_B") (pinfunction "Pin_5") (pintype "passive") (tstamp 77a463d8-648d-444d-90de-d1e88ee25e27))
+      (net 48 "/Cpu/ENCGAUCHE_B") (pinfunction "Pin_5") (pintype "passive") (tstamp 77a463d8-648d-444d-90de-d1e88ee25e27))
     (pad "6" thru_hole circle locked (at 2.54 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
       (net 2 "GND") (pinfunction "Pin_6") (pintype "passive") (tstamp 51cf9093-5756-4dd7-894b-612d489ddf81))
     (model "${KICAD6_3DMODEL_DIR}/Connector_IDC.3dshapes/IDC-Header_2x03_P2.54mm_Vertical.step" hide
@@ -465,7 +464,7 @@
     (pad "1" smd roundrect (at -0.9375 0 30) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "K") (pintype "passive") (tstamp 58e2a104-1075-421c-9cd8-77ed883bc85b))
     (pad "2" smd roundrect (at 0.9375 0 30) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
-      (net 47 "Net-(D5-Pad2)") (pinfunction "A") (pintype "passive") (tstamp e70cc500-9c48-4403-bd64-15aed5313bb8))
+      (net 46 "Net-(D5-Pad2)") (pinfunction "A") (pintype "passive") (tstamp e70cc500-9c48-4403-bd64-15aed5313bb8))
     (model "${KICAD6_3DMODEL_DIR}/Diode_SMD.3dshapes/D_0805_2012Metric.step" hide
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -641,15 +640,15 @@
     (fp_line (start -1.98 4.59) (end -3.18 4.59) (layer "F.Fab") (width 0.1) (tstamp e47e395a-62fd-4a5d-a8eb-7135b8ef3371))
     (fp_line (start -3.18 -4.1) (end -2.18 -5.1) (layer "F.Fab") (width 0.1) (tstamp f495be51-7263-4b91-b5f7-0579af09ad82))
     (pad "1" thru_hole roundrect locked (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.1470588235)
-      (net 29 "/Cpu/OUTDROIT_A") (pinfunction "Pin_1") (pintype "passive") (tstamp 24db725a-3abd-4083-970e-7bf8f2e5a15e))
+      (net 28 "/Cpu/OUTDROIT_A") (pinfunction "Pin_1") (pintype "passive") (tstamp 24db725a-3abd-4083-970e-7bf8f2e5a15e))
     (pad "2" thru_hole circle locked (at 2.54 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
-      (net 31 "/Cpu/OUTDROIT_B") (pinfunction "Pin_2") (pintype "passive") (tstamp ba0cf286-680a-4174-ae7c-ea949e2544ea))
+      (net 30 "/Cpu/OUTDROIT_B") (pinfunction "Pin_2") (pintype "passive") (tstamp ba0cf286-680a-4174-ae7c-ea949e2544ea))
     (pad "3" thru_hole circle locked (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
       (net 18 "Net-(J1-Pad3)") (pinfunction "Pin_3") (pintype "passive") (tstamp 57186978-9d49-4c8a-bc7f-57512ee4a69a))
     (pad "4" thru_hole circle locked (at 2.54 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
-      (net 50 "/Cpu/ENCDROIT_A") (pinfunction "Pin_4") (pintype "passive") (tstamp bcf40bd7-6be2-4b8a-8adc-1fe082fd7ef7))
+      (net 49 "/Cpu/ENCDROIT_A") (pinfunction "Pin_4") (pintype "passive") (tstamp bcf40bd7-6be2-4b8a-8adc-1fe082fd7ef7))
     (pad "5" thru_hole circle locked (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
-      (net 51 "/Cpu/ENCDROIT_B") (pinfunction "Pin_5") (pintype "passive") (tstamp b6aea2eb-3923-4064-be44-ecca4e77e115))
+      (net 50 "/Cpu/ENCDROIT_B") (pinfunction "Pin_5") (pintype "passive") (tstamp b6aea2eb-3923-4064-be44-ecca4e77e115))
     (pad "6" thru_hole circle locked (at 2.54 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
       (net 2 "GND") (pinfunction "Pin_6") (pintype "passive") (tstamp 68e3b881-91d0-43c9-ad61-ce2acc62e0f9))
     (model "${KICAD6_3DMODEL_DIR}/Connector_IDC.3dshapes/IDC-Header_2x03_P2.54mm_Vertical.step" hide
@@ -801,19 +800,19 @@
     (pad "1" smd rect locked (at -1.95 -2.54) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
       (net 9 "+2V5") (pinfunction "Pin_1") (pintype "passive") (tstamp 6582f68a-41b4-48ad-b35e-a0e0a235ed57))
     (pad "2" smd rect locked (at 1.95 -2.54) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
-      (net 86 "/Cpu/SWDIO") (pinfunction "Pin_2") (pintype "passive") (tstamp d6f30294-1179-4d23-8fff-1e83103bcaf3))
+      (net 84 "/Cpu/SWDIO") (pinfunction "Pin_2") (pintype "passive") (tstamp d6f30294-1179-4d23-8fff-1e83103bcaf3))
     (pad "3" smd rect locked (at -1.95 -1.27) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
       (net 2 "GND") (pinfunction "Pin_3") (pintype "passive") (tstamp 38a6d7d1-93a5-4710-8393-214d671c8a45))
     (pad "4" smd rect locked (at 1.95 -1.27) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
-      (net 89 "/Cpu/SWCLK") (pinfunction "Pin_4") (pintype "passive") (tstamp a5f24796-d3a9-41da-a433-86ec98bca65a))
+      (net 87 "/Cpu/SWCLK") (pinfunction "Pin_4") (pintype "passive") (tstamp a5f24796-d3a9-41da-a433-86ec98bca65a))
     (pad "5" smd rect locked (at -1.95 0) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
       (net 2 "GND") (pinfunction "Pin_5") (pintype "passive") (tstamp 7219d64c-2423-453b-9229-0b6f002f7888))
     (pad "6" smd rect locked (at 1.95 0) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
-      (net 61 "unconnected-(J3-Pad6)") (pinfunction "Pin_6") (pintype "passive+no_connect") (tstamp 9815337e-64b0-40f5-9279-1545a13c1251))
+      (net 60 "unconnected-(J3-Pad6)") (pinfunction "Pin_6") (pintype "passive+no_connect") (tstamp 9815337e-64b0-40f5-9279-1545a13c1251))
     (pad "7" smd rect locked (at -1.95 1.27) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
-      (net 64 "unconnected-(J3-Pad7)") (pinfunction "Pin_7") (pintype "passive+no_connect") (tstamp c7cf9499-a2bd-4486-a844-2d68411f8780))
+      (net 63 "unconnected-(J3-Pad7)") (pinfunction "Pin_7") (pintype "passive+no_connect") (tstamp c7cf9499-a2bd-4486-a844-2d68411f8780))
     (pad "8" smd rect locked (at 1.95 1.27) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
-      (net 65 "unconnected-(J3-Pad8)") (pinfunction "Pin_8") (pintype "passive+no_connect") (tstamp 066bd039-f1dd-496c-9e41-48b64b937bff))
+      (net 64 "unconnected-(J3-Pad8)") (pinfunction "Pin_8") (pintype "passive+no_connect") (tstamp 066bd039-f1dd-496c-9e41-48b64b937bff))
     (pad "9" smd rect locked (at -1.95 2.54) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
       (net 2 "GND") (pinfunction "Pin_9") (pintype "passive") (tstamp 179bd768-4bf5-40c3-8dbf-f03be0a42d42))
     (pad "10" smd rect locked (at 1.95 2.54) (size 2.4 0.74) (layers "F.Cu" "F.Paste" "F.Mask")
@@ -857,7 +856,7 @@
     (fp_line (start -2 -2) (end -2 2) (layer "F.Fab") (width 0.1) (tstamp b9c382ee-2ac7-478a-932e-dc8c5b10713e))
     (fp_line (start 2 -2) (end -2 -2) (layer "F.Fab") (width 0.1) (tstamp cc56720a-c07e-4b1e-b25c-6709bf908818))
     (pad "1" smd rect (at -1.4 0 180) (size 1.2 3.7) (layers "F.Cu" "F.Paste" "F.Mask")
-      (net 92 "Net-(C6-Pad1)") (pinfunction "1") (pintype "passive") (tstamp 9291cb5b-6e4c-44e4-b72f-8dd118791278))
+      (net 90 "Net-(C6-Pad1)") (pinfunction "1") (pintype "passive") (tstamp 9291cb5b-6e4c-44e4-b72f-8dd118791278))
     (pad "2" smd rect (at 1.4 0 180) (size 1.2 3.7) (layers "F.Cu" "F.Paste" "F.Mask")
       (net 16 "Net-(D2-Pad2)") (pinfunction "2") (pintype "passive") (tstamp ef326b4c-8386-4167-b146-92447014c865))
     (model "${KICAD6_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Taiyo-Yuden_MD-4040.step"
@@ -904,41 +903,41 @@
     (pad "1" thru_hole rect locked (at 1.2 -20 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
       (net 9 "+2V5") (pinfunction "VCC") (pintype "power_in") (tstamp ec077f5b-77bc-4755-b1b5-5f0c0da59c56))
     (pad "2" thru_hole circle locked (at 1.2 -18 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 55 "/Cpu/USART_RX") (pinfunction "DOUT") (pintype "output") (tstamp 907d84a7-a761-49c8-9d7e-4dc34d48bb10))
+      (net 54 "/Cpu/USART_RX") (pinfunction "DOUT") (pintype "output") (tstamp 907d84a7-a761-49c8-9d7e-4dc34d48bb10))
     (pad "3" thru_hole circle locked (at 1.2 -16 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 62 "/Cpu/USART_TX") (pinfunction "DIN") (pintype "input") (tstamp 4ab4043f-8af9-40c0-a633-4539b908fac5))
+      (net 61 "/Cpu/USART_TX") (pinfunction "DIN") (pintype "input") (tstamp 4ab4043f-8af9-40c0-a633-4539b908fac5))
     (pad "4" thru_hole circle locked (at 1.2 -14 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 30 "unconnected-(U1-Pad4)") (pinfunction "DIO12") (pintype "bidirectional+no_connect") (tstamp 186ca3e0-22eb-4c86-94c9-27d88ddc0f25))
+      (net 29 "unconnected-(U1-Pad4)") (pinfunction "DIO12") (pintype "bidirectional+no_connect") (tstamp 186ca3e0-22eb-4c86-94c9-27d88ddc0f25))
     (pad "5" thru_hole circle locked (at 1.2 -12 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 63 "/Cpu/XBEE_RESET") (pinfunction "~{RESET}") (pintype "input") (tstamp 4df20591-6b75-4f1c-9ae9-6401c5cf9adf))
+      (net 62 "/Cpu/XBEE_RESET") (pinfunction "~{RESET}") (pintype "input") (tstamp 4df20591-6b75-4f1c-9ae9-6401c5cf9adf))
     (pad "6" thru_hole circle locked (at 1.2 -10 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 32 "unconnected-(U1-Pad6)") (pinfunction "RSSI") (pintype "output+no_connect") (tstamp ebd94dc7-f5ba-48dd-992e-583122d69095))
+      (net 31 "unconnected-(U1-Pad6)") (pinfunction "RSSI") (pintype "output+no_connect") (tstamp ebd94dc7-f5ba-48dd-992e-583122d69095))
     (pad "7" thru_hole circle locked (at 1.2 -8 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 33 "unconnected-(U1-Pad7)") (pinfunction "DIO11") (pintype "bidirectional+no_connect") (tstamp b23116ce-069a-4aa9-9322-88e9807402d9))
+      (net 32 "unconnected-(U1-Pad7)") (pinfunction "DIO11") (pintype "bidirectional+no_connect") (tstamp b23116ce-069a-4aa9-9322-88e9807402d9))
     (pad "8" thru_hole circle locked (at 1.2 -6 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask) (tstamp 222dcbbe-c8c1-4854-894a-e15a9c685325))
     (pad "9" thru_hole circle locked (at 1.2 -4 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 35 "unconnected-(U1-Pad9)") (pinfunction "~{DTR}/SLEEP_REQ") (pintype "input+no_connect") (tstamp 0c5e32d2-bada-46e3-bca4-274f5f118a85))
+      (net 34 "unconnected-(U1-Pad9)") (pinfunction "~{DTR}/SLEEP_REQ") (pintype "input+no_connect") (tstamp 0c5e32d2-bada-46e3-bca4-274f5f118a85))
     (pad "10" thru_hole circle locked (at 1.2 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 5354c4e8-1feb-4d94-a330-4c3120ea3ec5))
     (pad "11" thru_hole circle locked (at 23.2 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 37 "unconnected-(U1-Pad11)") (pinfunction "DIO4") (pintype "bidirectional+no_connect") (tstamp f63f1d51-80b0-4c09-bd95-9fe58d2ec9e0))
+      (net 36 "unconnected-(U1-Pad11)") (pinfunction "DIO4") (pintype "bidirectional+no_connect") (tstamp f63f1d51-80b0-4c09-bd95-9fe58d2ec9e0))
     (pad "12" thru_hole circle locked (at 23.2 -4 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 38 "unconnected-(U1-Pad12)") (pinfunction "~{CTS}") (pintype "output+no_connect") (tstamp 0ec8872c-c1dc-42a2-bd37-7414a4edec0c))
+      (net 37 "unconnected-(U1-Pad12)") (pinfunction "~{CTS}") (pintype "output+no_connect") (tstamp 0ec8872c-c1dc-42a2-bd37-7414a4edec0c))
     (pad "13" thru_hole circle locked (at 23.2 -6 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 39 "unconnected-(U1-Pad13)") (pinfunction "~{SLEEP}") (pintype "output+no_connect") (tstamp 928b14de-802d-4950-8b9d-0d1f7c5f25a2))
+      (net 38 "unconnected-(U1-Pad13)") (pinfunction "~{SLEEP}") (pintype "output+no_connect") (tstamp 928b14de-802d-4950-8b9d-0d1f7c5f25a2))
     (pad "14" thru_hole circle locked (at 23.2 -8 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask) (tstamp ecee459c-01c2-42d0-a1c1-e7a2f68b49bd))
     (pad "15" thru_hole circle locked (at 23.2 -10 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 41 "unconnected-(U1-Pad15)") (pinfunction "ASSOCIATE") (pintype "output+no_connect") (tstamp 9400b2a0-a8de-4176-bec1-ecb25b8836e3))
+      (net 40 "unconnected-(U1-Pad15)") (pinfunction "ASSOCIATE") (pintype "output+no_connect") (tstamp 9400b2a0-a8de-4176-bec1-ecb25b8836e3))
     (pad "16" thru_hole circle locked (at 23.2 -12 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 42 "unconnected-(U1-Pad16)") (pinfunction "~{RTS}") (pintype "input+no_connect") (tstamp 025cd670-7427-4a03-9be5-92ba89e55b3a))
+      (net 41 "unconnected-(U1-Pad16)") (pinfunction "~{RTS}") (pintype "input+no_connect") (tstamp 025cd670-7427-4a03-9be5-92ba89e55b3a))
     (pad "17" thru_hole circle locked (at 23.2 -14 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 43 "unconnected-(U1-Pad17)") (pinfunction "DIO3") (pintype "bidirectional+no_connect") (tstamp b6f23ec5-7ef9-47fa-a7fa-a4086e510043))
+      (net 42 "unconnected-(U1-Pad17)") (pinfunction "DIO3") (pintype "bidirectional+no_connect") (tstamp b6f23ec5-7ef9-47fa-a7fa-a4086e510043))
     (pad "18" thru_hole circle locked (at 23.2 -16 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 44 "unconnected-(U1-Pad18)") (pinfunction "DIO2") (pintype "bidirectional+no_connect") (tstamp 01e6735d-a3ca-4409-a40a-adf8acf85dfc))
+      (net 43 "unconnected-(U1-Pad18)") (pinfunction "DIO2") (pintype "bidirectional+no_connect") (tstamp 01e6735d-a3ca-4409-a40a-adf8acf85dfc))
     (pad "19" thru_hole circle locked (at 23.2 -18 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 45 "unconnected-(U1-Pad19)") (pinfunction "DIO1") (pintype "bidirectional+no_connect") (tstamp 186ddc71-2599-4473-851e-61a11658ffe0))
+      (net 44 "unconnected-(U1-Pad19)") (pinfunction "DIO1") (pintype "bidirectional+no_connect") (tstamp 186ddc71-2599-4473-851e-61a11658ffe0))
     (pad "20" thru_hole circle locked (at 23.2 -20 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
-      (net 46 "unconnected-(U1-Pad20)") (pinfunction "DIO0") (pintype "bidirectional+no_connect") (tstamp 9f9dca0e-f97f-40e0-b827-275e94e930d9))
+      (net 45 "unconnected-(U1-Pad20)") (pinfunction "DIO0") (pintype "bidirectional+no_connect") (tstamp 9f9dca0e-f97f-40e0-b827-275e94e930d9))
     (model "/home/dimercur/kicad/local-packages3d/Insa.3dshapes/User Library-XBee-Chip.STEP"
       (offset (xyz 12.2 10.5 4))
       (scale (xyz 1 1 1))
@@ -982,7 +981,7 @@
     (pad "1" smd roundrect (at -0.9375 0 30) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "K") (pintype "passive") (tstamp b6015792-6f51-4c21-9322-feb46412d71b))
     (pad "2" smd roundrect (at 0.9375 0 30) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
-      (net 40 "Net-(D4-Pad2)") (pinfunction "A") (pintype "passive") (tstamp 68f323c8-e7ab-4230-92f3-f6e9061e68af))
+      (net 39 "Net-(D4-Pad2)") (pinfunction "A") (pintype "passive") (tstamp 68f323c8-e7ab-4230-92f3-f6e9061e68af))
     (model "${KICAD6_3DMODEL_DIR}/Diode_SMD.3dshapes/D_0805_2012Metric.step" hide
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -1031,7 +1030,7 @@
     (pad "1" smd roundrect (at -0.9375 0 30) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "K") (pintype "passive") (tstamp c0293351-bd8d-4ec8-916c-e2cf4f30253f))
     (pad "2" smd roundrect (at 0.9375 0 30) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
-      (net 36 "Net-(D3-Pad2)") (pinfunction "A") (pintype "passive") (tstamp d7e814e8-ba42-4f8f-ba10-5d99643ce283))
+      (net 35 "Net-(D3-Pad2)") (pinfunction "A") (pintype "passive") (tstamp d7e814e8-ba42-4f8f-ba10-5d99643ce283))
     (model "${KICAD6_3DMODEL_DIR}/Diode_SMD.3dshapes/D_0805_2012Metric.step" hide
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -1188,17 +1187,17 @@
     (fp_line (start -3.5 -3.5) (end -3.5 2.5) (layer "B.Fab") (width 0.1) (tstamp e2ecf559-5441-4ae1-8b43-eec07f59eaad))
     (fp_line (start -3.5 2.5) (end -2.5 3.5) (layer "B.Fab") (width 0.1) (tstamp ee6061a8-1403-45f2-a75d-aebe9dbf5885))
     (pad "1" smd roundrect (at -4.1625 2.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 48 "/Cpu/ENCGAUCHE_A") (pinfunction "PC0") (pintype "bidirectional") (tstamp 340ffbbe-61c1-482d-b5ea-c2fe403988dc))
+      (net 47 "/Cpu/ENCGAUCHE_A") (pinfunction "PC0") (pintype "bidirectional") (tstamp 340ffbbe-61c1-482d-b5ea-c2fe403988dc))
     (pad "2" smd roundrect (at -4.1625 2.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 56 "unconnected-(U2-Pad2)") (pinfunction "PC13") (pintype "bidirectional+no_connect") (tstamp 9e728f14-922f-43a0-80a0-5c91f3ce0c3b))
+      (net 55 "unconnected-(U2-Pad2)") (pinfunction "PC13") (pintype "bidirectional+no_connect") (tstamp 9e728f14-922f-43a0-80a0-5c91f3ce0c3b))
     (pad "3" smd roundrect (at -4.1625 1.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 57 "unconnected-(U2-Pad3)") (pinfunction "PC14") (pintype "bidirectional+no_connect") (tstamp 46447f7b-d79b-472b-aaec-41ecd91b35bc))
+      (net 56 "unconnected-(U2-Pad3)") (pinfunction "PC14") (pintype "bidirectional+no_connect") (tstamp 46447f7b-d79b-472b-aaec-41ecd91b35bc))
     (pad "4" smd roundrect (at -4.1625 1.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 58 "unconnected-(U2-Pad4)") (pinfunction "PC15") (pintype "bidirectional+no_connect") (tstamp c54aad6b-9641-4d27-85af-1ed6966f5b67))
+      (net 57 "unconnected-(U2-Pad4)") (pinfunction "PC15") (pintype "bidirectional+no_connect") (tstamp c54aad6b-9641-4d27-85af-1ed6966f5b67))
     (pad "5" smd roundrect (at -4.1625 0.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 59 "unconnected-(U2-Pad5)") (pinfunction "PH0") (pintype "input+no_connect") (tstamp 871c3567-9050-42c6-94df-1775cb20fa05))
+      (net 58 "unconnected-(U2-Pad5)") (pinfunction "PH0") (pintype "input+no_connect") (tstamp 871c3567-9050-42c6-94df-1775cb20fa05))
     (pad "6" smd roundrect (at -4.1625 0.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 60 "unconnected-(U2-Pad6)") (pinfunction "PH1") (pintype "input+no_connect") (tstamp 89f4988c-bf50-401a-986b-f9d76ce02ec1))
+      (net 59 "unconnected-(U2-Pad6)") (pinfunction "PH1") (pintype "input+no_connect") (tstamp 89f4988c-bf50-401a-986b-f9d76ce02ec1))
     (pad "7" smd roundrect (at -4.1625 -0.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 17 "/Cpu/RESET") (pinfunction "NRST") (pintype "input") (tstamp 621f66c8-0d28-4ce2-a0d4-ca85a4f88f1c))
     (pad "8" smd roundrect (at -4.1625 -0.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
@@ -1206,79 +1205,79 @@
     (pad "9" smd roundrect (at -4.1625 -1.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 9 "+2V5") (pinfunction "VDDA") (pintype "power_in") (tstamp 41ac9f5e-50d3-4103-b1ec-8f8a4473a3c2))
     (pad "10" smd roundrect (at -4.1625 -1.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 79 "/Cpu/BATTERY_SENSE") (pinfunction "PA0") (pintype "bidirectional") (tstamp b02a0f29-e80f-41e7-adeb-ff8e439ccf08))
+      (net 77 "/Cpu/BATTERY_SENSE") (pinfunction "PA0") (pintype "bidirectional") (tstamp b02a0f29-e80f-41e7-adeb-ff8e439ccf08))
     (pad "11" smd roundrect (at -4.1625 -2.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 76 "/Cpu/PWM_GAUCHE_B") (pinfunction "PA1") (pintype "bidirectional") (tstamp 45e208ef-3dbf-455c-b8eb-44fde8f8247d))
+      (net 74 "/Cpu/PWM_GAUCHE_B") (pinfunction "PA1") (pintype "bidirectional") (tstamp 45e208ef-3dbf-455c-b8eb-44fde8f8247d))
     (pad "12" smd roundrect (at -4.1625 -2.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 50 "/Cpu/ENCDROIT_A") (pinfunction "PA2") (pintype "bidirectional") (tstamp 4fa6ee9c-2f3a-470d-b465-2ba2e64c59e5))
+      (net 49 "/Cpu/ENCDROIT_A") (pinfunction "PA2") (pintype "bidirectional") (tstamp 4fa6ee9c-2f3a-470d-b465-2ba2e64c59e5))
     (pad "13" smd roundrect (at -2.75 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 51 "/Cpu/ENCDROIT_B") (pinfunction "PA3") (pintype "bidirectional") (tstamp e428e261-02f0-4650-b01d-c388448a6ebe))
+      (net 50 "/Cpu/ENCDROIT_B") (pinfunction "PA3") (pintype "bidirectional") (tstamp e428e261-02f0-4650-b01d-c388448a6ebe))
     (pad "14" smd roundrect (at -2.25 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 66 "unconnected-(U2-Pad14)") (pinfunction "PA4") (pintype "bidirectional+no_connect") (tstamp bbe9d954-03cf-4544-8ffa-e71030f20f56))
+      (net 65 "unconnected-(U2-Pad14)") (pinfunction "PA4") (pintype "bidirectional+no_connect") (tstamp bbe9d954-03cf-4544-8ffa-e71030f20f56))
     (pad "15" smd roundrect (at -1.75 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 49 "/Cpu/ENCGAUCHE_B") (pinfunction "PA5") (pintype "bidirectional") (tstamp 6e5bbbb0-1b86-4c75-bb3f-70d46d7a17fa))
+      (net 48 "/Cpu/ENCGAUCHE_B") (pinfunction "PA5") (pintype "bidirectional") (tstamp 6e5bbbb0-1b86-4c75-bb3f-70d46d7a17fa))
     (pad "16" smd roundrect (at -1.25 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 68 "unconnected-(U2-Pad16)") (pinfunction "PA6") (pintype "bidirectional+no_connect") (tstamp 1554ec1c-15bb-4fd3-b5c4-f88c6bc8a8c5))
+      (net 66 "unconnected-(U2-Pad16)") (pinfunction "PA6") (pintype "bidirectional+no_connect") (tstamp 1554ec1c-15bb-4fd3-b5c4-f88c6bc8a8c5))
     (pad "17" smd roundrect (at -0.75 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 69 "unconnected-(U2-Pad17)") (pinfunction "PA7") (pintype "bidirectional+no_connect") (tstamp c3b2b465-2b94-4622-8f62-3e86e631f7f5))
+      (net 67 "unconnected-(U2-Pad17)") (pinfunction "PA7") (pintype "bidirectional+no_connect") (tstamp c3b2b465-2b94-4622-8f62-3e86e631f7f5))
     (pad "18" smd roundrect (at -0.25 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 87 "/Cpu/PWM_DROIT_A") (pinfunction "PB0") (pintype "bidirectional") (tstamp 2bb0535e-9a49-4673-bc93-3e6d6ce5334b))
+      (net 85 "/Cpu/PWM_DROIT_A") (pinfunction "PB0") (pintype "bidirectional") (tstamp 2bb0535e-9a49-4673-bc93-3e6d6ce5334b))
     (pad "19" smd roundrect (at 0.25 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 88 "/Cpu/PWM_DROIT_B") (pinfunction "PB1") (pintype "bidirectional") (tstamp 4eec2f11-9dfd-4d9f-8ab0-940c49e9636c))
+      (net 86 "/Cpu/PWM_DROIT_B") (pinfunction "PB1") (pintype "bidirectional") (tstamp 4eec2f11-9dfd-4d9f-8ab0-940c49e9636c))
     (pad "20" smd roundrect (at 0.75 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 72 "unconnected-(U2-Pad20)") (pinfunction "PB2") (pintype "bidirectional+no_connect") (tstamp 0a9d31f7-367e-4e7e-8ac1-0026d73eb9c0))
+      (net 70 "unconnected-(U2-Pad20)") (pinfunction "PB2") (pintype "bidirectional+no_connect") (tstamp 0a9d31f7-367e-4e7e-8ac1-0026d73eb9c0))
     (pad "21" smd roundrect (at 1.25 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 62 "/Cpu/USART_TX") (pinfunction "PB10") (pintype "bidirectional") (tstamp 684f65a7-41a7-46dc-b3de-a3f339387201))
+      (net 61 "/Cpu/USART_TX") (pinfunction "PB10") (pintype "bidirectional") (tstamp 684f65a7-41a7-46dc-b3de-a3f339387201))
     (pad "22" smd roundrect (at 1.75 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 55 "/Cpu/USART_RX") (pinfunction "PB11") (pintype "bidirectional") (tstamp 2944bfad-d643-498d-a1b9-edd07c6b2363))
+      (net 54 "/Cpu/USART_RX") (pinfunction "PB11") (pintype "bidirectional") (tstamp 2944bfad-d643-498d-a1b9-edd07c6b2363))
     (pad "23" smd roundrect (at 2.25 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "VSS") (pintype "power_in") (tstamp 8c9ae927-7690-4dc9-ae26-d72798cb5ae9))
     (pad "24" smd roundrect (at 2.75 -4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 9 "+2V5") (pinfunction "VDD") (pintype "power_in") (tstamp 2fa4526b-81a9-4830-9bc6-7e6e3addae0f))
     (pad "25" smd roundrect (at 4.1625 -2.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 52 "/Cpu/LED_ROUGE") (pinfunction "PB12") (pintype "bidirectional") (tstamp 1c3c77f9-ae0b-40fe-be67-b79fd1e46504))
+      (net 51 "/Cpu/LED_ROUGE") (pinfunction "PB12") (pintype "bidirectional") (tstamp 1c3c77f9-ae0b-40fe-be67-b79fd1e46504))
     (pad "26" smd roundrect (at 4.1625 -2.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 53 "/Cpu/LED_ORANGE") (pinfunction "PB13") (pintype "bidirectional") (tstamp 1768b417-b3a3-41a4-8ed5-0c8b541ee421))
+      (net 52 "/Cpu/LED_ORANGE") (pinfunction "PB13") (pintype "bidirectional") (tstamp 1768b417-b3a3-41a4-8ed5-0c8b541ee421))
     (pad "27" smd roundrect (at 4.1625 -1.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 54 "/Cpu/LED_VERTE") (pinfunction "PB14") (pintype "bidirectional") (tstamp 3ac11378-61ca-4e34-aa4d-b2d5f5fe5b21))
+      (net 53 "/Cpu/LED_VERTE") (pinfunction "PB14") (pintype "bidirectional") (tstamp 3ac11378-61ca-4e34-aa4d-b2d5f5fe5b21))
     (pad "28" smd roundrect (at 4.1625 -1.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 80 "/Cpu/SHUTDOWN_ENC") (pinfunction "PB15") (pintype "bidirectional") (tstamp 33c90375-65d5-4963-b12b-518be872c277))
+      (net 78 "/Cpu/SHUTDOWN_ENC") (pinfunction "PB15") (pintype "bidirectional") (tstamp 33c90375-65d5-4963-b12b-518be872c277))
     (pad "29" smd roundrect (at 4.1625 -0.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 75 "/Cpu/PWM_GAUCHE_A") (pinfunction "PA8") (pintype "bidirectional") (tstamp 0a77d83e-b042-4be9-9a8c-6de25c89b4d2))
+      (net 73 "/Cpu/PWM_GAUCHE_A") (pinfunction "PA8") (pintype "bidirectional") (tstamp 0a77d83e-b042-4be9-9a8c-6de25c89b4d2))
     (pad "30" smd roundrect (at 4.1625 -0.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 82 "unconnected-(U2-Pad30)") (pinfunction "PA9") (pintype "bidirectional+no_connect") (tstamp ee5fd5bd-4e15-4b25-ba0b-bb4bf26073d3))
+      (net 80 "unconnected-(U2-Pad30)") (pinfunction "PA9") (pintype "bidirectional+no_connect") (tstamp ee5fd5bd-4e15-4b25-ba0b-bb4bf26073d3))
     (pad "31" smd roundrect (at 4.1625 0.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 83 "unconnected-(U2-Pad31)") (pinfunction "PA10") (pintype "bidirectional+no_connect") (tstamp 46ed0940-a43b-45dc-ab13-7ed5f069e50d))
+      (net 81 "unconnected-(U2-Pad31)") (pinfunction "PA10") (pintype "bidirectional+no_connect") (tstamp 46ed0940-a43b-45dc-ab13-7ed5f069e50d))
     (pad "32" smd roundrect (at 4.1625 0.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 84 "unconnected-(U2-Pad32)") (pinfunction "PA11") (pintype "bidirectional+no_connect") (tstamp d603c54e-76d0-4d5d-8944-c5017d4309c8))
+      (net 82 "unconnected-(U2-Pad32)") (pinfunction "PA11") (pintype "bidirectional+no_connect") (tstamp d603c54e-76d0-4d5d-8944-c5017d4309c8))
     (pad "33" smd roundrect (at 4.1625 1.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 85 "unconnected-(U2-Pad33)") (pinfunction "PA12") (pintype "bidirectional+no_connect") (tstamp adf45750-ae25-4425-8788-bf0bcd390f53))
+      (net 83 "unconnected-(U2-Pad33)") (pinfunction "PA12") (pintype "bidirectional+no_connect") (tstamp adf45750-ae25-4425-8788-bf0bcd390f53))
     (pad "34" smd roundrect (at 4.1625 1.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 86 "/Cpu/SWDIO") (pinfunction "PA13") (pintype "bidirectional") (tstamp e86312c8-dee6-499f-a63a-4496cf18e434))
+      (net 84 "/Cpu/SWDIO") (pinfunction "PA13") (pintype "bidirectional") (tstamp e86312c8-dee6-499f-a63a-4496cf18e434))
     (pad "35" smd roundrect (at 4.1625 2.25) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "VSS") (pintype "power_in") (tstamp 11d50de7-e336-4149-831e-e5192c27e5e0))
     (pad "36" smd roundrect (at 4.1625 2.75) (size 1.475 0.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 9 "+2V5") (pinfunction "VDD") (pintype "power_in") (tstamp 02b8651a-16ab-47c3-a5ea-8bb6c323c195))
     (pad "37" smd roundrect (at 2.75 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 89 "/Cpu/SWCLK") (pinfunction "PA14") (pintype "bidirectional") (tstamp f7cf1470-0125-44d4-9b2a-8c0588674147))
+      (net 87 "/Cpu/SWCLK") (pinfunction "PA14") (pintype "bidirectional") (tstamp f7cf1470-0125-44d4-9b2a-8c0588674147))
     (pad "38" smd roundrect (at 2.25 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 63 "/Cpu/XBEE_RESET") (pinfunction "PA15") (pintype "bidirectional") (tstamp 13ab4464-6878-40a1-8c36-2ff37c9813d9))
+      (net 62 "/Cpu/XBEE_RESET") (pinfunction "PA15") (pintype "bidirectional") (tstamp 13ab4464-6878-40a1-8c36-2ff37c9813d9))
     (pad "39" smd roundrect (at 1.75 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 77 "/Cpu/BUTTON_SENSE") (pinfunction "PB3") (pintype "bidirectional") (tstamp e8e96c48-5615-4bde-957c-f9f2cfd58968))
+      (net 75 "/Cpu/BUTTON_SENSE") (pinfunction "PB3") (pintype "bidirectional") (tstamp e8e96c48-5615-4bde-957c-f9f2cfd58968))
     (pad "40" smd roundrect (at 1.25 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 78 "/Cpu/USB_SENSE") (pinfunction "PB4") (pintype "bidirectional") (tstamp 1f315b87-966e-425a-8c77-53bc7390800b))
+      (net 76 "/Cpu/USB_SENSE") (pinfunction "PB4") (pintype "bidirectional") (tstamp 1f315b87-966e-425a-8c77-53bc7390800b))
     (pad "41" smd roundrect (at 0.75 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 91 "unconnected-(U2-Pad41)") (pinfunction "PB5") (pintype "bidirectional+no_connect") (tstamp b58e5569-baa9-4b07-9ccc-2ba2d0707838))
+      (net 89 "unconnected-(U2-Pad41)") (pinfunction "PB5") (pintype "bidirectional+no_connect") (tstamp b58e5569-baa9-4b07-9ccc-2ba2d0707838))
     (pad "42" smd roundrect (at 0.25 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 74 "/Cpu/CHARGER_ST2") (pinfunction "PB6") (pintype "bidirectional") (tstamp 94b8d16f-6c3c-4392-a014-338582e6a98b))
+      (net 72 "/Cpu/CHARGER_ST2") (pinfunction "PB6") (pintype "bidirectional") (tstamp 94b8d16f-6c3c-4392-a014-338582e6a98b))
     (pad "43" smd roundrect (at -0.25 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 71 "/Cpu/CHARGER_ST1") (pinfunction "PB7") (pintype "bidirectional") (tstamp fc3917e2-9d99-41b6-8c25-bb86c6714b8d))
+      (net 69 "/Cpu/CHARGER_ST1") (pinfunction "PB7") (pintype "bidirectional") (tstamp fc3917e2-9d99-41b6-8c25-bb86c6714b8d))
     (pad "44" smd roundrect (at -0.75 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 81 "Net-(R26-Pad2)") (pinfunction "BOOT0") (pintype "input") (tstamp 5edd9e9f-7d42-44e2-a8ef-f8474989fa23))
+      (net 79 "Net-(R26-Pad2)") (pinfunction "BOOT0") (pintype "input") (tstamp 5edd9e9f-7d42-44e2-a8ef-f8474989fa23))
     (pad "45" smd roundrect (at -1.25 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 90 "/Cpu/SHUTDOWN_5V") (pinfunction "PB8") (pintype "bidirectional") (tstamp 73a36cc0-5a3e-436f-8f82-757b16607905))
+      (net 88 "/Cpu/SHUTDOWN_5V") (pinfunction "PB8") (pintype "bidirectional") (tstamp 73a36cc0-5a3e-436f-8f82-757b16607905))
     (pad "46" smd roundrect (at -1.75 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 73 "/Cpu/SHUTDOWN") (pinfunction "PB9") (pintype "bidirectional") (tstamp cf96116b-4a69-43d5-a315-e3389e2eb03d))
+      (net 71 "/Cpu/SHUTDOWN") (pinfunction "PB9") (pintype "bidirectional") (tstamp cf96116b-4a69-43d5-a315-e3389e2eb03d))
     (pad "47" smd roundrect (at -2.25 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "VSS") (pintype "power_in") (tstamp 32e71579-ba54-40fc-96ae-d03728ec6f0d))
     (pad "48" smd roundrect (at -2.75 4.1625) (size 0.3 1.475) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
@@ -1292,7 +1291,7 @@
 
   (footprint "Capacitor_SMD:C_0805_2012Metric" (layer "B.Cu")
     (tedit 5F68FEEE) (tstamp 16fc9342-6d8f-407e-b6c1-e2037edbd252)
-    (at 184.785 115.57 90)
+    (at 185.928 116.332 90)
     (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
     (tags "capacitor")
     (property "Sheetfile" "power_charge.kicad_sch")
@@ -1364,7 +1363,7 @@
     (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp c58589b5-850f-49ed-bc17-326b14cc62c0))
     (fp_line (start 1 -0.625) (end -1 -0.625) (layer "B.Fab") (width 0.1) (tstamp ee77460c-e3ef-4125-9bbc-1217b80c0ab9))
     (pad "1" smd roundrect (at -0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 20 "Net-(R7-Pad1)") (pintype "passive") (tstamp c331fc36-c40c-462d-a72a-2c182544a978))
+      (net 19 "Net-(C21-Pad1)") (pintype "passive") (tstamp c331fc36-c40c-462d-a72a-2c182544a978))
     (pad "2" smd roundrect (at 0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 21 "Net-(R7-Pad2)") (pintype "passive") (tstamp 03f35650-399f-4132-a78d-bc0b0fcb3e00))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
@@ -1450,7 +1449,7 @@
     (pad "1" smd roundrect (at -0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 5 "VBUS") (pintype "passive") (tstamp 1f9c4cf0-f789-430f-a369-346038738e7f))
     (pad "2" smd roundrect (at 0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 78 "/Cpu/USB_SENSE") (pintype "passive") (tstamp 129982c2-eb59-43ba-9941-3408f2eaf57b))
+      (net 76 "/Cpu/USB_SENSE") (pintype "passive") (tstamp 129982c2-eb59-43ba-9941-3408f2eaf57b))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -1490,7 +1489,7 @@
     (fp_line (start 1 -0.625) (end -1 -0.625) (layer "B.Fab") (width 0.1) (tstamp a1615d32-ae6b-433e-b21a-666172310118))
     (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp a35deda3-fb43-4f03-b634-6391dcf02291))
     (pad "1" smd roundrect (at -0.95 0) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 92 "Net-(C6-Pad1)") (pintype "passive") (tstamp 522791e6-2cfe-4654-903a-520f8f637174))
+      (net 90 "Net-(C6-Pad1)") (pintype "passive") (tstamp 522791e6-2cfe-4654-903a-520f8f637174))
     (pad "2" smd roundrect (at 0.95 0) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 9c101946-c204-42fe-bd03-41d848ecfadd))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
@@ -1534,7 +1533,7 @@
     (pad "1" smd roundrect (at -0.9125 0) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 9 "+2V5") (pintype "passive") (tstamp 33096927-0f07-42b4-b4da-203b936cda46))
     (pad "2" smd roundrect (at 0.9125 0) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 71 "/Cpu/CHARGER_ST1") (pintype "passive") (tstamp 9c19fd67-f45f-4771-8574-4c78f8b35cee))
+      (net 69 "/Cpu/CHARGER_ST1") (pintype "passive") (tstamp 9c19fd67-f45f-4771-8574-4c78f8b35cee))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -1621,19 +1620,19 @@
     (pad "1" smd roundrect (at -1.1375 0.975) (size 1.325 0.5) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 1 "+BATT") (pinfunction "Vin") (pintype "power_in") (tstamp c46ff7a9-1d7d-47ed-9946-03946e9a5050))
     (pad "2" smd roundrect (at -1.1375 0.325) (size 1.325 0.5) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 34 "Net-(SW1-Pad2)") (pinfunction "~{PB}") (pintype "input") (tstamp 9b9dc154-7203-4ed0-b9b2-391e01cbbdec))
+      (net 33 "Net-(SW1-Pad2)") (pinfunction "~{PB}") (pintype "input") (tstamp 9b9dc154-7203-4ed0-b9b2-391e01cbbdec))
     (pad "3" smd roundrect (at -1.1375 -0.325) (size 1.325 0.5) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 3 "Net-(C1-Pad1)") (pinfunction "ONT") (pintype "bidirectional") (tstamp 299bd83a-2cef-452f-9255-306bf9979a9a))
     (pad "4" smd roundrect (at -1.1375 -0.975) (size 1.325 0.5) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp e543a1cd-4f8a-4809-ad88-dd17dffdb9fe))
     (pad "5" smd roundrect (at 1.1375 -0.975) (size 1.325 0.5) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 77 "/Cpu/BUTTON_SENSE") (pinfunction "~{INT}") (pintype "output") (tstamp 838e31ff-3f07-4beb-afd5-e5aa3b210e0f))
+      (net 75 "/Cpu/BUTTON_SENSE") (pinfunction "~{INT}") (pintype "output") (tstamp 838e31ff-3f07-4beb-afd5-e5aa3b210e0f))
     (pad "6" smd roundrect (at 1.1375 -0.325) (size 1.325 0.5) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 70 "Net-(R1-Pad1)") (pinfunction "~{EN}") (pintype "input") (tstamp ad96a9f8-3533-4bc1-b430-f94098570967))
+      (net 68 "Net-(R1-Pad1)") (pinfunction "~{EN}") (pintype "input") (tstamp ad96a9f8-3533-4bc1-b430-f94098570967))
     (pad "7" smd roundrect (at 1.1375 0.325) (size 1.325 0.5) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 4 "Net-(C2-Pad1)") (pinfunction "PDT") (pintype "bidirectional") (tstamp fcd20836-51a2-4128-9ac7-41314f868b50))
     (pad "8" smd roundrect (at 1.1375 0.975) (size 1.325 0.5) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 73 "/Cpu/SHUTDOWN") (pinfunction "~{KILL}") (pintype "input") (tstamp 1fe68ba5-e826-4138-8a35-3bf25a5e5266))
+      (net 71 "/Cpu/SHUTDOWN") (pinfunction "~{KILL}") (pintype "input") (tstamp 1fe68ba5-e826-4138-8a35-3bf25a5e5266))
     (model "${KICAD6_3DMODEL_DIR}/Package_TO_SOT_SMD.3dshapes/SOT-23-8.step" hide
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -1683,7 +1682,7 @@
     (pad "2" smd rect (at -1.16 0 180) (size 0.7 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
       (net 18 "Net-(J1-Pad3)") (pinfunction "D") (pintype "passive") (tstamp 40ae43ed-0eed-48a1-934c-7989d3b7f010))
     (pad "3" smd rect (at -1.16 -0.95 180) (size 0.7 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 19 "Net-(R24-Pad2)") (pinfunction "G") (pintype "input") (tstamp 1757d203-7eb5-45af-b83a-ff41cf14655c))
+      (net 20 "Net-(Q2-Pad3)") (pinfunction "G") (pintype "input") (tstamp 1757d203-7eb5-45af-b83a-ff41cf14655c))
     (pad "4" smd rect (at 1.16 -0.95 180) (size 0.7 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
       (net 9 "+2V5") (pinfunction "S") (pintype "passive") (tstamp 39e14fe5-a86a-48c8-a65e-560bf96520c4))
     (pad "5" smd rect (at 1.16 0 180) (size 0.7 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
@@ -1697,6 +1696,48 @@
     )
   )
 
+  (footprint "Capacitor_SMD:C_0805_2012Metric" (layer "B.Cu")
+    (tedit 5F68FEEE) (tstamp 403f13b0-7d5d-4335-b468-ce691c225bee)
+    (at 175.895 109.855 90)
+    (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (tags "capacitor")
+    (property "Sheetfile" "power_charge.kicad_sch")
+    (property "Sheetname" "Power_Charge")
+    (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/6278b169-e9ba-49e9-9fd2-15de3e39aefb")
+    (attr smd)
+    (fp_text reference "C21" (at 4.572 0 90) (layer "B.SilkS")
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+      (tstamp c0a6a59d-c585-4f4b-814a-9d89e4f4708d)
+    )
+    (fp_text value "1nF" (at 0 -1.68 90) (layer "B.Fab")
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+      (tstamp 79aa9c2f-a94f-4784-a1dd-2382625433c4)
+    )
+    (fp_text user "${REFERENCE}" (at 0 0 90) (layer "B.Fab")
+      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
+      (tstamp a6c34460-3aa0-4443-a553-2d1ee6cbd7f3)
+    )
+    (fp_line (start -0.261252 0.735) (end 0.261252 0.735) (layer "B.SilkS") (width 0.12) (tstamp 97b69ca8-a967-4c78-b88e-97e8c434b8aa))
+    (fp_line (start -0.261252 -0.735) (end 0.261252 -0.735) (layer "B.SilkS") (width 0.12) (tstamp c4c9ff50-3c57-4bca-9873-9c6eedcacddc))
+    (fp_line (start -1.7 -0.98) (end -1.7 0.98) (layer "B.CrtYd") (width 0.05) (tstamp 1ed9f605-a068-4b7d-b507-104737d02424))
+    (fp_line (start -1.7 0.98) (end 1.7 0.98) (layer "B.CrtYd") (width 0.05) (tstamp 24ea69f9-0bbf-43c6-95cf-850bfdd759b4))
+    (fp_line (start 1.7 0.98) (end 1.7 -0.98) (layer "B.CrtYd") (width 0.05) (tstamp 3fdbd23b-3042-44df-afe8-cabbf02d2585))
+    (fp_line (start 1.7 -0.98) (end -1.7 -0.98) (layer "B.CrtYd") (width 0.05) (tstamp 820f148e-347c-4702-8358-ca76210fbbea))
+    (fp_line (start 1 -0.625) (end -1 -0.625) (layer "B.Fab") (width 0.1) (tstamp 2e33fec3-4604-4f32-a154-862750fc63b9))
+    (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp 511c5eef-0c0c-49f1-a0b7-12ded2f738a7))
+    (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp 85a9ac4a-5e01-4853-a90e-8925121fa96e))
+    (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp 9cabdaea-934a-4913-b6b7-d91adfbb4ee8))
+    (pad "1" smd roundrect (at -0.95 0 90) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
+      (net 19 "Net-(C21-Pad1)") (pintype "passive") (tstamp 57114a3a-3f6c-47c4-b04e-44cbc4b7b257))
+    (pad "2" smd roundrect (at 0.95 0 90) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
+      (net 2 "GND") (pintype "passive") (tstamp 47028535-91ae-4f37-9917-203b7c058e09))
+    (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl"
+      (offset (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
   (footprint "Resistor_SMD:R_0805_2012Metric" (layer "B.Cu")
     (tedit 5F68FEEE) (tstamp 42906c05-dcf2-4d0c-82fe-bf6fea93150a)
     (at 131.445 112.395)
@@ -1731,7 +1772,7 @@
     (pad "1" smd roundrect (at -0.9125 0) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 9 "+2V5") (pintype "passive") (tstamp 7a276161-e676-496a-b633-2c9665715907))
     (pad "2" smd roundrect (at 0.9125 0) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 19 "Net-(R24-Pad2)") (pintype "passive") (tstamp bb5fe06e-d683-4818-b699-429f2d3c9356))
+      (net 20 "Net-(Q2-Pad3)") (pintype "passive") (tstamp bb5fe06e-d683-4818-b699-429f2d3c9356))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -1771,7 +1812,7 @@
     (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp a2b3b3d7-e227-4856-a0ce-41f7eb07a71f))
     (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp d076419b-5c15-4653-a113-e2ce1e8975ee))
     (pad "1" smd roundrect (at -0.9125 0) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 70 "Net-(R1-Pad1)") (pintype "passive") (tstamp 8d85282e-0a8f-4718-9802-ef0034569733))
+      (net 68 "Net-(R1-Pad1)") (pintype "passive") (tstamp 8d85282e-0a8f-4718-9802-ef0034569733))
     (pad "2" smd roundrect (at 0.9125 0) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 1 "+BATT") (pintype "passive") (tstamp 4e443621-0922-4868-b4c0-89aaba98be54))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
@@ -1836,7 +1877,7 @@
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp a806835f-f872-410b-b185-6593ede2bb7f)
     )
-    (fp_text value "1.5K" (at 0 -1.65 90) (layer "B.Fab")
+    (fp_text value "1K" (at 0 -1.65 90) (layer "B.Fab")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp bb35530d-56a4-4fe5-a903-6c8ca59d0b7d)
     )
@@ -1855,9 +1896,9 @@
     (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp 6887911f-02f8-4f3c-abbc-72e0dd92ef05))
     (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp 9b595d42-d71b-4372-a1db-2d29b11eb345))
     (pad "1" smd roundrect (at -0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 52 "/Cpu/LED_ROUGE") (pintype "passive") (tstamp d9c17f70-90d7-4fad-8517-8e524fb3f5f7))
+      (net 51 "/Cpu/LED_ROUGE") (pintype "passive") (tstamp d9c17f70-90d7-4fad-8517-8e524fb3f5f7))
     (pad "2" smd roundrect (at 0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 36 "Net-(D3-Pad2)") (pintype "passive") (tstamp f22c17be-0f72-42b8-bae1-b45538c75da1))
+      (net 35 "Net-(D3-Pad2)") (pintype "passive") (tstamp f22c17be-0f72-42b8-bae1-b45538c75da1))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -1874,7 +1915,7 @@
     (property "Sheetname" "Power_Charge")
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/3db638a4-555f-4907-9209-4f7decb8a38c")
     (attr smd)
-    (fp_text reference "R13" (at 3.81 0 90) (layer "B.SilkS")
+    (fp_text reference "R13" (at 4.572 0 90) (layer "B.SilkS")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp 18b26fc1-3a27-4d32-bb56-7bb480f98de0)
     )
@@ -1940,25 +1981,25 @@
     (fp_line (start 1.95 -2.45) (end -1.95 -2.45) (layer "B.Fab") (width 0.1) (tstamp a4782eaa-96a1-4571-9631-0fc5e247396d))
     (fp_line (start -0.95 2.45) (end 1.95 2.45) (layer "B.Fab") (width 0.1) (tstamp e5619820-f0a6-4548-b39e-6d009a33b9bb))
     (pad "1" smd rect (at -2.55 2 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 75 "/Cpu/PWM_GAUCHE_A") (pinfunction "IN1") (pintype "input") (tstamp 1a373272-b282-4e52-97a1-fb54f1fb5de5))
+      (net 73 "/Cpu/PWM_GAUCHE_A") (pinfunction "IN1") (pintype "input") (tstamp 1a373272-b282-4e52-97a1-fb54f1fb5de5))
     (pad "2" smd rect (at -2.55 1 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 76 "/Cpu/PWM_GAUCHE_B") (pinfunction "IN2") (pintype "input") (tstamp a758de68-01e6-472b-985d-c8645256e7e9))
+      (net 74 "/Cpu/PWM_GAUCHE_B") (pinfunction "IN2") (pintype "input") (tstamp a758de68-01e6-472b-985d-c8645256e7e9))
     (pad "3" smd rect (at -2.55 0 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
       (net 10 "+5V") (pinfunction "VBB") (pintype "power_in") (tstamp 2e9acf73-eda8-412c-b53f-91d138e01288))
     (pad "4" smd rect (at -2.55 -1 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 87 "/Cpu/PWM_DROIT_A") (pinfunction "IN3") (pintype "input") (tstamp e5108a12-995e-44ea-b61c-d487a07a7ac0))
+      (net 85 "/Cpu/PWM_DROIT_A") (pinfunction "IN3") (pintype "input") (tstamp e5108a12-995e-44ea-b61c-d487a07a7ac0))
     (pad "5" smd rect (at -2.55 -2 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 88 "/Cpu/PWM_DROIT_B") (pinfunction "IN4") (pintype "input") (tstamp 58a4ce45-04d4-4557-8a21-c005c54c7202))
+      (net 86 "/Cpu/PWM_DROIT_B") (pinfunction "IN4") (pintype "input") (tstamp 58a4ce45-04d4-4557-8a21-c005c54c7202))
     (pad "6" smd rect (at 2.55 -2 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 31 "/Cpu/OUTDROIT_B") (pinfunction "OUT4") (pintype "output") (tstamp a27a208b-16f3-4a9d-bd43-ddaaffdd27dc))
+      (net 30 "/Cpu/OUTDROIT_B") (pinfunction "OUT4") (pintype "output") (tstamp a27a208b-16f3-4a9d-bd43-ddaaffdd27dc))
     (pad "7" smd rect (at 2.55 -1 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 29 "/Cpu/OUTDROIT_A") (pinfunction "OUT3") (pintype "output") (tstamp 53b591ec-4b9a-475a-838a-4a3e8e4209b2))
+      (net 28 "/Cpu/OUTDROIT_A") (pinfunction "OUT3") (pintype "output") (tstamp 53b591ec-4b9a-475a-838a-4a3e8e4209b2))
     (pad "8" smd rect (at 2.55 0 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 6345492e-4213-4031-89c8-7a71751b305d))
     (pad "9" smd rect (at 2.55 1 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 28 "/Cpu/OUTGAUCHE_B") (pinfunction "OUT2") (pintype "output") (tstamp 9dcf1543-26ee-40af-8d17-f14bb03c870c))
+      (net 27 "/Cpu/OUTGAUCHE_B") (pinfunction "OUT2") (pintype "output") (tstamp 9dcf1543-26ee-40af-8d17-f14bb03c870c))
     (pad "10" smd rect (at 2.55 2 180) (size 1.1 0.51) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 27 "/Cpu/OUTGAUCHE_A") (pinfunction "OUT1") (pintype "output") (tstamp df5752d6-cd10-46af-9068-60f79394ecb8))
+      (net 26 "/Cpu/OUTGAUCHE_A") (pinfunction "OUT1") (pintype "output") (tstamp df5752d6-cd10-46af-9068-60f79394ecb8))
     (model "${KICAD6_3DMODEL_DIR}/Package_SO.3dshapes/SSOP-10_3.9x4.9mm_P1.00mm.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -1966,84 +2007,42 @@
     )
   )
 
-  (footprint "Resistor_SMD:R_0805_2012Metric" (layer "B.Cu")
-    (tedit 5F68FEEE) (tstamp 535dd013-87e7-4d6b-9792-2844a086e5de)
-    (at 174.625 115.57 180)
-    (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-    (tags "resistor")
-    (property "Sheetfile" "power_charge.kicad_sch")
-    (property "Sheetname" "Power_Charge")
-    (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/0c20669d-295e-45e5-a8a7-340d59f9a6b1")
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-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 9aaf1f23-f659-440f-a426-d37327b7ba71)
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-    (fp_text value "7,5K" (at 0 -1.65) (layer "B.Fab")
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 388404b4-87c8-409a-80d3-cb4af416e444)
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-    (fp_text user "${REFERENCE}" (at 0 0) (layer "B.Fab")
-      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
-      (tstamp f86df00b-12cd-449f-a774-6818eddbbb12)
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-    (fp_line (start -0.227064 0.735) (end 0.227064 0.735) (layer "B.SilkS") (width 0.12) (tstamp 86d061cf-35de-4cbf-99d7-ab31d9452537))
-    (fp_line (start -0.227064 -0.735) (end 0.227064 -0.735) (layer "B.SilkS") (width 0.12) (tstamp 9ccc0dbc-29aa-43c3-9b20-d5de95e0eeb3))
-    (fp_line (start -1.68 0.95) (end 1.68 0.95) (layer "B.CrtYd") (width 0.05) (tstamp 0cd5edb4-aadb-4e62-8e74-ae0a94ab6dff))
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-    (fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer "B.CrtYd") (width 0.05) (tstamp ca06c97c-91be-4eef-9aea-37b8a350b3d3))
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-      (net 26 "Net-(R21-Pad1)") (pintype "passive") (tstamp 5992a1dd-b6c0-4fbe-95cc-9b5b59e71ad7))
-    (pad "2" smd roundrect (at 0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 1 "+BATT") (pintype "passive") (tstamp d2c52d47-e959-4d38-baf4-18c641f55a09))
-    (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
-      (offset (xyz 0 0 0))
-      (scale (xyz 1 1 1))
-      (rotate (xyz 0 0 0))
-    )
-  )
-
-  (footprint "Capacitor_SMD:C_0805_2012Metric" (layer "B.Cu")
+  (footprint "Capacitor_SMD:C_1210_3225Metric" (layer "B.Cu")
     (tedit 5F68FEEE) (tstamp 5993f681-de50-4dcf-890a-88f61f75094d)
-    (at 188.595 106.045 -90)
-    (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (at 187.96 106.045 -90)
+    (descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
     (tags "capacitor")
     (property "Sheetfile" "power_charge.kicad_sch")
     (property "Sheetname" "Power_Charge")
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/134fab3f-3d52-45ee-9c4d-4b9cd2356757")
     (attr smd)
-    (fp_text reference "C3" (at 0 1.68 -270) (layer "B.SilkS")
+    (fp_text reference "C3" (at -3.937 0.127 90) (layer "B.SilkS")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 40192b37-846c-4f08-bc31-891b464f685f)
+      (tstamp 03b771bd-1284-47db-b26d-90af862b9680)
     )
-    (fp_text value "1µF" (at 0 -1.68 -270) (layer "B.Fab")
+    (fp_text value "100µF" (at 0 -2.3 90) (layer "B.Fab")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 38409c99-7c49-48ec-88ea-4c5f56d5bca5)
+      (tstamp 38884169-7547-44f8-901c-eb6189d52de5)
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-    (fp_text user "${REFERENCE}" (at 0 0 -270) (layer "B.Fab")
-      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
-      (tstamp 21c2d37a-8cf8-4644-aa56-ce98968bf44b)
+    (fp_text user "${REFERENCE}" (at 0 0 90) (layer "B.Fab")
+      (effects (font (size 0.8 0.8) (thickness 0.12)) (justify mirror))
+      (tstamp 50efd05e-5477-4b57-9f42-bd8bc0557219)
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-    (fp_line (start 1.7 -0.98) (end -1.7 -0.98) (layer "B.CrtYd") (width 0.05) (tstamp 896dfe1c-5859-4b0b-8ae2-3a292777499d))
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-    (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp 57f13b18-8d6e-44c0-8cce-58bdcb672c40))
-    (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp de11e60b-8a37-4229-a134-2492eefc6a7c))
-    (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp e494689a-7088-40dd-9eaa-934218e8d897))
-    (pad "1" smd roundrect (at -0.95 0 270) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 5 "VBUS") (pintype "passive") (tstamp a658ac51-8943-4897-afd7-a76194474086))
-    (pad "2" smd roundrect (at 0.95 0 270) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 2 "GND") (pintype "passive") (tstamp ecea0950-b2e0-4cd3-bde5-866dc7594f0a))
-    (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
+    (fp_line (start -0.711252 -1.36) (end 0.711252 -1.36) (layer "B.SilkS") (width 0.12) (tstamp 6ff9a284-ff31-4de4-a58a-15408da8c61c))
+    (fp_line (start -0.711252 1.36) (end 0.711252 1.36) (layer "B.SilkS") (width 0.12) (tstamp d7a7cf1d-123f-400a-ba0f-11b5f828e4e0))
+    (fp_line (start -2.3 -1.6) (end -2.3 1.6) (layer "B.CrtYd") (width 0.05) (tstamp 92508e93-d418-40f5-bbd0-1363c83673be))
+    (fp_line (start -2.3 1.6) (end 2.3 1.6) (layer "B.CrtYd") (width 0.05) (tstamp a1530453-33af-4d9a-839e-8029216d69e8))
+    (fp_line (start 2.3 1.6) (end 2.3 -1.6) (layer "B.CrtYd") (width 0.05) (tstamp a4929bad-fa38-4fa7-b38e-484a52cba527))
+    (fp_line (start 2.3 -1.6) (end -2.3 -1.6) (layer "B.CrtYd") (width 0.05) (tstamp b4b289da-e1d8-45cc-9b55-290a4e9ff632))
+    (fp_line (start 1.6 -1.25) (end -1.6 -1.25) (layer "B.Fab") (width 0.1) (tstamp 1f166fa4-64ea-42c7-9202-7dc120c55a5b))
+    (fp_line (start -1.6 1.25) (end 1.6 1.25) (layer "B.Fab") (width 0.1) (tstamp 4c65ec5d-a4dc-41c6-960d-269799442856))
+    (fp_line (start -1.6 -1.25) (end -1.6 1.25) (layer "B.Fab") (width 0.1) (tstamp a350ed15-88d9-4899-aeb0-e1136ac16fbd))
+    (fp_line (start 1.6 1.25) (end 1.6 -1.25) (layer "B.Fab") (width 0.1) (tstamp bb6f47eb-6507-4708-8647-73eeab1c2f5b))
+    (pad "1" smd roundrect (at -1.475 0 270) (size 1.15 2.7) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.217391)
+      (net 5 "VBUS") (pintype "passive") (tstamp e4c97f1b-1e4b-47b8-961d-776e2847fe92))
+    (pad "2" smd roundrect (at 1.475 0 270) (size 1.15 2.7) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.217391)
+      (net 2 "GND") (pintype "passive") (tstamp b9bdf873-fbe0-42a7-9734-61ca25c41249))
+    (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1210_3225Metric.wrl"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
       (rotate (xyz 0 0 0))
@@ -2084,7 +2083,7 @@
     (pad "1" smd roundrect (at -0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 15 "Net-(Q1-Pad3)") (pintype "passive") (tstamp dd74863a-1571-426e-87a9-b748a3cdfe17))
     (pad "2" smd roundrect (at 0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 70 "Net-(R1-Pad1)") (pintype "passive") (tstamp 7cd0ddd1-2eb9-4d9c-a397-82f35c635a27))
+      (net 68 "Net-(R1-Pad1)") (pintype "passive") (tstamp 7cd0ddd1-2eb9-4d9c-a397-82f35c635a27))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -2092,109 +2091,42 @@
     )
   )
 
-  (footprint "Jumper:SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm_NumberLabels" (layer "B.Cu")
-    (tedit 5B391ED1) (tstamp 5f4c03f0-34b2-41b3-872e-1229b9985e49)
-    (at 150.495 126.365 180)
-    (descr "SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, open, labeled with numbers")
-    (tags "solder jumper open")
-    (property "Sheetfile" "cpu.kicad_sch")
-    (property "Sheetname" "Cpu")
-    (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/55f864fb-4849-4d8d-9e04-3291044a27a8")
-    (attr exclude_from_pos_files)
-    (fp_text reference "JP1" (at 0 -2.54) (layer "B.SilkS")
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 01e292a3-2682-4662-b3e9-be3faaa56098)
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-    (fp_text value "Jumper_3_Bridged12" (at 0 -1.9) (layer "B.Fab")
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 1ac9de5b-9ae0-4660-8da7-1a18ec001d88)
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-    (fp_text user "1" (at -2.6 0) (layer "B.SilkS")
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 288aad15-fd3a-4b80-b89b-6d6e8f83efe3)
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-    (fp_text user "3" (at 2.6 0) (layer "B.SilkS")
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 981d7c38-2a7e-4ce9-a2a9-542202d84b25)
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-    (fp_arc (start -2.05 -0.3) (mid -1.844975 -0.794975) (end -1.35 -1) (layer "B.SilkS") (width 0.12) (tstamp 479d1259-aff7-4398-b39c-a99f45076d7b))
-    (fp_arc (start -1.35 1) (mid -1.844975 0.794975) (end -2.05 0.3) (layer "B.SilkS") (width 0.12) (tstamp eeb8e41f-636c-4f51-af7e-cd2b3a46a9b0))
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-    (pad "1" smd custom (at -1.3 0 180) (size 1 0.5) (layers "B.Cu" "B.Mask")
-      (net 2 "GND") (pinfunction "A") (pintype "passive") (zone_connect 2)
-      (options (clearance outline) (anchor rect))
-      (primitives
-        (gr_circle (center 0 -0.25) (end 0.5 -0.25) (width 0) (fill yes))
-        (gr_circle (center 0 0.25) (end 0.5 0.25) (width 0) (fill yes))
-        (gr_poly (pts
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-    (pad "2" smd rect (at 0 0 180) (size 1 1.5) (layers "B.Cu" "B.Mask")
-      (net 67 "Net-(JP1-Pad2)") (pinfunction "C") (pintype "passive") (tstamp 2617b69f-1ec0-4493-b234-9d1cc7b4f280))
-    (pad "3" smd custom (at 1.3 0 180) (size 1 0.5) (layers "B.Cu" "B.Mask")
-      (net 9 "+2V5") (pinfunction "B") (pintype "passive") (zone_connect 2)
-      (options (clearance outline) (anchor rect))
-      (primitives
-        (gr_circle (center 0 -0.25) (end 0.5 -0.25) (width 0) (fill yes))
-        (gr_circle (center 0 0.25) (end 0.5 0.25) (width 0) (fill yes))
-        (gr_poly (pts
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-  )
-
-  (footprint "Capacitor_SMD:C_0805_2012Metric" (layer "B.Cu")
+  (footprint "Capacitor_SMD:C_1210_3225Metric" (layer "B.Cu")
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+      (net 2 "GND") (pintype "passive") (tstamp d1d17e65-4bd8-44e4-bd0c-162a97be1a20))
+    (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1210_3225Metric.wrl"
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-      (net 74 "/Cpu/CHARGER_ST2") (pintype "passive") (tstamp 918df7c6-260d-453b-9bb1-a204c382a2ca))
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+    (fp_line (start -1.1564 1.8288) (end -1.1564 2.1336) (layer "B.CrtYd") (width 0.05) (tstamp 9a7c00f1-f217-4254-9790-3cae8ccf00a1))
+    (fp_line (start 2.1336 -1.1564) (end 2.1336 1.1564) (layer "B.CrtYd") (width 0.05) (tstamp a0004818-3f1c-4af1-b5cb-b2d7e6ec7867))
+    (fp_line (start 1.1564 -1.8288) (end 1.1564 -2.1336) (layer "B.CrtYd") (width 0.05) (tstamp a3ec000f-ae80-4af3-9e12-8beacfd2000c))
+    (fp_line (start -1.1564 -2.1336) (end -1.1564 -1.8288) (layer "B.CrtYd") (width 0.05) (tstamp a6974342-528a-43cf-bfbe-001e43ea0b86))
+    (fp_line (start -1.1564 -1.8288) (end -1.1564 -2.1336) (layer "B.CrtYd") (width 0.05) (tstamp bc0d7002-0cc2-45bf-8621-7d85368c27e6))
+    (fp_line (start -2.1336 -1.1564) (end -2.1336 1.1564) (layer "B.CrtYd") (width 0.05) (tstamp c3741af6-f0ca-4703-acc0-4ab1a6fb5b58))
+    (fp_line (start -1.8288 1.1564) (end -1.8288 1.8288) (layer "B.CrtYd") (width 0.05) (tstamp c950793e-bd6b-4b8e-bac4-d4278b912887))
+    (fp_line (start -2.1336 1.1564) (end -1.8288 1.1564) (layer "B.CrtYd") (width 0.05) (tstamp cff835d2-3d5e-4864-a5fa-8d4545941e65))
+    (fp_line (start 1.8288 1.8288) (end 1.8288 1.1564) (layer "B.CrtYd") (width 0.05) (tstamp e1684944-4677-4f5e-87e7-a77b435442b4))
+    (fp_line (start 2.1336 1.1564) (end 2.1336 -1.1564) (layer "B.CrtYd") (width 0.05) (tstamp e3ee53b8-48e1-4cfb-8507-706bddfef5c6))
+    (fp_line (start -2.1336 -1.1564) (end -2.1336 1.1564) (layer "B.CrtYd") (width 0.05) (tstamp f12fd563-ab5b-4a0c-8c57-50483c4367d0))
+    (fp_line (start -1.1564 1.8288) (end -1.1564 2.1336) (layer "B.CrtYd") (width 0.05) (tstamp f21cf224-a4cc-4062-abf0-0f8834e32b36))
+    (fp_line (start -1.8288 -1.8288) (end -1.8288 -1.1564) (layer "B.CrtYd") (width 0.05) (tstamp f2a94656-7f58-4bde-95d7-ae7e31b6a831))
+    (fp_line (start 1.8288 -1.8288) (end 1.8288 -1.1564) (layer "B.CrtYd") (width 0.05) (tstamp f2c0530b-1849-4697-94ae-3b0510800091))
+    (fp_line (start -1.5748 -1.5748) (end 1.5748 -1.5748) (layer "B.Fab") (width 0.1) (tstamp 415cd0aa-fe98-48a4-af2c-ad54802c43aa))
+    (fp_line (start -1.5748 1.5748) (end -1.5748 -1.5748) (layer "B.Fab") (width 0.1) (tstamp 64185d30-b219-4785-888b-6c913f4c7ec4))
+    (fp_line (start -1.5748 0.3048) (end -0.3048 1.5748) (layer "B.Fab") (width 0.1) (tstamp a23a31be-68e7-4aeb-842c-264352376e17))
+    (fp_line (start 1.5748 1.5748) (end -1.5748 1.5748) (layer "B.Fab") (width 0.1) (tstamp c06cf886-4c18-444a-84da-674d61a2a901))
+    (fp_line (start 1.5748 -1.5748) (end 1.5748 1.5748) (layer "B.Fab") (width 0.1) (tstamp d4dac931-885c-4591-8b16-09199b265013))
+    (pad "1" smd rect (at -1.4732 0.750001 90) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 5 "VBUS") (pinfunction "Vin") (pintype "power_in") (tstamp cbe6abf4-4170-4e7a-9724-a68de5952628))
+    (pad "2" smd rect (at -1.4732 0.25 90) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 5 "VBUS") (pinfunction "Vinsns") (pintype "power_in") (tstamp 819652f4-2e23-4433-a264-f0a93381741e))
+    (pad "3" smd rect (at -1.4732 -0.25 90) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 72 "/Cpu/CHARGER_ST2") (pinfunction "ST2") (pintype "open_collector") (tstamp 93b1d670-8a89-4b2e-8f75-c49360b73b88))
+    (pad "4" smd rect (at -1.4732 -0.750001 90) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 69 "/Cpu/CHARGER_ST1") (pinfunction "ST1") (pintype "open_collector") (tstamp 55a1b850-2ebd-4f67-875a-a18689747661))
+    (pad "5" smd rect (at -0.750001 -1.4732 180) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 6 "Net-(C4-Pad1)") (pinfunction "T_PRG") (pintype "passive") (tstamp 5a2ea2e0-ad96-4a47-ad0c-3397c837bd5d))
+    (pad "6" smd rect (at -0.25 -1.4732 180) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp b0d4cbfe-1a89-474e-bff9-5825d276c689))
+    (pad "7" smd rect (at 0.25 -1.4732 180) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 2 "GND") (pinfunction "SHDN") (pintype "input") (tstamp 67023a94-4cec-4c95-9ce6-8c4b337f2c2e))
+    (pad "8" smd rect (at 0.750001 -1.4732 180) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 21 "Net-(R7-Pad2)") (pinfunction "TH") (pintype "input") (tstamp 24dfe5d1-06c7-43c0-a550-3f57de07f299))
+    (pad "9" smd rect (at 1.4732 -0.750001 90) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 5 "VBUS") (pinfunction "ISEL") (pintype "input") (tstamp aab93f3a-d6a5-4f6f-9f22-4bd11d5fa2c8))
+    (pad "10" smd rect (at 1.4732 -0.25 90) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 1 "+BATT") (pinfunction "Vosns") (pintype "input") (tstamp fb9c4c02-ade9-4a71-9ac1-fbc3f02a9a96))
+    (pad "11" smd rect (at 1.4732 0.25 90) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 1 "+BATT") (pinfunction "Vout") (pintype "power_out") (tstamp 457ba061-cd81-4f2a-8abd-c9ac9133b2d5))
+    (pad "12" smd rect (at 1.4732 0.750001 90) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 19 "Net-(C21-Pad1)") (pinfunction "V_REF") (pintype "output") (tstamp de8926ba-98f3-4d79-b600-55ac019871d5))
+    (pad "13" smd rect (at 0.750001 1.4732 180) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 24 "Net-(R13-Pad1)") (pinfunction "I_END") (pintype "bidirectional") (tstamp 2fcd202b-13bf-4e70-8744-a8bcb96bcd32))
+    (pad "14" smd rect (at 0.25 1.4732 180) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 5 "VBUS") (pinfunction "MODE") (pintype "input") (tstamp 4d393f72-549a-4363-9333-e5f078029e33))
+    (pad "15" smd rect (at -0.25 1.4732 180) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 23 "Net-(R12-Pad1)") (pinfunction "I_USB") (pintype "input") (tstamp 763a9ee4-4b9d-48c7-a12b-2608a5929e4c))
+    (pad "16" smd rect (at -0.750001 1.4732 180) (size 0.254 0.8128) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 25 "Net-(R14-Pad1)") (pinfunction "I_AC") (pintype "input") (tstamp 395ed865-2df8-46d2-85e6-16af3c356d14))
+    (pad "17" thru_hole circle (at 0.397715 0.409905 180) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask)
+      (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 0fdab647-767d-477f-bb51-7e68afae04cc))
+    (pad "17" thru_hole circle (at -0.4 0.4 180) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask)
+      (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 1917b5c1-4d09-4114-a3a1-93c51432a7c9))
+    (pad "17" smd rect (at 0 0 180) (size 1.5 1.5) (layers "B.Cu" "B.Paste" "B.Mask")
+      (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 78cfb875-a10a-4c56-9a98-b5c2ab7354c5))
+    (pad "17" thru_hole circle (at 0.397715 -0.4 180) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask)
+      (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 97bf082d-40d9-4d42-9b6c-9ce59cf70db7))
+    (pad "17" thru_hole circle (at -0.4 -0.4 180) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask)
+      (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp d6f91094-adac-46ba-a68a-821ec748a725))
   )
 
   (footprint "Resistor_SMD:R_0805_2012Metric" (layer "B.Cu")
@@ -2727,7 +2662,7 @@
     (property "Sheetname" "Power_Charge")
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/df2f3a3c-018d-44e4-a157-467cac57137f")
     (attr smd)
-    (fp_text reference "R14" (at 3.81 0 90) (layer "B.SilkS")
+    (fp_text reference "R14" (at 4.572 -0.127 90) (layer "B.SilkS")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp 1ca9d503-01c3-433d-8c6a-610ee24ed8f3)
     )
@@ -2802,42 +2737,42 @@
     )
   )
 
-  (footprint "Capacitor_SMD:C_0805_2012Metric" (layer "B.Cu")
+  (footprint "Capacitor_SMD:C_1210_3225Metric" (layer "B.Cu")
     (tedit 5F68FEEE) (tstamp 8d5a5654-e00f-4522-985f-ccd5e8bcafde)
     (at 167.005 86.4925 -90)
-    (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
     (tags "capacitor")
     (property "Sheetfile" "power_charge.kicad_sch")
     (property "Sheetname" "Power_Charge")
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/a63b8def-5f1b-4d9d-bb74-90ccd6d05047")
     (attr smd)
-    (fp_text reference "C10" (at 3.81 0 90) (layer "B.SilkS")
+    (fp_text reference "C10" (at 0 2.3 90) (layer "B.SilkS")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 517e37cd-b5fe-4f28-aff2-d1db5114f245)
+      (tstamp c2a35f3f-5d61-46eb-b6b7-655a213ea017)
     )
-    (fp_text value "22µF" (at 0 -1.68 90) (layer "B.Fab")
+    (fp_text value "100µF" (at 0 -2.3 90) (layer "B.Fab")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-      (tstamp 433499c7-245b-408e-bbc3-e7848d006ffd)
+      (tstamp c555d867-bbe8-4d46-a6bf-74799de85443)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "B.Fab")
-      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
-      (tstamp 66038908-3ef5-4af1-8e55-1020c2bcb036)
+      (effects (font (size 0.8 0.8) (thickness 0.12)) (justify mirror))
+      (tstamp 05618346-9482-4140-ad64-a0f145b5ac4e)
     )
-    (fp_line (start -0.261252 0.735) (end 0.261252 0.735) (layer "B.SilkS") (width 0.12) (tstamp 1770570f-eab0-4f64-8270-6b607f68ce4f))
-    (fp_line (start -0.261252 -0.735) (end 0.261252 -0.735) (layer "B.SilkS") (width 0.12) (tstamp c08b8b7c-ec85-4cc4-944d-a6f85f493757))
-    (fp_line (start 1.7 0.98) (end 1.7 -0.98) (layer "B.CrtYd") (width 0.05) (tstamp 190518a8-3f2c-46c3-9ff0-3d759adc456e))
-    (fp_line (start -1.7 0.98) (end 1.7 0.98) (layer "B.CrtYd") (width 0.05) (tstamp 6054e782-dae5-4376-b227-391494a6006b))
-    (fp_line (start 1.7 -0.98) (end -1.7 -0.98) (layer "B.CrtYd") (width 0.05) (tstamp a8ad1c02-4d6c-42e1-82ab-602a36ad15bd))
-    (fp_line (start -1.7 -0.98) (end -1.7 0.98) (layer "B.CrtYd") (width 0.05) (tstamp e3405dc6-c848-4c62-8f87-17dbe8945b8f))
-    (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp 0a645645-927c-4aff-b6f3-4fe1b4a0d1d3))
-    (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp 175bb6cf-5909-4ecf-8afb-c379bb676d47))
-    (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp 316df94e-a4f2-4462-9dd9-9daca886b086))
-    (fp_line (start 1 -0.625) (end -1 -0.625) (layer "B.Fab") (width 0.1) (tstamp ab2dcc1e-d0a1-40f9-bc9f-c81a8f472b35))
-    (pad "1" smd roundrect (at -0.95 0 270) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 10 "+5V") (pintype "passive") (tstamp fc8f9b0a-0888-4245-8c66-7535a6bbf440))
-    (pad "2" smd roundrect (at 0.95 0 270) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 2 "GND") (pintype "passive") (tstamp 953a33bd-055f-4848-8c49-8cf8f5875ce9))
-    (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
+    (fp_line (start -0.711252 -1.36) (end 0.711252 -1.36) (layer "B.SilkS") (width 0.12) (tstamp 19ba9651-b975-4763-9345-1e7454a1b4ca))
+    (fp_line (start -0.711252 1.36) (end 0.711252 1.36) (layer "B.SilkS") (width 0.12) (tstamp 556322e0-e3cc-426f-8f87-432f6438d7c2))
+    (fp_line (start -2.3 -1.6) (end -2.3 1.6) (layer "B.CrtYd") (width 0.05) (tstamp 14df7d57-05aa-44fd-a8e1-6378659c7fd9))
+    (fp_line (start 2.3 1.6) (end 2.3 -1.6) (layer "B.CrtYd") (width 0.05) (tstamp 791b70e5-3d6d-4242-ac9a-53332ee8b101))
+    (fp_line (start 2.3 -1.6) (end -2.3 -1.6) (layer "B.CrtYd") (width 0.05) (tstamp a8f0dca5-dd1f-43d3-b11f-c2d1ef6a36f1))
+    (fp_line (start -2.3 1.6) (end 2.3 1.6) (layer "B.CrtYd") (width 0.05) (tstamp b7ce7e15-0932-4207-b6df-f0d45a35fd40))
+    (fp_line (start 1.6 1.25) (end 1.6 -1.25) (layer "B.Fab") (width 0.1) (tstamp 432a8bbf-a999-4ab0-9dc3-3a2e2c674c14))
+    (fp_line (start -1.6 -1.25) (end -1.6 1.25) (layer "B.Fab") (width 0.1) (tstamp 681388d1-ccf5-4ad8-994c-81b1da7f80c3))
+    (fp_line (start -1.6 1.25) (end 1.6 1.25) (layer "B.Fab") (width 0.1) (tstamp f4e92bd5-203e-4d1c-834d-aa9e921a3cf4))
+    (fp_line (start 1.6 -1.25) (end -1.6 -1.25) (layer "B.Fab") (width 0.1) (tstamp f703999b-62f4-40b4-8b8a-39a18b1a4f01))
+    (pad "1" smd roundrect (at -1.475 0 270) (size 1.15 2.7) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.217391)
+      (net 10 "+5V") (pintype "passive") (tstamp b0850e73-aa72-4004-990c-44a791b52929))
+    (pad "2" smd roundrect (at 1.475 0 270) (size 1.15 2.7) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.217391)
+      (net 2 "GND") (pintype "passive") (tstamp 2367667b-a723-4841-bf00-a2dcf307d5fa))
+    (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1210_3225Metric.wrl"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
       (rotate (xyz 0 0 0))
@@ -2876,9 +2811,9 @@
     (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp dbfcdc7a-63fe-496f-adbc-6892f6e120a8))
     (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp fad80b9c-7061-4661-ae0e-f9eea13553ae))
     (pad "1" smd roundrect (at -0.9125 0 90) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 67 "Net-(JP1-Pad2)") (pintype "passive") (tstamp 17d0a705-dc21-466f-ae4c-5a7ee846d9bb))
+      (net 2 "GND") (pintype "passive") (tstamp 17d0a705-dc21-466f-ae4c-5a7ee846d9bb))
     (pad "2" smd roundrect (at 0.9125 0 90) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 81 "Net-(R26-Pad2)") (pintype "passive") (tstamp 67db9ff2-e419-407a-a228-cfb62c5135dd))
+      (net 79 "Net-(R26-Pad2)") (pintype "passive") (tstamp 67db9ff2-e419-407a-a228-cfb62c5135dd))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -2918,7 +2853,7 @@
     (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp 75137d29-c8ca-444e-8b05-4c42f22d385d))
     (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp 8cb8ca30-3a40-49ad-b864-3e1fea08efda))
     (pad "1" smd roundrect (at -0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 89 "/Cpu/SWCLK") (pintype "passive") (tstamp 113eea5d-b259-4439-8906-8a29eeb98f25))
+      (net 87 "/Cpu/SWCLK") (pintype "passive") (tstamp 113eea5d-b259-4439-8906-8a29eeb98f25))
     (pad "2" smd roundrect (at 0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 2 "GND") (pintype "passive") (tstamp 43e9a5ca-1bc7-42e1-9066-cf70cc5ee044))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
@@ -3004,7 +2939,7 @@
     (pad "1" smd roundrect (at -0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 9 "+2V5") (pintype "passive") (tstamp 3ebd69f7-0fd4-4e9e-98fa-7911d830061f))
     (pad "2" smd roundrect (at 0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 77 "/Cpu/BUTTON_SENSE") (pintype "passive") (tstamp aa23c3c3-2fc4-4e06-9d6c-13e84f4e92dc))
+      (net 75 "/Cpu/BUTTON_SENSE") (pintype "passive") (tstamp aa23c3c3-2fc4-4e06-9d6c-13e84f4e92dc))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3044,9 +2979,9 @@
     (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp 4cd63117-0cbb-4694-befd-634a112dd93e))
     (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp 52f936f4-a513-4206-ab4d-5f379cae5b80))
     (pad "1" smd roundrect (at -0.9125 0 90) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 19 "Net-(R24-Pad2)") (pintype "passive") (tstamp 57ec50c6-8aea-4ca8-b787-bcb5d676b5d5))
+      (net 20 "Net-(Q2-Pad3)") (pintype "passive") (tstamp 57ec50c6-8aea-4ca8-b787-bcb5d676b5d5))
     (pad "2" smd roundrect (at 0.9125 0 90) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 80 "/Cpu/SHUTDOWN_ENC") (pintype "passive") (tstamp 3d9b4cf8-53d4-439d-8b99-4fc95d58118a))
+      (net 78 "/Cpu/SHUTDOWN_ENC") (pintype "passive") (tstamp 3d9b4cf8-53d4-439d-8b99-4fc95d58118a))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3088,7 +3023,7 @@
     (pad "1" smd roundrect (at -0.9125 0 90) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 9 "+2V5") (pintype "passive") (tstamp 7aa27ac1-1697-4f25-9859-65f94a672d0c))
     (pad "2" smd roundrect (at 0.9125 0 90) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 86 "/Cpu/SWDIO") (pintype "passive") (tstamp 57274c8f-8ec6-4b4e-a9f3-8b4e336dba57))
+      (net 84 "/Cpu/SWDIO") (pintype "passive") (tstamp 57274c8f-8ec6-4b4e-a9f3-8b4e336dba57))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3128,9 +3063,9 @@
     (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp 8116609b-6353-4a5d-bd2e-8a3dd4c968a3))
     (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp fc906c51-16a5-4d20-bf89-cb79b47e41c9))
     (pad "1" smd roundrect (at -0.95 0 180) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 27 "/Cpu/OUTGAUCHE_A") (pintype "passive") (tstamp 6de65047-e3d3-46cc-bd53-13e248e1f15d))
+      (net 26 "/Cpu/OUTGAUCHE_A") (pintype "passive") (tstamp 6de65047-e3d3-46cc-bd53-13e248e1f15d))
     (pad "2" smd roundrect (at 0.95 0 180) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 28 "/Cpu/OUTGAUCHE_B") (pintype "passive") (tstamp 207ce73a-4ac6-4ad6-82a5-faaf99626820))
+      (net 27 "/Cpu/OUTGAUCHE_B") (pintype "passive") (tstamp 207ce73a-4ac6-4ad6-82a5-faaf99626820))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3151,7 +3086,7 @@
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp a425b3d0-485c-4b74-a1f4-e3f988e6d57c)
     )
-    (fp_text value "1.5K" (at 0 -1.65 90) (layer "B.Fab")
+    (fp_text value "820" (at 0 -1.65 90) (layer "B.Fab")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp 8a779069-9dc9-4a3a-b013-3fa4bf5ce08d)
     )
@@ -3170,9 +3105,9 @@
     (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp 92732cbf-9c25-4415-bd00-02121455d8ef))
     (fp_line (start 1 -0.625) (end -1 -0.625) (layer "B.Fab") (width 0.1) (tstamp a9ec29e8-a6fe-40c8-93e7-ccb4832ba30e))
     (pad "1" smd roundrect (at -0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 54 "/Cpu/LED_VERTE") (pintype "passive") (tstamp a98605cf-8704-4cc1-bf37-77ca790ea5fa))
+      (net 53 "/Cpu/LED_VERTE") (pintype "passive") (tstamp a98605cf-8704-4cc1-bf37-77ca790ea5fa))
     (pad "2" smd roundrect (at 0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 47 "Net-(D5-Pad2)") (pintype "passive") (tstamp 1fff71c1-30ab-41ba-ba9c-a1b2f1fe45c9))
+      (net 46 "Net-(D5-Pad2)") (pintype "passive") (tstamp 1fff71c1-30ab-41ba-ba9c-a1b2f1fe45c9))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3189,7 +3124,7 @@
     (property "Sheetname" "Power_Charge")
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/da5fc659-2f73-4499-97f7-301d8bfb0ffa")
     (attr smd)
-    (fp_text reference "R12" (at 3.81 0 90) (layer "B.SilkS")
+    (fp_text reference "R12" (at 4.572 -0.127 90) (layer "B.SilkS")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp 6eced115-3a37-4550-8416-c6c2b6db2f93)
     )
@@ -3254,9 +3189,9 @@
     (fp_line (start 1 0.625) (end 1 -0.625) (layer "B.Fab") (width 0.1) (tstamp bd8e4e0c-19bf-48e4-ba53-d391d69b7c73))
     (fp_line (start -1 -0.625) (end -1 0.625) (layer "B.Fab") (width 0.1) (tstamp d0f85786-2c21-4fcc-b2c1-9f8d294e6e07))
     (pad "1" smd roundrect (at -0.95 0 90) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 29 "/Cpu/OUTDROIT_A") (pintype "passive") (tstamp f71eb5b2-4d87-41a1-a61b-5ffb2b33058d))
+      (net 28 "/Cpu/OUTDROIT_A") (pintype "passive") (tstamp f71eb5b2-4d87-41a1-a61b-5ffb2b33058d))
     (pad "2" smd roundrect (at 0.95 0 90) (size 1 1.45) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 31 "/Cpu/OUTDROIT_B") (pintype "passive") (tstamp d9a63d7f-53b9-499d-9202-bf885262d4d6))
+      (net 30 "/Cpu/OUTDROIT_B") (pintype "passive") (tstamp d9a63d7f-53b9-499d-9202-bf885262d4d6))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3418,7 +3353,7 @@
     (property "Sheetname" "Power_Charge")
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/fa604296-bc37-4ba5-96fe-4590ffd6650e")
     (attr smd)
-    (fp_text reference "U6" (at 3.175 0.635 180) (layer "B.SilkS")
+    (fp_text reference "U6" (at 3.175 1.143 180) (layer "B.SilkS")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp 7f9561bd-ddea-4df6-b738-91f4e9ed0090)
     )
@@ -3444,11 +3379,11 @@
     (fp_line (start -0.8 -1.45) (end -0.8 1.05) (layer "B.Fab") (width 0.1) (tstamp 930f6090-107e-485c-8ba7-ff48a4bcba4c))
     (fp_line (start 0.8 1.45) (end 0.8 -1.45) (layer "B.Fab") (width 0.1) (tstamp be56a237-53d2-41ef-81ca-646a92552c42))
     (pad "1" smd roundrect (at -1.1375 0.95 90) (size 1.325 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 92 "Net-(C6-Pad1)") (pinfunction "Vin") (pintype "power_in") (tstamp ae85a7a9-7f01-48d9-9130-b6ec9c9a3ac6))
+      (net 90 "Net-(C6-Pad1)") (pinfunction "Vin") (pintype "power_in") (tstamp ae85a7a9-7f01-48d9-9130-b6ec9c9a3ac6))
     (pad "2" smd roundrect (at -1.1375 0 90) (size 1.325 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 3215ed63-e882-46ba-bca7-4546fbcaee43))
     (pad "3" smd roundrect (at -1.1375 -0.95 90) (size 1.325 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 92 "Net-(C6-Pad1)") (pinfunction "~{SHDN}") (pintype "input") (tstamp 90301ad6-193f-4b34-bb61-050f46bb58ee))
+      (net 90 "Net-(C6-Pad1)") (pinfunction "~{SHDN}") (pintype "input") (tstamp 90301ad6-193f-4b34-bb61-050f46bb58ee))
     (pad "4" smd roundrect (at 1.1375 -0.95 90) (size 1.325 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 12 "Net-(C9-Pad1)") (pinfunction "~{ERROR}") (pintype "open_collector") (tstamp 6f602514-4444-42af-bbc7-2fb826be5aa6))
     (pad "5" smd roundrect (at 1.1375 0.95 90) (size 1.325 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
@@ -3599,7 +3534,7 @@
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp e5f696e6-3ce9-48c2-a15c-17b0c7963603)
     )
-    (fp_text value "1.5K" (at 0 -1.65 90) (layer "B.Fab")
+    (fp_text value "1K" (at 0 -1.65 90) (layer "B.Fab")
       (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp 3fc168eb-e76d-4ca2-a950-2dd4df28466b)
     )
@@ -3618,9 +3553,9 @@
     (fp_line (start 1 -0.625) (end -1 -0.625) (layer "B.Fab") (width 0.1) (tstamp 95340c17-2abc-4751-9eaa-ff9103bcdb64))
     (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp e453a778-c765-437d-bd8f-f13a8eced165))
     (pad "1" smd roundrect (at -0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 53 "/Cpu/LED_ORANGE") (pintype "passive") (tstamp 2016ff62-9a3e-4dd9-9bf0-03128a294040))
+      (net 52 "/Cpu/LED_ORANGE") (pintype "passive") (tstamp 2016ff62-9a3e-4dd9-9bf0-03128a294040))
     (pad "2" smd roundrect (at 0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 40 "Net-(D4-Pad2)") (pintype "passive") (tstamp f9288899-9571-41e5-a147-ecd96cb8c666))
+      (net 39 "Net-(D4-Pad2)") (pintype "passive") (tstamp f9288899-9571-41e5-a147-ecd96cb8c666))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3664,9 +3599,9 @@
     (pad "2" smd rect (at 0.35 -0.15 180) (size 0.3 0.3) (layers "B.Cu" "B.Paste" "B.Mask")
       (net 11 "/Power_Charge/Sense_BATT") (pinfunction "K") (pintype "passive") (tstamp cbafcbb8-b605-4278-80d9-442dae63c4ff))
     (pad "3" smd rect (at 1 -1.875 180) (size 0.25 0.25) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 92 "Net-(C6-Pad1)") (pinfunction "A") (pintype "passive") (tstamp 68d107d1-e9da-46c2-b0e3-2c148a6187e6))
+      (net 90 "Net-(C6-Pad1)") (pinfunction "A") (pintype "passive") (tstamp 68d107d1-e9da-46c2-b0e3-2c148a6187e6))
     (pad "3" smd rect (at 1 -1.25 180) (size 1 1.5) (layers "B.Cu" "B.Paste" "B.Mask")
-      (net 92 "Net-(C6-Pad1)") (pinfunction "A") (pintype "passive") (tstamp f9a1a7e3-ca2a-4cf5-9deb-0d72d1672ebe))
+      (net 90 "Net-(C6-Pad1)") (pinfunction "A") (pintype "passive") (tstamp f9a1a7e3-ca2a-4cf5-9deb-0d72d1672ebe))
     (model "${KICAD6_3DMODEL_DIR}/Package_TO_SOT_SMD.3dshapes/Nexperia_CFP15_SOT-1289.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3720,9 +3655,9 @@
     (pad "3" smd roundrect (at -2.575 -0.635 180) (size 1.75 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "Test") (pintype "input") (tstamp dc3038f5-2390-4f5d-ab92-8fc56eacc296))
     (pad "4" smd roundrect (at -2.575 -1.905 180) (size 1.75 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 90 "/Cpu/SHUTDOWN_5V") (pinfunction "SS") (pintype "input") (tstamp d41bf944-8277-427e-8a02-2aba88c902db))
+      (net 88 "/Cpu/SHUTDOWN_5V") (pinfunction "SS") (pintype "input") (tstamp d41bf944-8277-427e-8a02-2aba88c902db))
     (pad "5" smd roundrect (at 2.575 -1.905 180) (size 1.75 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
-      (net 92 "Net-(C6-Pad1)") (pinfunction "VCC") (pintype "power_in") (tstamp a76675b7-b1b6-4dc1-90cf-7106efbe27df))
+      (net 90 "Net-(C6-Pad1)") (pinfunction "VCC") (pintype "power_in") (tstamp a76675b7-b1b6-4dc1-90cf-7106efbe27df))
     (pad "6" smd roundrect (at 2.575 -0.635 180) (size 1.75 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "AGND") (pintype "power_in") (tstamp 0987e646-0bd0-4507-8b35-4df24befdbd3))
     (pad "7" smd roundrect (at 2.575 0.635 180) (size 1.75 0.6) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.25)
@@ -3817,7 +3752,7 @@
     (pad "1" smd roundrect (at -0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 9 "+2V5") (pintype "passive") (tstamp 6ed14150-0386-47e5-920b-8665fadfcb72))
     (pad "2" smd roundrect (at 0.9125 0 180) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 73 "/Cpu/SHUTDOWN") (pintype "passive") (tstamp aa1478b7-0d15-49cb-b631-cf33fcfbeb12))
+      (net 71 "/Cpu/SHUTDOWN") (pintype "passive") (tstamp aa1478b7-0d15-49cb-b631-cf33fcfbeb12))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3901,7 +3836,7 @@
     (pad "1" smd roundrect (at -0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 12 "Net-(C9-Pad1)") (pintype "passive") (tstamp e6760790-a817-4111-8bcc-fd39beff88f6))
     (pad "2" smd roundrect (at 0.9125 0 270) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 92 "Net-(C6-Pad1)") (pintype "passive") (tstamp e2943189-1aa8-4e21-9799-bb11f07040f8))
+      (net 90 "Net-(C6-Pad1)") (pintype "passive") (tstamp e2943189-1aa8-4e21-9799-bb11f07040f8))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
       (offset (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -3941,7 +3876,7 @@
     (fp_line (start -1 0.625) (end 1 0.625) (layer "B.Fab") (width 0.1) (tstamp cd7ff416-78a5-4664-92d3-3bd4ee102e8d))
     (fp_line (start 1 -0.625) (end -1 -0.625) (layer "B.Fab") (width 0.1) (tstamp f56f4d1e-b4fc-4cf3-af8f-a14151f7ee58))
     (pad "1" smd roundrect (at -0.9125 0) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
-      (net 79 "/Cpu/BATTERY_SENSE") (pintype "passive") (tstamp 18bb0580-b213-4c08-a0eb-6548ebc33751))
+      (net 77 "/Cpu/BATTERY_SENSE") (pintype "passive") (tstamp 18bb0580-b213-4c08-a0eb-6548ebc33751))
     (pad "2" smd roundrect (at 0.9125 0) (size 1.025 1.4) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.243902439)
       (net 2 "GND") (pintype "passive") (tstamp b4a66a83-a9a8-4166-8061-503c85a66bf6))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
@@ -3969,10 +3904,8 @@
   (gr_circle locked (center 127.75 70) (end 127.75 68.4) (layer "Edge.Cuts") (width 0.5) (fill none) (tstamp 6985e986-3bd9-4919-8de6-4f618f92417a))
   (gr_line locked (start 167.75 149) (end 172.75 149) (layer "Edge.Cuts") (width 0.5) (tstamp 85b1c874-e15f-44e5-a875-edfbec6368e5))
   (gr_line locked (start 172.75 63) (end 167.75 63) (layer "Edge.Cuts") (width 0.5) (tstamp 8b8dfa05-b45d-4689-b800-56795a4d7efd))
-  (gr_circle locked (center 172.75 123.795455) (end 172.75 123.785455) (layer "Edge.Cuts") (width 0.0001) (fill solid) (tstamp 8e9f76d1-535a-4ebd-8a4a-5b2f645c6d71))
   (gr_circle locked (center 159 125.5) (end 159 125.49) (layer "Edge.Cuts") (width 0.0001) (fill solid) (tstamp 959dc665-ffb6-4008-b6ee-f9e62657f035))
   (gr_circle locked (center 159 86.5) (end 159 86.49) (layer "Edge.Cuts") (width 0.0001) (fill solid) (tstamp 96a222db-7524-4478-afa9-78e9d3128609))
-  (gr_circle locked (center 172.75 88.204545) (end 172.75 88.194545) (layer "Edge.Cuts") (width 0.0001) (fill solid) (tstamp 96ab076d-c503-4a7a-949b-948e3cd54a17))
   (gr_circle locked (center 149 116) (end 149 115.99) (layer "Edge.Cuts") (width 0.0001) (fill solid) (tstamp 9714d992-64e8-46ed-bf42-037390e9e1f0))
   (gr_line locked (start 132.75 149) (end 132.75 140.5) (layer "Edge.Cuts") (width 0.5) (tstamp 97ee9e30-8641-465a-8870-e8650b1636fb))
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@@ -4015,56 +3948,58 @@
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-        (xy 148.803035 104.725538)
-        (xy 148.778349 104.702357)
+        (xy 148.778348 104.702356)
         (xy 148.775507 104.699602)
         (xy 148.75577 104.679865)
         (xy 148.752573 104.677385)
@@ -18109,7 +25736,7 @@
         (xy 145.166232 103.956633)
         (xy 145.165542 103.950072)
         (xy 145.106527 103.768444)
-        (xy 145.076466 103.716376)
+        (xy 145.099682 103.756587)
         (xy 145.018008 103.615125)
         (xy 145.01104 103.603056)
         (xy 144.937863 103.521785)
@@ -18127,40 +25754,36 @@
         (xy 145.215473 103.241556)
         (xy 145.218776 103.247278)
         (xy 145.218777 103.247279)
-        (xy 145.236685 103.278296)
+        (xy 145.239677 103.283478)
         (xy 145.31096 103.406944)
         (xy 145.315378 103.411851)
         (xy 145.315379 103.411852)
-        (xy 145.39925 103.505)
+        (xy 145.365631 103.467662)
         (xy 145.438747 103.548866)
-        (xy 145.507065 103.598502)
-        (xy 145.584372 103.654669)
         (xy 145.593248 103.661118)
         (xy 145.599276 103.663802)
         (xy 145.599278 103.663803)
         (xy 145.761681 103.736109)
         (xy 145.767712 103.738794)
-        (xy 145.861112 103.758647)
+        (xy 145.850861 103.756468)
         (xy 145.948056 103.777128)
         (xy 145.948061 103.777128)
         (xy 145.954513 103.7785)
         (xy 146.145487 103.7785)
         (xy 146.151939 103.777128)
         (xy 146.151944 103.777128)
-        (xy 146.238887 103.758647)
+        (xy 146.249139 103.756468)
         (xy 146.332288 103.738794)
         (xy 146.338319 103.736109)
         (xy 146.500722 103.663803)
         (xy 146.500724 103.663802)
         (xy 146.506752 103.661118)
-        (xy 146.515629 103.654669)
-        (xy 146.592935 103.598502)
         (xy 146.661253 103.548866)
-        (xy 146.70075 103.505)
+        (xy 146.734369 103.467662)
         (xy 146.784621 103.411852)
         (xy 146.784622 103.411851)
         (xy 146.78904 103.406944)
-        (xy 146.863315 103.278296)
+        (xy 146.860323 103.283478)
         (xy 146.881223 103.247279)
         (xy 146.881224 103.247278)
         (xy 146.884527 103.241556)
@@ -18231,7 +25854,7 @@
         (xy 145.478717 100.646757)
         (xy 145.42019 100.672448)
         (xy 145.414109 100.67493)
-        (xy 145.397823 100.681084)
+        (xy 145.39497 100.682162)
         (xy 145.391784 100.683366)
         (xy 145.347247 100.6915)
         (xy 145.319513 100.6915)
@@ -18250,11 +25873,11 @@
         (xy 144.925502 99.694403)
         (xy 144.937858 99.678221)
         (xy 145.01104 99.596944)
-        (xy 145.069314 99.49601)
+        (xy 145.077159 99.482422)
         (xy 145.103223 99.437279)
         (xy 145.103224 99.437278)
         (xy 145.106527 99.431556)
-        (xy 145.133737 99.347813)
+        (xy 145.139231 99.330904)
         (xy 145.145844 99.310552)
         (xy 145.185918 99.251947)
         (xy 145.251315 99.22431)
@@ -18269,7 +25892,7 @@
         (xy 145.431299 99.414097)
         (xy 145.432632 99.416351)
         (xy 145.435685 99.423305)
-        (xy 145.474327 99.473662)
+        (xy 145.470909 99.469208)
         (xy 145.474579 99.473991)
         (xy 145.478459 99.479332)
         (xy 145.510339 99.52572)
@@ -18282,7 +25905,7 @@
         (xy 145.79855 99.81052)
         (xy 145.804404 99.816785)
         (xy 145.842439 99.860385)
-        (xy 145.860197 99.872865)
+        (xy 145.848657 99.864755)
         (xy 145.894697 99.897112)
         (xy 145.899993 99.901045)
         (xy 145.950282 99.940477)
@@ -18339,7 +25962,7 @@
         (xy 148.962568 99.874942)
         (xy 148.957385 99.804135)
         (xy 148.962568 99.786482)
-        (xy 148.97155 99.762524)
+        (xy 148.969813 99.767158)
         (xy 148.996745 99.695316)
         (xy 149.0035 99.633134)
         (xy 149.0035 99.026866)
@@ -18347,7 +25970,7 @@
         (xy 148.962835 98.874229)
         (xy 148.957652 98.803423)
         (xy 148.962835 98.78577)
-        (xy 148.968292 98.771213)
+        (xy 148.993971 98.702715)
         (xy 148.996745 98.695316)
         (xy 149.0035 98.633134)
         (xy 149.0035 98.026866)
@@ -18380,7 +26003,7 @@
         (xy 149.261487 96.452909)
         (xy 149.369798 96.369798)
         (xy 149.452909 96.261487)
-        (xy 149.458096 96.248966)
+        (xy 149.461631 96.240432)
         (xy 149.495591 96.158443)
         (xy 149.540139 96.103162)
         (xy 149.607503 96.080741)
@@ -18460,16 +26083,16 @@
         (xy 127.097251 84.426695)
         (xy 127.097548 84.431848)
         (xy 127.097548 84.431851)
-        (xy 127.104273 84.548479)
+        (xy 127.103968 84.543192)
         (xy 127.11011 84.649715)
         (xy 127.111247 84.654761)
         (xy 127.111248 84.654767)
-        (xy 127.120095 84.694022)
+        (xy 127.119194 84.690023)
         (xy 127.159222 84.867639)
         (xy 127.207352 84.986169)
         (xy 127.23592 85.056524)
         (xy 127.243266 85.074616)
-        (xy 127.281087 85.136334)
+        (xy 127.281787 85.137476)
         (xy 127.357291 85.260688)
         (xy 127.359987 85.265088)
         (xy 127.50625 85.433938)
@@ -18494,20 +26117,20 @@
         (xy 127.397714 86.146411)
         (xy 127.350056 86.216275)
         (xy 127.274743 86.32668)
-        (xy 127.243458 86.394079)
+        (xy 127.24899 86.38216)
         (xy 127.18352 86.523205)
         (xy 127.180688 86.529305)
         (xy 127.120989 86.74457)
         (xy 127.097251 86.966695)
         (xy 127.097548 86.971848)
         (xy 127.097548 86.971851)
-        (xy 127.108995 87.170385)
+        (xy 127.109244 87.174693)
         (xy 127.11011 87.189715)
         (xy 127.111247 87.194761)
         (xy 127.111248 87.194767)
         (xy 127.135304 87.301508)
         (xy 127.159222 87.407639)
-        (xy 127.210243 87.53329)
+        (xy 127.188564 87.4799)
         (xy 127.232865 87.589)
         (xy 127.243266 87.614616)
         (xy 127.267154 87.653598)
@@ -18529,9 +26152,6 @@
         (xy 127.590027 89.561376)
         (xy 127.5815 89.6446)
         (xy 127.5815 90.6954)
-        (xy 127.581837 90.698646)
-        (xy 127.581837 90.69865)
-        (xy 127.588985 90.767538)
         (xy 127.592474 90.801166)
         (xy 127.64845 90.968946)
         (xy 127.741522 91.119348)
@@ -18545,8 +26165,11 @@
         (xy 127.877275 91.797352)
         (xy 127.87858 91.804829)
         (xy 127.87858 91.80483)
+        (xy 127.880703 91.816994)
+        (xy 127.885987 91.847267)
         (xy 127.888261 91.860299)
-        (xy 127.889224 91.866825)
+        (xy 127.889223 91.866821)
+        (xy 127.893199 91.899676)
         (xy 127.896898 91.930242)
         (xy 127.894982 91.930474)
         (xy 127.892258 91.991367)
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_prl b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_prl
index eb641fa..130a151 100644
--- a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_prl
+++ b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_prl
@@ -62,7 +62,7 @@
       35,
       36
     ],
-    "visible_layers": "ffcffff_ffffffff",
+    "visible_layers": "ffcfdff_ffffffff",
     "zone_display_mode": 0
   },
   "meta": {
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_pro b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_pro
index 2288b83..83180ea 100644
--- a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_pro
+++ b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_pro
@@ -44,7 +44,7 @@
         "silk_text_thickness": 0.15,
         "silk_text_upright": false,
         "zones": {
-          "45_degree_only": false,
+          "45_degree_only": true,
           "min_clearance": 0.508
         }
       },
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_sch b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_sch
index d09555a..dfa35b1 100644
--- a/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_sch
+++ b/hardware/pcb/Dumber-v3/dumber-v3/dumber-v3.kicad_sch
@@ -345,6 +345,9 @@
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/bf430e39-c14a-4ff2-b3f9-01704606b17a"
       (reference "#FLG0102") (unit 1) (value "PWR_FLAG") (footprint "")
     )
+    (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/164b46bb-47a3-4594-ae70-2e2ccc0851ea"
+      (reference "#PWR01") (unit 1) (value "GND") (footprint "")
+    )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/fd167bd0-441b-451a-a5e1-0aab203dc3d4"
       (reference "#PWR02") (unit 1) (value "+2V5") (footprint "")
     )
@@ -423,9 +426,6 @@
     (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/6f9a5a58-ab28-4346-bc05-af16f57c158d"
       (reference "#PWR028") (unit 1) (value "GND") (footprint "")
     )
-    (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/a9030619-07d6-40a1-a218-b160d5d918d4"
-      (reference "#PWR029") (unit 1) (value "+2V5") (footprint "")
-    )
     (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/0e54446f-aeb2-4641-9a9e-b60cb11a5233"
       (reference "#PWR030") (unit 1) (value "GND") (footprint "")
     )
@@ -478,7 +478,7 @@
       (reference "C2") (unit 1) (value "68nF") (footprint "Capacitor_SMD:C_0805_2012Metric")
     )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/134fab3f-3d52-45ee-9c4d-4b9cd2356757"
-      (reference "C3") (unit 1) (value "1µF") (footprint "Capacitor_SMD:C_0805_2012Metric")
+      (reference "C3") (unit 1) (value "100µF") (footprint "Capacitor_SMD:C_1210_3225Metric")
     )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/6a3d59a8-c0ed-4965-938e-bb8a6da91426"
       (reference "C4") (unit 1) (value "10nF") (footprint "Capacitor_SMD:C_0805_2012Metric")
@@ -493,13 +493,13 @@
       (reference "C7") (unit 1) (value "1µF") (footprint "Capacitor_SMD:C_0805_2012Metric")
     )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/db04ab93-6753-4375-baed-64e74f12496d"
-      (reference "C8") (unit 1) (value "22µF") (footprint "Capacitor_SMD:C_0805_2012Metric")
+      (reference "C8") (unit 1) (value "100µF") (footprint "Capacitor_SMD:C_1210_3225Metric")
     )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/16366f03-a170-4809-ab0e-52a609d8b01f"
       (reference "C9") (unit 1) (value "100pF") (footprint "Capacitor_SMD:C_0805_2012Metric")
     )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/a63b8def-5f1b-4d9d-bb74-90ccd6d05047"
-      (reference "C10") (unit 1) (value "22µF") (footprint "Capacitor_SMD:C_0805_2012Metric")
+      (reference "C10") (unit 1) (value "100µF") (footprint "Capacitor_SMD:C_1210_3225Metric")
     )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/707c32d4-4845-4691-92d6-ca54beed384c"
       (reference "C11") (unit 1) (value "1µF") (footprint "Capacitor_SMD:C_0805_2012Metric")
@@ -531,6 +531,9 @@
     (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/5ac179f3-da22-4fda-a42d-23a6caf2906d"
       (reference "C20") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0805_2012Metric")
     )
+    (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/6278b169-e9ba-49e9-9fd2-15de3e39aefb"
+      (reference "C21") (unit 1) (value "1nF") (footprint "Capacitor_SMD:C_0805_2012Metric")
+    )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/d735c11c-af51-402c-bf6b-5022004af723"
       (reference "D1") (unit 1) (value "PMEG2020CPA") (footprint "INSA:Nexperia_SOT-1061")
     )
@@ -555,9 +558,6 @@
     (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/eb3899c1-5b12-45e0-8c00-fdefc61483aa"
       (reference "J3") (unit 1) (value "Conn_02x05_Odd_Even") (footprint "Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical_SMD")
     )
-    (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/55f864fb-4849-4d8d-9e04-3291044a27a8"
-      (reference "JP1") (unit 1) (value "Jumper_3_Bridged12") (footprint "Jumper:SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm_NumberLabels")
-    )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/ae93d87b-a48e-48be-af7f-711e740d7cdc"
       (reference "L2") (unit 1) (value "22µH") (footprint "Inductor_SMD:L_Taiyo-Yuden_MD-4040")
     )
@@ -622,7 +622,7 @@
       (reference "R15") (unit 1) (value "1M") (footprint "Resistor_SMD:R_0805_2012Metric")
     )
     (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/5adf52fb-af5a-46ac-94b1-da31d840abc2"
-      (reference "R16") (unit 1) (value "1.5K") (footprint "Resistor_SMD:R_0805_2012Metric")
+      (reference "R16") (unit 1) (value "1K") (footprint "Resistor_SMD:R_0805_2012Metric")
     )
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/6d0a8559-6806-445a-9150-dfd0496b6eb9"
       (reference "R17") (unit 1) (value "150K") (footprint "Resistor_SMD:R_0805_2012Metric")
@@ -636,14 +636,11 @@
     (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/afedd976-fee3-498a-a95d-a679b70be92a"
       (reference "R20") (unit 1) (value "100K") (footprint "Resistor_SMD:R_0805_2012Metric")
     )
-    (path "/3615d78e-1dd3-4b20-9017-3539b8f88e06/0c20669d-295e-45e5-a8a7-340d59f9a6b1"
-      (reference "R21") (unit 1) (value "7,5K") (footprint "Resistor_SMD:R_0805_2012Metric")
-    )
     (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/6584e4cf-80fd-476b-ad9c-e381729bd6ab"
-      (reference "R22") (unit 1) (value "1.5K") (footprint "Resistor_SMD:R_0805_2012Metric")
+      (reference "R22") (unit 1) (value "1K") (footprint "Resistor_SMD:R_0805_2012Metric")
     )
     (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/97d27f4c-b224-4415-b3b6-33cbd34be51c"
-      (reference "R23") (unit 1) (value "1.5K") (footprint "Resistor_SMD:R_0805_2012Metric")
+      (reference "R23") (unit 1) (value "820") (footprint "Resistor_SMD:R_0805_2012Metric")
     )
     (path "/1b100198-bac5-4efe-bc54-3b6ec493e580/b6914fe2-614d-400f-b838-b498fec4ecdb"
       (reference "R24") (unit 1) (value "100K") (footprint "Resistor_SMD:R_0805_2012Metric")
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/fp-info-cache b/hardware/pcb/Dumber-v3/dumber-v3/fp-info-cache
index a6acfa8..f2b8487 100644
--- a/hardware/pcb/Dumber-v3/dumber-v3/fp-info-cache
+++ b/hardware/pcb/Dumber-v3/dumber-v3/fp-info-cache
@@ -1,4 +1,4 @@
-20396245938686076
+20396253180362096
 Audio_Module
 Reverb_BTDR-1H
 Digital Reverberation Unit, http://www.belton.co.kr/inc/downfile.php?seq=17&file=pdf (footprint from http://www.uk-electronic.de/PDF/BTDR-1.pdf)
diff --git a/hardware/pcb/Dumber-v3/dumber-v3/power_charge.kicad_sch b/hardware/pcb/Dumber-v3/dumber-v3/power_charge.kicad_sch
index 682479a..f1ea398 100644
--- a/hardware/pcb/Dumber-v3/dumber-v3/power_charge.kicad_sch
+++ b/hardware/pcb/Dumber-v3/dumber-v3/power_charge.kicad_sch
@@ -1372,6 +1372,9 @@
   (junction (at 73.66 39.37) (diameter 0) (color 0 0 0 0)
     (uuid 351e3e58-43b0-44c6-a68a-270356cd94d1)
   )
+  (junction (at 96.52 130.81) (diameter 0) (color 0 0 0 0)
+    (uuid 357be12d-52b1-475b-b3e8-825c8bbd399e)
+  )
   (junction (at 240.03 114.3) (diameter 0) (color 0 0 0 0)
     (uuid 3ce70885-2410-4a40-9b25-49a283a83f00)
   )
@@ -1538,6 +1541,10 @@
     (uuid 096cff1e-2821-4f29-bb07-41064189aa44)
   )
 
+  (wire (pts (xy 86.36 130.81) (xy 96.52 130.81))
+    (stroke (width 0) (type default) (color 0 0 0 0))
+    (uuid 0e822db9-88ee-4c84-8ccb-5413f38c0288)
+  )
   (wire (pts (xy 29.21 175.26) (xy 36.83 175.26))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 0f57ebba-6d22-4008-b0da-3bc05526e8f8)
@@ -1804,7 +1811,7 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 5ea200fc-8364-4ee7-a7e1-cb5f2e24afc1)
   )
-  (wire (pts (xy 129.54 148.59) (xy 133.35 148.59))
+  (wire (pts (xy 119.38 148.59) (xy 133.35 148.59))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 5f46d14a-0fc6-4fb2-a1d2-46dd70ef43d2)
   )
@@ -1890,10 +1897,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 84b5a90a-10e0-45bc-a339-4adef0fd8738)
   )
-  (wire (pts (xy 119.38 148.59) (xy 121.92 148.59))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 84eb434c-7eb8-4ce1-879f-4aa9e4c79fcb)
-  )
   (polyline (pts (xy 138.43 34.29) (xy 153.67 34.29))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 87654038-ae4c-4250-b87a-27e1baed1282)
@@ -1969,6 +1972,10 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid a4046d1f-82bb-474f-ba54-41ad8b7d0406)
   )
+  (wire (pts (xy 86.36 138.43) (xy 86.36 139.7))
+    (stroke (width 0) (type default) (color 0 0 0 0))
+    (uuid a54c4f56-12d2-4a1f-8299-c92294a2338c)
+  )
   (wire (pts (xy 142.24 172.72) (xy 152.4 172.72))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid a54d30b6-acea-4947-b067-bf134101e406)
@@ -2321,21 +2328,6 @@
     (pin "2" (uuid 0b9f7f6c-789a-45a6-8d38-5d1e7b8b259b))
   )
 
-  (symbol (lib_id "Device:R") (at 125.73 148.59 90) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid 0c20669d-295e-45e5-a8a7-340d59f9a6b1)
-    (property "Reference" "R21" (id 0) (at 125.73 143.8742 90))
-    (property "Value" "7,5K" (id 1) (at 125.73 146.4111 90))
-    (property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 125.73 150.368 90)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "~" (id 3) (at 125.73 148.59 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid 65fd311c-46fa-4325-b40b-1f497aad78ed))
-    (pin "2" (uuid eba59a58-435a-41b4-9f71-1ae17c5e00f2))
-  )
-
   (symbol (lib_id "power:GND") (at 132.08 133.35 0) (unit 1)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 0dd782e0-9e02-4e39-92ca-eecd22392654)
@@ -2389,10 +2381,10 @@
     (property "Reference" "C3" (id 0) (at 67.691 149.0253 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "1µF" (id 1) (at 67.691 151.5622 0)
+    (property "Value" "100µF" (id 1) (at 67.691 151.5622 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "Capacitor_SMD:C_0805_2012Metric" (id 2) (at 65.7352 153.67 0)
+    (property "Footprint" "Capacitor_SMD:C_1210_3225Metric" (id 2) (at 65.7352 153.67 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "Datasheet" "~" (id 3) (at 64.77 149.86 0)
@@ -2421,6 +2413,22 @@
     (pin "2" (uuid 42234153-38fc-439d-b516-c1a17002b585))
   )
 
+  (symbol (lib_id "power:GND") (at 86.36 139.7 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 164b46bb-47a3-4594-ae70-2e2ccc0851ea)
+    (property "Reference" "#PWR01" (id 0) (at 86.36 146.05 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 86.36 144.1434 0))
+    (property "Footprint" "" (id 2) (at 86.36 139.7 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 86.36 139.7 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 7f0fe5ba-6ee0-4cb5-b4ba-68c071699a09))
+  )
+
   (symbol (lib_id "Device:C") (at 120.65 87.63 0) (unit 1)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 290b23d2-ab07-4d64-ad75-994bc73cc28d)
@@ -2600,6 +2608,25 @@
     (pin "1" (uuid 5b73e5f4-35f3-478d-b237-3b5d00a5d8be))
   )
 
+  (symbol (lib_id "Device:C") (at 86.36 134.62 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 6278b169-e9ba-49e9-9fd2-15de3e39aefb)
+    (property "Reference" "C21" (id 0) (at 89.281 133.7853 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "1nF" (id 1) (at 89.281 136.3222 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "Capacitor_SMD:C_0805_2012Metric" (id 2) (at 87.3252 138.43 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 86.36 134.62 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid a4bad89f-89ac-42b4-a013-ee2f3a3249ca))
+    (pin "2" (uuid f1b6fe64-9436-46a3-933a-d8a3ab3a4bc3))
+  )
+
   (symbol (lib_id "power:GND") (at 146.05 59.69 0) (unit 1)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 6356ee3f-ac97-4d3d-ba8f-2922f4be28e3)
@@ -2832,10 +2859,10 @@
     (property "Reference" "C10" (id 0) (at 187.071 103.3053 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "22µF" (id 1) (at 187.071 105.8422 0)
+    (property "Value" "100µF" (id 1) (at 187.071 105.8422 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "Capacitor_SMD:C_0805_2012Metric" (id 2) (at 185.1152 107.95 0)
+    (property "Footprint" "Capacitor_SMD:C_1210_3225Metric" (id 2) (at 185.1152 107.95 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "Datasheet" "~" (id 3) (at 184.15 104.14 0)
@@ -3193,10 +3220,10 @@
     (property "Reference" "C8" (id 0) (at 164.211 103.3053 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "22µF" (id 1) (at 164.211 105.8422 0)
+    (property "Value" "100µF" (id 1) (at 164.211 105.8422 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "Capacitor_SMD:C_0805_2012Metric" (id 2) (at 162.2552 107.95 0)
+    (property "Footprint" "Capacitor_SMD:C_1210_3225Metric" (id 2) (at 162.2552 107.95 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "Datasheet" "~" (id 3) (at 161.29 104.14 0)
diff --git a/software/dumber3/.cproject b/software/dumber3/.cproject
index 1c87d9c..87e49a4 100644
--- a/software/dumber3/.cproject
+++ b/software/dumber3/.cproject
@@ -21,7 +21,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1194953091" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1508870668" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.475855176" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.802392362" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32L010C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include | ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy | ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 ||  ||  || USE_HAL_DRIVER | STM32L010x6 ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L010C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.802392362" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32L010C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include | ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 ||  ||  || USE_HAL_DRIVER | STM32L010x6 ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L010C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1582271634" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/Dumber3}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1329460993" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.635805233" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -102,7 +102,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.824717414" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.242496753" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.176318081" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1275174120" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32L010C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include | ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy | ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 ||  ||  || USE_HAL_DRIVER | STM32L010x6 ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L010C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1275174120" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32L010C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include | ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 ||  ||  || USE_HAL_DRIVER | STM32L010x6 ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L010C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1084432067" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/Dumber3}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.84530615" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1851868879" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -175,4 +175,5 @@
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
 	</storageModule>
+	<storageModule moduleId="refreshScope"/>
 </cproject>
\ No newline at end of file
diff --git a/software/dumber3/.settings/stm32cubeide.project.prefs b/software/dumber3/.settings/stm32cubeide.project.prefs
index 5f630ed..6c2fa2e 100644
--- a/software/dumber3/.settings/stm32cubeide.project.prefs
+++ b/software/dumber3/.settings/stm32cubeide.project.prefs
@@ -1,3 +1,4 @@
 66BE74F758C12D739921AEA421D593D3=1
+8DF89ED150041C4CBC7CB9A9CAA90856=F6D4FB8752309FD4FF5082AF3D7E281B
 DC22A860405A8BF2F2C095E5B6529F12=F6D4FB8752309FD4FF5082AF3D7E281B
 eclipse.preferences.version=1
diff --git a/software/dumber3/Core/Inc/FreeRTOSConfig.h b/software/dumber3/Core/Inc/FreeRTOSConfig.h
index 1c9fcf2..3663fed 100644
--- a/software/dumber3/Core/Inc/FreeRTOSConfig.h
+++ b/software/dumber3/Core/Inc/FreeRTOSConfig.h
@@ -65,7 +65,7 @@
 #define configTICK_RATE_HZ                       ((TickType_t)100)
 #define configMAX_PRIORITIES                     ( 56 )
 #define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
-#define configTOTAL_HEAP_SIZE                    ((size_t)3072)
+#define configTOTAL_HEAP_SIZE                    ((size_t)2048)
 #define configMAX_TASK_NAME_LEN                  ( 16 )
 #define configUSE_TRACE_FACILITY                 1
 #define configUSE_16_BIT_TICKS                   0
diff --git a/software/dumber3/Core/Inc/batterie.h b/software/dumber3/Core/Inc/batterie.h
new file mode 100644
index 0000000..99419ed
--- /dev/null
+++ b/software/dumber3/Core/Inc/batterie.h
@@ -0,0 +1,13 @@
+/*
+ * batterie.h
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+#ifndef INC_BATTERIE_H_
+#define INC_BATTERIE_H_
+
+
+
+#endif /* INC_BATTERIE_H_ */
diff --git a/software/dumber3/Core/Inc/config.h b/software/dumber3/Core/Inc/config.h
new file mode 100644
index 0000000..d1e055f
--- /dev/null
+++ b/software/dumber3/Core/Inc/config.h
@@ -0,0 +1,18 @@
+/*
+ * config.h
+ *
+ *  Created on: 14 sept. 2022
+ *      Author: dimercur
+ */
+#include "stm32l0xx_hal.h"
+#include "cmsis_os.h"
+
+#define STACK_SIZE 					100
+
+#define PriorityMoteurs        		(configMAX_PRIORITIES -1)
+#define PriorityXbee 				(configMAX_PRIORITIES -2)
+#define PriorityBatterie			(configMAX_PRIORITIES -3)
+#define PrioritySequenceur			(configMAX_PRIORITIES -4)
+#define PriorityLeds    			(configMAX_PRIORITIES -5)
+
+TickType_t msToTicks(TickType_t ms);
diff --git a/software/dumber3/Core/Inc/leds.h b/software/dumber3/Core/Inc/leds.h
new file mode 100644
index 0000000..6391a06
--- /dev/null
+++ b/software/dumber3/Core/Inc/leds.h
@@ -0,0 +1,33 @@
+/*
+ * leds.h
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+#ifndef INC_LEDS_H_
+#define INC_LEDS_H_
+
+typedef enum {
+	leds_off=0,
+	leds_idle,
+	leds_connecte,
+	leds_watchdog_expire,
+	leds_niveau_bat_0,
+	leds_niveau_bat_1,
+	leds_niveau_bat_2,
+	leds_niveau_bat_3,
+	leds_niveau_bat_4,
+	leds_niveau_bat_5,
+	leds_charge_bat_0,
+	leds_charge_bat_1,
+	leds_charge_bat_2,
+	leds_charge_bat_3,
+	leds_charge_bat_4,
+	leds_charge_bat_5,
+	leds_erreur
+} LEDS_State;
+
+void LEDS_Init(void);
+void LEDS_RegleAnimation(LEDS_State etat);
+#endif /* INC_LEDS_H_ */
diff --git a/software/dumber3/Core/Inc/main.h b/software/dumber3/Core/Inc/main.h
index 41e4dd1..d236688 100644
--- a/software/dumber3/Core/Inc/main.h
+++ b/software/dumber3/Core/Inc/main.h
@@ -32,6 +32,16 @@ extern "C" {
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
+#include "cmsis_os.h"
+
+#include "config.h"
+
+#include "messages.h"
+#include "leds.h"
+#include "moteurs.h"
+#include "batterie.h"
+#include "sequenceur.h"
+#include "xbee.h"
 
 /* USER CODE END Includes */
 
diff --git a/software/dumber3/Core/Inc/messages.h b/software/dumber3/Core/Inc/messages.h
new file mode 100644
index 0000000..610b51d
--- /dev/null
+++ b/software/dumber3/Core/Inc/messages.h
@@ -0,0 +1,48 @@
+/*
+ * messages.h
+ *
+ *  Created on: 14 sept. 2022
+ *      Author: dimercur
+ */
+
+#ifndef INC_MESSAGES_H_
+#define INC_MESSAGES_H_
+
+#include "main.h"
+#include "queue.h"
+
+typedef struct {
+	uint16_t id;
+	QueueHandle_t* sender;
+	void *data;
+} MESSAGE_Typedef;
+
+extern QueueHandle_t LEDS_Mailbox;
+extern QueueHandle_t MOTEURS_Mailbox;
+extern QueueHandle_t SEQUENCEUR_Mailbox;
+extern QueueHandle_t BATTERIE_Mailbox;
+extern QueueHandle_t XBEE_Mailbox;
+
+#define MSG_ID_NO_MESSAGE		0xFFFF
+
+#define MSG_ID_LED_ETAT			0
+
+#define MSG_ID_BAT_NIVEAU		0
+#define MSG_ID_BAT_CHARGE		1
+#define MSG_ID_BAT_CHARGEUR_ON	2
+#define MSG_ID_BAT_CHARGEUR_OFF	3
+#define MSG_ID_BAT_CHARGEUR_ERR	4
+
+#define MSG_ID_MOTEURS_MARCHE	0
+#define MSG_ID_MOTEURS_ARRET	0
+
+#define MSG_ID_XBEE_CMD_VALIDE		0
+#define MSG_ID_XBEE_CMD_INVALIDE	1
+#define MSG_ID_XBEE_REPONSE			2
+
+void MESSAGE_Init(void);
+MESSAGE_Typedef MESSAGE_ReadMailbox(QueueHandle_t mbx);
+MESSAGE_Typedef MESSAGE_ReadMailboxNoDelay(QueueHandle_t mbx);
+void MESSAGE_SendMailbox(QueueHandle_t mbx_dest, uint16_t id, QueueHandle_t mbx_sender, void *data);
+
+#endif /* INC_MESSAGES_H_ */
diff --git a/software/dumber3/Core/Inc/moteurs.h b/software/dumber3/Core/Inc/moteurs.h
new file mode 100644
index 0000000..52742ab
--- /dev/null
+++ b/software/dumber3/Core/Inc/moteurs.h
@@ -0,0 +1,15 @@
+/*
+ * moteurs.h
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+#ifndef INC_MOTEURS_H_
+#define INC_MOTEURS_H_
+
+void MOTEURS_Init(void);
+//void MOTEURS_Set(uint8_t mot, int16_t val);
+void MOTEURS_Test (void);
+
+#endif /* INC_MOTEURS_H_ */
diff --git a/software/dumber3/Core/Inc/sequenceur.h b/software/dumber3/Core/Inc/sequenceur.h
new file mode 100644
index 0000000..9577f0f
--- /dev/null
+++ b/software/dumber3/Core/Inc/sequenceur.h
@@ -0,0 +1,13 @@
+/*
+ * statemachine.h
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+#ifndef INC_SEQUENCEUR_H_
+#define INC_SEQUENCEUR_H_
+
+
+
+#endif /* INC_SEQUENCEUR_H_ */
diff --git a/software/dumber3/Core/Inc/xbee.h b/software/dumber3/Core/Inc/xbee.h
new file mode 100644
index 0000000..07b4bf8
--- /dev/null
+++ b/software/dumber3/Core/Inc/xbee.h
@@ -0,0 +1,13 @@
+/*
+ * xbee.h
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+#ifndef INC_XBEE_H_
+#define INC_XBEE_H_
+
+
+
+#endif /* INC_XBEE_H_ */
diff --git a/software/dumber3/Core/Src/batterie.c b/software/dumber3/Core/Src/batterie.c
new file mode 100644
index 0000000..2c288e6
--- /dev/null
+++ b/software/dumber3/Core/Src/batterie.c
@@ -0,0 +1,8 @@
+/*
+ * batterie.c
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+
diff --git a/software/dumber3/Core/Src/leds.c b/software/dumber3/Core/Src/leds.c
new file mode 100644
index 0000000..790033b
--- /dev/null
+++ b/software/dumber3/Core/Src/leds.c
@@ -0,0 +1,202 @@
+/*
+ * leds.h
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+#include "main.h"
+
+#define LEDS_AllumeVerte() HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET)
+#define LEDS_AllumeJaune() HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_SET)
+#define LEDS_AllumeRouge() HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET)
+#define LEDS_EteintVerte() HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET)
+#define LEDS_EteintJaune() HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_RESET)
+#define LEDS_EteintRouge() HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET)
+
+LEDS_State LEDS_Animation;
+LEDS_State LEDS_AnimationAncien;
+
+StaticTask_t xTaskLeds;
+
+/* Buffer that the task being created will use as its stack.  Note this is
+    an array of StackType_t variables.  The size of StackType_t is dependent on
+    the RTOS port. */
+StackType_t xStackLeds[ STACK_SIZE ];
+TaskHandle_t xHandleLeds = NULL;
+
+void LEDS_AnimationThread(void* params);
+
+void LEDS_Init(void) {
+	LEDS_EteintVerte();
+	LEDS_EteintJaune();
+	LEDS_EteintRouge();
+
+	LEDS_Animation=leds_off;
+
+	/* Mailbox is created in messages.c */
+
+	/* Create the task without using any dynamic memory allocation. */
+	xHandleLeds = xTaskCreateStatic(
+			LEDS_AnimationThread,       /* Function that implements the task. */
+			"LEDS Animation",          /* Text name for the task. */
+			STACK_SIZE,      /* Number of indexes in the xStack array. */
+			NULL,    /* Parameter passed into the task. */
+			PriorityLeds,/* Priority at which the task is created. */
+			xStackLeds,          /* Array to use as the task's stack. */
+			&xTaskLeds);  /* Variable to hold the task's data structure. */
+	vTaskResume(xHandleLeds);
+}
+
+void LEDS_RegleAnimation(LEDS_State etat) {
+	LEDS_Animation=etat;
+}
+
+void LEDS_AnimationThread(void* params) {
+	MESSAGE_Typedef msg;
+	uint8_t cnt=0;
+
+	while (1) {
+		vTaskDelay(pdMS_TO_TICKS(100));
+
+		msg = MESSAGE_ReadMailboxNoDelay(LEDS_Mailbox);
+
+		cnt++;
+
+		if (msg.id == MSG_ID_LED_ETAT) { // Si c'est bien un message de changemnet d'etat LEDS
+			LEDS_Animation = *((LEDS_State*)msg.data);
+
+			if (LEDS_Animation != LEDS_AnimationAncien) { 	// si le nouvel etat est different de l'ancien
+				// dans ce cas, on eteint les leds pour repartir sur une base saine
+				LEDS_AnimationAncien = LEDS_Animation;
+
+				LEDS_EteintVerte();
+				LEDS_EteintJaune();
+				LEDS_EteintRouge();
+				cnt=0;
+			}
+		}
+
+		switch (LEDS_Animation) {
+		case leds_off:
+			LEDS_EteintVerte();
+			LEDS_EteintJaune();
+			LEDS_EteintRouge();
+			break;
+		case leds_idle:
+			if (cnt<5)
+				LEDS_AllumeVerte();
+			else if (cnt<10)
+				LEDS_EteintVerte();
+			else
+				cnt=0;
+			break;
+		case leds_connecte:
+			LEDS_AllumeVerte();
+			break;
+		case leds_watchdog_expire:
+			if (cnt<5)
+				LEDS_AllumeRouge();
+			else if (cnt<10)
+				LEDS_EteintRouge();
+			else
+				cnt=0;
+			break;
+		case leds_niveau_bat_0:
+			if (!(cnt%2))
+				LEDS_AllumeRouge();
+			else
+				LEDS_EteintRouge();
+			break;
+		case leds_niveau_bat_1:
+			LEDS_AllumeRouge();
+			break;
+		case leds_niveau_bat_2:
+			LEDS_AllumeRouge();
+
+			if (cnt<3)
+				LEDS_AllumeJaune();
+			else if (cnt<6)
+				LEDS_EteintJaune();
+			else
+				cnt=0;
+			break;
+		case leds_niveau_bat_3:
+			LEDS_AllumeRouge();
+			LEDS_AllumeJaune();
+			break;
+		case leds_niveau_bat_4:
+			LEDS_AllumeRouge();
+			LEDS_AllumeJaune();
+
+			if (cnt<3)
+				LEDS_AllumeVerte();
+			else if (cnt<6)
+				LEDS_EteintVerte();
+			else
+				cnt=0;
+			break;
+		case leds_niveau_bat_5:
+			LEDS_AllumeRouge();
+			LEDS_AllumeJaune();
+			LEDS_AllumeVerte();
+			break;
+		case leds_charge_bat_0:
+		case leds_charge_bat_1:
+			if (cnt<3)
+				LEDS_AllumeRouge();
+			else if (cnt<6)
+				LEDS_AllumeJaune();
+			else if (cnt<9)
+				LEDS_AllumeVerte();
+			else if (cnt<12){
+				LEDS_EteintVerte();
+				LEDS_EteintJaune();
+				LEDS_EteintRouge();
+			} else
+				cnt=0;
+			break;
+		case leds_charge_bat_2:
+		case leds_charge_bat_3:
+			LEDS_AllumeRouge();
+			if (cnt<3)
+				LEDS_AllumeJaune();
+			else if (cnt<6)
+				LEDS_AllumeVerte();
+			else if (cnt <9){
+				LEDS_EteintVerte();
+				LEDS_EteintJaune();
+			} else
+				cnt=0;
+			break;
+		case leds_charge_bat_4:
+		case leds_charge_bat_5:
+			LEDS_AllumeRouge();
+			LEDS_AllumeJaune();
+
+			if (cnt<3)
+				LEDS_AllumeVerte();
+			else if (cnt<6)
+				LEDS_EteintVerte();
+			else
+				cnt=0;
+			break;
+		case leds_erreur:
+			if (cnt<5) {
+				LEDS_AllumeRouge();
+				LEDS_AllumeJaune();
+				LEDS_AllumeVerte();
+			}
+			else if (cnt<10) {
+				LEDS_EteintRouge();
+				LEDS_EteintJaune();
+				LEDS_EteintVerte();
+			}
+			else
+				cnt=0;
+			break;
+		default:
+			break;
+		}
+	}
+}
diff --git a/software/dumber3/Core/Src/main.c b/software/dumber3/Core/Src/main.c
index 3526ccd..663141d 100644
--- a/software/dumber3/Core/Src/main.c
+++ b/software/dumber3/Core/Src/main.c
@@ -1,28 +1,35 @@
 /* USER CODE BEGIN Header */
 /**
-  ******************************************************************************
-  * @file           : main.c
-  * @brief          : Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2022 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
+ ******************************************************************************
+ * @file           : main.c
+ * @brief          : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
+#include <sequenceur.h>
 #include "main.h"
 #include "cmsis_os.h"
 
+
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
+#include "moteurs.h"
+#include "leds.h"
+#include "xbee.h"
+#include "batterie.h"
+#include "messages.h"
 
 /* USER CODE END Includes */
 
@@ -55,9 +62,9 @@ TIM_HandleTypeDef htim21;
 /* Definitions for defaultTask */
 osThreadId_t defaultTaskHandle;
 const osThreadAttr_t defaultTask_attributes = {
-  .name = "defaultTask",
-  .stack_size = 128 * 4,
-  .priority = (osPriority_t) osPriorityNormal,
+		.name = "defaultTask",
+		.stack_size = 128 * 4,
+		.priority = (osPriority_t) osPriorityNormal,
 };
 /* USER CODE BEGIN PV */
 
@@ -84,491 +91,527 @@ void StartDefaultTask(void *argument);
 /* USER CODE END 0 */
 
 /**
-  * @brief  The application entry point.
-  * @retval int
-  */
+ * @brief  The application entry point.
+ * @retval int
+ */
 int main(void)
 {
-  /* USER CODE BEGIN 1 */
+	/* USER CODE BEGIN 1 */
 
-  /* USER CODE END 1 */
+	/* USER CODE END 1 */
 
-  /* MCU Configuration--------------------------------------------------------*/
+	/* MCU Configuration--------------------------------------------------------*/
 
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-  HAL_Init();
+	/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+	HAL_Init();
 
-  /* USER CODE BEGIN Init */
+	/* USER CODE BEGIN Init */
 
-  /* USER CODE END Init */
+	/* USER CODE END Init */
 
-  /* Configure the system clock */
-  SystemClock_Config();
+	/* Configure the system clock */
+	SystemClock_Config();
 
-  /* USER CODE BEGIN SysInit */
+	/* USER CODE BEGIN SysInit */
 
-  /* USER CODE END SysInit */
+	/* USER CODE END SysInit */
 
-  /* Initialize all configured peripherals */
-  MX_GPIO_Init();
-  MX_DMA_Init();
-  MX_LPTIM1_Init();
-  MX_LPUART1_UART_Init();
-  MX_TIM2_Init();
-  MX_TIM21_Init();
-  MX_ADC_Init();
-  /* USER CODE BEGIN 2 */
+	/* Initialize all configured peripherals */
+	MX_GPIO_Init();
+	MX_DMA_Init();
+	MX_LPTIM1_Init();
+	MX_LPUART1_UART_Init();
+	MX_TIM2_Init();
+	MX_TIM21_Init();
+	MX_ADC_Init();
+	/* USER CODE BEGIN 2 */
+	/* Init des messages box */
+	MESSAGE_Init();
 
-  /* USER CODE END 2 */
+	LEDS_Init();
 
-  /* Init scheduler */
-  osKernelInitialize();
+	/*MOTEURS_Init();
+  MOTEURS_Test();*/
+	/* USER CODE END 2 */
 
-  /* USER CODE BEGIN RTOS_MUTEX */
-  /* add mutexes, ... */
-  /* USER CODE END RTOS_MUTEX */
+	/* Init scheduler */
+	osKernelInitialize();
 
-  /* USER CODE BEGIN RTOS_SEMAPHORES */
-  /* add semaphores, ... */
-  /* USER CODE END RTOS_SEMAPHORES */
+	/* USER CODE BEGIN RTOS_MUTEX */
+	/* add mutexes, ... */
+	/* USER CODE END RTOS_MUTEX */
 
-  /* USER CODE BEGIN RTOS_TIMERS */
-  /* start timers, add new ones, ... */
-  /* USER CODE END RTOS_TIMERS */
+	/* USER CODE BEGIN RTOS_SEMAPHORES */
+	/* add semaphores, ... */
+	/* USER CODE END RTOS_SEMAPHORES */
 
-  /* USER CODE BEGIN RTOS_QUEUES */
-  /* add queues, ... */
-  /* USER CODE END RTOS_QUEUES */
+	/* USER CODE BEGIN RTOS_TIMERS */
+	/* start timers, add new ones, ... */
+	/* USER CODE END RTOS_TIMERS */
 
-  /* Create the thread(s) */
-  /* creation of defaultTask */
-  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
+	/* USER CODE BEGIN RTOS_QUEUES */
+	/* add queues, ... */
+	/* USER CODE END RTOS_QUEUES */
 
-  /* USER CODE BEGIN RTOS_THREADS */
-  /* add threads, ... */
-  /* USER CODE END RTOS_THREADS */
+	/* Create the thread(s) */
+	/* creation of defaultTask */
+	defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
 
-  /* USER CODE BEGIN RTOS_EVENTS */
-  /* add events, ... */
-  /* USER CODE END RTOS_EVENTS */
+	/* USER CODE BEGIN RTOS_THREADS */
+	/* add threads, ... */
 
-  /* Start scheduler */
-  osKernelStart();
+	/* USER CODE END RTOS_THREADS */
 
-  /* We should never get here as control is now taken by the scheduler */
-  /* Infinite loop */
-  /* USER CODE BEGIN WHILE */
-  while (1)
-  {
-    /* USER CODE END WHILE */
+	/* USER CODE BEGIN RTOS_EVENTS */
+	/* add events, ... */
+	/* USER CODE END RTOS_EVENTS */
 
-    /* USER CODE BEGIN 3 */
-  }
-  /* USER CODE END 3 */
+	/* Start scheduler */
+	osKernelStart();
+
+	/* We should never get here as control is now taken by the scheduler */
+	/* Infinite loop */
+	/* USER CODE BEGIN WHILE */
+	while (1)
+	{
+		/* USER CODE END WHILE */
+
+		/* USER CODE BEGIN 3 */
+	}
+	/* USER CODE END 3 */
 }
 
 /**
-  * @brief System Clock Configuration
-  * @retval None
-  */
+ * @brief System Clock Configuration
+ * @retval None
+ */
 void SystemClock_Config(void)
 {
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+	RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+	RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+	RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure the main internal regulator output voltage
-  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the RCC Oscillators according to the specified parameters
-  * in the RCC_OscInitTypeDef structure.
-  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
-  RCC_OscInitStruct.MSICalibrationValue = 0;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /** Initializes the CPU, AHB and APB buses clocks
-  */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+	/** Configure the main internal regulator output voltage
+	 */
+	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+	/** Initializes the RCC Oscillators according to the specified parameters
+	 * in the RCC_OscInitTypeDef structure.
+	 */
+	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+	RCC_OscInitStruct.HSIState = RCC_HSI_DIV4;
+	RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_3;
+	RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	/** Initializes the CPU, AHB and APB buses clocks
+	 */
+	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+			|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_LPTIM1;
-  PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
-  PeriphClkInit.LptimClockSelection = RCC_LPTIM1CLKSOURCE_PCLK;
+	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_LPTIM1;
+	PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+	PeriphClkInit.LptimClockSelection = RCC_LPTIM1CLKSOURCE_PCLK;
 
-  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
-  {
-    Error_Handler();
-  }
+	if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+	{
+		Error_Handler();
+	}
 }
 
 /**
-  * @brief ADC Initialization Function
-  * @param None
-  * @retval None
-  */
+ * @brief ADC Initialization Function
+ * @param None
+ * @retval None
+ */
 static void MX_ADC_Init(void)
 {
 
-  /* USER CODE BEGIN ADC_Init 0 */
+	/* USER CODE BEGIN ADC_Init 0 */
 
-  /* USER CODE END ADC_Init 0 */
+	/* USER CODE END ADC_Init 0 */
 
-  ADC_ChannelConfTypeDef sConfig = {0};
+	ADC_ChannelConfTypeDef sConfig = {0};
 
-  /* USER CODE BEGIN ADC_Init 1 */
+	/* USER CODE BEGIN ADC_Init 1 */
 
-  /* USER CODE END ADC_Init 1 */
-  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
-  */
-  hadc.Instance = ADC1;
-  hadc.Init.OversamplingMode = DISABLE;
-  hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1;
-  hadc.Init.Resolution = ADC_RESOLUTION_12B;
-  hadc.Init.SamplingTime = ADC_SAMPLETIME_160CYCLES_5;
-  hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
-  hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
-  hadc.Init.ContinuousConvMode = DISABLE;
-  hadc.Init.DiscontinuousConvMode = DISABLE;
-  hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
-  hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
-  hadc.Init.DMAContinuousRequests = DISABLE;
-  hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
-  hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
-  hadc.Init.LowPowerAutoWait = DISABLE;
-  hadc.Init.LowPowerFrequencyMode = ENABLE;
-  hadc.Init.LowPowerAutoPowerOff = DISABLE;
-  if (HAL_ADC_Init(&hadc) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /** Configure for the selected ADC regular channel to be converted.
-  */
-  sConfig.Channel = ADC_CHANNEL_0;
-  sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
-  if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN ADC_Init 2 */
+	/* USER CODE END ADC_Init 1 */
+	/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
+	 */
+	hadc.Instance = ADC1;
+	hadc.Init.OversamplingMode = DISABLE;
+	hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1;
+	hadc.Init.Resolution = ADC_RESOLUTION_8B;
+	hadc.Init.SamplingTime = ADC_SAMPLETIME_160CYCLES_5;
+	hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
+	hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+	hadc.Init.ContinuousConvMode = DISABLE;
+	hadc.Init.DiscontinuousConvMode = DISABLE;
+	hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+	hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+	hadc.Init.DMAContinuousRequests = DISABLE;
+	hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+	hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+	hadc.Init.LowPowerAutoWait = DISABLE;
+	hadc.Init.LowPowerFrequencyMode = DISABLE;
+	hadc.Init.LowPowerAutoPowerOff = DISABLE;
+	if (HAL_ADC_Init(&hadc) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	/** Configure for the selected ADC regular channel to be converted.
+	 */
+	sConfig.Channel = ADC_CHANNEL_0;
+	sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+	if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	/* USER CODE BEGIN ADC_Init 2 */
 
-  /* USER CODE END ADC_Init 2 */
+	/* USER CODE END ADC_Init 2 */
 
 }
 
 /**
-  * @brief LPTIM1 Initialization Function
-  * @param None
-  * @retval None
-  */
+ * @brief LPTIM1 Initialization Function
+ * @param None
+ * @retval None
+ */
 static void MX_LPTIM1_Init(void)
 {
 
-  /* USER CODE BEGIN LPTIM1_Init 0 */
+	/* USER CODE BEGIN LPTIM1_Init 0 */
 
-  /* USER CODE END LPTIM1_Init 0 */
+	/* USER CODE END LPTIM1_Init 0 */
 
-  /* USER CODE BEGIN LPTIM1_Init 1 */
+	/* USER CODE BEGIN LPTIM1_Init 1 */
 
-  /* USER CODE END LPTIM1_Init 1 */
-  hlptim1.Instance = LPTIM1;
-  hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
-  hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
-  hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING;
-  hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION;
-  hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
-  hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
-  hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
-  hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL;
-  if (HAL_LPTIM_Init(&hlptim1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN LPTIM1_Init 2 */
+	/* USER CODE END LPTIM1_Init 1 */
+	hlptim1.Instance = LPTIM1;
+	hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
+	hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
+	hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING;
+	hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION;
+	hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
+	hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
+	hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
+	hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL;
+	if (HAL_LPTIM_Init(&hlptim1) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	/* USER CODE BEGIN LPTIM1_Init 2 */
 
-  /* USER CODE END LPTIM1_Init 2 */
+	/* USER CODE END LPTIM1_Init 2 */
 
 }
 
 /**
-  * @brief LPUART1 Initialization Function
-  * @param None
-  * @retval None
-  */
+ * @brief LPUART1 Initialization Function
+ * @param None
+ * @retval None
+ */
 static void MX_LPUART1_UART_Init(void)
 {
 
-  /* USER CODE BEGIN LPUART1_Init 0 */
+	/* USER CODE BEGIN LPUART1_Init 0 */
 
-  /* USER CODE END LPUART1_Init 0 */
+	/* USER CODE END LPUART1_Init 0 */
 
-  /* USER CODE BEGIN LPUART1_Init 1 */
+	/* USER CODE BEGIN LPUART1_Init 1 */
 
-  /* USER CODE END LPUART1_Init 1 */
-  hlpuart1.Instance = LPUART1;
-  hlpuart1.Init.BaudRate = 9600;
-  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
-  hlpuart1.Init.StopBits = UART_STOPBITS_1;
-  hlpuart1.Init.Parity = UART_PARITY_NONE;
-  hlpuart1.Init.Mode = UART_MODE_TX_RX;
-  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
-  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
-  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
-  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN LPUART1_Init 2 */
+	/* USER CODE END LPUART1_Init 1 */
+	hlpuart1.Instance = LPUART1;
+	hlpuart1.Init.BaudRate = 9600;
+	hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+	hlpuart1.Init.StopBits = UART_STOPBITS_1;
+	hlpuart1.Init.Parity = UART_PARITY_NONE;
+	hlpuart1.Init.Mode = UART_MODE_TX_RX;
+	hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+	hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+	hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+	if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	/* USER CODE BEGIN LPUART1_Init 2 */
 
-  /* USER CODE END LPUART1_Init 2 */
+	/* USER CODE END LPUART1_Init 2 */
 
 }
 
 /**
-  * @brief TIM2 Initialization Function
-  * @param None
-  * @retval None
-  */
+ * @brief TIM2 Initialization Function
+ * @param None
+ * @retval None
+ */
 static void MX_TIM2_Init(void)
 {
 
-  /* USER CODE BEGIN TIM2_Init 0 */
+	/* USER CODE BEGIN TIM2_Init 0 */
 
-  /* USER CODE END TIM2_Init 0 */
+	/* USER CODE END TIM2_Init 0 */
 
-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
-  TIM_MasterConfigTypeDef sMasterConfig = {0};
-  TIM_OC_InitTypeDef sConfigOC = {0};
+	TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+	TIM_MasterConfigTypeDef sMasterConfig = {0};
+	TIM_OC_InitTypeDef sConfigOC = {0};
 
-  /* USER CODE BEGIN TIM2_Init 1 */
+	/* USER CODE BEGIN TIM2_Init 1 */
 
-  /* USER CODE END TIM2_Init 1 */
-  htim2.Instance = TIM2;
-  htim2.Init.Prescaler = 0;
-  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
-  htim2.Init.Period = 65535;
-  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
-  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
-  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
-  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
-  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
-  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sConfigOC.OCMode = TIM_OCMODE_PWM1;
-  sConfigOC.Pulse = 0;
-  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
-  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
-  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN TIM2_Init 2 */
+	/* USER CODE END TIM2_Init 1 */
+	htim2.Instance = TIM2;
+	htim2.Init.Prescaler = 0;
+	htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+	htim2.Init.Period = 255;
+	htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+	htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+	if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+	if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+	sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+	if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	sConfigOC.OCMode = TIM_OCMODE_PWM1;
+	sConfigOC.Pulse = 0;
+	sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+	sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+	if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	/* USER CODE BEGIN TIM2_Init 2 */
 
-  /* USER CODE END TIM2_Init 2 */
-  HAL_TIM_MspPostInit(&htim2);
+	/* USER CODE END TIM2_Init 2 */
+	HAL_TIM_MspPostInit(&htim2);
 
 }
 
 /**
-  * @brief TIM21 Initialization Function
-  * @param None
-  * @retval None
-  */
+ * @brief TIM21 Initialization Function
+ * @param None
+ * @retval None
+ */
 static void MX_TIM21_Init(void)
 {
 
-  /* USER CODE BEGIN TIM21_Init 0 */
+	/* USER CODE BEGIN TIM21_Init 0 */
 
-  /* USER CODE END TIM21_Init 0 */
+	/* USER CODE END TIM21_Init 0 */
 
-  TIM_Encoder_InitTypeDef sConfig = {0};
-  TIM_MasterConfigTypeDef sMasterConfig = {0};
+	TIM_Encoder_InitTypeDef sConfig = {0};
+	TIM_MasterConfigTypeDef sMasterConfig = {0};
 
-  /* USER CODE BEGIN TIM21_Init 1 */
+	/* USER CODE BEGIN TIM21_Init 1 */
 
-  /* USER CODE END TIM21_Init 1 */
-  htim21.Instance = TIM21;
-  htim21.Init.Prescaler = 0;
-  htim21.Init.CounterMode = TIM_COUNTERMODE_UP;
-  htim21.Init.Period = 65535;
-  htim21.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
-  htim21.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
-  sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
-  sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
-  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
-  sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
-  sConfig.IC1Filter = 0;
-  sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
-  sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
-  sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
-  sConfig.IC2Filter = 0;
-  if (HAL_TIM_Encoder_Init(&htim21, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
-  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
-  if (HAL_TIMEx_MasterConfigSynchronization(&htim21, &sMasterConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN TIM21_Init 2 */
+	/* USER CODE END TIM21_Init 1 */
+	htim21.Instance = TIM21;
+	htim21.Init.Prescaler = 0;
+	htim21.Init.CounterMode = TIM_COUNTERMODE_UP;
+	htim21.Init.Period = 65535;
+	htim21.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+	htim21.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+	sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
+	sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
+	sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+	sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
+	sConfig.IC1Filter = 0;
+	sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
+	sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
+	sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
+	sConfig.IC2Filter = 0;
+	if (HAL_TIM_Encoder_Init(&htim21, &sConfig) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+	sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+	if (HAL_TIMEx_MasterConfigSynchronization(&htim21, &sMasterConfig) != HAL_OK)
+	{
+		Error_Handler();
+	}
+	/* USER CODE BEGIN TIM21_Init 2 */
 
-  /* USER CODE END TIM21_Init 2 */
+	/* USER CODE END TIM21_Init 2 */
 
 }
 
 /**
-  * Enable DMA controller clock
-  */
+ * Enable DMA controller clock
+ */
 static void MX_DMA_Init(void)
 {
 
-  /* DMA controller clock enable */
-  __HAL_RCC_DMA1_CLK_ENABLE();
+	/* DMA controller clock enable */
+	__HAL_RCC_DMA1_CLK_ENABLE();
 
-  /* DMA interrupt init */
-  /* DMA1_Channel2_3_IRQn interrupt configuration */
-  HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3, 0);
-  HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+	/* DMA interrupt init */
+	/* DMA1_Channel2_3_IRQn interrupt configuration */
+	HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3, 0);
+	HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
 
 }
 
 /**
-  * @brief GPIO Initialization Function
-  * @param None
-  * @retval None
-  */
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
 static void MX_GPIO_Init(void)
 {
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
+	GPIO_InitTypeDef GPIO_InitStruct = {0};
 
-  /* GPIO Ports Clock Enable */
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
+	/* GPIO Ports Clock Enable */
+	__HAL_RCC_GPIOC_CLK_ENABLE();
+	__HAL_RCC_GPIOA_CLK_ENABLE();
+	__HAL_RCC_GPIOB_CLK_ENABLE();
 
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOB, LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin|SHUTDOWN_ENCODERS_Pin
-                          |SHUTDOWN_5V_Pin|SHUTDOWN_Pin, GPIO_PIN_RESET);
+	/*Configure GPIO pin Output Level */
+	HAL_GPIO_WritePin(GPIOB, LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin|SHUTDOWN_ENCODERS_Pin
+			|SHUTDOWN_5V_Pin, GPIO_PIN_RESET);
 
-  /*Configure GPIO pins : LED_ROUGE_Pin LED_ORANGE_Pin LED_VERTE_Pin SHUTDOWN_ENCODERS_Pin
-                           SHUTDOWN_5V_Pin SHUTDOWN_Pin */
-  GPIO_InitStruct.Pin = LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin|SHUTDOWN_ENCODERS_Pin
-                          |SHUTDOWN_5V_Pin|SHUTDOWN_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+	/*Configure GPIO pin Output Level */
+	HAL_GPIO_WritePin(SHUTDOWN_GPIO_Port, SHUTDOWN_Pin, GPIO_PIN_SET);
 
-  /*Configure GPIO pins : BUTTON_SENSE_Pin USB_SENSE_Pin */
-  GPIO_InitStruct.Pin = BUTTON_SENSE_Pin|USB_SENSE_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+	/*Configure GPIO pins : LED_ROUGE_Pin LED_ORANGE_Pin LED_VERTE_Pin */
+	GPIO_InitStruct.Pin = LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin;
+	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
-  /*Configure GPIO pins : CHARGER_ST2_Pin CHARGER_ST1_Pin */
-  GPIO_InitStruct.Pin = CHARGER_ST2_Pin|CHARGER_ST1_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+	/*Configure GPIO pins : SHUTDOWN_ENCODERS_Pin SHUTDOWN_5V_Pin SHUTDOWN_Pin */
+	GPIO_InitStruct.Pin = SHUTDOWN_ENCODERS_Pin|SHUTDOWN_5V_Pin|SHUTDOWN_Pin;
+	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
-  /* EXTI interrupt init*/
-  HAL_NVIC_SetPriority(EXTI2_3_IRQn, 0, 0);
-  HAL_NVIC_EnableIRQ(EXTI2_3_IRQn);
+	/*Configure GPIO pins : BUTTON_SENSE_Pin USB_SENSE_Pin */
+	GPIO_InitStruct.Pin = BUTTON_SENSE_Pin|USB_SENSE_Pin;
+	GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+	/*Configure GPIO pins : CHARGER_ST2_Pin CHARGER_ST1_Pin */
+	GPIO_InitStruct.Pin = CHARGER_ST2_Pin|CHARGER_ST1_Pin;
+	GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+	/* EXTI interrupt init*/
+	HAL_NVIC_SetPriority(EXTI2_3_IRQn, 3, 0);
+	HAL_NVIC_EnableIRQ(EXTI2_3_IRQn);
 }
 
 /* USER CODE BEGIN 4 */
+TickType_t msToTicks(TickType_t ms) {
+	TickType_t tmp = ms;
 
+	if (ms<(1000/configTICK_RATE_HZ))
+		tmp = 1;
+	else {
+		tmp = ms/(1000/configTICK_RATE_HZ);
+
+		if (ms % (1000/configTICK_RATE_HZ)) // if the delay is not true multiple of tick rate, increase by one (delay longer)
+			tmp ++;
+	}
+	return tmp;
+}
 /* USER CODE END 4 */
 
 /* USER CODE BEGIN Header_StartDefaultTask */
 /**
-  * @brief  Function implementing the defaultTask thread.
-  * @param  argument: Not used
-  * @retval None
-  */
+ * @brief  Function implementing the defaultTask thread.
+ * @param  argument: Not used
+ * @retval None
+ */
 /* USER CODE END Header_StartDefaultTask */
 void StartDefaultTask(void *argument)
 {
-  /* USER CODE BEGIN 5 */
-  /* Infinite loop */
-  for(;;)
-  {
-    osDelay(1);
-  }
-  /* USER CODE END 5 */
+	/* USER CODE BEGIN 5 */
+	LEDS_State state = leds_off;
+
+	/* Infinite loop */
+	for(;;)
+	{
+		state++;
+		MESSAGE_SendMailbox(LEDS_Mailbox, MSG_ID_LED_ETAT, SEQUENCEUR_Mailbox, (void*)&state);
+
+		if (state>leds_erreur)
+			state = leds_off;
+
+		vTaskDelay(pdMS_TO_TICKS(5000));
+	}
+	/* USER CODE END 5 */
 }
 
 /**
-  * @brief  This function is executed in case of error occurrence.
-  * @retval None
-  */
+ * @brief  This function is executed in case of error occurrence.
+ * @retval None
+ */
 void Error_Handler(void)
 {
-  /* USER CODE BEGIN Error_Handler_Debug */
-  /* User can add his own implementation to report the HAL error return state */
-  __disable_irq();
-  while (1)
-  {
-  }
-  /* USER CODE END Error_Handler_Debug */
+	/* USER CODE BEGIN Error_Handler_Debug */
+	/* User can add his own implementation to report the HAL error return state */
+	__disable_irq();
+	while (1)
+	{
+	}
+	/* USER CODE END Error_Handler_Debug */
 }
 
 #ifdef  USE_FULL_ASSERT
 /**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
+ * @brief  Reports the name of the source file and the source line number
+ *         where the assert_param error has occurred.
+ * @param  file: pointer to the source file name
+ * @param  line: assert_param error line source number
+ * @retval None
+ */
 void assert_failed(uint8_t *file, uint32_t line)
 {
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
+	/* USER CODE BEGIN 6 */
+	/* User can add his own implementation to report the file name and line number,
      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
+	/* USER CODE END 6 */
 }
 #endif /* USE_FULL_ASSERT */
 
diff --git a/software/dumber3/Core/Src/messages.c b/software/dumber3/Core/Src/messages.c
new file mode 100644
index 0000000..8c2df94
--- /dev/null
+++ b/software/dumber3/Core/Src/messages.c
@@ -0,0 +1,64 @@
+/*
+ * messages.c
+ *
+ *  Created on: 14 sept. 2022
+ *      Author: dimercur
+ */
+
+#include "messages.h"
+#include "stdlib.h"
+
+#define QUEUE_SIZE 5
+
+QueueHandle_t LEDS_Mailbox;
+QueueHandle_t MOTEURS_Mailbox;
+QueueHandle_t SEQUENCEUR_Mailbox;
+QueueHandle_t BATTERIE_Mailbox;
+QueueHandle_t XBEE_Mailbox;
+
+void  MESSAGE_Init(void) {
+	LEDS_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+	MOTEURS_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+	SEQUENCEUR_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+	BATTERIE_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+	XBEE_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+}
+
+MESSAGE_Typedef MESSAGE_ReadMailbox(QueueHandle_t mbx) {
+	MESSAGE_Typedef msg= {0};
+	char msg_received =0;
+
+	while (!msg_received) {
+		if (xQueueReceive(mbx, &msg, portMAX_DELAY)) { // un message à été reçu
+			msg_received=1;
+
+			return msg;
+		}
+	}
+
+	return msg;
+}
+
+MESSAGE_Typedef MESSAGE_ReadMailboxNoDelay(QueueHandle_t mbx) {
+	MESSAGE_Typedef msg= {0};
+
+	if (!xQueueReceive(mbx, &msg, 0))  // Pas de message dans la mailbox
+		msg.id=MSG_ID_NO_MESSAGE;
+
+	return msg;
+}
+
+void MESSAGE_SendMailbox(QueueHandle_t mbx_dest, uint16_t id, QueueHandle_t mbx_sender, void *data){
+	MESSAGE_Typedef msg;
+
+	msg.id=id;
+	msg.sender = &mbx_sender;
+	msg.data=data;
+
+	if (!xQueueSend(mbx_dest, &msg, 0)) { // envoi sans attendre
+		//printf("Failed to send data, Queue full.\r\n");
+	}
+}
+
+
+
diff --git a/software/dumber3/Core/Src/moteurs.c b/software/dumber3/Core/Src/moteurs.c
new file mode 100644
index 0000000..00be383
--- /dev/null
+++ b/software/dumber3/Core/Src/moteurs.c
@@ -0,0 +1,215 @@
+/*
+ * moteurs.c
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+#include "main.h"
+
+extern LPTIM_HandleTypeDef hlptim1;
+
+extern TIM_HandleTypeDef htim2;
+extern TIM_HandleTypeDef htim21;
+
+int16_t MOTEUR_CmdMoteurG;
+int16_t MOTEUR_CmdMoteurD;
+int16_t MOTEUR_ConsigneMoteurG;
+int16_t MOTEUR_ConsigneMoteurD;
+
+int16_t MOTEUR_NBImpulsionsG;
+int16_t MOTEUR_NBImpulsionsD;
+
+uint16_t MOTEUR_DerniereValEncodeursG;
+uint16_t MOTEUR_DerniereValEncodeursD;
+
+#define MOTEUR_GAUCHE	0
+#define MOTEUR_DROIT	1
+
+#define MOTEUR_Kp 		15
+#define MOTEUR_DELAY	3
+
+/*
+ * Global informations
+ * Main clock: 6 Mhz
+ * Tim2 PWM range: 0 - 255 (freq: 23437,5 Mhz)
+ * TIM21: encodeur gauche (0 - 65535)
+ * LPTIM: encodeur droit (0 - 65535)
+ */
+
+/**
+ *
+ */
+void MOTEURS_DesactiveAlim(void) {
+	HAL_GPIO_WritePin(GPIOB, SHUTDOWN_ENCODERS_Pin, GPIO_PIN_SET);
+	HAL_GPIO_WritePin(GPIOB, SHUTDOWN_5V_Pin, GPIO_PIN_RESET);
+}
+
+/**
+ *
+ */
+void MOTEURS_ActiveAlim(void) {
+	HAL_GPIO_WritePin(GPIOB, SHUTDOWN_ENCODERS_Pin, GPIO_PIN_RESET);
+	HAL_GPIO_WritePin(GPIOB, SHUTDOWN_5V_Pin, GPIO_PIN_SET);
+}
+
+/**
+ *
+ */
+GPIO_PinState MOTEURS_EtatAlim(void) {
+	return HAL_GPIO_ReadPin(GPIOB, SHUTDOWN_5V_Pin);
+}
+
+int16_t MOTEUR_LireEncodeursGauche(void) {
+	uint16_t loc_val= htim21.Instance->CNT;
+	uint16_t overflow = htim21.Instance->SR;
+	int16_t val_end;
+
+	htim21.Instance->SR = htim21.Instance->SR & ~(TIM_SR_UIF);
+
+	if (overflow & TIM_SR_UIF) {
+		val_end = 0xFFFF-loc_val + MOTEUR_DerniereValEncodeursG;
+	} else {
+		val_end = MOTEUR_DerniereValEncodeursG-loc_val;
+	}
+
+	MOTEUR_DerniereValEncodeursG = loc_val;
+	return val_end;
+}
+
+int16_t MOTEUR_LireEncodeursDroit(void) {
+	uint16_t loc_val= hlptim1.Instance->CNT;
+	uint32_t status = hlptim1.Instance->ISR;
+	int16_t val_end;
+
+	hlptim1.Instance->ICR=0xFF; // refait descendre les flags ISR
+
+	if (status & LPTIM_ISR_ARRM) {
+		val_end = 0xFFFF-loc_val + MOTEUR_DerniereValEncodeursD;
+	} else {
+		val_end = MOTEUR_DerniereValEncodeursD-loc_val;
+	}
+
+	val_end= -val_end;
+
+	MOTEUR_DerniereValEncodeursD = loc_val;
+	return val_end;
+}
+
+/**
+ *
+ */
+void MOTEURS_Init(void) {
+	/* Desactive les alimentations des moteurs */
+	MOTEURS_DesactiveAlim();
+
+	/* Lance les timers (timers PWM + timers encodeurs) et regle tout à zero*/
+	hlptim1.Instance->CR = LPTIM_CR_ENABLE;
+	hlptim1.Instance->CR =  LPTIM_CR_ENABLE | LPTIM_CR_CNTSTRT;
+	hlptim1.Instance->ARR = 65535;
+	hlptim1.Instance->CFGR = LPTIM_CFGR_ENC;
+
+	hlptim1.Instance->CNT = 0;
+
+	htim21.Instance->ARR = 65535;
+	htim21.Instance->CR1 = htim21.Instance->CR1 | TIM_CR1_CEN| TIM_CR1_URS;
+	htim21.Instance->CNT = 0;
+
+	htim2.Instance->ARR = 255;
+	htim2.Instance->CNT = 0;
+	htim2.Instance->CCR1 = 0;
+	htim2.Instance->CCR2 = 0;
+	htim2.Instance->CCR3 = 0;
+	htim2.Instance->CCR4 = 0;
+	htim2.Instance->CR1 = htim2.Instance->CR1 | TIM_CR1_CEN;
+	htim2.Instance->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E;
+
+	MOTEUR_CmdMoteurG =0;
+	MOTEUR_CmdMoteurD =0;
+	MOTEUR_ConsigneMoteurG =0;
+	MOTEUR_ConsigneMoteurD =0;
+}
+
+/**
+ * @brief Active les encodeurs et le regulateur des moteur si necessaire et
+ *        regle la commande du moteur (entre -255 et +255)
+ */
+void MOTEURS_Set(uint8_t mot, int16_t val) {
+	uint8_t loc_val;
+
+	if (val>=0) {
+		if (val>255) loc_val = 255;
+		else  loc_val =(uint8_t)val;
+	} else {
+		if (val < -255) loc_val = 255;
+		else loc_val =(uint8_t)(-val);
+	}
+
+	if (MOTEURS_EtatAlim()==GPIO_PIN_RESET)
+		MOTEURS_ActiveAlim();
+
+	if (mot == MOTEUR_DROIT) {
+		if (val >=0) {
+			htim2.Instance->CCR1 = (uint16_t)loc_val;
+			htim2.Instance->CCR2 = 0;
+		} else {
+			htim2.Instance->CCR2 = (uint16_t)loc_val;
+			htim2.Instance->CCR1 = 0;
+		}
+	} else {
+		if (val >=0) {
+			htim2.Instance->CCR4 = (uint16_t)loc_val;
+			htim2.Instance->CCR3 = 0;
+		} else {
+			htim2.Instance->CCR3 = (uint16_t)loc_val;
+			htim2.Instance->CCR4 = 0;
+		}
+	}
+}
+
+void MOTEURS_Test (void) {
+	int16_t deltaG, deltaD =0;
+
+	MOTEUR_LireEncodeursGauche();
+	MOTEUR_LireEncodeursDroit();
+
+	while (1) {
+		HAL_Delay(MOTEUR_DELAY);
+
+		MOTEUR_NBImpulsionsG = MOTEUR_LireEncodeursGauche();
+		MOTEUR_NBImpulsionsD = MOTEUR_LireEncodeursDroit();
+
+		deltaG = MOTEUR_ConsigneMoteurG - MOTEUR_NBImpulsionsG;
+		deltaD = MOTEUR_ConsigneMoteurD - MOTEUR_NBImpulsionsD;
+
+		if (((MOTEUR_ConsigneMoteurD ==0) && (MOTEUR_ConsigneMoteurG ==0)) &&
+				((deltaD==0) && (deltaG==0))) MOTEURS_DesactiveAlim();
+		else MOTEURS_ActiveAlim();
+
+		if (deltaG !=0) {
+			MOTEUR_CmdMoteurG = MOTEUR_CmdMoteurG + MOTEUR_Kp*deltaG;
+			if (MOTEUR_ConsigneMoteurG>=0) {
+				if (MOTEUR_CmdMoteurG>255) MOTEUR_CmdMoteurG=255;
+				if (MOTEUR_CmdMoteurG<0) MOTEUR_CmdMoteurG=0;
+			} else {
+				if (MOTEUR_CmdMoteurG>0) MOTEUR_CmdMoteurG=0;
+				if (MOTEUR_CmdMoteurG<-255) MOTEUR_CmdMoteurG=-255;
+			}
+
+			MOTEURS_Set(MOTEUR_GAUCHE, MOTEUR_CmdMoteurG);
+		}
+
+		if (deltaD !=0) {
+			MOTEUR_CmdMoteurD = MOTEUR_CmdMoteurD + MOTEUR_Kp*deltaD;
+			if (MOTEUR_ConsigneMoteurD>=0) {
+				if (MOTEUR_CmdMoteurD>255) MOTEUR_CmdMoteurD=255;
+				if (MOTEUR_CmdMoteurD<0) MOTEUR_CmdMoteurD=0;
+			} else {
+				if (MOTEUR_CmdMoteurD>0) MOTEUR_CmdMoteurD=0;
+				if (MOTEUR_CmdMoteurD<-255) MOTEUR_CmdMoteurD=-255;
+			}
+
+			MOTEURS_Set(MOTEUR_DROIT, MOTEUR_CmdMoteurD);
+		}
+	}
+}
diff --git a/software/dumber3/Core/Src/sequenceur.c b/software/dumber3/Core/Src/sequenceur.c
new file mode 100644
index 0000000..18902e4
--- /dev/null
+++ b/software/dumber3/Core/Src/sequenceur.c
@@ -0,0 +1,8 @@
+/*
+ * statemachine.c
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+
diff --git a/software/dumber3/Core/Src/xbee.c b/software/dumber3/Core/Src/xbee.c
new file mode 100644
index 0000000..3ac50a4
--- /dev/null
+++ b/software/dumber3/Core/Src/xbee.c
@@ -0,0 +1,8 @@
+/*
+ * xbee.c
+ *
+ *  Created on: Sep 12, 2022
+ *      Author: dimercur
+ */
+
+
diff --git a/software/dumber3/Debug/Core/Src/batterie.su b/software/dumber3/Debug/Core/Src/batterie.su
new file mode 100644
index 0000000..e69de29
diff --git a/software/dumber3/Debug/Core/Src/freertos.su b/software/dumber3/Debug/Core/Src/freertos.su
new file mode 100644
index 0000000..b383c15
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/freertos.su
@@ -0,0 +1,2 @@
+freertos.c:57:13:PreSleepProcessing	16	static
+freertos.c:62:13:PostSleepProcessing	16	static
diff --git a/software/dumber3/Debug/Core/Src/leds.su b/software/dumber3/Debug/Core/Src/leds.su
new file mode 100644
index 0000000..4e62631
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/leds.su
@@ -0,0 +1,3 @@
+leds.c:30:6:LEDS_Init	24	static
+leds.c:51:6:LEDS_RegleAnimation	16	static
+leds.c:55:6:LEDS_AnimationThread	40	static
diff --git a/software/dumber3/Debug/Core/Src/main.su b/software/dumber3/Debug/Core/Src/main.su
new file mode 100644
index 0000000..e294325
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/main.su
@@ -0,0 +1,12 @@
+main.c:97:5:main	8	static
+main.c:188:6:SystemClock_Config	112	static
+main.c:239:13:MX_ADC_Init	16	static
+main.c:293:13:MX_LPTIM1_Init	8	static
+main.c:327:13:MX_LPUART1_UART_Init	8	static
+main.c:361:13:MX_TIM2_Init	48	static
+main.c:432:13:MX_TIM21_Init	64	static
+main.c:479:13:MX_DMA_Init	16	static
+main.c:497:13:MX_GPIO_Init	48	static
+main.c:545:12:msToTicks	24	static
+main.c:567:6:StartDefaultTask	32	static
+main.c:590:6:Error_Handler	8	static,ignoring_inline_asm
diff --git a/software/dumber3/Debug/Core/Src/messages.su b/software/dumber3/Debug/Core/Src/messages.su
new file mode 100644
index 0000000..0ee776e
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/messages.su
@@ -0,0 +1,4 @@
+messages.c:19:7:MESSAGE_Init	8	static
+messages.c:27:17:MESSAGE_ReadMailbox	40	static
+messages.c:42:17:MESSAGE_ReadMailboxNoDelay	40	static
+messages.c:51:6:MESSAGE_SendMailbox	40	static
diff --git a/software/dumber3/Debug/Core/Src/moteurs.su b/software/dumber3/Debug/Core/Src/moteurs.su
new file mode 100644
index 0000000..f0b7147
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/moteurs.su
@@ -0,0 +1,8 @@
+moteurs.c:43:6:MOTEURS_DesactiveAlim	8	static
+moteurs.c:51:6:MOTEURS_ActiveAlim	8	static
+moteurs.c:59:15:MOTEURS_EtatAlim	8	static
+moteurs.c:63:9:MOTEUR_LireEncodeursGauche	16	static
+moteurs.c:80:9:MOTEUR_LireEncodeursDroit	16	static
+moteurs.c:102:6:MOTEURS_Init	8	static
+moteurs.c:137:6:MOTEURS_Set	24	static
+moteurs.c:170:6:MOTEURS_Test	16	static
diff --git a/software/dumber3/Debug/Core/Src/sequenceur.su b/software/dumber3/Debug/Core/Src/sequenceur.su
new file mode 100644
index 0000000..e69de29
diff --git a/software/dumber3/Debug/Core/Src/statemachine.su b/software/dumber3/Debug/Core/Src/statemachine.su
new file mode 100644
index 0000000..e69de29
diff --git a/software/dumber3/Debug/Core/Src/stm32l0xx_hal_msp.su b/software/dumber3/Debug/Core/Src/stm32l0xx_hal_msp.su
new file mode 100644
index 0000000..a0d2174
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/stm32l0xx_hal_msp.su
@@ -0,0 +1,12 @@
+stm32l0xx_hal_msp.c:69:6:HAL_MspInit	8	static
+stm32l0xx_hal_msp.c:93:6:HAL_ADC_MspInit	48	static
+stm32l0xx_hal_msp.c:129:6:HAL_ADC_MspDeInit	16	static
+stm32l0xx_hal_msp.c:159:6:HAL_LPTIM_MspInit	56	static
+stm32l0xx_hal_msp.c:203:6:HAL_LPTIM_MspDeInit	16	static
+stm32l0xx_hal_msp.c:234:6:HAL_UART_MspInit	48	static
+stm32l0xx_hal_msp.c:308:6:HAL_UART_MspDeInit	16	static
+stm32l0xx_hal_msp.c:343:6:HAL_TIM_Base_MspInit	16	static
+stm32l0xx_hal_msp.c:365:6:HAL_TIM_Encoder_MspInit	48	static
+stm32l0xx_hal_msp.c:395:6:HAL_TIM_MspPostInit	56	static
+stm32l0xx_hal_msp.c:445:6:HAL_TIM_Base_MspDeInit	16	static
+stm32l0xx_hal_msp.c:467:6:HAL_TIM_Encoder_MspDeInit	16	static
diff --git a/software/dumber3/Debug/Core/Src/stm32l0xx_it.su b/software/dumber3/Debug/Core/Src/stm32l0xx_it.su
new file mode 100644
index 0000000..764b6f0
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/stm32l0xx_it.su
@@ -0,0 +1,7 @@
+stm32l0xx_it.c:75:6:NMI_Handler	8	static
+stm32l0xx_it.c:90:6:HardFault_Handler	8	static
+stm32l0xx_it.c:105:6:SysTick_Handler	8	static
+stm32l0xx_it.c:134:6:EXTI2_3_IRQHandler	8	static
+stm32l0xx_it.c:148:6:DMA1_Channel2_3_IRQHandler	8	static
+stm32l0xx_it.c:163:6:ADC1_IRQHandler	8	static
+stm32l0xx_it.c:177:6:LPUART1_IRQHandler	8	static
diff --git a/software/dumber3/Debug/Core/Src/subdir.mk b/software/dumber3/Debug/Core/Src/subdir.mk
new file mode 100644
index 0000000..09c74b8
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/subdir.mk
@@ -0,0 +1,56 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Core/Src/batterie.c \
+../Core/Src/freertos.c \
+../Core/Src/leds.c \
+../Core/Src/main.c \
+../Core/Src/messages.c \
+../Core/Src/moteurs.c \
+../Core/Src/sequenceur.c \
+../Core/Src/stm32l0xx_hal_msp.c \
+../Core/Src/stm32l0xx_it.c \
+../Core/Src/syscalls.c \
+../Core/Src/sysmem.c \
+../Core/Src/system_stm32l0xx.c \
+../Core/Src/xbee.c 
+
+OBJS += \
+./Core/Src/batterie.o \
+./Core/Src/freertos.o \
+./Core/Src/leds.o \
+./Core/Src/main.o \
+./Core/Src/messages.o \
+./Core/Src/moteurs.o \
+./Core/Src/sequenceur.o \
+./Core/Src/stm32l0xx_hal_msp.o \
+./Core/Src/stm32l0xx_it.o \
+./Core/Src/syscalls.o \
+./Core/Src/sysmem.o \
+./Core/Src/system_stm32l0xx.o \
+./Core/Src/xbee.o 
+
+C_DEPS += \
+./Core/Src/batterie.d \
+./Core/Src/freertos.d \
+./Core/Src/leds.d \
+./Core/Src/main.d \
+./Core/Src/messages.d \
+./Core/Src/moteurs.d \
+./Core/Src/sequenceur.d \
+./Core/Src/stm32l0xx_hal_msp.d \
+./Core/Src/stm32l0xx_it.d \
+./Core/Src/syscalls.d \
+./Core/Src/sysmem.d \
+./Core/Src/system_stm32l0xx.d \
+./Core/Src/xbee.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Src/%.o: ../Core/Src/%.c Core/Src/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/software/dumber3/Debug/Core/Src/syscalls.su b/software/dumber3/Debug/Core/Src/syscalls.su
new file mode 100644
index 0000000..2661431
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/syscalls.su
@@ -0,0 +1,18 @@
+syscalls.c:45:6:initialise_monitor_handles	8	static
+syscalls.c:49:5:_getpid	8	static
+syscalls.c:54:5:_kill	16	static
+syscalls.c:60:6:_exit	16	static
+syscalls.c:66:27:_read	32	static
+syscalls.c:78:27:_write	32	static
+syscalls.c:89:5:_close	16	static
+syscalls.c:95:5:_fstat	16	static
+syscalls.c:101:5:_isatty	16	static
+syscalls.c:106:5:_lseek	24	static
+syscalls.c:111:5:_open	20	static
+syscalls.c:117:5:_wait	16	static
+syscalls.c:123:5:_unlink	16	static
+syscalls.c:129:5:_times	16	static
+syscalls.c:134:5:_stat	16	static
+syscalls.c:140:5:_link	16	static
+syscalls.c:146:5:_fork	8	static
+syscalls.c:152:5:_execve	24	static
diff --git a/software/dumber3/Debug/Core/Src/sysmem.su b/software/dumber3/Debug/Core/Src/sysmem.su
new file mode 100644
index 0000000..4474c68
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/sysmem.su
@@ -0,0 +1 @@
+sysmem.c:54:7:_sbrk	32	static
diff --git a/software/dumber3/Debug/Core/Src/system_stm32l0xx.su b/software/dumber3/Debug/Core/Src/system_stm32l0xx.su
new file mode 100644
index 0000000..abf8ac4
--- /dev/null
+++ b/software/dumber3/Debug/Core/Src/system_stm32l0xx.su
@@ -0,0 +1,2 @@
+system_stm32l0xx.c:154:6:SystemInit	8	static
+system_stm32l0xx.c:200:6:SystemCoreClockUpdate	32	static
diff --git a/software/dumber3/Debug/Core/Src/xbee.su b/software/dumber3/Debug/Core/Src/xbee.su
new file mode 100644
index 0000000..e69de29
diff --git a/software/dumber3/Debug/Core/Startup/subdir.mk b/software/dumber3/Debug/Core/Startup/subdir.mk
new file mode 100644
index 0000000..8294105
--- /dev/null
+++ b/software/dumber3/Debug/Core/Startup/subdir.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+S_SRCS += \
+../Core/Startup/startup_stm32l010c6tx.s 
+
+OBJS += \
+./Core/Startup/startup_stm32l010c6tx.o 
+
+S_DEPS += \
+./Core/Startup/startup_stm32l010c6tx.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
+	arm-none-eabi-gcc -mcpu=cortex-m0plus -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<"
+
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su
new file mode 100644
index 0000000..585fd26
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su
@@ -0,0 +1,31 @@
+stm32l0xx_hal.c:140:19:HAL_Init	16	static
+stm32l0xx_hal.c:178:19:HAL_DeInit	8	static
+stm32l0xx_hal.c:204:13:HAL_MspInit	8	static
+stm32l0xx_hal.c:215:13:HAL_MspDeInit	8	static
+stm32l0xx_hal.c:238:26:HAL_InitTick	24	static
+stm32l0xx_hal.c:294:13:HAL_IncTick	8	static
+stm32l0xx_hal.c:305:17:HAL_GetTick	8	static
+stm32l0xx_hal.c:314:10:HAL_GetTickPrio	8	static
+stm32l0xx_hal.c:323:19:HAL_SetTickFreq	40	static
+stm32l0xx_hal.c:355:21:HAL_GetTickFreq	8	static
+stm32l0xx_hal.c:371:13:HAL_Delay	24	static
+stm32l0xx_hal.c:397:13:HAL_SuspendTick	8	static
+stm32l0xx_hal.c:413:13:HAL_ResumeTick	8	static
+stm32l0xx_hal.c:423:10:HAL_GetHalVersion	8	static
+stm32l0xx_hal.c:432:10:HAL_GetREVID	8	static
+stm32l0xx_hal.c:441:10:HAL_GetDEVID	8	static
+stm32l0xx_hal.c:450:10:HAL_GetUIDw0	8	static
+stm32l0xx_hal.c:459:10:HAL_GetUIDw1	8	static
+stm32l0xx_hal.c:468:10:HAL_GetUIDw2	8	static
+stm32l0xx_hal.c:497:6:HAL_DBGMCU_EnableDBGSleepMode	8	static
+stm32l0xx_hal.c:506:6:HAL_DBGMCU_DisableDBGSleepMode	8	static
+stm32l0xx_hal.c:515:6:HAL_DBGMCU_EnableDBGStopMode	8	static
+stm32l0xx_hal.c:524:6:HAL_DBGMCU_DisableDBGStopMode	8	static
+stm32l0xx_hal.c:533:6:HAL_DBGMCU_EnableDBGStandbyMode	8	static
+stm32l0xx_hal.c:542:6:HAL_DBGMCU_DisableDBGStandbyMode	8	static
+stm32l0xx_hal.c:556:6:HAL_DBGMCU_DBG_EnableLowPowerConfig	16	static
+stm32l0xx_hal.c:573:6:HAL_DBGMCU_DBG_DisableLowPowerConfig	16	static
+stm32l0xx_hal.c:610:11:HAL_SYSCFG_GetBootMode	8	static
+stm32l0xx_hal.c:627:6:HAL_SYSCFG_VREFINT_OutputSelect	16	static
+stm32l0xx_hal.c:641:6:HAL_SYSCFG_Enable_Lock_VREFINT	8	static
+stm32l0xx_hal.c:651:6:HAL_SYSCFG_Disable_Lock_VREFINT	8	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.su
new file mode 100644
index 0000000..87b0f03
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.su
@@ -0,0 +1,29 @@
+stm32l0xx_hal_adc.c:402:19:HAL_ADC_Init	16	static
+stm32l0xx_hal_adc.c:648:19:HAL_ADC_DeInit	32	static
+stm32l0xx_hal_adc.c:779:13:HAL_ADC_MspInit	16	static
+stm32l0xx_hal_adc.c:794:13:HAL_ADC_MspDeInit	16	static
+stm32l0xx_hal_adc.c:1032:19:HAL_ADC_Start	32	static
+stm32l0xx_hal_adc.c:1098:19:HAL_ADC_Stop	32	static
+stm32l0xx_hal_adc.c:1152:19:HAL_ADC_PollForConversion	24	static
+stm32l0xx_hal_adc.c:1282:19:HAL_ADC_PollForEvent	32	static
+stm32l0xx_hal_adc.c:1369:19:HAL_ADC_Start_IT	32	static
+stm32l0xx_hal_adc.c:1450:19:HAL_ADC_Stop_IT	32	static
+stm32l0xx_hal_adc.c:1500:19:HAL_ADC_Start_DMA	40	static
+stm32l0xx_hal_adc.c:1590:19:HAL_ADC_Stop_DMA	32	static
+stm32l0xx_hal_adc.c:1675:10:HAL_ADC_GetValue	16	static
+stm32l0xx_hal_adc.c:1692:6:HAL_ADC_IRQHandler	16	static
+stm32l0xx_hal_adc.c:1823:13:HAL_ADC_ConvCpltCallback	16	static
+stm32l0xx_hal_adc.c:1838:13:HAL_ADC_ConvHalfCpltCallback	16	static
+stm32l0xx_hal_adc.c:1853:13:HAL_ADC_LevelOutOfWindowCallback	16	static
+stm32l0xx_hal_adc.c:1875:13:HAL_ADC_ErrorCallback	16	static
+stm32l0xx_hal_adc.c:1926:19:HAL_ADC_ConfigChannel	16	static
+stm32l0xx_hal_adc.c:2045:19:HAL_ADC_AnalogWDGConfig	32	static
+stm32l0xx_hal_adc.c:2162:10:HAL_ADC_GetState	16	static
+stm32l0xx_hal_adc.c:2176:10:HAL_ADC_GetError	16	static
+stm32l0xx_hal_adc.c:2209:26:ADC_Enable	24	static
+stm32l0xx_hal_adc.c:2271:26:ADC_Disable	24	static
+stm32l0xx_hal_adc.c:2332:26:ADC_ConversionStop	24	static
+stm32l0xx_hal_adc.c:2386:13:ADC_DMAConvCplt	24	static
+stm32l0xx_hal_adc.c:2450:13:ADC_DMAHalfConvCplt	24	static
+stm32l0xx_hal_adc.c:2468:13:ADC_DMAError	24	static
+stm32l0xx_hal_adc.c:2492:13:ADC_DelayMicroSecond	24	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.su
new file mode 100644
index 0000000..54b5cd8
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.su
@@ -0,0 +1,7 @@
+stm32l0xx_hal_adc_ex.c:107:19:HAL_ADCEx_Calibration_Start	32	static
+stm32l0xx_hal_adc_ex.c:192:10:HAL_ADCEx_Calibration_GetValue	16	static
+stm32l0xx_hal_adc_ex.c:211:19:HAL_ADCEx_Calibration_SetValue	32	static
+stm32l0xx_hal_adc_ex.c:259:19:HAL_ADCEx_EnableVREFINT	16	static
+stm32l0xx_hal_adc_ex.c:291:6:HAL_ADCEx_DisableVREFINT	8	static
+stm32l0xx_hal_adc_ex.c:306:19:HAL_ADCEx_EnableVREFINTTempSensor	16	static
+stm32l0xx_hal_adc_ex.c:338:6:HAL_ADCEx_DisableVREFINTTempSensor	8	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su
new file mode 100644
index 0000000..111a14b
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su
@@ -0,0 +1,21 @@
+core_cm0plus.h:741:22:__NVIC_EnableIRQ	16	static
+core_cm0plus.h:777:22:__NVIC_DisableIRQ	16	static,ignoring_inline_asm
+core_cm0plus.h:796:26:__NVIC_GetPendingIRQ	16	static
+core_cm0plus.h:815:22:__NVIC_SetPendingIRQ	16	static
+core_cm0plus.h:830:22:__NVIC_ClearPendingIRQ	16	static
+core_cm0plus.h:848:22:__NVIC_SetPriority	24	static
+core_cm0plus.h:872:26:__NVIC_GetPriority	16	static
+core_cm0plus.h:983:34:__NVIC_SystemReset	8	static,ignoring_inline_asm
+core_cm0plus.h:1054:26:SysTick_Config	16	static
+stm32l0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority	24	static
+stm32l0xx_hal_cortex.c:148:6:HAL_NVIC_EnableIRQ	16	static
+stm32l0xx_hal_cortex.c:164:6:HAL_NVIC_DisableIRQ	16	static
+stm32l0xx_hal_cortex.c:177:6:HAL_NVIC_SystemReset	8	static
+stm32l0xx_hal_cortex.c:190:10:HAL_SYSTICK_Config	16	static
+stm32l0xx_hal_cortex.c:222:10:HAL_NVIC_GetPriority	16	static
+stm32l0xx_hal_cortex.c:235:6:HAL_NVIC_SetPendingIRQ	16	static
+stm32l0xx_hal_cortex.c:250:10:HAL_NVIC_GetPendingIRQ	16	static
+stm32l0xx_hal_cortex.c:263:6:HAL_NVIC_ClearPendingIRQ	16	static
+stm32l0xx_hal_cortex.c:278:6:HAL_SYSTICK_CLKSourceConfig	16	static
+stm32l0xx_hal_cortex.c:296:6:HAL_SYSTICK_IRQHandler	8	static
+stm32l0xx_hal_cortex.c:305:13:HAL_SYSTICK_Callback	8	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su
new file mode 100644
index 0000000..498911c
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su
@@ -0,0 +1,13 @@
+stm32l0xx_hal_dma.c:139:19:HAL_DMA_Init	24	static
+stm32l0xx_hal_dma.c:214:19:HAL_DMA_DeInit	16	static
+stm32l0xx_hal_dma.c:294:19:HAL_DMA_Start	32	static
+stm32l0xx_hal_dma.c:337:19:HAL_DMA_Start_IT	32	static
+stm32l0xx_hal_dma.c:392:19:HAL_DMA_Abort	24	static
+stm32l0xx_hal_dma.c:433:19:HAL_DMA_Abort_IT	24	static
+stm32l0xx_hal_dma.c:478:19:HAL_DMA_PollForTransfer	32	static
+stm32l0xx_hal_dma.c:579:6:HAL_DMA_IRQHandler	24	static
+stm32l0xx_hal_dma.c:673:19:HAL_DMA_RegisterCallback	32	static
+stm32l0xx_hal_dma.c:724:19:HAL_DMA_UnRegisterCallback	24	static
+stm32l0xx_hal_dma.c:802:22:HAL_DMA_GetState	16	static
+stm32l0xx_hal_dma.c:814:10:HAL_DMA_GetError	16	static
+stm32l0xx_hal_dma.c:840:13:DMA_SetConfig	24	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su
new file mode 100644
index 0000000..e2e6501
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su
@@ -0,0 +1,9 @@
+stm32l0xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine	32	static
+stm32l0xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine	32	static
+stm32l0xx_hal_exti.c:317:19:HAL_EXTI_ClearConfigLine	32	static
+stm32l0xx_hal_exti.c:370:19:HAL_EXTI_RegisterCallback	32	static
+stm32l0xx_hal_exti.c:395:19:HAL_EXTI_GetHandle	16	static
+stm32l0xx_hal_exti.c:435:6:HAL_EXTI_IRQHandler	24	static
+stm32l0xx_hal_exti.c:467:10:HAL_EXTI_GetPending	32	static
+stm32l0xx_hal_exti.c:496:6:HAL_EXTI_ClearPending	24	static
+stm32l0xx_hal_exti.c:517:6:HAL_EXTI_GenerateSWI	24	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su
new file mode 100644
index 0000000..a580d01
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su
@@ -0,0 +1,13 @@
+stm32l0xx_hal_flash.c:231:19:HAL_FLASH_Program	40	static
+stm32l0xx_hal_flash.c:273:19:HAL_FLASH_Program_IT	32	static
+stm32l0xx_hal_flash.c:304:6:HAL_FLASH_IRQHandler	16	static
+stm32l0xx_hal_flash.c:428:13:HAL_FLASH_EndOfOperationCallback	16	static
+stm32l0xx_hal_flash.c:445:13:HAL_FLASH_OperationErrorCallback	16	static
+stm32l0xx_hal_flash.c:478:19:HAL_FLASH_Unlock	32	static,ignoring_inline_asm
+stm32l0xx_hal_flash.c:527:19:HAL_FLASH_Lock	8	static
+stm32l0xx_hal_flash.c:542:19:HAL_FLASH_OB_Unlock	24	static,ignoring_inline_asm
+stm32l0xx_hal_flash.c:579:19:HAL_FLASH_OB_Lock	8	static
+stm32l0xx_hal_flash.c:592:19:HAL_FLASH_OB_Launch	8	static
+stm32l0xx_hal_flash.c:624:10:HAL_FLASH_GetError	8	static
+stm32l0xx_hal_flash.c:646:19:FLASH_WaitForLastOperation	24	static
+stm32l0xx_hal_flash.c:703:13:FLASH_SetErrorCode	16	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su
new file mode 100644
index 0000000..8a09913
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su
@@ -0,0 +1,25 @@
+stm32l0xx_hal_flash_ex.c:171:19:HAL_FLASHEx_Erase	32	static
+stm32l0xx_hal_flash_ex.c:235:19:HAL_FLASHEx_Erase_IT	32	static
+stm32l0xx_hal_flash_ex.c:327:19:HAL_FLASHEx_OBProgram	32	static
+stm32l0xx_hal_flash_ex.c:410:6:HAL_FLASHEx_OBGetConfig	16	static
+stm32l0xx_hal_flash_ex.c:443:19:HAL_FLASHEx_AdvOBProgram	32	static
+stm32l0xx_hal_flash_ex.c:486:6:HAL_FLASHEx_AdvOBGetConfig	16	static
+stm32l0xx_hal_flash_ex.c:526:19:HAL_FLASHEx_OB_SelectPCROP	40	static
+stm32l0xx_hal_flash_ex.c:568:19:HAL_FLASHEx_OB_DeSelectPCROP	40	static
+stm32l0xx_hal_flash_ex.c:634:19:HAL_FLASHEx_DATAEEPROM_Unlock	24	static,ignoring_inline_asm
+stm32l0xx_hal_flash_ex.c:664:19:HAL_FLASHEx_DATAEEPROM_Lock	8	static
+stm32l0xx_hal_flash_ex.c:682:19:HAL_FLASHEx_DATAEEPROM_Erase	32	static
+stm32l0xx_hal_flash_ex.c:724:21:HAL_FLASHEx_DATAEEPROM_Program	40	static
+stm32l0xx_hal_flash_ex.c:780:6:HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram	8	static
+stm32l0xx_hal_flash_ex.c:789:6:HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram	8	static
+stm32l0xx_hal_flash_ex.c:825:26:FLASH_OB_RDPConfig	40	static
+stm32l0xx_hal_flash_ex.c:876:26:FLASH_OB_BORConfig	40	static
+stm32l0xx_hal_flash_ex.c:918:27:FLASH_OB_BOOTBit1Config	40	static
+stm32l0xx_hal_flash_ex.c:953:16:FLASH_OB_GetUser	8	static
+stm32l0xx_hal_flash_ex.c:967:16:FLASH_OB_GetRDP	16	static
+stm32l0xx_hal_flash_ex.c:985:16:FLASH_OB_GetBOR	8	static
+stm32l0xx_hal_flash_ex.c:995:16:FLASH_OB_GetBOOTBit1	8	static
+stm32l0xx_hal_flash_ex.c:1006:17:FLASH_OB_GetWRP	8	static
+stm32l0xx_hal_flash_ex.c:1046:26:FLASH_OB_ProtectedSectorsConfig	40	static
+stm32l0xx_hal_flash_ex.c:1140:26:FLASH_OB_UserConfig	40	static
+stm32l0xx_hal_flash_ex.c:1246:6:FLASH_PageErase	16	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su
new file mode 100644
index 0000000..acd0979
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su
@@ -0,0 +1,6 @@
+stm32l0xx_hal_flash_ramfunc.c:115:30:HAL_FLASHEx_EnableRunPowerDown	8	static
+stm32l0xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_DisableRunPowerDown	8	static
+stm32l0xx_hal_flash_ramfunc.c:305:30:HAL_FLASHEx_HalfPageProgram	32	static,ignoring_inline_asm
+stm32l0xx_hal_flash_ramfunc.c:376:30:HAL_FLASHEx_GetError	16	static
+stm32l0xx_hal_flash_ramfunc.c:458:37:FLASHRAM_WaitForLastOperation	16	static
+stm32l0xx_hal_flash_ramfunc.c:398:37:FLASHRAM_SetErrorCode	16	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su
new file mode 100644
index 0000000..14262a9
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su
@@ -0,0 +1,8 @@
+stm32l0xx_hal_gpio.c:156:6:HAL_GPIO_Init	32	static
+stm32l0xx_hal_gpio.c:286:6:HAL_GPIO_DeInit	32	static
+stm32l0xx_hal_gpio.c:367:15:HAL_GPIO_ReadPin	24	static
+stm32l0xx_hal_gpio.c:403:6:HAL_GPIO_WritePin	16	static
+stm32l0xx_hal_gpio.c:427:6:HAL_GPIO_TogglePin	24	static
+stm32l0xx_hal_gpio.c:454:19:HAL_GPIO_LockPin	24	static
+stm32l0xx_hal_gpio.c:487:6:HAL_GPIO_EXTI_IRQHandler	16	static
+stm32l0xx_hal_gpio.c:502:13:HAL_GPIO_EXTI_Callback	16	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su
new file mode 100644
index 0000000..b7d0802
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su
@@ -0,0 +1,79 @@
+stm32l0xx_hal_i2c.c:522:19:HAL_I2C_Init	16	static
+stm32l0xx_hal_i2c.c:632:19:HAL_I2C_DeInit	16	static
+stm32l0xx_hal_i2c.c:678:13:HAL_I2C_MspInit	16	static
+stm32l0xx_hal_i2c.c:694:13:HAL_I2C_MspDeInit	16	static
+stm32l0xx_hal_i2c.c:1115:19:HAL_I2C_Master_Transmit	48	static
+stm32l0xx_hal_i2c.c:1234:19:HAL_I2C_Master_Receive	48	static
+stm32l0xx_hal_i2c.c:1352:19:HAL_I2C_Slave_Transmit	40	static
+stm32l0xx_hal_i2c.c:1490:19:HAL_I2C_Slave_Receive	40	static
+stm32l0xx_hal_i2c.c:1617:19:HAL_I2C_Master_Transmit_IT	48	static
+stm32l0xx_hal_i2c.c:1688:19:HAL_I2C_Master_Receive_IT	48	static
+stm32l0xx_hal_i2c.c:1757:19:HAL_I2C_Slave_Transmit_IT	24	static
+stm32l0xx_hal_i2c.c:1807:19:HAL_I2C_Slave_Receive_IT	24	static
+stm32l0xx_hal_i2c.c:1859:19:HAL_I2C_Master_Transmit_DMA	48	static
+stm32l0xx_hal_i2c.c:2006:19:HAL_I2C_Master_Receive_DMA	48	static
+stm32l0xx_hal_i2c.c:2151:19:HAL_I2C_Slave_Transmit_DMA	40	static
+stm32l0xx_hal_i2c.c:2255:19:HAL_I2C_Slave_Receive_DMA	40	static
+stm32l0xx_hal_i2c.c:2363:19:HAL_I2C_Mem_Write	48	static
+stm32l0xx_hal_i2c.c:2500:19:HAL_I2C_Mem_Read	48	static
+stm32l0xx_hal_i2c.c:2637:19:HAL_I2C_Mem_Write_IT	48	static
+stm32l0xx_hal_i2c.c:2731:19:HAL_I2C_Mem_Read_IT	48	static
+stm32l0xx_hal_i2c.c:2823:19:HAL_I2C_Mem_Write_DMA	56	static
+stm32l0xx_hal_i2c.c:2970:19:HAL_I2C_Mem_Read_DMA	56	static
+stm32l0xx_hal_i2c.c:3113:19:HAL_I2C_IsDeviceReady	48	static
+stm32l0xx_hal_i2c.c:3255:19:HAL_I2C_Master_Seq_Transmit_IT	48	static
+stm32l0xx_hal_i2c.c:3342:19:HAL_I2C_Master_Seq_Transmit_DMA	56	static
+stm32l0xx_hal_i2c.c:3510:19:HAL_I2C_Master_Seq_Receive_IT	48	static
+stm32l0xx_hal_i2c.c:3597:19:HAL_I2C_Master_Seq_Receive_DMA	56	static
+stm32l0xx_hal_i2c.c:3763:19:HAL_I2C_Slave_Seq_Transmit_IT	24	static
+stm32l0xx_hal_i2c.c:3859:19:HAL_I2C_Slave_Seq_Transmit_DMA	40	static
+stm32l0xx_hal_i2c.c:4040:19:HAL_I2C_Slave_Seq_Receive_IT	24	static
+stm32l0xx_hal_i2c.c:4136:19:HAL_I2C_Slave_Seq_Receive_DMA	40	static
+stm32l0xx_hal_i2c.c:4313:19:HAL_I2C_EnableListen_IT	16	static
+stm32l0xx_hal_i2c.c:4337:19:HAL_I2C_DisableListen_IT	24	static
+stm32l0xx_hal_i2c.c:4370:19:HAL_I2C_Master_Abort_IT	24	static
+stm32l0xx_hal_i2c.c:4432:6:HAL_I2C_EV_IRQHandler	24	static
+stm32l0xx_hal_i2c.c:4451:6:HAL_I2C_ER_IRQHandler	32	static
+stm32l0xx_hal_i2c.c:4503:13:HAL_I2C_MasterTxCpltCallback	16	static
+stm32l0xx_hal_i2c.c:4519:13:HAL_I2C_MasterRxCpltCallback	16	static
+stm32l0xx_hal_i2c.c:4534:13:HAL_I2C_SlaveTxCpltCallback	16	static
+stm32l0xx_hal_i2c.c:4550:13:HAL_I2C_SlaveRxCpltCallback	16	static
+stm32l0xx_hal_i2c.c:4568:13:HAL_I2C_AddrCallback	16	static
+stm32l0xx_hal_i2c.c:4586:13:HAL_I2C_ListenCpltCallback	16	static
+stm32l0xx_hal_i2c.c:4602:13:HAL_I2C_MemTxCpltCallback	16	static
+stm32l0xx_hal_i2c.c:4618:13:HAL_I2C_MemRxCpltCallback	16	static
+stm32l0xx_hal_i2c.c:4634:13:HAL_I2C_ErrorCallback	16	static
+stm32l0xx_hal_i2c.c:4650:13:HAL_I2C_AbortCpltCallback	16	static
+stm32l0xx_hal_i2c.c:4685:22:HAL_I2C_GetState	16	static
+stm32l0xx_hal_i2c.c:4697:21:HAL_I2C_GetMode	16	static
+stm32l0xx_hal_i2c.c:4708:10:HAL_I2C_GetError	16	static
+stm32l0xx_hal_i2c.c:4733:26:I2C_Master_ISR_IT	48	static
+stm32l0xx_hal_i2c.c:4879:26:I2C_Slave_ISR_IT	32	static
+stm32l0xx_hal_i2c.c:5020:26:I2C_Master_ISR_DMA	48	static
+stm32l0xx_hal_i2c.c:5160:26:I2C_Slave_ISR_DMA	40	static
+stm32l0xx_hal_i2c.c:5305:26:I2C_RequestMemoryWrite	40	static
+stm32l0xx_hal_i2c.c:5360:26:I2C_RequestMemoryRead	40	static
+stm32l0xx_hal_i2c.c:5409:13:I2C_ITAddrCplt	32	static
+stm32l0xx_hal_i2c.c:5504:13:I2C_ITMasterSeqCplt	16	static
+stm32l0xx_hal_i2c.c:5557:13:I2C_ITSlaveSeqCplt	24	static
+stm32l0xx_hal_i2c.c:5631:13:I2C_ITMasterCplt	32	static
+stm32l0xx_hal_i2c.c:5774:13:I2C_ITSlaveCplt	32	static
+stm32l0xx_hal_i2c.c:5933:13:I2C_ITListenCplt	16	static
+stm32l0xx_hal_i2c.c:5984:13:I2C_ITError	24	static
+stm32l0xx_hal_i2c.c:6096:13:I2C_TreatErrorCallback	16	static
+stm32l0xx_hal_i2c.c:6134:13:I2C_Flush_TXDR	16	static
+stm32l0xx_hal_i2c.c:6155:13:I2C_DMAMasterTransmitCplt	24	static
+stm32l0xx_hal_i2c.c:6205:13:I2C_DMASlaveTransmitCplt	24	static
+stm32l0xx_hal_i2c.c:6233:13:I2C_DMAMasterReceiveCplt	24	static
+stm32l0xx_hal_i2c.c:6283:13:I2C_DMASlaveReceiveCplt	24	static
+stm32l0xx_hal_i2c.c:6311:13:I2C_DMAError	24	static
+stm32l0xx_hal_i2c.c:6329:13:I2C_DMAAbort	24	static
+stm32l0xx_hal_i2c.c:6357:26:I2C_WaitOnFlagUntilTimeout	24	static
+stm32l0xx_hal_i2c.c:6388:26:I2C_WaitOnTXISFlagUntilTimeout	24	static
+stm32l0xx_hal_i2c.c:6426:26:I2C_WaitOnSTOPFlagUntilTimeout	24	static
+stm32l0xx_hal_i2c.c:6461:26:I2C_WaitOnRXNEFlagUntilTimeout	24	static
+stm32l0xx_hal_i2c.c:6525:26:I2C_IsAcknowledgeFailed	24	static
+stm32l0xx_hal_i2c.c:6599:13:I2C_TransferConfig	32	static
+stm32l0xx_hal_i2c.c:6624:13:I2C_Enable_IRQ	24	static
+stm32l0xx_hal_i2c.c:6695:13:I2C_Disable_IRQ	24	static
+stm32l0xx_hal_i2c.c:6758:13:I2C_ConvertOtherXferOptions	16	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su
new file mode 100644
index 0000000..6c35e69
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su
@@ -0,0 +1,4 @@
+stm32l0xx_hal_i2c_ex.c:97:19:HAL_I2CEx_ConfigAnalogFilter	16	static
+stm32l0xx_hal_i2c_ex.c:141:19:HAL_I2CEx_ConfigDigitalFilter	24	static
+stm32l0xx_hal_i2c_ex.c:209:19:HAL_I2CEx_EnableWakeUp	16	static
+stm32l0xx_hal_i2c_ex.c:248:19:HAL_I2CEx_DisableWakeUp	16	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.su
new file mode 100644
index 0000000..9567e89
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.su
@@ -0,0 +1,42 @@
+stm32l0xx_hal_lptim.c:220:19:HAL_LPTIM_Init	24	static
+stm32l0xx_hal_lptim.c:341:19:HAL_LPTIM_DeInit	16	static
+stm32l0xx_hal_lptim.c:388:13:HAL_LPTIM_MspInit	16	static
+stm32l0xx_hal_lptim.c:403:13:HAL_LPTIM_MspDeInit	16	static
+stm32l0xx_hal_lptim.c:452:19:HAL_LPTIM_PWM_Start	24	static
+stm32l0xx_hal_lptim.c:507:19:HAL_LPTIM_PWM_Stop	16	static
+stm32l0xx_hal_lptim.c:539:19:HAL_LPTIM_PWM_Start_IT	24	static
+stm32l0xx_hal_lptim.c:624:19:HAL_LPTIM_PWM_Stop_IT	16	static
+stm32l0xx_hal_lptim.c:675:19:HAL_LPTIM_OnePulse_Start	24	static
+stm32l0xx_hal_lptim.c:730:19:HAL_LPTIM_OnePulse_Stop	16	static
+stm32l0xx_hal_lptim.c:762:19:HAL_LPTIM_OnePulse_Start_IT	24	static
+stm32l0xx_hal_lptim.c:847:19:HAL_LPTIM_OnePulse_Stop_IT	16	static
+stm32l0xx_hal_lptim.c:898:19:HAL_LPTIM_SetOnce_Start	24	static
+stm32l0xx_hal_lptim.c:953:19:HAL_LPTIM_SetOnce_Stop	16	static
+stm32l0xx_hal_lptim.c:985:19:HAL_LPTIM_SetOnce_Start_IT	24	static
+stm32l0xx_hal_lptim.c:1070:19:HAL_LPTIM_SetOnce_Stop_IT	16	static
+stm32l0xx_hal_lptim.c:1119:19:HAL_LPTIM_Encoder_Start	24	static
+stm32l0xx_hal_lptim.c:1178:19:HAL_LPTIM_Encoder_Stop	16	static
+stm32l0xx_hal_lptim.c:1211:19:HAL_LPTIM_Encoder_Start_IT	24	static
+stm32l0xx_hal_lptim.c:1288:19:HAL_LPTIM_Encoder_Stop_IT	16	static
+stm32l0xx_hal_lptim.c:1331:19:HAL_LPTIM_TimeOut_Start	24	static
+stm32l0xx_hal_lptim.c:1386:19:HAL_LPTIM_TimeOut_Stop	16	static
+stm32l0xx_hal_lptim.c:1423:19:HAL_LPTIM_TimeOut_Start_IT	24	static
+stm32l0xx_hal_lptim.c:1495:19:HAL_LPTIM_TimeOut_Stop_IT	16	static
+stm32l0xx_hal_lptim.c:1534:19:HAL_LPTIM_Counter_Start	16	static
+stm32l0xx_hal_lptim.c:1583:19:HAL_LPTIM_Counter_Stop	16	static
+stm32l0xx_hal_lptim.c:1613:19:HAL_LPTIM_Counter_Start_IT	16	static
+stm32l0xx_hal_lptim.c:1682:19:HAL_LPTIM_Counter_Stop_IT	16	static
+stm32l0xx_hal_lptim.c:1737:10:HAL_LPTIM_ReadCounter	16	static
+stm32l0xx_hal_lptim.c:1750:10:HAL_LPTIM_ReadAutoReload	16	static
+stm32l0xx_hal_lptim.c:1763:10:HAL_LPTIM_ReadCompare	16	static
+stm32l0xx_hal_lptim.c:1802:6:HAL_LPTIM_IRQHandler	16	static
+stm32l0xx_hal_lptim.c:1929:13:HAL_LPTIM_CompareMatchCallback	16	static
+stm32l0xx_hal_lptim.c:1944:13:HAL_LPTIM_AutoReloadMatchCallback	16	static
+stm32l0xx_hal_lptim.c:1959:13:HAL_LPTIM_TriggerCallback	16	static
+stm32l0xx_hal_lptim.c:1974:13:HAL_LPTIM_CompareWriteCallback	16	static
+stm32l0xx_hal_lptim.c:1989:13:HAL_LPTIM_AutoReloadWriteCallback	16	static
+stm32l0xx_hal_lptim.c:2004:13:HAL_LPTIM_DirectionUpCallback	16	static
+stm32l0xx_hal_lptim.c:2019:13:HAL_LPTIM_DirectionDownCallback	16	static
+stm32l0xx_hal_lptim.c:2273:24:HAL_LPTIM_GetState	16	static
+stm32l0xx_hal_lptim.c:2320:26:LPTIM_WaitForFlag	24	static
+stm32l0xx_hal_lptim.c:2345:6:LPTIM_Disable	40	static,ignoring_inline_asm
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su
new file mode 100644
index 0000000..d0d236e
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su
@@ -0,0 +1,12 @@
+stm32l0xx_hal_pwr.c:80:6:HAL_PWR_DeInit	8	static
+stm32l0xx_hal_pwr.c:327:6:HAL_PWR_EnableBkUpAccess	8	static
+stm32l0xx_hal_pwr.c:340:6:HAL_PWR_DisableBkUpAccess	8	static
+stm32l0xx_hal_pwr.c:425:6:HAL_PWR_EnableWakeUpPin	16	static
+stm32l0xx_hal_pwr.c:442:6:HAL_PWR_DisableWakeUpPin	16	static
+stm32l0xx_hal_pwr.c:465:6:HAL_PWR_EnterSLEEPMode	32	static,ignoring_inline_asm
+stm32l0xx_hal_pwr.c:546:6:HAL_PWR_EnterSTOPMode	32	static,ignoring_inline_asm
+stm32l0xx_hal_pwr.c:615:6:HAL_PWR_EnterSTANDBYMode	8	static,ignoring_inline_asm
+stm32l0xx_hal_pwr.c:639:6:HAL_PWR_EnableSleepOnExit	8	static
+stm32l0xx_hal_pwr.c:652:6:HAL_PWR_DisableSleepOnExit	8	static
+stm32l0xx_hal_pwr.c:665:6:HAL_PWR_EnableSEVOnPend	8	static
+stm32l0xx_hal_pwr.c:678:6:HAL_PWR_DisableSEVOnPend	8	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su
new file mode 100644
index 0000000..fa2f762
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su
@@ -0,0 +1,7 @@
+stm32l0xx_hal_pwr_ex.c:70:10:HAL_PWREx_GetVoltageRange	8	static
+stm32l0xx_hal_pwr_ex.c:83:6:HAL_PWREx_EnableFastWakeUp	8	static
+stm32l0xx_hal_pwr_ex.c:93:6:HAL_PWREx_DisableFastWakeUp	8	static
+stm32l0xx_hal_pwr_ex.c:103:6:HAL_PWREx_EnableUltraLowPower	8	static
+stm32l0xx_hal_pwr_ex.c:113:6:HAL_PWREx_DisableUltraLowPower	8	static
+stm32l0xx_hal_pwr_ex.c:131:6:HAL_PWREx_EnableLowPowerRunMode	8	static
+stm32l0xx_hal_pwr_ex.c:146:19:HAL_PWREx_DisableLowPowerRunMode	16	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su
new file mode 100644
index 0000000..2c9153c
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su
@@ -0,0 +1,13 @@
+stm32l0xx_hal_rcc.c:223:19:HAL_RCC_DeInit	32	static
+stm32l0xx_hal_rcc.c:338:19:HAL_RCC_OscConfig	56	static
+stm32l0xx_hal_rcc.c:859:19:HAL_RCC_ClockConfig	32	static
+stm32l0xx_hal_rcc.c:1120:6:HAL_RCC_MCOConfig	64	static
+stm32l0xx_hal_rcc.c:1177:6:HAL_RCC_EnableCSS	8	static
+stm32l0xx_hal_rcc.c:1213:10:HAL_RCC_GetSysClockFreq	72	static
+stm32l0xx_hal_rcc.c:1283:10:HAL_RCC_GetHCLKFreq	8	static
+stm32l0xx_hal_rcc.c:1294:10:HAL_RCC_GetPCLK1Freq	8	static
+stm32l0xx_hal_rcc.c:1306:10:HAL_RCC_GetPCLK2Freq	8	static
+stm32l0xx_hal_rcc.c:1319:6:HAL_RCC_GetOscConfig	16	static
+stm32l0xx_hal_rcc.c:1422:6:HAL_RCC_GetClockConfig	16	static
+stm32l0xx_hal_rcc.c:1453:6:HAL_RCC_NMI_IRQHandler	8	static
+stm32l0xx_hal_rcc.c:1470:13:HAL_RCC_CSSCallback	8	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su
new file mode 100644
index 0000000..2dbe186
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su
@@ -0,0 +1,8 @@
+stm32l0xx_hal_rcc_ex.c:97:19:HAL_RCCEx_PeriphCLKConfig	32	static
+stm32l0xx_hal_rcc_ex.c:296:6:HAL_RCCEx_GetPeriphCLKConfig	24	static
+stm32l0xx_hal_rcc_ex.c:374:10:HAL_RCCEx_GetPeriphCLKFreq	32	static
+stm32l0xx_hal_rcc_ex.c:744:6:HAL_RCCEx_EnableLSECSS	8	static
+stm32l0xx_hal_rcc_ex.c:756:6:HAL_RCCEx_DisableLSECSS	8	static
+stm32l0xx_hal_rcc_ex.c:770:6:HAL_RCCEx_EnableLSECSS_IT	8	static
+stm32l0xx_hal_rcc_ex.c:787:6:HAL_RCCEx_LSECSS_IRQHandler	8	static
+stm32l0xx_hal_rcc_ex.c:804:13:HAL_RCCEx_LSECSS_Callback	8	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su
new file mode 100644
index 0000000..786182c
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su
@@ -0,0 +1,119 @@
+stm32l0xx_hal_tim.c:269:19:HAL_TIM_Base_Init	16	static
+stm32l0xx_hal_tim.c:329:19:HAL_TIM_Base_DeInit	16	static
+stm32l0xx_hal_tim.c:371:13:HAL_TIM_Base_MspInit	16	static
+stm32l0xx_hal_tim.c:386:13:HAL_TIM_Base_MspDeInit	16	static
+stm32l0xx_hal_tim.c:402:19:HAL_TIM_Base_Start	24	static
+stm32l0xx_hal_tim.c:441:19:HAL_TIM_Base_Stop	16	static
+stm32l0xx_hal_tim.c:461:19:HAL_TIM_Base_Start_IT	24	static
+stm32l0xx_hal_tim.c:503:19:HAL_TIM_Base_Stop_IT	16	static
+stm32l0xx_hal_tim.c:528:19:HAL_TIM_Base_Start_DMA	32	static
+stm32l0xx_hal_tim.c:597:19:HAL_TIM_Base_Stop_DMA	16	static
+stm32l0xx_hal_tim.c:652:19:HAL_TIM_OC_Init	16	static
+stm32l0xx_hal_tim.c:712:19:HAL_TIM_OC_DeInit	16	static
+stm32l0xx_hal_tim.c:754:13:HAL_TIM_OC_MspInit	16	static
+stm32l0xx_hal_tim.c:769:13:HAL_TIM_OC_MspDeInit	16	static
+stm32l0xx_hal_tim.c:790:19:HAL_TIM_OC_Start	24	static
+stm32l0xx_hal_tim.c:838:19:HAL_TIM_OC_Stop	16	static
+stm32l0xx_hal_tim.c:867:19:HAL_TIM_OC_Start_IT	24	static
+stm32l0xx_hal_tim.c:954:19:HAL_TIM_OC_Stop_IT	24	static
+stm32l0xx_hal_tim.c:1025:19:HAL_TIM_OC_Start_DMA	32	static
+stm32l0xx_hal_tim.c:1182:19:HAL_TIM_OC_Stop_DMA	24	static
+stm32l0xx_hal_tim.c:1279:19:HAL_TIM_PWM_Init	16	static
+stm32l0xx_hal_tim.c:1339:19:HAL_TIM_PWM_DeInit	16	static
+stm32l0xx_hal_tim.c:1381:13:HAL_TIM_PWM_MspInit	16	static
+stm32l0xx_hal_tim.c:1396:13:HAL_TIM_PWM_MspDeInit	16	static
+stm32l0xx_hal_tim.c:1417:19:HAL_TIM_PWM_Start	24	static
+stm32l0xx_hal_tim.c:1465:19:HAL_TIM_PWM_Stop	16	static
+stm32l0xx_hal_tim.c:1494:19:HAL_TIM_PWM_Start_IT	24	static
+stm32l0xx_hal_tim.c:1581:19:HAL_TIM_PWM_Stop_IT	24	static
+stm32l0xx_hal_tim.c:1652:19:HAL_TIM_PWM_Start_DMA	32	static
+stm32l0xx_hal_tim.c:1808:19:HAL_TIM_PWM_Stop_DMA	24	static
+stm32l0xx_hal_tim.c:1905:19:HAL_TIM_IC_Init	16	static
+stm32l0xx_hal_tim.c:1965:19:HAL_TIM_IC_DeInit	16	static
+stm32l0xx_hal_tim.c:2007:13:HAL_TIM_IC_MspInit	16	static
+stm32l0xx_hal_tim.c:2022:13:HAL_TIM_IC_MspDeInit	16	static
+stm32l0xx_hal_tim.c:2043:19:HAL_TIM_IC_Start	24	static
+stm32l0xx_hal_tim.c:2092:19:HAL_TIM_IC_Stop	16	static
+stm32l0xx_hal_tim.c:2121:19:HAL_TIM_IC_Start_IT	24	static
+stm32l0xx_hal_tim.c:2210:19:HAL_TIM_IC_Stop_IT	24	static
+stm32l0xx_hal_tim.c:2281:19:HAL_TIM_IC_Start_DMA	32	static
+stm32l0xx_hal_tim.c:2436:19:HAL_TIM_IC_Stop_DMA	24	static
+stm32l0xx_hal_tim.c:2540:19:HAL_TIM_OnePulse_Init	16	static
+stm32l0xx_hal_tim.c:2608:19:HAL_TIM_OnePulse_DeInit	16	static
+stm32l0xx_hal_tim.c:2651:13:HAL_TIM_OnePulse_MspInit	16	static
+stm32l0xx_hal_tim.c:2666:13:HAL_TIM_OnePulse_MspDeInit	16	static
+stm32l0xx_hal_tim.c:2686:19:HAL_TIM_OnePulse_Start	32	static
+stm32l0xx_hal_tim.c:2731:19:HAL_TIM_OnePulse_Stop	16	static
+stm32l0xx_hal_tim.c:2766:19:HAL_TIM_OnePulse_Start_IT	32	static
+stm32l0xx_hal_tim.c:2817:19:HAL_TIM_OnePulse_Stop_IT	16	static
+stm32l0xx_hal_tim.c:2888:19:HAL_TIM_Encoder_Init	32	static
+stm32l0xx_hal_tim.c:3002:19:HAL_TIM_Encoder_DeInit	16	static
+stm32l0xx_hal_tim.c:3045:13:HAL_TIM_Encoder_MspInit	16	static
+stm32l0xx_hal_tim.c:3060:13:HAL_TIM_Encoder_MspDeInit	16	static
+stm32l0xx_hal_tim.c:3080:19:HAL_TIM_Encoder_Start	24	static
+stm32l0xx_hal_tim.c:3164:19:HAL_TIM_Encoder_Stop	16	static
+stm32l0xx_hal_tim.c:3221:19:HAL_TIM_Encoder_Start_IT	24	static
+stm32l0xx_hal_tim.c:3311:19:HAL_TIM_Encoder_Stop_IT	16	static
+stm32l0xx_hal_tim.c:3373:19:HAL_TIM_Encoder_Start_DMA	32	static
+stm32l0xx_hal_tim.c:3572:19:HAL_TIM_Encoder_Stop_DMA	16	static
+stm32l0xx_hal_tim.c:3646:6:HAL_TIM_IRQHandler	16	static
+stm32l0xx_hal_tim.c:3834:19:HAL_TIM_OC_ConfigChannel	32	static
+stm32l0xx_hal_tim.c:3913:19:HAL_TIM_IC_ConfigChannel	32	static
+stm32l0xx_hal_tim.c:4012:19:HAL_TIM_PWM_ConfigChannel	32	static
+stm32l0xx_hal_tim.c:4126:19:HAL_TIM_OnePulse_ConfigChannel	48	static
+stm32l0xx_hal_tim.c:4269:19:HAL_TIM_DMABurst_WriteStart	48	static
+stm32l0xx_hal_tim.c:4321:19:HAL_TIM_DMABurst_MultiWriteStart	32	static
+stm32l0xx_hal_tim.c:4487:19:HAL_TIM_DMABurst_WriteStop	24	static
+stm32l0xx_hal_tim.c:4581:19:HAL_TIM_DMABurst_ReadStart	48	static
+stm32l0xx_hal_tim.c:4632:19:HAL_TIM_DMABurst_MultiReadStart	32	static
+stm32l0xx_hal_tim.c:4798:19:HAL_TIM_DMABurst_ReadStop	24	static
+stm32l0xx_hal_tim.c:4871:19:HAL_TIM_GenerateEvent	16	static
+stm32l0xx_hal_tim.c:4908:19:HAL_TIM_ConfigOCrefClear	32	static
+stm32l0xx_hal_tim.c:5038:19:HAL_TIM_ConfigClockSource	24	static
+stm32l0xx_hal_tim.c:5192:19:HAL_TIM_ConfigTI1Input	24	static
+stm32l0xx_hal_tim.c:5224:19:HAL_TIM_SlaveConfigSynchro	16	static
+stm32l0xx_hal_tim.c:5264:19:HAL_TIM_SlaveConfigSynchro_IT	16	static
+stm32l0xx_hal_tim.c:5307:10:HAL_TIM_ReadCapturedValue	24	static
+stm32l0xx_hal_tim.c:5391:13:HAL_TIM_PeriodElapsedCallback	16	static
+stm32l0xx_hal_tim.c:5406:13:HAL_TIM_PeriodElapsedHalfCpltCallback	16	static
+stm32l0xx_hal_tim.c:5421:13:HAL_TIM_OC_DelayElapsedCallback	16	static
+stm32l0xx_hal_tim.c:5436:13:HAL_TIM_IC_CaptureCallback	16	static
+stm32l0xx_hal_tim.c:5451:13:HAL_TIM_IC_CaptureHalfCpltCallback	16	static
+stm32l0xx_hal_tim.c:5466:13:HAL_TIM_PWM_PulseFinishedCallback	16	static
+stm32l0xx_hal_tim.c:5481:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	16	static
+stm32l0xx_hal_tim.c:5496:13:HAL_TIM_TriggerCallback	16	static
+stm32l0xx_hal_tim.c:5511:13:HAL_TIM_TriggerHalfCpltCallback	16	static
+stm32l0xx_hal_tim.c:5526:13:HAL_TIM_ErrorCallback	16	static
+stm32l0xx_hal_tim.c:6011:22:HAL_TIM_Base_GetState	16	static
+stm32l0xx_hal_tim.c:6021:22:HAL_TIM_OC_GetState	16	static
+stm32l0xx_hal_tim.c:6031:22:HAL_TIM_PWM_GetState	16	static
+stm32l0xx_hal_tim.c:6041:22:HAL_TIM_IC_GetState	16	static
+stm32l0xx_hal_tim.c:6051:22:HAL_TIM_OnePulse_GetState	16	static
+stm32l0xx_hal_tim.c:6061:22:HAL_TIM_Encoder_GetState	16	static
+stm32l0xx_hal_tim.c:6071:23:HAL_TIM_GetActiveChannel	16	static
+stm32l0xx_hal_tim.c:6089:29:HAL_TIM_GetChannelState	24	static
+stm32l0xx_hal_tim.c:6106:30:HAL_TIM_DMABurstState	16	static
+stm32l0xx_hal_tim.c:6131:6:TIM_DMAError	24	static
+stm32l0xx_hal_tim.c:6174:13:TIM_DMADelayPulseCplt	24	static
+stm32l0xx_hal_tim.c:6233:13:TIM_DMADelayPulseHalfCplt	24	static
+stm32l0xx_hal_tim.c:6272:6:TIM_DMACaptureCplt	24	static
+stm32l0xx_hal_tim.c:6331:6:TIM_DMACaptureHalfCplt	24	static
+stm32l0xx_hal_tim.c:6370:13:TIM_DMAPeriodElapsedCplt	24	static
+stm32l0xx_hal_tim.c:6391:13:TIM_DMAPeriodElapsedHalfCplt	24	static
+stm32l0xx_hal_tim.c:6407:13:TIM_DMATriggerCplt	24	static
+stm32l0xx_hal_tim.c:6428:13:TIM_DMATriggerHalfCplt	24	static
+stm32l0xx_hal_tim.c:6445:13:TIM_Base_SetConfig	24	static
+stm32l0xx_hal_tim.c:6487:13:TIM_OC1_SetConfig	32	static
+stm32l0xx_hal_tim.c:6534:13:TIM_OC2_SetConfig	32	static
+stm32l0xx_hal_tim.c:6582:13:TIM_OC3_SetConfig	32	static
+stm32l0xx_hal_tim.c:6629:13:TIM_OC4_SetConfig	32	static
+stm32l0xx_hal_tim.c:6677:26:TIM_SlaveTimer_SetConfig	32	static
+stm32l0xx_hal_tim.c:6811:13:TIM_TI1_SetConfig	32	static
+stm32l0xx_hal_tim.c:6858:13:TIM_TI1_ConfigInputStage	32	static
+stm32l0xx_hal_tim.c:6901:13:TIM_TI2_SetConfig	32	static
+stm32l0xx_hal_tim.c:6941:13:TIM_TI2_ConfigInputStage	32	static
+stm32l0xx_hal_tim.c:6984:13:TIM_TI3_SetConfig	32	static
+stm32l0xx_hal_tim.c:7032:13:TIM_TI4_SetConfig	32	static
+stm32l0xx_hal_tim.c:7075:13:TIM_ITRx_SetConfig	24	static
+stm32l0xx_hal_tim.c:7105:13:TIM_ETR_SetConfig	32	static
+stm32l0xx_hal_tim.c:7135:13:TIM_CCxChannelCmd	32	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su
new file mode 100644
index 0000000..4a9d059
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su
@@ -0,0 +1,2 @@
+stm32l0xx_hal_tim_ex.c:82:19:HAL_TIMEx_MasterConfigSynchronization	24	static
+stm32l0xx_hal_tim_ex.c:394:19:HAL_TIMEx_RemapConfig	16	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su
new file mode 100644
index 0000000..ca12311
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su
@@ -0,0 +1,66 @@
+stm32l0xx_hal_uart.c:291:19:HAL_UART_Init	16	static
+stm32l0xx_hal_uart.c:364:19:HAL_HalfDuplex_Init	16	static
+stm32l0xx_hal_uart.c:437:19:HAL_LIN_Init	16	static
+stm32l0xx_hal_uart.c:534:19:HAL_MultiProcessor_Init	24	static
+stm32l0xx_hal_uart.c:608:19:HAL_UART_DeInit	16	static
+stm32l0xx_hal_uart.c:654:13:HAL_UART_MspInit	16	static
+stm32l0xx_hal_uart.c:669:13:HAL_UART_MspDeInit	16	static
+stm32l0xx_hal_uart.c:1087:19:HAL_UART_Transmit	48	static
+stm32l0xx_hal_uart.c:1188:19:HAL_UART_Receive	48	static
+stm32l0xx_hal_uart.c:1290:19:HAL_UART_Transmit_IT	40	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1359:19:HAL_UART_Receive_IT	40	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1418:19:HAL_UART_Transmit_DMA	40	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1510:19:HAL_UART_Receive_DMA	40	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1559:19:HAL_UART_DMAPause	88	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1593:19:HAL_UART_DMAResume	80	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1625:19:HAL_UART_DMAStop	56	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1700:19:HAL_UART_Abort	96	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1795:19:HAL_UART_AbortTransmit	48	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1847:19:HAL_UART_AbortReceive	80	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:1914:19:HAL_UART_Abort_IT	104	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:2060:19:HAL_UART_AbortTransmit_IT	48	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:2144:19:HAL_UART_AbortReceive_IT	80	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:2236:6:HAL_UART_IRQHandler	184	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:2527:13:HAL_UART_TxCpltCallback	16	static
+stm32l0xx_hal_uart.c:2542:13:HAL_UART_TxHalfCpltCallback	16	static
+stm32l0xx_hal_uart.c:2557:13:HAL_UART_RxCpltCallback	16	static
+stm32l0xx_hal_uart.c:2572:13:HAL_UART_RxHalfCpltCallback	16	static
+stm32l0xx_hal_uart.c:2587:13:HAL_UART_ErrorCallback	16	static
+stm32l0xx_hal_uart.c:2602:13:HAL_UART_AbortCpltCallback	16	static
+stm32l0xx_hal_uart.c:2617:13:HAL_UART_AbortTransmitCpltCallback	16	static
+stm32l0xx_hal_uart.c:2632:13:HAL_UART_AbortReceiveCpltCallback	16	static
+stm32l0xx_hal_uart.c:2649:13:HAL_UARTEx_RxEventCallback	16	static
+stm32l0xx_hal_uart.c:2697:6:HAL_UART_ReceiverTimeout_Config	16	static
+stm32l0xx_hal_uart.c:2712:19:HAL_UART_EnableReceiverTimeout	16	static
+stm32l0xx_hal_uart.c:2750:19:HAL_UART_DisableReceiverTimeout	16	static
+stm32l0xx_hal_uart.c:2788:19:HAL_MultiProcessor_EnableMuteMode	32	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:2808:19:HAL_MultiProcessor_DisableMuteMode	32	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:2828:6:HAL_MultiProcessor_EnterMuteMode	16	static
+stm32l0xx_hal_uart.c:2838:19:HAL_HalfDuplex_EnableTransmitter	48	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:2861:19:HAL_HalfDuplex_EnableReceiver	48	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:2885:19:HAL_LIN_SendBreak	16	static
+stm32l0xx_hal_uart.c:2930:23:HAL_UART_GetState	24	static
+stm32l0xx_hal_uart.c:2946:10:HAL_UART_GetError	16	static
+stm32l0xx_hal_uart.c:2990:19:UART_SetConfig	72	static
+stm32l0xx_hal_uart.c:3214:6:UART_AdvFeatureConfig	16	static
+stm32l0xx_hal_uart.c:3288:19:UART_CheckIdleState	32	static
+stm32l0xx_hal_uart.c:3339:19:UART_WaitOnFlagUntilTimeout	88	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3401:19:UART_Start_Receive_IT	56	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3445:19:UART_Start_Receive_DMA	72	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3502:13:UART_EndTxTransfer	32	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3517:13:UART_EndRxTransfer	64	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3543:13:UART_DMATransmitCplt	56	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3577:13:UART_DMATxHalfCplt	24	static
+stm32l0xx_hal_uart.c:3595:13:UART_DMAReceiveCplt	88	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3652:13:UART_DMARxHalfCplt	24	static
+stm32l0xx_hal_uart.c:3686:13:UART_DMAError	32	static
+stm32l0xx_hal_uart.c:3726:13:UART_DMAAbortOnError	24	static
+stm32l0xx_hal_uart.c:3749:13:UART_DMATxAbortCallback	24	static
+stm32l0xx_hal_uart.c:3799:13:UART_DMARxAbortCallback	24	static
+stm32l0xx_hal_uart.c:3851:13:UART_DMATxOnlyAbortCallback	24	static
+stm32l0xx_hal_uart.c:3879:13:UART_DMARxOnlyAbortCallback	24	static
+stm32l0xx_hal_uart.c:3912:13:UART_TxISR_8BIT	48	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3941:13:UART_TxISR_16BIT	56	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3973:13:UART_EndTransmit_IT	32	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:3998:13:UART_RxISR_8BIT	72	static,ignoring_inline_asm
+stm32l0xx_hal_uart.c:4075:13:UART_RxISR_16BIT	72	static,ignoring_inline_asm
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su
new file mode 100644
index 0000000..93233c0
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su
@@ -0,0 +1,12 @@
+stm32l0xx_hal_uart_ex.c:148:19:HAL_RS485Ex_Init	32	static
+stm32l0xx_hal_uart_ex.c:250:13:HAL_UARTEx_WakeupCallback	16	static
+stm32l0xx_hal_uart_ex.c:330:19:HAL_UARTEx_EnableClockStopMode	32	static,ignoring_inline_asm
+stm32l0xx_hal_uart_ex.c:349:19:HAL_UARTEx_DisableClockStopMode	32	static,ignoring_inline_asm
+stm32l0xx_hal_uart_ex.c:376:19:HAL_MultiProcessorEx_AddressLength_Set	16	static
+stm32l0xx_hal_uart_ex.c:414:19:HAL_UARTEx_StopModeWakeUpSourceConfig	40	static
+stm32l0xx_hal_uart_ex.c:469:19:HAL_UARTEx_EnableStopMode	32	static,ignoring_inline_asm
+stm32l0xx_hal_uart_ex.c:488:19:HAL_UARTEx_DisableStopMode	32	static,ignoring_inline_asm
+stm32l0xx_hal_uart_ex.c:524:19:HAL_UARTEx_ReceiveToIdle	40	static
+stm32l0xx_hal_uart_ex.c:665:19:HAL_UARTEx_ReceiveToIdle_IT	56	static,ignoring_inline_asm
+stm32l0xx_hal_uart_ex.c:743:19:HAL_UARTEx_ReceiveToIdle_DMA	56	static,ignoring_inline_asm
+stm32l0xx_hal_uart_ex.c:817:13:UARTEx_Wakeup_AddressConfig	24	static
diff --git a/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
new file mode 100644
index 0000000..c579eb3
--- /dev/null
+++ b/software/dumber3/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
@@ -0,0 +1,80 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c 
+
+OBJS += \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o 
+
+C_DEPS += \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Drivers/STM32L0xx_HAL_Driver/Src/%.o: ../Drivers/STM32L0xx_HAL_Driver/Src/%.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/software/dumber3/Debug/Dumber3.bin b/software/dumber3/Debug/Dumber3.bin
new file mode 100755
index 0000000..38769ab
Binary files /dev/null and b/software/dumber3/Debug/Dumber3.bin differ
diff --git a/software/dumber3/Debug/Dumber3.list b/software/dumber3/Debug/Dumber3.list
new file mode 100644
index 0000000..832081d
--- /dev/null
+++ b/software/dumber3/Debug/Dumber3.list
@@ -0,0 +1,22798 @@
+
+Dumber3.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .isr_vector   000000c0  08000000  08000000  00010000  2**0
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  1 .text         00007728  080000c0  080000c0  000100c0  2**4
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .rodata       00000130  080077e8  080077e8  000177e8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .ARM.extab    00000000  08007918  08007918  00020010  2**0
+                  CONTENTS
+  4 .ARM          00000008  08007918  08007918  00017918  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  5 .preinit_array 00000000  08007920  08007920  00020010  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  6 .init_array   00000004  08007920  08007920  00017920  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  7 .fini_array   00000004  08007924  08007924  00017924  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  8 .data         00000010  20000000  08007928  00020000  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  9 .bss          0000199c  20000010  08007938  00020010  2**2
+                  ALLOC
+ 10 ._user_heap_stack 00000604  200019ac  08007938  000219ac  2**0
+                  ALLOC
+ 11 .ARM.attributes 00000028  00000000  00000000  00020010  2**0
+                  CONTENTS, READONLY
+ 12 .debug_info   0001c98c  00000000  00000000  00020038  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_abbrev 00003b25  00000000  00000000  0003c9c4  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_aranges 00001650  00000000  00000000  000404f0  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_ranges 000014d8  00000000  00000000  00041b40  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_macro  00013dc2  00000000  00000000  00043018  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_line   00019121  00000000  00000000  00056dda  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .debug_str    0007a4cb  00000000  00000000  0006fefb  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 19 .comment      00000053  00000000  00000000  000ea3c6  2**0
+                  CONTENTS, READONLY
+ 20 .debug_frame  00005064  00000000  00000000  000ea41c  2**2
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+
+Disassembly of section .text:
+
+080000c0 <__do_global_dtors_aux>:
+ 80000c0:	b510      	push	{r4, lr}
+ 80000c2:	4c06      	ldr	r4, [pc, #24]	; (80000dc <__do_global_dtors_aux+0x1c>)
+ 80000c4:	7823      	ldrb	r3, [r4, #0]
+ 80000c6:	2b00      	cmp	r3, #0
+ 80000c8:	d107      	bne.n	80000da <__do_global_dtors_aux+0x1a>
+ 80000ca:	4b05      	ldr	r3, [pc, #20]	; (80000e0 <__do_global_dtors_aux+0x20>)
+ 80000cc:	2b00      	cmp	r3, #0
+ 80000ce:	d002      	beq.n	80000d6 <__do_global_dtors_aux+0x16>
+ 80000d0:	4804      	ldr	r0, [pc, #16]	; (80000e4 <__do_global_dtors_aux+0x24>)
+ 80000d2:	e000      	b.n	80000d6 <__do_global_dtors_aux+0x16>
+ 80000d4:	bf00      	nop
+ 80000d6:	2301      	movs	r3, #1
+ 80000d8:	7023      	strb	r3, [r4, #0]
+ 80000da:	bd10      	pop	{r4, pc}
+ 80000dc:	20000010 	.word	0x20000010
+ 80000e0:	00000000 	.word	0x00000000
+ 80000e4:	080077d0 	.word	0x080077d0
+
+080000e8 <frame_dummy>:
+ 80000e8:	4b04      	ldr	r3, [pc, #16]	; (80000fc <frame_dummy+0x14>)
+ 80000ea:	b510      	push	{r4, lr}
+ 80000ec:	2b00      	cmp	r3, #0
+ 80000ee:	d003      	beq.n	80000f8 <frame_dummy+0x10>
+ 80000f0:	4903      	ldr	r1, [pc, #12]	; (8000100 <frame_dummy+0x18>)
+ 80000f2:	4804      	ldr	r0, [pc, #16]	; (8000104 <frame_dummy+0x1c>)
+ 80000f4:	e000      	b.n	80000f8 <frame_dummy+0x10>
+ 80000f6:	bf00      	nop
+ 80000f8:	bd10      	pop	{r4, pc}
+ 80000fa:	46c0      	nop			; (mov r8, r8)
+ 80000fc:	00000000 	.word	0x00000000
+ 8000100:	20000014 	.word	0x20000014
+ 8000104:	080077d0 	.word	0x080077d0
+
+08000108 <__udivsi3>:
+ 8000108:	2200      	movs	r2, #0
+ 800010a:	0843      	lsrs	r3, r0, #1
+ 800010c:	428b      	cmp	r3, r1
+ 800010e:	d374      	bcc.n	80001fa <__udivsi3+0xf2>
+ 8000110:	0903      	lsrs	r3, r0, #4
+ 8000112:	428b      	cmp	r3, r1
+ 8000114:	d35f      	bcc.n	80001d6 <__udivsi3+0xce>
+ 8000116:	0a03      	lsrs	r3, r0, #8
+ 8000118:	428b      	cmp	r3, r1
+ 800011a:	d344      	bcc.n	80001a6 <__udivsi3+0x9e>
+ 800011c:	0b03      	lsrs	r3, r0, #12
+ 800011e:	428b      	cmp	r3, r1
+ 8000120:	d328      	bcc.n	8000174 <__udivsi3+0x6c>
+ 8000122:	0c03      	lsrs	r3, r0, #16
+ 8000124:	428b      	cmp	r3, r1
+ 8000126:	d30d      	bcc.n	8000144 <__udivsi3+0x3c>
+ 8000128:	22ff      	movs	r2, #255	; 0xff
+ 800012a:	0209      	lsls	r1, r1, #8
+ 800012c:	ba12      	rev	r2, r2
+ 800012e:	0c03      	lsrs	r3, r0, #16
+ 8000130:	428b      	cmp	r3, r1
+ 8000132:	d302      	bcc.n	800013a <__udivsi3+0x32>
+ 8000134:	1212      	asrs	r2, r2, #8
+ 8000136:	0209      	lsls	r1, r1, #8
+ 8000138:	d065      	beq.n	8000206 <__udivsi3+0xfe>
+ 800013a:	0b03      	lsrs	r3, r0, #12
+ 800013c:	428b      	cmp	r3, r1
+ 800013e:	d319      	bcc.n	8000174 <__udivsi3+0x6c>
+ 8000140:	e000      	b.n	8000144 <__udivsi3+0x3c>
+ 8000142:	0a09      	lsrs	r1, r1, #8
+ 8000144:	0bc3      	lsrs	r3, r0, #15
+ 8000146:	428b      	cmp	r3, r1
+ 8000148:	d301      	bcc.n	800014e <__udivsi3+0x46>
+ 800014a:	03cb      	lsls	r3, r1, #15
+ 800014c:	1ac0      	subs	r0, r0, r3
+ 800014e:	4152      	adcs	r2, r2
+ 8000150:	0b83      	lsrs	r3, r0, #14
+ 8000152:	428b      	cmp	r3, r1
+ 8000154:	d301      	bcc.n	800015a <__udivsi3+0x52>
+ 8000156:	038b      	lsls	r3, r1, #14
+ 8000158:	1ac0      	subs	r0, r0, r3
+ 800015a:	4152      	adcs	r2, r2
+ 800015c:	0b43      	lsrs	r3, r0, #13
+ 800015e:	428b      	cmp	r3, r1
+ 8000160:	d301      	bcc.n	8000166 <__udivsi3+0x5e>
+ 8000162:	034b      	lsls	r3, r1, #13
+ 8000164:	1ac0      	subs	r0, r0, r3
+ 8000166:	4152      	adcs	r2, r2
+ 8000168:	0b03      	lsrs	r3, r0, #12
+ 800016a:	428b      	cmp	r3, r1
+ 800016c:	d301      	bcc.n	8000172 <__udivsi3+0x6a>
+ 800016e:	030b      	lsls	r3, r1, #12
+ 8000170:	1ac0      	subs	r0, r0, r3
+ 8000172:	4152      	adcs	r2, r2
+ 8000174:	0ac3      	lsrs	r3, r0, #11
+ 8000176:	428b      	cmp	r3, r1
+ 8000178:	d301      	bcc.n	800017e <__udivsi3+0x76>
+ 800017a:	02cb      	lsls	r3, r1, #11
+ 800017c:	1ac0      	subs	r0, r0, r3
+ 800017e:	4152      	adcs	r2, r2
+ 8000180:	0a83      	lsrs	r3, r0, #10
+ 8000182:	428b      	cmp	r3, r1
+ 8000184:	d301      	bcc.n	800018a <__udivsi3+0x82>
+ 8000186:	028b      	lsls	r3, r1, #10
+ 8000188:	1ac0      	subs	r0, r0, r3
+ 800018a:	4152      	adcs	r2, r2
+ 800018c:	0a43      	lsrs	r3, r0, #9
+ 800018e:	428b      	cmp	r3, r1
+ 8000190:	d301      	bcc.n	8000196 <__udivsi3+0x8e>
+ 8000192:	024b      	lsls	r3, r1, #9
+ 8000194:	1ac0      	subs	r0, r0, r3
+ 8000196:	4152      	adcs	r2, r2
+ 8000198:	0a03      	lsrs	r3, r0, #8
+ 800019a:	428b      	cmp	r3, r1
+ 800019c:	d301      	bcc.n	80001a2 <__udivsi3+0x9a>
+ 800019e:	020b      	lsls	r3, r1, #8
+ 80001a0:	1ac0      	subs	r0, r0, r3
+ 80001a2:	4152      	adcs	r2, r2
+ 80001a4:	d2cd      	bcs.n	8000142 <__udivsi3+0x3a>
+ 80001a6:	09c3      	lsrs	r3, r0, #7
+ 80001a8:	428b      	cmp	r3, r1
+ 80001aa:	d301      	bcc.n	80001b0 <__udivsi3+0xa8>
+ 80001ac:	01cb      	lsls	r3, r1, #7
+ 80001ae:	1ac0      	subs	r0, r0, r3
+ 80001b0:	4152      	adcs	r2, r2
+ 80001b2:	0983      	lsrs	r3, r0, #6
+ 80001b4:	428b      	cmp	r3, r1
+ 80001b6:	d301      	bcc.n	80001bc <__udivsi3+0xb4>
+ 80001b8:	018b      	lsls	r3, r1, #6
+ 80001ba:	1ac0      	subs	r0, r0, r3
+ 80001bc:	4152      	adcs	r2, r2
+ 80001be:	0943      	lsrs	r3, r0, #5
+ 80001c0:	428b      	cmp	r3, r1
+ 80001c2:	d301      	bcc.n	80001c8 <__udivsi3+0xc0>
+ 80001c4:	014b      	lsls	r3, r1, #5
+ 80001c6:	1ac0      	subs	r0, r0, r3
+ 80001c8:	4152      	adcs	r2, r2
+ 80001ca:	0903      	lsrs	r3, r0, #4
+ 80001cc:	428b      	cmp	r3, r1
+ 80001ce:	d301      	bcc.n	80001d4 <__udivsi3+0xcc>
+ 80001d0:	010b      	lsls	r3, r1, #4
+ 80001d2:	1ac0      	subs	r0, r0, r3
+ 80001d4:	4152      	adcs	r2, r2
+ 80001d6:	08c3      	lsrs	r3, r0, #3
+ 80001d8:	428b      	cmp	r3, r1
+ 80001da:	d301      	bcc.n	80001e0 <__udivsi3+0xd8>
+ 80001dc:	00cb      	lsls	r3, r1, #3
+ 80001de:	1ac0      	subs	r0, r0, r3
+ 80001e0:	4152      	adcs	r2, r2
+ 80001e2:	0883      	lsrs	r3, r0, #2
+ 80001e4:	428b      	cmp	r3, r1
+ 80001e6:	d301      	bcc.n	80001ec <__udivsi3+0xe4>
+ 80001e8:	008b      	lsls	r3, r1, #2
+ 80001ea:	1ac0      	subs	r0, r0, r3
+ 80001ec:	4152      	adcs	r2, r2
+ 80001ee:	0843      	lsrs	r3, r0, #1
+ 80001f0:	428b      	cmp	r3, r1
+ 80001f2:	d301      	bcc.n	80001f8 <__udivsi3+0xf0>
+ 80001f4:	004b      	lsls	r3, r1, #1
+ 80001f6:	1ac0      	subs	r0, r0, r3
+ 80001f8:	4152      	adcs	r2, r2
+ 80001fa:	1a41      	subs	r1, r0, r1
+ 80001fc:	d200      	bcs.n	8000200 <__udivsi3+0xf8>
+ 80001fe:	4601      	mov	r1, r0
+ 8000200:	4152      	adcs	r2, r2
+ 8000202:	4610      	mov	r0, r2
+ 8000204:	4770      	bx	lr
+ 8000206:	e7ff      	b.n	8000208 <__udivsi3+0x100>
+ 8000208:	b501      	push	{r0, lr}
+ 800020a:	2000      	movs	r0, #0
+ 800020c:	f000 f806 	bl	800021c <__aeabi_idiv0>
+ 8000210:	bd02      	pop	{r1, pc}
+ 8000212:	46c0      	nop			; (mov r8, r8)
+
+08000214 <__aeabi_uidivmod>:
+ 8000214:	2900      	cmp	r1, #0
+ 8000216:	d0f7      	beq.n	8000208 <__udivsi3+0x100>
+ 8000218:	e776      	b.n	8000108 <__udivsi3>
+ 800021a:	4770      	bx	lr
+
+0800021c <__aeabi_idiv0>:
+ 800021c:	4770      	bx	lr
+ 800021e:	46c0      	nop			; (mov r8, r8)
+
+08000220 <__aeabi_uldivmod>:
+ 8000220:	2b00      	cmp	r3, #0
+ 8000222:	d111      	bne.n	8000248 <__aeabi_uldivmod+0x28>
+ 8000224:	2a00      	cmp	r2, #0
+ 8000226:	d10f      	bne.n	8000248 <__aeabi_uldivmod+0x28>
+ 8000228:	2900      	cmp	r1, #0
+ 800022a:	d100      	bne.n	800022e <__aeabi_uldivmod+0xe>
+ 800022c:	2800      	cmp	r0, #0
+ 800022e:	d002      	beq.n	8000236 <__aeabi_uldivmod+0x16>
+ 8000230:	2100      	movs	r1, #0
+ 8000232:	43c9      	mvns	r1, r1
+ 8000234:	1c08      	adds	r0, r1, #0
+ 8000236:	b407      	push	{r0, r1, r2}
+ 8000238:	4802      	ldr	r0, [pc, #8]	; (8000244 <__aeabi_uldivmod+0x24>)
+ 800023a:	a102      	add	r1, pc, #8	; (adr r1, 8000244 <__aeabi_uldivmod+0x24>)
+ 800023c:	1840      	adds	r0, r0, r1
+ 800023e:	9002      	str	r0, [sp, #8]
+ 8000240:	bd03      	pop	{r0, r1, pc}
+ 8000242:	46c0      	nop			; (mov r8, r8)
+ 8000244:	ffffffd9 	.word	0xffffffd9
+ 8000248:	b403      	push	{r0, r1}
+ 800024a:	4668      	mov	r0, sp
+ 800024c:	b501      	push	{r0, lr}
+ 800024e:	9802      	ldr	r0, [sp, #8]
+ 8000250:	f000 f82e 	bl	80002b0 <__udivmoddi4>
+ 8000254:	9b01      	ldr	r3, [sp, #4]
+ 8000256:	469e      	mov	lr, r3
+ 8000258:	b002      	add	sp, #8
+ 800025a:	bc0c      	pop	{r2, r3}
+ 800025c:	4770      	bx	lr
+ 800025e:	46c0      	nop			; (mov r8, r8)
+
+08000260 <__aeabi_lmul>:
+ 8000260:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 8000262:	0415      	lsls	r5, r2, #16
+ 8000264:	0c2d      	lsrs	r5, r5, #16
+ 8000266:	000f      	movs	r7, r1
+ 8000268:	0001      	movs	r1, r0
+ 800026a:	002e      	movs	r6, r5
+ 800026c:	46c6      	mov	lr, r8
+ 800026e:	4684      	mov	ip, r0
+ 8000270:	0400      	lsls	r0, r0, #16
+ 8000272:	0c14      	lsrs	r4, r2, #16
+ 8000274:	0c00      	lsrs	r0, r0, #16
+ 8000276:	0c09      	lsrs	r1, r1, #16
+ 8000278:	4346      	muls	r6, r0
+ 800027a:	434d      	muls	r5, r1
+ 800027c:	4360      	muls	r0, r4
+ 800027e:	4361      	muls	r1, r4
+ 8000280:	1940      	adds	r0, r0, r5
+ 8000282:	0c34      	lsrs	r4, r6, #16
+ 8000284:	1824      	adds	r4, r4, r0
+ 8000286:	b500      	push	{lr}
+ 8000288:	42a5      	cmp	r5, r4
+ 800028a:	d903      	bls.n	8000294 <__aeabi_lmul+0x34>
+ 800028c:	2080      	movs	r0, #128	; 0x80
+ 800028e:	0240      	lsls	r0, r0, #9
+ 8000290:	4680      	mov	r8, r0
+ 8000292:	4441      	add	r1, r8
+ 8000294:	0c25      	lsrs	r5, r4, #16
+ 8000296:	186d      	adds	r5, r5, r1
+ 8000298:	4661      	mov	r1, ip
+ 800029a:	4359      	muls	r1, r3
+ 800029c:	437a      	muls	r2, r7
+ 800029e:	0430      	lsls	r0, r6, #16
+ 80002a0:	1949      	adds	r1, r1, r5
+ 80002a2:	0424      	lsls	r4, r4, #16
+ 80002a4:	0c00      	lsrs	r0, r0, #16
+ 80002a6:	1820      	adds	r0, r4, r0
+ 80002a8:	1889      	adds	r1, r1, r2
+ 80002aa:	bc80      	pop	{r7}
+ 80002ac:	46b8      	mov	r8, r7
+ 80002ae:	bdf0      	pop	{r4, r5, r6, r7, pc}
+
+080002b0 <__udivmoddi4>:
+ 80002b0:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 80002b2:	4657      	mov	r7, sl
+ 80002b4:	464e      	mov	r6, r9
+ 80002b6:	4645      	mov	r5, r8
+ 80002b8:	46de      	mov	lr, fp
+ 80002ba:	b5e0      	push	{r5, r6, r7, lr}
+ 80002bc:	0004      	movs	r4, r0
+ 80002be:	000d      	movs	r5, r1
+ 80002c0:	4692      	mov	sl, r2
+ 80002c2:	4699      	mov	r9, r3
+ 80002c4:	b083      	sub	sp, #12
+ 80002c6:	428b      	cmp	r3, r1
+ 80002c8:	d830      	bhi.n	800032c <__udivmoddi4+0x7c>
+ 80002ca:	d02d      	beq.n	8000328 <__udivmoddi4+0x78>
+ 80002cc:	4649      	mov	r1, r9
+ 80002ce:	4650      	mov	r0, sl
+ 80002d0:	f000 f8ba 	bl	8000448 <__clzdi2>
+ 80002d4:	0029      	movs	r1, r5
+ 80002d6:	0006      	movs	r6, r0
+ 80002d8:	0020      	movs	r0, r4
+ 80002da:	f000 f8b5 	bl	8000448 <__clzdi2>
+ 80002de:	1a33      	subs	r3, r6, r0
+ 80002e0:	4698      	mov	r8, r3
+ 80002e2:	3b20      	subs	r3, #32
+ 80002e4:	469b      	mov	fp, r3
+ 80002e6:	d433      	bmi.n	8000350 <__udivmoddi4+0xa0>
+ 80002e8:	465a      	mov	r2, fp
+ 80002ea:	4653      	mov	r3, sl
+ 80002ec:	4093      	lsls	r3, r2
+ 80002ee:	4642      	mov	r2, r8
+ 80002f0:	001f      	movs	r7, r3
+ 80002f2:	4653      	mov	r3, sl
+ 80002f4:	4093      	lsls	r3, r2
+ 80002f6:	001e      	movs	r6, r3
+ 80002f8:	42af      	cmp	r7, r5
+ 80002fa:	d83a      	bhi.n	8000372 <__udivmoddi4+0xc2>
+ 80002fc:	42af      	cmp	r7, r5
+ 80002fe:	d100      	bne.n	8000302 <__udivmoddi4+0x52>
+ 8000300:	e078      	b.n	80003f4 <__udivmoddi4+0x144>
+ 8000302:	465b      	mov	r3, fp
+ 8000304:	1ba4      	subs	r4, r4, r6
+ 8000306:	41bd      	sbcs	r5, r7
+ 8000308:	2b00      	cmp	r3, #0
+ 800030a:	da00      	bge.n	800030e <__udivmoddi4+0x5e>
+ 800030c:	e075      	b.n	80003fa <__udivmoddi4+0x14a>
+ 800030e:	2200      	movs	r2, #0
+ 8000310:	2300      	movs	r3, #0
+ 8000312:	9200      	str	r2, [sp, #0]
+ 8000314:	9301      	str	r3, [sp, #4]
+ 8000316:	2301      	movs	r3, #1
+ 8000318:	465a      	mov	r2, fp
+ 800031a:	4093      	lsls	r3, r2
+ 800031c:	9301      	str	r3, [sp, #4]
+ 800031e:	2301      	movs	r3, #1
+ 8000320:	4642      	mov	r2, r8
+ 8000322:	4093      	lsls	r3, r2
+ 8000324:	9300      	str	r3, [sp, #0]
+ 8000326:	e028      	b.n	800037a <__udivmoddi4+0xca>
+ 8000328:	4282      	cmp	r2, r0
+ 800032a:	d9cf      	bls.n	80002cc <__udivmoddi4+0x1c>
+ 800032c:	2200      	movs	r2, #0
+ 800032e:	2300      	movs	r3, #0
+ 8000330:	9200      	str	r2, [sp, #0]
+ 8000332:	9301      	str	r3, [sp, #4]
+ 8000334:	9b0c      	ldr	r3, [sp, #48]	; 0x30
+ 8000336:	2b00      	cmp	r3, #0
+ 8000338:	d001      	beq.n	800033e <__udivmoddi4+0x8e>
+ 800033a:	601c      	str	r4, [r3, #0]
+ 800033c:	605d      	str	r5, [r3, #4]
+ 800033e:	9800      	ldr	r0, [sp, #0]
+ 8000340:	9901      	ldr	r1, [sp, #4]
+ 8000342:	b003      	add	sp, #12
+ 8000344:	bcf0      	pop	{r4, r5, r6, r7}
+ 8000346:	46bb      	mov	fp, r7
+ 8000348:	46b2      	mov	sl, r6
+ 800034a:	46a9      	mov	r9, r5
+ 800034c:	46a0      	mov	r8, r4
+ 800034e:	bdf0      	pop	{r4, r5, r6, r7, pc}
+ 8000350:	4642      	mov	r2, r8
+ 8000352:	2320      	movs	r3, #32
+ 8000354:	1a9b      	subs	r3, r3, r2
+ 8000356:	4652      	mov	r2, sl
+ 8000358:	40da      	lsrs	r2, r3
+ 800035a:	4641      	mov	r1, r8
+ 800035c:	0013      	movs	r3, r2
+ 800035e:	464a      	mov	r2, r9
+ 8000360:	408a      	lsls	r2, r1
+ 8000362:	0017      	movs	r7, r2
+ 8000364:	4642      	mov	r2, r8
+ 8000366:	431f      	orrs	r7, r3
+ 8000368:	4653      	mov	r3, sl
+ 800036a:	4093      	lsls	r3, r2
+ 800036c:	001e      	movs	r6, r3
+ 800036e:	42af      	cmp	r7, r5
+ 8000370:	d9c4      	bls.n	80002fc <__udivmoddi4+0x4c>
+ 8000372:	2200      	movs	r2, #0
+ 8000374:	2300      	movs	r3, #0
+ 8000376:	9200      	str	r2, [sp, #0]
+ 8000378:	9301      	str	r3, [sp, #4]
+ 800037a:	4643      	mov	r3, r8
+ 800037c:	2b00      	cmp	r3, #0
+ 800037e:	d0d9      	beq.n	8000334 <__udivmoddi4+0x84>
+ 8000380:	07fb      	lsls	r3, r7, #31
+ 8000382:	0872      	lsrs	r2, r6, #1
+ 8000384:	431a      	orrs	r2, r3
+ 8000386:	4646      	mov	r6, r8
+ 8000388:	087b      	lsrs	r3, r7, #1
+ 800038a:	e00e      	b.n	80003aa <__udivmoddi4+0xfa>
+ 800038c:	42ab      	cmp	r3, r5
+ 800038e:	d101      	bne.n	8000394 <__udivmoddi4+0xe4>
+ 8000390:	42a2      	cmp	r2, r4
+ 8000392:	d80c      	bhi.n	80003ae <__udivmoddi4+0xfe>
+ 8000394:	1aa4      	subs	r4, r4, r2
+ 8000396:	419d      	sbcs	r5, r3
+ 8000398:	2001      	movs	r0, #1
+ 800039a:	1924      	adds	r4, r4, r4
+ 800039c:	416d      	adcs	r5, r5
+ 800039e:	2100      	movs	r1, #0
+ 80003a0:	3e01      	subs	r6, #1
+ 80003a2:	1824      	adds	r4, r4, r0
+ 80003a4:	414d      	adcs	r5, r1
+ 80003a6:	2e00      	cmp	r6, #0
+ 80003a8:	d006      	beq.n	80003b8 <__udivmoddi4+0x108>
+ 80003aa:	42ab      	cmp	r3, r5
+ 80003ac:	d9ee      	bls.n	800038c <__udivmoddi4+0xdc>
+ 80003ae:	3e01      	subs	r6, #1
+ 80003b0:	1924      	adds	r4, r4, r4
+ 80003b2:	416d      	adcs	r5, r5
+ 80003b4:	2e00      	cmp	r6, #0
+ 80003b6:	d1f8      	bne.n	80003aa <__udivmoddi4+0xfa>
+ 80003b8:	9800      	ldr	r0, [sp, #0]
+ 80003ba:	9901      	ldr	r1, [sp, #4]
+ 80003bc:	465b      	mov	r3, fp
+ 80003be:	1900      	adds	r0, r0, r4
+ 80003c0:	4169      	adcs	r1, r5
+ 80003c2:	2b00      	cmp	r3, #0
+ 80003c4:	db24      	blt.n	8000410 <__udivmoddi4+0x160>
+ 80003c6:	002b      	movs	r3, r5
+ 80003c8:	465a      	mov	r2, fp
+ 80003ca:	4644      	mov	r4, r8
+ 80003cc:	40d3      	lsrs	r3, r2
+ 80003ce:	002a      	movs	r2, r5
+ 80003d0:	40e2      	lsrs	r2, r4
+ 80003d2:	001c      	movs	r4, r3
+ 80003d4:	465b      	mov	r3, fp
+ 80003d6:	0015      	movs	r5, r2
+ 80003d8:	2b00      	cmp	r3, #0
+ 80003da:	db2a      	blt.n	8000432 <__udivmoddi4+0x182>
+ 80003dc:	0026      	movs	r6, r4
+ 80003de:	409e      	lsls	r6, r3
+ 80003e0:	0033      	movs	r3, r6
+ 80003e2:	0026      	movs	r6, r4
+ 80003e4:	4647      	mov	r7, r8
+ 80003e6:	40be      	lsls	r6, r7
+ 80003e8:	0032      	movs	r2, r6
+ 80003ea:	1a80      	subs	r0, r0, r2
+ 80003ec:	4199      	sbcs	r1, r3
+ 80003ee:	9000      	str	r0, [sp, #0]
+ 80003f0:	9101      	str	r1, [sp, #4]
+ 80003f2:	e79f      	b.n	8000334 <__udivmoddi4+0x84>
+ 80003f4:	42a3      	cmp	r3, r4
+ 80003f6:	d8bc      	bhi.n	8000372 <__udivmoddi4+0xc2>
+ 80003f8:	e783      	b.n	8000302 <__udivmoddi4+0x52>
+ 80003fa:	4642      	mov	r2, r8
+ 80003fc:	2320      	movs	r3, #32
+ 80003fe:	2100      	movs	r1, #0
+ 8000400:	1a9b      	subs	r3, r3, r2
+ 8000402:	2200      	movs	r2, #0
+ 8000404:	9100      	str	r1, [sp, #0]
+ 8000406:	9201      	str	r2, [sp, #4]
+ 8000408:	2201      	movs	r2, #1
+ 800040a:	40da      	lsrs	r2, r3
+ 800040c:	9201      	str	r2, [sp, #4]
+ 800040e:	e786      	b.n	800031e <__udivmoddi4+0x6e>
+ 8000410:	4642      	mov	r2, r8
+ 8000412:	2320      	movs	r3, #32
+ 8000414:	1a9b      	subs	r3, r3, r2
+ 8000416:	002a      	movs	r2, r5
+ 8000418:	4646      	mov	r6, r8
+ 800041a:	409a      	lsls	r2, r3
+ 800041c:	0023      	movs	r3, r4
+ 800041e:	40f3      	lsrs	r3, r6
+ 8000420:	4644      	mov	r4, r8
+ 8000422:	4313      	orrs	r3, r2
+ 8000424:	002a      	movs	r2, r5
+ 8000426:	40e2      	lsrs	r2, r4
+ 8000428:	001c      	movs	r4, r3
+ 800042a:	465b      	mov	r3, fp
+ 800042c:	0015      	movs	r5, r2
+ 800042e:	2b00      	cmp	r3, #0
+ 8000430:	dad4      	bge.n	80003dc <__udivmoddi4+0x12c>
+ 8000432:	4642      	mov	r2, r8
+ 8000434:	002f      	movs	r7, r5
+ 8000436:	2320      	movs	r3, #32
+ 8000438:	0026      	movs	r6, r4
+ 800043a:	4097      	lsls	r7, r2
+ 800043c:	1a9b      	subs	r3, r3, r2
+ 800043e:	40de      	lsrs	r6, r3
+ 8000440:	003b      	movs	r3, r7
+ 8000442:	4333      	orrs	r3, r6
+ 8000444:	e7cd      	b.n	80003e2 <__udivmoddi4+0x132>
+ 8000446:	46c0      	nop			; (mov r8, r8)
+
+08000448 <__clzdi2>:
+ 8000448:	b510      	push	{r4, lr}
+ 800044a:	2900      	cmp	r1, #0
+ 800044c:	d103      	bne.n	8000456 <__clzdi2+0xe>
+ 800044e:	f000 f807 	bl	8000460 <__clzsi2>
+ 8000452:	3020      	adds	r0, #32
+ 8000454:	e002      	b.n	800045c <__clzdi2+0x14>
+ 8000456:	1c08      	adds	r0, r1, #0
+ 8000458:	f000 f802 	bl	8000460 <__clzsi2>
+ 800045c:	bd10      	pop	{r4, pc}
+ 800045e:	46c0      	nop			; (mov r8, r8)
+
+08000460 <__clzsi2>:
+ 8000460:	211c      	movs	r1, #28
+ 8000462:	2301      	movs	r3, #1
+ 8000464:	041b      	lsls	r3, r3, #16
+ 8000466:	4298      	cmp	r0, r3
+ 8000468:	d301      	bcc.n	800046e <__clzsi2+0xe>
+ 800046a:	0c00      	lsrs	r0, r0, #16
+ 800046c:	3910      	subs	r1, #16
+ 800046e:	0a1b      	lsrs	r3, r3, #8
+ 8000470:	4298      	cmp	r0, r3
+ 8000472:	d301      	bcc.n	8000478 <__clzsi2+0x18>
+ 8000474:	0a00      	lsrs	r0, r0, #8
+ 8000476:	3908      	subs	r1, #8
+ 8000478:	091b      	lsrs	r3, r3, #4
+ 800047a:	4298      	cmp	r0, r3
+ 800047c:	d301      	bcc.n	8000482 <__clzsi2+0x22>
+ 800047e:	0900      	lsrs	r0, r0, #4
+ 8000480:	3904      	subs	r1, #4
+ 8000482:	a202      	add	r2, pc, #8	; (adr r2, 800048c <__clzsi2+0x2c>)
+ 8000484:	5c10      	ldrb	r0, [r2, r0]
+ 8000486:	1840      	adds	r0, r0, r1
+ 8000488:	4770      	bx	lr
+ 800048a:	46c0      	nop			; (mov r8, r8)
+ 800048c:	02020304 	.word	0x02020304
+ 8000490:	01010101 	.word	0x01010101
+	...
+
+0800049c <PreSleepProcessing>:
+
+/* USER CODE END FunctionPrototypes */
+
+/* USER CODE BEGIN PREPOSTSLEEP */
+__weak void PreSleepProcessing(uint32_t *ulExpectedIdleTime)
+{
+ 800049c:	b580      	push	{r7, lr}
+ 800049e:	b082      	sub	sp, #8
+ 80004a0:	af00      	add	r7, sp, #0
+ 80004a2:	6078      	str	r0, [r7, #4]
+/* place for user code */
+}
+ 80004a4:	46c0      	nop			; (mov r8, r8)
+ 80004a6:	46bd      	mov	sp, r7
+ 80004a8:	b002      	add	sp, #8
+ 80004aa:	bd80      	pop	{r7, pc}
+
+080004ac <PostSleepProcessing>:
+
+__weak void PostSleepProcessing(uint32_t *ulExpectedIdleTime)
+{
+ 80004ac:	b580      	push	{r7, lr}
+ 80004ae:	b082      	sub	sp, #8
+ 80004b0:	af00      	add	r7, sp, #0
+ 80004b2:	6078      	str	r0, [r7, #4]
+/* place for user code */
+}
+ 80004b4:	46c0      	nop			; (mov r8, r8)
+ 80004b6:	46bd      	mov	sp, r7
+ 80004b8:	b002      	add	sp, #8
+ 80004ba:	bd80      	pop	{r7, pc}
+
+080004bc <LEDS_Init>:
+StackType_t xStackLeds[ STACK_SIZE ];
+TaskHandle_t xHandleLeds = NULL;
+
+void LEDS_AnimationThread(void* params);
+
+void LEDS_Init(void) {
+ 80004bc:	b580      	push	{r7, lr}
+ 80004be:	b084      	sub	sp, #16
+ 80004c0:	af04      	add	r7, sp, #16
+	LEDS_EteintVerte();
+ 80004c2:	2380      	movs	r3, #128	; 0x80
+ 80004c4:	01db      	lsls	r3, r3, #7
+ 80004c6:	4816      	ldr	r0, [pc, #88]	; (8000520 <LEDS_Init+0x64>)
+ 80004c8:	2200      	movs	r2, #0
+ 80004ca:	0019      	movs	r1, r3
+ 80004cc:	f002 f818 	bl	8002500 <HAL_GPIO_WritePin>
+	LEDS_EteintJaune();
+ 80004d0:	2380      	movs	r3, #128	; 0x80
+ 80004d2:	019b      	lsls	r3, r3, #6
+ 80004d4:	4812      	ldr	r0, [pc, #72]	; (8000520 <LEDS_Init+0x64>)
+ 80004d6:	2200      	movs	r2, #0
+ 80004d8:	0019      	movs	r1, r3
+ 80004da:	f002 f811 	bl	8002500 <HAL_GPIO_WritePin>
+	LEDS_EteintRouge();
+ 80004de:	2380      	movs	r3, #128	; 0x80
+ 80004e0:	015b      	lsls	r3, r3, #5
+ 80004e2:	480f      	ldr	r0, [pc, #60]	; (8000520 <LEDS_Init+0x64>)
+ 80004e4:	2200      	movs	r2, #0
+ 80004e6:	0019      	movs	r1, r3
+ 80004e8:	f002 f80a 	bl	8002500 <HAL_GPIO_WritePin>
+
+	LEDS_Animation=leds_off;
+ 80004ec:	4b0d      	ldr	r3, [pc, #52]	; (8000524 <LEDS_Init+0x68>)
+ 80004ee:	2200      	movs	r2, #0
+ 80004f0:	701a      	strb	r2, [r3, #0]
+
+	/* Mailbox is created in messages.c */
+
+	/* Create the task without using any dynamic memory allocation. */
+	xHandleLeds = xTaskCreateStatic(
+ 80004f2:	490d      	ldr	r1, [pc, #52]	; (8000528 <LEDS_Init+0x6c>)
+ 80004f4:	480d      	ldr	r0, [pc, #52]	; (800052c <LEDS_Init+0x70>)
+ 80004f6:	4b0e      	ldr	r3, [pc, #56]	; (8000530 <LEDS_Init+0x74>)
+ 80004f8:	9302      	str	r3, [sp, #8]
+ 80004fa:	4b0e      	ldr	r3, [pc, #56]	; (8000534 <LEDS_Init+0x78>)
+ 80004fc:	9301      	str	r3, [sp, #4]
+ 80004fe:	2333      	movs	r3, #51	; 0x33
+ 8000500:	9300      	str	r3, [sp, #0]
+ 8000502:	2300      	movs	r3, #0
+ 8000504:	2264      	movs	r2, #100	; 0x64
+ 8000506:	f005 fae4 	bl	8005ad2 <xTaskCreateStatic>
+ 800050a:	0002      	movs	r2, r0
+ 800050c:	4b0a      	ldr	r3, [pc, #40]	; (8000538 <LEDS_Init+0x7c>)
+ 800050e:	601a      	str	r2, [r3, #0]
+			STACK_SIZE,      /* Number of indexes in the xStack array. */
+			NULL,    /* Parameter passed into the task. */
+			PriorityLeds,/* Priority at which the task is created. */
+			xStackLeds,          /* Array to use as the task's stack. */
+			&xTaskLeds);  /* Variable to hold the task's data structure. */
+	vTaskResume(xHandleLeds);
+ 8000510:	4b09      	ldr	r3, [pc, #36]	; (8000538 <LEDS_Init+0x7c>)
+ 8000512:	681b      	ldr	r3, [r3, #0]
+ 8000514:	0018      	movs	r0, r3
+ 8000516:	f005 fcaf 	bl	8005e78 <vTaskResume>
+}
+ 800051a:	46c0      	nop			; (mov r8, r8)
+ 800051c:	46bd      	mov	sp, r7
+ 800051e:	bd80      	pop	{r7, pc}
+ 8000520:	50000400 	.word	0x50000400
+ 8000524:	2000153c 	.word	0x2000153c
+ 8000528:	080077e8 	.word	0x080077e8
+ 800052c:	0800053d 	.word	0x0800053d
+ 8000530:	200016d4 	.word	0x200016d4
+ 8000534:	20001540 	.word	0x20001540
+ 8000538:	2000002c 	.word	0x2000002c
+
+0800053c <LEDS_AnimationThread>:
+
+void LEDS_RegleAnimation(LEDS_State etat) {
+	LEDS_Animation=etat;
+}
+
+void LEDS_AnimationThread(void* params) {
+ 800053c:	b5b0      	push	{r4, r5, r7, lr}
+ 800053e:	b086      	sub	sp, #24
+ 8000540:	af00      	add	r7, sp, #0
+ 8000542:	6078      	str	r0, [r7, #4]
+	MESSAGE_Typedef msg;
+	uint8_t cnt=0;
+ 8000544:	2317      	movs	r3, #23
+ 8000546:	18fb      	adds	r3, r7, r3
+ 8000548:	2200      	movs	r2, #0
+ 800054a:	701a      	strb	r2, [r3, #0]
+
+	while (1) {
+		vTaskDelay(pdMS_TO_TICKS(100));
+ 800054c:	200a      	movs	r0, #10
+ 800054e:	f005 fc47 	bl	8005de0 <vTaskDelay>
+
+		msg = MESSAGE_ReadMailboxNoDelay(LEDS_Mailbox);
+ 8000552:	4bdc      	ldr	r3, [pc, #880]	; (80008c4 <LEDS_AnimationThread+0x388>)
+ 8000554:	681a      	ldr	r2, [r3, #0]
+ 8000556:	2408      	movs	r4, #8
+ 8000558:	193b      	adds	r3, r7, r4
+ 800055a:	0011      	movs	r1, r2
+ 800055c:	0018      	movs	r0, r3
+ 800055e:	f000 fda7 	bl	80010b0 <MESSAGE_ReadMailboxNoDelay>
+
+		cnt++;
+ 8000562:	2517      	movs	r5, #23
+ 8000564:	197b      	adds	r3, r7, r5
+ 8000566:	781a      	ldrb	r2, [r3, #0]
+ 8000568:	197b      	adds	r3, r7, r5
+ 800056a:	3201      	adds	r2, #1
+ 800056c:	701a      	strb	r2, [r3, #0]
+
+		if (msg.id == MSG_ID_LED_ETAT) { // Si c'est bien un message de changemnet d'etat LEDS
+ 800056e:	193b      	adds	r3, r7, r4
+ 8000570:	881b      	ldrh	r3, [r3, #0]
+ 8000572:	2b00      	cmp	r3, #0
+ 8000574:	d126      	bne.n	80005c4 <LEDS_AnimationThread+0x88>
+			LEDS_Animation = *((LEDS_State*)msg.data);
+ 8000576:	193b      	adds	r3, r7, r4
+ 8000578:	689b      	ldr	r3, [r3, #8]
+ 800057a:	781a      	ldrb	r2, [r3, #0]
+ 800057c:	4bd2      	ldr	r3, [pc, #840]	; (80008c8 <LEDS_AnimationThread+0x38c>)
+ 800057e:	701a      	strb	r2, [r3, #0]
+
+			if (LEDS_Animation != LEDS_AnimationAncien) { 	// si le nouvel etat est different de l'ancien
+ 8000580:	4bd1      	ldr	r3, [pc, #836]	; (80008c8 <LEDS_AnimationThread+0x38c>)
+ 8000582:	781a      	ldrb	r2, [r3, #0]
+ 8000584:	4bd1      	ldr	r3, [pc, #836]	; (80008cc <LEDS_AnimationThread+0x390>)
+ 8000586:	781b      	ldrb	r3, [r3, #0]
+ 8000588:	429a      	cmp	r2, r3
+ 800058a:	d01b      	beq.n	80005c4 <LEDS_AnimationThread+0x88>
+				// dans ce cas, on eteint les leds pour repartir sur une base saine
+				LEDS_AnimationAncien = LEDS_Animation;
+ 800058c:	4bce      	ldr	r3, [pc, #824]	; (80008c8 <LEDS_AnimationThread+0x38c>)
+ 800058e:	781a      	ldrb	r2, [r3, #0]
+ 8000590:	4bce      	ldr	r3, [pc, #824]	; (80008cc <LEDS_AnimationThread+0x390>)
+ 8000592:	701a      	strb	r2, [r3, #0]
+
+				LEDS_EteintVerte();
+ 8000594:	2380      	movs	r3, #128	; 0x80
+ 8000596:	01db      	lsls	r3, r3, #7
+ 8000598:	48cd      	ldr	r0, [pc, #820]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800059a:	2200      	movs	r2, #0
+ 800059c:	0019      	movs	r1, r3
+ 800059e:	f001 ffaf 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintJaune();
+ 80005a2:	2380      	movs	r3, #128	; 0x80
+ 80005a4:	019b      	lsls	r3, r3, #6
+ 80005a6:	48ca      	ldr	r0, [pc, #808]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80005a8:	2200      	movs	r2, #0
+ 80005aa:	0019      	movs	r1, r3
+ 80005ac:	f001 ffa8 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintRouge();
+ 80005b0:	2380      	movs	r3, #128	; 0x80
+ 80005b2:	015b      	lsls	r3, r3, #5
+ 80005b4:	48c6      	ldr	r0, [pc, #792]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80005b6:	2200      	movs	r2, #0
+ 80005b8:	0019      	movs	r1, r3
+ 80005ba:	f001 ffa1 	bl	8002500 <HAL_GPIO_WritePin>
+				cnt=0;
+ 80005be:	197b      	adds	r3, r7, r5
+ 80005c0:	2200      	movs	r2, #0
+ 80005c2:	701a      	strb	r2, [r3, #0]
+			}
+		}
+
+		switch (LEDS_Animation) {
+ 80005c4:	4bc0      	ldr	r3, [pc, #768]	; (80008c8 <LEDS_AnimationThread+0x38c>)
+ 80005c6:	781b      	ldrb	r3, [r3, #0]
+ 80005c8:	2b10      	cmp	r3, #16
+ 80005ca:	d900      	bls.n	80005ce <LEDS_AnimationThread+0x92>
+ 80005cc:	e1ec      	b.n	80009a8 <LEDS_AnimationThread+0x46c>
+ 80005ce:	009a      	lsls	r2, r3, #2
+ 80005d0:	4bc0      	ldr	r3, [pc, #768]	; (80008d4 <LEDS_AnimationThread+0x398>)
+ 80005d2:	18d3      	adds	r3, r2, r3
+ 80005d4:	681b      	ldr	r3, [r3, #0]
+ 80005d6:	469f      	mov	pc, r3
+		case leds_off:
+			LEDS_EteintVerte();
+ 80005d8:	2380      	movs	r3, #128	; 0x80
+ 80005da:	01db      	lsls	r3, r3, #7
+ 80005dc:	48bc      	ldr	r0, [pc, #752]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80005de:	2200      	movs	r2, #0
+ 80005e0:	0019      	movs	r1, r3
+ 80005e2:	f001 ff8d 	bl	8002500 <HAL_GPIO_WritePin>
+			LEDS_EteintJaune();
+ 80005e6:	2380      	movs	r3, #128	; 0x80
+ 80005e8:	019b      	lsls	r3, r3, #6
+ 80005ea:	48b9      	ldr	r0, [pc, #740]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80005ec:	2200      	movs	r2, #0
+ 80005ee:	0019      	movs	r1, r3
+ 80005f0:	f001 ff86 	bl	8002500 <HAL_GPIO_WritePin>
+			LEDS_EteintRouge();
+ 80005f4:	2380      	movs	r3, #128	; 0x80
+ 80005f6:	015b      	lsls	r3, r3, #5
+ 80005f8:	48b5      	ldr	r0, [pc, #724]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80005fa:	2200      	movs	r2, #0
+ 80005fc:	0019      	movs	r1, r3
+ 80005fe:	f001 ff7f 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000602:	e1d2      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_idle:
+			if (cnt<5)
+ 8000604:	2317      	movs	r3, #23
+ 8000606:	18fb      	adds	r3, r7, r3
+ 8000608:	781b      	ldrb	r3, [r3, #0]
+ 800060a:	2b04      	cmp	r3, #4
+ 800060c:	d807      	bhi.n	800061e <LEDS_AnimationThread+0xe2>
+				LEDS_AllumeVerte();
+ 800060e:	2380      	movs	r3, #128	; 0x80
+ 8000610:	01db      	lsls	r3, r3, #7
+ 8000612:	48af      	ldr	r0, [pc, #700]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000614:	2201      	movs	r2, #1
+ 8000616:	0019      	movs	r1, r3
+ 8000618:	f001 ff72 	bl	8002500 <HAL_GPIO_WritePin>
+			else if (cnt<10)
+				LEDS_EteintVerte();
+			else
+				cnt=0;
+			break;
+ 800061c:	e1c5      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<10)
+ 800061e:	2317      	movs	r3, #23
+ 8000620:	18fb      	adds	r3, r7, r3
+ 8000622:	781b      	ldrb	r3, [r3, #0]
+ 8000624:	2b09      	cmp	r3, #9
+ 8000626:	d807      	bhi.n	8000638 <LEDS_AnimationThread+0xfc>
+				LEDS_EteintVerte();
+ 8000628:	2380      	movs	r3, #128	; 0x80
+ 800062a:	01db      	lsls	r3, r3, #7
+ 800062c:	48a8      	ldr	r0, [pc, #672]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800062e:	2200      	movs	r2, #0
+ 8000630:	0019      	movs	r1, r3
+ 8000632:	f001 ff65 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000636:	e1b8      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				cnt=0;
+ 8000638:	2317      	movs	r3, #23
+ 800063a:	18fb      	adds	r3, r7, r3
+ 800063c:	2200      	movs	r2, #0
+ 800063e:	701a      	strb	r2, [r3, #0]
+			break;
+ 8000640:	e1b3      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_connecte:
+			LEDS_AllumeVerte();
+ 8000642:	2380      	movs	r3, #128	; 0x80
+ 8000644:	01db      	lsls	r3, r3, #7
+ 8000646:	48a2      	ldr	r0, [pc, #648]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000648:	2201      	movs	r2, #1
+ 800064a:	0019      	movs	r1, r3
+ 800064c:	f001 ff58 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000650:	e1ab      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_watchdog_expire:
+			if (cnt<5)
+ 8000652:	2317      	movs	r3, #23
+ 8000654:	18fb      	adds	r3, r7, r3
+ 8000656:	781b      	ldrb	r3, [r3, #0]
+ 8000658:	2b04      	cmp	r3, #4
+ 800065a:	d807      	bhi.n	800066c <LEDS_AnimationThread+0x130>
+				LEDS_AllumeRouge();
+ 800065c:	2380      	movs	r3, #128	; 0x80
+ 800065e:	015b      	lsls	r3, r3, #5
+ 8000660:	489b      	ldr	r0, [pc, #620]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000662:	2201      	movs	r2, #1
+ 8000664:	0019      	movs	r1, r3
+ 8000666:	f001 ff4b 	bl	8002500 <HAL_GPIO_WritePin>
+			else if (cnt<10)
+				LEDS_EteintRouge();
+			else
+				cnt=0;
+			break;
+ 800066a:	e19e      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<10)
+ 800066c:	2317      	movs	r3, #23
+ 800066e:	18fb      	adds	r3, r7, r3
+ 8000670:	781b      	ldrb	r3, [r3, #0]
+ 8000672:	2b09      	cmp	r3, #9
+ 8000674:	d807      	bhi.n	8000686 <LEDS_AnimationThread+0x14a>
+				LEDS_EteintRouge();
+ 8000676:	2380      	movs	r3, #128	; 0x80
+ 8000678:	015b      	lsls	r3, r3, #5
+ 800067a:	4895      	ldr	r0, [pc, #596]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800067c:	2200      	movs	r2, #0
+ 800067e:	0019      	movs	r1, r3
+ 8000680:	f001 ff3e 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000684:	e191      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				cnt=0;
+ 8000686:	2317      	movs	r3, #23
+ 8000688:	18fb      	adds	r3, r7, r3
+ 800068a:	2200      	movs	r2, #0
+ 800068c:	701a      	strb	r2, [r3, #0]
+			break;
+ 800068e:	e18c      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_niveau_bat_0:
+			if (!(cnt%2))
+ 8000690:	2317      	movs	r3, #23
+ 8000692:	18fb      	adds	r3, r7, r3
+ 8000694:	781b      	ldrb	r3, [r3, #0]
+ 8000696:	2201      	movs	r2, #1
+ 8000698:	4013      	ands	r3, r2
+ 800069a:	b2db      	uxtb	r3, r3
+ 800069c:	2b00      	cmp	r3, #0
+ 800069e:	d107      	bne.n	80006b0 <LEDS_AnimationThread+0x174>
+				LEDS_AllumeRouge();
+ 80006a0:	2380      	movs	r3, #128	; 0x80
+ 80006a2:	015b      	lsls	r3, r3, #5
+ 80006a4:	488a      	ldr	r0, [pc, #552]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80006a6:	2201      	movs	r2, #1
+ 80006a8:	0019      	movs	r1, r3
+ 80006aa:	f001 ff29 	bl	8002500 <HAL_GPIO_WritePin>
+			else
+				LEDS_EteintRouge();
+			break;
+ 80006ae:	e17c      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				LEDS_EteintRouge();
+ 80006b0:	2380      	movs	r3, #128	; 0x80
+ 80006b2:	015b      	lsls	r3, r3, #5
+ 80006b4:	4886      	ldr	r0, [pc, #536]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80006b6:	2200      	movs	r2, #0
+ 80006b8:	0019      	movs	r1, r3
+ 80006ba:	f001 ff21 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 80006be:	e174      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_niveau_bat_1:
+			LEDS_AllumeRouge();
+ 80006c0:	2380      	movs	r3, #128	; 0x80
+ 80006c2:	015b      	lsls	r3, r3, #5
+ 80006c4:	4882      	ldr	r0, [pc, #520]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80006c6:	2201      	movs	r2, #1
+ 80006c8:	0019      	movs	r1, r3
+ 80006ca:	f001 ff19 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 80006ce:	e16c      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_niveau_bat_2:
+			LEDS_AllumeRouge();
+ 80006d0:	2380      	movs	r3, #128	; 0x80
+ 80006d2:	015b      	lsls	r3, r3, #5
+ 80006d4:	487e      	ldr	r0, [pc, #504]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80006d6:	2201      	movs	r2, #1
+ 80006d8:	0019      	movs	r1, r3
+ 80006da:	f001 ff11 	bl	8002500 <HAL_GPIO_WritePin>
+
+			if (cnt<3)
+ 80006de:	2317      	movs	r3, #23
+ 80006e0:	18fb      	adds	r3, r7, r3
+ 80006e2:	781b      	ldrb	r3, [r3, #0]
+ 80006e4:	2b02      	cmp	r3, #2
+ 80006e6:	d807      	bhi.n	80006f8 <LEDS_AnimationThread+0x1bc>
+				LEDS_AllumeJaune();
+ 80006e8:	2380      	movs	r3, #128	; 0x80
+ 80006ea:	019b      	lsls	r3, r3, #6
+ 80006ec:	4878      	ldr	r0, [pc, #480]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80006ee:	2201      	movs	r2, #1
+ 80006f0:	0019      	movs	r1, r3
+ 80006f2:	f001 ff05 	bl	8002500 <HAL_GPIO_WritePin>
+			else if (cnt<6)
+				LEDS_EteintJaune();
+			else
+				cnt=0;
+			break;
+ 80006f6:	e158      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<6)
+ 80006f8:	2317      	movs	r3, #23
+ 80006fa:	18fb      	adds	r3, r7, r3
+ 80006fc:	781b      	ldrb	r3, [r3, #0]
+ 80006fe:	2b05      	cmp	r3, #5
+ 8000700:	d807      	bhi.n	8000712 <LEDS_AnimationThread+0x1d6>
+				LEDS_EteintJaune();
+ 8000702:	2380      	movs	r3, #128	; 0x80
+ 8000704:	019b      	lsls	r3, r3, #6
+ 8000706:	4872      	ldr	r0, [pc, #456]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000708:	2200      	movs	r2, #0
+ 800070a:	0019      	movs	r1, r3
+ 800070c:	f001 fef8 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000710:	e14b      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				cnt=0;
+ 8000712:	2317      	movs	r3, #23
+ 8000714:	18fb      	adds	r3, r7, r3
+ 8000716:	2200      	movs	r2, #0
+ 8000718:	701a      	strb	r2, [r3, #0]
+			break;
+ 800071a:	e146      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_niveau_bat_3:
+			LEDS_AllumeRouge();
+ 800071c:	2380      	movs	r3, #128	; 0x80
+ 800071e:	015b      	lsls	r3, r3, #5
+ 8000720:	486b      	ldr	r0, [pc, #428]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000722:	2201      	movs	r2, #1
+ 8000724:	0019      	movs	r1, r3
+ 8000726:	f001 feeb 	bl	8002500 <HAL_GPIO_WritePin>
+			LEDS_AllumeJaune();
+ 800072a:	2380      	movs	r3, #128	; 0x80
+ 800072c:	019b      	lsls	r3, r3, #6
+ 800072e:	4868      	ldr	r0, [pc, #416]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000730:	2201      	movs	r2, #1
+ 8000732:	0019      	movs	r1, r3
+ 8000734:	f001 fee4 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000738:	e137      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_niveau_bat_4:
+			LEDS_AllumeRouge();
+ 800073a:	2380      	movs	r3, #128	; 0x80
+ 800073c:	015b      	lsls	r3, r3, #5
+ 800073e:	4864      	ldr	r0, [pc, #400]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000740:	2201      	movs	r2, #1
+ 8000742:	0019      	movs	r1, r3
+ 8000744:	f001 fedc 	bl	8002500 <HAL_GPIO_WritePin>
+			LEDS_AllumeJaune();
+ 8000748:	2380      	movs	r3, #128	; 0x80
+ 800074a:	019b      	lsls	r3, r3, #6
+ 800074c:	4860      	ldr	r0, [pc, #384]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800074e:	2201      	movs	r2, #1
+ 8000750:	0019      	movs	r1, r3
+ 8000752:	f001 fed5 	bl	8002500 <HAL_GPIO_WritePin>
+
+			if (cnt<3)
+ 8000756:	2317      	movs	r3, #23
+ 8000758:	18fb      	adds	r3, r7, r3
+ 800075a:	781b      	ldrb	r3, [r3, #0]
+ 800075c:	2b02      	cmp	r3, #2
+ 800075e:	d807      	bhi.n	8000770 <LEDS_AnimationThread+0x234>
+				LEDS_AllumeVerte();
+ 8000760:	2380      	movs	r3, #128	; 0x80
+ 8000762:	01db      	lsls	r3, r3, #7
+ 8000764:	485a      	ldr	r0, [pc, #360]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000766:	2201      	movs	r2, #1
+ 8000768:	0019      	movs	r1, r3
+ 800076a:	f001 fec9 	bl	8002500 <HAL_GPIO_WritePin>
+			else if (cnt<6)
+				LEDS_EteintVerte();
+			else
+				cnt=0;
+			break;
+ 800076e:	e11c      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<6)
+ 8000770:	2317      	movs	r3, #23
+ 8000772:	18fb      	adds	r3, r7, r3
+ 8000774:	781b      	ldrb	r3, [r3, #0]
+ 8000776:	2b05      	cmp	r3, #5
+ 8000778:	d807      	bhi.n	800078a <LEDS_AnimationThread+0x24e>
+				LEDS_EteintVerte();
+ 800077a:	2380      	movs	r3, #128	; 0x80
+ 800077c:	01db      	lsls	r3, r3, #7
+ 800077e:	4854      	ldr	r0, [pc, #336]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000780:	2200      	movs	r2, #0
+ 8000782:	0019      	movs	r1, r3
+ 8000784:	f001 febc 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000788:	e10f      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				cnt=0;
+ 800078a:	2317      	movs	r3, #23
+ 800078c:	18fb      	adds	r3, r7, r3
+ 800078e:	2200      	movs	r2, #0
+ 8000790:	701a      	strb	r2, [r3, #0]
+			break;
+ 8000792:	e10a      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_niveau_bat_5:
+			LEDS_AllumeRouge();
+ 8000794:	2380      	movs	r3, #128	; 0x80
+ 8000796:	015b      	lsls	r3, r3, #5
+ 8000798:	484d      	ldr	r0, [pc, #308]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800079a:	2201      	movs	r2, #1
+ 800079c:	0019      	movs	r1, r3
+ 800079e:	f001 feaf 	bl	8002500 <HAL_GPIO_WritePin>
+			LEDS_AllumeJaune();
+ 80007a2:	2380      	movs	r3, #128	; 0x80
+ 80007a4:	019b      	lsls	r3, r3, #6
+ 80007a6:	484a      	ldr	r0, [pc, #296]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80007a8:	2201      	movs	r2, #1
+ 80007aa:	0019      	movs	r1, r3
+ 80007ac:	f001 fea8 	bl	8002500 <HAL_GPIO_WritePin>
+			LEDS_AllumeVerte();
+ 80007b0:	2380      	movs	r3, #128	; 0x80
+ 80007b2:	01db      	lsls	r3, r3, #7
+ 80007b4:	4846      	ldr	r0, [pc, #280]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80007b6:	2201      	movs	r2, #1
+ 80007b8:	0019      	movs	r1, r3
+ 80007ba:	f001 fea1 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 80007be:	e0f4      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_charge_bat_0:
+		case leds_charge_bat_1:
+			if (cnt<3)
+ 80007c0:	2317      	movs	r3, #23
+ 80007c2:	18fb      	adds	r3, r7, r3
+ 80007c4:	781b      	ldrb	r3, [r3, #0]
+ 80007c6:	2b02      	cmp	r3, #2
+ 80007c8:	d807      	bhi.n	80007da <LEDS_AnimationThread+0x29e>
+				LEDS_AllumeRouge();
+ 80007ca:	2380      	movs	r3, #128	; 0x80
+ 80007cc:	015b      	lsls	r3, r3, #5
+ 80007ce:	4840      	ldr	r0, [pc, #256]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80007d0:	2201      	movs	r2, #1
+ 80007d2:	0019      	movs	r1, r3
+ 80007d4:	f001 fe94 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintVerte();
+				LEDS_EteintJaune();
+				LEDS_EteintRouge();
+			} else
+				cnt=0;
+			break;
+ 80007d8:	e0e7      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<6)
+ 80007da:	2317      	movs	r3, #23
+ 80007dc:	18fb      	adds	r3, r7, r3
+ 80007de:	781b      	ldrb	r3, [r3, #0]
+ 80007e0:	2b05      	cmp	r3, #5
+ 80007e2:	d807      	bhi.n	80007f4 <LEDS_AnimationThread+0x2b8>
+				LEDS_AllumeJaune();
+ 80007e4:	2380      	movs	r3, #128	; 0x80
+ 80007e6:	019b      	lsls	r3, r3, #6
+ 80007e8:	4839      	ldr	r0, [pc, #228]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80007ea:	2201      	movs	r2, #1
+ 80007ec:	0019      	movs	r1, r3
+ 80007ee:	f001 fe87 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 80007f2:	e0da      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<9)
+ 80007f4:	2317      	movs	r3, #23
+ 80007f6:	18fb      	adds	r3, r7, r3
+ 80007f8:	781b      	ldrb	r3, [r3, #0]
+ 80007fa:	2b08      	cmp	r3, #8
+ 80007fc:	d807      	bhi.n	800080e <LEDS_AnimationThread+0x2d2>
+				LEDS_AllumeVerte();
+ 80007fe:	2380      	movs	r3, #128	; 0x80
+ 8000800:	01db      	lsls	r3, r3, #7
+ 8000802:	4833      	ldr	r0, [pc, #204]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000804:	2201      	movs	r2, #1
+ 8000806:	0019      	movs	r1, r3
+ 8000808:	f001 fe7a 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 800080c:	e0cd      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<12){
+ 800080e:	2317      	movs	r3, #23
+ 8000810:	18fb      	adds	r3, r7, r3
+ 8000812:	781b      	ldrb	r3, [r3, #0]
+ 8000814:	2b0b      	cmp	r3, #11
+ 8000816:	d815      	bhi.n	8000844 <LEDS_AnimationThread+0x308>
+				LEDS_EteintVerte();
+ 8000818:	2380      	movs	r3, #128	; 0x80
+ 800081a:	01db      	lsls	r3, r3, #7
+ 800081c:	482c      	ldr	r0, [pc, #176]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800081e:	2200      	movs	r2, #0
+ 8000820:	0019      	movs	r1, r3
+ 8000822:	f001 fe6d 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintJaune();
+ 8000826:	2380      	movs	r3, #128	; 0x80
+ 8000828:	019b      	lsls	r3, r3, #6
+ 800082a:	4829      	ldr	r0, [pc, #164]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800082c:	2200      	movs	r2, #0
+ 800082e:	0019      	movs	r1, r3
+ 8000830:	f001 fe66 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintRouge();
+ 8000834:	2380      	movs	r3, #128	; 0x80
+ 8000836:	015b      	lsls	r3, r3, #5
+ 8000838:	4825      	ldr	r0, [pc, #148]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800083a:	2200      	movs	r2, #0
+ 800083c:	0019      	movs	r1, r3
+ 800083e:	f001 fe5f 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000842:	e0b2      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				cnt=0;
+ 8000844:	2317      	movs	r3, #23
+ 8000846:	18fb      	adds	r3, r7, r3
+ 8000848:	2200      	movs	r2, #0
+ 800084a:	701a      	strb	r2, [r3, #0]
+			break;
+ 800084c:	e0ad      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_charge_bat_2:
+		case leds_charge_bat_3:
+			LEDS_AllumeRouge();
+ 800084e:	2380      	movs	r3, #128	; 0x80
+ 8000850:	015b      	lsls	r3, r3, #5
+ 8000852:	481f      	ldr	r0, [pc, #124]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000854:	2201      	movs	r2, #1
+ 8000856:	0019      	movs	r1, r3
+ 8000858:	f001 fe52 	bl	8002500 <HAL_GPIO_WritePin>
+			if (cnt<3)
+ 800085c:	2317      	movs	r3, #23
+ 800085e:	18fb      	adds	r3, r7, r3
+ 8000860:	781b      	ldrb	r3, [r3, #0]
+ 8000862:	2b02      	cmp	r3, #2
+ 8000864:	d807      	bhi.n	8000876 <LEDS_AnimationThread+0x33a>
+				LEDS_AllumeJaune();
+ 8000866:	2380      	movs	r3, #128	; 0x80
+ 8000868:	019b      	lsls	r3, r3, #6
+ 800086a:	4819      	ldr	r0, [pc, #100]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 800086c:	2201      	movs	r2, #1
+ 800086e:	0019      	movs	r1, r3
+ 8000870:	f001 fe46 	bl	8002500 <HAL_GPIO_WritePin>
+			else if (cnt <9){
+				LEDS_EteintVerte();
+				LEDS_EteintJaune();
+			} else
+				cnt=0;
+			break;
+ 8000874:	e099      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<6)
+ 8000876:	2317      	movs	r3, #23
+ 8000878:	18fb      	adds	r3, r7, r3
+ 800087a:	781b      	ldrb	r3, [r3, #0]
+ 800087c:	2b05      	cmp	r3, #5
+ 800087e:	d807      	bhi.n	8000890 <LEDS_AnimationThread+0x354>
+				LEDS_AllumeVerte();
+ 8000880:	2380      	movs	r3, #128	; 0x80
+ 8000882:	01db      	lsls	r3, r3, #7
+ 8000884:	4812      	ldr	r0, [pc, #72]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 8000886:	2201      	movs	r2, #1
+ 8000888:	0019      	movs	r1, r3
+ 800088a:	f001 fe39 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 800088e:	e08c      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt <9){
+ 8000890:	2317      	movs	r3, #23
+ 8000892:	18fb      	adds	r3, r7, r3
+ 8000894:	781b      	ldrb	r3, [r3, #0]
+ 8000896:	2b08      	cmp	r3, #8
+ 8000898:	d80e      	bhi.n	80008b8 <LEDS_AnimationThread+0x37c>
+				LEDS_EteintVerte();
+ 800089a:	2380      	movs	r3, #128	; 0x80
+ 800089c:	01db      	lsls	r3, r3, #7
+ 800089e:	480c      	ldr	r0, [pc, #48]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80008a0:	2200      	movs	r2, #0
+ 80008a2:	0019      	movs	r1, r3
+ 80008a4:	f001 fe2c 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintJaune();
+ 80008a8:	2380      	movs	r3, #128	; 0x80
+ 80008aa:	019b      	lsls	r3, r3, #6
+ 80008ac:	4808      	ldr	r0, [pc, #32]	; (80008d0 <LEDS_AnimationThread+0x394>)
+ 80008ae:	2200      	movs	r2, #0
+ 80008b0:	0019      	movs	r1, r3
+ 80008b2:	f001 fe25 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 80008b6:	e078      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				cnt=0;
+ 80008b8:	2317      	movs	r3, #23
+ 80008ba:	18fb      	adds	r3, r7, r3
+ 80008bc:	2200      	movs	r2, #0
+ 80008be:	701a      	strb	r2, [r3, #0]
+			break;
+ 80008c0:	e073      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+ 80008c2:	46c0      	nop			; (mov r8, r8)
+ 80008c4:	20001964 	.word	0x20001964
+ 80008c8:	2000153c 	.word	0x2000153c
+ 80008cc:	200016d0 	.word	0x200016d0
+ 80008d0:	50000400 	.word	0x50000400
+ 80008d4:	0800781c 	.word	0x0800781c
+		case leds_charge_bat_4:
+		case leds_charge_bat_5:
+			LEDS_AllumeRouge();
+ 80008d8:	2380      	movs	r3, #128	; 0x80
+ 80008da:	015b      	lsls	r3, r3, #5
+ 80008dc:	4833      	ldr	r0, [pc, #204]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 80008de:	2201      	movs	r2, #1
+ 80008e0:	0019      	movs	r1, r3
+ 80008e2:	f001 fe0d 	bl	8002500 <HAL_GPIO_WritePin>
+			LEDS_AllumeJaune();
+ 80008e6:	2380      	movs	r3, #128	; 0x80
+ 80008e8:	019b      	lsls	r3, r3, #6
+ 80008ea:	4830      	ldr	r0, [pc, #192]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 80008ec:	2201      	movs	r2, #1
+ 80008ee:	0019      	movs	r1, r3
+ 80008f0:	f001 fe06 	bl	8002500 <HAL_GPIO_WritePin>
+
+			if (cnt<3)
+ 80008f4:	2317      	movs	r3, #23
+ 80008f6:	18fb      	adds	r3, r7, r3
+ 80008f8:	781b      	ldrb	r3, [r3, #0]
+ 80008fa:	2b02      	cmp	r3, #2
+ 80008fc:	d807      	bhi.n	800090e <LEDS_AnimationThread+0x3d2>
+				LEDS_AllumeVerte();
+ 80008fe:	2380      	movs	r3, #128	; 0x80
+ 8000900:	01db      	lsls	r3, r3, #7
+ 8000902:	482a      	ldr	r0, [pc, #168]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 8000904:	2201      	movs	r2, #1
+ 8000906:	0019      	movs	r1, r3
+ 8000908:	f001 fdfa 	bl	8002500 <HAL_GPIO_WritePin>
+			else if (cnt<6)
+				LEDS_EteintVerte();
+			else
+				cnt=0;
+			break;
+ 800090c:	e04d      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<6)
+ 800090e:	2317      	movs	r3, #23
+ 8000910:	18fb      	adds	r3, r7, r3
+ 8000912:	781b      	ldrb	r3, [r3, #0]
+ 8000914:	2b05      	cmp	r3, #5
+ 8000916:	d807      	bhi.n	8000928 <LEDS_AnimationThread+0x3ec>
+				LEDS_EteintVerte();
+ 8000918:	2380      	movs	r3, #128	; 0x80
+ 800091a:	01db      	lsls	r3, r3, #7
+ 800091c:	4823      	ldr	r0, [pc, #140]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 800091e:	2200      	movs	r2, #0
+ 8000920:	0019      	movs	r1, r3
+ 8000922:	f001 fded 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 8000926:	e040      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				cnt=0;
+ 8000928:	2317      	movs	r3, #23
+ 800092a:	18fb      	adds	r3, r7, r3
+ 800092c:	2200      	movs	r2, #0
+ 800092e:	701a      	strb	r2, [r3, #0]
+			break;
+ 8000930:	e03b      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		case leds_erreur:
+			if (cnt<5) {
+ 8000932:	2317      	movs	r3, #23
+ 8000934:	18fb      	adds	r3, r7, r3
+ 8000936:	781b      	ldrb	r3, [r3, #0]
+ 8000938:	2b04      	cmp	r3, #4
+ 800093a:	d815      	bhi.n	8000968 <LEDS_AnimationThread+0x42c>
+				LEDS_AllumeRouge();
+ 800093c:	2380      	movs	r3, #128	; 0x80
+ 800093e:	015b      	lsls	r3, r3, #5
+ 8000940:	481a      	ldr	r0, [pc, #104]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 8000942:	2201      	movs	r2, #1
+ 8000944:	0019      	movs	r1, r3
+ 8000946:	f001 fddb 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_AllumeJaune();
+ 800094a:	2380      	movs	r3, #128	; 0x80
+ 800094c:	019b      	lsls	r3, r3, #6
+ 800094e:	4817      	ldr	r0, [pc, #92]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 8000950:	2201      	movs	r2, #1
+ 8000952:	0019      	movs	r1, r3
+ 8000954:	f001 fdd4 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_AllumeVerte();
+ 8000958:	2380      	movs	r3, #128	; 0x80
+ 800095a:	01db      	lsls	r3, r3, #7
+ 800095c:	4813      	ldr	r0, [pc, #76]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 800095e:	2201      	movs	r2, #1
+ 8000960:	0019      	movs	r1, r3
+ 8000962:	f001 fdcd 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintJaune();
+				LEDS_EteintVerte();
+			}
+			else
+				cnt=0;
+			break;
+ 8000966:	e020      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+			else if (cnt<10) {
+ 8000968:	2317      	movs	r3, #23
+ 800096a:	18fb      	adds	r3, r7, r3
+ 800096c:	781b      	ldrb	r3, [r3, #0]
+ 800096e:	2b09      	cmp	r3, #9
+ 8000970:	d815      	bhi.n	800099e <LEDS_AnimationThread+0x462>
+				LEDS_EteintRouge();
+ 8000972:	2380      	movs	r3, #128	; 0x80
+ 8000974:	015b      	lsls	r3, r3, #5
+ 8000976:	480d      	ldr	r0, [pc, #52]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 8000978:	2200      	movs	r2, #0
+ 800097a:	0019      	movs	r1, r3
+ 800097c:	f001 fdc0 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintJaune();
+ 8000980:	2380      	movs	r3, #128	; 0x80
+ 8000982:	019b      	lsls	r3, r3, #6
+ 8000984:	4809      	ldr	r0, [pc, #36]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 8000986:	2200      	movs	r2, #0
+ 8000988:	0019      	movs	r1, r3
+ 800098a:	f001 fdb9 	bl	8002500 <HAL_GPIO_WritePin>
+				LEDS_EteintVerte();
+ 800098e:	2380      	movs	r3, #128	; 0x80
+ 8000990:	01db      	lsls	r3, r3, #7
+ 8000992:	4806      	ldr	r0, [pc, #24]	; (80009ac <LEDS_AnimationThread+0x470>)
+ 8000994:	2200      	movs	r2, #0
+ 8000996:	0019      	movs	r1, r3
+ 8000998:	f001 fdb2 	bl	8002500 <HAL_GPIO_WritePin>
+			break;
+ 800099c:	e005      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+				cnt=0;
+ 800099e:	2317      	movs	r3, #23
+ 80009a0:	18fb      	adds	r3, r7, r3
+ 80009a2:	2200      	movs	r2, #0
+ 80009a4:	701a      	strb	r2, [r3, #0]
+			break;
+ 80009a6:	e000      	b.n	80009aa <LEDS_AnimationThread+0x46e>
+		default:
+			break;
+ 80009a8:	46c0      	nop			; (mov r8, r8)
+		vTaskDelay(pdMS_TO_TICKS(100));
+ 80009aa:	e5cf      	b.n	800054c <LEDS_AnimationThread+0x10>
+ 80009ac:	50000400 	.word	0x50000400
+
+080009b0 <main>:
+/**
+ * @brief  The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ 80009b0:	b580      	push	{r7, lr}
+ 80009b2:	af00      	add	r7, sp, #0
+	/* USER CODE END 1 */
+
+	/* MCU Configuration--------------------------------------------------------*/
+
+	/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+	HAL_Init();
+ 80009b4:	f000 fe8a 	bl	80016cc <HAL_Init>
+	/* USER CODE BEGIN Init */
+
+	/* USER CODE END Init */
+
+	/* Configure the system clock */
+	SystemClock_Config();
+ 80009b8:	f000 f826 	bl	8000a08 <SystemClock_Config>
+	/* USER CODE BEGIN SysInit */
+
+	/* USER CODE END SysInit */
+
+	/* Initialize all configured peripherals */
+	MX_GPIO_Init();
+ 80009bc:	f000 fa78 	bl	8000eb0 <MX_GPIO_Init>
+	MX_DMA_Init();
+ 80009c0:	f000 fa58 	bl	8000e74 <MX_DMA_Init>
+	MX_LPTIM1_Init();
+ 80009c4:	f000 f8f8 	bl	8000bb8 <MX_LPTIM1_Init>
+	MX_LPUART1_UART_Init();
+ 80009c8:	f000 f926 	bl	8000c18 <MX_LPUART1_UART_Init>
+	MX_TIM2_Init();
+ 80009cc:	f000 f952 	bl	8000c74 <MX_TIM2_Init>
+	MX_TIM21_Init();
+ 80009d0:	f000 f9ec 	bl	8000dac <MX_TIM21_Init>
+	MX_ADC_Init();
+ 80009d4:	f000 f88c 	bl	8000af0 <MX_ADC_Init>
+	/* USER CODE BEGIN 2 */
+	/* Init des messages box */
+	MESSAGE_Init();
+ 80009d8:	f000 fb32 	bl	8001040 <MESSAGE_Init>
+
+	LEDS_Init();
+ 80009dc:	f7ff fd6e 	bl	80004bc <LEDS_Init>
+	/*MOTEURS_Init();
+  MOTEURS_Test();*/
+	/* USER CODE END 2 */
+
+	/* Init scheduler */
+	osKernelInitialize();
+ 80009e0:	f004 fa3c 	bl	8004e5c <osKernelInitialize>
+	/* add queues, ... */
+	/* USER CODE END RTOS_QUEUES */
+
+	/* Create the thread(s) */
+	/* creation of defaultTask */
+	defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
+ 80009e4:	4a05      	ldr	r2, [pc, #20]	; (80009fc <main+0x4c>)
+ 80009e6:	4b06      	ldr	r3, [pc, #24]	; (8000a00 <main+0x50>)
+ 80009e8:	2100      	movs	r1, #0
+ 80009ea:	0018      	movs	r0, r3
+ 80009ec:	f004 fa92 	bl	8004f14 <osThreadNew>
+ 80009f0:	0002      	movs	r2, r0
+ 80009f2:	4b04      	ldr	r3, [pc, #16]	; (8000a04 <main+0x54>)
+ 80009f4:	601a      	str	r2, [r3, #0]
+	/* USER CODE BEGIN RTOS_EVENTS */
+	/* add events, ... */
+	/* USER CODE END RTOS_EVENTS */
+
+	/* Start scheduler */
+	osKernelStart();
+ 80009f6:	f004 fa5d 	bl	8004eb4 <osKernelStart>
+
+	/* We should never get here as control is now taken by the scheduler */
+	/* Infinite loop */
+	/* USER CODE BEGIN WHILE */
+	while (1)
+ 80009fa:	e7fe      	b.n	80009fa <main+0x4a>
+ 80009fc:	08007860 	.word	0x08007860
+ 8000a00:	08000fe1 	.word	0x08000fe1
+ 8000a04:	20001730 	.word	0x20001730
+
+08000a08 <SystemClock_Config>:
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ 8000a08:	b590      	push	{r4, r7, lr}
+ 8000a0a:	b099      	sub	sp, #100	; 0x64
+ 8000a0c:	af00      	add	r7, sp, #0
+	RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 8000a0e:	242c      	movs	r4, #44	; 0x2c
+ 8000a10:	193b      	adds	r3, r7, r4
+ 8000a12:	0018      	movs	r0, r3
+ 8000a14:	2334      	movs	r3, #52	; 0x34
+ 8000a16:	001a      	movs	r2, r3
+ 8000a18:	2100      	movs	r1, #0
+ 8000a1a:	f006 fed0 	bl	80077be <memset>
+	RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 8000a1e:	2318      	movs	r3, #24
+ 8000a20:	18fb      	adds	r3, r7, r3
+ 8000a22:	0018      	movs	r0, r3
+ 8000a24:	2314      	movs	r3, #20
+ 8000a26:	001a      	movs	r2, r3
+ 8000a28:	2100      	movs	r1, #0
+ 8000a2a:	f006 fec8 	bl	80077be <memset>
+	RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ 8000a2e:	003b      	movs	r3, r7
+ 8000a30:	0018      	movs	r0, r3
+ 8000a32:	2318      	movs	r3, #24
+ 8000a34:	001a      	movs	r2, r3
+ 8000a36:	2100      	movs	r1, #0
+ 8000a38:	f006 fec1 	bl	80077be <memset>
+
+	/** Configure the main internal regulator output voltage
+	 */
+	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 8000a3c:	4b2a      	ldr	r3, [pc, #168]	; (8000ae8 <SystemClock_Config+0xe0>)
+ 8000a3e:	681b      	ldr	r3, [r3, #0]
+ 8000a40:	4a2a      	ldr	r2, [pc, #168]	; (8000aec <SystemClock_Config+0xe4>)
+ 8000a42:	401a      	ands	r2, r3
+ 8000a44:	4b28      	ldr	r3, [pc, #160]	; (8000ae8 <SystemClock_Config+0xe0>)
+ 8000a46:	2180      	movs	r1, #128	; 0x80
+ 8000a48:	0109      	lsls	r1, r1, #4
+ 8000a4a:	430a      	orrs	r2, r1
+ 8000a4c:	601a      	str	r2, [r3, #0]
+	/** Initializes the RCC Oscillators according to the specified parameters
+	 * in the RCC_OscInitTypeDef structure.
+	 */
+	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ 8000a4e:	0021      	movs	r1, r4
+ 8000a50:	187b      	adds	r3, r7, r1
+ 8000a52:	2202      	movs	r2, #2
+ 8000a54:	601a      	str	r2, [r3, #0]
+	RCC_OscInitStruct.HSIState = RCC_HSI_DIV4;
+ 8000a56:	187b      	adds	r3, r7, r1
+ 8000a58:	2209      	movs	r2, #9
+ 8000a5a:	60da      	str	r2, [r3, #12]
+	RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ 8000a5c:	187b      	adds	r3, r7, r1
+ 8000a5e:	2210      	movs	r2, #16
+ 8000a60:	611a      	str	r2, [r3, #16]
+	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 8000a62:	187b      	adds	r3, r7, r1
+ 8000a64:	2202      	movs	r2, #2
+ 8000a66:	625a      	str	r2, [r3, #36]	; 0x24
+	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ 8000a68:	187b      	adds	r3, r7, r1
+ 8000a6a:	2200      	movs	r2, #0
+ 8000a6c:	629a      	str	r2, [r3, #40]	; 0x28
+	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_3;
+ 8000a6e:	187b      	adds	r3, r7, r1
+ 8000a70:	2200      	movs	r2, #0
+ 8000a72:	62da      	str	r2, [r3, #44]	; 0x2c
+	RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ 8000a74:	187b      	adds	r3, r7, r1
+ 8000a76:	2280      	movs	r2, #128	; 0x80
+ 8000a78:	03d2      	lsls	r2, r2, #15
+ 8000a7a:	631a      	str	r2, [r3, #48]	; 0x30
+	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 8000a7c:	187b      	adds	r3, r7, r1
+ 8000a7e:	0018      	movs	r0, r3
+ 8000a80:	f001 fe0e 	bl	80026a0 <HAL_RCC_OscConfig>
+ 8000a84:	1e03      	subs	r3, r0, #0
+ 8000a86:	d001      	beq.n	8000a8c <SystemClock_Config+0x84>
+	{
+		Error_Handler();
+ 8000a88:	f000 fad4 	bl	8001034 <Error_Handler>
+	}
+	/** Initializes the CPU, AHB and APB buses clocks
+	 */
+	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 8000a8c:	2118      	movs	r1, #24
+ 8000a8e:	187b      	adds	r3, r7, r1
+ 8000a90:	220f      	movs	r2, #15
+ 8000a92:	601a      	str	r2, [r3, #0]
+			|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ 8000a94:	187b      	adds	r3, r7, r1
+ 8000a96:	2203      	movs	r2, #3
+ 8000a98:	605a      	str	r2, [r3, #4]
+	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 8000a9a:	187b      	adds	r3, r7, r1
+ 8000a9c:	2200      	movs	r2, #0
+ 8000a9e:	609a      	str	r2, [r3, #8]
+	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ 8000aa0:	187b      	adds	r3, r7, r1
+ 8000aa2:	2200      	movs	r2, #0
+ 8000aa4:	60da      	str	r2, [r3, #12]
+	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 8000aa6:	187b      	adds	r3, r7, r1
+ 8000aa8:	2200      	movs	r2, #0
+ 8000aaa:	611a      	str	r2, [r3, #16]
+
+	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ 8000aac:	187b      	adds	r3, r7, r1
+ 8000aae:	2100      	movs	r1, #0
+ 8000ab0:	0018      	movs	r0, r3
+ 8000ab2:	f002 f971 	bl	8002d98 <HAL_RCC_ClockConfig>
+ 8000ab6:	1e03      	subs	r3, r0, #0
+ 8000ab8:	d001      	beq.n	8000abe <SystemClock_Config+0xb6>
+	{
+		Error_Handler();
+ 8000aba:	f000 fabb 	bl	8001034 <Error_Handler>
+	}
+	PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_LPTIM1;
+ 8000abe:	003b      	movs	r3, r7
+ 8000ac0:	2284      	movs	r2, #132	; 0x84
+ 8000ac2:	601a      	str	r2, [r3, #0]
+	PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+ 8000ac4:	003b      	movs	r3, r7
+ 8000ac6:	2200      	movs	r2, #0
+ 8000ac8:	60da      	str	r2, [r3, #12]
+	PeriphClkInit.LptimClockSelection = RCC_LPTIM1CLKSOURCE_PCLK;
+ 8000aca:	003b      	movs	r3, r7
+ 8000acc:	2200      	movs	r2, #0
+ 8000ace:	615a      	str	r2, [r3, #20]
+
+	if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 8000ad0:	003b      	movs	r3, r7
+ 8000ad2:	0018      	movs	r0, r3
+ 8000ad4:	f002 fb84 	bl	80031e0 <HAL_RCCEx_PeriphCLKConfig>
+ 8000ad8:	1e03      	subs	r3, r0, #0
+ 8000ada:	d001      	beq.n	8000ae0 <SystemClock_Config+0xd8>
+	{
+		Error_Handler();
+ 8000adc:	f000 faaa 	bl	8001034 <Error_Handler>
+	}
+}
+ 8000ae0:	46c0      	nop			; (mov r8, r8)
+ 8000ae2:	46bd      	mov	sp, r7
+ 8000ae4:	b019      	add	sp, #100	; 0x64
+ 8000ae6:	bd90      	pop	{r4, r7, pc}
+ 8000ae8:	40007000 	.word	0x40007000
+ 8000aec:	ffffe7ff 	.word	0xffffe7ff
+
+08000af0 <MX_ADC_Init>:
+ * @brief ADC Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_ADC_Init(void)
+{
+ 8000af0:	b580      	push	{r7, lr}
+ 8000af2:	b082      	sub	sp, #8
+ 8000af4:	af00      	add	r7, sp, #0
+
+	/* USER CODE BEGIN ADC_Init 0 */
+
+	/* USER CODE END ADC_Init 0 */
+
+	ADC_ChannelConfTypeDef sConfig = {0};
+ 8000af6:	003b      	movs	r3, r7
+ 8000af8:	0018      	movs	r0, r3
+ 8000afa:	2308      	movs	r3, #8
+ 8000afc:	001a      	movs	r2, r3
+ 8000afe:	2100      	movs	r1, #0
+ 8000b00:	f006 fe5d 	bl	80077be <memset>
+	/* USER CODE BEGIN ADC_Init 1 */
+
+	/* USER CODE END ADC_Init 1 */
+	/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
+	 */
+	hadc.Instance = ADC1;
+ 8000b04:	4b2a      	ldr	r3, [pc, #168]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b06:	4a2b      	ldr	r2, [pc, #172]	; (8000bb4 <MX_ADC_Init+0xc4>)
+ 8000b08:	601a      	str	r2, [r3, #0]
+	hadc.Init.OversamplingMode = DISABLE;
+ 8000b0a:	4b29      	ldr	r3, [pc, #164]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b0c:	2200      	movs	r2, #0
+ 8000b0e:	63da      	str	r2, [r3, #60]	; 0x3c
+	hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1;
+ 8000b10:	4b27      	ldr	r3, [pc, #156]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b12:	22c0      	movs	r2, #192	; 0xc0
+ 8000b14:	0612      	lsls	r2, r2, #24
+ 8000b16:	605a      	str	r2, [r3, #4]
+	hadc.Init.Resolution = ADC_RESOLUTION_8B;
+ 8000b18:	4b25      	ldr	r3, [pc, #148]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b1a:	2210      	movs	r2, #16
+ 8000b1c:	609a      	str	r2, [r3, #8]
+	hadc.Init.SamplingTime = ADC_SAMPLETIME_160CYCLES_5;
+ 8000b1e:	4b24      	ldr	r3, [pc, #144]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b20:	2207      	movs	r2, #7
+ 8000b22:	639a      	str	r2, [r3, #56]	; 0x38
+	hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
+ 8000b24:	4b22      	ldr	r3, [pc, #136]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b26:	2201      	movs	r2, #1
+ 8000b28:	611a      	str	r2, [r3, #16]
+	hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 8000b2a:	4b21      	ldr	r3, [pc, #132]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b2c:	2200      	movs	r2, #0
+ 8000b2e:	60da      	str	r2, [r3, #12]
+	hadc.Init.ContinuousConvMode = DISABLE;
+ 8000b30:	4b1f      	ldr	r3, [pc, #124]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b32:	2220      	movs	r2, #32
+ 8000b34:	2100      	movs	r1, #0
+ 8000b36:	5499      	strb	r1, [r3, r2]
+	hadc.Init.DiscontinuousConvMode = DISABLE;
+ 8000b38:	4b1d      	ldr	r3, [pc, #116]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b3a:	2221      	movs	r2, #33	; 0x21
+ 8000b3c:	2100      	movs	r1, #0
+ 8000b3e:	5499      	strb	r1, [r3, r2]
+	hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 8000b40:	4b1b      	ldr	r3, [pc, #108]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b42:	2200      	movs	r2, #0
+ 8000b44:	629a      	str	r2, [r3, #40]	; 0x28
+	hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 8000b46:	4b1a      	ldr	r3, [pc, #104]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b48:	22c2      	movs	r2, #194	; 0xc2
+ 8000b4a:	32ff      	adds	r2, #255	; 0xff
+ 8000b4c:	625a      	str	r2, [r3, #36]	; 0x24
+	hadc.Init.DMAContinuousRequests = DISABLE;
+ 8000b4e:	4b18      	ldr	r3, [pc, #96]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b50:	222c      	movs	r2, #44	; 0x2c
+ 8000b52:	2100      	movs	r1, #0
+ 8000b54:	5499      	strb	r1, [r3, r2]
+	hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 8000b56:	4b16      	ldr	r3, [pc, #88]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b58:	2204      	movs	r2, #4
+ 8000b5a:	615a      	str	r2, [r3, #20]
+	hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 8000b5c:	4b14      	ldr	r3, [pc, #80]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b5e:	2200      	movs	r2, #0
+ 8000b60:	631a      	str	r2, [r3, #48]	; 0x30
+	hadc.Init.LowPowerAutoWait = DISABLE;
+ 8000b62:	4b13      	ldr	r3, [pc, #76]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b64:	2200      	movs	r2, #0
+ 8000b66:	619a      	str	r2, [r3, #24]
+	hadc.Init.LowPowerFrequencyMode = DISABLE;
+ 8000b68:	4b11      	ldr	r3, [pc, #68]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b6a:	2200      	movs	r2, #0
+ 8000b6c:	635a      	str	r2, [r3, #52]	; 0x34
+	hadc.Init.LowPowerAutoPowerOff = DISABLE;
+ 8000b6e:	4b10      	ldr	r3, [pc, #64]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b70:	2200      	movs	r2, #0
+ 8000b72:	61da      	str	r2, [r3, #28]
+	if (HAL_ADC_Init(&hadc) != HAL_OK)
+ 8000b74:	4b0e      	ldr	r3, [pc, #56]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b76:	0018      	movs	r0, r3
+ 8000b78:	f000 fe18 	bl	80017ac <HAL_ADC_Init>
+ 8000b7c:	1e03      	subs	r3, r0, #0
+ 8000b7e:	d001      	beq.n	8000b84 <MX_ADC_Init+0x94>
+	{
+		Error_Handler();
+ 8000b80:	f000 fa58 	bl	8001034 <Error_Handler>
+	}
+	/** Configure for the selected ADC regular channel to be converted.
+	 */
+	sConfig.Channel = ADC_CHANNEL_0;
+ 8000b84:	003b      	movs	r3, r7
+ 8000b86:	2201      	movs	r2, #1
+ 8000b88:	601a      	str	r2, [r3, #0]
+	sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+ 8000b8a:	003b      	movs	r3, r7
+ 8000b8c:	2280      	movs	r2, #128	; 0x80
+ 8000b8e:	0152      	lsls	r2, r2, #5
+ 8000b90:	605a      	str	r2, [r3, #4]
+	if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
+ 8000b92:	003a      	movs	r2, r7
+ 8000b94:	4b06      	ldr	r3, [pc, #24]	; (8000bb0 <MX_ADC_Init+0xc0>)
+ 8000b96:	0011      	movs	r1, r2
+ 8000b98:	0018      	movs	r0, r3
+ 8000b9a:	f001 f84f 	bl	8001c3c <HAL_ADC_ConfigChannel>
+ 8000b9e:	1e03      	subs	r3, r0, #0
+ 8000ba0:	d001      	beq.n	8000ba6 <MX_ADC_Init+0xb6>
+	{
+		Error_Handler();
+ 8000ba2:	f000 fa47 	bl	8001034 <Error_Handler>
+	}
+	/* USER CODE BEGIN ADC_Init 2 */
+
+	/* USER CODE END ADC_Init 2 */
+
+}
+ 8000ba6:	46c0      	nop			; (mov r8, r8)
+ 8000ba8:	46bd      	mov	sp, r7
+ 8000baa:	b002      	add	sp, #8
+ 8000bac:	bd80      	pop	{r7, pc}
+ 8000bae:	46c0      	nop			; (mov r8, r8)
+ 8000bb0:	200018b8 	.word	0x200018b8
+ 8000bb4:	40012400 	.word	0x40012400
+
+08000bb8 <MX_LPTIM1_Init>:
+ * @brief LPTIM1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_LPTIM1_Init(void)
+{
+ 8000bb8:	b580      	push	{r7, lr}
+ 8000bba:	af00      	add	r7, sp, #0
+	/* USER CODE END LPTIM1_Init 0 */
+
+	/* USER CODE BEGIN LPTIM1_Init 1 */
+
+	/* USER CODE END LPTIM1_Init 1 */
+	hlptim1.Instance = LPTIM1;
+ 8000bbc:	4b13      	ldr	r3, [pc, #76]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000bbe:	4a14      	ldr	r2, [pc, #80]	; (8000c10 <MX_LPTIM1_Init+0x58>)
+ 8000bc0:	601a      	str	r2, [r3, #0]
+	hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
+ 8000bc2:	4b12      	ldr	r3, [pc, #72]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000bc4:	2200      	movs	r2, #0
+ 8000bc6:	605a      	str	r2, [r3, #4]
+	hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
+ 8000bc8:	4b10      	ldr	r3, [pc, #64]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000bca:	2200      	movs	r2, #0
+ 8000bcc:	609a      	str	r2, [r3, #8]
+	hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING;
+ 8000bce:	4b0f      	ldr	r3, [pc, #60]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000bd0:	2200      	movs	r2, #0
+ 8000bd2:	60da      	str	r2, [r3, #12]
+	hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION;
+ 8000bd4:	4b0d      	ldr	r3, [pc, #52]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000bd6:	2200      	movs	r2, #0
+ 8000bd8:	611a      	str	r2, [r3, #16]
+	hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
+ 8000bda:	4b0c      	ldr	r3, [pc, #48]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000bdc:	4a0d      	ldr	r2, [pc, #52]	; (8000c14 <MX_LPTIM1_Init+0x5c>)
+ 8000bde:	615a      	str	r2, [r3, #20]
+	hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
+ 8000be0:	4b0a      	ldr	r3, [pc, #40]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000be2:	2200      	movs	r2, #0
+ 8000be4:	621a      	str	r2, [r3, #32]
+	hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
+ 8000be6:	4b09      	ldr	r3, [pc, #36]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000be8:	2200      	movs	r2, #0
+ 8000bea:	625a      	str	r2, [r3, #36]	; 0x24
+	hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL;
+ 8000bec:	4b07      	ldr	r3, [pc, #28]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000bee:	2280      	movs	r2, #128	; 0x80
+ 8000bf0:	0412      	lsls	r2, r2, #16
+ 8000bf2:	629a      	str	r2, [r3, #40]	; 0x28
+	if (HAL_LPTIM_Init(&hlptim1) != HAL_OK)
+ 8000bf4:	4b05      	ldr	r3, [pc, #20]	; (8000c0c <MX_LPTIM1_Init+0x54>)
+ 8000bf6:	0018      	movs	r0, r3
+ 8000bf8:	f001 fcc6 	bl	8002588 <HAL_LPTIM_Init>
+ 8000bfc:	1e03      	subs	r3, r0, #0
+ 8000bfe:	d001      	beq.n	8000c04 <MX_LPTIM1_Init+0x4c>
+	{
+		Error_Handler();
+ 8000c00:	f000 fa18 	bl	8001034 <Error_Handler>
+	}
+	/* USER CODE BEGIN LPTIM1_Init 2 */
+
+	/* USER CODE END LPTIM1_Init 2 */
+
+}
+ 8000c04:	46c0      	nop			; (mov r8, r8)
+ 8000c06:	46bd      	mov	sp, r7
+ 8000c08:	bd80      	pop	{r7, pc}
+ 8000c0a:	46c0      	nop			; (mov r8, r8)
+ 8000c0c:	200017b8 	.word	0x200017b8
+ 8000c10:	40007c00 	.word	0x40007c00
+ 8000c14:	0000ffff 	.word	0x0000ffff
+
+08000c18 <MX_LPUART1_UART_Init>:
+ * @brief LPUART1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_LPUART1_UART_Init(void)
+{
+ 8000c18:	b580      	push	{r7, lr}
+ 8000c1a:	af00      	add	r7, sp, #0
+	/* USER CODE END LPUART1_Init 0 */
+
+	/* USER CODE BEGIN LPUART1_Init 1 */
+
+	/* USER CODE END LPUART1_Init 1 */
+	hlpuart1.Instance = LPUART1;
+ 8000c1c:	4b13      	ldr	r3, [pc, #76]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c1e:	4a14      	ldr	r2, [pc, #80]	; (8000c70 <MX_LPUART1_UART_Init+0x58>)
+ 8000c20:	601a      	str	r2, [r3, #0]
+	hlpuart1.Init.BaudRate = 9600;
+ 8000c22:	4b12      	ldr	r3, [pc, #72]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c24:	2296      	movs	r2, #150	; 0x96
+ 8000c26:	0192      	lsls	r2, r2, #6
+ 8000c28:	605a      	str	r2, [r3, #4]
+	hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+ 8000c2a:	4b10      	ldr	r3, [pc, #64]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c2c:	2200      	movs	r2, #0
+ 8000c2e:	609a      	str	r2, [r3, #8]
+	hlpuart1.Init.StopBits = UART_STOPBITS_1;
+ 8000c30:	4b0e      	ldr	r3, [pc, #56]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c32:	2200      	movs	r2, #0
+ 8000c34:	60da      	str	r2, [r3, #12]
+	hlpuart1.Init.Parity = UART_PARITY_NONE;
+ 8000c36:	4b0d      	ldr	r3, [pc, #52]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c38:	2200      	movs	r2, #0
+ 8000c3a:	611a      	str	r2, [r3, #16]
+	hlpuart1.Init.Mode = UART_MODE_TX_RX;
+ 8000c3c:	4b0b      	ldr	r3, [pc, #44]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c3e:	220c      	movs	r2, #12
+ 8000c40:	615a      	str	r2, [r3, #20]
+	hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8000c42:	4b0a      	ldr	r3, [pc, #40]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c44:	2200      	movs	r2, #0
+ 8000c46:	619a      	str	r2, [r3, #24]
+	hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8000c48:	4b08      	ldr	r3, [pc, #32]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c4a:	2200      	movs	r2, #0
+ 8000c4c:	621a      	str	r2, [r3, #32]
+	hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 8000c4e:	4b07      	ldr	r3, [pc, #28]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c50:	2200      	movs	r2, #0
+ 8000c52:	625a      	str	r2, [r3, #36]	; 0x24
+	if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+ 8000c54:	4b05      	ldr	r3, [pc, #20]	; (8000c6c <MX_LPUART1_UART_Init+0x54>)
+ 8000c56:	0018      	movs	r0, r3
+ 8000c58:	f003 f8e2 	bl	8003e20 <HAL_UART_Init>
+ 8000c5c:	1e03      	subs	r3, r0, #0
+ 8000c5e:	d001      	beq.n	8000c64 <MX_LPUART1_UART_Init+0x4c>
+	{
+		Error_Handler();
+ 8000c60:	f000 f9e8 	bl	8001034 <Error_Handler>
+	}
+	/* USER CODE BEGIN LPUART1_Init 2 */
+
+	/* USER CODE END LPUART1_Init 2 */
+
+}
+ 8000c64:	46c0      	nop			; (mov r8, r8)
+ 8000c66:	46bd      	mov	sp, r7
+ 8000c68:	bd80      	pop	{r7, pc}
+ 8000c6a:	46c0      	nop			; (mov r8, r8)
+ 8000c6c:	20001734 	.word	0x20001734
+ 8000c70:	40004800 	.word	0x40004800
+
+08000c74 <MX_TIM2_Init>:
+ * @brief TIM2 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM2_Init(void)
+{
+ 8000c74:	b580      	push	{r7, lr}
+ 8000c76:	b08a      	sub	sp, #40	; 0x28
+ 8000c78:	af00      	add	r7, sp, #0
+
+	/* USER CODE BEGIN TIM2_Init 0 */
+
+	/* USER CODE END TIM2_Init 0 */
+
+	TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 8000c7a:	2318      	movs	r3, #24
+ 8000c7c:	18fb      	adds	r3, r7, r3
+ 8000c7e:	0018      	movs	r0, r3
+ 8000c80:	2310      	movs	r3, #16
+ 8000c82:	001a      	movs	r2, r3
+ 8000c84:	2100      	movs	r1, #0
+ 8000c86:	f006 fd9a 	bl	80077be <memset>
+	TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8000c8a:	2310      	movs	r3, #16
+ 8000c8c:	18fb      	adds	r3, r7, r3
+ 8000c8e:	0018      	movs	r0, r3
+ 8000c90:	2308      	movs	r3, #8
+ 8000c92:	001a      	movs	r2, r3
+ 8000c94:	2100      	movs	r1, #0
+ 8000c96:	f006 fd92 	bl	80077be <memset>
+	TIM_OC_InitTypeDef sConfigOC = {0};
+ 8000c9a:	003b      	movs	r3, r7
+ 8000c9c:	0018      	movs	r0, r3
+ 8000c9e:	2310      	movs	r3, #16
+ 8000ca0:	001a      	movs	r2, r3
+ 8000ca2:	2100      	movs	r1, #0
+ 8000ca4:	f006 fd8b 	bl	80077be <memset>
+
+	/* USER CODE BEGIN TIM2_Init 1 */
+
+	/* USER CODE END TIM2_Init 1 */
+	htim2.Instance = TIM2;
+ 8000ca8:	4b3f      	ldr	r3, [pc, #252]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000caa:	2280      	movs	r2, #128	; 0x80
+ 8000cac:	05d2      	lsls	r2, r2, #23
+ 8000cae:	601a      	str	r2, [r3, #0]
+	htim2.Init.Prescaler = 0;
+ 8000cb0:	4b3d      	ldr	r3, [pc, #244]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000cb2:	2200      	movs	r2, #0
+ 8000cb4:	605a      	str	r2, [r3, #4]
+	htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8000cb6:	4b3c      	ldr	r3, [pc, #240]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000cb8:	2200      	movs	r2, #0
+ 8000cba:	609a      	str	r2, [r3, #8]
+	htim2.Init.Period = 255;
+ 8000cbc:	4b3a      	ldr	r3, [pc, #232]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000cbe:	22ff      	movs	r2, #255	; 0xff
+ 8000cc0:	60da      	str	r2, [r3, #12]
+	htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8000cc2:	4b39      	ldr	r3, [pc, #228]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000cc4:	2200      	movs	r2, #0
+ 8000cc6:	611a      	str	r2, [r3, #16]
+	htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8000cc8:	4b37      	ldr	r3, [pc, #220]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000cca:	2200      	movs	r2, #0
+ 8000ccc:	615a      	str	r2, [r3, #20]
+	if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+ 8000cce:	4b36      	ldr	r3, [pc, #216]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000cd0:	0018      	movs	r0, r3
+ 8000cd2:	f002 fbab 	bl	800342c <HAL_TIM_Base_Init>
+ 8000cd6:	1e03      	subs	r3, r0, #0
+ 8000cd8:	d001      	beq.n	8000cde <MX_TIM2_Init+0x6a>
+	{
+		Error_Handler();
+ 8000cda:	f000 f9ab 	bl	8001034 <Error_Handler>
+	}
+	sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 8000cde:	2118      	movs	r1, #24
+ 8000ce0:	187b      	adds	r3, r7, r1
+ 8000ce2:	2280      	movs	r2, #128	; 0x80
+ 8000ce4:	0152      	lsls	r2, r2, #5
+ 8000ce6:	601a      	str	r2, [r3, #0]
+	if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+ 8000ce8:	187a      	adds	r2, r7, r1
+ 8000cea:	4b2f      	ldr	r3, [pc, #188]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000cec:	0011      	movs	r1, r2
+ 8000cee:	0018      	movs	r0, r3
+ 8000cf0:	f002 fd8a 	bl	8003808 <HAL_TIM_ConfigClockSource>
+ 8000cf4:	1e03      	subs	r3, r0, #0
+ 8000cf6:	d001      	beq.n	8000cfc <MX_TIM2_Init+0x88>
+	{
+		Error_Handler();
+ 8000cf8:	f000 f99c 	bl	8001034 <Error_Handler>
+	}
+	if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
+ 8000cfc:	4b2a      	ldr	r3, [pc, #168]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000cfe:	0018      	movs	r0, r3
+ 8000d00:	f002 fbd4 	bl	80034ac <HAL_TIM_PWM_Init>
+ 8000d04:	1e03      	subs	r3, r0, #0
+ 8000d06:	d001      	beq.n	8000d0c <MX_TIM2_Init+0x98>
+	{
+		Error_Handler();
+ 8000d08:	f000 f994 	bl	8001034 <Error_Handler>
+	}
+	sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8000d0c:	2110      	movs	r1, #16
+ 8000d0e:	187b      	adds	r3, r7, r1
+ 8000d10:	2200      	movs	r2, #0
+ 8000d12:	601a      	str	r2, [r3, #0]
+	sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8000d14:	187b      	adds	r3, r7, r1
+ 8000d16:	2200      	movs	r2, #0
+ 8000d18:	605a      	str	r2, [r3, #4]
+	if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+ 8000d1a:	187a      	adds	r2, r7, r1
+ 8000d1c:	4b22      	ldr	r3, [pc, #136]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000d1e:	0011      	movs	r1, r2
+ 8000d20:	0018      	movs	r0, r3
+ 8000d22:	f003 f82d 	bl	8003d80 <HAL_TIMEx_MasterConfigSynchronization>
+ 8000d26:	1e03      	subs	r3, r0, #0
+ 8000d28:	d001      	beq.n	8000d2e <MX_TIM2_Init+0xba>
+	{
+		Error_Handler();
+ 8000d2a:	f000 f983 	bl	8001034 <Error_Handler>
+	}
+	sConfigOC.OCMode = TIM_OCMODE_PWM1;
+ 8000d2e:	003b      	movs	r3, r7
+ 8000d30:	2260      	movs	r2, #96	; 0x60
+ 8000d32:	601a      	str	r2, [r3, #0]
+	sConfigOC.Pulse = 0;
+ 8000d34:	003b      	movs	r3, r7
+ 8000d36:	2200      	movs	r2, #0
+ 8000d38:	605a      	str	r2, [r3, #4]
+	sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 8000d3a:	003b      	movs	r3, r7
+ 8000d3c:	2200      	movs	r2, #0
+ 8000d3e:	609a      	str	r2, [r3, #8]
+	sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+ 8000d40:	003b      	movs	r3, r7
+ 8000d42:	2200      	movs	r2, #0
+ 8000d44:	60da      	str	r2, [r3, #12]
+	if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+ 8000d46:	0039      	movs	r1, r7
+ 8000d48:	4b17      	ldr	r3, [pc, #92]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000d4a:	2200      	movs	r2, #0
+ 8000d4c:	0018      	movs	r0, r3
+ 8000d4e:	f002 fc95 	bl	800367c <HAL_TIM_PWM_ConfigChannel>
+ 8000d52:	1e03      	subs	r3, r0, #0
+ 8000d54:	d001      	beq.n	8000d5a <MX_TIM2_Init+0xe6>
+	{
+		Error_Handler();
+ 8000d56:	f000 f96d 	bl	8001034 <Error_Handler>
+	}
+	if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+ 8000d5a:	0039      	movs	r1, r7
+ 8000d5c:	4b12      	ldr	r3, [pc, #72]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000d5e:	2204      	movs	r2, #4
+ 8000d60:	0018      	movs	r0, r3
+ 8000d62:	f002 fc8b 	bl	800367c <HAL_TIM_PWM_ConfigChannel>
+ 8000d66:	1e03      	subs	r3, r0, #0
+ 8000d68:	d001      	beq.n	8000d6e <MX_TIM2_Init+0xfa>
+	{
+		Error_Handler();
+ 8000d6a:	f000 f963 	bl	8001034 <Error_Handler>
+	}
+	if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+ 8000d6e:	0039      	movs	r1, r7
+ 8000d70:	4b0d      	ldr	r3, [pc, #52]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000d72:	2208      	movs	r2, #8
+ 8000d74:	0018      	movs	r0, r3
+ 8000d76:	f002 fc81 	bl	800367c <HAL_TIM_PWM_ConfigChannel>
+ 8000d7a:	1e03      	subs	r3, r0, #0
+ 8000d7c:	d001      	beq.n	8000d82 <MX_TIM2_Init+0x10e>
+	{
+		Error_Handler();
+ 8000d7e:	f000 f959 	bl	8001034 <Error_Handler>
+	}
+	if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+ 8000d82:	0039      	movs	r1, r7
+ 8000d84:	4b08      	ldr	r3, [pc, #32]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000d86:	220c      	movs	r2, #12
+ 8000d88:	0018      	movs	r0, r3
+ 8000d8a:	f002 fc77 	bl	800367c <HAL_TIM_PWM_ConfigChannel>
+ 8000d8e:	1e03      	subs	r3, r0, #0
+ 8000d90:	d001      	beq.n	8000d96 <MX_TIM2_Init+0x122>
+	{
+		Error_Handler();
+ 8000d92:	f000 f94f 	bl	8001034 <Error_Handler>
+	}
+	/* USER CODE BEGIN TIM2_Init 2 */
+
+	/* USER CODE END TIM2_Init 2 */
+	HAL_TIM_MspPostInit(&htim2);
+ 8000d96:	4b04      	ldr	r3, [pc, #16]	; (8000da8 <MX_TIM2_Init+0x134>)
+ 8000d98:	0018      	movs	r0, r3
+ 8000d9a:	f000 fb93 	bl	80014c4 <HAL_TIM_MspPostInit>
+
+}
+ 8000d9e:	46c0      	nop			; (mov r8, r8)
+ 8000da0:	46bd      	mov	sp, r7
+ 8000da2:	b00a      	add	sp, #40	; 0x28
+ 8000da4:	bd80      	pop	{r7, pc}
+ 8000da6:	46c0      	nop			; (mov r8, r8)
+ 8000da8:	20001878 	.word	0x20001878
+
+08000dac <MX_TIM21_Init>:
+ * @brief TIM21 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM21_Init(void)
+{
+ 8000dac:	b590      	push	{r4, r7, lr}
+ 8000dae:	b08d      	sub	sp, #52	; 0x34
+ 8000db0:	af00      	add	r7, sp, #0
+
+	/* USER CODE BEGIN TIM21_Init 0 */
+
+	/* USER CODE END TIM21_Init 0 */
+
+	TIM_Encoder_InitTypeDef sConfig = {0};
+ 8000db2:	240c      	movs	r4, #12
+ 8000db4:	193b      	adds	r3, r7, r4
+ 8000db6:	0018      	movs	r0, r3
+ 8000db8:	2324      	movs	r3, #36	; 0x24
+ 8000dba:	001a      	movs	r2, r3
+ 8000dbc:	2100      	movs	r1, #0
+ 8000dbe:	f006 fcfe 	bl	80077be <memset>
+	TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8000dc2:	1d3b      	adds	r3, r7, #4
+ 8000dc4:	0018      	movs	r0, r3
+ 8000dc6:	2308      	movs	r3, #8
+ 8000dc8:	001a      	movs	r2, r3
+ 8000dca:	2100      	movs	r1, #0
+ 8000dcc:	f006 fcf7 	bl	80077be <memset>
+
+	/* USER CODE BEGIN TIM21_Init 1 */
+
+	/* USER CODE END TIM21_Init 1 */
+	htim21.Instance = TIM21;
+ 8000dd0:	4b25      	ldr	r3, [pc, #148]	; (8000e68 <MX_TIM21_Init+0xbc>)
+ 8000dd2:	4a26      	ldr	r2, [pc, #152]	; (8000e6c <MX_TIM21_Init+0xc0>)
+ 8000dd4:	601a      	str	r2, [r3, #0]
+	htim21.Init.Prescaler = 0;
+ 8000dd6:	4b24      	ldr	r3, [pc, #144]	; (8000e68 <MX_TIM21_Init+0xbc>)
+ 8000dd8:	2200      	movs	r2, #0
+ 8000dda:	605a      	str	r2, [r3, #4]
+	htim21.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8000ddc:	4b22      	ldr	r3, [pc, #136]	; (8000e68 <MX_TIM21_Init+0xbc>)
+ 8000dde:	2200      	movs	r2, #0
+ 8000de0:	609a      	str	r2, [r3, #8]
+	htim21.Init.Period = 65535;
+ 8000de2:	4b21      	ldr	r3, [pc, #132]	; (8000e68 <MX_TIM21_Init+0xbc>)
+ 8000de4:	4a22      	ldr	r2, [pc, #136]	; (8000e70 <MX_TIM21_Init+0xc4>)
+ 8000de6:	60da      	str	r2, [r3, #12]
+	htim21.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8000de8:	4b1f      	ldr	r3, [pc, #124]	; (8000e68 <MX_TIM21_Init+0xbc>)
+ 8000dea:	2200      	movs	r2, #0
+ 8000dec:	611a      	str	r2, [r3, #16]
+	htim21.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8000dee:	4b1e      	ldr	r3, [pc, #120]	; (8000e68 <MX_TIM21_Init+0xbc>)
+ 8000df0:	2200      	movs	r2, #0
+ 8000df2:	615a      	str	r2, [r3, #20]
+	sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
+ 8000df4:	0021      	movs	r1, r4
+ 8000df6:	187b      	adds	r3, r7, r1
+ 8000df8:	2201      	movs	r2, #1
+ 8000dfa:	601a      	str	r2, [r3, #0]
+	sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
+ 8000dfc:	187b      	adds	r3, r7, r1
+ 8000dfe:	2200      	movs	r2, #0
+ 8000e00:	605a      	str	r2, [r3, #4]
+	sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+ 8000e02:	187b      	adds	r3, r7, r1
+ 8000e04:	2201      	movs	r2, #1
+ 8000e06:	609a      	str	r2, [r3, #8]
+	sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
+ 8000e08:	187b      	adds	r3, r7, r1
+ 8000e0a:	2200      	movs	r2, #0
+ 8000e0c:	60da      	str	r2, [r3, #12]
+	sConfig.IC1Filter = 0;
+ 8000e0e:	187b      	adds	r3, r7, r1
+ 8000e10:	2200      	movs	r2, #0
+ 8000e12:	611a      	str	r2, [r3, #16]
+	sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
+ 8000e14:	187b      	adds	r3, r7, r1
+ 8000e16:	2200      	movs	r2, #0
+ 8000e18:	615a      	str	r2, [r3, #20]
+	sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
+ 8000e1a:	187b      	adds	r3, r7, r1
+ 8000e1c:	2201      	movs	r2, #1
+ 8000e1e:	619a      	str	r2, [r3, #24]
+	sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
+ 8000e20:	187b      	adds	r3, r7, r1
+ 8000e22:	2200      	movs	r2, #0
+ 8000e24:	61da      	str	r2, [r3, #28]
+	sConfig.IC2Filter = 0;
+ 8000e26:	187b      	adds	r3, r7, r1
+ 8000e28:	2200      	movs	r2, #0
+ 8000e2a:	621a      	str	r2, [r3, #32]
+	if (HAL_TIM_Encoder_Init(&htim21, &sConfig) != HAL_OK)
+ 8000e2c:	187a      	adds	r2, r7, r1
+ 8000e2e:	4b0e      	ldr	r3, [pc, #56]	; (8000e68 <MX_TIM21_Init+0xbc>)
+ 8000e30:	0011      	movs	r1, r2
+ 8000e32:	0018      	movs	r0, r3
+ 8000e34:	f002 fb82 	bl	800353c <HAL_TIM_Encoder_Init>
+ 8000e38:	1e03      	subs	r3, r0, #0
+ 8000e3a:	d001      	beq.n	8000e40 <MX_TIM21_Init+0x94>
+	{
+		Error_Handler();
+ 8000e3c:	f000 f8fa 	bl	8001034 <Error_Handler>
+	}
+	sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8000e40:	1d3b      	adds	r3, r7, #4
+ 8000e42:	2200      	movs	r2, #0
+ 8000e44:	601a      	str	r2, [r3, #0]
+	sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8000e46:	1d3b      	adds	r3, r7, #4
+ 8000e48:	2200      	movs	r2, #0
+ 8000e4a:	605a      	str	r2, [r3, #4]
+	if (HAL_TIMEx_MasterConfigSynchronization(&htim21, &sMasterConfig) != HAL_OK)
+ 8000e4c:	1d3a      	adds	r2, r7, #4
+ 8000e4e:	4b06      	ldr	r3, [pc, #24]	; (8000e68 <MX_TIM21_Init+0xbc>)
+ 8000e50:	0011      	movs	r1, r2
+ 8000e52:	0018      	movs	r0, r3
+ 8000e54:	f002 ff94 	bl	8003d80 <HAL_TIMEx_MasterConfigSynchronization>
+ 8000e58:	1e03      	subs	r3, r0, #0
+ 8000e5a:	d001      	beq.n	8000e60 <MX_TIM21_Init+0xb4>
+	{
+		Error_Handler();
+ 8000e5c:	f000 f8ea 	bl	8001034 <Error_Handler>
+	}
+	/* USER CODE BEGIN TIM21_Init 2 */
+
+	/* USER CODE END TIM21_Init 2 */
+
+}
+ 8000e60:	46c0      	nop			; (mov r8, r8)
+ 8000e62:	46bd      	mov	sp, r7
+ 8000e64:	b00d      	add	sp, #52	; 0x34
+ 8000e66:	bd90      	pop	{r4, r7, pc}
+ 8000e68:	20001914 	.word	0x20001914
+ 8000e6c:	40010800 	.word	0x40010800
+ 8000e70:	0000ffff 	.word	0x0000ffff
+
+08000e74 <MX_DMA_Init>:
+
+/**
+ * Enable DMA controller clock
+ */
+static void MX_DMA_Init(void)
+{
+ 8000e74:	b580      	push	{r7, lr}
+ 8000e76:	b082      	sub	sp, #8
+ 8000e78:	af00      	add	r7, sp, #0
+
+	/* DMA controller clock enable */
+	__HAL_RCC_DMA1_CLK_ENABLE();
+ 8000e7a:	4b0c      	ldr	r3, [pc, #48]	; (8000eac <MX_DMA_Init+0x38>)
+ 8000e7c:	6b1a      	ldr	r2, [r3, #48]	; 0x30
+ 8000e7e:	4b0b      	ldr	r3, [pc, #44]	; (8000eac <MX_DMA_Init+0x38>)
+ 8000e80:	2101      	movs	r1, #1
+ 8000e82:	430a      	orrs	r2, r1
+ 8000e84:	631a      	str	r2, [r3, #48]	; 0x30
+ 8000e86:	4b09      	ldr	r3, [pc, #36]	; (8000eac <MX_DMA_Init+0x38>)
+ 8000e88:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8000e8a:	2201      	movs	r2, #1
+ 8000e8c:	4013      	ands	r3, r2
+ 8000e8e:	607b      	str	r3, [r7, #4]
+ 8000e90:	687b      	ldr	r3, [r7, #4]
+
+	/* DMA interrupt init */
+	/* DMA1_Channel2_3_IRQn interrupt configuration */
+	HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3, 0);
+ 8000e92:	2200      	movs	r2, #0
+ 8000e94:	2103      	movs	r1, #3
+ 8000e96:	200a      	movs	r0, #10
+ 8000e98:	f000 ffe4 	bl	8001e64 <HAL_NVIC_SetPriority>
+	HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+ 8000e9c:	200a      	movs	r0, #10
+ 8000e9e:	f000 fff6 	bl	8001e8e <HAL_NVIC_EnableIRQ>
+
+}
+ 8000ea2:	46c0      	nop			; (mov r8, r8)
+ 8000ea4:	46bd      	mov	sp, r7
+ 8000ea6:	b002      	add	sp, #8
+ 8000ea8:	bd80      	pop	{r7, pc}
+ 8000eaa:	46c0      	nop			; (mov r8, r8)
+ 8000eac:	40021000 	.word	0x40021000
+
+08000eb0 <MX_GPIO_Init>:
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ 8000eb0:	b590      	push	{r4, r7, lr}
+ 8000eb2:	b089      	sub	sp, #36	; 0x24
+ 8000eb4:	af00      	add	r7, sp, #0
+	GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000eb6:	240c      	movs	r4, #12
+ 8000eb8:	193b      	adds	r3, r7, r4
+ 8000eba:	0018      	movs	r0, r3
+ 8000ebc:	2314      	movs	r3, #20
+ 8000ebe:	001a      	movs	r2, r3
+ 8000ec0:	2100      	movs	r1, #0
+ 8000ec2:	f006 fc7c 	bl	80077be <memset>
+
+	/* GPIO Ports Clock Enable */
+	__HAL_RCC_GPIOC_CLK_ENABLE();
+ 8000ec6:	4b44      	ldr	r3, [pc, #272]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000ec8:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8000eca:	4b43      	ldr	r3, [pc, #268]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000ecc:	2104      	movs	r1, #4
+ 8000ece:	430a      	orrs	r2, r1
+ 8000ed0:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8000ed2:	4b41      	ldr	r3, [pc, #260]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000ed4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000ed6:	2204      	movs	r2, #4
+ 8000ed8:	4013      	ands	r3, r2
+ 8000eda:	60bb      	str	r3, [r7, #8]
+ 8000edc:	68bb      	ldr	r3, [r7, #8]
+	__HAL_RCC_GPIOA_CLK_ENABLE();
+ 8000ede:	4b3e      	ldr	r3, [pc, #248]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000ee0:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8000ee2:	4b3d      	ldr	r3, [pc, #244]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000ee4:	2101      	movs	r1, #1
+ 8000ee6:	430a      	orrs	r2, r1
+ 8000ee8:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8000eea:	4b3b      	ldr	r3, [pc, #236]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000eec:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000eee:	2201      	movs	r2, #1
+ 8000ef0:	4013      	ands	r3, r2
+ 8000ef2:	607b      	str	r3, [r7, #4]
+ 8000ef4:	687b      	ldr	r3, [r7, #4]
+	__HAL_RCC_GPIOB_CLK_ENABLE();
+ 8000ef6:	4b38      	ldr	r3, [pc, #224]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000ef8:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8000efa:	4b37      	ldr	r3, [pc, #220]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000efc:	2102      	movs	r1, #2
+ 8000efe:	430a      	orrs	r2, r1
+ 8000f00:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8000f02:	4b35      	ldr	r3, [pc, #212]	; (8000fd8 <MX_GPIO_Init+0x128>)
+ 8000f04:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000f06:	2202      	movs	r2, #2
+ 8000f08:	4013      	ands	r3, r2
+ 8000f0a:	603b      	str	r3, [r7, #0]
+ 8000f0c:	683b      	ldr	r3, [r7, #0]
+
+	/*Configure GPIO pin Output Level */
+	HAL_GPIO_WritePin(GPIOB, LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin|SHUTDOWN_ENCODERS_Pin
+ 8000f0e:	23f1      	movs	r3, #241	; 0xf1
+ 8000f10:	021b      	lsls	r3, r3, #8
+ 8000f12:	4832      	ldr	r0, [pc, #200]	; (8000fdc <MX_GPIO_Init+0x12c>)
+ 8000f14:	2200      	movs	r2, #0
+ 8000f16:	0019      	movs	r1, r3
+ 8000f18:	f001 faf2 	bl	8002500 <HAL_GPIO_WritePin>
+			|SHUTDOWN_5V_Pin, GPIO_PIN_RESET);
+
+	/*Configure GPIO pin Output Level */
+	HAL_GPIO_WritePin(SHUTDOWN_GPIO_Port, SHUTDOWN_Pin, GPIO_PIN_SET);
+ 8000f1c:	2380      	movs	r3, #128	; 0x80
+ 8000f1e:	009b      	lsls	r3, r3, #2
+ 8000f20:	482e      	ldr	r0, [pc, #184]	; (8000fdc <MX_GPIO_Init+0x12c>)
+ 8000f22:	2201      	movs	r2, #1
+ 8000f24:	0019      	movs	r1, r3
+ 8000f26:	f001 faeb 	bl	8002500 <HAL_GPIO_WritePin>
+
+	/*Configure GPIO pins : LED_ROUGE_Pin LED_ORANGE_Pin LED_VERTE_Pin */
+	GPIO_InitStruct.Pin = LED_ROUGE_Pin|LED_ORANGE_Pin|LED_VERTE_Pin;
+ 8000f2a:	193b      	adds	r3, r7, r4
+ 8000f2c:	22e0      	movs	r2, #224	; 0xe0
+ 8000f2e:	01d2      	lsls	r2, r2, #7
+ 8000f30:	601a      	str	r2, [r3, #0]
+	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8000f32:	193b      	adds	r3, r7, r4
+ 8000f34:	2201      	movs	r2, #1
+ 8000f36:	605a      	str	r2, [r3, #4]
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000f38:	193b      	adds	r3, r7, r4
+ 8000f3a:	2200      	movs	r2, #0
+ 8000f3c:	609a      	str	r2, [r3, #8]
+	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000f3e:	193b      	adds	r3, r7, r4
+ 8000f40:	2203      	movs	r2, #3
+ 8000f42:	60da      	str	r2, [r3, #12]
+	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8000f44:	193b      	adds	r3, r7, r4
+ 8000f46:	4a25      	ldr	r2, [pc, #148]	; (8000fdc <MX_GPIO_Init+0x12c>)
+ 8000f48:	0019      	movs	r1, r3
+ 8000f4a:	0010      	movs	r0, r2
+ 8000f4c:	f001 f96a 	bl	8002224 <HAL_GPIO_Init>
+
+	/*Configure GPIO pins : SHUTDOWN_ENCODERS_Pin SHUTDOWN_5V_Pin SHUTDOWN_Pin */
+	GPIO_InitStruct.Pin = SHUTDOWN_ENCODERS_Pin|SHUTDOWN_5V_Pin|SHUTDOWN_Pin;
+ 8000f50:	0021      	movs	r1, r4
+ 8000f52:	187b      	adds	r3, r7, r1
+ 8000f54:	2283      	movs	r2, #131	; 0x83
+ 8000f56:	0212      	lsls	r2, r2, #8
+ 8000f58:	601a      	str	r2, [r3, #0]
+	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8000f5a:	000c      	movs	r4, r1
+ 8000f5c:	193b      	adds	r3, r7, r4
+ 8000f5e:	2201      	movs	r2, #1
+ 8000f60:	605a      	str	r2, [r3, #4]
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000f62:	193b      	adds	r3, r7, r4
+ 8000f64:	2200      	movs	r2, #0
+ 8000f66:	609a      	str	r2, [r3, #8]
+	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8000f68:	193b      	adds	r3, r7, r4
+ 8000f6a:	2200      	movs	r2, #0
+ 8000f6c:	60da      	str	r2, [r3, #12]
+	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8000f6e:	193b      	adds	r3, r7, r4
+ 8000f70:	4a1a      	ldr	r2, [pc, #104]	; (8000fdc <MX_GPIO_Init+0x12c>)
+ 8000f72:	0019      	movs	r1, r3
+ 8000f74:	0010      	movs	r0, r2
+ 8000f76:	f001 f955 	bl	8002224 <HAL_GPIO_Init>
+
+	/*Configure GPIO pins : BUTTON_SENSE_Pin USB_SENSE_Pin */
+	GPIO_InitStruct.Pin = BUTTON_SENSE_Pin|USB_SENSE_Pin;
+ 8000f7a:	0021      	movs	r1, r4
+ 8000f7c:	187b      	adds	r3, r7, r1
+ 8000f7e:	2218      	movs	r2, #24
+ 8000f80:	601a      	str	r2, [r3, #0]
+	GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+ 8000f82:	187b      	adds	r3, r7, r1
+ 8000f84:	2288      	movs	r2, #136	; 0x88
+ 8000f86:	0352      	lsls	r2, r2, #13
+ 8000f88:	605a      	str	r2, [r3, #4]
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000f8a:	187b      	adds	r3, r7, r1
+ 8000f8c:	2200      	movs	r2, #0
+ 8000f8e:	609a      	str	r2, [r3, #8]
+	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8000f90:	000c      	movs	r4, r1
+ 8000f92:	187b      	adds	r3, r7, r1
+ 8000f94:	4a11      	ldr	r2, [pc, #68]	; (8000fdc <MX_GPIO_Init+0x12c>)
+ 8000f96:	0019      	movs	r1, r3
+ 8000f98:	0010      	movs	r0, r2
+ 8000f9a:	f001 f943 	bl	8002224 <HAL_GPIO_Init>
+
+	/*Configure GPIO pins : CHARGER_ST2_Pin CHARGER_ST1_Pin */
+	GPIO_InitStruct.Pin = CHARGER_ST2_Pin|CHARGER_ST1_Pin;
+ 8000f9e:	0021      	movs	r1, r4
+ 8000fa0:	187b      	adds	r3, r7, r1
+ 8000fa2:	22c0      	movs	r2, #192	; 0xc0
+ 8000fa4:	601a      	str	r2, [r3, #0]
+	GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 8000fa6:	187b      	adds	r3, r7, r1
+ 8000fa8:	2200      	movs	r2, #0
+ 8000faa:	605a      	str	r2, [r3, #4]
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000fac:	187b      	adds	r3, r7, r1
+ 8000fae:	2200      	movs	r2, #0
+ 8000fb0:	609a      	str	r2, [r3, #8]
+	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8000fb2:	187b      	adds	r3, r7, r1
+ 8000fb4:	4a09      	ldr	r2, [pc, #36]	; (8000fdc <MX_GPIO_Init+0x12c>)
+ 8000fb6:	0019      	movs	r1, r3
+ 8000fb8:	0010      	movs	r0, r2
+ 8000fba:	f001 f933 	bl	8002224 <HAL_GPIO_Init>
+
+	/* EXTI interrupt init*/
+	HAL_NVIC_SetPriority(EXTI2_3_IRQn, 3, 0);
+ 8000fbe:	2200      	movs	r2, #0
+ 8000fc0:	2103      	movs	r1, #3
+ 8000fc2:	2006      	movs	r0, #6
+ 8000fc4:	f000 ff4e 	bl	8001e64 <HAL_NVIC_SetPriority>
+	HAL_NVIC_EnableIRQ(EXTI2_3_IRQn);
+ 8000fc8:	2006      	movs	r0, #6
+ 8000fca:	f000 ff60 	bl	8001e8e <HAL_NVIC_EnableIRQ>
+}
+ 8000fce:	46c0      	nop			; (mov r8, r8)
+ 8000fd0:	46bd      	mov	sp, r7
+ 8000fd2:	b009      	add	sp, #36	; 0x24
+ 8000fd4:	bd90      	pop	{r4, r7, pc}
+ 8000fd6:	46c0      	nop			; (mov r8, r8)
+ 8000fd8:	40021000 	.word	0x40021000
+ 8000fdc:	50000400 	.word	0x50000400
+
+08000fe0 <StartDefaultTask>:
+ * @param  argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void *argument)
+{
+ 8000fe0:	b590      	push	{r4, r7, lr}
+ 8000fe2:	b085      	sub	sp, #20
+ 8000fe4:	af00      	add	r7, sp, #0
+ 8000fe6:	6078      	str	r0, [r7, #4]
+	/* USER CODE BEGIN 5 */
+	LEDS_State state = leds_off;
+ 8000fe8:	230f      	movs	r3, #15
+ 8000fea:	18fb      	adds	r3, r7, r3
+ 8000fec:	2200      	movs	r2, #0
+ 8000fee:	701a      	strb	r2, [r3, #0]
+
+	/* Infinite loop */
+	for(;;)
+	{
+		state++;
+ 8000ff0:	210f      	movs	r1, #15
+ 8000ff2:	187b      	adds	r3, r7, r1
+ 8000ff4:	781b      	ldrb	r3, [r3, #0]
+ 8000ff6:	3301      	adds	r3, #1
+ 8000ff8:	b2da      	uxtb	r2, r3
+ 8000ffa:	187b      	adds	r3, r7, r1
+ 8000ffc:	701a      	strb	r2, [r3, #0]
+		MESSAGE_SendMailbox(LEDS_Mailbox, MSG_ID_LED_ETAT, SEQUENCEUR_Mailbox, (void*)&state);
+ 8000ffe:	4b0b      	ldr	r3, [pc, #44]	; (800102c <StartDefaultTask+0x4c>)
+ 8001000:	6818      	ldr	r0, [r3, #0]
+ 8001002:	4b0b      	ldr	r3, [pc, #44]	; (8001030 <StartDefaultTask+0x50>)
+ 8001004:	681a      	ldr	r2, [r3, #0]
+ 8001006:	000c      	movs	r4, r1
+ 8001008:	187b      	adds	r3, r7, r1
+ 800100a:	2100      	movs	r1, #0
+ 800100c:	f000 f872 	bl	80010f4 <MESSAGE_SendMailbox>
+
+		if (state>leds_erreur)
+ 8001010:	0021      	movs	r1, r4
+ 8001012:	187b      	adds	r3, r7, r1
+ 8001014:	781b      	ldrb	r3, [r3, #0]
+ 8001016:	2b10      	cmp	r3, #16
+ 8001018:	d902      	bls.n	8001020 <StartDefaultTask+0x40>
+			state = leds_off;
+ 800101a:	187b      	adds	r3, r7, r1
+ 800101c:	2200      	movs	r2, #0
+ 800101e:	701a      	strb	r2, [r3, #0]
+
+		vTaskDelay(pdMS_TO_TICKS(5000));
+ 8001020:	23fa      	movs	r3, #250	; 0xfa
+ 8001022:	005b      	lsls	r3, r3, #1
+ 8001024:	0018      	movs	r0, r3
+ 8001026:	f004 fedb 	bl	8005de0 <vTaskDelay>
+		state++;
+ 800102a:	e7e1      	b.n	8000ff0 <StartDefaultTask+0x10>
+ 800102c:	20001964 	.word	0x20001964
+ 8001030:	20001960 	.word	0x20001960
+
+08001034 <Error_Handler>:
+/**
+ * @brief  This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ 8001034:	b580      	push	{r7, lr}
+ 8001036:	af00      	add	r7, sp, #0
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+ 8001038:	b672      	cpsid	i
+}
+ 800103a:	46c0      	nop			; (mov r8, r8)
+	/* USER CODE BEGIN Error_Handler_Debug */
+	/* User can add his own implementation to report the HAL error return state */
+	__disable_irq();
+	while (1)
+ 800103c:	e7fe      	b.n	800103c <Error_Handler+0x8>
+	...
+
+08001040 <MESSAGE_Init>:
+QueueHandle_t MOTEURS_Mailbox;
+QueueHandle_t SEQUENCEUR_Mailbox;
+QueueHandle_t BATTERIE_Mailbox;
+QueueHandle_t XBEE_Mailbox;
+
+void  MESSAGE_Init(void) {
+ 8001040:	b580      	push	{r7, lr}
+ 8001042:	af00      	add	r7, sp, #0
+	LEDS_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+ 8001044:	2200      	movs	r2, #0
+ 8001046:	210c      	movs	r1, #12
+ 8001048:	2005      	movs	r0, #5
+ 800104a:	f004 f980 	bl	800534e <xQueueGenericCreate>
+ 800104e:	0002      	movs	r2, r0
+ 8001050:	4b12      	ldr	r3, [pc, #72]	; (800109c <MESSAGE_Init+0x5c>)
+ 8001052:	601a      	str	r2, [r3, #0]
+	MOTEURS_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+ 8001054:	2200      	movs	r2, #0
+ 8001056:	210c      	movs	r1, #12
+ 8001058:	2005      	movs	r0, #5
+ 800105a:	f004 f978 	bl	800534e <xQueueGenericCreate>
+ 800105e:	0002      	movs	r2, r0
+ 8001060:	4b0f      	ldr	r3, [pc, #60]	; (80010a0 <MESSAGE_Init+0x60>)
+ 8001062:	601a      	str	r2, [r3, #0]
+	SEQUENCEUR_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+ 8001064:	2200      	movs	r2, #0
+ 8001066:	210c      	movs	r1, #12
+ 8001068:	2005      	movs	r0, #5
+ 800106a:	f004 f970 	bl	800534e <xQueueGenericCreate>
+ 800106e:	0002      	movs	r2, r0
+ 8001070:	4b0c      	ldr	r3, [pc, #48]	; (80010a4 <MESSAGE_Init+0x64>)
+ 8001072:	601a      	str	r2, [r3, #0]
+	BATTERIE_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+ 8001074:	2200      	movs	r2, #0
+ 8001076:	210c      	movs	r1, #12
+ 8001078:	2005      	movs	r0, #5
+ 800107a:	f004 f968 	bl	800534e <xQueueGenericCreate>
+ 800107e:	0002      	movs	r2, r0
+ 8001080:	4b09      	ldr	r3, [pc, #36]	; (80010a8 <MESSAGE_Init+0x68>)
+ 8001082:	601a      	str	r2, [r3, #0]
+	XBEE_Mailbox = xQueueCreate(QUEUE_SIZE, sizeof(MESSAGE_Typedef));
+ 8001084:	2200      	movs	r2, #0
+ 8001086:	210c      	movs	r1, #12
+ 8001088:	2005      	movs	r0, #5
+ 800108a:	f004 f960 	bl	800534e <xQueueGenericCreate>
+ 800108e:	0002      	movs	r2, r0
+ 8001090:	4b06      	ldr	r3, [pc, #24]	; (80010ac <MESSAGE_Init+0x6c>)
+ 8001092:	601a      	str	r2, [r3, #0]
+}
+ 8001094:	46c0      	nop			; (mov r8, r8)
+ 8001096:	46bd      	mov	sp, r7
+ 8001098:	bd80      	pop	{r7, pc}
+ 800109a:	46c0      	nop			; (mov r8, r8)
+ 800109c:	20001964 	.word	0x20001964
+ 80010a0:	20001958 	.word	0x20001958
+ 80010a4:	20001960 	.word	0x20001960
+ 80010a8:	2000195c 	.word	0x2000195c
+ 80010ac:	20001954 	.word	0x20001954
+
+080010b0 <MESSAGE_ReadMailboxNoDelay>:
+	}
+
+	return msg;
+}
+
+MESSAGE_Typedef MESSAGE_ReadMailboxNoDelay(QueueHandle_t mbx) {
+ 80010b0:	b590      	push	{r4, r7, lr}
+ 80010b2:	b087      	sub	sp, #28
+ 80010b4:	af00      	add	r7, sp, #0
+ 80010b6:	6078      	str	r0, [r7, #4]
+ 80010b8:	6039      	str	r1, [r7, #0]
+	MESSAGE_Typedef msg= {0};
+ 80010ba:	240c      	movs	r4, #12
+ 80010bc:	193b      	adds	r3, r7, r4
+ 80010be:	0018      	movs	r0, r3
+ 80010c0:	230c      	movs	r3, #12
+ 80010c2:	001a      	movs	r2, r3
+ 80010c4:	2100      	movs	r1, #0
+ 80010c6:	f006 fb7a 	bl	80077be <memset>
+
+	if (!xQueueReceive(mbx, &msg, 0))  // Pas de message dans la mailbox
+ 80010ca:	1939      	adds	r1, r7, r4
+ 80010cc:	683b      	ldr	r3, [r7, #0]
+ 80010ce:	2200      	movs	r2, #0
+ 80010d0:	0018      	movs	r0, r3
+ 80010d2:	f004 fad0 	bl	8005676 <xQueueReceive>
+ 80010d6:	1e03      	subs	r3, r0, #0
+ 80010d8:	d103      	bne.n	80010e2 <MESSAGE_ReadMailboxNoDelay+0x32>
+		msg.id=MSG_ID_NO_MESSAGE;
+ 80010da:	193b      	adds	r3, r7, r4
+ 80010dc:	2201      	movs	r2, #1
+ 80010de:	4252      	negs	r2, r2
+ 80010e0:	801a      	strh	r2, [r3, #0]
+
+	return msg;
+ 80010e2:	687b      	ldr	r3, [r7, #4]
+ 80010e4:	220c      	movs	r2, #12
+ 80010e6:	18ba      	adds	r2, r7, r2
+ 80010e8:	ca13      	ldmia	r2!, {r0, r1, r4}
+ 80010ea:	c313      	stmia	r3!, {r0, r1, r4}
+}
+ 80010ec:	6878      	ldr	r0, [r7, #4]
+ 80010ee:	46bd      	mov	sp, r7
+ 80010f0:	b007      	add	sp, #28
+ 80010f2:	bd90      	pop	{r4, r7, pc}
+
+080010f4 <MESSAGE_SendMailbox>:
+
+void MESSAGE_SendMailbox(QueueHandle_t mbx_dest, uint16_t id, QueueHandle_t mbx_sender, void *data){
+ 80010f4:	b580      	push	{r7, lr}
+ 80010f6:	b088      	sub	sp, #32
+ 80010f8:	af00      	add	r7, sp, #0
+ 80010fa:	60f8      	str	r0, [r7, #12]
+ 80010fc:	607a      	str	r2, [r7, #4]
+ 80010fe:	603b      	str	r3, [r7, #0]
+ 8001100:	200a      	movs	r0, #10
+ 8001102:	183b      	adds	r3, r7, r0
+ 8001104:	1c0a      	adds	r2, r1, #0
+ 8001106:	801a      	strh	r2, [r3, #0]
+	MESSAGE_Typedef msg;
+
+	msg.id=id;
+ 8001108:	2114      	movs	r1, #20
+ 800110a:	187b      	adds	r3, r7, r1
+ 800110c:	183a      	adds	r2, r7, r0
+ 800110e:	8812      	ldrh	r2, [r2, #0]
+ 8001110:	801a      	strh	r2, [r3, #0]
+	msg.sender = &mbx_sender;
+ 8001112:	187b      	adds	r3, r7, r1
+ 8001114:	1d3a      	adds	r2, r7, #4
+ 8001116:	605a      	str	r2, [r3, #4]
+	msg.data=data;
+ 8001118:	187b      	adds	r3, r7, r1
+ 800111a:	683a      	ldr	r2, [r7, #0]
+ 800111c:	609a      	str	r2, [r3, #8]
+
+	if (!xQueueSend(mbx_dest, &msg, 0)) { // envoi sans attendre
+ 800111e:	1879      	adds	r1, r7, r1
+ 8001120:	68f8      	ldr	r0, [r7, #12]
+ 8001122:	2300      	movs	r3, #0
+ 8001124:	2200      	movs	r2, #0
+ 8001126:	f004 f971 	bl	800540c <xQueueGenericSend>
+		//printf("Failed to send data, Queue full.\r\n");
+	}
+}
+ 800112a:	46c0      	nop			; (mov r8, r8)
+ 800112c:	46bd      	mov	sp, r7
+ 800112e:	b008      	add	sp, #32
+ 8001130:	bd80      	pop	{r7, pc}
+	...
+
+08001134 <HAL_MspInit>:
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+ 8001134:	b580      	push	{r7, lr}
+ 8001136:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8001138:	4b0b      	ldr	r3, [pc, #44]	; (8001168 <HAL_MspInit+0x34>)
+ 800113a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800113c:	4b0a      	ldr	r3, [pc, #40]	; (8001168 <HAL_MspInit+0x34>)
+ 800113e:	2101      	movs	r1, #1
+ 8001140:	430a      	orrs	r2, r1
+ 8001142:	635a      	str	r2, [r3, #52]	; 0x34
+  __HAL_RCC_PWR_CLK_ENABLE();
+ 8001144:	4b08      	ldr	r3, [pc, #32]	; (8001168 <HAL_MspInit+0x34>)
+ 8001146:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8001148:	4b07      	ldr	r3, [pc, #28]	; (8001168 <HAL_MspInit+0x34>)
+ 800114a:	2180      	movs	r1, #128	; 0x80
+ 800114c:	0549      	lsls	r1, r1, #21
+ 800114e:	430a      	orrs	r2, r1
+ 8001150:	639a      	str	r2, [r3, #56]	; 0x38
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 3, 0);
+ 8001152:	2302      	movs	r3, #2
+ 8001154:	425b      	negs	r3, r3
+ 8001156:	2200      	movs	r2, #0
+ 8001158:	2103      	movs	r1, #3
+ 800115a:	0018      	movs	r0, r3
+ 800115c:	f000 fe82 	bl	8001e64 <HAL_NVIC_SetPriority>
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+ 8001160:	46c0      	nop			; (mov r8, r8)
+ 8001162:	46bd      	mov	sp, r7
+ 8001164:	bd80      	pop	{r7, pc}
+ 8001166:	46c0      	nop			; (mov r8, r8)
+ 8001168:	40021000 	.word	0x40021000
+
+0800116c <HAL_ADC_MspInit>:
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ 800116c:	b590      	push	{r4, r7, lr}
+ 800116e:	b089      	sub	sp, #36	; 0x24
+ 8001170:	af00      	add	r7, sp, #0
+ 8001172:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8001174:	240c      	movs	r4, #12
+ 8001176:	193b      	adds	r3, r7, r4
+ 8001178:	0018      	movs	r0, r3
+ 800117a:	2314      	movs	r3, #20
+ 800117c:	001a      	movs	r2, r3
+ 800117e:	2100      	movs	r1, #0
+ 8001180:	f006 fb1d 	bl	80077be <memset>
+  if(hadc->Instance==ADC1)
+ 8001184:	687b      	ldr	r3, [r7, #4]
+ 8001186:	681b      	ldr	r3, [r3, #0]
+ 8001188:	4a18      	ldr	r2, [pc, #96]	; (80011ec <HAL_ADC_MspInit+0x80>)
+ 800118a:	4293      	cmp	r3, r2
+ 800118c:	d12a      	bne.n	80011e4 <HAL_ADC_MspInit+0x78>
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC1_CLK_ENABLE();
+ 800118e:	4b18      	ldr	r3, [pc, #96]	; (80011f0 <HAL_ADC_MspInit+0x84>)
+ 8001190:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8001192:	4b17      	ldr	r3, [pc, #92]	; (80011f0 <HAL_ADC_MspInit+0x84>)
+ 8001194:	2180      	movs	r1, #128	; 0x80
+ 8001196:	0089      	lsls	r1, r1, #2
+ 8001198:	430a      	orrs	r2, r1
+ 800119a:	635a      	str	r2, [r3, #52]	; 0x34
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 800119c:	4b14      	ldr	r3, [pc, #80]	; (80011f0 <HAL_ADC_MspInit+0x84>)
+ 800119e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80011a0:	4b13      	ldr	r3, [pc, #76]	; (80011f0 <HAL_ADC_MspInit+0x84>)
+ 80011a2:	2101      	movs	r1, #1
+ 80011a4:	430a      	orrs	r2, r1
+ 80011a6:	62da      	str	r2, [r3, #44]	; 0x2c
+ 80011a8:	4b11      	ldr	r3, [pc, #68]	; (80011f0 <HAL_ADC_MspInit+0x84>)
+ 80011aa:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80011ac:	2201      	movs	r2, #1
+ 80011ae:	4013      	ands	r3, r2
+ 80011b0:	60bb      	str	r3, [r7, #8]
+ 80011b2:	68bb      	ldr	r3, [r7, #8]
+    /**ADC GPIO Configuration
+    PA0     ------> ADC_IN0
+    */
+    GPIO_InitStruct.Pin = BATTERY_SENSE_Pin;
+ 80011b4:	193b      	adds	r3, r7, r4
+ 80011b6:	2201      	movs	r2, #1
+ 80011b8:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 80011ba:	193b      	adds	r3, r7, r4
+ 80011bc:	2203      	movs	r2, #3
+ 80011be:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80011c0:	193b      	adds	r3, r7, r4
+ 80011c2:	2200      	movs	r2, #0
+ 80011c4:	609a      	str	r2, [r3, #8]
+    HAL_GPIO_Init(BATTERY_SENSE_GPIO_Port, &GPIO_InitStruct);
+ 80011c6:	193a      	adds	r2, r7, r4
+ 80011c8:	23a0      	movs	r3, #160	; 0xa0
+ 80011ca:	05db      	lsls	r3, r3, #23
+ 80011cc:	0011      	movs	r1, r2
+ 80011ce:	0018      	movs	r0, r3
+ 80011d0:	f001 f828 	bl	8002224 <HAL_GPIO_Init>
+
+    /* ADC1 interrupt Init */
+    HAL_NVIC_SetPriority(ADC1_IRQn, 3, 0);
+ 80011d4:	2200      	movs	r2, #0
+ 80011d6:	2103      	movs	r1, #3
+ 80011d8:	200c      	movs	r0, #12
+ 80011da:	f000 fe43 	bl	8001e64 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(ADC1_IRQn);
+ 80011de:	200c      	movs	r0, #12
+ 80011e0:	f000 fe55 	bl	8001e8e <HAL_NVIC_EnableIRQ>
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+ 80011e4:	46c0      	nop			; (mov r8, r8)
+ 80011e6:	46bd      	mov	sp, r7
+ 80011e8:	b009      	add	sp, #36	; 0x24
+ 80011ea:	bd90      	pop	{r4, r7, pc}
+ 80011ec:	40012400 	.word	0x40012400
+ 80011f0:	40021000 	.word	0x40021000
+
+080011f4 <HAL_LPTIM_MspInit>:
+* This function configures the hardware resources used in this example
+* @param hlptim: LPTIM handle pointer
+* @retval None
+*/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim)
+{
+ 80011f4:	b590      	push	{r4, r7, lr}
+ 80011f6:	b08b      	sub	sp, #44	; 0x2c
+ 80011f8:	af00      	add	r7, sp, #0
+ 80011fa:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80011fc:	2414      	movs	r4, #20
+ 80011fe:	193b      	adds	r3, r7, r4
+ 8001200:	0018      	movs	r0, r3
+ 8001202:	2314      	movs	r3, #20
+ 8001204:	001a      	movs	r2, r3
+ 8001206:	2100      	movs	r1, #0
+ 8001208:	f006 fad9 	bl	80077be <memset>
+  if(hlptim->Instance==LPTIM1)
+ 800120c:	687b      	ldr	r3, [r7, #4]
+ 800120e:	681b      	ldr	r3, [r3, #0]
+ 8001210:	4a28      	ldr	r2, [pc, #160]	; (80012b4 <HAL_LPTIM_MspInit+0xc0>)
+ 8001212:	4293      	cmp	r3, r2
+ 8001214:	d14a      	bne.n	80012ac <HAL_LPTIM_MspInit+0xb8>
+  {
+  /* USER CODE BEGIN LPTIM1_MspInit 0 */
+
+  /* USER CODE END LPTIM1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPTIM1_CLK_ENABLE();
+ 8001216:	4b28      	ldr	r3, [pc, #160]	; (80012b8 <HAL_LPTIM_MspInit+0xc4>)
+ 8001218:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 800121a:	4b27      	ldr	r3, [pc, #156]	; (80012b8 <HAL_LPTIM_MspInit+0xc4>)
+ 800121c:	2180      	movs	r1, #128	; 0x80
+ 800121e:	0609      	lsls	r1, r1, #24
+ 8001220:	430a      	orrs	r2, r1
+ 8001222:	639a      	str	r2, [r3, #56]	; 0x38
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 8001224:	4b24      	ldr	r3, [pc, #144]	; (80012b8 <HAL_LPTIM_MspInit+0xc4>)
+ 8001226:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8001228:	4b23      	ldr	r3, [pc, #140]	; (80012b8 <HAL_LPTIM_MspInit+0xc4>)
+ 800122a:	2104      	movs	r1, #4
+ 800122c:	430a      	orrs	r2, r1
+ 800122e:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8001230:	4b21      	ldr	r3, [pc, #132]	; (80012b8 <HAL_LPTIM_MspInit+0xc4>)
+ 8001232:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8001234:	2204      	movs	r2, #4
+ 8001236:	4013      	ands	r3, r2
+ 8001238:	613b      	str	r3, [r7, #16]
+ 800123a:	693b      	ldr	r3, [r7, #16]
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 800123c:	4b1e      	ldr	r3, [pc, #120]	; (80012b8 <HAL_LPTIM_MspInit+0xc4>)
+ 800123e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8001240:	4b1d      	ldr	r3, [pc, #116]	; (80012b8 <HAL_LPTIM_MspInit+0xc4>)
+ 8001242:	2101      	movs	r1, #1
+ 8001244:	430a      	orrs	r2, r1
+ 8001246:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8001248:	4b1b      	ldr	r3, [pc, #108]	; (80012b8 <HAL_LPTIM_MspInit+0xc4>)
+ 800124a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800124c:	2201      	movs	r2, #1
+ 800124e:	4013      	ands	r3, r2
+ 8001250:	60fb      	str	r3, [r7, #12]
+ 8001252:	68fb      	ldr	r3, [r7, #12]
+    /**LPTIM1 GPIO Configuration
+    PC0     ------> LPTIM1_IN1
+    PA5     ------> LPTIM1_IN2
+    */
+    GPIO_InitStruct.Pin = ENC_PHA_GAUCHE_Pin;
+ 8001254:	193b      	adds	r3, r7, r4
+ 8001256:	2201      	movs	r2, #1
+ 8001258:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800125a:	193b      	adds	r3, r7, r4
+ 800125c:	2202      	movs	r2, #2
+ 800125e:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001260:	193b      	adds	r3, r7, r4
+ 8001262:	2200      	movs	r2, #0
+ 8001264:	609a      	str	r2, [r3, #8]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001266:	193b      	adds	r3, r7, r4
+ 8001268:	2200      	movs	r2, #0
+ 800126a:	60da      	str	r2, [r3, #12]
+    GPIO_InitStruct.Alternate = GPIO_AF0_LPTIM1;
+ 800126c:	193b      	adds	r3, r7, r4
+ 800126e:	2200      	movs	r2, #0
+ 8001270:	611a      	str	r2, [r3, #16]
+    HAL_GPIO_Init(ENC_PHA_GAUCHE_GPIO_Port, &GPIO_InitStruct);
+ 8001272:	193b      	adds	r3, r7, r4
+ 8001274:	4a11      	ldr	r2, [pc, #68]	; (80012bc <HAL_LPTIM_MspInit+0xc8>)
+ 8001276:	0019      	movs	r1, r3
+ 8001278:	0010      	movs	r0, r2
+ 800127a:	f000 ffd3 	bl	8002224 <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = ENC_PHB_GAUCHE_Pin;
+ 800127e:	0021      	movs	r1, r4
+ 8001280:	187b      	adds	r3, r7, r1
+ 8001282:	2220      	movs	r2, #32
+ 8001284:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001286:	187b      	adds	r3, r7, r1
+ 8001288:	2202      	movs	r2, #2
+ 800128a:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800128c:	187b      	adds	r3, r7, r1
+ 800128e:	2200      	movs	r2, #0
+ 8001290:	609a      	str	r2, [r3, #8]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001292:	187b      	adds	r3, r7, r1
+ 8001294:	2200      	movs	r2, #0
+ 8001296:	60da      	str	r2, [r3, #12]
+    GPIO_InitStruct.Alternate = GPIO_AF1_LPTIM1;
+ 8001298:	187b      	adds	r3, r7, r1
+ 800129a:	2201      	movs	r2, #1
+ 800129c:	611a      	str	r2, [r3, #16]
+    HAL_GPIO_Init(ENC_PHB_GAUCHE_GPIO_Port, &GPIO_InitStruct);
+ 800129e:	187a      	adds	r2, r7, r1
+ 80012a0:	23a0      	movs	r3, #160	; 0xa0
+ 80012a2:	05db      	lsls	r3, r3, #23
+ 80012a4:	0011      	movs	r1, r2
+ 80012a6:	0018      	movs	r0, r3
+ 80012a8:	f000 ffbc 	bl	8002224 <HAL_GPIO_Init>
+  /* USER CODE BEGIN LPTIM1_MspInit 1 */
+
+  /* USER CODE END LPTIM1_MspInit 1 */
+  }
+
+}
+ 80012ac:	46c0      	nop			; (mov r8, r8)
+ 80012ae:	46bd      	mov	sp, r7
+ 80012b0:	b00b      	add	sp, #44	; 0x2c
+ 80012b2:	bd90      	pop	{r4, r7, pc}
+ 80012b4:	40007c00 	.word	0x40007c00
+ 80012b8:	40021000 	.word	0x40021000
+ 80012bc:	50000800 	.word	0x50000800
+
+080012c0 <HAL_UART_MspInit>:
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ 80012c0:	b590      	push	{r4, r7, lr}
+ 80012c2:	b089      	sub	sp, #36	; 0x24
+ 80012c4:	af00      	add	r7, sp, #0
+ 80012c6:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80012c8:	240c      	movs	r4, #12
+ 80012ca:	193b      	adds	r3, r7, r4
+ 80012cc:	0018      	movs	r0, r3
+ 80012ce:	2314      	movs	r3, #20
+ 80012d0:	001a      	movs	r2, r3
+ 80012d2:	2100      	movs	r1, #0
+ 80012d4:	f006 fa73 	bl	80077be <memset>
+  if(huart->Instance==LPUART1)
+ 80012d8:	687b      	ldr	r3, [r7, #4]
+ 80012da:	681b      	ldr	r3, [r3, #0]
+ 80012dc:	4a46      	ldr	r2, [pc, #280]	; (80013f8 <HAL_UART_MspInit+0x138>)
+ 80012de:	4293      	cmp	r3, r2
+ 80012e0:	d000      	beq.n	80012e4 <HAL_UART_MspInit+0x24>
+ 80012e2:	e085      	b.n	80013f0 <HAL_UART_MspInit+0x130>
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+ 80012e4:	4b45      	ldr	r3, [pc, #276]	; (80013fc <HAL_UART_MspInit+0x13c>)
+ 80012e6:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 80012e8:	4b44      	ldr	r3, [pc, #272]	; (80013fc <HAL_UART_MspInit+0x13c>)
+ 80012ea:	2180      	movs	r1, #128	; 0x80
+ 80012ec:	02c9      	lsls	r1, r1, #11
+ 80012ee:	430a      	orrs	r2, r1
+ 80012f0:	639a      	str	r2, [r3, #56]	; 0x38
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 80012f2:	4b42      	ldr	r3, [pc, #264]	; (80013fc <HAL_UART_MspInit+0x13c>)
+ 80012f4:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80012f6:	4b41      	ldr	r3, [pc, #260]	; (80013fc <HAL_UART_MspInit+0x13c>)
+ 80012f8:	2102      	movs	r1, #2
+ 80012fa:	430a      	orrs	r2, r1
+ 80012fc:	62da      	str	r2, [r3, #44]	; 0x2c
+ 80012fe:	4b3f      	ldr	r3, [pc, #252]	; (80013fc <HAL_UART_MspInit+0x13c>)
+ 8001300:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8001302:	2202      	movs	r2, #2
+ 8001304:	4013      	ands	r3, r2
+ 8001306:	60bb      	str	r3, [r7, #8]
+ 8001308:	68bb      	ldr	r3, [r7, #8]
+    /**LPUART1 GPIO Configuration
+    PB10     ------> LPUART1_TX
+    PB11     ------> LPUART1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
+ 800130a:	193b      	adds	r3, r7, r4
+ 800130c:	22c0      	movs	r2, #192	; 0xc0
+ 800130e:	0112      	lsls	r2, r2, #4
+ 8001310:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001312:	0021      	movs	r1, r4
+ 8001314:	187b      	adds	r3, r7, r1
+ 8001316:	2202      	movs	r2, #2
+ 8001318:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800131a:	187b      	adds	r3, r7, r1
+ 800131c:	2200      	movs	r2, #0
+ 800131e:	609a      	str	r2, [r3, #8]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8001320:	187b      	adds	r3, r7, r1
+ 8001322:	2203      	movs	r2, #3
+ 8001324:	60da      	str	r2, [r3, #12]
+    GPIO_InitStruct.Alternate = GPIO_AF6_LPUART1;
+ 8001326:	187b      	adds	r3, r7, r1
+ 8001328:	2206      	movs	r2, #6
+ 800132a:	611a      	str	r2, [r3, #16]
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 800132c:	187b      	adds	r3, r7, r1
+ 800132e:	4a34      	ldr	r2, [pc, #208]	; (8001400 <HAL_UART_MspInit+0x140>)
+ 8001330:	0019      	movs	r1, r3
+ 8001332:	0010      	movs	r0, r2
+ 8001334:	f000 ff76 	bl	8002224 <HAL_GPIO_Init>
+
+    /* LPUART1 DMA Init */
+    /* LPUART1_RX Init */
+    hdma_lpuart1_rx.Instance = DMA1_Channel3;
+ 8001338:	4b32      	ldr	r3, [pc, #200]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 800133a:	4a33      	ldr	r2, [pc, #204]	; (8001408 <HAL_UART_MspInit+0x148>)
+ 800133c:	601a      	str	r2, [r3, #0]
+    hdma_lpuart1_rx.Init.Request = DMA_REQUEST_5;
+ 800133e:	4b31      	ldr	r3, [pc, #196]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 8001340:	2205      	movs	r2, #5
+ 8001342:	605a      	str	r2, [r3, #4]
+    hdma_lpuart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ 8001344:	4b2f      	ldr	r3, [pc, #188]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 8001346:	2200      	movs	r2, #0
+ 8001348:	609a      	str	r2, [r3, #8]
+    hdma_lpuart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 800134a:	4b2e      	ldr	r3, [pc, #184]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 800134c:	2200      	movs	r2, #0
+ 800134e:	60da      	str	r2, [r3, #12]
+    hdma_lpuart1_rx.Init.MemInc = DMA_MINC_ENABLE;
+ 8001350:	4b2c      	ldr	r3, [pc, #176]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 8001352:	2280      	movs	r2, #128	; 0x80
+ 8001354:	611a      	str	r2, [r3, #16]
+    hdma_lpuart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 8001356:	4b2b      	ldr	r3, [pc, #172]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 8001358:	2200      	movs	r2, #0
+ 800135a:	615a      	str	r2, [r3, #20]
+    hdma_lpuart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 800135c:	4b29      	ldr	r3, [pc, #164]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 800135e:	2200      	movs	r2, #0
+ 8001360:	619a      	str	r2, [r3, #24]
+    hdma_lpuart1_rx.Init.Mode = DMA_NORMAL;
+ 8001362:	4b28      	ldr	r3, [pc, #160]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 8001364:	2200      	movs	r2, #0
+ 8001366:	61da      	str	r2, [r3, #28]
+    hdma_lpuart1_rx.Init.Priority = DMA_PRIORITY_HIGH;
+ 8001368:	4b26      	ldr	r3, [pc, #152]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 800136a:	2280      	movs	r2, #128	; 0x80
+ 800136c:	0192      	lsls	r2, r2, #6
+ 800136e:	621a      	str	r2, [r3, #32]
+    if (HAL_DMA_Init(&hdma_lpuart1_rx) != HAL_OK)
+ 8001370:	4b24      	ldr	r3, [pc, #144]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 8001372:	0018      	movs	r0, r3
+ 8001374:	f000 fda8 	bl	8001ec8 <HAL_DMA_Init>
+ 8001378:	1e03      	subs	r3, r0, #0
+ 800137a:	d001      	beq.n	8001380 <HAL_UART_MspInit+0xc0>
+    {
+      Error_Handler();
+ 800137c:	f7ff fe5a 	bl	8001034 <Error_Handler>
+    }
+
+    __HAL_LINKDMA(huart,hdmarx,hdma_lpuart1_rx);
+ 8001380:	687b      	ldr	r3, [r7, #4]
+ 8001382:	4a20      	ldr	r2, [pc, #128]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 8001384:	671a      	str	r2, [r3, #112]	; 0x70
+ 8001386:	4b1f      	ldr	r3, [pc, #124]	; (8001404 <HAL_UART_MspInit+0x144>)
+ 8001388:	687a      	ldr	r2, [r7, #4]
+ 800138a:	629a      	str	r2, [r3, #40]	; 0x28
+
+    /* LPUART1_TX Init */
+    hdma_lpuart1_tx.Instance = DMA1_Channel2;
+ 800138c:	4b1f      	ldr	r3, [pc, #124]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 800138e:	4a20      	ldr	r2, [pc, #128]	; (8001410 <HAL_UART_MspInit+0x150>)
+ 8001390:	601a      	str	r2, [r3, #0]
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_5;
+ 8001392:	4b1e      	ldr	r3, [pc, #120]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 8001394:	2205      	movs	r2, #5
+ 8001396:	605a      	str	r2, [r3, #4]
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 8001398:	4b1c      	ldr	r3, [pc, #112]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 800139a:	2210      	movs	r2, #16
+ 800139c:	609a      	str	r2, [r3, #8]
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 800139e:	4b1b      	ldr	r3, [pc, #108]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013a0:	2200      	movs	r2, #0
+ 80013a2:	60da      	str	r2, [r3, #12]
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 80013a4:	4b19      	ldr	r3, [pc, #100]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013a6:	2280      	movs	r2, #128	; 0x80
+ 80013a8:	611a      	str	r2, [r3, #16]
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 80013aa:	4b18      	ldr	r3, [pc, #96]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013ac:	2200      	movs	r2, #0
+ 80013ae:	615a      	str	r2, [r3, #20]
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 80013b0:	4b16      	ldr	r3, [pc, #88]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013b2:	2200      	movs	r2, #0
+ 80013b4:	619a      	str	r2, [r3, #24]
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+ 80013b6:	4b15      	ldr	r3, [pc, #84]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013b8:	2200      	movs	r2, #0
+ 80013ba:	61da      	str	r2, [r3, #28]
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_HIGH;
+ 80013bc:	4b13      	ldr	r3, [pc, #76]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013be:	2280      	movs	r2, #128	; 0x80
+ 80013c0:	0192      	lsls	r2, r2, #6
+ 80013c2:	621a      	str	r2, [r3, #32]
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+ 80013c4:	4b11      	ldr	r3, [pc, #68]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013c6:	0018      	movs	r0, r3
+ 80013c8:	f000 fd7e 	bl	8001ec8 <HAL_DMA_Init>
+ 80013cc:	1e03      	subs	r3, r0, #0
+ 80013ce:	d001      	beq.n	80013d4 <HAL_UART_MspInit+0x114>
+    {
+      Error_Handler();
+ 80013d0:	f7ff fe30 	bl	8001034 <Error_Handler>
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+ 80013d4:	687b      	ldr	r3, [r7, #4]
+ 80013d6:	4a0d      	ldr	r2, [pc, #52]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013d8:	66da      	str	r2, [r3, #108]	; 0x6c
+ 80013da:	4b0c      	ldr	r3, [pc, #48]	; (800140c <HAL_UART_MspInit+0x14c>)
+ 80013dc:	687a      	ldr	r2, [r7, #4]
+ 80013de:	629a      	str	r2, [r3, #40]	; 0x28
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 3, 0);
+ 80013e0:	2200      	movs	r2, #0
+ 80013e2:	2103      	movs	r1, #3
+ 80013e4:	201d      	movs	r0, #29
+ 80013e6:	f000 fd3d 	bl	8001e64 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+ 80013ea:	201d      	movs	r0, #29
+ 80013ec:	f000 fd4f 	bl	8001e8e <HAL_NVIC_EnableIRQ>
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+
+}
+ 80013f0:	46c0      	nop			; (mov r8, r8)
+ 80013f2:	46bd      	mov	sp, r7
+ 80013f4:	b009      	add	sp, #36	; 0x24
+ 80013f6:	bd90      	pop	{r4, r7, pc}
+ 80013f8:	40004800 	.word	0x40004800
+ 80013fc:	40021000 	.word	0x40021000
+ 8001400:	50000400 	.word	0x50000400
+ 8001404:	20001830 	.word	0x20001830
+ 8001408:	40020030 	.word	0x40020030
+ 800140c:	200017e8 	.word	0x200017e8
+ 8001410:	4002001c 	.word	0x4002001c
+
+08001414 <HAL_TIM_Base_MspInit>:
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+ 8001414:	b580      	push	{r7, lr}
+ 8001416:	b082      	sub	sp, #8
+ 8001418:	af00      	add	r7, sp, #0
+ 800141a:	6078      	str	r0, [r7, #4]
+  if(htim_base->Instance==TIM2)
+ 800141c:	687b      	ldr	r3, [r7, #4]
+ 800141e:	681a      	ldr	r2, [r3, #0]
+ 8001420:	2380      	movs	r3, #128	; 0x80
+ 8001422:	05db      	lsls	r3, r3, #23
+ 8001424:	429a      	cmp	r2, r3
+ 8001426:	d105      	bne.n	8001434 <HAL_TIM_Base_MspInit+0x20>
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+ 8001428:	4b04      	ldr	r3, [pc, #16]	; (800143c <HAL_TIM_Base_MspInit+0x28>)
+ 800142a:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 800142c:	4b03      	ldr	r3, [pc, #12]	; (800143c <HAL_TIM_Base_MspInit+0x28>)
+ 800142e:	2101      	movs	r1, #1
+ 8001430:	430a      	orrs	r2, r1
+ 8001432:	639a      	str	r2, [r3, #56]	; 0x38
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+
+}
+ 8001434:	46c0      	nop			; (mov r8, r8)
+ 8001436:	46bd      	mov	sp, r7
+ 8001438:	b002      	add	sp, #8
+ 800143a:	bd80      	pop	{r7, pc}
+ 800143c:	40021000 	.word	0x40021000
+
+08001440 <HAL_TIM_Encoder_MspInit>:
+* This function configures the hardware resources used in this example
+* @param htim_encoder: TIM_Encoder handle pointer
+* @retval None
+*/
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
+{
+ 8001440:	b590      	push	{r4, r7, lr}
+ 8001442:	b089      	sub	sp, #36	; 0x24
+ 8001444:	af00      	add	r7, sp, #0
+ 8001446:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8001448:	240c      	movs	r4, #12
+ 800144a:	193b      	adds	r3, r7, r4
+ 800144c:	0018      	movs	r0, r3
+ 800144e:	2314      	movs	r3, #20
+ 8001450:	001a      	movs	r2, r3
+ 8001452:	2100      	movs	r1, #0
+ 8001454:	f006 f9b3 	bl	80077be <memset>
+  if(htim_encoder->Instance==TIM21)
+ 8001458:	687b      	ldr	r3, [r7, #4]
+ 800145a:	681b      	ldr	r3, [r3, #0]
+ 800145c:	4a17      	ldr	r2, [pc, #92]	; (80014bc <HAL_TIM_Encoder_MspInit+0x7c>)
+ 800145e:	4293      	cmp	r3, r2
+ 8001460:	d128      	bne.n	80014b4 <HAL_TIM_Encoder_MspInit+0x74>
+  {
+  /* USER CODE BEGIN TIM21_MspInit 0 */
+
+  /* USER CODE END TIM21_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM21_CLK_ENABLE();
+ 8001462:	4b17      	ldr	r3, [pc, #92]	; (80014c0 <HAL_TIM_Encoder_MspInit+0x80>)
+ 8001464:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8001466:	4b16      	ldr	r3, [pc, #88]	; (80014c0 <HAL_TIM_Encoder_MspInit+0x80>)
+ 8001468:	2104      	movs	r1, #4
+ 800146a:	430a      	orrs	r2, r1
+ 800146c:	635a      	str	r2, [r3, #52]	; 0x34
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 800146e:	4b14      	ldr	r3, [pc, #80]	; (80014c0 <HAL_TIM_Encoder_MspInit+0x80>)
+ 8001470:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8001472:	4b13      	ldr	r3, [pc, #76]	; (80014c0 <HAL_TIM_Encoder_MspInit+0x80>)
+ 8001474:	2101      	movs	r1, #1
+ 8001476:	430a      	orrs	r2, r1
+ 8001478:	62da      	str	r2, [r3, #44]	; 0x2c
+ 800147a:	4b11      	ldr	r3, [pc, #68]	; (80014c0 <HAL_TIM_Encoder_MspInit+0x80>)
+ 800147c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800147e:	2201      	movs	r2, #1
+ 8001480:	4013      	ands	r3, r2
+ 8001482:	60bb      	str	r3, [r7, #8]
+ 8001484:	68bb      	ldr	r3, [r7, #8]
+    /**TIM21 GPIO Configuration
+    PA2     ------> TIM21_CH1
+    PA3     ------> TIM21_CH2
+    */
+    GPIO_InitStruct.Pin = ENC_PHA_DROIT_Pin|ENC_PHB_DROIT_Pin;
+ 8001486:	0021      	movs	r1, r4
+ 8001488:	187b      	adds	r3, r7, r1
+ 800148a:	220c      	movs	r2, #12
+ 800148c:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800148e:	187b      	adds	r3, r7, r1
+ 8001490:	2202      	movs	r2, #2
+ 8001492:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001494:	187b      	adds	r3, r7, r1
+ 8001496:	2200      	movs	r2, #0
+ 8001498:	609a      	str	r2, [r3, #8]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 800149a:	187b      	adds	r3, r7, r1
+ 800149c:	2200      	movs	r2, #0
+ 800149e:	60da      	str	r2, [r3, #12]
+    GPIO_InitStruct.Alternate = GPIO_AF0_TIM21;
+ 80014a0:	187b      	adds	r3, r7, r1
+ 80014a2:	2200      	movs	r2, #0
+ 80014a4:	611a      	str	r2, [r3, #16]
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80014a6:	187a      	adds	r2, r7, r1
+ 80014a8:	23a0      	movs	r3, #160	; 0xa0
+ 80014aa:	05db      	lsls	r3, r3, #23
+ 80014ac:	0011      	movs	r1, r2
+ 80014ae:	0018      	movs	r0, r3
+ 80014b0:	f000 feb8 	bl	8002224 <HAL_GPIO_Init>
+  /* USER CODE BEGIN TIM21_MspInit 1 */
+
+  /* USER CODE END TIM21_MspInit 1 */
+  }
+
+}
+ 80014b4:	46c0      	nop			; (mov r8, r8)
+ 80014b6:	46bd      	mov	sp, r7
+ 80014b8:	b009      	add	sp, #36	; 0x24
+ 80014ba:	bd90      	pop	{r4, r7, pc}
+ 80014bc:	40010800 	.word	0x40010800
+ 80014c0:	40021000 	.word	0x40021000
+
+080014c4 <HAL_TIM_MspPostInit>:
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+ 80014c4:	b590      	push	{r4, r7, lr}
+ 80014c6:	b08b      	sub	sp, #44	; 0x2c
+ 80014c8:	af00      	add	r7, sp, #0
+ 80014ca:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80014cc:	2414      	movs	r4, #20
+ 80014ce:	193b      	adds	r3, r7, r4
+ 80014d0:	0018      	movs	r0, r3
+ 80014d2:	2314      	movs	r3, #20
+ 80014d4:	001a      	movs	r2, r3
+ 80014d6:	2100      	movs	r1, #0
+ 80014d8:	f006 f971 	bl	80077be <memset>
+  if(htim->Instance==TIM2)
+ 80014dc:	687b      	ldr	r3, [r7, #4]
+ 80014de:	681a      	ldr	r2, [r3, #0]
+ 80014e0:	2380      	movs	r3, #128	; 0x80
+ 80014e2:	05db      	lsls	r3, r3, #23
+ 80014e4:	429a      	cmp	r2, r3
+ 80014e6:	d15a      	bne.n	800159e <HAL_TIM_MspPostInit+0xda>
+  {
+  /* USER CODE BEGIN TIM2_MspPostInit 0 */
+
+  /* USER CODE END TIM2_MspPostInit 0 */
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80014e8:	4b2f      	ldr	r3, [pc, #188]	; (80015a8 <HAL_TIM_MspPostInit+0xe4>)
+ 80014ea:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80014ec:	4b2e      	ldr	r3, [pc, #184]	; (80015a8 <HAL_TIM_MspPostInit+0xe4>)
+ 80014ee:	2101      	movs	r1, #1
+ 80014f0:	430a      	orrs	r2, r1
+ 80014f2:	62da      	str	r2, [r3, #44]	; 0x2c
+ 80014f4:	4b2c      	ldr	r3, [pc, #176]	; (80015a8 <HAL_TIM_MspPostInit+0xe4>)
+ 80014f6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80014f8:	2201      	movs	r2, #1
+ 80014fa:	4013      	ands	r3, r2
+ 80014fc:	613b      	str	r3, [r7, #16]
+ 80014fe:	693b      	ldr	r3, [r7, #16]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8001500:	4b29      	ldr	r3, [pc, #164]	; (80015a8 <HAL_TIM_MspPostInit+0xe4>)
+ 8001502:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8001504:	4b28      	ldr	r3, [pc, #160]	; (80015a8 <HAL_TIM_MspPostInit+0xe4>)
+ 8001506:	2102      	movs	r1, #2
+ 8001508:	430a      	orrs	r2, r1
+ 800150a:	62da      	str	r2, [r3, #44]	; 0x2c
+ 800150c:	4b26      	ldr	r3, [pc, #152]	; (80015a8 <HAL_TIM_MspPostInit+0xe4>)
+ 800150e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8001510:	2202      	movs	r2, #2
+ 8001512:	4013      	ands	r3, r2
+ 8001514:	60fb      	str	r3, [r7, #12]
+ 8001516:	68fb      	ldr	r3, [r7, #12]
+    PA1     ------> TIM2_CH2
+    PB0     ------> TIM2_CH3
+    PB1     ------> TIM2_CH4
+    PA8     ------> TIM2_CH1
+    */
+    GPIO_InitStruct.Pin = PWM_B_GAUCHE_Pin;
+ 8001518:	193b      	adds	r3, r7, r4
+ 800151a:	2202      	movs	r2, #2
+ 800151c:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800151e:	193b      	adds	r3, r7, r4
+ 8001520:	2202      	movs	r2, #2
+ 8001522:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001524:	193b      	adds	r3, r7, r4
+ 8001526:	2200      	movs	r2, #0
+ 8001528:	609a      	str	r2, [r3, #8]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 800152a:	193b      	adds	r3, r7, r4
+ 800152c:	2200      	movs	r2, #0
+ 800152e:	60da      	str	r2, [r3, #12]
+    GPIO_InitStruct.Alternate = GPIO_AF2_TIM2;
+ 8001530:	193b      	adds	r3, r7, r4
+ 8001532:	2202      	movs	r2, #2
+ 8001534:	611a      	str	r2, [r3, #16]
+    HAL_GPIO_Init(PWM_B_GAUCHE_GPIO_Port, &GPIO_InitStruct);
+ 8001536:	193a      	adds	r2, r7, r4
+ 8001538:	23a0      	movs	r3, #160	; 0xa0
+ 800153a:	05db      	lsls	r3, r3, #23
+ 800153c:	0011      	movs	r1, r2
+ 800153e:	0018      	movs	r0, r3
+ 8001540:	f000 fe70 	bl	8002224 <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = PWM_A_DROIT_Pin|PWM_B_DROIT_Pin;
+ 8001544:	193b      	adds	r3, r7, r4
+ 8001546:	2203      	movs	r2, #3
+ 8001548:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800154a:	193b      	adds	r3, r7, r4
+ 800154c:	2202      	movs	r2, #2
+ 800154e:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001550:	193b      	adds	r3, r7, r4
+ 8001552:	2200      	movs	r2, #0
+ 8001554:	609a      	str	r2, [r3, #8]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001556:	193b      	adds	r3, r7, r4
+ 8001558:	2200      	movs	r2, #0
+ 800155a:	60da      	str	r2, [r3, #12]
+    GPIO_InitStruct.Alternate = GPIO_AF5_TIM2;
+ 800155c:	193b      	adds	r3, r7, r4
+ 800155e:	2205      	movs	r2, #5
+ 8001560:	611a      	str	r2, [r3, #16]
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001562:	193b      	adds	r3, r7, r4
+ 8001564:	4a11      	ldr	r2, [pc, #68]	; (80015ac <HAL_TIM_MspPostInit+0xe8>)
+ 8001566:	0019      	movs	r1, r3
+ 8001568:	0010      	movs	r0, r2
+ 800156a:	f000 fe5b 	bl	8002224 <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = PWM_A_GAUCHE_Pin;
+ 800156e:	0021      	movs	r1, r4
+ 8001570:	187b      	adds	r3, r7, r1
+ 8001572:	2280      	movs	r2, #128	; 0x80
+ 8001574:	0052      	lsls	r2, r2, #1
+ 8001576:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001578:	187b      	adds	r3, r7, r1
+ 800157a:	2202      	movs	r2, #2
+ 800157c:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800157e:	187b      	adds	r3, r7, r1
+ 8001580:	2200      	movs	r2, #0
+ 8001582:	609a      	str	r2, [r3, #8]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001584:	187b      	adds	r3, r7, r1
+ 8001586:	2200      	movs	r2, #0
+ 8001588:	60da      	str	r2, [r3, #12]
+    GPIO_InitStruct.Alternate = GPIO_AF5_TIM2;
+ 800158a:	187b      	adds	r3, r7, r1
+ 800158c:	2205      	movs	r2, #5
+ 800158e:	611a      	str	r2, [r3, #16]
+    HAL_GPIO_Init(PWM_A_GAUCHE_GPIO_Port, &GPIO_InitStruct);
+ 8001590:	187a      	adds	r2, r7, r1
+ 8001592:	23a0      	movs	r3, #160	; 0xa0
+ 8001594:	05db      	lsls	r3, r3, #23
+ 8001596:	0011      	movs	r1, r2
+ 8001598:	0018      	movs	r0, r3
+ 800159a:	f000 fe43 	bl	8002224 <HAL_GPIO_Init>
+  /* USER CODE BEGIN TIM2_MspPostInit 1 */
+
+  /* USER CODE END TIM2_MspPostInit 1 */
+  }
+
+}
+ 800159e:	46c0      	nop			; (mov r8, r8)
+ 80015a0:	46bd      	mov	sp, r7
+ 80015a2:	b00b      	add	sp, #44	; 0x2c
+ 80015a4:	bd90      	pop	{r4, r7, pc}
+ 80015a6:	46c0      	nop			; (mov r8, r8)
+ 80015a8:	40021000 	.word	0x40021000
+ 80015ac:	50000400 	.word	0x50000400
+
+080015b0 <NMI_Handler>:
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable Interrupt.
+  */
+void NMI_Handler(void)
+{
+ 80015b0:	b580      	push	{r7, lr}
+ 80015b2:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  while (1)
+ 80015b4:	e7fe      	b.n	80015b4 <NMI_Handler+0x4>
+
+080015b6 <HardFault_Handler>:
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+ 80015b6:	b580      	push	{r7, lr}
+ 80015b8:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+ 80015ba:	e7fe      	b.n	80015ba <HardFault_Handler+0x4>
+
+080015bc <SysTick_Handler>:
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+ 80015bc:	b580      	push	{r7, lr}
+ 80015be:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+ 80015c0:	f000 f8d8 	bl	8001774 <HAL_IncTick>
+#if (INCLUDE_xTaskGetSchedulerState == 1 )
+  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
+ 80015c4:	f005 f930 	bl	8006828 <xTaskGetSchedulerState>
+ 80015c8:	0003      	movs	r3, r0
+ 80015ca:	2b01      	cmp	r3, #1
+ 80015cc:	d001      	beq.n	80015d2 <SysTick_Handler+0x16>
+  {
+#endif /* INCLUDE_xTaskGetSchedulerState */
+  xPortSysTickHandler();
+ 80015ce:	f005 fe03 	bl	80071d8 <xPortSysTickHandler>
+  }
+#endif /* INCLUDE_xTaskGetSchedulerState */
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+ 80015d2:	46c0      	nop			; (mov r8, r8)
+ 80015d4:	46bd      	mov	sp, r7
+ 80015d6:	bd80      	pop	{r7, pc}
+
+080015d8 <EXTI2_3_IRQHandler>:
+
+/**
+  * @brief This function handles EXTI line 2 and line 3 interrupts.
+  */
+void EXTI2_3_IRQHandler(void)
+{
+ 80015d8:	b580      	push	{r7, lr}
+ 80015da:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN EXTI2_3_IRQn 0 */
+
+  /* USER CODE END EXTI2_3_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
+ 80015dc:	2008      	movs	r0, #8
+ 80015de:	f000 ffad 	bl	800253c <HAL_GPIO_EXTI_IRQHandler>
+  /* USER CODE BEGIN EXTI2_3_IRQn 1 */
+
+  /* USER CODE END EXTI2_3_IRQn 1 */
+}
+ 80015e2:	46c0      	nop			; (mov r8, r8)
+ 80015e4:	46bd      	mov	sp, r7
+ 80015e6:	bd80      	pop	{r7, pc}
+
+080015e8 <DMA1_Channel2_3_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 channel 2 and channel 3 interrupts.
+  */
+void DMA1_Channel2_3_IRQHandler(void)
+{
+ 80015e8:	b580      	push	{r7, lr}
+ 80015ea:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel2_3_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+ 80015ec:	4b05      	ldr	r3, [pc, #20]	; (8001604 <DMA1_Channel2_3_IRQHandler+0x1c>)
+ 80015ee:	0018      	movs	r0, r3
+ 80015f0:	f000 fd69 	bl	80020c6 <HAL_DMA_IRQHandler>
+  HAL_DMA_IRQHandler(&hdma_lpuart1_rx);
+ 80015f4:	4b04      	ldr	r3, [pc, #16]	; (8001608 <DMA1_Channel2_3_IRQHandler+0x20>)
+ 80015f6:	0018      	movs	r0, r3
+ 80015f8:	f000 fd65 	bl	80020c6 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel2_3_IRQn 1 */
+}
+ 80015fc:	46c0      	nop			; (mov r8, r8)
+ 80015fe:	46bd      	mov	sp, r7
+ 8001600:	bd80      	pop	{r7, pc}
+ 8001602:	46c0      	nop			; (mov r8, r8)
+ 8001604:	200017e8 	.word	0x200017e8
+ 8001608:	20001830 	.word	0x20001830
+
+0800160c <ADC1_IRQHandler>:
+
+/**
+  * @brief This function handles ADC global interrupt.
+  */
+void ADC1_IRQHandler(void)
+{
+ 800160c:	b580      	push	{r7, lr}
+ 800160e:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN ADC1_IRQn 0 */
+
+  /* USER CODE END ADC1_IRQn 0 */
+  HAL_ADC_IRQHandler(&hadc);
+ 8001610:	4b03      	ldr	r3, [pc, #12]	; (8001620 <ADC1_IRQHandler+0x14>)
+ 8001612:	0018      	movs	r0, r3
+ 8001614:	f000 fa3e 	bl	8001a94 <HAL_ADC_IRQHandler>
+  /* USER CODE BEGIN ADC1_IRQn 1 */
+
+  /* USER CODE END ADC1_IRQn 1 */
+}
+ 8001618:	46c0      	nop			; (mov r8, r8)
+ 800161a:	46bd      	mov	sp, r7
+ 800161c:	bd80      	pop	{r7, pc}
+ 800161e:	46c0      	nop			; (mov r8, r8)
+ 8001620:	200018b8 	.word	0x200018b8
+
+08001624 <LPUART1_IRQHandler>:
+
+/**
+  * @brief This function handles LPUART1 global interrupt / LPUART1 wake-up interrupt through EXTI line 28.
+  */
+void LPUART1_IRQHandler(void)
+{
+ 8001624:	b580      	push	{r7, lr}
+ 8001626:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+ 8001628:	4b03      	ldr	r3, [pc, #12]	; (8001638 <LPUART1_IRQHandler+0x14>)
+ 800162a:	0018      	movs	r0, r3
+ 800162c:	f002 fc4c 	bl	8003ec8 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+ 8001630:	46c0      	nop			; (mov r8, r8)
+ 8001632:	46bd      	mov	sp, r7
+ 8001634:	bd80      	pop	{r7, pc}
+ 8001636:	46c0      	nop			; (mov r8, r8)
+ 8001638:	20001734 	.word	0x20001734
+
+0800163c <SystemInit>:
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+ 800163c:	b580      	push	{r7, lr}
+ 800163e:	af00      	add	r7, sp, #0
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined (USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+ 8001640:	46c0      	nop			; (mov r8, r8)
+ 8001642:	46bd      	mov	sp, r7
+ 8001644:	bd80      	pop	{r7, pc}
+	...
+
+08001648 <Reset_Handler>:
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+   ldr   r0, =_estack
+ 8001648:	4813      	ldr	r0, [pc, #76]	; (8001698 <LoopForever+0x2>)
+   mov   sp, r0          /* set stack pointer */
+ 800164a:	4685      	mov	sp, r0
+
+/*Check if boot space corresponds to system memory*/
+
+    LDR R0,=0x00000004
+ 800164c:	4813      	ldr	r0, [pc, #76]	; (800169c <LoopForever+0x6>)
+    LDR R1, [R0]
+ 800164e:	6801      	ldr	r1, [r0, #0]
+    LSRS R1, R1, #24
+ 8001650:	0e09      	lsrs	r1, r1, #24
+    LDR R2,=0x1F
+ 8001652:	4a13      	ldr	r2, [pc, #76]	; (80016a0 <LoopForever+0xa>)
+    CMP R1, R2
+ 8001654:	4291      	cmp	r1, r2
+    BNE ApplicationStart
+ 8001656:	d105      	bne.n	8001664 <ApplicationStart>
+
+ /*SYSCFG clock enable*/
+    LDR R0,=0x40021034
+ 8001658:	4812      	ldr	r0, [pc, #72]	; (80016a4 <LoopForever+0xe>)
+    LDR R1,=0x00000001
+ 800165a:	4913      	ldr	r1, [pc, #76]	; (80016a8 <LoopForever+0x12>)
+    STR R1, [R0]
+ 800165c:	6001      	str	r1, [r0, #0]
+
+/*Set CFGR1 register with flash memory remap at address 0*/
+    LDR R0,=0x40010000
+ 800165e:	4813      	ldr	r0, [pc, #76]	; (80016ac <LoopForever+0x16>)
+    LDR R1,=0x00000000
+ 8001660:	4913      	ldr	r1, [pc, #76]	; (80016b0 <LoopForever+0x1a>)
+    STR R1, [R0]
+ 8001662:	6001      	str	r1, [r0, #0]
+
+08001664 <ApplicationStart>:
+
+ApplicationStart:
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+ 8001664:	4813      	ldr	r0, [pc, #76]	; (80016b4 <LoopForever+0x1e>)
+  ldr r1, =_edata
+ 8001666:	4914      	ldr	r1, [pc, #80]	; (80016b8 <LoopForever+0x22>)
+  ldr r2, =_sidata
+ 8001668:	4a14      	ldr	r2, [pc, #80]	; (80016bc <LoopForever+0x26>)
+  movs r3, #0
+ 800166a:	2300      	movs	r3, #0
+  b LoopCopyDataInit
+ 800166c:	e002      	b.n	8001674 <LoopCopyDataInit>
+
+0800166e <CopyDataInit>:
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+ 800166e:	58d4      	ldr	r4, [r2, r3]
+  str r4, [r0, r3]
+ 8001670:	50c4      	str	r4, [r0, r3]
+  adds r3, r3, #4
+ 8001672:	3304      	adds	r3, #4
+
+08001674 <LoopCopyDataInit>:
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+ 8001674:	18c4      	adds	r4, r0, r3
+  cmp r4, r1
+ 8001676:	428c      	cmp	r4, r1
+  bcc CopyDataInit
+ 8001678:	d3f9      	bcc.n	800166e <CopyDataInit>
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+ 800167a:	4a11      	ldr	r2, [pc, #68]	; (80016c0 <LoopForever+0x2a>)
+  ldr r4, =_ebss
+ 800167c:	4c11      	ldr	r4, [pc, #68]	; (80016c4 <LoopForever+0x2e>)
+  movs r3, #0
+ 800167e:	2300      	movs	r3, #0
+  b LoopFillZerobss
+ 8001680:	e001      	b.n	8001686 <LoopFillZerobss>
+
+08001682 <FillZerobss>:
+
+FillZerobss:
+  str  r3, [r2]
+ 8001682:	6013      	str	r3, [r2, #0]
+  adds r2, r2, #4
+ 8001684:	3204      	adds	r2, #4
+
+08001686 <LoopFillZerobss>:
+
+LoopFillZerobss:
+  cmp r2, r4
+ 8001686:	42a2      	cmp	r2, r4
+  bcc FillZerobss
+ 8001688:	d3fb      	bcc.n	8001682 <FillZerobss>
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+ 800168a:	f7ff ffd7 	bl	800163c <SystemInit>
+/* Call static constructors */
+    bl __libc_init_array
+ 800168e:	f006 f869 	bl	8007764 <__libc_init_array>
+/* Call the application's entry point.*/
+  bl  main
+ 8001692:	f7ff f98d 	bl	80009b0 <main>
+
+08001696 <LoopForever>:
+
+LoopForever:
+    b LoopForever
+ 8001696:	e7fe      	b.n	8001696 <LoopForever>
+   ldr   r0, =_estack
+ 8001698:	20002000 	.word	0x20002000
+    LDR R0,=0x00000004
+ 800169c:	00000004 	.word	0x00000004
+    LDR R2,=0x1F
+ 80016a0:	0000001f 	.word	0x0000001f
+    LDR R0,=0x40021034
+ 80016a4:	40021034 	.word	0x40021034
+    LDR R1,=0x00000001
+ 80016a8:	00000001 	.word	0x00000001
+    LDR R0,=0x40010000
+ 80016ac:	40010000 	.word	0x40010000
+    LDR R1,=0x00000000
+ 80016b0:	00000000 	.word	0x00000000
+  ldr r0, =_sdata
+ 80016b4:	20000000 	.word	0x20000000
+  ldr r1, =_edata
+ 80016b8:	20000010 	.word	0x20000010
+  ldr r2, =_sidata
+ 80016bc:	08007928 	.word	0x08007928
+  ldr r2, =_sbss
+ 80016c0:	20000010 	.word	0x20000010
+  ldr r4, =_ebss
+ 80016c4:	200019ac 	.word	0x200019ac
+
+080016c8 <DMA1_Channel1_IRQHandler>:
+ * @retval : None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+ 80016c8:	e7fe      	b.n	80016c8 <DMA1_Channel1_IRQHandler>
+	...
+
+080016cc <HAL_Init>:
+  *        In the default implementation,Systick is used as source of time base.
+  *        the tick variable is incremented each 1ms in its ISR.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 80016cc:	b580      	push	{r7, lr}
+ 80016ce:	b082      	sub	sp, #8
+ 80016d0:	af00      	add	r7, sp, #0
+  HAL_StatusTypeDef  status = HAL_OK;
+ 80016d2:	1dfb      	adds	r3, r7, #7
+ 80016d4:	2200      	movs	r2, #0
+ 80016d6:	701a      	strb	r2, [r3, #0]
+#if (BUFFER_CACHE_DISABLE != 0)
+  __HAL_FLASH_BUFFER_CACHE_DISABLE();
+#endif /* BUFFER_CACHE_DISABLE */
+
+#if (PREREAD_ENABLE != 0)
+  __HAL_FLASH_PREREAD_BUFFER_ENABLE();
+ 80016d8:	4b0b      	ldr	r3, [pc, #44]	; (8001708 <HAL_Init+0x3c>)
+ 80016da:	681a      	ldr	r2, [r3, #0]
+ 80016dc:	4b0a      	ldr	r3, [pc, #40]	; (8001708 <HAL_Init+0x3c>)
+ 80016de:	2140      	movs	r1, #64	; 0x40
+ 80016e0:	430a      	orrs	r2, r1
+ 80016e2:	601a      	str	r2, [r3, #0]
+#if (PREFETCH_ENABLE != 0)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ 80016e4:	2003      	movs	r0, #3
+ 80016e6:	f000 f811 	bl	800170c <HAL_InitTick>
+ 80016ea:	1e03      	subs	r3, r0, #0
+ 80016ec:	d003      	beq.n	80016f6 <HAL_Init+0x2a>
+  {
+    status = HAL_ERROR;
+ 80016ee:	1dfb      	adds	r3, r7, #7
+ 80016f0:	2201      	movs	r2, #1
+ 80016f2:	701a      	strb	r2, [r3, #0]
+ 80016f4:	e001      	b.n	80016fa <HAL_Init+0x2e>
+  }
+  else
+  {
+    /* Init the low level hardware */
+    HAL_MspInit();
+ 80016f6:	f7ff fd1d 	bl	8001134 <HAL_MspInit>
+  }
+
+  /* Return function status */
+  return status;
+ 80016fa:	1dfb      	adds	r3, r7, #7
+ 80016fc:	781b      	ldrb	r3, [r3, #0]
+}
+ 80016fe:	0018      	movs	r0, r3
+ 8001700:	46bd      	mov	sp, r7
+ 8001702:	b002      	add	sp, #8
+ 8001704:	bd80      	pop	{r7, pc}
+ 8001706:	46c0      	nop			; (mov r8, r8)
+ 8001708:	40022000 	.word	0x40022000
+
+0800170c <HAL_InitTick>:
+  *       implementation  in user file.
+  * @param TickPriority Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 800170c:	b590      	push	{r4, r7, lr}
+ 800170e:	b083      	sub	sp, #12
+ 8001710:	af00      	add	r7, sp, #0
+ 8001712:	6078      	str	r0, [r7, #4]
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ 8001714:	4b14      	ldr	r3, [pc, #80]	; (8001768 <HAL_InitTick+0x5c>)
+ 8001716:	681c      	ldr	r4, [r3, #0]
+ 8001718:	4b14      	ldr	r3, [pc, #80]	; (800176c <HAL_InitTick+0x60>)
+ 800171a:	781b      	ldrb	r3, [r3, #0]
+ 800171c:	0019      	movs	r1, r3
+ 800171e:	23fa      	movs	r3, #250	; 0xfa
+ 8001720:	0098      	lsls	r0, r3, #2
+ 8001722:	f7fe fcf1 	bl	8000108 <__udivsi3>
+ 8001726:	0003      	movs	r3, r0
+ 8001728:	0019      	movs	r1, r3
+ 800172a:	0020      	movs	r0, r4
+ 800172c:	f7fe fcec 	bl	8000108 <__udivsi3>
+ 8001730:	0003      	movs	r3, r0
+ 8001732:	0018      	movs	r0, r3
+ 8001734:	f000 fbbb 	bl	8001eae <HAL_SYSTICK_Config>
+ 8001738:	1e03      	subs	r3, r0, #0
+ 800173a:	d001      	beq.n	8001740 <HAL_InitTick+0x34>
+  {
+    return HAL_ERROR;
+ 800173c:	2301      	movs	r3, #1
+ 800173e:	e00f      	b.n	8001760 <HAL_InitTick+0x54>
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 8001740:	687b      	ldr	r3, [r7, #4]
+ 8001742:	2b03      	cmp	r3, #3
+ 8001744:	d80b      	bhi.n	800175e <HAL_InitTick+0x52>
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 8001746:	6879      	ldr	r1, [r7, #4]
+ 8001748:	2301      	movs	r3, #1
+ 800174a:	425b      	negs	r3, r3
+ 800174c:	2200      	movs	r2, #0
+ 800174e:	0018      	movs	r0, r3
+ 8001750:	f000 fb88 	bl	8001e64 <HAL_NVIC_SetPriority>
+    uwTickPrio = TickPriority;
+ 8001754:	4b06      	ldr	r3, [pc, #24]	; (8001770 <HAL_InitTick+0x64>)
+ 8001756:	687a      	ldr	r2, [r7, #4]
+ 8001758:	601a      	str	r2, [r3, #0]
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+ 800175a:	2300      	movs	r3, #0
+ 800175c:	e000      	b.n	8001760 <HAL_InitTick+0x54>
+    return HAL_ERROR;
+ 800175e:	2301      	movs	r3, #1
+}
+ 8001760:	0018      	movs	r0, r3
+ 8001762:	46bd      	mov	sp, r7
+ 8001764:	b003      	add	sp, #12
+ 8001766:	bd90      	pop	{r4, r7, pc}
+ 8001768:	20000000 	.word	0x20000000
+ 800176c:	20000008 	.word	0x20000008
+ 8001770:	20000004 	.word	0x20000004
+
+08001774 <HAL_IncTick>:
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+ 8001774:	b580      	push	{r7, lr}
+ 8001776:	af00      	add	r7, sp, #0
+  uwTick += uwTickFreq;
+ 8001778:	4b05      	ldr	r3, [pc, #20]	; (8001790 <HAL_IncTick+0x1c>)
+ 800177a:	781b      	ldrb	r3, [r3, #0]
+ 800177c:	001a      	movs	r2, r3
+ 800177e:	4b05      	ldr	r3, [pc, #20]	; (8001794 <HAL_IncTick+0x20>)
+ 8001780:	681b      	ldr	r3, [r3, #0]
+ 8001782:	18d2      	adds	r2, r2, r3
+ 8001784:	4b03      	ldr	r3, [pc, #12]	; (8001794 <HAL_IncTick+0x20>)
+ 8001786:	601a      	str	r2, [r3, #0]
+}
+ 8001788:	46c0      	nop			; (mov r8, r8)
+ 800178a:	46bd      	mov	sp, r7
+ 800178c:	bd80      	pop	{r7, pc}
+ 800178e:	46c0      	nop			; (mov r8, r8)
+ 8001790:	20000008 	.word	0x20000008
+ 8001794:	20001968 	.word	0x20001968
+
+08001798 <HAL_GetTick>:
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+ 8001798:	b580      	push	{r7, lr}
+ 800179a:	af00      	add	r7, sp, #0
+  return uwTick;
+ 800179c:	4b02      	ldr	r3, [pc, #8]	; (80017a8 <HAL_GetTick+0x10>)
+ 800179e:	681b      	ldr	r3, [r3, #0]
+}
+ 80017a0:	0018      	movs	r0, r3
+ 80017a2:	46bd      	mov	sp, r7
+ 80017a4:	bd80      	pop	{r7, pc}
+ 80017a6:	46c0      	nop			; (mov r8, r8)
+ 80017a8:	20001968 	.word	0x20001968
+
+080017ac <HAL_ADC_Init>:
+  *         function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly.  
+  * @param  hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ 80017ac:	b580      	push	{r7, lr}
+ 80017ae:	b082      	sub	sp, #8
+ 80017b0:	af00      	add	r7, sp, #0
+ 80017b2:	6078      	str	r0, [r7, #4]
+ 
+  /* Check ADC handle */
+  if(hadc == NULL)
+ 80017b4:	687b      	ldr	r3, [r7, #4]
+ 80017b6:	2b00      	cmp	r3, #0
+ 80017b8:	d101      	bne.n	80017be <HAL_ADC_Init+0x12>
+  {
+    return HAL_ERROR;
+ 80017ba:	2301      	movs	r3, #1
+ 80017bc:	e159      	b.n	8001a72 <HAL_ADC_Init+0x2c6>
+  /* Refer to header of this file for more details on clock enabling procedure*/
+  
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  /* - ADC voltage regulator enable                                           */
+  if(hadc->State == HAL_ADC_STATE_RESET)
+ 80017be:	687b      	ldr	r3, [r7, #4]
+ 80017c0:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80017c2:	2b00      	cmp	r3, #0
+ 80017c4:	d10a      	bne.n	80017dc <HAL_ADC_Init+0x30>
+  {
+    /* Initialize ADC error code */
+    ADC_CLEAR_ERRORCODE(hadc);
+ 80017c6:	687b      	ldr	r3, [r7, #4]
+ 80017c8:	2200      	movs	r2, #0
+ 80017ca:	659a      	str	r2, [r3, #88]	; 0x58
+    
+    /* Allocate lock resource and initialize it */
+    hadc->Lock = HAL_UNLOCKED;
+ 80017cc:	687b      	ldr	r3, [r7, #4]
+ 80017ce:	2250      	movs	r2, #80	; 0x50
+ 80017d0:	2100      	movs	r1, #0
+ 80017d2:	5499      	strb	r1, [r3, r2]
+    
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+ 80017d4:	687b      	ldr	r3, [r7, #4]
+ 80017d6:	0018      	movs	r0, r3
+ 80017d8:	f7ff fcc8 	bl	800116c <HAL_ADC_MspInit>
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  /* and if there is no conversion on going on regular group (ADC can be      */
+  /* enabled anyway, in case of call of this function to update a parameter   */
+  /* on the fly).                                                             */
+  if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) ||
+ 80017dc:	687b      	ldr	r3, [r7, #4]
+ 80017de:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80017e0:	2210      	movs	r2, #16
+ 80017e2:	4013      	ands	r3, r2
+ 80017e4:	2b10      	cmp	r3, #16
+ 80017e6:	d005      	beq.n	80017f4 <HAL_ADC_Init+0x48>
+     (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)  )
+ 80017e8:	687b      	ldr	r3, [r7, #4]
+ 80017ea:	681b      	ldr	r3, [r3, #0]
+ 80017ec:	689b      	ldr	r3, [r3, #8]
+ 80017ee:	2204      	movs	r2, #4
+ 80017f0:	4013      	ands	r3, r2
+  if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) ||
+ 80017f2:	d00b      	beq.n	800180c <HAL_ADC_Init+0x60>
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 80017f4:	687b      	ldr	r3, [r7, #4]
+ 80017f6:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80017f8:	2210      	movs	r2, #16
+ 80017fa:	431a      	orrs	r2, r3
+ 80017fc:	687b      	ldr	r3, [r7, #4]
+ 80017fe:	655a      	str	r2, [r3, #84]	; 0x54
+        
+    /* Process unlocked */
+    __HAL_UNLOCK(hadc);
+ 8001800:	687b      	ldr	r3, [r7, #4]
+ 8001802:	2250      	movs	r2, #80	; 0x50
+ 8001804:	2100      	movs	r1, #0
+ 8001806:	5499      	strb	r1, [r3, r2]
+    return HAL_ERROR;
+ 8001808:	2301      	movs	r3, #1
+ 800180a:	e132      	b.n	8001a72 <HAL_ADC_Init+0x2c6>
+  }
+
+  /* Set ADC state */
+  ADC_STATE_CLR_SET(hadc->State,
+ 800180c:	687b      	ldr	r3, [r7, #4]
+ 800180e:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001810:	4a9a      	ldr	r2, [pc, #616]	; (8001a7c <HAL_ADC_Init+0x2d0>)
+ 8001812:	4013      	ands	r3, r2
+ 8001814:	2202      	movs	r2, #2
+ 8001816:	431a      	orrs	r2, r3
+ 8001818:	687b      	ldr	r3, [r7, #4]
+ 800181a:	655a      	str	r2, [r3, #84]	; 0x54
+  /* Parameters update conditioned to ADC state:                            */
+  /* Parameters that can be updated only when ADC is disabled:              */
+  /*  - ADC clock mode                                                      */
+  /*  - ADC clock prescaler                                                 */
+  /*  - ADC Resolution                                                      */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+ 800181c:	687b      	ldr	r3, [r7, #4]
+ 800181e:	681b      	ldr	r3, [r3, #0]
+ 8001820:	689b      	ldr	r3, [r3, #8]
+ 8001822:	2203      	movs	r2, #3
+ 8001824:	4013      	ands	r3, r2
+ 8001826:	2b01      	cmp	r3, #1
+ 8001828:	d108      	bne.n	800183c <HAL_ADC_Init+0x90>
+ 800182a:	687b      	ldr	r3, [r7, #4]
+ 800182c:	681b      	ldr	r3, [r3, #0]
+ 800182e:	681b      	ldr	r3, [r3, #0]
+ 8001830:	2201      	movs	r2, #1
+ 8001832:	4013      	ands	r3, r2
+ 8001834:	2b01      	cmp	r3, #1
+ 8001836:	d101      	bne.n	800183c <HAL_ADC_Init+0x90>
+ 8001838:	2301      	movs	r3, #1
+ 800183a:	e000      	b.n	800183e <HAL_ADC_Init+0x92>
+ 800183c:	2300      	movs	r3, #0
+ 800183e:	2b00      	cmp	r3, #0
+ 8001840:	d149      	bne.n	80018d6 <HAL_ADC_Init+0x12a>
+    /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+    /*     (set into HAL_ADC_ConfigChannel() )                              */
+   
+    /* Configuration of ADC clock: clock source PCLK or asynchronous with 
+    selectable prescaler */
+    __HAL_ADC_CLOCK_PRESCALER(hadc);
+ 8001842:	687b      	ldr	r3, [r7, #4]
+ 8001844:	685a      	ldr	r2, [r3, #4]
+ 8001846:	23c0      	movs	r3, #192	; 0xc0
+ 8001848:	061b      	lsls	r3, r3, #24
+ 800184a:	429a      	cmp	r2, r3
+ 800184c:	d00b      	beq.n	8001866 <HAL_ADC_Init+0xba>
+ 800184e:	687b      	ldr	r3, [r7, #4]
+ 8001850:	685a      	ldr	r2, [r3, #4]
+ 8001852:	2380      	movs	r3, #128	; 0x80
+ 8001854:	05db      	lsls	r3, r3, #23
+ 8001856:	429a      	cmp	r2, r3
+ 8001858:	d005      	beq.n	8001866 <HAL_ADC_Init+0xba>
+ 800185a:	687b      	ldr	r3, [r7, #4]
+ 800185c:	685a      	ldr	r2, [r3, #4]
+ 800185e:	2380      	movs	r3, #128	; 0x80
+ 8001860:	061b      	lsls	r3, r3, #24
+ 8001862:	429a      	cmp	r2, r3
+ 8001864:	d111      	bne.n	800188a <HAL_ADC_Init+0xde>
+ 8001866:	687b      	ldr	r3, [r7, #4]
+ 8001868:	681b      	ldr	r3, [r3, #0]
+ 800186a:	691a      	ldr	r2, [r3, #16]
+ 800186c:	687b      	ldr	r3, [r7, #4]
+ 800186e:	681b      	ldr	r3, [r3, #0]
+ 8001870:	0092      	lsls	r2, r2, #2
+ 8001872:	0892      	lsrs	r2, r2, #2
+ 8001874:	611a      	str	r2, [r3, #16]
+ 8001876:	687b      	ldr	r3, [r7, #4]
+ 8001878:	681b      	ldr	r3, [r3, #0]
+ 800187a:	6919      	ldr	r1, [r3, #16]
+ 800187c:	687b      	ldr	r3, [r7, #4]
+ 800187e:	685a      	ldr	r2, [r3, #4]
+ 8001880:	687b      	ldr	r3, [r7, #4]
+ 8001882:	681b      	ldr	r3, [r3, #0]
+ 8001884:	430a      	orrs	r2, r1
+ 8001886:	611a      	str	r2, [r3, #16]
+ 8001888:	e014      	b.n	80018b4 <HAL_ADC_Init+0x108>
+ 800188a:	687b      	ldr	r3, [r7, #4]
+ 800188c:	681b      	ldr	r3, [r3, #0]
+ 800188e:	691a      	ldr	r2, [r3, #16]
+ 8001890:	687b      	ldr	r3, [r7, #4]
+ 8001892:	681b      	ldr	r3, [r3, #0]
+ 8001894:	0092      	lsls	r2, r2, #2
+ 8001896:	0892      	lsrs	r2, r2, #2
+ 8001898:	611a      	str	r2, [r3, #16]
+ 800189a:	4b79      	ldr	r3, [pc, #484]	; (8001a80 <HAL_ADC_Init+0x2d4>)
+ 800189c:	681a      	ldr	r2, [r3, #0]
+ 800189e:	4b78      	ldr	r3, [pc, #480]	; (8001a80 <HAL_ADC_Init+0x2d4>)
+ 80018a0:	4978      	ldr	r1, [pc, #480]	; (8001a84 <HAL_ADC_Init+0x2d8>)
+ 80018a2:	400a      	ands	r2, r1
+ 80018a4:	601a      	str	r2, [r3, #0]
+ 80018a6:	4b76      	ldr	r3, [pc, #472]	; (8001a80 <HAL_ADC_Init+0x2d4>)
+ 80018a8:	6819      	ldr	r1, [r3, #0]
+ 80018aa:	687b      	ldr	r3, [r7, #4]
+ 80018ac:	685a      	ldr	r2, [r3, #4]
+ 80018ae:	4b74      	ldr	r3, [pc, #464]	; (8001a80 <HAL_ADC_Init+0x2d4>)
+ 80018b0:	430a      	orrs	r2, r1
+ 80018b2:	601a      	str	r2, [r3, #0]
+    
+    /* Configuration of ADC:                                                */
+    /*  - Resolution                                                        */
+    hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES);
+ 80018b4:	687b      	ldr	r3, [r7, #4]
+ 80018b6:	681b      	ldr	r3, [r3, #0]
+ 80018b8:	68da      	ldr	r2, [r3, #12]
+ 80018ba:	687b      	ldr	r3, [r7, #4]
+ 80018bc:	681b      	ldr	r3, [r3, #0]
+ 80018be:	2118      	movs	r1, #24
+ 80018c0:	438a      	bics	r2, r1
+ 80018c2:	60da      	str	r2, [r3, #12]
+    hadc->Instance->CFGR1 |= hadc->Init.Resolution;    
+ 80018c4:	687b      	ldr	r3, [r7, #4]
+ 80018c6:	681b      	ldr	r3, [r3, #0]
+ 80018c8:	68d9      	ldr	r1, [r3, #12]
+ 80018ca:	687b      	ldr	r3, [r7, #4]
+ 80018cc:	689a      	ldr	r2, [r3, #8]
+ 80018ce:	687b      	ldr	r3, [r7, #4]
+ 80018d0:	681b      	ldr	r3, [r3, #0]
+ 80018d2:	430a      	orrs	r2, r1
+ 80018d4:	60da      	str	r2, [r3, #12]
+  }
+  
+  /* Set the Low Frequency mode */
+  ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN;
+ 80018d6:	4b6a      	ldr	r3, [pc, #424]	; (8001a80 <HAL_ADC_Init+0x2d4>)
+ 80018d8:	681a      	ldr	r2, [r3, #0]
+ 80018da:	4b69      	ldr	r3, [pc, #420]	; (8001a80 <HAL_ADC_Init+0x2d4>)
+ 80018dc:	496a      	ldr	r1, [pc, #424]	; (8001a88 <HAL_ADC_Init+0x2dc>)
+ 80018de:	400a      	ands	r2, r1
+ 80018e0:	601a      	str	r2, [r3, #0]
+  ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode);  
+ 80018e2:	4b67      	ldr	r3, [pc, #412]	; (8001a80 <HAL_ADC_Init+0x2d4>)
+ 80018e4:	6819      	ldr	r1, [r3, #0]
+ 80018e6:	687b      	ldr	r3, [r7, #4]
+ 80018e8:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 80018ea:	065a      	lsls	r2, r3, #25
+ 80018ec:	4b64      	ldr	r3, [pc, #400]	; (8001a80 <HAL_ADC_Init+0x2d4>)
+ 80018ee:	430a      	orrs	r2, r1
+ 80018f0:	601a      	str	r2, [r3, #0]
+   
+  /* Enable voltage regulator (if disabled at this step) */
+  if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
+ 80018f2:	687b      	ldr	r3, [r7, #4]
+ 80018f4:	681b      	ldr	r3, [r3, #0]
+ 80018f6:	689a      	ldr	r2, [r3, #8]
+ 80018f8:	2380      	movs	r3, #128	; 0x80
+ 80018fa:	055b      	lsls	r3, r3, #21
+ 80018fc:	4013      	ands	r3, r2
+ 80018fe:	d108      	bne.n	8001912 <HAL_ADC_Init+0x166>
+  {
+    /* Set ADVREGEN bit */
+    hadc->Instance->CR |= ADC_CR_ADVREGEN;
+ 8001900:	687b      	ldr	r3, [r7, #4]
+ 8001902:	681b      	ldr	r3, [r3, #0]
+ 8001904:	689a      	ldr	r2, [r3, #8]
+ 8001906:	687b      	ldr	r3, [r7, #4]
+ 8001908:	681b      	ldr	r3, [r3, #0]
+ 800190a:	2180      	movs	r1, #128	; 0x80
+ 800190c:	0549      	lsls	r1, r1, #21
+ 800190e:	430a      	orrs	r2, r1
+ 8001910:	609a      	str	r2, [r3, #8]
+  /*  - Continuous conversion mode                                            */
+  /*  - DMA continuous request                                                */
+  /*  - Overrun                                                               */
+  /*  - AutoDelay feature                                                     */
+  /*  - Discontinuous mode                                                    */
+  hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN   |
+ 8001912:	687b      	ldr	r3, [r7, #4]
+ 8001914:	681b      	ldr	r3, [r3, #0]
+ 8001916:	68da      	ldr	r2, [r3, #12]
+ 8001918:	687b      	ldr	r3, [r7, #4]
+ 800191a:	681b      	ldr	r3, [r3, #0]
+ 800191c:	495b      	ldr	r1, [pc, #364]	; (8001a8c <HAL_ADC_Init+0x2e0>)
+ 800191e:	400a      	ands	r2, r1
+ 8001920:	60da      	str	r2, [r3, #12]
+                             ADC_CFGR1_OVRMOD  |
+                             ADC_CFGR1_AUTDLY  |
+                             ADC_CFGR1_AUTOFF  |
+                             ADC_CFGR1_DISCEN   );
+  
+  hadc->Instance->CFGR1 |= (hadc->Init.DataAlign                             |
+ 8001922:	687b      	ldr	r3, [r7, #4]
+ 8001924:	681b      	ldr	r3, [r3, #0]
+ 8001926:	68d9      	ldr	r1, [r3, #12]
+ 8001928:	687b      	ldr	r3, [r7, #4]
+ 800192a:	68da      	ldr	r2, [r3, #12]
+                            ADC_SCANDIR(hadc->Init.ScanConvMode)             |
+ 800192c:	687b      	ldr	r3, [r7, #4]
+ 800192e:	691b      	ldr	r3, [r3, #16]
+ 8001930:	2b02      	cmp	r3, #2
+ 8001932:	d101      	bne.n	8001938 <HAL_ADC_Init+0x18c>
+ 8001934:	2304      	movs	r3, #4
+ 8001936:	e000      	b.n	800193a <HAL_ADC_Init+0x18e>
+ 8001938:	2300      	movs	r3, #0
+  hadc->Instance->CFGR1 |= (hadc->Init.DataAlign                             |
+ 800193a:	431a      	orrs	r2, r3
+                            ADC_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)    |
+ 800193c:	687b      	ldr	r3, [r7, #4]
+ 800193e:	2020      	movs	r0, #32
+ 8001940:	5c1b      	ldrb	r3, [r3, r0]
+ 8001942:	035b      	lsls	r3, r3, #13
+                            ADC_SCANDIR(hadc->Init.ScanConvMode)             |
+ 8001944:	431a      	orrs	r2, r3
+                            ADC_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
+ 8001946:	687b      	ldr	r3, [r7, #4]
+ 8001948:	202c      	movs	r0, #44	; 0x2c
+ 800194a:	5c1b      	ldrb	r3, [r3, r0]
+ 800194c:	005b      	lsls	r3, r3, #1
+                            ADC_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)    |
+ 800194e:	431a      	orrs	r2, r3
+                            hadc->Init.Overrun                               |
+ 8001950:	687b      	ldr	r3, [r7, #4]
+ 8001952:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+                            ADC_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
+ 8001954:	431a      	orrs	r2, r3
+                            __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) |
+ 8001956:	687b      	ldr	r3, [r7, #4]
+ 8001958:	699b      	ldr	r3, [r3, #24]
+ 800195a:	039b      	lsls	r3, r3, #14
+                            hadc->Init.Overrun                               |
+ 800195c:	431a      	orrs	r2, r3
+                            __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff));
+ 800195e:	687b      	ldr	r3, [r7, #4]
+ 8001960:	69db      	ldr	r3, [r3, #28]
+ 8001962:	03db      	lsls	r3, r3, #15
+                            __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) |
+ 8001964:	431a      	orrs	r2, r3
+  hadc->Instance->CFGR1 |= (hadc->Init.DataAlign                             |
+ 8001966:	687b      	ldr	r3, [r7, #4]
+ 8001968:	681b      	ldr	r3, [r3, #0]
+ 800196a:	430a      	orrs	r2, r1
+ 800196c:	60da      	str	r2, [r3, #12]
+  /* Enable external trigger if trigger selection is different of software  */
+  /* start.                                                                 */
+  /* Note: This configuration keeps the hardware feature of parameter       */
+  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+  /*       software start.                                                  */
+  if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ 800196e:	687b      	ldr	r3, [r7, #4]
+ 8001970:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 8001972:	23c2      	movs	r3, #194	; 0xc2
+ 8001974:	33ff      	adds	r3, #255	; 0xff
+ 8001976:	429a      	cmp	r2, r3
+ 8001978:	d00b      	beq.n	8001992 <HAL_ADC_Init+0x1e6>
+  {
+    hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv |
+ 800197a:	687b      	ldr	r3, [r7, #4]
+ 800197c:	681b      	ldr	r3, [r3, #0]
+ 800197e:	68d9      	ldr	r1, [r3, #12]
+ 8001980:	687b      	ldr	r3, [r7, #4]
+ 8001982:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+                             hadc->Init.ExternalTrigConvEdge;
+ 8001984:	687b      	ldr	r3, [r7, #4]
+ 8001986:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+    hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv |
+ 8001988:	431a      	orrs	r2, r3
+ 800198a:	687b      	ldr	r3, [r7, #4]
+ 800198c:	681b      	ldr	r3, [r3, #0]
+ 800198e:	430a      	orrs	r2, r1
+ 8001990:	60da      	str	r2, [r3, #12]
+  }
+  
+  /* Enable discontinuous mode only if continuous mode is disabled */
+  if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ 8001992:	687b      	ldr	r3, [r7, #4]
+ 8001994:	2221      	movs	r2, #33	; 0x21
+ 8001996:	5c9b      	ldrb	r3, [r3, r2]
+ 8001998:	2b01      	cmp	r3, #1
+ 800199a:	d11a      	bne.n	80019d2 <HAL_ADC_Init+0x226>
+  {
+    if (hadc->Init.ContinuousConvMode == DISABLE)
+ 800199c:	687b      	ldr	r3, [r7, #4]
+ 800199e:	2220      	movs	r2, #32
+ 80019a0:	5c9b      	ldrb	r3, [r3, r2]
+ 80019a2:	2b00      	cmp	r3, #0
+ 80019a4:	d109      	bne.n	80019ba <HAL_ADC_Init+0x20e>
+    {
+      /* Enable the selected ADC group regular discontinuous mode */
+      hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN);
+ 80019a6:	687b      	ldr	r3, [r7, #4]
+ 80019a8:	681b      	ldr	r3, [r3, #0]
+ 80019aa:	68da      	ldr	r2, [r3, #12]
+ 80019ac:	687b      	ldr	r3, [r7, #4]
+ 80019ae:	681b      	ldr	r3, [r3, #0]
+ 80019b0:	2180      	movs	r1, #128	; 0x80
+ 80019b2:	0249      	lsls	r1, r1, #9
+ 80019b4:	430a      	orrs	r2, r1
+ 80019b6:	60da      	str	r2, [r3, #12]
+ 80019b8:	e00b      	b.n	80019d2 <HAL_ADC_Init+0x226>
+      /* ADC regular group discontinuous was intended to be enabled,        */
+      /* but ADC regular group modes continuous and sequencer discontinuous */
+      /* cannot be enabled simultaneously.                                  */
+      
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 80019ba:	687b      	ldr	r3, [r7, #4]
+ 80019bc:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80019be:	2220      	movs	r2, #32
+ 80019c0:	431a      	orrs	r2, r3
+ 80019c2:	687b      	ldr	r3, [r7, #4]
+ 80019c4:	655a      	str	r2, [r3, #84]	; 0x54
+      
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 80019c6:	687b      	ldr	r3, [r7, #4]
+ 80019c8:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 80019ca:	2201      	movs	r2, #1
+ 80019cc:	431a      	orrs	r2, r3
+ 80019ce:	687b      	ldr	r3, [r7, #4]
+ 80019d0:	659a      	str	r2, [r3, #88]	; 0x58
+    }
+  }
+  
+  if (hadc->Init.OversamplingMode == ENABLE)
+ 80019d2:	687b      	ldr	r3, [r7, #4]
+ 80019d4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80019d6:	2b01      	cmp	r3, #1
+ 80019d8:	d11f      	bne.n	8001a1a <HAL_ADC_Init+0x26e>
+    /* Configuration of Oversampler:                                          */
+    /*  - Oversampling Ratio                                                  */
+    /*  - Right bit shift                                                     */
+    /*  - Triggered mode                                                      */
+    
+    hadc->Instance->CFGR2 &= ~( ADC_CFGR2_OVSR |
+ 80019da:	687b      	ldr	r3, [r7, #4]
+ 80019dc:	681b      	ldr	r3, [r3, #0]
+ 80019de:	691a      	ldr	r2, [r3, #16]
+ 80019e0:	687b      	ldr	r3, [r7, #4]
+ 80019e2:	681b      	ldr	r3, [r3, #0]
+ 80019e4:	492a      	ldr	r1, [pc, #168]	; (8001a90 <HAL_ADC_Init+0x2e4>)
+ 80019e6:	400a      	ands	r2, r1
+ 80019e8:	611a      	str	r2, [r3, #16]
+                                ADC_CFGR2_OVSS |
+                                ADC_CFGR2_TOVS );
+    
+    hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio         |
+ 80019ea:	687b      	ldr	r3, [r7, #4]
+ 80019ec:	681b      	ldr	r3, [r3, #0]
+ 80019ee:	6919      	ldr	r1, [r3, #16]
+ 80019f0:	687b      	ldr	r3, [r7, #4]
+ 80019f2:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+                               hadc->Init.Oversample.RightBitShift             |
+ 80019f4:	687b      	ldr	r3, [r7, #4]
+ 80019f6:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+    hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio         |
+ 80019f8:	431a      	orrs	r2, r3
+                               hadc->Init.Oversample.TriggeredMode );
+ 80019fa:	687b      	ldr	r3, [r7, #4]
+ 80019fc:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+                               hadc->Init.Oversample.RightBitShift             |
+ 80019fe:	431a      	orrs	r2, r3
+    hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio         |
+ 8001a00:	687b      	ldr	r3, [r7, #4]
+ 8001a02:	681b      	ldr	r3, [r3, #0]
+ 8001a04:	430a      	orrs	r2, r1
+ 8001a06:	611a      	str	r2, [r3, #16]
+    
+    /* Enable OverSampling mode */
+     hadc->Instance->CFGR2 |= ADC_CFGR2_OVSE;
+ 8001a08:	687b      	ldr	r3, [r7, #4]
+ 8001a0a:	681b      	ldr	r3, [r3, #0]
+ 8001a0c:	691a      	ldr	r2, [r3, #16]
+ 8001a0e:	687b      	ldr	r3, [r7, #4]
+ 8001a10:	681b      	ldr	r3, [r3, #0]
+ 8001a12:	2101      	movs	r1, #1
+ 8001a14:	430a      	orrs	r2, r1
+ 8001a16:	611a      	str	r2, [r3, #16]
+ 8001a18:	e00e      	b.n	8001a38 <HAL_ADC_Init+0x28c>
+  }
+  else
+  {
+    if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE))
+ 8001a1a:	687b      	ldr	r3, [r7, #4]
+ 8001a1c:	681b      	ldr	r3, [r3, #0]
+ 8001a1e:	691b      	ldr	r3, [r3, #16]
+ 8001a20:	2201      	movs	r2, #1
+ 8001a22:	4013      	ands	r3, r2
+ 8001a24:	2b01      	cmp	r3, #1
+ 8001a26:	d107      	bne.n	8001a38 <HAL_ADC_Init+0x28c>
+    {
+      /* Disable OverSampling mode if needed */
+      hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE;
+ 8001a28:	687b      	ldr	r3, [r7, #4]
+ 8001a2a:	681b      	ldr	r3, [r3, #0]
+ 8001a2c:	691a      	ldr	r2, [r3, #16]
+ 8001a2e:	687b      	ldr	r3, [r7, #4]
+ 8001a30:	681b      	ldr	r3, [r3, #0]
+ 8001a32:	2101      	movs	r1, #1
+ 8001a34:	438a      	bics	r2, r1
+ 8001a36:	611a      	str	r2, [r3, #16]
+    }
+  }    
+  
+  /* Clear the old sampling time */
+  hadc->Instance->SMPR &= (uint32_t)(~ADC_SMPR_SMPR);
+ 8001a38:	687b      	ldr	r3, [r7, #4]
+ 8001a3a:	681b      	ldr	r3, [r3, #0]
+ 8001a3c:	695a      	ldr	r2, [r3, #20]
+ 8001a3e:	687b      	ldr	r3, [r7, #4]
+ 8001a40:	681b      	ldr	r3, [r3, #0]
+ 8001a42:	2107      	movs	r1, #7
+ 8001a44:	438a      	bics	r2, r1
+ 8001a46:	615a      	str	r2, [r3, #20]
+  
+  /* Set the new sample time */
+  hadc->Instance->SMPR |= hadc->Init.SamplingTime;
+ 8001a48:	687b      	ldr	r3, [r7, #4]
+ 8001a4a:	681b      	ldr	r3, [r3, #0]
+ 8001a4c:	6959      	ldr	r1, [r3, #20]
+ 8001a4e:	687b      	ldr	r3, [r7, #4]
+ 8001a50:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8001a52:	687b      	ldr	r3, [r7, #4]
+ 8001a54:	681b      	ldr	r3, [r3, #0]
+ 8001a56:	430a      	orrs	r2, r1
+ 8001a58:	615a      	str	r2, [r3, #20]
+  
+  /* Clear ADC error code */
+  ADC_CLEAR_ERRORCODE(hadc);
+ 8001a5a:	687b      	ldr	r3, [r7, #4]
+ 8001a5c:	2200      	movs	r2, #0
+ 8001a5e:	659a      	str	r2, [r3, #88]	; 0x58
+
+  /* Set the ADC state */
+  ADC_STATE_CLR_SET(hadc->State,
+ 8001a60:	687b      	ldr	r3, [r7, #4]
+ 8001a62:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001a64:	2203      	movs	r2, #3
+ 8001a66:	4393      	bics	r3, r2
+ 8001a68:	2201      	movs	r2, #1
+ 8001a6a:	431a      	orrs	r2, r3
+ 8001a6c:	687b      	ldr	r3, [r7, #4]
+ 8001a6e:	655a      	str	r2, [r3, #84]	; 0x54
+                    HAL_ADC_STATE_BUSY_INTERNAL,
+                    HAL_ADC_STATE_READY);
+
+
+  /* Return function status */
+  return HAL_OK;
+ 8001a70:	2300      	movs	r3, #0
+}
+ 8001a72:	0018      	movs	r0, r3
+ 8001a74:	46bd      	mov	sp, r7
+ 8001a76:	b002      	add	sp, #8
+ 8001a78:	bd80      	pop	{r7, pc}
+ 8001a7a:	46c0      	nop			; (mov r8, r8)
+ 8001a7c:	fffffefd 	.word	0xfffffefd
+ 8001a80:	40012708 	.word	0x40012708
+ 8001a84:	ffc3ffff 	.word	0xffc3ffff
+ 8001a88:	fdffffff 	.word	0xfdffffff
+ 8001a8c:	fffe0219 	.word	0xfffe0219
+ 8001a90:	fffffc03 	.word	0xfffffc03
+
+08001a94 <HAL_ADC_IRQHandler>:
+  * @brief  Handle ADC interrupt request.
+  * @param  hadc ADC handle
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ 8001a94:	b580      	push	{r7, lr}
+ 8001a96:	b082      	sub	sp, #8
+ 8001a98:	af00      	add	r7, sp, #0
+ 8001a9a:	6078      	str	r0, [r7, #4]
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  
+  /* ========== Check End of Conversion flag for regular group ========== */
+  if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || 
+ 8001a9c:	687b      	ldr	r3, [r7, #4]
+ 8001a9e:	681b      	ldr	r3, [r3, #0]
+ 8001aa0:	681b      	ldr	r3, [r3, #0]
+ 8001aa2:	2204      	movs	r2, #4
+ 8001aa4:	4013      	ands	r3, r2
+ 8001aa6:	2b04      	cmp	r3, #4
+ 8001aa8:	d106      	bne.n	8001ab8 <HAL_ADC_IRQHandler+0x24>
+ 8001aaa:	687b      	ldr	r3, [r7, #4]
+ 8001aac:	681b      	ldr	r3, [r3, #0]
+ 8001aae:	685b      	ldr	r3, [r3, #4]
+ 8001ab0:	2204      	movs	r2, #4
+ 8001ab2:	4013      	ands	r3, r2
+ 8001ab4:	2b04      	cmp	r3, #4
+ 8001ab6:	d00d      	beq.n	8001ad4 <HAL_ADC_IRQHandler+0x40>
+      (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS))   )
+ 8001ab8:	687b      	ldr	r3, [r7, #4]
+ 8001aba:	681b      	ldr	r3, [r3, #0]
+ 8001abc:	681b      	ldr	r3, [r3, #0]
+ 8001abe:	2208      	movs	r2, #8
+ 8001ac0:	4013      	ands	r3, r2
+  if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || 
+ 8001ac2:	2b08      	cmp	r3, #8
+ 8001ac4:	d154      	bne.n	8001b70 <HAL_ADC_IRQHandler+0xdc>
+      (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS))   )
+ 8001ac6:	687b      	ldr	r3, [r7, #4]
+ 8001ac8:	681b      	ldr	r3, [r3, #0]
+ 8001aca:	685b      	ldr	r3, [r3, #4]
+ 8001acc:	2208      	movs	r2, #8
+ 8001ace:	4013      	ands	r3, r2
+ 8001ad0:	2b08      	cmp	r3, #8
+ 8001ad2:	d14d      	bne.n	8001b70 <HAL_ADC_IRQHandler+0xdc>
+  {
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ 8001ad4:	687b      	ldr	r3, [r7, #4]
+ 8001ad6:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001ad8:	2210      	movs	r2, #16
+ 8001ada:	4013      	ands	r3, r2
+ 8001adc:	d106      	bne.n	8001aec <HAL_ADC_IRQHandler+0x58>
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ 8001ade:	687b      	ldr	r3, [r7, #4]
+ 8001ae0:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001ae2:	2280      	movs	r2, #128	; 0x80
+ 8001ae4:	0092      	lsls	r2, r2, #2
+ 8001ae6:	431a      	orrs	r2, r3
+ 8001ae8:	687b      	ldr	r3, [r7, #4]
+ 8001aea:	655a      	str	r2, [r3, #84]	; 0x54
+    }
+    
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going.        */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+ 8001aec:	687b      	ldr	r3, [r7, #4]
+ 8001aee:	681b      	ldr	r3, [r3, #0]
+ 8001af0:	68da      	ldr	r2, [r3, #12]
+ 8001af2:	23c0      	movs	r3, #192	; 0xc0
+ 8001af4:	011b      	lsls	r3, r3, #4
+ 8001af6:	4013      	ands	r3, r2
+ 8001af8:	d12e      	bne.n	8001b58 <HAL_ADC_IRQHandler+0xc4>
+       (hadc->Init.ContinuousConvMode == DISABLE)   )
+ 8001afa:	687b      	ldr	r3, [r7, #4]
+ 8001afc:	2220      	movs	r2, #32
+ 8001afe:	5c9b      	ldrb	r3, [r3, r2]
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+ 8001b00:	2b00      	cmp	r3, #0
+ 8001b02:	d129      	bne.n	8001b58 <HAL_ADC_IRQHandler+0xc4>
+    {
+      /* If End of Sequence is reached, disable interrupts */
+      if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ 8001b04:	687b      	ldr	r3, [r7, #4]
+ 8001b06:	681b      	ldr	r3, [r3, #0]
+ 8001b08:	681b      	ldr	r3, [r3, #0]
+ 8001b0a:	2208      	movs	r2, #8
+ 8001b0c:	4013      	ands	r3, r2
+ 8001b0e:	2b08      	cmp	r3, #8
+ 8001b10:	d122      	bne.n	8001b58 <HAL_ADC_IRQHandler+0xc4>
+      {
+        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
+        /* ADSTART==0 (no conversion on going)                                */
+        if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ 8001b12:	687b      	ldr	r3, [r7, #4]
+ 8001b14:	681b      	ldr	r3, [r3, #0]
+ 8001b16:	689b      	ldr	r3, [r3, #8]
+ 8001b18:	2204      	movs	r2, #4
+ 8001b1a:	4013      	ands	r3, r2
+ 8001b1c:	d110      	bne.n	8001b40 <HAL_ADC_IRQHandler+0xac>
+        {
+          /* Disable ADC end of single conversion interrupt on group regular */
+          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
+          /* HAL_Start_IT(), but is not disabled here because can be used     */
+          /* by overrun IRQ process below.                                    */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+ 8001b1e:	687b      	ldr	r3, [r7, #4]
+ 8001b20:	681b      	ldr	r3, [r3, #0]
+ 8001b22:	685a      	ldr	r2, [r3, #4]
+ 8001b24:	687b      	ldr	r3, [r7, #4]
+ 8001b26:	681b      	ldr	r3, [r3, #0]
+ 8001b28:	210c      	movs	r1, #12
+ 8001b2a:	438a      	bics	r2, r1
+ 8001b2c:	605a      	str	r2, [r3, #4]
+          
+          /* Set ADC state */
+          ADC_STATE_CLR_SET(hadc->State,
+ 8001b2e:	687b      	ldr	r3, [r7, #4]
+ 8001b30:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001b32:	4a35      	ldr	r2, [pc, #212]	; (8001c08 <HAL_ADC_IRQHandler+0x174>)
+ 8001b34:	4013      	ands	r3, r2
+ 8001b36:	2201      	movs	r2, #1
+ 8001b38:	431a      	orrs	r2, r3
+ 8001b3a:	687b      	ldr	r3, [r7, #4]
+ 8001b3c:	655a      	str	r2, [r3, #84]	; 0x54
+ 8001b3e:	e00b      	b.n	8001b58 <HAL_ADC_IRQHandler+0xc4>
+                            HAL_ADC_STATE_READY);
+        }
+        else
+        {
+          /* Change ADC state to error state */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8001b40:	687b      	ldr	r3, [r7, #4]
+ 8001b42:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001b44:	2220      	movs	r2, #32
+ 8001b46:	431a      	orrs	r2, r3
+ 8001b48:	687b      	ldr	r3, [r7, #4]
+ 8001b4a:	655a      	str	r2, [r3, #84]	; 0x54
+          
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 8001b4c:	687b      	ldr	r3, [r7, #4]
+ 8001b4e:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8001b50:	2201      	movs	r2, #1
+ 8001b52:	431a      	orrs	r2, r3
+ 8001b54:	687b      	ldr	r3, [r7, #4]
+ 8001b56:	659a      	str	r2, [r3, #88]	; 0x58
+    /*       from EOC or EOS, possibility to use:                             */
+    /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "                */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+ 8001b58:	687b      	ldr	r3, [r7, #4]
+ 8001b5a:	0018      	movs	r0, r3
+ 8001b5c:	f000 f856 	bl	8001c0c <HAL_ADC_ConvCpltCallback>
+    /* Note: Management of low power auto-wait enabled: flags must be cleared */
+    /*       by user when fetching ADC conversion data.                       */
+    /*       This case is managed in IRQ handler, but this low-power mode     */
+    /*       should not be used with programming model IT or DMA.             */
+    /*       Refer to comment of parameter "LowPowerAutoWait".                */
+    if (hadc->Init.LowPowerAutoWait != ENABLE)
+ 8001b60:	687b      	ldr	r3, [r7, #4]
+ 8001b62:	699b      	ldr	r3, [r3, #24]
+ 8001b64:	2b01      	cmp	r3, #1
+ 8001b66:	d003      	beq.n	8001b70 <HAL_ADC_IRQHandler+0xdc>
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ 8001b68:	687b      	ldr	r3, [r7, #4]
+ 8001b6a:	681b      	ldr	r3, [r3, #0]
+ 8001b6c:	220c      	movs	r2, #12
+ 8001b6e:	601a      	str	r2, [r3, #0]
+    }
+  }
+  
+  /* ========== Check analog watchdog 1 flag ========== */
+  if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
+ 8001b70:	687b      	ldr	r3, [r7, #4]
+ 8001b72:	681b      	ldr	r3, [r3, #0]
+ 8001b74:	681b      	ldr	r3, [r3, #0]
+ 8001b76:	2280      	movs	r2, #128	; 0x80
+ 8001b78:	4013      	ands	r3, r2
+ 8001b7a:	2b80      	cmp	r3, #128	; 0x80
+ 8001b7c:	d115      	bne.n	8001baa <HAL_ADC_IRQHandler+0x116>
+ 8001b7e:	687b      	ldr	r3, [r7, #4]
+ 8001b80:	681b      	ldr	r3, [r3, #0]
+ 8001b82:	685b      	ldr	r3, [r3, #4]
+ 8001b84:	2280      	movs	r2, #128	; 0x80
+ 8001b86:	4013      	ands	r3, r2
+ 8001b88:	2b80      	cmp	r3, #128	; 0x80
+ 8001b8a:	d10e      	bne.n	8001baa <HAL_ADC_IRQHandler+0x116>
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+ 8001b8c:	687b      	ldr	r3, [r7, #4]
+ 8001b8e:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001b90:	2280      	movs	r2, #128	; 0x80
+ 8001b92:	0252      	lsls	r2, r2, #9
+ 8001b94:	431a      	orrs	r2, r3
+ 8001b96:	687b      	ldr	r3, [r7, #4]
+ 8001b98:	655a      	str	r2, [r3, #84]	; 0x54
+    
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->LevelOutOfWindowCallback(hadc);
+#else
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+ 8001b9a:	687b      	ldr	r3, [r7, #4]
+ 8001b9c:	0018      	movs	r0, r3
+ 8001b9e:	f000 f83d 	bl	8001c1c <HAL_ADC_LevelOutOfWindowCallback>
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    
+    /* Clear ADC Analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ 8001ba2:	687b      	ldr	r3, [r7, #4]
+ 8001ba4:	681b      	ldr	r3, [r3, #0]
+ 8001ba6:	2280      	movs	r2, #128	; 0x80
+ 8001ba8:	601a      	str	r2, [r3, #0]
+   
+  }
+  
+  
+  /* ========== Check Overrun flag ========== */
+  if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
+ 8001baa:	687b      	ldr	r3, [r7, #4]
+ 8001bac:	681b      	ldr	r3, [r3, #0]
+ 8001bae:	681b      	ldr	r3, [r3, #0]
+ 8001bb0:	2210      	movs	r2, #16
+ 8001bb2:	4013      	ands	r3, r2
+ 8001bb4:	2b10      	cmp	r3, #16
+ 8001bb6:	d123      	bne.n	8001c00 <HAL_ADC_IRQHandler+0x16c>
+ 8001bb8:	687b      	ldr	r3, [r7, #4]
+ 8001bba:	681b      	ldr	r3, [r3, #0]
+ 8001bbc:	685b      	ldr	r3, [r3, #4]
+ 8001bbe:	2210      	movs	r2, #16
+ 8001bc0:	4013      	ands	r3, r2
+ 8001bc2:	2b10      	cmp	r3, #16
+ 8001bc4:	d11c      	bne.n	8001c00 <HAL_ADC_IRQHandler+0x16c>
+    /* overrun event is not considered as an error.                           */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    /* Exception for usage with DMA overrun event always considered as an     */
+    /* error.                                                                 */
+    if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)            ||
+ 8001bc6:	687b      	ldr	r3, [r7, #4]
+ 8001bc8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8001bca:	2b00      	cmp	r3, #0
+ 8001bcc:	d006      	beq.n	8001bdc <HAL_ADC_IRQHandler+0x148>
+        HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)  )
+ 8001bce:	687b      	ldr	r3, [r7, #4]
+ 8001bd0:	681b      	ldr	r3, [r3, #0]
+ 8001bd2:	68db      	ldr	r3, [r3, #12]
+ 8001bd4:	2201      	movs	r2, #1
+ 8001bd6:	4013      	ands	r3, r2
+    if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)            ||
+ 8001bd8:	2b01      	cmp	r3, #1
+ 8001bda:	d10d      	bne.n	8001bf8 <HAL_ADC_IRQHandler+0x164>
+    {
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ 8001bdc:	687b      	ldr	r3, [r7, #4]
+ 8001bde:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8001be0:	2202      	movs	r2, #2
+ 8001be2:	431a      	orrs	r2, r3
+ 8001be4:	687b      	ldr	r3, [r7, #4]
+ 8001be6:	659a      	str	r2, [r3, #88]	; 0x58
+      
+      /* Clear ADC overrun flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ 8001be8:	687b      	ldr	r3, [r7, #4]
+ 8001bea:	681b      	ldr	r3, [r3, #0]
+ 8001bec:	2210      	movs	r2, #16
+ 8001bee:	601a      	str	r2, [r3, #0]
+      
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+ 8001bf0:	687b      	ldr	r3, [r7, #4]
+ 8001bf2:	0018      	movs	r0, r3
+ 8001bf4:	f000 f81a 	bl	8001c2c <HAL_ADC_ErrorCallback>
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+    
+    /* Clear the Overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ 8001bf8:	687b      	ldr	r3, [r7, #4]
+ 8001bfa:	681b      	ldr	r3, [r3, #0]
+ 8001bfc:	2210      	movs	r2, #16
+ 8001bfe:	601a      	str	r2, [r3, #0]
+  }
+  
+}
+ 8001c00:	46c0      	nop			; (mov r8, r8)
+ 8001c02:	46bd      	mov	sp, r7
+ 8001c04:	b002      	add	sp, #8
+ 8001c06:	bd80      	pop	{r7, pc}
+ 8001c08:	fffffefe 	.word	0xfffffefe
+
+08001c0c <HAL_ADC_ConvCpltCallback>:
+  * @brief  Conversion complete callback in non-blocking mode.
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ 8001c0c:	b580      	push	{r7, lr}
+ 8001c0e:	b082      	sub	sp, #8
+ 8001c10:	af00      	add	r7, sp, #0
+ 8001c12:	6078      	str	r0, [r7, #4]
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+   */
+}
+ 8001c14:	46c0      	nop			; (mov r8, r8)
+ 8001c16:	46bd      	mov	sp, r7
+ 8001c18:	b002      	add	sp, #8
+ 8001c1a:	bd80      	pop	{r7, pc}
+
+08001c1c <HAL_ADC_LevelOutOfWindowCallback>:
+  * @brief  Analog watchdog 1 callback in non-blocking mode.
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+ 8001c1c:	b580      	push	{r7, lr}
+ 8001c1e:	b082      	sub	sp, #8
+ 8001c20:	af00      	add	r7, sp, #0
+ 8001c22:	6078      	str	r0, [r7, #4]
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+  */
+}
+ 8001c24:	46c0      	nop			; (mov r8, r8)
+ 8001c26:	46bd      	mov	sp, r7
+ 8001c28:	b002      	add	sp, #8
+ 8001c2a:	bd80      	pop	{r7, pc}
+
+08001c2c <HAL_ADC_ErrorCallback>:
+  *           (this function is also clearing overrun flag)
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ 8001c2c:	b580      	push	{r7, lr}
+ 8001c2e:	b082      	sub	sp, #8
+ 8001c30:	af00      	add	r7, sp, #0
+ 8001c32:	6078      	str	r0, [r7, #4]
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+ 8001c34:	46c0      	nop			; (mov r8, r8)
+ 8001c36:	46bd      	mov	sp, r7
+ 8001c38:	b002      	add	sp, #8
+ 8001c3a:	bd80      	pop	{r7, pc}
+
+08001c3c <HAL_ADC_ConfigChannel>:
+  * @param  hadc ADC handle
+  * @param  sConfig Structure of ADC channel assigned to ADC group regular.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ 8001c3c:	b580      	push	{r7, lr}
+ 8001c3e:	b082      	sub	sp, #8
+ 8001c40:	af00      	add	r7, sp, #0
+ 8001c42:	6078      	str	r0, [r7, #4]
+ 8001c44:	6039      	str	r1, [r7, #0]
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+  assert_param(IS_ADC_RANK(sConfig->Rank));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+ 8001c46:	687b      	ldr	r3, [r7, #4]
+ 8001c48:	2250      	movs	r2, #80	; 0x50
+ 8001c4a:	5c9b      	ldrb	r3, [r3, r2]
+ 8001c4c:	2b01      	cmp	r3, #1
+ 8001c4e:	d101      	bne.n	8001c54 <HAL_ADC_ConfigChannel+0x18>
+ 8001c50:	2302      	movs	r3, #2
+ 8001c52:	e050      	b.n	8001cf6 <HAL_ADC_ConfigChannel+0xba>
+ 8001c54:	687b      	ldr	r3, [r7, #4]
+ 8001c56:	2250      	movs	r2, #80	; 0x50
+ 8001c58:	2101      	movs	r1, #1
+ 8001c5a:	5499      	strb	r1, [r3, r2]
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Management of internal measurement channels: Vbat/VrefInt/TempSensor  */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)
+ 8001c5c:	687b      	ldr	r3, [r7, #4]
+ 8001c5e:	681b      	ldr	r3, [r3, #0]
+ 8001c60:	689b      	ldr	r3, [r3, #8]
+ 8001c62:	2204      	movs	r2, #4
+ 8001c64:	4013      	ands	r3, r2
+ 8001c66:	d00b      	beq.n	8001c80 <HAL_ADC_ConfigChannel+0x44>
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8001c68:	687b      	ldr	r3, [r7, #4]
+ 8001c6a:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001c6c:	2220      	movs	r2, #32
+ 8001c6e:	431a      	orrs	r2, r3
+ 8001c70:	687b      	ldr	r3, [r7, #4]
+ 8001c72:	655a      	str	r2, [r3, #84]	; 0x54
+    /* Process unlocked */
+    __HAL_UNLOCK(hadc);
+ 8001c74:	687b      	ldr	r3, [r7, #4]
+ 8001c76:	2250      	movs	r2, #80	; 0x50
+ 8001c78:	2100      	movs	r1, #0
+ 8001c7a:	5499      	strb	r1, [r3, r2]
+    return HAL_ERROR;
+ 8001c7c:	2301      	movs	r3, #1
+ 8001c7e:	e03a      	b.n	8001cf6 <HAL_ADC_ConfigChannel+0xba>
+  }
+  
+  if (sConfig->Rank != ADC_RANK_NONE)
+ 8001c80:	683b      	ldr	r3, [r7, #0]
+ 8001c82:	685b      	ldr	r3, [r3, #4]
+ 8001c84:	4a1e      	ldr	r2, [pc, #120]	; (8001d00 <HAL_ADC_ConfigChannel+0xc4>)
+ 8001c86:	4293      	cmp	r3, r2
+ 8001c88:	d018      	beq.n	8001cbc <HAL_ADC_ConfigChannel+0x80>
+  {
+    /* Enable selected channels */
+    hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK);
+ 8001c8a:	687b      	ldr	r3, [r7, #4]
+ 8001c8c:	681b      	ldr	r3, [r3, #0]
+ 8001c8e:	6a99      	ldr	r1, [r3, #40]	; 0x28
+ 8001c90:	683b      	ldr	r3, [r7, #0]
+ 8001c92:	681b      	ldr	r3, [r3, #0]
+ 8001c94:	035b      	lsls	r3, r3, #13
+ 8001c96:	0b5a      	lsrs	r2, r3, #13
+ 8001c98:	687b      	ldr	r3, [r7, #4]
+ 8001c9a:	681b      	ldr	r3, [r3, #0]
+ 8001c9c:	430a      	orrs	r2, r1
+ 8001c9e:	629a      	str	r2, [r3, #40]	; 0x28
+      ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US);
+    }
+    #endif
+    
+    /* If VRefInt channel is selected, then enable the internal buffers and path   */
+    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
+ 8001ca0:	683b      	ldr	r3, [r7, #0]
+ 8001ca2:	681a      	ldr	r2, [r3, #0]
+ 8001ca4:	2380      	movs	r3, #128	; 0x80
+ 8001ca6:	029b      	lsls	r3, r3, #10
+ 8001ca8:	4013      	ands	r3, r2
+ 8001caa:	d01f      	beq.n	8001cec <HAL_ADC_ConfigChannel+0xb0>
+    {
+      ADC->CCR |= ADC_CCR_VREFEN;   
+ 8001cac:	4b15      	ldr	r3, [pc, #84]	; (8001d04 <HAL_ADC_ConfigChannel+0xc8>)
+ 8001cae:	681a      	ldr	r2, [r3, #0]
+ 8001cb0:	4b14      	ldr	r3, [pc, #80]	; (8001d04 <HAL_ADC_ConfigChannel+0xc8>)
+ 8001cb2:	2180      	movs	r1, #128	; 0x80
+ 8001cb4:	03c9      	lsls	r1, r1, #15
+ 8001cb6:	430a      	orrs	r2, r1
+ 8001cb8:	601a      	str	r2, [r3, #0]
+ 8001cba:	e017      	b.n	8001cec <HAL_ADC_ConfigChannel+0xb0>
+  }
+  else
+  {
+    /* Regular sequence configuration */
+    /* Reset the channel selection register from the selected channel */
+    hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK));
+ 8001cbc:	687b      	ldr	r3, [r7, #4]
+ 8001cbe:	681b      	ldr	r3, [r3, #0]
+ 8001cc0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8001cc2:	683b      	ldr	r3, [r7, #0]
+ 8001cc4:	681b      	ldr	r3, [r3, #0]
+ 8001cc6:	035b      	lsls	r3, r3, #13
+ 8001cc8:	0b5b      	lsrs	r3, r3, #13
+ 8001cca:	43d9      	mvns	r1, r3
+ 8001ccc:	687b      	ldr	r3, [r7, #4]
+ 8001cce:	681b      	ldr	r3, [r3, #0]
+ 8001cd0:	400a      	ands	r2, r1
+ 8001cd2:	629a      	str	r2, [r3, #40]	; 0x28
+      ADC->CCR &= ~ADC_CCR_TSEN;   
+    }
+    #endif
+    
+    /* If VRefInt channel is selected, then enable the internal buffers and path   */
+    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
+ 8001cd4:	683b      	ldr	r3, [r7, #0]
+ 8001cd6:	681a      	ldr	r2, [r3, #0]
+ 8001cd8:	2380      	movs	r3, #128	; 0x80
+ 8001cda:	029b      	lsls	r3, r3, #10
+ 8001cdc:	4013      	ands	r3, r2
+ 8001cde:	d005      	beq.n	8001cec <HAL_ADC_ConfigChannel+0xb0>
+    {
+      ADC->CCR &= ~ADC_CCR_VREFEN;   
+ 8001ce0:	4b08      	ldr	r3, [pc, #32]	; (8001d04 <HAL_ADC_ConfigChannel+0xc8>)
+ 8001ce2:	681a      	ldr	r2, [r3, #0]
+ 8001ce4:	4b07      	ldr	r3, [pc, #28]	; (8001d04 <HAL_ADC_ConfigChannel+0xc8>)
+ 8001ce6:	4908      	ldr	r1, [pc, #32]	; (8001d08 <HAL_ADC_ConfigChannel+0xcc>)
+ 8001ce8:	400a      	ands	r2, r1
+ 8001cea:	601a      	str	r2, [r3, #0]
+    }
+#endif
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+ 8001cec:	687b      	ldr	r3, [r7, #4]
+ 8001cee:	2250      	movs	r2, #80	; 0x50
+ 8001cf0:	2100      	movs	r1, #0
+ 8001cf2:	5499      	strb	r1, [r3, r2]
+  
+  /* Return function status */
+  return HAL_OK;
+ 8001cf4:	2300      	movs	r3, #0
+}
+ 8001cf6:	0018      	movs	r0, r3
+ 8001cf8:	46bd      	mov	sp, r7
+ 8001cfa:	b002      	add	sp, #8
+ 8001cfc:	bd80      	pop	{r7, pc}
+ 8001cfe:	46c0      	nop			; (mov r8, r8)
+ 8001d00:	00001001 	.word	0x00001001
+ 8001d04:	40012708 	.word	0x40012708
+ 8001d08:	ffbfffff 	.word	0xffbfffff
+
+08001d0c <__NVIC_EnableIRQ>:
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ 8001d0c:	b580      	push	{r7, lr}
+ 8001d0e:	b082      	sub	sp, #8
+ 8001d10:	af00      	add	r7, sp, #0
+ 8001d12:	0002      	movs	r2, r0
+ 8001d14:	1dfb      	adds	r3, r7, #7
+ 8001d16:	701a      	strb	r2, [r3, #0]
+  if ((int32_t)(IRQn) >= 0)
+ 8001d18:	1dfb      	adds	r3, r7, #7
+ 8001d1a:	781b      	ldrb	r3, [r3, #0]
+ 8001d1c:	2b7f      	cmp	r3, #127	; 0x7f
+ 8001d1e:	d809      	bhi.n	8001d34 <__NVIC_EnableIRQ+0x28>
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 8001d20:	1dfb      	adds	r3, r7, #7
+ 8001d22:	781b      	ldrb	r3, [r3, #0]
+ 8001d24:	001a      	movs	r2, r3
+ 8001d26:	231f      	movs	r3, #31
+ 8001d28:	401a      	ands	r2, r3
+ 8001d2a:	4b04      	ldr	r3, [pc, #16]	; (8001d3c <__NVIC_EnableIRQ+0x30>)
+ 8001d2c:	2101      	movs	r1, #1
+ 8001d2e:	4091      	lsls	r1, r2
+ 8001d30:	000a      	movs	r2, r1
+ 8001d32:	601a      	str	r2, [r3, #0]
+  }
+}
+ 8001d34:	46c0      	nop			; (mov r8, r8)
+ 8001d36:	46bd      	mov	sp, r7
+ 8001d38:	b002      	add	sp, #8
+ 8001d3a:	bd80      	pop	{r7, pc}
+ 8001d3c:	e000e100 	.word	0xe000e100
+
+08001d40 <__NVIC_SetPriority>:
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 8001d40:	b590      	push	{r4, r7, lr}
+ 8001d42:	b083      	sub	sp, #12
+ 8001d44:	af00      	add	r7, sp, #0
+ 8001d46:	0002      	movs	r2, r0
+ 8001d48:	6039      	str	r1, [r7, #0]
+ 8001d4a:	1dfb      	adds	r3, r7, #7
+ 8001d4c:	701a      	strb	r2, [r3, #0]
+  if ((int32_t)(IRQn) >= 0)
+ 8001d4e:	1dfb      	adds	r3, r7, #7
+ 8001d50:	781b      	ldrb	r3, [r3, #0]
+ 8001d52:	2b7f      	cmp	r3, #127	; 0x7f
+ 8001d54:	d828      	bhi.n	8001da8 <__NVIC_SetPriority+0x68>
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8001d56:	4a2f      	ldr	r2, [pc, #188]	; (8001e14 <__NVIC_SetPriority+0xd4>)
+ 8001d58:	1dfb      	adds	r3, r7, #7
+ 8001d5a:	781b      	ldrb	r3, [r3, #0]
+ 8001d5c:	b25b      	sxtb	r3, r3
+ 8001d5e:	089b      	lsrs	r3, r3, #2
+ 8001d60:	33c0      	adds	r3, #192	; 0xc0
+ 8001d62:	009b      	lsls	r3, r3, #2
+ 8001d64:	589b      	ldr	r3, [r3, r2]
+ 8001d66:	1dfa      	adds	r2, r7, #7
+ 8001d68:	7812      	ldrb	r2, [r2, #0]
+ 8001d6a:	0011      	movs	r1, r2
+ 8001d6c:	2203      	movs	r2, #3
+ 8001d6e:	400a      	ands	r2, r1
+ 8001d70:	00d2      	lsls	r2, r2, #3
+ 8001d72:	21ff      	movs	r1, #255	; 0xff
+ 8001d74:	4091      	lsls	r1, r2
+ 8001d76:	000a      	movs	r2, r1
+ 8001d78:	43d2      	mvns	r2, r2
+ 8001d7a:	401a      	ands	r2, r3
+ 8001d7c:	0011      	movs	r1, r2
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 8001d7e:	683b      	ldr	r3, [r7, #0]
+ 8001d80:	019b      	lsls	r3, r3, #6
+ 8001d82:	22ff      	movs	r2, #255	; 0xff
+ 8001d84:	401a      	ands	r2, r3
+ 8001d86:	1dfb      	adds	r3, r7, #7
+ 8001d88:	781b      	ldrb	r3, [r3, #0]
+ 8001d8a:	0018      	movs	r0, r3
+ 8001d8c:	2303      	movs	r3, #3
+ 8001d8e:	4003      	ands	r3, r0
+ 8001d90:	00db      	lsls	r3, r3, #3
+ 8001d92:	409a      	lsls	r2, r3
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8001d94:	481f      	ldr	r0, [pc, #124]	; (8001e14 <__NVIC_SetPriority+0xd4>)
+ 8001d96:	1dfb      	adds	r3, r7, #7
+ 8001d98:	781b      	ldrb	r3, [r3, #0]
+ 8001d9a:	b25b      	sxtb	r3, r3
+ 8001d9c:	089b      	lsrs	r3, r3, #2
+ 8001d9e:	430a      	orrs	r2, r1
+ 8001da0:	33c0      	adds	r3, #192	; 0xc0
+ 8001da2:	009b      	lsls	r3, r3, #2
+ 8001da4:	501a      	str	r2, [r3, r0]
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+ 8001da6:	e031      	b.n	8001e0c <__NVIC_SetPriority+0xcc>
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8001da8:	4a1b      	ldr	r2, [pc, #108]	; (8001e18 <__NVIC_SetPriority+0xd8>)
+ 8001daa:	1dfb      	adds	r3, r7, #7
+ 8001dac:	781b      	ldrb	r3, [r3, #0]
+ 8001dae:	0019      	movs	r1, r3
+ 8001db0:	230f      	movs	r3, #15
+ 8001db2:	400b      	ands	r3, r1
+ 8001db4:	3b08      	subs	r3, #8
+ 8001db6:	089b      	lsrs	r3, r3, #2
+ 8001db8:	3306      	adds	r3, #6
+ 8001dba:	009b      	lsls	r3, r3, #2
+ 8001dbc:	18d3      	adds	r3, r2, r3
+ 8001dbe:	3304      	adds	r3, #4
+ 8001dc0:	681b      	ldr	r3, [r3, #0]
+ 8001dc2:	1dfa      	adds	r2, r7, #7
+ 8001dc4:	7812      	ldrb	r2, [r2, #0]
+ 8001dc6:	0011      	movs	r1, r2
+ 8001dc8:	2203      	movs	r2, #3
+ 8001dca:	400a      	ands	r2, r1
+ 8001dcc:	00d2      	lsls	r2, r2, #3
+ 8001dce:	21ff      	movs	r1, #255	; 0xff
+ 8001dd0:	4091      	lsls	r1, r2
+ 8001dd2:	000a      	movs	r2, r1
+ 8001dd4:	43d2      	mvns	r2, r2
+ 8001dd6:	401a      	ands	r2, r3
+ 8001dd8:	0011      	movs	r1, r2
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 8001dda:	683b      	ldr	r3, [r7, #0]
+ 8001ddc:	019b      	lsls	r3, r3, #6
+ 8001dde:	22ff      	movs	r2, #255	; 0xff
+ 8001de0:	401a      	ands	r2, r3
+ 8001de2:	1dfb      	adds	r3, r7, #7
+ 8001de4:	781b      	ldrb	r3, [r3, #0]
+ 8001de6:	0018      	movs	r0, r3
+ 8001de8:	2303      	movs	r3, #3
+ 8001dea:	4003      	ands	r3, r0
+ 8001dec:	00db      	lsls	r3, r3, #3
+ 8001dee:	409a      	lsls	r2, r3
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8001df0:	4809      	ldr	r0, [pc, #36]	; (8001e18 <__NVIC_SetPriority+0xd8>)
+ 8001df2:	1dfb      	adds	r3, r7, #7
+ 8001df4:	781b      	ldrb	r3, [r3, #0]
+ 8001df6:	001c      	movs	r4, r3
+ 8001df8:	230f      	movs	r3, #15
+ 8001dfa:	4023      	ands	r3, r4
+ 8001dfc:	3b08      	subs	r3, #8
+ 8001dfe:	089b      	lsrs	r3, r3, #2
+ 8001e00:	430a      	orrs	r2, r1
+ 8001e02:	3306      	adds	r3, #6
+ 8001e04:	009b      	lsls	r3, r3, #2
+ 8001e06:	18c3      	adds	r3, r0, r3
+ 8001e08:	3304      	adds	r3, #4
+ 8001e0a:	601a      	str	r2, [r3, #0]
+}
+ 8001e0c:	46c0      	nop			; (mov r8, r8)
+ 8001e0e:	46bd      	mov	sp, r7
+ 8001e10:	b003      	add	sp, #12
+ 8001e12:	bd90      	pop	{r4, r7, pc}
+ 8001e14:	e000e100 	.word	0xe000e100
+ 8001e18:	e000ed00 	.word	0xe000ed00
+
+08001e1c <SysTick_Config>:
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ 8001e1c:	b580      	push	{r7, lr}
+ 8001e1e:	b082      	sub	sp, #8
+ 8001e20:	af00      	add	r7, sp, #0
+ 8001e22:	6078      	str	r0, [r7, #4]
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 8001e24:	687b      	ldr	r3, [r7, #4]
+ 8001e26:	1e5a      	subs	r2, r3, #1
+ 8001e28:	2380      	movs	r3, #128	; 0x80
+ 8001e2a:	045b      	lsls	r3, r3, #17
+ 8001e2c:	429a      	cmp	r2, r3
+ 8001e2e:	d301      	bcc.n	8001e34 <SysTick_Config+0x18>
+  {
+    return (1UL);                                                   /* Reload value impossible */
+ 8001e30:	2301      	movs	r3, #1
+ 8001e32:	e010      	b.n	8001e56 <SysTick_Config+0x3a>
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+ 8001e34:	4b0a      	ldr	r3, [pc, #40]	; (8001e60 <SysTick_Config+0x44>)
+ 8001e36:	687a      	ldr	r2, [r7, #4]
+ 8001e38:	3a01      	subs	r2, #1
+ 8001e3a:	605a      	str	r2, [r3, #4]
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8001e3c:	2301      	movs	r3, #1
+ 8001e3e:	425b      	negs	r3, r3
+ 8001e40:	2103      	movs	r1, #3
+ 8001e42:	0018      	movs	r0, r3
+ 8001e44:	f7ff ff7c 	bl	8001d40 <__NVIC_SetPriority>
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+ 8001e48:	4b05      	ldr	r3, [pc, #20]	; (8001e60 <SysTick_Config+0x44>)
+ 8001e4a:	2200      	movs	r2, #0
+ 8001e4c:	609a      	str	r2, [r3, #8]
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 8001e4e:	4b04      	ldr	r3, [pc, #16]	; (8001e60 <SysTick_Config+0x44>)
+ 8001e50:	2207      	movs	r2, #7
+ 8001e52:	601a      	str	r2, [r3, #0]
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+ 8001e54:	2300      	movs	r3, #0
+}
+ 8001e56:	0018      	movs	r0, r3
+ 8001e58:	46bd      	mov	sp, r7
+ 8001e5a:	b002      	add	sp, #8
+ 8001e5c:	bd80      	pop	{r7, pc}
+ 8001e5e:	46c0      	nop			; (mov r8, r8)
+ 8001e60:	e000e010 	.word	0xe000e010
+
+08001e64 <HAL_NVIC_SetPriority>:
+  *         with stm32l0xx devices, this parameter is a dummy value and it is ignored, because 
+  *         no subpriority supported in Cortex M0+ based products.   
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{ 
+ 8001e64:	b580      	push	{r7, lr}
+ 8001e66:	b084      	sub	sp, #16
+ 8001e68:	af00      	add	r7, sp, #0
+ 8001e6a:	60b9      	str	r1, [r7, #8]
+ 8001e6c:	607a      	str	r2, [r7, #4]
+ 8001e6e:	210f      	movs	r1, #15
+ 8001e70:	187b      	adds	r3, r7, r1
+ 8001e72:	1c02      	adds	r2, r0, #0
+ 8001e74:	701a      	strb	r2, [r3, #0]
+    /* Check the parameters */
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  NVIC_SetPriority(IRQn,PreemptPriority);
+ 8001e76:	68ba      	ldr	r2, [r7, #8]
+ 8001e78:	187b      	adds	r3, r7, r1
+ 8001e7a:	781b      	ldrb	r3, [r3, #0]
+ 8001e7c:	b25b      	sxtb	r3, r3
+ 8001e7e:	0011      	movs	r1, r2
+ 8001e80:	0018      	movs	r0, r3
+ 8001e82:	f7ff ff5d 	bl	8001d40 <__NVIC_SetPriority>
+}
+ 8001e86:	46c0      	nop			; (mov r8, r8)
+ 8001e88:	46bd      	mov	sp, r7
+ 8001e8a:	b004      	add	sp, #16
+ 8001e8c:	bd80      	pop	{r7, pc}
+
+08001e8e <HAL_NVIC_EnableIRQ>:
+  *         This parameter can be an enumerator of  IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)  
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ 8001e8e:	b580      	push	{r7, lr}
+ 8001e90:	b082      	sub	sp, #8
+ 8001e92:	af00      	add	r7, sp, #0
+ 8001e94:	0002      	movs	r2, r0
+ 8001e96:	1dfb      	adds	r3, r7, #7
+ 8001e98:	701a      	strb	r2, [r3, #0]
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+ 8001e9a:	1dfb      	adds	r3, r7, #7
+ 8001e9c:	781b      	ldrb	r3, [r3, #0]
+ 8001e9e:	b25b      	sxtb	r3, r3
+ 8001ea0:	0018      	movs	r0, r3
+ 8001ea2:	f7ff ff33 	bl	8001d0c <__NVIC_EnableIRQ>
+}
+ 8001ea6:	46c0      	nop			; (mov r8, r8)
+ 8001ea8:	46bd      	mov	sp, r7
+ 8001eaa:	b002      	add	sp, #8
+ 8001eac:	bd80      	pop	{r7, pc}
+
+08001eae <HAL_SYSTICK_Config>:
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 8001eae:	b580      	push	{r7, lr}
+ 8001eb0:	b082      	sub	sp, #8
+ 8001eb2:	af00      	add	r7, sp, #0
+ 8001eb4:	6078      	str	r0, [r7, #4]
+   return SysTick_Config(TicksNumb);
+ 8001eb6:	687b      	ldr	r3, [r7, #4]
+ 8001eb8:	0018      	movs	r0, r3
+ 8001eba:	f7ff ffaf 	bl	8001e1c <SysTick_Config>
+ 8001ebe:	0003      	movs	r3, r0
+}
+ 8001ec0:	0018      	movs	r0, r3
+ 8001ec2:	46bd      	mov	sp, r7
+ 8001ec4:	b002      	add	sp, #8
+ 8001ec6:	bd80      	pop	{r7, pc}
+
+08001ec8 <HAL_DMA_Init>:
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ 8001ec8:	b580      	push	{r7, lr}
+ 8001eca:	b084      	sub	sp, #16
+ 8001ecc:	af00      	add	r7, sp, #0
+ 8001ece:	6078      	str	r0, [r7, #4]
+  uint32_t tmp;
+
+  /* Check the DMA handle allocation */
+  if(hdma == NULL)
+ 8001ed0:	687b      	ldr	r3, [r7, #4]
+ 8001ed2:	2b00      	cmp	r3, #0
+ 8001ed4:	d101      	bne.n	8001eda <HAL_DMA_Init+0x12>
+  {
+    return HAL_ERROR;
+ 8001ed6:	2301      	movs	r3, #1
+ 8001ed8:	e061      	b.n	8001f9e <HAL_DMA_Init+0xd6>
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  /* Compute the channel index */
+  /* Only one DMA: DMA1 */
+  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+ 8001eda:	687b      	ldr	r3, [r7, #4]
+ 8001edc:	681b      	ldr	r3, [r3, #0]
+ 8001ede:	4a32      	ldr	r2, [pc, #200]	; (8001fa8 <HAL_DMA_Init+0xe0>)
+ 8001ee0:	4694      	mov	ip, r2
+ 8001ee2:	4463      	add	r3, ip
+ 8001ee4:	2114      	movs	r1, #20
+ 8001ee6:	0018      	movs	r0, r3
+ 8001ee8:	f7fe f90e 	bl	8000108 <__udivsi3>
+ 8001eec:	0003      	movs	r3, r0
+ 8001eee:	009a      	lsls	r2, r3, #2
+ 8001ef0:	687b      	ldr	r3, [r7, #4]
+ 8001ef2:	645a      	str	r2, [r3, #68]	; 0x44
+  hdma->DmaBaseAddress = DMA1;
+ 8001ef4:	687b      	ldr	r3, [r7, #4]
+ 8001ef6:	4a2d      	ldr	r2, [pc, #180]	; (8001fac <HAL_DMA_Init+0xe4>)
+ 8001ef8:	641a      	str	r2, [r3, #64]	; 0x40
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+ 8001efa:	687b      	ldr	r3, [r7, #4]
+ 8001efc:	2225      	movs	r2, #37	; 0x25
+ 8001efe:	2102      	movs	r1, #2
+ 8001f00:	5499      	strb	r1, [r3, r2]
+
+  /* Get the CR register value */
+  tmp = hdma->Instance->CCR;
+ 8001f02:	687b      	ldr	r3, [r7, #4]
+ 8001f04:	681b      	ldr	r3, [r3, #0]
+ 8001f06:	681b      	ldr	r3, [r3, #0]
+ 8001f08:	60fb      	str	r3, [r7, #12]
+
+  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
+  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |
+ 8001f0a:	68fb      	ldr	r3, [r7, #12]
+ 8001f0c:	4a28      	ldr	r2, [pc, #160]	; (8001fb0 <HAL_DMA_Init+0xe8>)
+ 8001f0e:	4013      	ands	r3, r2
+ 8001f10:	60fb      	str	r3, [r7, #12]
+                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
+                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
+
+  /* Prepare the DMA Channel configuration */
+  tmp |=  hdma->Init.Direction        |
+ 8001f12:	687b      	ldr	r3, [r7, #4]
+ 8001f14:	689a      	ldr	r2, [r3, #8]
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8001f16:	687b      	ldr	r3, [r7, #4]
+ 8001f18:	68db      	ldr	r3, [r3, #12]
+  tmp |=  hdma->Init.Direction        |
+ 8001f1a:	431a      	orrs	r2, r3
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8001f1c:	687b      	ldr	r3, [r7, #4]
+ 8001f1e:	691b      	ldr	r3, [r3, #16]
+ 8001f20:	431a      	orrs	r2, r3
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8001f22:	687b      	ldr	r3, [r7, #4]
+ 8001f24:	695b      	ldr	r3, [r3, #20]
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8001f26:	431a      	orrs	r2, r3
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8001f28:	687b      	ldr	r3, [r7, #4]
+ 8001f2a:	699b      	ldr	r3, [r3, #24]
+ 8001f2c:	431a      	orrs	r2, r3
+          hdma->Init.Mode                | hdma->Init.Priority;
+ 8001f2e:	687b      	ldr	r3, [r7, #4]
+ 8001f30:	69db      	ldr	r3, [r3, #28]
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8001f32:	431a      	orrs	r2, r3
+          hdma->Init.Mode                | hdma->Init.Priority;
+ 8001f34:	687b      	ldr	r3, [r7, #4]
+ 8001f36:	6a1b      	ldr	r3, [r3, #32]
+ 8001f38:	4313      	orrs	r3, r2
+  tmp |=  hdma->Init.Direction        |
+ 8001f3a:	68fa      	ldr	r2, [r7, #12]
+ 8001f3c:	4313      	orrs	r3, r2
+ 8001f3e:	60fb      	str	r3, [r7, #12]
+
+  /* Write to DMA Channel CR register */
+  hdma->Instance->CCR = tmp;
+ 8001f40:	687b      	ldr	r3, [r7, #4]
+ 8001f42:	681b      	ldr	r3, [r3, #0]
+ 8001f44:	68fa      	ldr	r2, [r7, #12]
+ 8001f46:	601a      	str	r2, [r3, #0]
+
+  /* Set request selection */
+  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
+ 8001f48:	687b      	ldr	r3, [r7, #4]
+ 8001f4a:	689a      	ldr	r2, [r3, #8]
+ 8001f4c:	2380      	movs	r3, #128	; 0x80
+ 8001f4e:	01db      	lsls	r3, r3, #7
+ 8001f50:	429a      	cmp	r2, r3
+ 8001f52:	d018      	beq.n	8001f86 <HAL_DMA_Init+0xbe>
+  {
+    /* Write to DMA channel selection register */
+    /* Reset request selection for DMA1 Channelx */
+    DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
+ 8001f54:	4b17      	ldr	r3, [pc, #92]	; (8001fb4 <HAL_DMA_Init+0xec>)
+ 8001f56:	681a      	ldr	r2, [r3, #0]
+ 8001f58:	687b      	ldr	r3, [r7, #4]
+ 8001f5a:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8001f5c:	211c      	movs	r1, #28
+ 8001f5e:	400b      	ands	r3, r1
+ 8001f60:	210f      	movs	r1, #15
+ 8001f62:	4099      	lsls	r1, r3
+ 8001f64:	000b      	movs	r3, r1
+ 8001f66:	43d9      	mvns	r1, r3
+ 8001f68:	4b12      	ldr	r3, [pc, #72]	; (8001fb4 <HAL_DMA_Init+0xec>)
+ 8001f6a:	400a      	ands	r2, r1
+ 8001f6c:	601a      	str	r2, [r3, #0]
+
+    /* Configure request selection for DMA1 Channelx */
+    DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
+ 8001f6e:	4b11      	ldr	r3, [pc, #68]	; (8001fb4 <HAL_DMA_Init+0xec>)
+ 8001f70:	6819      	ldr	r1, [r3, #0]
+ 8001f72:	687b      	ldr	r3, [r7, #4]
+ 8001f74:	685a      	ldr	r2, [r3, #4]
+ 8001f76:	687b      	ldr	r3, [r7, #4]
+ 8001f78:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8001f7a:	201c      	movs	r0, #28
+ 8001f7c:	4003      	ands	r3, r0
+ 8001f7e:	409a      	lsls	r2, r3
+ 8001f80:	4b0c      	ldr	r3, [pc, #48]	; (8001fb4 <HAL_DMA_Init+0xec>)
+ 8001f82:	430a      	orrs	r2, r1
+ 8001f84:	601a      	str	r2, [r3, #0]
+  }
+
+  /* Initialise the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8001f86:	687b      	ldr	r3, [r7, #4]
+ 8001f88:	2200      	movs	r2, #0
+ 8001f8a:	63da      	str	r2, [r3, #60]	; 0x3c
+
+  /* Initialize the DMA state*/
+  hdma->State  = HAL_DMA_STATE_READY;
+ 8001f8c:	687b      	ldr	r3, [r7, #4]
+ 8001f8e:	2225      	movs	r2, #37	; 0x25
+ 8001f90:	2101      	movs	r1, #1
+ 8001f92:	5499      	strb	r1, [r3, r2]
+
+  /* Allocate lock resource and initialize it */
+  hdma->Lock = HAL_UNLOCKED;
+ 8001f94:	687b      	ldr	r3, [r7, #4]
+ 8001f96:	2224      	movs	r2, #36	; 0x24
+ 8001f98:	2100      	movs	r1, #0
+ 8001f9a:	5499      	strb	r1, [r3, r2]
+
+  return HAL_OK;
+ 8001f9c:	2300      	movs	r3, #0
+}
+ 8001f9e:	0018      	movs	r0, r3
+ 8001fa0:	46bd      	mov	sp, r7
+ 8001fa2:	b004      	add	sp, #16
+ 8001fa4:	bd80      	pop	{r7, pc}
+ 8001fa6:	46c0      	nop			; (mov r8, r8)
+ 8001fa8:	bffdfff8 	.word	0xbffdfff8
+ 8001fac:	40020000 	.word	0x40020000
+ 8001fb0:	ffff800f 	.word	0xffff800f
+ 8001fb4:	400200a8 	.word	0x400200a8
+
+08001fb8 <HAL_DMA_Abort>:
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+    * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ 8001fb8:	b580      	push	{r7, lr}
+ 8001fba:	b084      	sub	sp, #16
+ 8001fbc:	af00      	add	r7, sp, #0
+ 8001fbe:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8001fc0:	230f      	movs	r3, #15
+ 8001fc2:	18fb      	adds	r3, r7, r3
+ 8001fc4:	2200      	movs	r2, #0
+ 8001fc6:	701a      	strb	r2, [r3, #0]
+
+  /* Check the DMA peripheral state */
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+ 8001fc8:	687b      	ldr	r3, [r7, #4]
+ 8001fca:	2225      	movs	r2, #37	; 0x25
+ 8001fcc:	5c9b      	ldrb	r3, [r3, r2]
+ 8001fce:	b2db      	uxtb	r3, r3
+ 8001fd0:	2b02      	cmp	r3, #2
+ 8001fd2:	d008      	beq.n	8001fe6 <HAL_DMA_Abort+0x2e>
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 8001fd4:	687b      	ldr	r3, [r7, #4]
+ 8001fd6:	2204      	movs	r2, #4
+ 8001fd8:	63da      	str	r2, [r3, #60]	; 0x3c
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 8001fda:	687b      	ldr	r3, [r7, #4]
+ 8001fdc:	2224      	movs	r2, #36	; 0x24
+ 8001fde:	2100      	movs	r1, #0
+ 8001fe0:	5499      	strb	r1, [r3, r2]
+
+    return HAL_ERROR;
+ 8001fe2:	2301      	movs	r3, #1
+ 8001fe4:	e024      	b.n	8002030 <HAL_DMA_Abort+0x78>
+  }
+  else
+  {
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8001fe6:	687b      	ldr	r3, [r7, #4]
+ 8001fe8:	681b      	ldr	r3, [r3, #0]
+ 8001fea:	681a      	ldr	r2, [r3, #0]
+ 8001fec:	687b      	ldr	r3, [r7, #4]
+ 8001fee:	681b      	ldr	r3, [r3, #0]
+ 8001ff0:	210e      	movs	r1, #14
+ 8001ff2:	438a      	bics	r2, r1
+ 8001ff4:	601a      	str	r2, [r3, #0]
+
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+ 8001ff6:	687b      	ldr	r3, [r7, #4]
+ 8001ff8:	681b      	ldr	r3, [r3, #0]
+ 8001ffa:	681a      	ldr	r2, [r3, #0]
+ 8001ffc:	687b      	ldr	r3, [r7, #4]
+ 8001ffe:	681b      	ldr	r3, [r3, #0]
+ 8002000:	2101      	movs	r1, #1
+ 8002002:	438a      	bics	r2, r1
+ 8002004:	601a      	str	r2, [r3, #0]
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
+ 8002006:	687b      	ldr	r3, [r7, #4]
+ 8002008:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800200a:	221c      	movs	r2, #28
+ 800200c:	401a      	ands	r2, r3
+ 800200e:	687b      	ldr	r3, [r7, #4]
+ 8002010:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8002012:	2101      	movs	r1, #1
+ 8002014:	4091      	lsls	r1, r2
+ 8002016:	000a      	movs	r2, r1
+ 8002018:	605a      	str	r2, [r3, #4]
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+ 800201a:	687b      	ldr	r3, [r7, #4]
+ 800201c:	2225      	movs	r2, #37	; 0x25
+ 800201e:	2101      	movs	r1, #1
+ 8002020:	5499      	strb	r1, [r3, r2]
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 8002022:	687b      	ldr	r3, [r7, #4]
+ 8002024:	2224      	movs	r2, #36	; 0x24
+ 8002026:	2100      	movs	r1, #0
+ 8002028:	5499      	strb	r1, [r3, r2]
+
+    return status;
+ 800202a:	230f      	movs	r3, #15
+ 800202c:	18fb      	adds	r3, r7, r3
+ 800202e:	781b      	ldrb	r3, [r3, #0]
+  }
+}
+ 8002030:	0018      	movs	r0, r3
+ 8002032:	46bd      	mov	sp, r7
+ 8002034:	b004      	add	sp, #16
+ 8002036:	bd80      	pop	{r7, pc}
+
+08002038 <HAL_DMA_Abort_IT>:
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ 8002038:	b580      	push	{r7, lr}
+ 800203a:	b084      	sub	sp, #16
+ 800203c:	af00      	add	r7, sp, #0
+ 800203e:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8002040:	210f      	movs	r1, #15
+ 8002042:	187b      	adds	r3, r7, r1
+ 8002044:	2200      	movs	r2, #0
+ 8002046:	701a      	strb	r2, [r3, #0]
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+ 8002048:	687b      	ldr	r3, [r7, #4]
+ 800204a:	2225      	movs	r2, #37	; 0x25
+ 800204c:	5c9b      	ldrb	r3, [r3, r2]
+ 800204e:	b2db      	uxtb	r3, r3
+ 8002050:	2b02      	cmp	r3, #2
+ 8002052:	d006      	beq.n	8002062 <HAL_DMA_Abort_IT+0x2a>
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 8002054:	687b      	ldr	r3, [r7, #4]
+ 8002056:	2204      	movs	r2, #4
+ 8002058:	63da      	str	r2, [r3, #60]	; 0x3c
+
+    status = HAL_ERROR;
+ 800205a:	187b      	adds	r3, r7, r1
+ 800205c:	2201      	movs	r2, #1
+ 800205e:	701a      	strb	r2, [r3, #0]
+ 8002060:	e02a      	b.n	80020b8 <HAL_DMA_Abort_IT+0x80>
+  }
+  else
+  {
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8002062:	687b      	ldr	r3, [r7, #4]
+ 8002064:	681b      	ldr	r3, [r3, #0]
+ 8002066:	681a      	ldr	r2, [r3, #0]
+ 8002068:	687b      	ldr	r3, [r7, #4]
+ 800206a:	681b      	ldr	r3, [r3, #0]
+ 800206c:	210e      	movs	r1, #14
+ 800206e:	438a      	bics	r2, r1
+ 8002070:	601a      	str	r2, [r3, #0]
+
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+ 8002072:	687b      	ldr	r3, [r7, #4]
+ 8002074:	681b      	ldr	r3, [r3, #0]
+ 8002076:	681a      	ldr	r2, [r3, #0]
+ 8002078:	687b      	ldr	r3, [r7, #4]
+ 800207a:	681b      	ldr	r3, [r3, #0]
+ 800207c:	2101      	movs	r1, #1
+ 800207e:	438a      	bics	r2, r1
+ 8002080:	601a      	str	r2, [r3, #0]
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
+ 8002082:	687b      	ldr	r3, [r7, #4]
+ 8002084:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8002086:	221c      	movs	r2, #28
+ 8002088:	401a      	ands	r2, r3
+ 800208a:	687b      	ldr	r3, [r7, #4]
+ 800208c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800208e:	2101      	movs	r1, #1
+ 8002090:	4091      	lsls	r1, r2
+ 8002092:	000a      	movs	r2, r1
+ 8002094:	605a      	str	r2, [r3, #4]
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+ 8002096:	687b      	ldr	r3, [r7, #4]
+ 8002098:	2225      	movs	r2, #37	; 0x25
+ 800209a:	2101      	movs	r1, #1
+ 800209c:	5499      	strb	r1, [r3, r2]
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 800209e:	687b      	ldr	r3, [r7, #4]
+ 80020a0:	2224      	movs	r2, #36	; 0x24
+ 80020a2:	2100      	movs	r1, #0
+ 80020a4:	5499      	strb	r1, [r3, r2]
+
+    /* Call User Abort callback */
+    if(hdma->XferAbortCallback != NULL)
+ 80020a6:	687b      	ldr	r3, [r7, #4]
+ 80020a8:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80020aa:	2b00      	cmp	r3, #0
+ 80020ac:	d004      	beq.n	80020b8 <HAL_DMA_Abort_IT+0x80>
+    {
+      hdma->XferAbortCallback(hdma);
+ 80020ae:	687b      	ldr	r3, [r7, #4]
+ 80020b0:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80020b2:	687a      	ldr	r2, [r7, #4]
+ 80020b4:	0010      	movs	r0, r2
+ 80020b6:	4798      	blx	r3
+    }
+  }
+  return status;
+ 80020b8:	230f      	movs	r3, #15
+ 80020ba:	18fb      	adds	r3, r7, r3
+ 80020bc:	781b      	ldrb	r3, [r3, #0]
+}
+ 80020be:	0018      	movs	r0, r3
+ 80020c0:	46bd      	mov	sp, r7
+ 80020c2:	b004      	add	sp, #16
+ 80020c4:	bd80      	pop	{r7, pc}
+
+080020c6 <HAL_DMA_IRQHandler>:
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ 80020c6:	b580      	push	{r7, lr}
+ 80020c8:	b084      	sub	sp, #16
+ 80020ca:	af00      	add	r7, sp, #0
+ 80020cc:	6078      	str	r0, [r7, #4]
+  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ 80020ce:	687b      	ldr	r3, [r7, #4]
+ 80020d0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80020d2:	681b      	ldr	r3, [r3, #0]
+ 80020d4:	60fb      	str	r3, [r7, #12]
+  uint32_t source_it = hdma->Instance->CCR;
+ 80020d6:	687b      	ldr	r3, [r7, #4]
+ 80020d8:	681b      	ldr	r3, [r3, #0]
+ 80020da:	681b      	ldr	r3, [r3, #0]
+ 80020dc:	60bb      	str	r3, [r7, #8]
+
+  /* Half Transfer Complete Interrupt management ******************************/
+  if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT)))
+ 80020de:	687b      	ldr	r3, [r7, #4]
+ 80020e0:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 80020e2:	221c      	movs	r2, #28
+ 80020e4:	4013      	ands	r3, r2
+ 80020e6:	2204      	movs	r2, #4
+ 80020e8:	409a      	lsls	r2, r3
+ 80020ea:	0013      	movs	r3, r2
+ 80020ec:	68fa      	ldr	r2, [r7, #12]
+ 80020ee:	4013      	ands	r3, r2
+ 80020f0:	d026      	beq.n	8002140 <HAL_DMA_IRQHandler+0x7a>
+ 80020f2:	68bb      	ldr	r3, [r7, #8]
+ 80020f4:	2204      	movs	r2, #4
+ 80020f6:	4013      	ands	r3, r2
+ 80020f8:	d022      	beq.n	8002140 <HAL_DMA_IRQHandler+0x7a>
+  {
+      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ 80020fa:	687b      	ldr	r3, [r7, #4]
+ 80020fc:	681b      	ldr	r3, [r3, #0]
+ 80020fe:	681b      	ldr	r3, [r3, #0]
+ 8002100:	2220      	movs	r2, #32
+ 8002102:	4013      	ands	r3, r2
+ 8002104:	d107      	bne.n	8002116 <HAL_DMA_IRQHandler+0x50>
+      {
+        /* Disable the half transfer interrupt */
+        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 8002106:	687b      	ldr	r3, [r7, #4]
+ 8002108:	681b      	ldr	r3, [r3, #0]
+ 800210a:	681a      	ldr	r2, [r3, #0]
+ 800210c:	687b      	ldr	r3, [r7, #4]
+ 800210e:	681b      	ldr	r3, [r3, #0]
+ 8002110:	2104      	movs	r1, #4
+ 8002112:	438a      	bics	r2, r1
+ 8002114:	601a      	str	r2, [r3, #0]
+      }
+      /* Clear the half transfer complete flag */
+      hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU);
+ 8002116:	687b      	ldr	r3, [r7, #4]
+ 8002118:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800211a:	221c      	movs	r2, #28
+ 800211c:	401a      	ands	r2, r3
+ 800211e:	687b      	ldr	r3, [r7, #4]
+ 8002120:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8002122:	2104      	movs	r1, #4
+ 8002124:	4091      	lsls	r1, r2
+ 8002126:	000a      	movs	r2, r1
+ 8002128:	605a      	str	r2, [r3, #4]
+
+      /* DMA peripheral state is not updated in Half Transfer */
+      /* but in Transfer Complete case */
+
+     if(hdma->XferHalfCpltCallback != NULL)
+ 800212a:	687b      	ldr	r3, [r7, #4]
+ 800212c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800212e:	2b00      	cmp	r3, #0
+ 8002130:	d100      	bne.n	8002134 <HAL_DMA_IRQHandler+0x6e>
+ 8002132:	e071      	b.n	8002218 <HAL_DMA_IRQHandler+0x152>
+      {
+        /* Half transfer callback */
+        hdma->XferHalfCpltCallback(hdma);
+ 8002134:	687b      	ldr	r3, [r7, #4]
+ 8002136:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8002138:	687a      	ldr	r2, [r7, #4]
+ 800213a:	0010      	movs	r0, r2
+ 800213c:	4798      	blx	r3
+     if(hdma->XferHalfCpltCallback != NULL)
+ 800213e:	e06b      	b.n	8002218 <HAL_DMA_IRQHandler+0x152>
+      }
+  }
+
+  /* Transfer Complete Interrupt management ***********************************/
+  else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
+ 8002140:	687b      	ldr	r3, [r7, #4]
+ 8002142:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8002144:	221c      	movs	r2, #28
+ 8002146:	4013      	ands	r3, r2
+ 8002148:	2202      	movs	r2, #2
+ 800214a:	409a      	lsls	r2, r3
+ 800214c:	0013      	movs	r3, r2
+ 800214e:	68fa      	ldr	r2, [r7, #12]
+ 8002150:	4013      	ands	r3, r2
+ 8002152:	d02d      	beq.n	80021b0 <HAL_DMA_IRQHandler+0xea>
+ 8002154:	68bb      	ldr	r3, [r7, #8]
+ 8002156:	2202      	movs	r2, #2
+ 8002158:	4013      	ands	r3, r2
+ 800215a:	d029      	beq.n	80021b0 <HAL_DMA_IRQHandler+0xea>
+  {
+    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ 800215c:	687b      	ldr	r3, [r7, #4]
+ 800215e:	681b      	ldr	r3, [r3, #0]
+ 8002160:	681b      	ldr	r3, [r3, #0]
+ 8002162:	2220      	movs	r2, #32
+ 8002164:	4013      	ands	r3, r2
+ 8002166:	d10b      	bne.n	8002180 <HAL_DMA_IRQHandler+0xba>
+    {
+      /* Disable the transfer complete and error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+ 8002168:	687b      	ldr	r3, [r7, #4]
+ 800216a:	681b      	ldr	r3, [r3, #0]
+ 800216c:	681a      	ldr	r2, [r3, #0]
+ 800216e:	687b      	ldr	r3, [r7, #4]
+ 8002170:	681b      	ldr	r3, [r3, #0]
+ 8002172:	210a      	movs	r1, #10
+ 8002174:	438a      	bics	r2, r1
+ 8002176:	601a      	str	r2, [r3, #0]
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+ 8002178:	687b      	ldr	r3, [r7, #4]
+ 800217a:	2225      	movs	r2, #37	; 0x25
+ 800217c:	2101      	movs	r1, #1
+ 800217e:	5499      	strb	r1, [r3, r2]
+    }
+    /* Clear the transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
+ 8002180:	687b      	ldr	r3, [r7, #4]
+ 8002182:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8002184:	221c      	movs	r2, #28
+ 8002186:	401a      	ands	r2, r3
+ 8002188:	687b      	ldr	r3, [r7, #4]
+ 800218a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800218c:	2102      	movs	r1, #2
+ 800218e:	4091      	lsls	r1, r2
+ 8002190:	000a      	movs	r2, r1
+ 8002192:	605a      	str	r2, [r3, #4]
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 8002194:	687b      	ldr	r3, [r7, #4]
+ 8002196:	2224      	movs	r2, #36	; 0x24
+ 8002198:	2100      	movs	r1, #0
+ 800219a:	5499      	strb	r1, [r3, r2]
+
+    if(hdma->XferCpltCallback != NULL)
+ 800219c:	687b      	ldr	r3, [r7, #4]
+ 800219e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80021a0:	2b00      	cmp	r3, #0
+ 80021a2:	d039      	beq.n	8002218 <HAL_DMA_IRQHandler+0x152>
+    {
+      /* Transfer complete callback */
+      hdma->XferCpltCallback(hdma);
+ 80021a4:	687b      	ldr	r3, [r7, #4]
+ 80021a6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80021a8:	687a      	ldr	r2, [r7, #4]
+ 80021aa:	0010      	movs	r0, r2
+ 80021ac:	4798      	blx	r3
+    if(hdma->XferCpltCallback != NULL)
+ 80021ae:	e033      	b.n	8002218 <HAL_DMA_IRQHandler+0x152>
+    }
+  }
+
+  /* Transfer Error Interrupt management **************************************/
+  else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE)))
+ 80021b0:	687b      	ldr	r3, [r7, #4]
+ 80021b2:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 80021b4:	221c      	movs	r2, #28
+ 80021b6:	4013      	ands	r3, r2
+ 80021b8:	2208      	movs	r2, #8
+ 80021ba:	409a      	lsls	r2, r3
+ 80021bc:	0013      	movs	r3, r2
+ 80021be:	68fa      	ldr	r2, [r7, #12]
+ 80021c0:	4013      	ands	r3, r2
+ 80021c2:	d02a      	beq.n	800221a <HAL_DMA_IRQHandler+0x154>
+ 80021c4:	68bb      	ldr	r3, [r7, #8]
+ 80021c6:	2208      	movs	r2, #8
+ 80021c8:	4013      	ands	r3, r2
+ 80021ca:	d026      	beq.n	800221a <HAL_DMA_IRQHandler+0x154>
+  {
+    /* When a DMA transfer error occurs */
+    /* A hardware clear of its EN bits is performed */
+    /* Disable ALL DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 80021cc:	687b      	ldr	r3, [r7, #4]
+ 80021ce:	681b      	ldr	r3, [r3, #0]
+ 80021d0:	681a      	ldr	r2, [r3, #0]
+ 80021d2:	687b      	ldr	r3, [r7, #4]
+ 80021d4:	681b      	ldr	r3, [r3, #0]
+ 80021d6:	210e      	movs	r1, #14
+ 80021d8:	438a      	bics	r2, r1
+ 80021da:	601a      	str	r2, [r3, #0]
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
+ 80021dc:	687b      	ldr	r3, [r7, #4]
+ 80021de:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 80021e0:	221c      	movs	r2, #28
+ 80021e2:	401a      	ands	r2, r3
+ 80021e4:	687b      	ldr	r3, [r7, #4]
+ 80021e6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80021e8:	2101      	movs	r1, #1
+ 80021ea:	4091      	lsls	r1, r2
+ 80021ec:	000a      	movs	r2, r1
+ 80021ee:	605a      	str	r2, [r3, #4]
+
+    /* Update error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_TE;
+ 80021f0:	687b      	ldr	r3, [r7, #4]
+ 80021f2:	2201      	movs	r2, #1
+ 80021f4:	63da      	str	r2, [r3, #60]	; 0x3c
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+ 80021f6:	687b      	ldr	r3, [r7, #4]
+ 80021f8:	2225      	movs	r2, #37	; 0x25
+ 80021fa:	2101      	movs	r1, #1
+ 80021fc:	5499      	strb	r1, [r3, r2]
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 80021fe:	687b      	ldr	r3, [r7, #4]
+ 8002200:	2224      	movs	r2, #36	; 0x24
+ 8002202:	2100      	movs	r1, #0
+ 8002204:	5499      	strb	r1, [r3, r2]
+
+    if (hdma->XferErrorCallback != NULL)
+ 8002206:	687b      	ldr	r3, [r7, #4]
+ 8002208:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800220a:	2b00      	cmp	r3, #0
+ 800220c:	d005      	beq.n	800221a <HAL_DMA_IRQHandler+0x154>
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+ 800220e:	687b      	ldr	r3, [r7, #4]
+ 8002210:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8002212:	687a      	ldr	r2, [r7, #4]
+ 8002214:	0010      	movs	r0, r2
+ 8002216:	4798      	blx	r3
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+  return;
+ 8002218:	46c0      	nop			; (mov r8, r8)
+ 800221a:	46c0      	nop			; (mov r8, r8)
+}
+ 800221c:	46bd      	mov	sp, r7
+ 800221e:	b004      	add	sp, #16
+ 8002220:	bd80      	pop	{r7, pc}
+	...
+
+08002224 <HAL_GPIO_Init>:
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *                    the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 8002224:	b580      	push	{r7, lr}
+ 8002226:	b086      	sub	sp, #24
+ 8002228:	af00      	add	r7, sp, #0
+ 800222a:	6078      	str	r0, [r7, #4]
+ 800222c:	6039      	str	r1, [r7, #0]
+  uint32_t position = 0x00U;
+ 800222e:	2300      	movs	r3, #0
+ 8002230:	617b      	str	r3, [r7, #20]
+  uint32_t iocurrent = 0x00U;
+ 8002232:	2300      	movs	r3, #0
+ 8002234:	60fb      	str	r3, [r7, #12]
+  uint32_t temp = 0x00U;
+ 8002236:	2300      	movs	r3, #0
+ 8002238:	613b      	str	r3, [r7, #16]
+  /* Check the parameters */
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, (GPIO_Init->Pin)));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0)
+ 800223a:	e149      	b.n	80024d0 <HAL_GPIO_Init+0x2ac>
+  {
+    /* Get the IO position */
+    iocurrent = (GPIO_Init->Pin) & (1U << position);
+ 800223c:	683b      	ldr	r3, [r7, #0]
+ 800223e:	681b      	ldr	r3, [r3, #0]
+ 8002240:	2101      	movs	r1, #1
+ 8002242:	697a      	ldr	r2, [r7, #20]
+ 8002244:	4091      	lsls	r1, r2
+ 8002246:	000a      	movs	r2, r1
+ 8002248:	4013      	ands	r3, r2
+ 800224a:	60fb      	str	r3, [r7, #12]
+
+    if (iocurrent)
+ 800224c:	68fb      	ldr	r3, [r7, #12]
+ 800224e:	2b00      	cmp	r3, #0
+ 8002250:	d100      	bne.n	8002254 <HAL_GPIO_Init+0x30>
+ 8002252:	e13a      	b.n	80024ca <HAL_GPIO_Init+0x2a6>
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+ 8002254:	683b      	ldr	r3, [r7, #0]
+ 8002256:	685b      	ldr	r3, [r3, #4]
+ 8002258:	2203      	movs	r2, #3
+ 800225a:	4013      	ands	r3, r2
+ 800225c:	2b01      	cmp	r3, #1
+ 800225e:	d005      	beq.n	800226c <HAL_GPIO_Init+0x48>
+          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 8002260:	683b      	ldr	r3, [r7, #0]
+ 8002262:	685b      	ldr	r3, [r3, #4]
+ 8002264:	2203      	movs	r2, #3
+ 8002266:	4013      	ands	r3, r2
+      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+ 8002268:	2b02      	cmp	r3, #2
+ 800226a:	d130      	bne.n	80022ce <HAL_GPIO_Init+0xaa>
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+ 800226c:	687b      	ldr	r3, [r7, #4]
+ 800226e:	689b      	ldr	r3, [r3, #8]
+ 8002270:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
+ 8002272:	697b      	ldr	r3, [r7, #20]
+ 8002274:	005b      	lsls	r3, r3, #1
+ 8002276:	2203      	movs	r2, #3
+ 8002278:	409a      	lsls	r2, r3
+ 800227a:	0013      	movs	r3, r2
+ 800227c:	43da      	mvns	r2, r3
+ 800227e:	693b      	ldr	r3, [r7, #16]
+ 8002280:	4013      	ands	r3, r2
+ 8002282:	613b      	str	r3, [r7, #16]
+        temp |= (GPIO_Init->Speed << (position * 2U));
+ 8002284:	683b      	ldr	r3, [r7, #0]
+ 8002286:	68da      	ldr	r2, [r3, #12]
+ 8002288:	697b      	ldr	r3, [r7, #20]
+ 800228a:	005b      	lsls	r3, r3, #1
+ 800228c:	409a      	lsls	r2, r3
+ 800228e:	0013      	movs	r3, r2
+ 8002290:	693a      	ldr	r2, [r7, #16]
+ 8002292:	4313      	orrs	r3, r2
+ 8002294:	613b      	str	r3, [r7, #16]
+        GPIOx->OSPEEDR = temp;
+ 8002296:	687b      	ldr	r3, [r7, #4]
+ 8002298:	693a      	ldr	r2, [r7, #16]
+ 800229a:	609a      	str	r2, [r3, #8]
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+ 800229c:	687b      	ldr	r3, [r7, #4]
+ 800229e:	685b      	ldr	r3, [r3, #4]
+ 80022a0:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 80022a2:	2201      	movs	r2, #1
+ 80022a4:	697b      	ldr	r3, [r7, #20]
+ 80022a6:	409a      	lsls	r2, r3
+ 80022a8:	0013      	movs	r3, r2
+ 80022aa:	43da      	mvns	r2, r3
+ 80022ac:	693b      	ldr	r3, [r7, #16]
+ 80022ae:	4013      	ands	r3, r2
+ 80022b0:	613b      	str	r3, [r7, #16]
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+ 80022b2:	683b      	ldr	r3, [r7, #0]
+ 80022b4:	685b      	ldr	r3, [r3, #4]
+ 80022b6:	091b      	lsrs	r3, r3, #4
+ 80022b8:	2201      	movs	r2, #1
+ 80022ba:	401a      	ands	r2, r3
+ 80022bc:	697b      	ldr	r3, [r7, #20]
+ 80022be:	409a      	lsls	r2, r3
+ 80022c0:	0013      	movs	r3, r2
+ 80022c2:	693a      	ldr	r2, [r7, #16]
+ 80022c4:	4313      	orrs	r3, r2
+ 80022c6:	613b      	str	r3, [r7, #16]
+        GPIOx->OTYPER = temp;
+ 80022c8:	687b      	ldr	r3, [r7, #4]
+ 80022ca:	693a      	ldr	r2, [r7, #16]
+ 80022cc:	605a      	str	r2, [r3, #4]
+      }
+
+      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ 80022ce:	683b      	ldr	r3, [r7, #0]
+ 80022d0:	685b      	ldr	r3, [r3, #4]
+ 80022d2:	2203      	movs	r2, #3
+ 80022d4:	4013      	ands	r3, r2
+ 80022d6:	2b03      	cmp	r3, #3
+ 80022d8:	d017      	beq.n	800230a <HAL_GPIO_Init+0xe6>
+      {
+        /* Check the Pull parameter */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+        /* Activate the Pull-up or Pull down resistor for the current IO */
+        temp = GPIOx->PUPDR;
+ 80022da:	687b      	ldr	r3, [r7, #4]
+ 80022dc:	68db      	ldr	r3, [r3, #12]
+ 80022de:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ 80022e0:	697b      	ldr	r3, [r7, #20]
+ 80022e2:	005b      	lsls	r3, r3, #1
+ 80022e4:	2203      	movs	r2, #3
+ 80022e6:	409a      	lsls	r2, r3
+ 80022e8:	0013      	movs	r3, r2
+ 80022ea:	43da      	mvns	r2, r3
+ 80022ec:	693b      	ldr	r3, [r7, #16]
+ 80022ee:	4013      	ands	r3, r2
+ 80022f0:	613b      	str	r3, [r7, #16]
+        temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 80022f2:	683b      	ldr	r3, [r7, #0]
+ 80022f4:	689a      	ldr	r2, [r3, #8]
+ 80022f6:	697b      	ldr	r3, [r7, #20]
+ 80022f8:	005b      	lsls	r3, r3, #1
+ 80022fa:	409a      	lsls	r2, r3
+ 80022fc:	0013      	movs	r3, r2
+ 80022fe:	693a      	ldr	r2, [r7, #16]
+ 8002300:	4313      	orrs	r3, r2
+ 8002302:	613b      	str	r3, [r7, #16]
+        GPIOx->PUPDR = temp;
+ 8002304:	687b      	ldr	r3, [r7, #4]
+ 8002306:	693a      	ldr	r2, [r7, #16]
+ 8002308:	60da      	str	r2, [r3, #12]
+      }
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 800230a:	683b      	ldr	r3, [r7, #0]
+ 800230c:	685b      	ldr	r3, [r3, #4]
+ 800230e:	2203      	movs	r2, #3
+ 8002310:	4013      	ands	r3, r2
+ 8002312:	2b02      	cmp	r3, #2
+ 8002314:	d123      	bne.n	800235e <HAL_GPIO_Init+0x13a>
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+ 8002316:	697b      	ldr	r3, [r7, #20]
+ 8002318:	08da      	lsrs	r2, r3, #3
+ 800231a:	687b      	ldr	r3, [r7, #4]
+ 800231c:	3208      	adds	r2, #8
+ 800231e:	0092      	lsls	r2, r2, #2
+ 8002320:	58d3      	ldr	r3, [r2, r3]
+ 8002322:	613b      	str	r3, [r7, #16]
+        temp &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
+ 8002324:	697b      	ldr	r3, [r7, #20]
+ 8002326:	2207      	movs	r2, #7
+ 8002328:	4013      	ands	r3, r2
+ 800232a:	009b      	lsls	r3, r3, #2
+ 800232c:	220f      	movs	r2, #15
+ 800232e:	409a      	lsls	r2, r3
+ 8002330:	0013      	movs	r3, r2
+ 8002332:	43da      	mvns	r2, r3
+ 8002334:	693b      	ldr	r3, [r7, #16]
+ 8002336:	4013      	ands	r3, r2
+ 8002338:	613b      	str	r3, [r7, #16]
+        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
+ 800233a:	683b      	ldr	r3, [r7, #0]
+ 800233c:	691a      	ldr	r2, [r3, #16]
+ 800233e:	697b      	ldr	r3, [r7, #20]
+ 8002340:	2107      	movs	r1, #7
+ 8002342:	400b      	ands	r3, r1
+ 8002344:	009b      	lsls	r3, r3, #2
+ 8002346:	409a      	lsls	r2, r3
+ 8002348:	0013      	movs	r3, r2
+ 800234a:	693a      	ldr	r2, [r7, #16]
+ 800234c:	4313      	orrs	r3, r2
+ 800234e:	613b      	str	r3, [r7, #16]
+        GPIOx->AFR[position >> 3U] = temp;
+ 8002350:	697b      	ldr	r3, [r7, #20]
+ 8002352:	08da      	lsrs	r2, r3, #3
+ 8002354:	687b      	ldr	r3, [r7, #4]
+ 8002356:	3208      	adds	r2, #8
+ 8002358:	0092      	lsls	r2, r2, #2
+ 800235a:	6939      	ldr	r1, [r7, #16]
+ 800235c:	50d1      	str	r1, [r2, r3]
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+ 800235e:	687b      	ldr	r3, [r7, #4]
+ 8002360:	681b      	ldr	r3, [r3, #0]
+ 8002362:	613b      	str	r3, [r7, #16]
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ 8002364:	697b      	ldr	r3, [r7, #20]
+ 8002366:	005b      	lsls	r3, r3, #1
+ 8002368:	2203      	movs	r2, #3
+ 800236a:	409a      	lsls	r2, r3
+ 800236c:	0013      	movs	r3, r2
+ 800236e:	43da      	mvns	r2, r3
+ 8002370:	693b      	ldr	r3, [r7, #16]
+ 8002372:	4013      	ands	r3, r2
+ 8002374:	613b      	str	r3, [r7, #16]
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 8002376:	683b      	ldr	r3, [r7, #0]
+ 8002378:	685b      	ldr	r3, [r3, #4]
+ 800237a:	2203      	movs	r2, #3
+ 800237c:	401a      	ands	r2, r3
+ 800237e:	697b      	ldr	r3, [r7, #20]
+ 8002380:	005b      	lsls	r3, r3, #1
+ 8002382:	409a      	lsls	r2, r3
+ 8002384:	0013      	movs	r3, r2
+ 8002386:	693a      	ldr	r2, [r7, #16]
+ 8002388:	4313      	orrs	r3, r2
+ 800238a:	613b      	str	r3, [r7, #16]
+      GPIOx->MODER = temp;
+ 800238c:	687b      	ldr	r3, [r7, #4]
+ 800238e:	693a      	ldr	r2, [r7, #16]
+ 8002390:	601a      	str	r2, [r3, #0]
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
+ 8002392:	683b      	ldr	r3, [r7, #0]
+ 8002394:	685a      	ldr	r2, [r3, #4]
+ 8002396:	23c0      	movs	r3, #192	; 0xc0
+ 8002398:	029b      	lsls	r3, r3, #10
+ 800239a:	4013      	ands	r3, r2
+ 800239c:	d100      	bne.n	80023a0 <HAL_GPIO_Init+0x17c>
+ 800239e:	e094      	b.n	80024ca <HAL_GPIO_Init+0x2a6>
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 80023a0:	4b51      	ldr	r3, [pc, #324]	; (80024e8 <HAL_GPIO_Init+0x2c4>)
+ 80023a2:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 80023a4:	4b50      	ldr	r3, [pc, #320]	; (80024e8 <HAL_GPIO_Init+0x2c4>)
+ 80023a6:	2101      	movs	r1, #1
+ 80023a8:	430a      	orrs	r2, r1
+ 80023aa:	635a      	str	r2, [r3, #52]	; 0x34
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+ 80023ac:	4a4f      	ldr	r2, [pc, #316]	; (80024ec <HAL_GPIO_Init+0x2c8>)
+ 80023ae:	697b      	ldr	r3, [r7, #20]
+ 80023b0:	089b      	lsrs	r3, r3, #2
+ 80023b2:	3302      	adds	r3, #2
+ 80023b4:	009b      	lsls	r3, r3, #2
+ 80023b6:	589b      	ldr	r3, [r3, r2]
+ 80023b8:	613b      	str	r3, [r7, #16]
+        CLEAR_BIT(temp, (0x0FUL) << (4U * (position & 0x03U)));
+ 80023ba:	697b      	ldr	r3, [r7, #20]
+ 80023bc:	2203      	movs	r2, #3
+ 80023be:	4013      	ands	r3, r2
+ 80023c0:	009b      	lsls	r3, r3, #2
+ 80023c2:	220f      	movs	r2, #15
+ 80023c4:	409a      	lsls	r2, r3
+ 80023c6:	0013      	movs	r3, r2
+ 80023c8:	43da      	mvns	r2, r3
+ 80023ca:	693b      	ldr	r3, [r7, #16]
+ 80023cc:	4013      	ands	r3, r2
+ 80023ce:	613b      	str	r3, [r7, #16]
+        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U)));
+ 80023d0:	687a      	ldr	r2, [r7, #4]
+ 80023d2:	23a0      	movs	r3, #160	; 0xa0
+ 80023d4:	05db      	lsls	r3, r3, #23
+ 80023d6:	429a      	cmp	r2, r3
+ 80023d8:	d013      	beq.n	8002402 <HAL_GPIO_Init+0x1de>
+ 80023da:	687b      	ldr	r3, [r7, #4]
+ 80023dc:	4a44      	ldr	r2, [pc, #272]	; (80024f0 <HAL_GPIO_Init+0x2cc>)
+ 80023de:	4293      	cmp	r3, r2
+ 80023e0:	d00d      	beq.n	80023fe <HAL_GPIO_Init+0x1da>
+ 80023e2:	687b      	ldr	r3, [r7, #4]
+ 80023e4:	4a43      	ldr	r2, [pc, #268]	; (80024f4 <HAL_GPIO_Init+0x2d0>)
+ 80023e6:	4293      	cmp	r3, r2
+ 80023e8:	d007      	beq.n	80023fa <HAL_GPIO_Init+0x1d6>
+ 80023ea:	687b      	ldr	r3, [r7, #4]
+ 80023ec:	4a42      	ldr	r2, [pc, #264]	; (80024f8 <HAL_GPIO_Init+0x2d4>)
+ 80023ee:	4293      	cmp	r3, r2
+ 80023f0:	d101      	bne.n	80023f6 <HAL_GPIO_Init+0x1d2>
+ 80023f2:	2305      	movs	r3, #5
+ 80023f4:	e006      	b.n	8002404 <HAL_GPIO_Init+0x1e0>
+ 80023f6:	2306      	movs	r3, #6
+ 80023f8:	e004      	b.n	8002404 <HAL_GPIO_Init+0x1e0>
+ 80023fa:	2302      	movs	r3, #2
+ 80023fc:	e002      	b.n	8002404 <HAL_GPIO_Init+0x1e0>
+ 80023fe:	2301      	movs	r3, #1
+ 8002400:	e000      	b.n	8002404 <HAL_GPIO_Init+0x1e0>
+ 8002402:	2300      	movs	r3, #0
+ 8002404:	697a      	ldr	r2, [r7, #20]
+ 8002406:	2103      	movs	r1, #3
+ 8002408:	400a      	ands	r2, r1
+ 800240a:	0092      	lsls	r2, r2, #2
+ 800240c:	4093      	lsls	r3, r2
+ 800240e:	693a      	ldr	r2, [r7, #16]
+ 8002410:	4313      	orrs	r3, r2
+ 8002412:	613b      	str	r3, [r7, #16]
+        SYSCFG->EXTICR[position >> 2U] = temp;
+ 8002414:	4935      	ldr	r1, [pc, #212]	; (80024ec <HAL_GPIO_Init+0x2c8>)
+ 8002416:	697b      	ldr	r3, [r7, #20]
+ 8002418:	089b      	lsrs	r3, r3, #2
+ 800241a:	3302      	adds	r3, #2
+ 800241c:	009b      	lsls	r3, r3, #2
+ 800241e:	693a      	ldr	r2, [r7, #16]
+ 8002420:	505a      	str	r2, [r3, r1]
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR;
+ 8002422:	4b36      	ldr	r3, [pc, #216]	; (80024fc <HAL_GPIO_Init+0x2d8>)
+ 8002424:	681b      	ldr	r3, [r3, #0]
+ 8002426:	613b      	str	r3, [r7, #16]
+        temp &= ~((uint32_t)iocurrent);
+ 8002428:	68fb      	ldr	r3, [r7, #12]
+ 800242a:	43da      	mvns	r2, r3
+ 800242c:	693b      	ldr	r3, [r7, #16]
+ 800242e:	4013      	ands	r3, r2
+ 8002430:	613b      	str	r3, [r7, #16]
+        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+ 8002432:	683b      	ldr	r3, [r7, #0]
+ 8002434:	685a      	ldr	r2, [r3, #4]
+ 8002436:	2380      	movs	r3, #128	; 0x80
+ 8002438:	025b      	lsls	r3, r3, #9
+ 800243a:	4013      	ands	r3, r2
+ 800243c:	d003      	beq.n	8002446 <HAL_GPIO_Init+0x222>
+        {
+          temp |= iocurrent;
+ 800243e:	693a      	ldr	r2, [r7, #16]
+ 8002440:	68fb      	ldr	r3, [r7, #12]
+ 8002442:	4313      	orrs	r3, r2
+ 8002444:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->IMR = temp;
+ 8002446:	4b2d      	ldr	r3, [pc, #180]	; (80024fc <HAL_GPIO_Init+0x2d8>)
+ 8002448:	693a      	ldr	r2, [r7, #16]
+ 800244a:	601a      	str	r2, [r3, #0]
+
+        temp = EXTI->EMR;
+ 800244c:	4b2b      	ldr	r3, [pc, #172]	; (80024fc <HAL_GPIO_Init+0x2d8>)
+ 800244e:	685b      	ldr	r3, [r3, #4]
+ 8002450:	613b      	str	r3, [r7, #16]
+        temp &= ~((uint32_t)iocurrent);
+ 8002452:	68fb      	ldr	r3, [r7, #12]
+ 8002454:	43da      	mvns	r2, r3
+ 8002456:	693b      	ldr	r3, [r7, #16]
+ 8002458:	4013      	ands	r3, r2
+ 800245a:	613b      	str	r3, [r7, #16]
+        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+ 800245c:	683b      	ldr	r3, [r7, #0]
+ 800245e:	685a      	ldr	r2, [r3, #4]
+ 8002460:	2380      	movs	r3, #128	; 0x80
+ 8002462:	029b      	lsls	r3, r3, #10
+ 8002464:	4013      	ands	r3, r2
+ 8002466:	d003      	beq.n	8002470 <HAL_GPIO_Init+0x24c>
+        {
+          temp |= iocurrent;
+ 8002468:	693a      	ldr	r2, [r7, #16]
+ 800246a:	68fb      	ldr	r3, [r7, #12]
+ 800246c:	4313      	orrs	r3, r2
+ 800246e:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->EMR = temp;
+ 8002470:	4b22      	ldr	r3, [pc, #136]	; (80024fc <HAL_GPIO_Init+0x2d8>)
+ 8002472:	693a      	ldr	r2, [r7, #16]
+ 8002474:	605a      	str	r2, [r3, #4]
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR;
+ 8002476:	4b21      	ldr	r3, [pc, #132]	; (80024fc <HAL_GPIO_Init+0x2d8>)
+ 8002478:	689b      	ldr	r3, [r3, #8]
+ 800247a:	613b      	str	r3, [r7, #16]
+        temp &= ~((uint32_t)iocurrent);
+ 800247c:	68fb      	ldr	r3, [r7, #12]
+ 800247e:	43da      	mvns	r2, r3
+ 8002480:	693b      	ldr	r3, [r7, #16]
+ 8002482:	4013      	ands	r3, r2
+ 8002484:	613b      	str	r3, [r7, #16]
+        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
+ 8002486:	683b      	ldr	r3, [r7, #0]
+ 8002488:	685a      	ldr	r2, [r3, #4]
+ 800248a:	2380      	movs	r3, #128	; 0x80
+ 800248c:	035b      	lsls	r3, r3, #13
+ 800248e:	4013      	ands	r3, r2
+ 8002490:	d003      	beq.n	800249a <HAL_GPIO_Init+0x276>
+        {
+          temp |= iocurrent;
+ 8002492:	693a      	ldr	r2, [r7, #16]
+ 8002494:	68fb      	ldr	r3, [r7, #12]
+ 8002496:	4313      	orrs	r3, r2
+ 8002498:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->RTSR = temp;
+ 800249a:	4b18      	ldr	r3, [pc, #96]	; (80024fc <HAL_GPIO_Init+0x2d8>)
+ 800249c:	693a      	ldr	r2, [r7, #16]
+ 800249e:	609a      	str	r2, [r3, #8]
+
+        temp = EXTI->FTSR;
+ 80024a0:	4b16      	ldr	r3, [pc, #88]	; (80024fc <HAL_GPIO_Init+0x2d8>)
+ 80024a2:	68db      	ldr	r3, [r3, #12]
+ 80024a4:	613b      	str	r3, [r7, #16]
+        temp &= ~((uint32_t)iocurrent);
+ 80024a6:	68fb      	ldr	r3, [r7, #12]
+ 80024a8:	43da      	mvns	r2, r3
+ 80024aa:	693b      	ldr	r3, [r7, #16]
+ 80024ac:	4013      	ands	r3, r2
+ 80024ae:	613b      	str	r3, [r7, #16]
+        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
+ 80024b0:	683b      	ldr	r3, [r7, #0]
+ 80024b2:	685a      	ldr	r2, [r3, #4]
+ 80024b4:	2380      	movs	r3, #128	; 0x80
+ 80024b6:	039b      	lsls	r3, r3, #14
+ 80024b8:	4013      	ands	r3, r2
+ 80024ba:	d003      	beq.n	80024c4 <HAL_GPIO_Init+0x2a0>
+        {
+          temp |= iocurrent;
+ 80024bc:	693a      	ldr	r2, [r7, #16]
+ 80024be:	68fb      	ldr	r3, [r7, #12]
+ 80024c0:	4313      	orrs	r3, r2
+ 80024c2:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->FTSR = temp;
+ 80024c4:	4b0d      	ldr	r3, [pc, #52]	; (80024fc <HAL_GPIO_Init+0x2d8>)
+ 80024c6:	693a      	ldr	r2, [r7, #16]
+ 80024c8:	60da      	str	r2, [r3, #12]
+      }
+    }
+    position++;
+ 80024ca:	697b      	ldr	r3, [r7, #20]
+ 80024cc:	3301      	adds	r3, #1
+ 80024ce:	617b      	str	r3, [r7, #20]
+  while (((GPIO_Init->Pin) >> position) != 0)
+ 80024d0:	683b      	ldr	r3, [r7, #0]
+ 80024d2:	681a      	ldr	r2, [r3, #0]
+ 80024d4:	697b      	ldr	r3, [r7, #20]
+ 80024d6:	40da      	lsrs	r2, r3
+ 80024d8:	1e13      	subs	r3, r2, #0
+ 80024da:	d000      	beq.n	80024de <HAL_GPIO_Init+0x2ba>
+ 80024dc:	e6ae      	b.n	800223c <HAL_GPIO_Init+0x18>
+  }
+}
+ 80024de:	46c0      	nop			; (mov r8, r8)
+ 80024e0:	46c0      	nop			; (mov r8, r8)
+ 80024e2:	46bd      	mov	sp, r7
+ 80024e4:	b006      	add	sp, #24
+ 80024e6:	bd80      	pop	{r7, pc}
+ 80024e8:	40021000 	.word	0x40021000
+ 80024ec:	40010000 	.word	0x40010000
+ 80024f0:	50000400 	.word	0x50000400
+ 80024f4:	50000800 	.word	0x50000800
+ 80024f8:	50001c00 	.word	0x50001c00
+ 80024fc:	40010400 	.word	0x40010400
+
+08002500 <HAL_GPIO_WritePin>:
+  *                        GPIO_PIN_RESET: to clear the port pin
+  *                        GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 8002500:	b580      	push	{r7, lr}
+ 8002502:	b082      	sub	sp, #8
+ 8002504:	af00      	add	r7, sp, #0
+ 8002506:	6078      	str	r0, [r7, #4]
+ 8002508:	0008      	movs	r0, r1
+ 800250a:	0011      	movs	r1, r2
+ 800250c:	1cbb      	adds	r3, r7, #2
+ 800250e:	1c02      	adds	r2, r0, #0
+ 8002510:	801a      	strh	r2, [r3, #0]
+ 8002512:	1c7b      	adds	r3, r7, #1
+ 8002514:	1c0a      	adds	r2, r1, #0
+ 8002516:	701a      	strb	r2, [r3, #0]
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+ 8002518:	1c7b      	adds	r3, r7, #1
+ 800251a:	781b      	ldrb	r3, [r3, #0]
+ 800251c:	2b00      	cmp	r3, #0
+ 800251e:	d004      	beq.n	800252a <HAL_GPIO_WritePin+0x2a>
+  {
+    GPIOx->BSRR = GPIO_Pin;
+ 8002520:	1cbb      	adds	r3, r7, #2
+ 8002522:	881a      	ldrh	r2, [r3, #0]
+ 8002524:	687b      	ldr	r3, [r7, #4]
+ 8002526:	619a      	str	r2, [r3, #24]
+  }
+  else
+  {
+    GPIOx->BRR = GPIO_Pin ;
+  }
+}
+ 8002528:	e003      	b.n	8002532 <HAL_GPIO_WritePin+0x32>
+    GPIOx->BRR = GPIO_Pin ;
+ 800252a:	1cbb      	adds	r3, r7, #2
+ 800252c:	881a      	ldrh	r2, [r3, #0]
+ 800252e:	687b      	ldr	r3, [r7, #4]
+ 8002530:	629a      	str	r2, [r3, #40]	; 0x28
+}
+ 8002532:	46c0      	nop			; (mov r8, r8)
+ 8002534:	46bd      	mov	sp, r7
+ 8002536:	b002      	add	sp, #8
+ 8002538:	bd80      	pop	{r7, pc}
+	...
+
+0800253c <HAL_GPIO_EXTI_IRQHandler>:
+  * @brief  This function handles EXTI interrupt request.
+  * @param  GPIO_Pin Specifies the pins connected to the EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ 800253c:	b580      	push	{r7, lr}
+ 800253e:	b082      	sub	sp, #8
+ 8002540:	af00      	add	r7, sp, #0
+ 8002542:	0002      	movs	r2, r0
+ 8002544:	1dbb      	adds	r3, r7, #6
+ 8002546:	801a      	strh	r2, [r3, #0]
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ 8002548:	4b09      	ldr	r3, [pc, #36]	; (8002570 <HAL_GPIO_EXTI_IRQHandler+0x34>)
+ 800254a:	695b      	ldr	r3, [r3, #20]
+ 800254c:	1dba      	adds	r2, r7, #6
+ 800254e:	8812      	ldrh	r2, [r2, #0]
+ 8002550:	4013      	ands	r3, r2
+ 8002552:	d008      	beq.n	8002566 <HAL_GPIO_EXTI_IRQHandler+0x2a>
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ 8002554:	4b06      	ldr	r3, [pc, #24]	; (8002570 <HAL_GPIO_EXTI_IRQHandler+0x34>)
+ 8002556:	1dba      	adds	r2, r7, #6
+ 8002558:	8812      	ldrh	r2, [r2, #0]
+ 800255a:	615a      	str	r2, [r3, #20]
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ 800255c:	1dbb      	adds	r3, r7, #6
+ 800255e:	881b      	ldrh	r3, [r3, #0]
+ 8002560:	0018      	movs	r0, r3
+ 8002562:	f000 f807 	bl	8002574 <HAL_GPIO_EXTI_Callback>
+  }
+}
+ 8002566:	46c0      	nop			; (mov r8, r8)
+ 8002568:	46bd      	mov	sp, r7
+ 800256a:	b002      	add	sp, #8
+ 800256c:	bd80      	pop	{r7, pc}
+ 800256e:	46c0      	nop			; (mov r8, r8)
+ 8002570:	40010400 	.word	0x40010400
+
+08002574 <HAL_GPIO_EXTI_Callback>:
+  * @brief  EXTI line detection callbacks.
+  * @param  GPIO_Pin Specifies the pins connected to the EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ 8002574:	b580      	push	{r7, lr}
+ 8002576:	b082      	sub	sp, #8
+ 8002578:	af00      	add	r7, sp, #0
+ 800257a:	0002      	movs	r2, r0
+ 800257c:	1dbb      	adds	r3, r7, #6
+ 800257e:	801a      	strh	r2, [r3, #0]
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+ 8002580:	46c0      	nop			; (mov r8, r8)
+ 8002582:	46bd      	mov	sp, r7
+ 8002584:	b002      	add	sp, #8
+ 8002586:	bd80      	pop	{r7, pc}
+
+08002588 <HAL_LPTIM_Init>:
+  *         LPTIM_InitTypeDef and initialize the associated handle.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
+{
+ 8002588:	b580      	push	{r7, lr}
+ 800258a:	b084      	sub	sp, #16
+ 800258c:	af00      	add	r7, sp, #0
+ 800258e:	6078      	str	r0, [r7, #4]
+  uint32_t tmpcfgr;
+
+  /* Check the LPTIM handle allocation */
+  if (hlptim == NULL)
+ 8002590:	687b      	ldr	r3, [r7, #4]
+ 8002592:	2b00      	cmp	r3, #0
+ 8002594:	d101      	bne.n	800259a <HAL_LPTIM_Init+0x12>
+  {
+    return HAL_ERROR;
+ 8002596:	2301      	movs	r3, #1
+ 8002598:	e078      	b.n	800268c <HAL_LPTIM_Init+0x104>
+  }
+  assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
+  assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
+  assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
+
+  if (hlptim->State == HAL_LPTIM_STATE_RESET)
+ 800259a:	687b      	ldr	r3, [r7, #4]
+ 800259c:	222e      	movs	r2, #46	; 0x2e
+ 800259e:	5c9b      	ldrb	r3, [r3, r2]
+ 80025a0:	b2db      	uxtb	r3, r3
+ 80025a2:	2b00      	cmp	r3, #0
+ 80025a4:	d107      	bne.n	80025b6 <HAL_LPTIM_Init+0x2e>
+  {
+    /* Allocate lock resource and initialize it */
+    hlptim->Lock = HAL_UNLOCKED;
+ 80025a6:	687b      	ldr	r3, [r7, #4]
+ 80025a8:	222d      	movs	r2, #45	; 0x2d
+ 80025aa:	2100      	movs	r1, #0
+ 80025ac:	5499      	strb	r1, [r3, r2]
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    hlptim->MspInitCallback(hlptim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_LPTIM_MspInit(hlptim);
+ 80025ae:	687b      	ldr	r3, [r7, #4]
+ 80025b0:	0018      	movs	r0, r3
+ 80025b2:	f7fe fe1f 	bl	80011f4 <HAL_LPTIM_MspInit>
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+  }
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+ 80025b6:	687b      	ldr	r3, [r7, #4]
+ 80025b8:	222e      	movs	r2, #46	; 0x2e
+ 80025ba:	2102      	movs	r1, #2
+ 80025bc:	5499      	strb	r1, [r3, r2]
+
+  /* Get the LPTIMx CFGR value */
+  tmpcfgr = hlptim->Instance->CFGR;
+ 80025be:	687b      	ldr	r3, [r7, #4]
+ 80025c0:	681b      	ldr	r3, [r3, #0]
+ 80025c2:	68db      	ldr	r3, [r3, #12]
+ 80025c4:	60fb      	str	r3, [r7, #12]
+
+  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ 80025c6:	687b      	ldr	r3, [r7, #4]
+ 80025c8:	685b      	ldr	r3, [r3, #4]
+ 80025ca:	2b01      	cmp	r3, #1
+ 80025cc:	d005      	beq.n	80025da <HAL_LPTIM_Init+0x52>
+      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ 80025ce:	687b      	ldr	r3, [r7, #4]
+ 80025d0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 80025d2:	2380      	movs	r3, #128	; 0x80
+ 80025d4:	041b      	lsls	r3, r3, #16
+ 80025d6:	429a      	cmp	r2, r3
+ 80025d8:	d103      	bne.n	80025e2 <HAL_LPTIM_Init+0x5a>
+  {
+    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ 80025da:	68fb      	ldr	r3, [r7, #12]
+ 80025dc:	221e      	movs	r2, #30
+ 80025de:	4393      	bics	r3, r2
+ 80025e0:	60fb      	str	r3, [r7, #12]
+  }
+  if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ 80025e2:	687b      	ldr	r3, [r7, #4]
+ 80025e4:	695b      	ldr	r3, [r3, #20]
+ 80025e6:	4a2b      	ldr	r2, [pc, #172]	; (8002694 <HAL_LPTIM_Init+0x10c>)
+ 80025e8:	4293      	cmp	r3, r2
+ 80025ea:	d003      	beq.n	80025f4 <HAL_LPTIM_Init+0x6c>
+  {
+    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ 80025ec:	68fb      	ldr	r3, [r7, #12]
+ 80025ee:	4a2a      	ldr	r2, [pc, #168]	; (8002698 <HAL_LPTIM_Init+0x110>)
+ 80025f0:	4013      	ands	r3, r2
+ 80025f2:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+  tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ 80025f4:	68fb      	ldr	r3, [r7, #12]
+ 80025f6:	4a29      	ldr	r2, [pc, #164]	; (800269c <HAL_LPTIM_Init+0x114>)
+ 80025f8:	4013      	ands	r3, r2
+ 80025fa:	60fb      	str	r3, [r7, #12]
+                          LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
+
+  /* Set initialization parameters */
+  tmpcfgr |= (hlptim->Init.Clock.Source    |
+ 80025fc:	687b      	ldr	r3, [r7, #4]
+ 80025fe:	685a      	ldr	r2, [r3, #4]
+              hlptim->Init.Clock.Prescaler |
+ 8002600:	687b      	ldr	r3, [r7, #4]
+ 8002602:	689b      	ldr	r3, [r3, #8]
+  tmpcfgr |= (hlptim->Init.Clock.Source    |
+ 8002604:	431a      	orrs	r2, r3
+              hlptim->Init.OutputPolarity  |
+ 8002606:	687b      	ldr	r3, [r7, #4]
+ 8002608:	6a1b      	ldr	r3, [r3, #32]
+              hlptim->Init.Clock.Prescaler |
+ 800260a:	431a      	orrs	r2, r3
+              hlptim->Init.UpdateMode      |
+ 800260c:	687b      	ldr	r3, [r7, #4]
+ 800260e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+              hlptim->Init.OutputPolarity  |
+ 8002610:	431a      	orrs	r2, r3
+              hlptim->Init.CounterSource);
+ 8002612:	687b      	ldr	r3, [r7, #4]
+ 8002614:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+              hlptim->Init.UpdateMode      |
+ 8002616:	4313      	orrs	r3, r2
+  tmpcfgr |= (hlptim->Init.Clock.Source    |
+ 8002618:	68fa      	ldr	r2, [r7, #12]
+ 800261a:	4313      	orrs	r3, r2
+ 800261c:	60fb      	str	r3, [r7, #12]
+
+  /* Glitch filters for internal triggers and  external inputs are configured
+   * only if an internal clock source is provided to the LPTIM
+   */
+  if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
+ 800261e:	687b      	ldr	r3, [r7, #4]
+ 8002620:	685b      	ldr	r3, [r3, #4]
+ 8002622:	2b00      	cmp	r3, #0
+ 8002624:	d107      	bne.n	8002636 <HAL_LPTIM_Init+0xae>
+  {
+    tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
+ 8002626:	687b      	ldr	r3, [r7, #4]
+ 8002628:	69da      	ldr	r2, [r3, #28]
+                hlptim->Init.UltraLowPowerClock.SampleTime);
+ 800262a:	687b      	ldr	r3, [r7, #4]
+ 800262c:	691b      	ldr	r3, [r3, #16]
+    tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
+ 800262e:	4313      	orrs	r3, r2
+ 8002630:	68fa      	ldr	r2, [r7, #12]
+ 8002632:	4313      	orrs	r3, r2
+ 8002634:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Configure LPTIM external clock polarity and digital filter */
+  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ 8002636:	687b      	ldr	r3, [r7, #4]
+ 8002638:	685b      	ldr	r3, [r3, #4]
+ 800263a:	2b01      	cmp	r3, #1
+ 800263c:	d005      	beq.n	800264a <HAL_LPTIM_Init+0xc2>
+      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ 800263e:	687b      	ldr	r3, [r7, #4]
+ 8002640:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8002642:	2380      	movs	r3, #128	; 0x80
+ 8002644:	041b      	lsls	r3, r3, #16
+ 8002646:	429a      	cmp	r2, r3
+ 8002648:	d107      	bne.n	800265a <HAL_LPTIM_Init+0xd2>
+  {
+    tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ 800264a:	687b      	ldr	r3, [r7, #4]
+ 800264c:	68da      	ldr	r2, [r3, #12]
+                hlptim->Init.UltraLowPowerClock.SampleTime);
+ 800264e:	687b      	ldr	r3, [r7, #4]
+ 8002650:	691b      	ldr	r3, [r3, #16]
+    tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ 8002652:	4313      	orrs	r3, r2
+ 8002654:	68fa      	ldr	r2, [r7, #12]
+ 8002656:	4313      	orrs	r3, r2
+ 8002658:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Configure LPTIM external trigger */
+  if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ 800265a:	687b      	ldr	r3, [r7, #4]
+ 800265c:	695b      	ldr	r3, [r3, #20]
+ 800265e:	4a0d      	ldr	r2, [pc, #52]	; (8002694 <HAL_LPTIM_Init+0x10c>)
+ 8002660:	4293      	cmp	r3, r2
+ 8002662:	d00a      	beq.n	800267a <HAL_LPTIM_Init+0xf2>
+  {
+    /* Enable External trigger and set the trigger source */
+    tmpcfgr |= (hlptim->Init.Trigger.Source     |
+ 8002664:	687b      	ldr	r3, [r7, #4]
+ 8002666:	695a      	ldr	r2, [r3, #20]
+                hlptim->Init.Trigger.ActiveEdge |
+ 8002668:	687b      	ldr	r3, [r7, #4]
+ 800266a:	699b      	ldr	r3, [r3, #24]
+    tmpcfgr |= (hlptim->Init.Trigger.Source     |
+ 800266c:	431a      	orrs	r2, r3
+                hlptim->Init.Trigger.SampleTime);
+ 800266e:	687b      	ldr	r3, [r7, #4]
+ 8002670:	69db      	ldr	r3, [r3, #28]
+                hlptim->Init.Trigger.ActiveEdge |
+ 8002672:	4313      	orrs	r3, r2
+    tmpcfgr |= (hlptim->Init.Trigger.Source     |
+ 8002674:	68fa      	ldr	r2, [r7, #12]
+ 8002676:	4313      	orrs	r3, r2
+ 8002678:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Write to LPTIMx CFGR */
+  hlptim->Instance->CFGR = tmpcfgr;
+ 800267a:	687b      	ldr	r3, [r7, #4]
+ 800267c:	681b      	ldr	r3, [r3, #0]
+ 800267e:	68fa      	ldr	r2, [r7, #12]
+ 8002680:	60da      	str	r2, [r3, #12]
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+ 8002682:	687b      	ldr	r3, [r7, #4]
+ 8002684:	222e      	movs	r2, #46	; 0x2e
+ 8002686:	2101      	movs	r1, #1
+ 8002688:	5499      	strb	r1, [r3, r2]
+
+  /* Return function status */
+  return HAL_OK;
+ 800268a:	2300      	movs	r3, #0
+}
+ 800268c:	0018      	movs	r0, r3
+ 800268e:	46bd      	mov	sp, r7
+ 8002690:	b004      	add	sp, #16
+ 8002692:	bd80      	pop	{r7, pc}
+ 8002694:	0000ffff 	.word	0x0000ffff
+ 8002698:	ffff1f3f 	.word	0xffff1f3f
+ 800269c:	ff19f1fe 	.word	0xff19f1fe
+
+080026a0 <HAL_RCC_OscConfig>:
+  *         supported by this macro. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+ 80026a0:	b5b0      	push	{r4, r5, r7, lr}
+ 80026a2:	b08a      	sub	sp, #40	; 0x28
+ 80026a4:	af00      	add	r7, sp, #0
+ 80026a6:	6078      	str	r0, [r7, #4]
+  uint32_t hsi_state;
+  HAL_StatusTypeDef status;
+  uint32_t sysclk_source, pll_config;
+
+  /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+ 80026a8:	687b      	ldr	r3, [r7, #4]
+ 80026aa:	2b00      	cmp	r3, #0
+ 80026ac:	d102      	bne.n	80026b4 <HAL_RCC_OscConfig+0x14>
+  {
+    return HAL_ERROR;
+ 80026ae:	2301      	movs	r3, #1
+ 80026b0:	f000 fb6c 	bl	8002d8c <HAL_RCC_OscConfig+0x6ec>
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 80026b4:	4bc8      	ldr	r3, [pc, #800]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80026b6:	68db      	ldr	r3, [r3, #12]
+ 80026b8:	220c      	movs	r2, #12
+ 80026ba:	4013      	ands	r3, r2
+ 80026bc:	61fb      	str	r3, [r7, #28]
+  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 80026be:	4bc6      	ldr	r3, [pc, #792]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80026c0:	68da      	ldr	r2, [r3, #12]
+ 80026c2:	2380      	movs	r3, #128	; 0x80
+ 80026c4:	025b      	lsls	r3, r3, #9
+ 80026c6:	4013      	ands	r3, r2
+ 80026c8:	61bb      	str	r3, [r7, #24]
+
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 80026ca:	687b      	ldr	r3, [r7, #4]
+ 80026cc:	681b      	ldr	r3, [r3, #0]
+ 80026ce:	2201      	movs	r2, #1
+ 80026d0:	4013      	ands	r3, r2
+ 80026d2:	d100      	bne.n	80026d6 <HAL_RCC_OscConfig+0x36>
+ 80026d4:	e07d      	b.n	80027d2 <HAL_RCC_OscConfig+0x132>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
+ 80026d6:	69fb      	ldr	r3, [r7, #28]
+ 80026d8:	2b08      	cmp	r3, #8
+ 80026da:	d007      	beq.n	80026ec <HAL_RCC_OscConfig+0x4c>
+       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
+ 80026dc:	69fb      	ldr	r3, [r7, #28]
+ 80026de:	2b0c      	cmp	r3, #12
+ 80026e0:	d112      	bne.n	8002708 <HAL_RCC_OscConfig+0x68>
+ 80026e2:	69ba      	ldr	r2, [r7, #24]
+ 80026e4:	2380      	movs	r3, #128	; 0x80
+ 80026e6:	025b      	lsls	r3, r3, #9
+ 80026e8:	429a      	cmp	r2, r3
+ 80026ea:	d10d      	bne.n	8002708 <HAL_RCC_OscConfig+0x68>
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 80026ec:	4bba      	ldr	r3, [pc, #744]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80026ee:	681a      	ldr	r2, [r3, #0]
+ 80026f0:	2380      	movs	r3, #128	; 0x80
+ 80026f2:	029b      	lsls	r3, r3, #10
+ 80026f4:	4013      	ands	r3, r2
+ 80026f6:	d100      	bne.n	80026fa <HAL_RCC_OscConfig+0x5a>
+ 80026f8:	e06a      	b.n	80027d0 <HAL_RCC_OscConfig+0x130>
+ 80026fa:	687b      	ldr	r3, [r7, #4]
+ 80026fc:	685b      	ldr	r3, [r3, #4]
+ 80026fe:	2b00      	cmp	r3, #0
+ 8002700:	d166      	bne.n	80027d0 <HAL_RCC_OscConfig+0x130>
+      {
+        return HAL_ERROR;
+ 8002702:	2301      	movs	r3, #1
+ 8002704:	f000 fb42 	bl	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 8002708:	687b      	ldr	r3, [r7, #4]
+ 800270a:	685a      	ldr	r2, [r3, #4]
+ 800270c:	2380      	movs	r3, #128	; 0x80
+ 800270e:	025b      	lsls	r3, r3, #9
+ 8002710:	429a      	cmp	r2, r3
+ 8002712:	d107      	bne.n	8002724 <HAL_RCC_OscConfig+0x84>
+ 8002714:	4bb0      	ldr	r3, [pc, #704]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002716:	681a      	ldr	r2, [r3, #0]
+ 8002718:	4baf      	ldr	r3, [pc, #700]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800271a:	2180      	movs	r1, #128	; 0x80
+ 800271c:	0249      	lsls	r1, r1, #9
+ 800271e:	430a      	orrs	r2, r1
+ 8002720:	601a      	str	r2, [r3, #0]
+ 8002722:	e027      	b.n	8002774 <HAL_RCC_OscConfig+0xd4>
+ 8002724:	687b      	ldr	r3, [r7, #4]
+ 8002726:	685a      	ldr	r2, [r3, #4]
+ 8002728:	23a0      	movs	r3, #160	; 0xa0
+ 800272a:	02db      	lsls	r3, r3, #11
+ 800272c:	429a      	cmp	r2, r3
+ 800272e:	d10e      	bne.n	800274e <HAL_RCC_OscConfig+0xae>
+ 8002730:	4ba9      	ldr	r3, [pc, #676]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002732:	681a      	ldr	r2, [r3, #0]
+ 8002734:	4ba8      	ldr	r3, [pc, #672]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002736:	2180      	movs	r1, #128	; 0x80
+ 8002738:	02c9      	lsls	r1, r1, #11
+ 800273a:	430a      	orrs	r2, r1
+ 800273c:	601a      	str	r2, [r3, #0]
+ 800273e:	4ba6      	ldr	r3, [pc, #664]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002740:	681a      	ldr	r2, [r3, #0]
+ 8002742:	4ba5      	ldr	r3, [pc, #660]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002744:	2180      	movs	r1, #128	; 0x80
+ 8002746:	0249      	lsls	r1, r1, #9
+ 8002748:	430a      	orrs	r2, r1
+ 800274a:	601a      	str	r2, [r3, #0]
+ 800274c:	e012      	b.n	8002774 <HAL_RCC_OscConfig+0xd4>
+ 800274e:	4ba2      	ldr	r3, [pc, #648]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002750:	681a      	ldr	r2, [r3, #0]
+ 8002752:	4ba1      	ldr	r3, [pc, #644]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002754:	49a1      	ldr	r1, [pc, #644]	; (80029dc <HAL_RCC_OscConfig+0x33c>)
+ 8002756:	400a      	ands	r2, r1
+ 8002758:	601a      	str	r2, [r3, #0]
+ 800275a:	4b9f      	ldr	r3, [pc, #636]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800275c:	681a      	ldr	r2, [r3, #0]
+ 800275e:	2380      	movs	r3, #128	; 0x80
+ 8002760:	025b      	lsls	r3, r3, #9
+ 8002762:	4013      	ands	r3, r2
+ 8002764:	60fb      	str	r3, [r7, #12]
+ 8002766:	68fb      	ldr	r3, [r7, #12]
+ 8002768:	4b9b      	ldr	r3, [pc, #620]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800276a:	681a      	ldr	r2, [r3, #0]
+ 800276c:	4b9a      	ldr	r3, [pc, #616]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800276e:	499c      	ldr	r1, [pc, #624]	; (80029e0 <HAL_RCC_OscConfig+0x340>)
+ 8002770:	400a      	ands	r2, r1
+ 8002772:	601a      	str	r2, [r3, #0]
+
+      /* Check the HSE State */
+      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 8002774:	687b      	ldr	r3, [r7, #4]
+ 8002776:	685b      	ldr	r3, [r3, #4]
+ 8002778:	2b00      	cmp	r3, #0
+ 800277a:	d014      	beq.n	80027a6 <HAL_RCC_OscConfig+0x106>
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 800277c:	f7ff f80c 	bl	8001798 <HAL_GetTick>
+ 8002780:	0003      	movs	r3, r0
+ 8002782:	617b      	str	r3, [r7, #20]
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 8002784:	e008      	b.n	8002798 <HAL_RCC_OscConfig+0xf8>
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 8002786:	f7ff f807 	bl	8001798 <HAL_GetTick>
+ 800278a:	0002      	movs	r2, r0
+ 800278c:	697b      	ldr	r3, [r7, #20]
+ 800278e:	1ad3      	subs	r3, r2, r3
+ 8002790:	2b64      	cmp	r3, #100	; 0x64
+ 8002792:	d901      	bls.n	8002798 <HAL_RCC_OscConfig+0xf8>
+          {
+            return HAL_TIMEOUT;
+ 8002794:	2303      	movs	r3, #3
+ 8002796:	e2f9      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 8002798:	4b8f      	ldr	r3, [pc, #572]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800279a:	681a      	ldr	r2, [r3, #0]
+ 800279c:	2380      	movs	r3, #128	; 0x80
+ 800279e:	029b      	lsls	r3, r3, #10
+ 80027a0:	4013      	ands	r3, r2
+ 80027a2:	d0f0      	beq.n	8002786 <HAL_RCC_OscConfig+0xe6>
+ 80027a4:	e015      	b.n	80027d2 <HAL_RCC_OscConfig+0x132>
+        }
+      }
+      else
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 80027a6:	f7fe fff7 	bl	8001798 <HAL_GetTick>
+ 80027aa:	0003      	movs	r3, r0
+ 80027ac:	617b      	str	r3, [r7, #20]
+
+        /* Wait till HSE is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+ 80027ae:	e008      	b.n	80027c2 <HAL_RCC_OscConfig+0x122>
+        {
+           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 80027b0:	f7fe fff2 	bl	8001798 <HAL_GetTick>
+ 80027b4:	0002      	movs	r2, r0
+ 80027b6:	697b      	ldr	r3, [r7, #20]
+ 80027b8:	1ad3      	subs	r3, r2, r3
+ 80027ba:	2b64      	cmp	r3, #100	; 0x64
+ 80027bc:	d901      	bls.n	80027c2 <HAL_RCC_OscConfig+0x122>
+          {
+            return HAL_TIMEOUT;
+ 80027be:	2303      	movs	r3, #3
+ 80027c0:	e2e4      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+ 80027c2:	4b85      	ldr	r3, [pc, #532]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80027c4:	681a      	ldr	r2, [r3, #0]
+ 80027c6:	2380      	movs	r3, #128	; 0x80
+ 80027c8:	029b      	lsls	r3, r3, #10
+ 80027ca:	4013      	ands	r3, r2
+ 80027cc:	d1f0      	bne.n	80027b0 <HAL_RCC_OscConfig+0x110>
+ 80027ce:	e000      	b.n	80027d2 <HAL_RCC_OscConfig+0x132>
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 80027d0:	46c0      	nop			; (mov r8, r8)
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 80027d2:	687b      	ldr	r3, [r7, #4]
+ 80027d4:	681b      	ldr	r3, [r3, #0]
+ 80027d6:	2202      	movs	r2, #2
+ 80027d8:	4013      	ands	r3, r2
+ 80027da:	d100      	bne.n	80027de <HAL_RCC_OscConfig+0x13e>
+ 80027dc:	e099      	b.n	8002912 <HAL_RCC_OscConfig+0x272>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    hsi_state = RCC_OscInitStruct->HSIState;
+ 80027de:	687b      	ldr	r3, [r7, #4]
+ 80027e0:	68db      	ldr	r3, [r3, #12]
+ 80027e2:	627b      	str	r3, [r7, #36]	; 0x24
+
+#if defined(RCC_CR_HSIOUTEN)
+    if((hsi_state & RCC_HSI_OUTEN) != 0U)
+ 80027e4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80027e6:	2220      	movs	r2, #32
+ 80027e8:	4013      	ands	r3, r2
+ 80027ea:	d009      	beq.n	8002800 <HAL_RCC_OscConfig+0x160>
+    {
+      /* HSI Output enable for timer requested */
+      SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
+ 80027ec:	4b7a      	ldr	r3, [pc, #488]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80027ee:	681a      	ldr	r2, [r3, #0]
+ 80027f0:	4b79      	ldr	r3, [pc, #484]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80027f2:	2120      	movs	r1, #32
+ 80027f4:	430a      	orrs	r2, r1
+ 80027f6:	601a      	str	r2, [r3, #0]
+
+      hsi_state &= ~RCC_CR_HSIOUTEN;
+ 80027f8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80027fa:	2220      	movs	r2, #32
+ 80027fc:	4393      	bics	r3, r2
+ 80027fe:	627b      	str	r3, [r7, #36]	; 0x24
+    }
+#endif
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
+ 8002800:	69fb      	ldr	r3, [r7, #28]
+ 8002802:	2b04      	cmp	r3, #4
+ 8002804:	d005      	beq.n	8002812 <HAL_RCC_OscConfig+0x172>
+       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
+ 8002806:	69fb      	ldr	r3, [r7, #28]
+ 8002808:	2b0c      	cmp	r3, #12
+ 800280a:	d13e      	bne.n	800288a <HAL_RCC_OscConfig+0x1ea>
+ 800280c:	69bb      	ldr	r3, [r7, #24]
+ 800280e:	2b00      	cmp	r3, #0
+ 8002810:	d13b      	bne.n	800288a <HAL_RCC_OscConfig+0x1ea>
+    {
+      /* When HSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (hsi_state == RCC_HSI_OFF))
+ 8002812:	4b71      	ldr	r3, [pc, #452]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002814:	681b      	ldr	r3, [r3, #0]
+ 8002816:	2204      	movs	r2, #4
+ 8002818:	4013      	ands	r3, r2
+ 800281a:	d004      	beq.n	8002826 <HAL_RCC_OscConfig+0x186>
+ 800281c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800281e:	2b00      	cmp	r3, #0
+ 8002820:	d101      	bne.n	8002826 <HAL_RCC_OscConfig+0x186>
+      {
+        return HAL_ERROR;
+ 8002822:	2301      	movs	r3, #1
+ 8002824:	e2b2      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      }
+      /* Otherwise, just the calibration and HSI or HSIdiv4 are allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8002826:	4b6c      	ldr	r3, [pc, #432]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002828:	685b      	ldr	r3, [r3, #4]
+ 800282a:	4a6e      	ldr	r2, [pc, #440]	; (80029e4 <HAL_RCC_OscConfig+0x344>)
+ 800282c:	4013      	ands	r3, r2
+ 800282e:	0019      	movs	r1, r3
+ 8002830:	687b      	ldr	r3, [r7, #4]
+ 8002832:	691b      	ldr	r3, [r3, #16]
+ 8002834:	021a      	lsls	r2, r3, #8
+ 8002836:	4b68      	ldr	r3, [pc, #416]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002838:	430a      	orrs	r2, r1
+ 800283a:	605a      	str	r2, [r3, #4]
+
+        /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
+        __HAL_RCC_HSI_CONFIG(hsi_state);
+ 800283c:	4b66      	ldr	r3, [pc, #408]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800283e:	681b      	ldr	r3, [r3, #0]
+ 8002840:	2209      	movs	r2, #9
+ 8002842:	4393      	bics	r3, r2
+ 8002844:	0019      	movs	r1, r3
+ 8002846:	4b64      	ldr	r3, [pc, #400]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002848:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 800284a:	430a      	orrs	r2, r1
+ 800284c:	601a      	str	r2, [r3, #0]
+      }
+
+      /* Update the SystemCoreClock global variable */
+      SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+ 800284e:	f000 fbeb 	bl	8003028 <HAL_RCC_GetSysClockFreq>
+ 8002852:	0001      	movs	r1, r0
+ 8002854:	4b60      	ldr	r3, [pc, #384]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002856:	68db      	ldr	r3, [r3, #12]
+ 8002858:	091b      	lsrs	r3, r3, #4
+ 800285a:	220f      	movs	r2, #15
+ 800285c:	4013      	ands	r3, r2
+ 800285e:	4a62      	ldr	r2, [pc, #392]	; (80029e8 <HAL_RCC_OscConfig+0x348>)
+ 8002860:	5cd3      	ldrb	r3, [r2, r3]
+ 8002862:	000a      	movs	r2, r1
+ 8002864:	40da      	lsrs	r2, r3
+ 8002866:	4b61      	ldr	r3, [pc, #388]	; (80029ec <HAL_RCC_OscConfig+0x34c>)
+ 8002868:	601a      	str	r2, [r3, #0]
+
+      /* Configure the source of time base considering new system clocks settings*/
+      status = HAL_InitTick (uwTickPrio);
+ 800286a:	4b61      	ldr	r3, [pc, #388]	; (80029f0 <HAL_RCC_OscConfig+0x350>)
+ 800286c:	681b      	ldr	r3, [r3, #0]
+ 800286e:	2513      	movs	r5, #19
+ 8002870:	197c      	adds	r4, r7, r5
+ 8002872:	0018      	movs	r0, r3
+ 8002874:	f7fe ff4a 	bl	800170c <HAL_InitTick>
+ 8002878:	0003      	movs	r3, r0
+ 800287a:	7023      	strb	r3, [r4, #0]
+      if(status != HAL_OK)
+ 800287c:	197b      	adds	r3, r7, r5
+ 800287e:	781b      	ldrb	r3, [r3, #0]
+ 8002880:	2b00      	cmp	r3, #0
+ 8002882:	d046      	beq.n	8002912 <HAL_RCC_OscConfig+0x272>
+      {
+        return status;
+ 8002884:	197b      	adds	r3, r7, r5
+ 8002886:	781b      	ldrb	r3, [r3, #0]
+ 8002888:	e280      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if(hsi_state != RCC_HSI_OFF)
+ 800288a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800288c:	2b00      	cmp	r3, #0
+ 800288e:	d027      	beq.n	80028e0 <HAL_RCC_OscConfig+0x240>
+      {
+        /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
+        __HAL_RCC_HSI_CONFIG(hsi_state);
+ 8002890:	4b51      	ldr	r3, [pc, #324]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002892:	681b      	ldr	r3, [r3, #0]
+ 8002894:	2209      	movs	r2, #9
+ 8002896:	4393      	bics	r3, r2
+ 8002898:	0019      	movs	r1, r3
+ 800289a:	4b4f      	ldr	r3, [pc, #316]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800289c:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 800289e:	430a      	orrs	r2, r1
+ 80028a0:	601a      	str	r2, [r3, #0]
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 80028a2:	f7fe ff79 	bl	8001798 <HAL_GetTick>
+ 80028a6:	0003      	movs	r3, r0
+ 80028a8:	617b      	str	r3, [r7, #20]
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 80028aa:	e008      	b.n	80028be <HAL_RCC_OscConfig+0x21e>
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 80028ac:	f7fe ff74 	bl	8001798 <HAL_GetTick>
+ 80028b0:	0002      	movs	r2, r0
+ 80028b2:	697b      	ldr	r3, [r7, #20]
+ 80028b4:	1ad3      	subs	r3, r2, r3
+ 80028b6:	2b02      	cmp	r3, #2
+ 80028b8:	d901      	bls.n	80028be <HAL_RCC_OscConfig+0x21e>
+          {
+            return HAL_TIMEOUT;
+ 80028ba:	2303      	movs	r3, #3
+ 80028bc:	e266      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 80028be:	4b46      	ldr	r3, [pc, #280]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80028c0:	681b      	ldr	r3, [r3, #0]
+ 80028c2:	2204      	movs	r2, #4
+ 80028c4:	4013      	ands	r3, r2
+ 80028c6:	d0f1      	beq.n	80028ac <HAL_RCC_OscConfig+0x20c>
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 80028c8:	4b43      	ldr	r3, [pc, #268]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80028ca:	685b      	ldr	r3, [r3, #4]
+ 80028cc:	4a45      	ldr	r2, [pc, #276]	; (80029e4 <HAL_RCC_OscConfig+0x344>)
+ 80028ce:	4013      	ands	r3, r2
+ 80028d0:	0019      	movs	r1, r3
+ 80028d2:	687b      	ldr	r3, [r7, #4]
+ 80028d4:	691b      	ldr	r3, [r3, #16]
+ 80028d6:	021a      	lsls	r2, r3, #8
+ 80028d8:	4b3f      	ldr	r3, [pc, #252]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80028da:	430a      	orrs	r2, r1
+ 80028dc:	605a      	str	r2, [r3, #4]
+ 80028de:	e018      	b.n	8002912 <HAL_RCC_OscConfig+0x272>
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+ 80028e0:	4b3d      	ldr	r3, [pc, #244]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80028e2:	681a      	ldr	r2, [r3, #0]
+ 80028e4:	4b3c      	ldr	r3, [pc, #240]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80028e6:	2101      	movs	r1, #1
+ 80028e8:	438a      	bics	r2, r1
+ 80028ea:	601a      	str	r2, [r3, #0]
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 80028ec:	f7fe ff54 	bl	8001798 <HAL_GetTick>
+ 80028f0:	0003      	movs	r3, r0
+ 80028f2:	617b      	str	r3, [r7, #20]
+
+        /* Wait till HSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+ 80028f4:	e008      	b.n	8002908 <HAL_RCC_OscConfig+0x268>
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 80028f6:	f7fe ff4f 	bl	8001798 <HAL_GetTick>
+ 80028fa:	0002      	movs	r2, r0
+ 80028fc:	697b      	ldr	r3, [r7, #20]
+ 80028fe:	1ad3      	subs	r3, r2, r3
+ 8002900:	2b02      	cmp	r3, #2
+ 8002902:	d901      	bls.n	8002908 <HAL_RCC_OscConfig+0x268>
+          {
+            return HAL_TIMEOUT;
+ 8002904:	2303      	movs	r3, #3
+ 8002906:	e241      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+ 8002908:	4b33      	ldr	r3, [pc, #204]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800290a:	681b      	ldr	r3, [r3, #0]
+ 800290c:	2204      	movs	r2, #4
+ 800290e:	4013      	ands	r3, r2
+ 8002910:	d1f1      	bne.n	80028f6 <HAL_RCC_OscConfig+0x256>
+        }
+      }
+    }
+  }
+  /*----------------------------- MSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
+ 8002912:	687b      	ldr	r3, [r7, #4]
+ 8002914:	681b      	ldr	r3, [r3, #0]
+ 8002916:	2210      	movs	r2, #16
+ 8002918:	4013      	ands	r3, r2
+ 800291a:	d100      	bne.n	800291e <HAL_RCC_OscConfig+0x27e>
+ 800291c:	e0a1      	b.n	8002a62 <HAL_RCC_OscConfig+0x3c2>
+  {
+    /* When the MSI is used as system clock it will not be disabled */
+    if(sysclk_source == RCC_CFGR_SWS_MSI)
+ 800291e:	69fb      	ldr	r3, [r7, #28]
+ 8002920:	2b00      	cmp	r3, #0
+ 8002922:	d140      	bne.n	80029a6 <HAL_RCC_OscConfig+0x306>
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
+ 8002924:	4b2c      	ldr	r3, [pc, #176]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002926:	681a      	ldr	r2, [r3, #0]
+ 8002928:	2380      	movs	r3, #128	; 0x80
+ 800292a:	009b      	lsls	r3, r3, #2
+ 800292c:	4013      	ands	r3, r2
+ 800292e:	d005      	beq.n	800293c <HAL_RCC_OscConfig+0x29c>
+ 8002930:	687b      	ldr	r3, [r7, #4]
+ 8002932:	699b      	ldr	r3, [r3, #24]
+ 8002934:	2b00      	cmp	r3, #0
+ 8002936:	d101      	bne.n	800293c <HAL_RCC_OscConfig+0x29c>
+      {
+        return HAL_ERROR;
+ 8002938:	2301      	movs	r3, #1
+ 800293a:	e227      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        /* Check MSICalibrationValue and MSIClockRange input parameters */
+        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
+        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
+
+        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
+        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
+ 800293c:	4b26      	ldr	r3, [pc, #152]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800293e:	685b      	ldr	r3, [r3, #4]
+ 8002940:	4a2c      	ldr	r2, [pc, #176]	; (80029f4 <HAL_RCC_OscConfig+0x354>)
+ 8002942:	4013      	ands	r3, r2
+ 8002944:	0019      	movs	r1, r3
+ 8002946:	687b      	ldr	r3, [r7, #4]
+ 8002948:	6a1a      	ldr	r2, [r3, #32]
+ 800294a:	4b23      	ldr	r3, [pc, #140]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 800294c:	430a      	orrs	r2, r1
+ 800294e:	605a      	str	r2, [r3, #4]
+        /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
+        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
+ 8002950:	4b21      	ldr	r3, [pc, #132]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002952:	685b      	ldr	r3, [r3, #4]
+ 8002954:	021b      	lsls	r3, r3, #8
+ 8002956:	0a19      	lsrs	r1, r3, #8
+ 8002958:	687b      	ldr	r3, [r7, #4]
+ 800295a:	69db      	ldr	r3, [r3, #28]
+ 800295c:	061a      	lsls	r2, r3, #24
+ 800295e:	4b1e      	ldr	r3, [pc, #120]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002960:	430a      	orrs	r2, r1
+ 8002962:	605a      	str	r2, [r3, #4]
+
+
+        /* Update the SystemCoreClock global variable */
+        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
+ 8002964:	687b      	ldr	r3, [r7, #4]
+ 8002966:	6a1b      	ldr	r3, [r3, #32]
+ 8002968:	0b5b      	lsrs	r3, r3, #13
+ 800296a:	3301      	adds	r3, #1
+ 800296c:	2280      	movs	r2, #128	; 0x80
+ 800296e:	0212      	lsls	r2, r2, #8
+ 8002970:	409a      	lsls	r2, r3
+                           >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+ 8002972:	4b19      	ldr	r3, [pc, #100]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 8002974:	68db      	ldr	r3, [r3, #12]
+ 8002976:	091b      	lsrs	r3, r3, #4
+ 8002978:	210f      	movs	r1, #15
+ 800297a:	400b      	ands	r3, r1
+ 800297c:	491a      	ldr	r1, [pc, #104]	; (80029e8 <HAL_RCC_OscConfig+0x348>)
+ 800297e:	5ccb      	ldrb	r3, [r1, r3]
+ 8002980:	40da      	lsrs	r2, r3
+        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
+ 8002982:	4b1a      	ldr	r3, [pc, #104]	; (80029ec <HAL_RCC_OscConfig+0x34c>)
+ 8002984:	601a      	str	r2, [r3, #0]
+
+        /* Configure the source of time base considering new system clocks settings*/
+        status = HAL_InitTick (uwTickPrio);
+ 8002986:	4b1a      	ldr	r3, [pc, #104]	; (80029f0 <HAL_RCC_OscConfig+0x350>)
+ 8002988:	681b      	ldr	r3, [r3, #0]
+ 800298a:	2513      	movs	r5, #19
+ 800298c:	197c      	adds	r4, r7, r5
+ 800298e:	0018      	movs	r0, r3
+ 8002990:	f7fe febc 	bl	800170c <HAL_InitTick>
+ 8002994:	0003      	movs	r3, r0
+ 8002996:	7023      	strb	r3, [r4, #0]
+        if(status != HAL_OK)
+ 8002998:	197b      	adds	r3, r7, r5
+ 800299a:	781b      	ldrb	r3, [r3, #0]
+ 800299c:	2b00      	cmp	r3, #0
+ 800299e:	d060      	beq.n	8002a62 <HAL_RCC_OscConfig+0x3c2>
+        {
+          return status;
+ 80029a0:	197b      	adds	r3, r7, r5
+ 80029a2:	781b      	ldrb	r3, [r3, #0]
+ 80029a4:	e1f2      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+    {
+      /* Check MSI State */
+      assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
+
+      /* Check the MSI State */
+      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
+ 80029a6:	687b      	ldr	r3, [r7, #4]
+ 80029a8:	699b      	ldr	r3, [r3, #24]
+ 80029aa:	2b00      	cmp	r3, #0
+ 80029ac:	d03f      	beq.n	8002a2e <HAL_RCC_OscConfig+0x38e>
+      {
+        /* Enable the Multi Speed oscillator (MSI). */
+        __HAL_RCC_MSI_ENABLE();
+ 80029ae:	4b0a      	ldr	r3, [pc, #40]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80029b0:	681a      	ldr	r2, [r3, #0]
+ 80029b2:	4b09      	ldr	r3, [pc, #36]	; (80029d8 <HAL_RCC_OscConfig+0x338>)
+ 80029b4:	2180      	movs	r1, #128	; 0x80
+ 80029b6:	0049      	lsls	r1, r1, #1
+ 80029b8:	430a      	orrs	r2, r1
+ 80029ba:	601a      	str	r2, [r3, #0]
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 80029bc:	f7fe feec 	bl	8001798 <HAL_GetTick>
+ 80029c0:	0003      	movs	r3, r0
+ 80029c2:	617b      	str	r3, [r7, #20]
+
+        /* Wait till MSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
+ 80029c4:	e018      	b.n	80029f8 <HAL_RCC_OscConfig+0x358>
+        {
+          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
+ 80029c6:	f7fe fee7 	bl	8001798 <HAL_GetTick>
+ 80029ca:	0002      	movs	r2, r0
+ 80029cc:	697b      	ldr	r3, [r7, #20]
+ 80029ce:	1ad3      	subs	r3, r2, r3
+ 80029d0:	2b02      	cmp	r3, #2
+ 80029d2:	d911      	bls.n	80029f8 <HAL_RCC_OscConfig+0x358>
+          {
+            return HAL_TIMEOUT;
+ 80029d4:	2303      	movs	r3, #3
+ 80029d6:	e1d9      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+ 80029d8:	40021000 	.word	0x40021000
+ 80029dc:	fffeffff 	.word	0xfffeffff
+ 80029e0:	fffbffff 	.word	0xfffbffff
+ 80029e4:	ffffe0ff 	.word	0xffffe0ff
+ 80029e8:	08007884 	.word	0x08007884
+ 80029ec:	20000000 	.word	0x20000000
+ 80029f0:	20000004 	.word	0x20000004
+ 80029f4:	ffff1fff 	.word	0xffff1fff
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
+ 80029f8:	4bc9      	ldr	r3, [pc, #804]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 80029fa:	681a      	ldr	r2, [r3, #0]
+ 80029fc:	2380      	movs	r3, #128	; 0x80
+ 80029fe:	009b      	lsls	r3, r3, #2
+ 8002a00:	4013      	ands	r3, r2
+ 8002a02:	d0e0      	beq.n	80029c6 <HAL_RCC_OscConfig+0x326>
+        /* Check MSICalibrationValue and MSIClockRange input parameters */
+        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
+        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
+
+        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
+        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
+ 8002a04:	4bc6      	ldr	r3, [pc, #792]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a06:	685b      	ldr	r3, [r3, #4]
+ 8002a08:	4ac6      	ldr	r2, [pc, #792]	; (8002d24 <HAL_RCC_OscConfig+0x684>)
+ 8002a0a:	4013      	ands	r3, r2
+ 8002a0c:	0019      	movs	r1, r3
+ 8002a0e:	687b      	ldr	r3, [r7, #4]
+ 8002a10:	6a1a      	ldr	r2, [r3, #32]
+ 8002a12:	4bc3      	ldr	r3, [pc, #780]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a14:	430a      	orrs	r2, r1
+ 8002a16:	605a      	str	r2, [r3, #4]
+         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
+        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
+ 8002a18:	4bc1      	ldr	r3, [pc, #772]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a1a:	685b      	ldr	r3, [r3, #4]
+ 8002a1c:	021b      	lsls	r3, r3, #8
+ 8002a1e:	0a19      	lsrs	r1, r3, #8
+ 8002a20:	687b      	ldr	r3, [r7, #4]
+ 8002a22:	69db      	ldr	r3, [r3, #28]
+ 8002a24:	061a      	lsls	r2, r3, #24
+ 8002a26:	4bbe      	ldr	r3, [pc, #760]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a28:	430a      	orrs	r2, r1
+ 8002a2a:	605a      	str	r2, [r3, #4]
+ 8002a2c:	e019      	b.n	8002a62 <HAL_RCC_OscConfig+0x3c2>
+      }
+      else
+      {
+        /* Disable the Multi Speed oscillator (MSI). */
+        __HAL_RCC_MSI_DISABLE();
+ 8002a2e:	4bbc      	ldr	r3, [pc, #752]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a30:	681a      	ldr	r2, [r3, #0]
+ 8002a32:	4bbb      	ldr	r3, [pc, #748]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a34:	49bc      	ldr	r1, [pc, #752]	; (8002d28 <HAL_RCC_OscConfig+0x688>)
+ 8002a36:	400a      	ands	r2, r1
+ 8002a38:	601a      	str	r2, [r3, #0]
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8002a3a:	f7fe fead 	bl	8001798 <HAL_GetTick>
+ 8002a3e:	0003      	movs	r3, r0
+ 8002a40:	617b      	str	r3, [r7, #20]
+
+        /* Wait till MSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
+ 8002a42:	e008      	b.n	8002a56 <HAL_RCC_OscConfig+0x3b6>
+        {
+          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
+ 8002a44:	f7fe fea8 	bl	8001798 <HAL_GetTick>
+ 8002a48:	0002      	movs	r2, r0
+ 8002a4a:	697b      	ldr	r3, [r7, #20]
+ 8002a4c:	1ad3      	subs	r3, r2, r3
+ 8002a4e:	2b02      	cmp	r3, #2
+ 8002a50:	d901      	bls.n	8002a56 <HAL_RCC_OscConfig+0x3b6>
+          {
+            return HAL_TIMEOUT;
+ 8002a52:	2303      	movs	r3, #3
+ 8002a54:	e19a      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
+ 8002a56:	4bb2      	ldr	r3, [pc, #712]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a58:	681a      	ldr	r2, [r3, #0]
+ 8002a5a:	2380      	movs	r3, #128	; 0x80
+ 8002a5c:	009b      	lsls	r3, r3, #2
+ 8002a5e:	4013      	ands	r3, r2
+ 8002a60:	d1f0      	bne.n	8002a44 <HAL_RCC_OscConfig+0x3a4>
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 8002a62:	687b      	ldr	r3, [r7, #4]
+ 8002a64:	681b      	ldr	r3, [r3, #0]
+ 8002a66:	2208      	movs	r2, #8
+ 8002a68:	4013      	ands	r3, r2
+ 8002a6a:	d036      	beq.n	8002ada <HAL_RCC_OscConfig+0x43a>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ 8002a6c:	687b      	ldr	r3, [r7, #4]
+ 8002a6e:	695b      	ldr	r3, [r3, #20]
+ 8002a70:	2b00      	cmp	r3, #0
+ 8002a72:	d019      	beq.n	8002aa8 <HAL_RCC_OscConfig+0x408>
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+ 8002a74:	4baa      	ldr	r3, [pc, #680]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a76:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002a78:	4ba9      	ldr	r3, [pc, #676]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a7a:	2101      	movs	r1, #1
+ 8002a7c:	430a      	orrs	r2, r1
+ 8002a7e:	651a      	str	r2, [r3, #80]	; 0x50
+
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8002a80:	f7fe fe8a 	bl	8001798 <HAL_GetTick>
+ 8002a84:	0003      	movs	r3, r0
+ 8002a86:	617b      	str	r3, [r7, #20]
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+ 8002a88:	e008      	b.n	8002a9c <HAL_RCC_OscConfig+0x3fc>
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 8002a8a:	f7fe fe85 	bl	8001798 <HAL_GetTick>
+ 8002a8e:	0002      	movs	r2, r0
+ 8002a90:	697b      	ldr	r3, [r7, #20]
+ 8002a92:	1ad3      	subs	r3, r2, r3
+ 8002a94:	2b02      	cmp	r3, #2
+ 8002a96:	d901      	bls.n	8002a9c <HAL_RCC_OscConfig+0x3fc>
+        {
+          return HAL_TIMEOUT;
+ 8002a98:	2303      	movs	r3, #3
+ 8002a9a:	e177      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+ 8002a9c:	4ba0      	ldr	r3, [pc, #640]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002a9e:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8002aa0:	2202      	movs	r2, #2
+ 8002aa2:	4013      	ands	r3, r2
+ 8002aa4:	d0f1      	beq.n	8002a8a <HAL_RCC_OscConfig+0x3ea>
+ 8002aa6:	e018      	b.n	8002ada <HAL_RCC_OscConfig+0x43a>
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+ 8002aa8:	4b9d      	ldr	r3, [pc, #628]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002aaa:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002aac:	4b9c      	ldr	r3, [pc, #624]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002aae:	2101      	movs	r1, #1
+ 8002ab0:	438a      	bics	r2, r1
+ 8002ab2:	651a      	str	r2, [r3, #80]	; 0x50
+
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8002ab4:	f7fe fe70 	bl	8001798 <HAL_GetTick>
+ 8002ab8:	0003      	movs	r3, r0
+ 8002aba:	617b      	str	r3, [r7, #20]
+
+      /* Wait till LSI is disabled */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+ 8002abc:	e008      	b.n	8002ad0 <HAL_RCC_OscConfig+0x430>
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 8002abe:	f7fe fe6b 	bl	8001798 <HAL_GetTick>
+ 8002ac2:	0002      	movs	r2, r0
+ 8002ac4:	697b      	ldr	r3, [r7, #20]
+ 8002ac6:	1ad3      	subs	r3, r2, r3
+ 8002ac8:	2b02      	cmp	r3, #2
+ 8002aca:	d901      	bls.n	8002ad0 <HAL_RCC_OscConfig+0x430>
+        {
+          return HAL_TIMEOUT;
+ 8002acc:	2303      	movs	r3, #3
+ 8002ace:	e15d      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+ 8002ad0:	4b93      	ldr	r3, [pc, #588]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002ad2:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8002ad4:	2202      	movs	r2, #2
+ 8002ad6:	4013      	ands	r3, r2
+ 8002ad8:	d1f1      	bne.n	8002abe <HAL_RCC_OscConfig+0x41e>
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 8002ada:	687b      	ldr	r3, [r7, #4]
+ 8002adc:	681b      	ldr	r3, [r3, #0]
+ 8002ade:	2204      	movs	r2, #4
+ 8002ae0:	4013      	ands	r3, r2
+ 8002ae2:	d100      	bne.n	8002ae6 <HAL_RCC_OscConfig+0x446>
+ 8002ae4:	e0ae      	b.n	8002c44 <HAL_RCC_OscConfig+0x5a4>
+  {
+    FlagStatus       pwrclkchanged = RESET;
+ 8002ae6:	2023      	movs	r0, #35	; 0x23
+ 8002ae8:	183b      	adds	r3, r7, r0
+ 8002aea:	2200      	movs	r2, #0
+ 8002aec:	701a      	strb	r2, [r3, #0]
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 8002aee:	4b8c      	ldr	r3, [pc, #560]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002af0:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8002af2:	2380      	movs	r3, #128	; 0x80
+ 8002af4:	055b      	lsls	r3, r3, #21
+ 8002af6:	4013      	ands	r3, r2
+ 8002af8:	d109      	bne.n	8002b0e <HAL_RCC_OscConfig+0x46e>
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+ 8002afa:	4b89      	ldr	r3, [pc, #548]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002afc:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8002afe:	4b88      	ldr	r3, [pc, #544]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002b00:	2180      	movs	r1, #128	; 0x80
+ 8002b02:	0549      	lsls	r1, r1, #21
+ 8002b04:	430a      	orrs	r2, r1
+ 8002b06:	639a      	str	r2, [r3, #56]	; 0x38
+      pwrclkchanged = SET;
+ 8002b08:	183b      	adds	r3, r7, r0
+ 8002b0a:	2201      	movs	r2, #1
+ 8002b0c:	701a      	strb	r2, [r3, #0]
+    }
+
+    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 8002b0e:	4b87      	ldr	r3, [pc, #540]	; (8002d2c <HAL_RCC_OscConfig+0x68c>)
+ 8002b10:	681a      	ldr	r2, [r3, #0]
+ 8002b12:	2380      	movs	r3, #128	; 0x80
+ 8002b14:	005b      	lsls	r3, r3, #1
+ 8002b16:	4013      	ands	r3, r2
+ 8002b18:	d11a      	bne.n	8002b50 <HAL_RCC_OscConfig+0x4b0>
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+ 8002b1a:	4b84      	ldr	r3, [pc, #528]	; (8002d2c <HAL_RCC_OscConfig+0x68c>)
+ 8002b1c:	681a      	ldr	r2, [r3, #0]
+ 8002b1e:	4b83      	ldr	r3, [pc, #524]	; (8002d2c <HAL_RCC_OscConfig+0x68c>)
+ 8002b20:	2180      	movs	r1, #128	; 0x80
+ 8002b22:	0049      	lsls	r1, r1, #1
+ 8002b24:	430a      	orrs	r2, r1
+ 8002b26:	601a      	str	r2, [r3, #0]
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+ 8002b28:	f7fe fe36 	bl	8001798 <HAL_GetTick>
+ 8002b2c:	0003      	movs	r3, r0
+ 8002b2e:	617b      	str	r3, [r7, #20]
+
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 8002b30:	e008      	b.n	8002b44 <HAL_RCC_OscConfig+0x4a4>
+      {
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 8002b32:	f7fe fe31 	bl	8001798 <HAL_GetTick>
+ 8002b36:	0002      	movs	r2, r0
+ 8002b38:	697b      	ldr	r3, [r7, #20]
+ 8002b3a:	1ad3      	subs	r3, r2, r3
+ 8002b3c:	2b64      	cmp	r3, #100	; 0x64
+ 8002b3e:	d901      	bls.n	8002b44 <HAL_RCC_OscConfig+0x4a4>
+        {
+          return HAL_TIMEOUT;
+ 8002b40:	2303      	movs	r3, #3
+ 8002b42:	e123      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 8002b44:	4b79      	ldr	r3, [pc, #484]	; (8002d2c <HAL_RCC_OscConfig+0x68c>)
+ 8002b46:	681a      	ldr	r2, [r3, #0]
+ 8002b48:	2380      	movs	r3, #128	; 0x80
+ 8002b4a:	005b      	lsls	r3, r3, #1
+ 8002b4c:	4013      	ands	r3, r2
+ 8002b4e:	d0f0      	beq.n	8002b32 <HAL_RCC_OscConfig+0x492>
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 8002b50:	687b      	ldr	r3, [r7, #4]
+ 8002b52:	689a      	ldr	r2, [r3, #8]
+ 8002b54:	2380      	movs	r3, #128	; 0x80
+ 8002b56:	005b      	lsls	r3, r3, #1
+ 8002b58:	429a      	cmp	r2, r3
+ 8002b5a:	d107      	bne.n	8002b6c <HAL_RCC_OscConfig+0x4cc>
+ 8002b5c:	4b70      	ldr	r3, [pc, #448]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002b5e:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002b60:	4b6f      	ldr	r3, [pc, #444]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002b62:	2180      	movs	r1, #128	; 0x80
+ 8002b64:	0049      	lsls	r1, r1, #1
+ 8002b66:	430a      	orrs	r2, r1
+ 8002b68:	651a      	str	r2, [r3, #80]	; 0x50
+ 8002b6a:	e031      	b.n	8002bd0 <HAL_RCC_OscConfig+0x530>
+ 8002b6c:	687b      	ldr	r3, [r7, #4]
+ 8002b6e:	689b      	ldr	r3, [r3, #8]
+ 8002b70:	2b00      	cmp	r3, #0
+ 8002b72:	d10c      	bne.n	8002b8e <HAL_RCC_OscConfig+0x4ee>
+ 8002b74:	4b6a      	ldr	r3, [pc, #424]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002b76:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002b78:	4b69      	ldr	r3, [pc, #420]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002b7a:	496b      	ldr	r1, [pc, #428]	; (8002d28 <HAL_RCC_OscConfig+0x688>)
+ 8002b7c:	400a      	ands	r2, r1
+ 8002b7e:	651a      	str	r2, [r3, #80]	; 0x50
+ 8002b80:	4b67      	ldr	r3, [pc, #412]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002b82:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002b84:	4b66      	ldr	r3, [pc, #408]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002b86:	496a      	ldr	r1, [pc, #424]	; (8002d30 <HAL_RCC_OscConfig+0x690>)
+ 8002b88:	400a      	ands	r2, r1
+ 8002b8a:	651a      	str	r2, [r3, #80]	; 0x50
+ 8002b8c:	e020      	b.n	8002bd0 <HAL_RCC_OscConfig+0x530>
+ 8002b8e:	687b      	ldr	r3, [r7, #4]
+ 8002b90:	689a      	ldr	r2, [r3, #8]
+ 8002b92:	23a0      	movs	r3, #160	; 0xa0
+ 8002b94:	00db      	lsls	r3, r3, #3
+ 8002b96:	429a      	cmp	r2, r3
+ 8002b98:	d10e      	bne.n	8002bb8 <HAL_RCC_OscConfig+0x518>
+ 8002b9a:	4b61      	ldr	r3, [pc, #388]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002b9c:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002b9e:	4b60      	ldr	r3, [pc, #384]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002ba0:	2180      	movs	r1, #128	; 0x80
+ 8002ba2:	00c9      	lsls	r1, r1, #3
+ 8002ba4:	430a      	orrs	r2, r1
+ 8002ba6:	651a      	str	r2, [r3, #80]	; 0x50
+ 8002ba8:	4b5d      	ldr	r3, [pc, #372]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002baa:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002bac:	4b5c      	ldr	r3, [pc, #368]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002bae:	2180      	movs	r1, #128	; 0x80
+ 8002bb0:	0049      	lsls	r1, r1, #1
+ 8002bb2:	430a      	orrs	r2, r1
+ 8002bb4:	651a      	str	r2, [r3, #80]	; 0x50
+ 8002bb6:	e00b      	b.n	8002bd0 <HAL_RCC_OscConfig+0x530>
+ 8002bb8:	4b59      	ldr	r3, [pc, #356]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002bba:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002bbc:	4b58      	ldr	r3, [pc, #352]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002bbe:	495a      	ldr	r1, [pc, #360]	; (8002d28 <HAL_RCC_OscConfig+0x688>)
+ 8002bc0:	400a      	ands	r2, r1
+ 8002bc2:	651a      	str	r2, [r3, #80]	; 0x50
+ 8002bc4:	4b56      	ldr	r3, [pc, #344]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002bc6:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002bc8:	4b55      	ldr	r3, [pc, #340]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002bca:	4959      	ldr	r1, [pc, #356]	; (8002d30 <HAL_RCC_OscConfig+0x690>)
+ 8002bcc:	400a      	ands	r2, r1
+ 8002bce:	651a      	str	r2, [r3, #80]	; 0x50
+
+    /* Check the LSE State */
+    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ 8002bd0:	687b      	ldr	r3, [r7, #4]
+ 8002bd2:	689b      	ldr	r3, [r3, #8]
+ 8002bd4:	2b00      	cmp	r3, #0
+ 8002bd6:	d015      	beq.n	8002c04 <HAL_RCC_OscConfig+0x564>
+    {
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8002bd8:	f7fe fdde 	bl	8001798 <HAL_GetTick>
+ 8002bdc:	0003      	movs	r3, r0
+ 8002bde:	617b      	str	r3, [r7, #20]
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 8002be0:	e009      	b.n	8002bf6 <HAL_RCC_OscConfig+0x556>
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 8002be2:	f7fe fdd9 	bl	8001798 <HAL_GetTick>
+ 8002be6:	0002      	movs	r2, r0
+ 8002be8:	697b      	ldr	r3, [r7, #20]
+ 8002bea:	1ad3      	subs	r3, r2, r3
+ 8002bec:	4a51      	ldr	r2, [pc, #324]	; (8002d34 <HAL_RCC_OscConfig+0x694>)
+ 8002bee:	4293      	cmp	r3, r2
+ 8002bf0:	d901      	bls.n	8002bf6 <HAL_RCC_OscConfig+0x556>
+        {
+          return HAL_TIMEOUT;
+ 8002bf2:	2303      	movs	r3, #3
+ 8002bf4:	e0ca      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 8002bf6:	4b4a      	ldr	r3, [pc, #296]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002bf8:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002bfa:	2380      	movs	r3, #128	; 0x80
+ 8002bfc:	009b      	lsls	r3, r3, #2
+ 8002bfe:	4013      	ands	r3, r2
+ 8002c00:	d0ef      	beq.n	8002be2 <HAL_RCC_OscConfig+0x542>
+ 8002c02:	e014      	b.n	8002c2e <HAL_RCC_OscConfig+0x58e>
+      }
+    }
+    else
+    {
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8002c04:	f7fe fdc8 	bl	8001798 <HAL_GetTick>
+ 8002c08:	0003      	movs	r3, r0
+ 8002c0a:	617b      	str	r3, [r7, #20]
+
+      /* Wait till LSE is disabled */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+ 8002c0c:	e009      	b.n	8002c22 <HAL_RCC_OscConfig+0x582>
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 8002c0e:	f7fe fdc3 	bl	8001798 <HAL_GetTick>
+ 8002c12:	0002      	movs	r2, r0
+ 8002c14:	697b      	ldr	r3, [r7, #20]
+ 8002c16:	1ad3      	subs	r3, r2, r3
+ 8002c18:	4a46      	ldr	r2, [pc, #280]	; (8002d34 <HAL_RCC_OscConfig+0x694>)
+ 8002c1a:	4293      	cmp	r3, r2
+ 8002c1c:	d901      	bls.n	8002c22 <HAL_RCC_OscConfig+0x582>
+        {
+          return HAL_TIMEOUT;
+ 8002c1e:	2303      	movs	r3, #3
+ 8002c20:	e0b4      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+ 8002c22:	4b3f      	ldr	r3, [pc, #252]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002c24:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8002c26:	2380      	movs	r3, #128	; 0x80
+ 8002c28:	009b      	lsls	r3, r3, #2
+ 8002c2a:	4013      	ands	r3, r2
+ 8002c2c:	d1ef      	bne.n	8002c0e <HAL_RCC_OscConfig+0x56e>
+        }
+      }
+    }
+
+    /* Require to disable power clock if necessary */
+    if(pwrclkchanged == SET)
+ 8002c2e:	2323      	movs	r3, #35	; 0x23
+ 8002c30:	18fb      	adds	r3, r7, r3
+ 8002c32:	781b      	ldrb	r3, [r3, #0]
+ 8002c34:	2b01      	cmp	r3, #1
+ 8002c36:	d105      	bne.n	8002c44 <HAL_RCC_OscConfig+0x5a4>
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+ 8002c38:	4b39      	ldr	r3, [pc, #228]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002c3a:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8002c3c:	4b38      	ldr	r3, [pc, #224]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002c3e:	493e      	ldr	r1, [pc, #248]	; (8002d38 <HAL_RCC_OscConfig+0x698>)
+ 8002c40:	400a      	ands	r2, r1
+ 8002c42:	639a      	str	r2, [r3, #56]	; 0x38
+#endif /* RCC_HSI48_SUPPORT */
+
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 8002c44:	687b      	ldr	r3, [r7, #4]
+ 8002c46:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8002c48:	2b00      	cmp	r3, #0
+ 8002c4a:	d100      	bne.n	8002c4e <HAL_RCC_OscConfig+0x5ae>
+ 8002c4c:	e09d      	b.n	8002d8a <HAL_RCC_OscConfig+0x6ea>
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 8002c4e:	69fb      	ldr	r3, [r7, #28]
+ 8002c50:	2b0c      	cmp	r3, #12
+ 8002c52:	d100      	bne.n	8002c56 <HAL_RCC_OscConfig+0x5b6>
+ 8002c54:	e076      	b.n	8002d44 <HAL_RCC_OscConfig+0x6a4>
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 8002c56:	687b      	ldr	r3, [r7, #4]
+ 8002c58:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8002c5a:	2b02      	cmp	r3, #2
+ 8002c5c:	d145      	bne.n	8002cea <HAL_RCC_OscConfig+0x64a>
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+        assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 8002c5e:	4b30      	ldr	r3, [pc, #192]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002c60:	681a      	ldr	r2, [r3, #0]
+ 8002c62:	4b2f      	ldr	r3, [pc, #188]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002c64:	4935      	ldr	r1, [pc, #212]	; (8002d3c <HAL_RCC_OscConfig+0x69c>)
+ 8002c66:	400a      	ands	r2, r1
+ 8002c68:	601a      	str	r2, [r3, #0]
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8002c6a:	f7fe fd95 	bl	8001798 <HAL_GetTick>
+ 8002c6e:	0003      	movs	r3, r0
+ 8002c70:	617b      	str	r3, [r7, #20]
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
+ 8002c72:	e008      	b.n	8002c86 <HAL_RCC_OscConfig+0x5e6>
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8002c74:	f7fe fd90 	bl	8001798 <HAL_GetTick>
+ 8002c78:	0002      	movs	r2, r0
+ 8002c7a:	697b      	ldr	r3, [r7, #20]
+ 8002c7c:	1ad3      	subs	r3, r2, r3
+ 8002c7e:	2b02      	cmp	r3, #2
+ 8002c80:	d901      	bls.n	8002c86 <HAL_RCC_OscConfig+0x5e6>
+          {
+            return HAL_TIMEOUT;
+ 8002c82:	2303      	movs	r3, #3
+ 8002c84:	e082      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
+ 8002c86:	4b26      	ldr	r3, [pc, #152]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002c88:	681a      	ldr	r2, [r3, #0]
+ 8002c8a:	2380      	movs	r3, #128	; 0x80
+ 8002c8c:	049b      	lsls	r3, r3, #18
+ 8002c8e:	4013      	ands	r3, r2
+ 8002c90:	d1f0      	bne.n	8002c74 <HAL_RCC_OscConfig+0x5d4>
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 8002c92:	4b23      	ldr	r3, [pc, #140]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002c94:	68db      	ldr	r3, [r3, #12]
+ 8002c96:	4a2a      	ldr	r2, [pc, #168]	; (8002d40 <HAL_RCC_OscConfig+0x6a0>)
+ 8002c98:	4013      	ands	r3, r2
+ 8002c9a:	0019      	movs	r1, r3
+ 8002c9c:	687b      	ldr	r3, [r7, #4]
+ 8002c9e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8002ca0:	687b      	ldr	r3, [r7, #4]
+ 8002ca2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8002ca4:	431a      	orrs	r2, r3
+ 8002ca6:	687b      	ldr	r3, [r7, #4]
+ 8002ca8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8002caa:	431a      	orrs	r2, r3
+ 8002cac:	4b1c      	ldr	r3, [pc, #112]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002cae:	430a      	orrs	r2, r1
+ 8002cb0:	60da      	str	r2, [r3, #12]
+                             RCC_OscInitStruct->PLL.PLLMUL,
+                             RCC_OscInitStruct->PLL.PLLDIV);
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+ 8002cb2:	4b1b      	ldr	r3, [pc, #108]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002cb4:	681a      	ldr	r2, [r3, #0]
+ 8002cb6:	4b1a      	ldr	r3, [pc, #104]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002cb8:	2180      	movs	r1, #128	; 0x80
+ 8002cba:	0449      	lsls	r1, r1, #17
+ 8002cbc:	430a      	orrs	r2, r1
+ 8002cbe:	601a      	str	r2, [r3, #0]
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8002cc0:	f7fe fd6a 	bl	8001798 <HAL_GetTick>
+ 8002cc4:	0003      	movs	r3, r0
+ 8002cc6:	617b      	str	r3, [r7, #20]
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == 0U)
+ 8002cc8:	e008      	b.n	8002cdc <HAL_RCC_OscConfig+0x63c>
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8002cca:	f7fe fd65 	bl	8001798 <HAL_GetTick>
+ 8002cce:	0002      	movs	r2, r0
+ 8002cd0:	697b      	ldr	r3, [r7, #20]
+ 8002cd2:	1ad3      	subs	r3, r2, r3
+ 8002cd4:	2b02      	cmp	r3, #2
+ 8002cd6:	d901      	bls.n	8002cdc <HAL_RCC_OscConfig+0x63c>
+          {
+            return HAL_TIMEOUT;
+ 8002cd8:	2303      	movs	r3, #3
+ 8002cda:	e057      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == 0U)
+ 8002cdc:	4b10      	ldr	r3, [pc, #64]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002cde:	681a      	ldr	r2, [r3, #0]
+ 8002ce0:	2380      	movs	r3, #128	; 0x80
+ 8002ce2:	049b      	lsls	r3, r3, #18
+ 8002ce4:	4013      	ands	r3, r2
+ 8002ce6:	d0f0      	beq.n	8002cca <HAL_RCC_OscConfig+0x62a>
+ 8002ce8:	e04f      	b.n	8002d8a <HAL_RCC_OscConfig+0x6ea>
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 8002cea:	4b0d      	ldr	r3, [pc, #52]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002cec:	681a      	ldr	r2, [r3, #0]
+ 8002cee:	4b0c      	ldr	r3, [pc, #48]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002cf0:	4912      	ldr	r1, [pc, #72]	; (8002d3c <HAL_RCC_OscConfig+0x69c>)
+ 8002cf2:	400a      	ands	r2, r1
+ 8002cf4:	601a      	str	r2, [r3, #0]
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8002cf6:	f7fe fd4f 	bl	8001798 <HAL_GetTick>
+ 8002cfa:	0003      	movs	r3, r0
+ 8002cfc:	617b      	str	r3, [r7, #20]
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
+ 8002cfe:	e008      	b.n	8002d12 <HAL_RCC_OscConfig+0x672>
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8002d00:	f7fe fd4a 	bl	8001798 <HAL_GetTick>
+ 8002d04:	0002      	movs	r2, r0
+ 8002d06:	697b      	ldr	r3, [r7, #20]
+ 8002d08:	1ad3      	subs	r3, r2, r3
+ 8002d0a:	2b02      	cmp	r3, #2
+ 8002d0c:	d901      	bls.n	8002d12 <HAL_RCC_OscConfig+0x672>
+          {
+            return HAL_TIMEOUT;
+ 8002d0e:	2303      	movs	r3, #3
+ 8002d10:	e03c      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
+ 8002d12:	4b03      	ldr	r3, [pc, #12]	; (8002d20 <HAL_RCC_OscConfig+0x680>)
+ 8002d14:	681a      	ldr	r2, [r3, #0]
+ 8002d16:	2380      	movs	r3, #128	; 0x80
+ 8002d18:	049b      	lsls	r3, r3, #18
+ 8002d1a:	4013      	ands	r3, r2
+ 8002d1c:	d1f0      	bne.n	8002d00 <HAL_RCC_OscConfig+0x660>
+ 8002d1e:	e034      	b.n	8002d8a <HAL_RCC_OscConfig+0x6ea>
+ 8002d20:	40021000 	.word	0x40021000
+ 8002d24:	ffff1fff 	.word	0xffff1fff
+ 8002d28:	fffffeff 	.word	0xfffffeff
+ 8002d2c:	40007000 	.word	0x40007000
+ 8002d30:	fffffbff 	.word	0xfffffbff
+ 8002d34:	00001388 	.word	0x00001388
+ 8002d38:	efffffff 	.word	0xefffffff
+ 8002d3c:	feffffff 	.word	0xfeffffff
+ 8002d40:	ff02ffff 	.word	0xff02ffff
+      }
+    }
+    else
+    {
+      /* Check if there is a request to disable the PLL used as System clock source */
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+ 8002d44:	687b      	ldr	r3, [r7, #4]
+ 8002d46:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8002d48:	2b01      	cmp	r3, #1
+ 8002d4a:	d101      	bne.n	8002d50 <HAL_RCC_OscConfig+0x6b0>
+      {
+        return HAL_ERROR;
+ 8002d4c:	2301      	movs	r3, #1
+ 8002d4e:	e01d      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+      }
+      else
+      {
+        /* Do not return HAL_ERROR if request repeats the current configuration */
+        pll_config = RCC->CFGR;
+ 8002d50:	4b10      	ldr	r3, [pc, #64]	; (8002d94 <HAL_RCC_OscConfig+0x6f4>)
+ 8002d52:	68db      	ldr	r3, [r3, #12]
+ 8002d54:	61bb      	str	r3, [r7, #24]
+        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 8002d56:	69ba      	ldr	r2, [r7, #24]
+ 8002d58:	2380      	movs	r3, #128	; 0x80
+ 8002d5a:	025b      	lsls	r3, r3, #9
+ 8002d5c:	401a      	ands	r2, r3
+ 8002d5e:	687b      	ldr	r3, [r7, #4]
+ 8002d60:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8002d62:	429a      	cmp	r2, r3
+ 8002d64:	d10f      	bne.n	8002d86 <HAL_RCC_OscConfig+0x6e6>
+           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
+ 8002d66:	69ba      	ldr	r2, [r7, #24]
+ 8002d68:	23f0      	movs	r3, #240	; 0xf0
+ 8002d6a:	039b      	lsls	r3, r3, #14
+ 8002d6c:	401a      	ands	r2, r3
+ 8002d6e:	687b      	ldr	r3, [r7, #4]
+ 8002d70:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 8002d72:	429a      	cmp	r2, r3
+ 8002d74:	d107      	bne.n	8002d86 <HAL_RCC_OscConfig+0x6e6>
+           (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
+ 8002d76:	69ba      	ldr	r2, [r7, #24]
+ 8002d78:	23c0      	movs	r3, #192	; 0xc0
+ 8002d7a:	041b      	lsls	r3, r3, #16
+ 8002d7c:	401a      	ands	r2, r3
+ 8002d7e:	687b      	ldr	r3, [r7, #4]
+ 8002d80:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
+ 8002d82:	429a      	cmp	r2, r3
+ 8002d84:	d001      	beq.n	8002d8a <HAL_RCC_OscConfig+0x6ea>
+        {
+          return HAL_ERROR;
+ 8002d86:	2301      	movs	r3, #1
+ 8002d88:	e000      	b.n	8002d8c <HAL_RCC_OscConfig+0x6ec>
+        }
+      }
+    }
+  }
+  return HAL_OK;
+ 8002d8a:	2300      	movs	r3, #0
+}
+ 8002d8c:	0018      	movs	r0, r3
+ 8002d8e:	46bd      	mov	sp, r7
+ 8002d90:	b00a      	add	sp, #40	; 0x28
+ 8002d92:	bdb0      	pop	{r4, r5, r7, pc}
+ 8002d94:	40021000 	.word	0x40021000
+
+08002d98 <HAL_RCC_ClockConfig>:
+  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ 8002d98:	b5b0      	push	{r4, r5, r7, lr}
+ 8002d9a:	b084      	sub	sp, #16
+ 8002d9c:	af00      	add	r7, sp, #0
+ 8002d9e:	6078      	str	r0, [r7, #4]
+ 8002da0:	6039      	str	r1, [r7, #0]
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+
+  /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+ 8002da2:	687b      	ldr	r3, [r7, #4]
+ 8002da4:	2b00      	cmp	r3, #0
+ 8002da6:	d101      	bne.n	8002dac <HAL_RCC_ClockConfig+0x14>
+  {
+    return HAL_ERROR;
+ 8002da8:	2301      	movs	r3, #1
+ 8002daa:	e128      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+  must be correctly programmed according to the frequency of the CPU clock
+  (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+ 8002dac:	4b96      	ldr	r3, [pc, #600]	; (8003008 <HAL_RCC_ClockConfig+0x270>)
+ 8002dae:	681b      	ldr	r3, [r3, #0]
+ 8002db0:	2201      	movs	r2, #1
+ 8002db2:	4013      	ands	r3, r2
+ 8002db4:	683a      	ldr	r2, [r7, #0]
+ 8002db6:	429a      	cmp	r2, r3
+ 8002db8:	d91e      	bls.n	8002df8 <HAL_RCC_ClockConfig+0x60>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 8002dba:	4b93      	ldr	r3, [pc, #588]	; (8003008 <HAL_RCC_ClockConfig+0x270>)
+ 8002dbc:	681b      	ldr	r3, [r3, #0]
+ 8002dbe:	2201      	movs	r2, #1
+ 8002dc0:	4393      	bics	r3, r2
+ 8002dc2:	0019      	movs	r1, r3
+ 8002dc4:	4b90      	ldr	r3, [pc, #576]	; (8003008 <HAL_RCC_ClockConfig+0x270>)
+ 8002dc6:	683a      	ldr	r2, [r7, #0]
+ 8002dc8:	430a      	orrs	r2, r1
+ 8002dca:	601a      	str	r2, [r3, #0]
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by polling the FLASH_ACR register */
+    tickstart = HAL_GetTick();
+ 8002dcc:	f7fe fce4 	bl	8001798 <HAL_GetTick>
+ 8002dd0:	0003      	movs	r3, r0
+ 8002dd2:	60fb      	str	r3, [r7, #12]
+
+    while (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8002dd4:	e009      	b.n	8002dea <HAL_RCC_ClockConfig+0x52>
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8002dd6:	f7fe fcdf 	bl	8001798 <HAL_GetTick>
+ 8002dda:	0002      	movs	r2, r0
+ 8002ddc:	68fb      	ldr	r3, [r7, #12]
+ 8002dde:	1ad3      	subs	r3, r2, r3
+ 8002de0:	4a8a      	ldr	r2, [pc, #552]	; (800300c <HAL_RCC_ClockConfig+0x274>)
+ 8002de2:	4293      	cmp	r3, r2
+ 8002de4:	d901      	bls.n	8002dea <HAL_RCC_ClockConfig+0x52>
+      {
+        return HAL_TIMEOUT;
+ 8002de6:	2303      	movs	r3, #3
+ 8002de8:	e109      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+    while (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8002dea:	4b87      	ldr	r3, [pc, #540]	; (8003008 <HAL_RCC_ClockConfig+0x270>)
+ 8002dec:	681b      	ldr	r3, [r3, #0]
+ 8002dee:	2201      	movs	r2, #1
+ 8002df0:	4013      	ands	r3, r2
+ 8002df2:	683a      	ldr	r2, [r7, #0]
+ 8002df4:	429a      	cmp	r2, r3
+ 8002df6:	d1ee      	bne.n	8002dd6 <HAL_RCC_ClockConfig+0x3e>
+      }
+    }
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 8002df8:	687b      	ldr	r3, [r7, #4]
+ 8002dfa:	681b      	ldr	r3, [r3, #0]
+ 8002dfc:	2202      	movs	r2, #2
+ 8002dfe:	4013      	ands	r3, r2
+ 8002e00:	d009      	beq.n	8002e16 <HAL_RCC_ClockConfig+0x7e>
+  {
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 8002e02:	4b83      	ldr	r3, [pc, #524]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002e04:	68db      	ldr	r3, [r3, #12]
+ 8002e06:	22f0      	movs	r2, #240	; 0xf0
+ 8002e08:	4393      	bics	r3, r2
+ 8002e0a:	0019      	movs	r1, r3
+ 8002e0c:	687b      	ldr	r3, [r7, #4]
+ 8002e0e:	689a      	ldr	r2, [r3, #8]
+ 8002e10:	4b7f      	ldr	r3, [pc, #508]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002e12:	430a      	orrs	r2, r1
+ 8002e14:	60da      	str	r2, [r3, #12]
+  }
+
+  /*------------------------- SYSCLK Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 8002e16:	687b      	ldr	r3, [r7, #4]
+ 8002e18:	681b      	ldr	r3, [r3, #0]
+ 8002e1a:	2201      	movs	r2, #1
+ 8002e1c:	4013      	ands	r3, r2
+ 8002e1e:	d100      	bne.n	8002e22 <HAL_RCC_ClockConfig+0x8a>
+ 8002e20:	e089      	b.n	8002f36 <HAL_RCC_ClockConfig+0x19e>
+  {
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+    /* HSE is selected as System Clock Source */
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 8002e22:	687b      	ldr	r3, [r7, #4]
+ 8002e24:	685b      	ldr	r3, [r3, #4]
+ 8002e26:	2b02      	cmp	r3, #2
+ 8002e28:	d107      	bne.n	8002e3a <HAL_RCC_ClockConfig+0xa2>
+    {
+      /* Check the HSE ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 8002e2a:	4b79      	ldr	r3, [pc, #484]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002e2c:	681a      	ldr	r2, [r3, #0]
+ 8002e2e:	2380      	movs	r3, #128	; 0x80
+ 8002e30:	029b      	lsls	r3, r3, #10
+ 8002e32:	4013      	ands	r3, r2
+ 8002e34:	d120      	bne.n	8002e78 <HAL_RCC_ClockConfig+0xe0>
+      {
+        return HAL_ERROR;
+ 8002e36:	2301      	movs	r3, #1
+ 8002e38:	e0e1      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+      }
+    }
+    /* PLL is selected as System Clock Source */
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 8002e3a:	687b      	ldr	r3, [r7, #4]
+ 8002e3c:	685b      	ldr	r3, [r3, #4]
+ 8002e3e:	2b03      	cmp	r3, #3
+ 8002e40:	d107      	bne.n	8002e52 <HAL_RCC_ClockConfig+0xba>
+    {
+      /* Check the PLL ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+ 8002e42:	4b73      	ldr	r3, [pc, #460]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002e44:	681a      	ldr	r2, [r3, #0]
+ 8002e46:	2380      	movs	r3, #128	; 0x80
+ 8002e48:	049b      	lsls	r3, r3, #18
+ 8002e4a:	4013      	ands	r3, r2
+ 8002e4c:	d114      	bne.n	8002e78 <HAL_RCC_ClockConfig+0xe0>
+      {
+        return HAL_ERROR;
+ 8002e4e:	2301      	movs	r3, #1
+ 8002e50:	e0d5      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+      }
+    }
+    /* HSI is selected as System Clock Source */
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
+ 8002e52:	687b      	ldr	r3, [r7, #4]
+ 8002e54:	685b      	ldr	r3, [r3, #4]
+ 8002e56:	2b01      	cmp	r3, #1
+ 8002e58:	d106      	bne.n	8002e68 <HAL_RCC_ClockConfig+0xd0>
+    {
+      /* Check the HSI ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 8002e5a:	4b6d      	ldr	r3, [pc, #436]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002e5c:	681b      	ldr	r3, [r3, #0]
+ 8002e5e:	2204      	movs	r2, #4
+ 8002e60:	4013      	ands	r3, r2
+ 8002e62:	d109      	bne.n	8002e78 <HAL_RCC_ClockConfig+0xe0>
+      {
+        return HAL_ERROR;
+ 8002e64:	2301      	movs	r3, #1
+ 8002e66:	e0ca      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+    }
+    /* MSI is selected as System Clock Source */
+    else
+    {
+      /* Check the MSI ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
+ 8002e68:	4b69      	ldr	r3, [pc, #420]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002e6a:	681a      	ldr	r2, [r3, #0]
+ 8002e6c:	2380      	movs	r3, #128	; 0x80
+ 8002e6e:	009b      	lsls	r3, r3, #2
+ 8002e70:	4013      	ands	r3, r2
+ 8002e72:	d101      	bne.n	8002e78 <HAL_RCC_ClockConfig+0xe0>
+      {
+        return HAL_ERROR;
+ 8002e74:	2301      	movs	r3, #1
+ 8002e76:	e0c2      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+      }
+    }
+    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ 8002e78:	4b65      	ldr	r3, [pc, #404]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002e7a:	68db      	ldr	r3, [r3, #12]
+ 8002e7c:	2203      	movs	r2, #3
+ 8002e7e:	4393      	bics	r3, r2
+ 8002e80:	0019      	movs	r1, r3
+ 8002e82:	687b      	ldr	r3, [r7, #4]
+ 8002e84:	685a      	ldr	r2, [r3, #4]
+ 8002e86:	4b62      	ldr	r3, [pc, #392]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002e88:	430a      	orrs	r2, r1
+ 8002e8a:	60da      	str	r2, [r3, #12]
+
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+ 8002e8c:	f7fe fc84 	bl	8001798 <HAL_GetTick>
+ 8002e90:	0003      	movs	r3, r0
+ 8002e92:	60fb      	str	r3, [r7, #12]
+
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 8002e94:	687b      	ldr	r3, [r7, #4]
+ 8002e96:	685b      	ldr	r3, [r3, #4]
+ 8002e98:	2b02      	cmp	r3, #2
+ 8002e9a:	d111      	bne.n	8002ec0 <HAL_RCC_ClockConfig+0x128>
+    {
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ 8002e9c:	e009      	b.n	8002eb2 <HAL_RCC_ClockConfig+0x11a>
+      {
+        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8002e9e:	f7fe fc7b 	bl	8001798 <HAL_GetTick>
+ 8002ea2:	0002      	movs	r2, r0
+ 8002ea4:	68fb      	ldr	r3, [r7, #12]
+ 8002ea6:	1ad3      	subs	r3, r2, r3
+ 8002ea8:	4a58      	ldr	r2, [pc, #352]	; (800300c <HAL_RCC_ClockConfig+0x274>)
+ 8002eaa:	4293      	cmp	r3, r2
+ 8002eac:	d901      	bls.n	8002eb2 <HAL_RCC_ClockConfig+0x11a>
+        {
+          return HAL_TIMEOUT;
+ 8002eae:	2303      	movs	r3, #3
+ 8002eb0:	e0a5      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ 8002eb2:	4b57      	ldr	r3, [pc, #348]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002eb4:	68db      	ldr	r3, [r3, #12]
+ 8002eb6:	220c      	movs	r2, #12
+ 8002eb8:	4013      	ands	r3, r2
+ 8002eba:	2b08      	cmp	r3, #8
+ 8002ebc:	d1ef      	bne.n	8002e9e <HAL_RCC_ClockConfig+0x106>
+ 8002ebe:	e03a      	b.n	8002f36 <HAL_RCC_ClockConfig+0x19e>
+        }
+      }
+    }
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 8002ec0:	687b      	ldr	r3, [r7, #4]
+ 8002ec2:	685b      	ldr	r3, [r3, #4]
+ 8002ec4:	2b03      	cmp	r3, #3
+ 8002ec6:	d111      	bne.n	8002eec <HAL_RCC_ClockConfig+0x154>
+    {
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 8002ec8:	e009      	b.n	8002ede <HAL_RCC_ClockConfig+0x146>
+      {
+        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8002eca:	f7fe fc65 	bl	8001798 <HAL_GetTick>
+ 8002ece:	0002      	movs	r2, r0
+ 8002ed0:	68fb      	ldr	r3, [r7, #12]
+ 8002ed2:	1ad3      	subs	r3, r2, r3
+ 8002ed4:	4a4d      	ldr	r2, [pc, #308]	; (800300c <HAL_RCC_ClockConfig+0x274>)
+ 8002ed6:	4293      	cmp	r3, r2
+ 8002ed8:	d901      	bls.n	8002ede <HAL_RCC_ClockConfig+0x146>
+        {
+          return HAL_TIMEOUT;
+ 8002eda:	2303      	movs	r3, #3
+ 8002edc:	e08f      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 8002ede:	4b4c      	ldr	r3, [pc, #304]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002ee0:	68db      	ldr	r3, [r3, #12]
+ 8002ee2:	220c      	movs	r2, #12
+ 8002ee4:	4013      	ands	r3, r2
+ 8002ee6:	2b0c      	cmp	r3, #12
+ 8002ee8:	d1ef      	bne.n	8002eca <HAL_RCC_ClockConfig+0x132>
+ 8002eea:	e024      	b.n	8002f36 <HAL_RCC_ClockConfig+0x19e>
+        }
+      }
+    }
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
+ 8002eec:	687b      	ldr	r3, [r7, #4]
+ 8002eee:	685b      	ldr	r3, [r3, #4]
+ 8002ef0:	2b01      	cmp	r3, #1
+ 8002ef2:	d11b      	bne.n	8002f2c <HAL_RCC_ClockConfig+0x194>
+    {
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ 8002ef4:	e009      	b.n	8002f0a <HAL_RCC_ClockConfig+0x172>
+      {
+        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8002ef6:	f7fe fc4f 	bl	8001798 <HAL_GetTick>
+ 8002efa:	0002      	movs	r2, r0
+ 8002efc:	68fb      	ldr	r3, [r7, #12]
+ 8002efe:	1ad3      	subs	r3, r2, r3
+ 8002f00:	4a42      	ldr	r2, [pc, #264]	; (800300c <HAL_RCC_ClockConfig+0x274>)
+ 8002f02:	4293      	cmp	r3, r2
+ 8002f04:	d901      	bls.n	8002f0a <HAL_RCC_ClockConfig+0x172>
+        {
+          return HAL_TIMEOUT;
+ 8002f06:	2303      	movs	r3, #3
+ 8002f08:	e079      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ 8002f0a:	4b41      	ldr	r3, [pc, #260]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002f0c:	68db      	ldr	r3, [r3, #12]
+ 8002f0e:	220c      	movs	r2, #12
+ 8002f10:	4013      	ands	r3, r2
+ 8002f12:	2b04      	cmp	r3, #4
+ 8002f14:	d1ef      	bne.n	8002ef6 <HAL_RCC_ClockConfig+0x15e>
+ 8002f16:	e00e      	b.n	8002f36 <HAL_RCC_ClockConfig+0x19e>
+    }
+    else
+    {
+      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
+      {
+        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8002f18:	f7fe fc3e 	bl	8001798 <HAL_GetTick>
+ 8002f1c:	0002      	movs	r2, r0
+ 8002f1e:	68fb      	ldr	r3, [r7, #12]
+ 8002f20:	1ad3      	subs	r3, r2, r3
+ 8002f22:	4a3a      	ldr	r2, [pc, #232]	; (800300c <HAL_RCC_ClockConfig+0x274>)
+ 8002f24:	4293      	cmp	r3, r2
+ 8002f26:	d901      	bls.n	8002f2c <HAL_RCC_ClockConfig+0x194>
+        {
+          return HAL_TIMEOUT;
+ 8002f28:	2303      	movs	r3, #3
+ 8002f2a:	e068      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
+ 8002f2c:	4b38      	ldr	r3, [pc, #224]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002f2e:	68db      	ldr	r3, [r3, #12]
+ 8002f30:	220c      	movs	r2, #12
+ 8002f32:	4013      	ands	r3, r2
+ 8002f34:	d1f0      	bne.n	8002f18 <HAL_RCC_ClockConfig+0x180>
+        }
+      }
+    }
+  }
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+ 8002f36:	4b34      	ldr	r3, [pc, #208]	; (8003008 <HAL_RCC_ClockConfig+0x270>)
+ 8002f38:	681b      	ldr	r3, [r3, #0]
+ 8002f3a:	2201      	movs	r2, #1
+ 8002f3c:	4013      	ands	r3, r2
+ 8002f3e:	683a      	ldr	r2, [r7, #0]
+ 8002f40:	429a      	cmp	r2, r3
+ 8002f42:	d21e      	bcs.n	8002f82 <HAL_RCC_ClockConfig+0x1ea>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 8002f44:	4b30      	ldr	r3, [pc, #192]	; (8003008 <HAL_RCC_ClockConfig+0x270>)
+ 8002f46:	681b      	ldr	r3, [r3, #0]
+ 8002f48:	2201      	movs	r2, #1
+ 8002f4a:	4393      	bics	r3, r2
+ 8002f4c:	0019      	movs	r1, r3
+ 8002f4e:	4b2e      	ldr	r3, [pc, #184]	; (8003008 <HAL_RCC_ClockConfig+0x270>)
+ 8002f50:	683a      	ldr	r2, [r7, #0]
+ 8002f52:	430a      	orrs	r2, r1
+ 8002f54:	601a      	str	r2, [r3, #0]
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by polling the FLASH_ACR register */
+    tickstart = HAL_GetTick();
+ 8002f56:	f7fe fc1f 	bl	8001798 <HAL_GetTick>
+ 8002f5a:	0003      	movs	r3, r0
+ 8002f5c:	60fb      	str	r3, [r7, #12]
+
+    while (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8002f5e:	e009      	b.n	8002f74 <HAL_RCC_ClockConfig+0x1dc>
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8002f60:	f7fe fc1a 	bl	8001798 <HAL_GetTick>
+ 8002f64:	0002      	movs	r2, r0
+ 8002f66:	68fb      	ldr	r3, [r7, #12]
+ 8002f68:	1ad3      	subs	r3, r2, r3
+ 8002f6a:	4a28      	ldr	r2, [pc, #160]	; (800300c <HAL_RCC_ClockConfig+0x274>)
+ 8002f6c:	4293      	cmp	r3, r2
+ 8002f6e:	d901      	bls.n	8002f74 <HAL_RCC_ClockConfig+0x1dc>
+      {
+        return HAL_TIMEOUT;
+ 8002f70:	2303      	movs	r3, #3
+ 8002f72:	e044      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+    while (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8002f74:	4b24      	ldr	r3, [pc, #144]	; (8003008 <HAL_RCC_ClockConfig+0x270>)
+ 8002f76:	681b      	ldr	r3, [r3, #0]
+ 8002f78:	2201      	movs	r2, #1
+ 8002f7a:	4013      	ands	r3, r2
+ 8002f7c:	683a      	ldr	r2, [r7, #0]
+ 8002f7e:	429a      	cmp	r2, r3
+ 8002f80:	d1ee      	bne.n	8002f60 <HAL_RCC_ClockConfig+0x1c8>
+      }
+    }
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8002f82:	687b      	ldr	r3, [r7, #4]
+ 8002f84:	681b      	ldr	r3, [r3, #0]
+ 8002f86:	2204      	movs	r2, #4
+ 8002f88:	4013      	ands	r3, r2
+ 8002f8a:	d009      	beq.n	8002fa0 <HAL_RCC_ClockConfig+0x208>
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 8002f8c:	4b20      	ldr	r3, [pc, #128]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002f8e:	68db      	ldr	r3, [r3, #12]
+ 8002f90:	4a20      	ldr	r2, [pc, #128]	; (8003014 <HAL_RCC_ClockConfig+0x27c>)
+ 8002f92:	4013      	ands	r3, r2
+ 8002f94:	0019      	movs	r1, r3
+ 8002f96:	687b      	ldr	r3, [r7, #4]
+ 8002f98:	68da      	ldr	r2, [r3, #12]
+ 8002f9a:	4b1d      	ldr	r3, [pc, #116]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002f9c:	430a      	orrs	r2, r1
+ 8002f9e:	60da      	str	r2, [r3, #12]
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 8002fa0:	687b      	ldr	r3, [r7, #4]
+ 8002fa2:	681b      	ldr	r3, [r3, #0]
+ 8002fa4:	2208      	movs	r2, #8
+ 8002fa6:	4013      	ands	r3, r2
+ 8002fa8:	d00a      	beq.n	8002fc0 <HAL_RCC_ClockConfig+0x228>
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ 8002faa:	4b19      	ldr	r3, [pc, #100]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002fac:	68db      	ldr	r3, [r3, #12]
+ 8002fae:	4a1a      	ldr	r2, [pc, #104]	; (8003018 <HAL_RCC_ClockConfig+0x280>)
+ 8002fb0:	4013      	ands	r3, r2
+ 8002fb2:	0019      	movs	r1, r3
+ 8002fb4:	687b      	ldr	r3, [r7, #4]
+ 8002fb6:	691b      	ldr	r3, [r3, #16]
+ 8002fb8:	00da      	lsls	r2, r3, #3
+ 8002fba:	4b15      	ldr	r3, [pc, #84]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002fbc:	430a      	orrs	r2, r1
+ 8002fbe:	60da      	str	r2, [r3, #12]
+  }
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+ 8002fc0:	f000 f832 	bl	8003028 <HAL_RCC_GetSysClockFreq>
+ 8002fc4:	0001      	movs	r1, r0
+ 8002fc6:	4b12      	ldr	r3, [pc, #72]	; (8003010 <HAL_RCC_ClockConfig+0x278>)
+ 8002fc8:	68db      	ldr	r3, [r3, #12]
+ 8002fca:	091b      	lsrs	r3, r3, #4
+ 8002fcc:	220f      	movs	r2, #15
+ 8002fce:	4013      	ands	r3, r2
+ 8002fd0:	4a12      	ldr	r2, [pc, #72]	; (800301c <HAL_RCC_ClockConfig+0x284>)
+ 8002fd2:	5cd3      	ldrb	r3, [r2, r3]
+ 8002fd4:	000a      	movs	r2, r1
+ 8002fd6:	40da      	lsrs	r2, r3
+ 8002fd8:	4b11      	ldr	r3, [pc, #68]	; (8003020 <HAL_RCC_ClockConfig+0x288>)
+ 8002fda:	601a      	str	r2, [r3, #0]
+
+  /* Configure the source of time base considering new system clocks settings*/
+  status = HAL_InitTick(uwTickPrio);
+ 8002fdc:	4b11      	ldr	r3, [pc, #68]	; (8003024 <HAL_RCC_ClockConfig+0x28c>)
+ 8002fde:	681b      	ldr	r3, [r3, #0]
+ 8002fe0:	250b      	movs	r5, #11
+ 8002fe2:	197c      	adds	r4, r7, r5
+ 8002fe4:	0018      	movs	r0, r3
+ 8002fe6:	f7fe fb91 	bl	800170c <HAL_InitTick>
+ 8002fea:	0003      	movs	r3, r0
+ 8002fec:	7023      	strb	r3, [r4, #0]
+  if(status != HAL_OK)
+ 8002fee:	197b      	adds	r3, r7, r5
+ 8002ff0:	781b      	ldrb	r3, [r3, #0]
+ 8002ff2:	2b00      	cmp	r3, #0
+ 8002ff4:	d002      	beq.n	8002ffc <HAL_RCC_ClockConfig+0x264>
+  {
+    return status;
+ 8002ff6:	197b      	adds	r3, r7, r5
+ 8002ff8:	781b      	ldrb	r3, [r3, #0]
+ 8002ffa:	e000      	b.n	8002ffe <HAL_RCC_ClockConfig+0x266>
+  }
+
+  return HAL_OK;
+ 8002ffc:	2300      	movs	r3, #0
+}
+ 8002ffe:	0018      	movs	r0, r3
+ 8003000:	46bd      	mov	sp, r7
+ 8003002:	b004      	add	sp, #16
+ 8003004:	bdb0      	pop	{r4, r5, r7, pc}
+ 8003006:	46c0      	nop			; (mov r8, r8)
+ 8003008:	40022000 	.word	0x40022000
+ 800300c:	00001388 	.word	0x00001388
+ 8003010:	40021000 	.word	0x40021000
+ 8003014:	fffff8ff 	.word	0xfffff8ff
+ 8003018:	ffffc7ff 	.word	0xffffc7ff
+ 800301c:	08007884 	.word	0x08007884
+ 8003020:	20000000 	.word	0x20000000
+ 8003024:	20000004 	.word	0x20000004
+
+08003028 <HAL_RCC_GetSysClockFreq>:
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ 8003028:	b5b0      	push	{r4, r5, r7, lr}
+ 800302a:	b08e      	sub	sp, #56	; 0x38
+ 800302c:	af00      	add	r7, sp, #0
+  uint32_t tmpreg, pllm, plld, pllvco, msiclkrange;    /* no init needed */
+  uint32_t sysclockfreq;
+
+  tmpreg = RCC->CFGR;
+ 800302e:	4b4c      	ldr	r3, [pc, #304]	; (8003160 <HAL_RCC_GetSysClockFreq+0x138>)
+ 8003030:	68db      	ldr	r3, [r3, #12]
+ 8003032:	62fb      	str	r3, [r7, #44]	; 0x2c
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (tmpreg & RCC_CFGR_SWS)
+ 8003034:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 8003036:	230c      	movs	r3, #12
+ 8003038:	4013      	ands	r3, r2
+ 800303a:	2b0c      	cmp	r3, #12
+ 800303c:	d014      	beq.n	8003068 <HAL_RCC_GetSysClockFreq+0x40>
+ 800303e:	d900      	bls.n	8003042 <HAL_RCC_GetSysClockFreq+0x1a>
+ 8003040:	e07b      	b.n	800313a <HAL_RCC_GetSysClockFreq+0x112>
+ 8003042:	2b04      	cmp	r3, #4
+ 8003044:	d002      	beq.n	800304c <HAL_RCC_GetSysClockFreq+0x24>
+ 8003046:	2b08      	cmp	r3, #8
+ 8003048:	d00b      	beq.n	8003062 <HAL_RCC_GetSysClockFreq+0x3a>
+ 800304a:	e076      	b.n	800313a <HAL_RCC_GetSysClockFreq+0x112>
+  {
+    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
+    {
+      if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
+ 800304c:	4b44      	ldr	r3, [pc, #272]	; (8003160 <HAL_RCC_GetSysClockFreq+0x138>)
+ 800304e:	681b      	ldr	r3, [r3, #0]
+ 8003050:	2210      	movs	r2, #16
+ 8003052:	4013      	ands	r3, r2
+ 8003054:	d002      	beq.n	800305c <HAL_RCC_GetSysClockFreq+0x34>
+      {
+        sysclockfreq =  (HSI_VALUE >> 2);
+ 8003056:	4b43      	ldr	r3, [pc, #268]	; (8003164 <HAL_RCC_GetSysClockFreq+0x13c>)
+ 8003058:	633b      	str	r3, [r7, #48]	; 0x30
+      }
+      else
+      {
+        sysclockfreq =  HSI_VALUE;
+      }
+      break;
+ 800305a:	e07c      	b.n	8003156 <HAL_RCC_GetSysClockFreq+0x12e>
+        sysclockfreq =  HSI_VALUE;
+ 800305c:	4b42      	ldr	r3, [pc, #264]	; (8003168 <HAL_RCC_GetSysClockFreq+0x140>)
+ 800305e:	633b      	str	r3, [r7, #48]	; 0x30
+      break;
+ 8003060:	e079      	b.n	8003156 <HAL_RCC_GetSysClockFreq+0x12e>
+    }
+    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
+    {
+      sysclockfreq = HSE_VALUE;
+ 8003062:	4b42      	ldr	r3, [pc, #264]	; (800316c <HAL_RCC_GetSysClockFreq+0x144>)
+ 8003064:	633b      	str	r3, [r7, #48]	; 0x30
+      break;
+ 8003066:	e076      	b.n	8003156 <HAL_RCC_GetSysClockFreq+0x12e>
+    }
+    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
+    {
+      pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
+ 8003068:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800306a:	0c9a      	lsrs	r2, r3, #18
+ 800306c:	230f      	movs	r3, #15
+ 800306e:	401a      	ands	r2, r3
+ 8003070:	4b3f      	ldr	r3, [pc, #252]	; (8003170 <HAL_RCC_GetSysClockFreq+0x148>)
+ 8003072:	5c9b      	ldrb	r3, [r3, r2]
+ 8003074:	62bb      	str	r3, [r7, #40]	; 0x28
+      plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
+ 8003076:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8003078:	0d9a      	lsrs	r2, r3, #22
+ 800307a:	2303      	movs	r3, #3
+ 800307c:	4013      	ands	r3, r2
+ 800307e:	3301      	adds	r3, #1
+ 8003080:	627b      	str	r3, [r7, #36]	; 0x24
+      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+ 8003082:	4b37      	ldr	r3, [pc, #220]	; (8003160 <HAL_RCC_GetSysClockFreq+0x138>)
+ 8003084:	68da      	ldr	r2, [r3, #12]
+ 8003086:	2380      	movs	r3, #128	; 0x80
+ 8003088:	025b      	lsls	r3, r3, #9
+ 800308a:	4013      	ands	r3, r2
+ 800308c:	d01a      	beq.n	80030c4 <HAL_RCC_GetSysClockFreq+0x9c>
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
+ 800308e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8003090:	61bb      	str	r3, [r7, #24]
+ 8003092:	2300      	movs	r3, #0
+ 8003094:	61fb      	str	r3, [r7, #28]
+ 8003096:	4a35      	ldr	r2, [pc, #212]	; (800316c <HAL_RCC_GetSysClockFreq+0x144>)
+ 8003098:	2300      	movs	r3, #0
+ 800309a:	69b8      	ldr	r0, [r7, #24]
+ 800309c:	69f9      	ldr	r1, [r7, #28]
+ 800309e:	f7fd f8df 	bl	8000260 <__aeabi_lmul>
+ 80030a2:	0002      	movs	r2, r0
+ 80030a4:	000b      	movs	r3, r1
+ 80030a6:	0010      	movs	r0, r2
+ 80030a8:	0019      	movs	r1, r3
+ 80030aa:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80030ac:	613b      	str	r3, [r7, #16]
+ 80030ae:	2300      	movs	r3, #0
+ 80030b0:	617b      	str	r3, [r7, #20]
+ 80030b2:	693a      	ldr	r2, [r7, #16]
+ 80030b4:	697b      	ldr	r3, [r7, #20]
+ 80030b6:	f7fd f8b3 	bl	8000220 <__aeabi_uldivmod>
+ 80030ba:	0002      	movs	r2, r0
+ 80030bc:	000b      	movs	r3, r1
+ 80030be:	0013      	movs	r3, r2
+ 80030c0:	637b      	str	r3, [r7, #52]	; 0x34
+ 80030c2:	e037      	b.n	8003134 <HAL_RCC_GetSysClockFreq+0x10c>
+      }
+      else
+      {
+        if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
+ 80030c4:	4b26      	ldr	r3, [pc, #152]	; (8003160 <HAL_RCC_GetSysClockFreq+0x138>)
+ 80030c6:	681b      	ldr	r3, [r3, #0]
+ 80030c8:	2210      	movs	r2, #16
+ 80030ca:	4013      	ands	r3, r2
+ 80030cc:	d01a      	beq.n	8003104 <HAL_RCC_GetSysClockFreq+0xdc>
+        {
+          pllvco = (uint32_t)((((uint64_t)(HSI_VALUE >> 2)) * (uint64_t)pllm) / (uint64_t)plld);
+ 80030ce:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80030d0:	60bb      	str	r3, [r7, #8]
+ 80030d2:	2300      	movs	r3, #0
+ 80030d4:	60fb      	str	r3, [r7, #12]
+ 80030d6:	4a23      	ldr	r2, [pc, #140]	; (8003164 <HAL_RCC_GetSysClockFreq+0x13c>)
+ 80030d8:	2300      	movs	r3, #0
+ 80030da:	68b8      	ldr	r0, [r7, #8]
+ 80030dc:	68f9      	ldr	r1, [r7, #12]
+ 80030de:	f7fd f8bf 	bl	8000260 <__aeabi_lmul>
+ 80030e2:	0002      	movs	r2, r0
+ 80030e4:	000b      	movs	r3, r1
+ 80030e6:	0010      	movs	r0, r2
+ 80030e8:	0019      	movs	r1, r3
+ 80030ea:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80030ec:	603b      	str	r3, [r7, #0]
+ 80030ee:	2300      	movs	r3, #0
+ 80030f0:	607b      	str	r3, [r7, #4]
+ 80030f2:	683a      	ldr	r2, [r7, #0]
+ 80030f4:	687b      	ldr	r3, [r7, #4]
+ 80030f6:	f7fd f893 	bl	8000220 <__aeabi_uldivmod>
+ 80030fa:	0002      	movs	r2, r0
+ 80030fc:	000b      	movs	r3, r1
+ 80030fe:	0013      	movs	r3, r2
+ 8003100:	637b      	str	r3, [r7, #52]	; 0x34
+ 8003102:	e017      	b.n	8003134 <HAL_RCC_GetSysClockFreq+0x10c>
+        }
+        else
+        {
+         pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
+ 8003104:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8003106:	0018      	movs	r0, r3
+ 8003108:	2300      	movs	r3, #0
+ 800310a:	0019      	movs	r1, r3
+ 800310c:	4a16      	ldr	r2, [pc, #88]	; (8003168 <HAL_RCC_GetSysClockFreq+0x140>)
+ 800310e:	2300      	movs	r3, #0
+ 8003110:	f7fd f8a6 	bl	8000260 <__aeabi_lmul>
+ 8003114:	0002      	movs	r2, r0
+ 8003116:	000b      	movs	r3, r1
+ 8003118:	0010      	movs	r0, r2
+ 800311a:	0019      	movs	r1, r3
+ 800311c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800311e:	001c      	movs	r4, r3
+ 8003120:	2300      	movs	r3, #0
+ 8003122:	001d      	movs	r5, r3
+ 8003124:	0022      	movs	r2, r4
+ 8003126:	002b      	movs	r3, r5
+ 8003128:	f7fd f87a 	bl	8000220 <__aeabi_uldivmod>
+ 800312c:	0002      	movs	r2, r0
+ 800312e:	000b      	movs	r3, r1
+ 8003130:	0013      	movs	r3, r2
+ 8003132:	637b      	str	r3, [r7, #52]	; 0x34
+        }
+      }
+      sysclockfreq = pllvco;
+ 8003134:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8003136:	633b      	str	r3, [r7, #48]	; 0x30
+      break;
+ 8003138:	e00d      	b.n	8003156 <HAL_RCC_GetSysClockFreq+0x12e>
+    }
+    case RCC_SYSCLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
+    default: /* MSI used as system clock */
+    {
+      msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
+ 800313a:	4b09      	ldr	r3, [pc, #36]	; (8003160 <HAL_RCC_GetSysClockFreq+0x138>)
+ 800313c:	685b      	ldr	r3, [r3, #4]
+ 800313e:	0b5b      	lsrs	r3, r3, #13
+ 8003140:	2207      	movs	r2, #7
+ 8003142:	4013      	ands	r3, r2
+ 8003144:	623b      	str	r3, [r7, #32]
+      sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
+ 8003146:	6a3b      	ldr	r3, [r7, #32]
+ 8003148:	3301      	adds	r3, #1
+ 800314a:	2280      	movs	r2, #128	; 0x80
+ 800314c:	0212      	lsls	r2, r2, #8
+ 800314e:	409a      	lsls	r2, r3
+ 8003150:	0013      	movs	r3, r2
+ 8003152:	633b      	str	r3, [r7, #48]	; 0x30
+      break;
+ 8003154:	46c0      	nop			; (mov r8, r8)
+    }
+  }
+  return sysclockfreq;
+ 8003156:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+}
+ 8003158:	0018      	movs	r0, r3
+ 800315a:	46bd      	mov	sp, r7
+ 800315c:	b00e      	add	sp, #56	; 0x38
+ 800315e:	bdb0      	pop	{r4, r5, r7, pc}
+ 8003160:	40021000 	.word	0x40021000
+ 8003164:	003d0900 	.word	0x003d0900
+ 8003168:	00f42400 	.word	0x00f42400
+ 800316c:	007a1200 	.word	0x007a1200
+ 8003170:	0800789c 	.word	0x0800789c
+
+08003174 <HAL_RCC_GetHCLKFreq>:
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ 8003174:	b580      	push	{r7, lr}
+ 8003176:	af00      	add	r7, sp, #0
+  return SystemCoreClock;
+ 8003178:	4b02      	ldr	r3, [pc, #8]	; (8003184 <HAL_RCC_GetHCLKFreq+0x10>)
+ 800317a:	681b      	ldr	r3, [r3, #0]
+}
+ 800317c:	0018      	movs	r0, r3
+ 800317e:	46bd      	mov	sp, r7
+ 8003180:	bd80      	pop	{r7, pc}
+ 8003182:	46c0      	nop			; (mov r8, r8)
+ 8003184:	20000000 	.word	0x20000000
+
+08003188 <HAL_RCC_GetPCLK1Freq>:
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ 8003188:	b580      	push	{r7, lr}
+ 800318a:	af00      	add	r7, sp, #0
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
+ 800318c:	f7ff fff2 	bl	8003174 <HAL_RCC_GetHCLKFreq>
+ 8003190:	0001      	movs	r1, r0
+ 8003192:	4b06      	ldr	r3, [pc, #24]	; (80031ac <HAL_RCC_GetPCLK1Freq+0x24>)
+ 8003194:	68db      	ldr	r3, [r3, #12]
+ 8003196:	0a1b      	lsrs	r3, r3, #8
+ 8003198:	2207      	movs	r2, #7
+ 800319a:	4013      	ands	r3, r2
+ 800319c:	4a04      	ldr	r2, [pc, #16]	; (80031b0 <HAL_RCC_GetPCLK1Freq+0x28>)
+ 800319e:	5cd3      	ldrb	r3, [r2, r3]
+ 80031a0:	40d9      	lsrs	r1, r3
+ 80031a2:	000b      	movs	r3, r1
+}
+ 80031a4:	0018      	movs	r0, r3
+ 80031a6:	46bd      	mov	sp, r7
+ 80031a8:	bd80      	pop	{r7, pc}
+ 80031aa:	46c0      	nop			; (mov r8, r8)
+ 80031ac:	40021000 	.word	0x40021000
+ 80031b0:	08007894 	.word	0x08007894
+
+080031b4 <HAL_RCC_GetPCLK2Freq>:
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK2 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ 80031b4:	b580      	push	{r7, lr}
+ 80031b6:	af00      	add	r7, sp, #0
+  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
+ 80031b8:	f7ff ffdc 	bl	8003174 <HAL_RCC_GetHCLKFreq>
+ 80031bc:	0001      	movs	r1, r0
+ 80031be:	4b06      	ldr	r3, [pc, #24]	; (80031d8 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 80031c0:	68db      	ldr	r3, [r3, #12]
+ 80031c2:	0adb      	lsrs	r3, r3, #11
+ 80031c4:	2207      	movs	r2, #7
+ 80031c6:	4013      	ands	r3, r2
+ 80031c8:	4a04      	ldr	r2, [pc, #16]	; (80031dc <HAL_RCC_GetPCLK2Freq+0x28>)
+ 80031ca:	5cd3      	ldrb	r3, [r2, r3]
+ 80031cc:	40d9      	lsrs	r1, r3
+ 80031ce:	000b      	movs	r3, r1
+}
+ 80031d0:	0018      	movs	r0, r3
+ 80031d2:	46bd      	mov	sp, r7
+ 80031d4:	bd80      	pop	{r7, pc}
+ 80031d6:	46c0      	nop			; (mov r8, r8)
+ 80031d8:	40021000 	.word	0x40021000
+ 80031dc:	08007894 	.word	0x08007894
+
+080031e0 <HAL_RCCEx_PeriphCLKConfig>:
+  * @retval HAL status
+  * @note   If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
+  *         to possibly update HSE divider.
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+ 80031e0:	b580      	push	{r7, lr}
+ 80031e2:	b086      	sub	sp, #24
+ 80031e4:	af00      	add	r7, sp, #0
+ 80031e6:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+  uint32_t temp_reg;
+  FlagStatus       pwrclkchanged = RESET;
+ 80031e8:	2017      	movs	r0, #23
+ 80031ea:	183b      	adds	r3, r7, r0
+ 80031ec:	2200      	movs	r2, #0
+ 80031ee:	701a      	strb	r2, [r3, #0]
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*------------------------------- RTC/LCD Configuration ------------------------*/
+  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+ 80031f0:	687b      	ldr	r3, [r7, #4]
+ 80031f2:	681b      	ldr	r3, [r3, #0]
+ 80031f4:	2220      	movs	r2, #32
+ 80031f6:	4013      	ands	r3, r2
+ 80031f8:	d100      	bne.n	80031fc <HAL_RCCEx_PeriphCLKConfig+0x1c>
+ 80031fa:	e0c2      	b.n	8003382 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
+#endif /* LCD */
+
+    /* As soon as function is called to change RTC clock source, activation of the
+       power domain is done. */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 80031fc:	4b81      	ldr	r3, [pc, #516]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80031fe:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8003200:	2380      	movs	r3, #128	; 0x80
+ 8003202:	055b      	lsls	r3, r3, #21
+ 8003204:	4013      	ands	r3, r2
+ 8003206:	d109      	bne.n	800321c <HAL_RCCEx_PeriphCLKConfig+0x3c>
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+ 8003208:	4b7e      	ldr	r3, [pc, #504]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800320a:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 800320c:	4b7d      	ldr	r3, [pc, #500]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800320e:	2180      	movs	r1, #128	; 0x80
+ 8003210:	0549      	lsls	r1, r1, #21
+ 8003212:	430a      	orrs	r2, r1
+ 8003214:	639a      	str	r2, [r3, #56]	; 0x38
+      pwrclkchanged = SET;
+ 8003216:	183b      	adds	r3, r7, r0
+ 8003218:	2201      	movs	r2, #1
+ 800321a:	701a      	strb	r2, [r3, #0]
+    }
+
+    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 800321c:	4b7a      	ldr	r3, [pc, #488]	; (8003408 <HAL_RCCEx_PeriphCLKConfig+0x228>)
+ 800321e:	681a      	ldr	r2, [r3, #0]
+ 8003220:	2380      	movs	r3, #128	; 0x80
+ 8003222:	005b      	lsls	r3, r3, #1
+ 8003224:	4013      	ands	r3, r2
+ 8003226:	d11a      	bne.n	800325e <HAL_RCCEx_PeriphCLKConfig+0x7e>
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+ 8003228:	4b77      	ldr	r3, [pc, #476]	; (8003408 <HAL_RCCEx_PeriphCLKConfig+0x228>)
+ 800322a:	681a      	ldr	r2, [r3, #0]
+ 800322c:	4b76      	ldr	r3, [pc, #472]	; (8003408 <HAL_RCCEx_PeriphCLKConfig+0x228>)
+ 800322e:	2180      	movs	r1, #128	; 0x80
+ 8003230:	0049      	lsls	r1, r1, #1
+ 8003232:	430a      	orrs	r2, r1
+ 8003234:	601a      	str	r2, [r3, #0]
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+ 8003236:	f7fe faaf 	bl	8001798 <HAL_GetTick>
+ 800323a:	0003      	movs	r3, r0
+ 800323c:	613b      	str	r3, [r7, #16]
+
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 800323e:	e008      	b.n	8003252 <HAL_RCCEx_PeriphCLKConfig+0x72>
+      {
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 8003240:	f7fe faaa 	bl	8001798 <HAL_GetTick>
+ 8003244:	0002      	movs	r2, r0
+ 8003246:	693b      	ldr	r3, [r7, #16]
+ 8003248:	1ad3      	subs	r3, r2, r3
+ 800324a:	2b64      	cmp	r3, #100	; 0x64
+ 800324c:	d901      	bls.n	8003252 <HAL_RCCEx_PeriphCLKConfig+0x72>
+        {
+          return HAL_TIMEOUT;
+ 800324e:	2303      	movs	r3, #3
+ 8003250:	e0d4      	b.n	80033fc <HAL_RCCEx_PeriphCLKConfig+0x21c>
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 8003252:	4b6d      	ldr	r3, [pc, #436]	; (8003408 <HAL_RCCEx_PeriphCLKConfig+0x228>)
+ 8003254:	681a      	ldr	r2, [r3, #0]
+ 8003256:	2380      	movs	r3, #128	; 0x80
+ 8003258:	005b      	lsls	r3, r3, #1
+ 800325a:	4013      	ands	r3, r2
+ 800325c:	d0f0      	beq.n	8003240 <HAL_RCCEx_PeriphCLKConfig+0x60>
+        }
+      }
+    }
+
+    /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
+    temp_reg = (RCC->CR & RCC_CR_RTCPRE);
+ 800325e:	4b69      	ldr	r3, [pc, #420]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003260:	681a      	ldr	r2, [r3, #0]
+ 8003262:	23c0      	movs	r3, #192	; 0xc0
+ 8003264:	039b      	lsls	r3, r3, #14
+ 8003266:	4013      	ands	r3, r2
+ 8003268:	60fb      	str	r3, [r7, #12]
+    if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
+ 800326a:	687b      	ldr	r3, [r7, #4]
+ 800326c:	685a      	ldr	r2, [r3, #4]
+ 800326e:	23c0      	movs	r3, #192	; 0xc0
+ 8003270:	039b      	lsls	r3, r3, #14
+ 8003272:	4013      	ands	r3, r2
+ 8003274:	68fa      	ldr	r2, [r7, #12]
+ 8003276:	429a      	cmp	r2, r3
+ 8003278:	d013      	beq.n	80032a2 <HAL_RCCEx_PeriphCLKConfig+0xc2>
+#if defined (LCD)
+     || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
+#endif /* LCD */
+       )
+    { /* Check HSE State */
+      if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
+ 800327a:	687b      	ldr	r3, [r7, #4]
+ 800327c:	685a      	ldr	r2, [r3, #4]
+ 800327e:	23c0      	movs	r3, #192	; 0xc0
+ 8003280:	029b      	lsls	r3, r3, #10
+ 8003282:	401a      	ands	r2, r3
+ 8003284:	23c0      	movs	r3, #192	; 0xc0
+ 8003286:	029b      	lsls	r3, r3, #10
+ 8003288:	429a      	cmp	r2, r3
+ 800328a:	d10a      	bne.n	80032a2 <HAL_RCCEx_PeriphCLKConfig+0xc2>
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ 800328c:	4b5d      	ldr	r3, [pc, #372]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800328e:	681a      	ldr	r2, [r3, #0]
+ 8003290:	2380      	movs	r3, #128	; 0x80
+ 8003292:	029b      	lsls	r3, r3, #10
+ 8003294:	401a      	ands	r2, r3
+ 8003296:	2380      	movs	r3, #128	; 0x80
+ 8003298:	029b      	lsls	r3, r3, #10
+ 800329a:	429a      	cmp	r2, r3
+ 800329c:	d101      	bne.n	80032a2 <HAL_RCCEx_PeriphCLKConfig+0xc2>
+        {
+          /* To update HSE divider, first switch-OFF HSE clock oscillator*/
+          return HAL_ERROR;
+ 800329e:	2301      	movs	r3, #1
+ 80032a0:	e0ac      	b.n	80033fc <HAL_RCCEx_PeriphCLKConfig+0x21c>
+        }
+      }
+    }
+
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
+ 80032a2:	4b58      	ldr	r3, [pc, #352]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80032a4:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 80032a6:	23c0      	movs	r3, #192	; 0xc0
+ 80032a8:	029b      	lsls	r3, r3, #10
+ 80032aa:	4013      	ands	r3, r2
+ 80032ac:	60fb      	str	r3, [r7, #12]
+
+    if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
+ 80032ae:	68fb      	ldr	r3, [r7, #12]
+ 80032b0:	2b00      	cmp	r3, #0
+ 80032b2:	d03b      	beq.n	800332c <HAL_RCCEx_PeriphCLKConfig+0x14c>
+ 80032b4:	687b      	ldr	r3, [r7, #4]
+ 80032b6:	685a      	ldr	r2, [r3, #4]
+ 80032b8:	23c0      	movs	r3, #192	; 0xc0
+ 80032ba:	029b      	lsls	r3, r3, #10
+ 80032bc:	4013      	ands	r3, r2
+ 80032be:	68fa      	ldr	r2, [r7, #12]
+ 80032c0:	429a      	cmp	r2, r3
+ 80032c2:	d033      	beq.n	800332c <HAL_RCCEx_PeriphCLKConfig+0x14c>
+      && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+ 80032c4:	687b      	ldr	r3, [r7, #4]
+ 80032c6:	681b      	ldr	r3, [r3, #0]
+ 80032c8:	2220      	movs	r2, #32
+ 80032ca:	4013      	ands	r3, r2
+ 80032cc:	d02e      	beq.n	800332c <HAL_RCCEx_PeriphCLKConfig+0x14c>
+       && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
+#endif /* LCD */
+     ))
+    {
+      /* Store the content of CSR register before the reset of Backup Domain */
+      temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
+ 80032ce:	4b4d      	ldr	r3, [pc, #308]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80032d0:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80032d2:	4a4e      	ldr	r2, [pc, #312]	; (800340c <HAL_RCCEx_PeriphCLKConfig+0x22c>)
+ 80032d4:	4013      	ands	r3, r2
+ 80032d6:	60fb      	str	r3, [r7, #12]
+
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+ 80032d8:	4b4a      	ldr	r3, [pc, #296]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80032da:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 80032dc:	4b49      	ldr	r3, [pc, #292]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80032de:	2180      	movs	r1, #128	; 0x80
+ 80032e0:	0309      	lsls	r1, r1, #12
+ 80032e2:	430a      	orrs	r2, r1
+ 80032e4:	651a      	str	r2, [r3, #80]	; 0x50
+      __HAL_RCC_BACKUPRESET_RELEASE();
+ 80032e6:	4b47      	ldr	r3, [pc, #284]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80032e8:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 80032ea:	4b46      	ldr	r3, [pc, #280]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80032ec:	4948      	ldr	r1, [pc, #288]	; (8003410 <HAL_RCCEx_PeriphCLKConfig+0x230>)
+ 80032ee:	400a      	ands	r2, r1
+ 80032f0:	651a      	str	r2, [r3, #80]	; 0x50
+
+      /* Restore the Content of CSR register */
+      RCC->CSR = temp_reg;
+ 80032f2:	4b44      	ldr	r3, [pc, #272]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80032f4:	68fa      	ldr	r2, [r7, #12]
+ 80032f6:	651a      	str	r2, [r3, #80]	; 0x50
+
+       /* Wait for LSERDY if LSE was enabled */
+      if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
+ 80032f8:	68fa      	ldr	r2, [r7, #12]
+ 80032fa:	2380      	movs	r3, #128	; 0x80
+ 80032fc:	005b      	lsls	r3, r3, #1
+ 80032fe:	4013      	ands	r3, r2
+ 8003300:	d014      	beq.n	800332c <HAL_RCCEx_PeriphCLKConfig+0x14c>
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8003302:	f7fe fa49 	bl	8001798 <HAL_GetTick>
+ 8003306:	0003      	movs	r3, r0
+ 8003308:	613b      	str	r3, [r7, #16]
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 800330a:	e009      	b.n	8003320 <HAL_RCCEx_PeriphCLKConfig+0x140>
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 800330c:	f7fe fa44 	bl	8001798 <HAL_GetTick>
+ 8003310:	0002      	movs	r2, r0
+ 8003312:	693b      	ldr	r3, [r7, #16]
+ 8003314:	1ad3      	subs	r3, r2, r3
+ 8003316:	4a3f      	ldr	r2, [pc, #252]	; (8003414 <HAL_RCCEx_PeriphCLKConfig+0x234>)
+ 8003318:	4293      	cmp	r3, r2
+ 800331a:	d901      	bls.n	8003320 <HAL_RCCEx_PeriphCLKConfig+0x140>
+          {
+            return HAL_TIMEOUT;
+ 800331c:	2303      	movs	r3, #3
+ 800331e:	e06d      	b.n	80033fc <HAL_RCCEx_PeriphCLKConfig+0x21c>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 8003320:	4b38      	ldr	r3, [pc, #224]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003322:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 8003324:	2380      	movs	r3, #128	; 0x80
+ 8003326:	009b      	lsls	r3, r3, #2
+ 8003328:	4013      	ands	r3, r2
+ 800332a:	d0ef      	beq.n	800330c <HAL_RCCEx_PeriphCLKConfig+0x12c>
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ 800332c:	687b      	ldr	r3, [r7, #4]
+ 800332e:	685a      	ldr	r2, [r3, #4]
+ 8003330:	23c0      	movs	r3, #192	; 0xc0
+ 8003332:	029b      	lsls	r3, r3, #10
+ 8003334:	401a      	ands	r2, r3
+ 8003336:	23c0      	movs	r3, #192	; 0xc0
+ 8003338:	029b      	lsls	r3, r3, #10
+ 800333a:	429a      	cmp	r2, r3
+ 800333c:	d10c      	bne.n	8003358 <HAL_RCCEx_PeriphCLKConfig+0x178>
+ 800333e:	4b31      	ldr	r3, [pc, #196]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003340:	681b      	ldr	r3, [r3, #0]
+ 8003342:	4a35      	ldr	r2, [pc, #212]	; (8003418 <HAL_RCCEx_PeriphCLKConfig+0x238>)
+ 8003344:	4013      	ands	r3, r2
+ 8003346:	0019      	movs	r1, r3
+ 8003348:	687b      	ldr	r3, [r7, #4]
+ 800334a:	685a      	ldr	r2, [r3, #4]
+ 800334c:	23c0      	movs	r3, #192	; 0xc0
+ 800334e:	039b      	lsls	r3, r3, #14
+ 8003350:	401a      	ands	r2, r3
+ 8003352:	4b2c      	ldr	r3, [pc, #176]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003354:	430a      	orrs	r2, r1
+ 8003356:	601a      	str	r2, [r3, #0]
+ 8003358:	4b2a      	ldr	r3, [pc, #168]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800335a:	6d19      	ldr	r1, [r3, #80]	; 0x50
+ 800335c:	687b      	ldr	r3, [r7, #4]
+ 800335e:	685a      	ldr	r2, [r3, #4]
+ 8003360:	23c0      	movs	r3, #192	; 0xc0
+ 8003362:	029b      	lsls	r3, r3, #10
+ 8003364:	401a      	ands	r2, r3
+ 8003366:	4b27      	ldr	r3, [pc, #156]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003368:	430a      	orrs	r2, r1
+ 800336a:	651a      	str	r2, [r3, #80]	; 0x50
+
+    /* Require to disable power clock if necessary */
+    if(pwrclkchanged == SET)
+ 800336c:	2317      	movs	r3, #23
+ 800336e:	18fb      	adds	r3, r7, r3
+ 8003370:	781b      	ldrb	r3, [r3, #0]
+ 8003372:	2b01      	cmp	r3, #1
+ 8003374:	d105      	bne.n	8003382 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+ 8003376:	4b23      	ldr	r3, [pc, #140]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003378:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 800337a:	4b22      	ldr	r3, [pc, #136]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800337c:	4927      	ldr	r1, [pc, #156]	; (800341c <HAL_RCCEx_PeriphCLKConfig+0x23c>)
+ 800337e:	400a      	ands	r2, r1
+ 8003380:	639a      	str	r2, [r3, #56]	; 0x38
+    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+  }
+#endif /* RCC_CCIPR_USART1SEL */
+
+  /*----------------------------- USART2 Configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ 8003382:	687b      	ldr	r3, [r7, #4]
+ 8003384:	681b      	ldr	r3, [r3, #0]
+ 8003386:	2202      	movs	r2, #2
+ 8003388:	4013      	ands	r3, r2
+ 800338a:	d009      	beq.n	80033a0 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+    /* Configure the USART2 clock source */
+    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ 800338c:	4b1d      	ldr	r3, [pc, #116]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800338e:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8003390:	220c      	movs	r2, #12
+ 8003392:	4393      	bics	r3, r2
+ 8003394:	0019      	movs	r1, r3
+ 8003396:	687b      	ldr	r3, [r7, #4]
+ 8003398:	689a      	ldr	r2, [r3, #8]
+ 800339a:	4b1a      	ldr	r3, [pc, #104]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800339c:	430a      	orrs	r2, r1
+ 800339e:	64da      	str	r2, [r3, #76]	; 0x4c
+  }
+
+  /*------------------------------ LPUART1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+ 80033a0:	687b      	ldr	r3, [r7, #4]
+ 80033a2:	681b      	ldr	r3, [r3, #0]
+ 80033a4:	2204      	movs	r2, #4
+ 80033a6:	4013      	ands	r3, r2
+ 80033a8:	d009      	beq.n	80033be <HAL_RCCEx_PeriphCLKConfig+0x1de>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
+
+    /* Configure the LPUAR1 clock source */
+    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+ 80033aa:	4b16      	ldr	r3, [pc, #88]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80033ac:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 80033ae:	4a1c      	ldr	r2, [pc, #112]	; (8003420 <HAL_RCCEx_PeriphCLKConfig+0x240>)
+ 80033b0:	4013      	ands	r3, r2
+ 80033b2:	0019      	movs	r1, r3
+ 80033b4:	687b      	ldr	r3, [r7, #4]
+ 80033b6:	68da      	ldr	r2, [r3, #12]
+ 80033b8:	4b12      	ldr	r3, [pc, #72]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80033ba:	430a      	orrs	r2, r1
+ 80033bc:	64da      	str	r2, [r3, #76]	; 0x4c
+  }
+
+  /*------------------------------ I2C1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ 80033be:	687b      	ldr	r3, [r7, #4]
+ 80033c0:	681b      	ldr	r3, [r3, #0]
+ 80033c2:	2208      	movs	r2, #8
+ 80033c4:	4013      	ands	r3, r2
+ 80033c6:	d009      	beq.n	80033dc <HAL_RCCEx_PeriphCLKConfig+0x1fc>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+    /* Configure the I2C1 clock source */
+    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ 80033c8:	4b0e      	ldr	r3, [pc, #56]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80033ca:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 80033cc:	4a15      	ldr	r2, [pc, #84]	; (8003424 <HAL_RCCEx_PeriphCLKConfig+0x244>)
+ 80033ce:	4013      	ands	r3, r2
+ 80033d0:	0019      	movs	r1, r3
+ 80033d2:	687b      	ldr	r3, [r7, #4]
+ 80033d4:	691a      	ldr	r2, [r3, #16]
+ 80033d6:	4b0b      	ldr	r3, [pc, #44]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80033d8:	430a      	orrs	r2, r1
+ 80033da:	64da      	str	r2, [r3, #76]	; 0x4c
+    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+  }
+#endif /* USB */
+
+  /*---------------------------- LPTIM1 configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
+ 80033dc:	687b      	ldr	r3, [r7, #4]
+ 80033de:	681b      	ldr	r3, [r3, #0]
+ 80033e0:	2280      	movs	r2, #128	; 0x80
+ 80033e2:	4013      	ands	r3, r2
+ 80033e4:	d009      	beq.n	80033fa <HAL_RCCEx_PeriphCLKConfig+0x21a>
+  {
+    assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
+ 80033e6:	4b07      	ldr	r3, [pc, #28]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80033e8:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 80033ea:	4a0f      	ldr	r2, [pc, #60]	; (8003428 <HAL_RCCEx_PeriphCLKConfig+0x248>)
+ 80033ec:	4013      	ands	r3, r2
+ 80033ee:	0019      	movs	r1, r3
+ 80033f0:	687b      	ldr	r3, [r7, #4]
+ 80033f2:	695a      	ldr	r2, [r3, #20]
+ 80033f4:	4b03      	ldr	r3, [pc, #12]	; (8003404 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80033f6:	430a      	orrs	r2, r1
+ 80033f8:	64da      	str	r2, [r3, #76]	; 0x4c
+  }
+
+  return HAL_OK;
+ 80033fa:	2300      	movs	r3, #0
+}
+ 80033fc:	0018      	movs	r0, r3
+ 80033fe:	46bd      	mov	sp, r7
+ 8003400:	b006      	add	sp, #24
+ 8003402:	bd80      	pop	{r7, pc}
+ 8003404:	40021000 	.word	0x40021000
+ 8003408:	40007000 	.word	0x40007000
+ 800340c:	fffcffff 	.word	0xfffcffff
+ 8003410:	fff7ffff 	.word	0xfff7ffff
+ 8003414:	00001388 	.word	0x00001388
+ 8003418:	ffcfffff 	.word	0xffcfffff
+ 800341c:	efffffff 	.word	0xefffffff
+ 8003420:	fffff3ff 	.word	0xfffff3ff
+ 8003424:	ffffcfff 	.word	0xffffcfff
+ 8003428:	fff3ffff 	.word	0xfff3ffff
+
+0800342c <HAL_TIM_Base_Init>:
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ 800342c:	b580      	push	{r7, lr}
+ 800342e:	b082      	sub	sp, #8
+ 8003430:	af00      	add	r7, sp, #0
+ 8003432:	6078      	str	r0, [r7, #4]
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+ 8003434:	687b      	ldr	r3, [r7, #4]
+ 8003436:	2b00      	cmp	r3, #0
+ 8003438:	d101      	bne.n	800343e <HAL_TIM_Base_Init+0x12>
+  {
+    return HAL_ERROR;
+ 800343a:	2301      	movs	r3, #1
+ 800343c:	e032      	b.n	80034a4 <HAL_TIM_Base_Init+0x78>
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 800343e:	687b      	ldr	r3, [r7, #4]
+ 8003440:	2239      	movs	r2, #57	; 0x39
+ 8003442:	5c9b      	ldrb	r3, [r3, r2]
+ 8003444:	b2db      	uxtb	r3, r3
+ 8003446:	2b00      	cmp	r3, #0
+ 8003448:	d107      	bne.n	800345a <HAL_TIM_Base_Init+0x2e>
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+ 800344a:	687b      	ldr	r3, [r7, #4]
+ 800344c:	2238      	movs	r2, #56	; 0x38
+ 800344e:	2100      	movs	r1, #0
+ 8003450:	5499      	strb	r1, [r3, r2]
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+ 8003452:	687b      	ldr	r3, [r7, #4]
+ 8003454:	0018      	movs	r0, r3
+ 8003456:	f7fd ffdd 	bl	8001414 <HAL_TIM_Base_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800345a:	687b      	ldr	r3, [r7, #4]
+ 800345c:	2239      	movs	r2, #57	; 0x39
+ 800345e:	2102      	movs	r1, #2
+ 8003460:	5499      	strb	r1, [r3, r2]
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8003462:	687b      	ldr	r3, [r7, #4]
+ 8003464:	681a      	ldr	r2, [r3, #0]
+ 8003466:	687b      	ldr	r3, [r7, #4]
+ 8003468:	3304      	adds	r3, #4
+ 800346a:	0019      	movs	r1, r3
+ 800346c:	0010      	movs	r0, r2
+ 800346e:	f000 fa9f 	bl	80039b0 <TIM_Base_SetConfig>
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8003472:	687b      	ldr	r3, [r7, #4]
+ 8003474:	223e      	movs	r2, #62	; 0x3e
+ 8003476:	2101      	movs	r1, #1
+ 8003478:	5499      	strb	r1, [r3, r2]
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 800347a:	687b      	ldr	r3, [r7, #4]
+ 800347c:	223a      	movs	r2, #58	; 0x3a
+ 800347e:	2101      	movs	r1, #1
+ 8003480:	5499      	strb	r1, [r3, r2]
+ 8003482:	687b      	ldr	r3, [r7, #4]
+ 8003484:	223b      	movs	r2, #59	; 0x3b
+ 8003486:	2101      	movs	r1, #1
+ 8003488:	5499      	strb	r1, [r3, r2]
+ 800348a:	687b      	ldr	r3, [r7, #4]
+ 800348c:	223c      	movs	r2, #60	; 0x3c
+ 800348e:	2101      	movs	r1, #1
+ 8003490:	5499      	strb	r1, [r3, r2]
+ 8003492:	687b      	ldr	r3, [r7, #4]
+ 8003494:	223d      	movs	r2, #61	; 0x3d
+ 8003496:	2101      	movs	r1, #1
+ 8003498:	5499      	strb	r1, [r3, r2]
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+ 800349a:	687b      	ldr	r3, [r7, #4]
+ 800349c:	2239      	movs	r2, #57	; 0x39
+ 800349e:	2101      	movs	r1, #1
+ 80034a0:	5499      	strb	r1, [r3, r2]
+
+  return HAL_OK;
+ 80034a2:	2300      	movs	r3, #0
+}
+ 80034a4:	0018      	movs	r0, r3
+ 80034a6:	46bd      	mov	sp, r7
+ 80034a8:	b002      	add	sp, #8
+ 80034aa:	bd80      	pop	{r7, pc}
+
+080034ac <HAL_TIM_PWM_Init>:
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ 80034ac:	b580      	push	{r7, lr}
+ 80034ae:	b082      	sub	sp, #8
+ 80034b0:	af00      	add	r7, sp, #0
+ 80034b2:	6078      	str	r0, [r7, #4]
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+ 80034b4:	687b      	ldr	r3, [r7, #4]
+ 80034b6:	2b00      	cmp	r3, #0
+ 80034b8:	d101      	bne.n	80034be <HAL_TIM_PWM_Init+0x12>
+  {
+    return HAL_ERROR;
+ 80034ba:	2301      	movs	r3, #1
+ 80034bc:	e032      	b.n	8003524 <HAL_TIM_PWM_Init+0x78>
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 80034be:	687b      	ldr	r3, [r7, #4]
+ 80034c0:	2239      	movs	r2, #57	; 0x39
+ 80034c2:	5c9b      	ldrb	r3, [r3, r2]
+ 80034c4:	b2db      	uxtb	r3, r3
+ 80034c6:	2b00      	cmp	r3, #0
+ 80034c8:	d107      	bne.n	80034da <HAL_TIM_PWM_Init+0x2e>
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+ 80034ca:	687b      	ldr	r3, [r7, #4]
+ 80034cc:	2238      	movs	r2, #56	; 0x38
+ 80034ce:	2100      	movs	r1, #0
+ 80034d0:	5499      	strb	r1, [r3, r2]
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+ 80034d2:	687b      	ldr	r3, [r7, #4]
+ 80034d4:	0018      	movs	r0, r3
+ 80034d6:	f000 f829 	bl	800352c <HAL_TIM_PWM_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 80034da:	687b      	ldr	r3, [r7, #4]
+ 80034dc:	2239      	movs	r2, #57	; 0x39
+ 80034de:	2102      	movs	r1, #2
+ 80034e0:	5499      	strb	r1, [r3, r2]
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 80034e2:	687b      	ldr	r3, [r7, #4]
+ 80034e4:	681a      	ldr	r2, [r3, #0]
+ 80034e6:	687b      	ldr	r3, [r7, #4]
+ 80034e8:	3304      	adds	r3, #4
+ 80034ea:	0019      	movs	r1, r3
+ 80034ec:	0010      	movs	r0, r2
+ 80034ee:	f000 fa5f 	bl	80039b0 <TIM_Base_SetConfig>
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 80034f2:	687b      	ldr	r3, [r7, #4]
+ 80034f4:	223e      	movs	r2, #62	; 0x3e
+ 80034f6:	2101      	movs	r1, #1
+ 80034f8:	5499      	strb	r1, [r3, r2]
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 80034fa:	687b      	ldr	r3, [r7, #4]
+ 80034fc:	223a      	movs	r2, #58	; 0x3a
+ 80034fe:	2101      	movs	r1, #1
+ 8003500:	5499      	strb	r1, [r3, r2]
+ 8003502:	687b      	ldr	r3, [r7, #4]
+ 8003504:	223b      	movs	r2, #59	; 0x3b
+ 8003506:	2101      	movs	r1, #1
+ 8003508:	5499      	strb	r1, [r3, r2]
+ 800350a:	687b      	ldr	r3, [r7, #4]
+ 800350c:	223c      	movs	r2, #60	; 0x3c
+ 800350e:	2101      	movs	r1, #1
+ 8003510:	5499      	strb	r1, [r3, r2]
+ 8003512:	687b      	ldr	r3, [r7, #4]
+ 8003514:	223d      	movs	r2, #61	; 0x3d
+ 8003516:	2101      	movs	r1, #1
+ 8003518:	5499      	strb	r1, [r3, r2]
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+ 800351a:	687b      	ldr	r3, [r7, #4]
+ 800351c:	2239      	movs	r2, #57	; 0x39
+ 800351e:	2101      	movs	r1, #1
+ 8003520:	5499      	strb	r1, [r3, r2]
+
+  return HAL_OK;
+ 8003522:	2300      	movs	r3, #0
+}
+ 8003524:	0018      	movs	r0, r3
+ 8003526:	46bd      	mov	sp, r7
+ 8003528:	b002      	add	sp, #8
+ 800352a:	bd80      	pop	{r7, pc}
+
+0800352c <HAL_TIM_PWM_MspInit>:
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ 800352c:	b580      	push	{r7, lr}
+ 800352e:	b082      	sub	sp, #8
+ 8003530:	af00      	add	r7, sp, #0
+ 8003532:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+ 8003534:	46c0      	nop			; (mov r8, r8)
+ 8003536:	46bd      	mov	sp, r7
+ 8003538:	b002      	add	sp, #8
+ 800353a:	bd80      	pop	{r7, pc}
+
+0800353c <HAL_TIM_Encoder_Init>:
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+{
+ 800353c:	b580      	push	{r7, lr}
+ 800353e:	b086      	sub	sp, #24
+ 8003540:	af00      	add	r7, sp, #0
+ 8003542:	6078      	str	r0, [r7, #4]
+ 8003544:	6039      	str	r1, [r7, #0]
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+ 8003546:	687b      	ldr	r3, [r7, #4]
+ 8003548:	2b00      	cmp	r3, #0
+ 800354a:	d101      	bne.n	8003550 <HAL_TIM_Encoder_Init+0x14>
+  {
+    return HAL_ERROR;
+ 800354c:	2301      	movs	r3, #1
+ 800354e:	e088      	b.n	8003662 <HAL_TIM_Encoder_Init+0x126>
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 8003550:	687b      	ldr	r3, [r7, #4]
+ 8003552:	2239      	movs	r2, #57	; 0x39
+ 8003554:	5c9b      	ldrb	r3, [r3, r2]
+ 8003556:	b2db      	uxtb	r3, r3
+ 8003558:	2b00      	cmp	r3, #0
+ 800355a:	d107      	bne.n	800356c <HAL_TIM_Encoder_Init+0x30>
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+ 800355c:	687b      	ldr	r3, [r7, #4]
+ 800355e:	2238      	movs	r2, #56	; 0x38
+ 8003560:	2100      	movs	r1, #0
+ 8003562:	5499      	strb	r1, [r3, r2]
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+ 8003564:	687b      	ldr	r3, [r7, #4]
+ 8003566:	0018      	movs	r0, r3
+ 8003568:	f7fd ff6a 	bl	8001440 <HAL_TIM_Encoder_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800356c:	687b      	ldr	r3, [r7, #4]
+ 800356e:	2239      	movs	r2, #57	; 0x39
+ 8003570:	2102      	movs	r1, #2
+ 8003572:	5499      	strb	r1, [r3, r2]
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+ 8003574:	687b      	ldr	r3, [r7, #4]
+ 8003576:	681b      	ldr	r3, [r3, #0]
+ 8003578:	689a      	ldr	r2, [r3, #8]
+ 800357a:	687b      	ldr	r3, [r7, #4]
+ 800357c:	681b      	ldr	r3, [r3, #0]
+ 800357e:	493b      	ldr	r1, [pc, #236]	; (800366c <HAL_TIM_Encoder_Init+0x130>)
+ 8003580:	400a      	ands	r2, r1
+ 8003582:	609a      	str	r2, [r3, #8]
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8003584:	687b      	ldr	r3, [r7, #4]
+ 8003586:	681a      	ldr	r2, [r3, #0]
+ 8003588:	687b      	ldr	r3, [r7, #4]
+ 800358a:	3304      	adds	r3, #4
+ 800358c:	0019      	movs	r1, r3
+ 800358e:	0010      	movs	r0, r2
+ 8003590:	f000 fa0e 	bl	80039b0 <TIM_Base_SetConfig>
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+ 8003594:	687b      	ldr	r3, [r7, #4]
+ 8003596:	681b      	ldr	r3, [r3, #0]
+ 8003598:	689b      	ldr	r3, [r3, #8]
+ 800359a:	617b      	str	r3, [r7, #20]
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+ 800359c:	687b      	ldr	r3, [r7, #4]
+ 800359e:	681b      	ldr	r3, [r3, #0]
+ 80035a0:	699b      	ldr	r3, [r3, #24]
+ 80035a2:	613b      	str	r3, [r7, #16]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+ 80035a4:	687b      	ldr	r3, [r7, #4]
+ 80035a6:	681b      	ldr	r3, [r3, #0]
+ 80035a8:	6a1b      	ldr	r3, [r3, #32]
+ 80035aa:	60fb      	str	r3, [r7, #12]
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+ 80035ac:	683b      	ldr	r3, [r7, #0]
+ 80035ae:	681b      	ldr	r3, [r3, #0]
+ 80035b0:	697a      	ldr	r2, [r7, #20]
+ 80035b2:	4313      	orrs	r3, r2
+ 80035b4:	617b      	str	r3, [r7, #20]
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ 80035b6:	693b      	ldr	r3, [r7, #16]
+ 80035b8:	4a2d      	ldr	r2, [pc, #180]	; (8003670 <HAL_TIM_Encoder_Init+0x134>)
+ 80035ba:	4013      	ands	r3, r2
+ 80035bc:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+ 80035be:	683b      	ldr	r3, [r7, #0]
+ 80035c0:	689a      	ldr	r2, [r3, #8]
+ 80035c2:	683b      	ldr	r3, [r7, #0]
+ 80035c4:	699b      	ldr	r3, [r3, #24]
+ 80035c6:	021b      	lsls	r3, r3, #8
+ 80035c8:	4313      	orrs	r3, r2
+ 80035ca:	693a      	ldr	r2, [r7, #16]
+ 80035cc:	4313      	orrs	r3, r2
+ 80035ce:	613b      	str	r3, [r7, #16]
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ 80035d0:	693b      	ldr	r3, [r7, #16]
+ 80035d2:	4a28      	ldr	r2, [pc, #160]	; (8003674 <HAL_TIM_Encoder_Init+0x138>)
+ 80035d4:	4013      	ands	r3, r2
+ 80035d6:	613b      	str	r3, [r7, #16]
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ 80035d8:	693b      	ldr	r3, [r7, #16]
+ 80035da:	4a27      	ldr	r2, [pc, #156]	; (8003678 <HAL_TIM_Encoder_Init+0x13c>)
+ 80035dc:	4013      	ands	r3, r2
+ 80035de:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 80035e0:	683b      	ldr	r3, [r7, #0]
+ 80035e2:	68da      	ldr	r2, [r3, #12]
+ 80035e4:	683b      	ldr	r3, [r7, #0]
+ 80035e6:	69db      	ldr	r3, [r3, #28]
+ 80035e8:	021b      	lsls	r3, r3, #8
+ 80035ea:	4313      	orrs	r3, r2
+ 80035ec:	693a      	ldr	r2, [r7, #16]
+ 80035ee:	4313      	orrs	r3, r2
+ 80035f0:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 80035f2:	683b      	ldr	r3, [r7, #0]
+ 80035f4:	691b      	ldr	r3, [r3, #16]
+ 80035f6:	011a      	lsls	r2, r3, #4
+ 80035f8:	683b      	ldr	r3, [r7, #0]
+ 80035fa:	6a1b      	ldr	r3, [r3, #32]
+ 80035fc:	031b      	lsls	r3, r3, #12
+ 80035fe:	4313      	orrs	r3, r2
+ 8003600:	693a      	ldr	r2, [r7, #16]
+ 8003602:	4313      	orrs	r3, r2
+ 8003604:	613b      	str	r3, [r7, #16]
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ 8003606:	68fb      	ldr	r3, [r7, #12]
+ 8003608:	2222      	movs	r2, #34	; 0x22
+ 800360a:	4393      	bics	r3, r2
+ 800360c:	60fb      	str	r3, [r7, #12]
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ 800360e:	68fb      	ldr	r3, [r7, #12]
+ 8003610:	2288      	movs	r2, #136	; 0x88
+ 8003612:	4393      	bics	r3, r2
+ 8003614:	60fb      	str	r3, [r7, #12]
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+ 8003616:	683b      	ldr	r3, [r7, #0]
+ 8003618:	685a      	ldr	r2, [r3, #4]
+ 800361a:	683b      	ldr	r3, [r7, #0]
+ 800361c:	695b      	ldr	r3, [r3, #20]
+ 800361e:	011b      	lsls	r3, r3, #4
+ 8003620:	4313      	orrs	r3, r2
+ 8003622:	68fa      	ldr	r2, [r7, #12]
+ 8003624:	4313      	orrs	r3, r2
+ 8003626:	60fb      	str	r3, [r7, #12]
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+ 8003628:	687b      	ldr	r3, [r7, #4]
+ 800362a:	681b      	ldr	r3, [r3, #0]
+ 800362c:	697a      	ldr	r2, [r7, #20]
+ 800362e:	609a      	str	r2, [r3, #8]
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+ 8003630:	687b      	ldr	r3, [r7, #4]
+ 8003632:	681b      	ldr	r3, [r3, #0]
+ 8003634:	693a      	ldr	r2, [r7, #16]
+ 8003636:	619a      	str	r2, [r3, #24]
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+ 8003638:	687b      	ldr	r3, [r7, #4]
+ 800363a:	681b      	ldr	r3, [r3, #0]
+ 800363c:	68fa      	ldr	r2, [r7, #12]
+ 800363e:	621a      	str	r2, [r3, #32]
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8003640:	687b      	ldr	r3, [r7, #4]
+ 8003642:	223e      	movs	r2, #62	; 0x3e
+ 8003644:	2101      	movs	r1, #1
+ 8003646:	5499      	strb	r1, [r3, r2]
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 8003648:	687b      	ldr	r3, [r7, #4]
+ 800364a:	223a      	movs	r2, #58	; 0x3a
+ 800364c:	2101      	movs	r1, #1
+ 800364e:	5499      	strb	r1, [r3, r2]
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 8003650:	687b      	ldr	r3, [r7, #4]
+ 8003652:	223b      	movs	r2, #59	; 0x3b
+ 8003654:	2101      	movs	r1, #1
+ 8003656:	5499      	strb	r1, [r3, r2]
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+ 8003658:	687b      	ldr	r3, [r7, #4]
+ 800365a:	2239      	movs	r2, #57	; 0x39
+ 800365c:	2101      	movs	r1, #1
+ 800365e:	5499      	strb	r1, [r3, r2]
+
+  return HAL_OK;
+ 8003660:	2300      	movs	r3, #0
+}
+ 8003662:	0018      	movs	r0, r3
+ 8003664:	46bd      	mov	sp, r7
+ 8003666:	b006      	add	sp, #24
+ 8003668:	bd80      	pop	{r7, pc}
+ 800366a:	46c0      	nop			; (mov r8, r8)
+ 800366c:	ffffbff8 	.word	0xffffbff8
+ 8003670:	fffffcfc 	.word	0xfffffcfc
+ 8003674:	fffff3f3 	.word	0xfffff3f3
+ 8003678:	ffff0f0f 	.word	0xffff0f0f
+
+0800367c <HAL_TIM_PWM_ConfigChannel>:
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+ 800367c:	b580      	push	{r7, lr}
+ 800367e:	b086      	sub	sp, #24
+ 8003680:	af00      	add	r7, sp, #0
+ 8003682:	60f8      	str	r0, [r7, #12]
+ 8003684:	60b9      	str	r1, [r7, #8]
+ 8003686:	607a      	str	r2, [r7, #4]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8003688:	2317      	movs	r3, #23
+ 800368a:	18fb      	adds	r3, r7, r3
+ 800368c:	2200      	movs	r2, #0
+ 800368e:	701a      	strb	r2, [r3, #0]
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+ 8003690:	68fb      	ldr	r3, [r7, #12]
+ 8003692:	2238      	movs	r2, #56	; 0x38
+ 8003694:	5c9b      	ldrb	r3, [r3, r2]
+ 8003696:	2b01      	cmp	r3, #1
+ 8003698:	d101      	bne.n	800369e <HAL_TIM_PWM_ConfigChannel+0x22>
+ 800369a:	2302      	movs	r3, #2
+ 800369c:	e0ad      	b.n	80037fa <HAL_TIM_PWM_ConfigChannel+0x17e>
+ 800369e:	68fb      	ldr	r3, [r7, #12]
+ 80036a0:	2238      	movs	r2, #56	; 0x38
+ 80036a2:	2101      	movs	r1, #1
+ 80036a4:	5499      	strb	r1, [r3, r2]
+
+  switch (Channel)
+ 80036a6:	687b      	ldr	r3, [r7, #4]
+ 80036a8:	2b0c      	cmp	r3, #12
+ 80036aa:	d100      	bne.n	80036ae <HAL_TIM_PWM_ConfigChannel+0x32>
+ 80036ac:	e076      	b.n	800379c <HAL_TIM_PWM_ConfigChannel+0x120>
+ 80036ae:	687b      	ldr	r3, [r7, #4]
+ 80036b0:	2b0c      	cmp	r3, #12
+ 80036b2:	d900      	bls.n	80036b6 <HAL_TIM_PWM_ConfigChannel+0x3a>
+ 80036b4:	e095      	b.n	80037e2 <HAL_TIM_PWM_ConfigChannel+0x166>
+ 80036b6:	687b      	ldr	r3, [r7, #4]
+ 80036b8:	2b08      	cmp	r3, #8
+ 80036ba:	d04e      	beq.n	800375a <HAL_TIM_PWM_ConfigChannel+0xde>
+ 80036bc:	687b      	ldr	r3, [r7, #4]
+ 80036be:	2b08      	cmp	r3, #8
+ 80036c0:	d900      	bls.n	80036c4 <HAL_TIM_PWM_ConfigChannel+0x48>
+ 80036c2:	e08e      	b.n	80037e2 <HAL_TIM_PWM_ConfigChannel+0x166>
+ 80036c4:	687b      	ldr	r3, [r7, #4]
+ 80036c6:	2b00      	cmp	r3, #0
+ 80036c8:	d003      	beq.n	80036d2 <HAL_TIM_PWM_ConfigChannel+0x56>
+ 80036ca:	687b      	ldr	r3, [r7, #4]
+ 80036cc:	2b04      	cmp	r3, #4
+ 80036ce:	d021      	beq.n	8003714 <HAL_TIM_PWM_ConfigChannel+0x98>
+ 80036d0:	e087      	b.n	80037e2 <HAL_TIM_PWM_ConfigChannel+0x166>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+ 80036d2:	68fb      	ldr	r3, [r7, #12]
+ 80036d4:	681b      	ldr	r3, [r3, #0]
+ 80036d6:	68ba      	ldr	r2, [r7, #8]
+ 80036d8:	0011      	movs	r1, r2
+ 80036da:	0018      	movs	r0, r3
+ 80036dc:	f000 f9b2 	bl	8003a44 <TIM_OC1_SetConfig>
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+ 80036e0:	68fb      	ldr	r3, [r7, #12]
+ 80036e2:	681b      	ldr	r3, [r3, #0]
+ 80036e4:	699a      	ldr	r2, [r3, #24]
+ 80036e6:	68fb      	ldr	r3, [r7, #12]
+ 80036e8:	681b      	ldr	r3, [r3, #0]
+ 80036ea:	2108      	movs	r1, #8
+ 80036ec:	430a      	orrs	r2, r1
+ 80036ee:	619a      	str	r2, [r3, #24]
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ 80036f0:	68fb      	ldr	r3, [r7, #12]
+ 80036f2:	681b      	ldr	r3, [r3, #0]
+ 80036f4:	699a      	ldr	r2, [r3, #24]
+ 80036f6:	68fb      	ldr	r3, [r7, #12]
+ 80036f8:	681b      	ldr	r3, [r3, #0]
+ 80036fa:	2104      	movs	r1, #4
+ 80036fc:	438a      	bics	r2, r1
+ 80036fe:	619a      	str	r2, [r3, #24]
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 8003700:	68fb      	ldr	r3, [r7, #12]
+ 8003702:	681b      	ldr	r3, [r3, #0]
+ 8003704:	6999      	ldr	r1, [r3, #24]
+ 8003706:	68bb      	ldr	r3, [r7, #8]
+ 8003708:	68da      	ldr	r2, [r3, #12]
+ 800370a:	68fb      	ldr	r3, [r7, #12]
+ 800370c:	681b      	ldr	r3, [r3, #0]
+ 800370e:	430a      	orrs	r2, r1
+ 8003710:	619a      	str	r2, [r3, #24]
+      break;
+ 8003712:	e06b      	b.n	80037ec <HAL_TIM_PWM_ConfigChannel+0x170>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+ 8003714:	68fb      	ldr	r3, [r7, #12]
+ 8003716:	681b      	ldr	r3, [r3, #0]
+ 8003718:	68ba      	ldr	r2, [r7, #8]
+ 800371a:	0011      	movs	r1, r2
+ 800371c:	0018      	movs	r0, r3
+ 800371e:	f000 f9cd 	bl	8003abc <TIM_OC2_SetConfig>
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+ 8003722:	68fb      	ldr	r3, [r7, #12]
+ 8003724:	681b      	ldr	r3, [r3, #0]
+ 8003726:	699a      	ldr	r2, [r3, #24]
+ 8003728:	68fb      	ldr	r3, [r7, #12]
+ 800372a:	681b      	ldr	r3, [r3, #0]
+ 800372c:	2180      	movs	r1, #128	; 0x80
+ 800372e:	0109      	lsls	r1, r1, #4
+ 8003730:	430a      	orrs	r2, r1
+ 8003732:	619a      	str	r2, [r3, #24]
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ 8003734:	68fb      	ldr	r3, [r7, #12]
+ 8003736:	681b      	ldr	r3, [r3, #0]
+ 8003738:	699a      	ldr	r2, [r3, #24]
+ 800373a:	68fb      	ldr	r3, [r7, #12]
+ 800373c:	681b      	ldr	r3, [r3, #0]
+ 800373e:	4931      	ldr	r1, [pc, #196]	; (8003804 <HAL_TIM_PWM_ConfigChannel+0x188>)
+ 8003740:	400a      	ands	r2, r1
+ 8003742:	619a      	str	r2, [r3, #24]
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 8003744:	68fb      	ldr	r3, [r7, #12]
+ 8003746:	681b      	ldr	r3, [r3, #0]
+ 8003748:	6999      	ldr	r1, [r3, #24]
+ 800374a:	68bb      	ldr	r3, [r7, #8]
+ 800374c:	68db      	ldr	r3, [r3, #12]
+ 800374e:	021a      	lsls	r2, r3, #8
+ 8003750:	68fb      	ldr	r3, [r7, #12]
+ 8003752:	681b      	ldr	r3, [r3, #0]
+ 8003754:	430a      	orrs	r2, r1
+ 8003756:	619a      	str	r2, [r3, #24]
+      break;
+ 8003758:	e048      	b.n	80037ec <HAL_TIM_PWM_ConfigChannel+0x170>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+ 800375a:	68fb      	ldr	r3, [r7, #12]
+ 800375c:	681b      	ldr	r3, [r3, #0]
+ 800375e:	68ba      	ldr	r2, [r7, #8]
+ 8003760:	0011      	movs	r1, r2
+ 8003762:	0018      	movs	r0, r3
+ 8003764:	f000 f9ec 	bl	8003b40 <TIM_OC3_SetConfig>
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+ 8003768:	68fb      	ldr	r3, [r7, #12]
+ 800376a:	681b      	ldr	r3, [r3, #0]
+ 800376c:	69da      	ldr	r2, [r3, #28]
+ 800376e:	68fb      	ldr	r3, [r7, #12]
+ 8003770:	681b      	ldr	r3, [r3, #0]
+ 8003772:	2108      	movs	r1, #8
+ 8003774:	430a      	orrs	r2, r1
+ 8003776:	61da      	str	r2, [r3, #28]
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ 8003778:	68fb      	ldr	r3, [r7, #12]
+ 800377a:	681b      	ldr	r3, [r3, #0]
+ 800377c:	69da      	ldr	r2, [r3, #28]
+ 800377e:	68fb      	ldr	r3, [r7, #12]
+ 8003780:	681b      	ldr	r3, [r3, #0]
+ 8003782:	2104      	movs	r1, #4
+ 8003784:	438a      	bics	r2, r1
+ 8003786:	61da      	str	r2, [r3, #28]
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 8003788:	68fb      	ldr	r3, [r7, #12]
+ 800378a:	681b      	ldr	r3, [r3, #0]
+ 800378c:	69d9      	ldr	r1, [r3, #28]
+ 800378e:	68bb      	ldr	r3, [r7, #8]
+ 8003790:	68da      	ldr	r2, [r3, #12]
+ 8003792:	68fb      	ldr	r3, [r7, #12]
+ 8003794:	681b      	ldr	r3, [r3, #0]
+ 8003796:	430a      	orrs	r2, r1
+ 8003798:	61da      	str	r2, [r3, #28]
+      break;
+ 800379a:	e027      	b.n	80037ec <HAL_TIM_PWM_ConfigChannel+0x170>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+ 800379c:	68fb      	ldr	r3, [r7, #12]
+ 800379e:	681b      	ldr	r3, [r3, #0]
+ 80037a0:	68ba      	ldr	r2, [r7, #8]
+ 80037a2:	0011      	movs	r1, r2
+ 80037a4:	0018      	movs	r0, r3
+ 80037a6:	f000 fa0b 	bl	8003bc0 <TIM_OC4_SetConfig>
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+ 80037aa:	68fb      	ldr	r3, [r7, #12]
+ 80037ac:	681b      	ldr	r3, [r3, #0]
+ 80037ae:	69da      	ldr	r2, [r3, #28]
+ 80037b0:	68fb      	ldr	r3, [r7, #12]
+ 80037b2:	681b      	ldr	r3, [r3, #0]
+ 80037b4:	2180      	movs	r1, #128	; 0x80
+ 80037b6:	0109      	lsls	r1, r1, #4
+ 80037b8:	430a      	orrs	r2, r1
+ 80037ba:	61da      	str	r2, [r3, #28]
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ 80037bc:	68fb      	ldr	r3, [r7, #12]
+ 80037be:	681b      	ldr	r3, [r3, #0]
+ 80037c0:	69da      	ldr	r2, [r3, #28]
+ 80037c2:	68fb      	ldr	r3, [r7, #12]
+ 80037c4:	681b      	ldr	r3, [r3, #0]
+ 80037c6:	490f      	ldr	r1, [pc, #60]	; (8003804 <HAL_TIM_PWM_ConfigChannel+0x188>)
+ 80037c8:	400a      	ands	r2, r1
+ 80037ca:	61da      	str	r2, [r3, #28]
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 80037cc:	68fb      	ldr	r3, [r7, #12]
+ 80037ce:	681b      	ldr	r3, [r3, #0]
+ 80037d0:	69d9      	ldr	r1, [r3, #28]
+ 80037d2:	68bb      	ldr	r3, [r7, #8]
+ 80037d4:	68db      	ldr	r3, [r3, #12]
+ 80037d6:	021a      	lsls	r2, r3, #8
+ 80037d8:	68fb      	ldr	r3, [r7, #12]
+ 80037da:	681b      	ldr	r3, [r3, #0]
+ 80037dc:	430a      	orrs	r2, r1
+ 80037de:	61da      	str	r2, [r3, #28]
+      break;
+ 80037e0:	e004      	b.n	80037ec <HAL_TIM_PWM_ConfigChannel+0x170>
+    }
+
+    default:
+      status = HAL_ERROR;
+ 80037e2:	2317      	movs	r3, #23
+ 80037e4:	18fb      	adds	r3, r7, r3
+ 80037e6:	2201      	movs	r2, #1
+ 80037e8:	701a      	strb	r2, [r3, #0]
+      break;
+ 80037ea:	46c0      	nop			; (mov r8, r8)
+  }
+
+  __HAL_UNLOCK(htim);
+ 80037ec:	68fb      	ldr	r3, [r7, #12]
+ 80037ee:	2238      	movs	r2, #56	; 0x38
+ 80037f0:	2100      	movs	r1, #0
+ 80037f2:	5499      	strb	r1, [r3, r2]
+
+  return status;
+ 80037f4:	2317      	movs	r3, #23
+ 80037f6:	18fb      	adds	r3, r7, r3
+ 80037f8:	781b      	ldrb	r3, [r3, #0]
+}
+ 80037fa:	0018      	movs	r0, r3
+ 80037fc:	46bd      	mov	sp, r7
+ 80037fe:	b006      	add	sp, #24
+ 8003800:	bd80      	pop	{r7, pc}
+ 8003802:	46c0      	nop			; (mov r8, r8)
+ 8003804:	fffffbff 	.word	0xfffffbff
+
+08003808 <HAL_TIM_ConfigClockSource>:
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+ 8003808:	b580      	push	{r7, lr}
+ 800380a:	b084      	sub	sp, #16
+ 800380c:	af00      	add	r7, sp, #0
+ 800380e:	6078      	str	r0, [r7, #4]
+ 8003810:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8003812:	230f      	movs	r3, #15
+ 8003814:	18fb      	adds	r3, r7, r3
+ 8003816:	2200      	movs	r2, #0
+ 8003818:	701a      	strb	r2, [r3, #0]
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+ 800381a:	687b      	ldr	r3, [r7, #4]
+ 800381c:	2238      	movs	r2, #56	; 0x38
+ 800381e:	5c9b      	ldrb	r3, [r3, r2]
+ 8003820:	2b01      	cmp	r3, #1
+ 8003822:	d101      	bne.n	8003828 <HAL_TIM_ConfigClockSource+0x20>
+ 8003824:	2302      	movs	r3, #2
+ 8003826:	e0bc      	b.n	80039a2 <HAL_TIM_ConfigClockSource+0x19a>
+ 8003828:	687b      	ldr	r3, [r7, #4]
+ 800382a:	2238      	movs	r2, #56	; 0x38
+ 800382c:	2101      	movs	r1, #1
+ 800382e:	5499      	strb	r1, [r3, r2]
+
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8003830:	687b      	ldr	r3, [r7, #4]
+ 8003832:	2239      	movs	r2, #57	; 0x39
+ 8003834:	2102      	movs	r1, #2
+ 8003836:	5499      	strb	r1, [r3, r2]
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+ 8003838:	687b      	ldr	r3, [r7, #4]
+ 800383a:	681b      	ldr	r3, [r3, #0]
+ 800383c:	689b      	ldr	r3, [r3, #8]
+ 800383e:	60bb      	str	r3, [r7, #8]
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 8003840:	68bb      	ldr	r3, [r7, #8]
+ 8003842:	2277      	movs	r2, #119	; 0x77
+ 8003844:	4393      	bics	r3, r2
+ 8003846:	60bb      	str	r3, [r7, #8]
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8003848:	68bb      	ldr	r3, [r7, #8]
+ 800384a:	4a58      	ldr	r2, [pc, #352]	; (80039ac <HAL_TIM_ConfigClockSource+0x1a4>)
+ 800384c:	4013      	ands	r3, r2
+ 800384e:	60bb      	str	r3, [r7, #8]
+  htim->Instance->SMCR = tmpsmcr;
+ 8003850:	687b      	ldr	r3, [r7, #4]
+ 8003852:	681b      	ldr	r3, [r3, #0]
+ 8003854:	68ba      	ldr	r2, [r7, #8]
+ 8003856:	609a      	str	r2, [r3, #8]
+
+  switch (sClockSourceConfig->ClockSource)
+ 8003858:	683b      	ldr	r3, [r7, #0]
+ 800385a:	681b      	ldr	r3, [r3, #0]
+ 800385c:	2280      	movs	r2, #128	; 0x80
+ 800385e:	0192      	lsls	r2, r2, #6
+ 8003860:	4293      	cmp	r3, r2
+ 8003862:	d040      	beq.n	80038e6 <HAL_TIM_ConfigClockSource+0xde>
+ 8003864:	2280      	movs	r2, #128	; 0x80
+ 8003866:	0192      	lsls	r2, r2, #6
+ 8003868:	4293      	cmp	r3, r2
+ 800386a:	d900      	bls.n	800386e <HAL_TIM_ConfigClockSource+0x66>
+ 800386c:	e088      	b.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+ 800386e:	2280      	movs	r2, #128	; 0x80
+ 8003870:	0152      	lsls	r2, r2, #5
+ 8003872:	4293      	cmp	r3, r2
+ 8003874:	d100      	bne.n	8003878 <HAL_TIM_ConfigClockSource+0x70>
+ 8003876:	e088      	b.n	800398a <HAL_TIM_ConfigClockSource+0x182>
+ 8003878:	2280      	movs	r2, #128	; 0x80
+ 800387a:	0152      	lsls	r2, r2, #5
+ 800387c:	4293      	cmp	r3, r2
+ 800387e:	d900      	bls.n	8003882 <HAL_TIM_ConfigClockSource+0x7a>
+ 8003880:	e07e      	b.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+ 8003882:	2b70      	cmp	r3, #112	; 0x70
+ 8003884:	d018      	beq.n	80038b8 <HAL_TIM_ConfigClockSource+0xb0>
+ 8003886:	d900      	bls.n	800388a <HAL_TIM_ConfigClockSource+0x82>
+ 8003888:	e07a      	b.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+ 800388a:	2b60      	cmp	r3, #96	; 0x60
+ 800388c:	d04f      	beq.n	800392e <HAL_TIM_ConfigClockSource+0x126>
+ 800388e:	d900      	bls.n	8003892 <HAL_TIM_ConfigClockSource+0x8a>
+ 8003890:	e076      	b.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+ 8003892:	2b50      	cmp	r3, #80	; 0x50
+ 8003894:	d03b      	beq.n	800390e <HAL_TIM_ConfigClockSource+0x106>
+ 8003896:	d900      	bls.n	800389a <HAL_TIM_ConfigClockSource+0x92>
+ 8003898:	e072      	b.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+ 800389a:	2b40      	cmp	r3, #64	; 0x40
+ 800389c:	d057      	beq.n	800394e <HAL_TIM_ConfigClockSource+0x146>
+ 800389e:	d900      	bls.n	80038a2 <HAL_TIM_ConfigClockSource+0x9a>
+ 80038a0:	e06e      	b.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+ 80038a2:	2b30      	cmp	r3, #48	; 0x30
+ 80038a4:	d063      	beq.n	800396e <HAL_TIM_ConfigClockSource+0x166>
+ 80038a6:	d86b      	bhi.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+ 80038a8:	2b20      	cmp	r3, #32
+ 80038aa:	d060      	beq.n	800396e <HAL_TIM_ConfigClockSource+0x166>
+ 80038ac:	d868      	bhi.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+ 80038ae:	2b00      	cmp	r3, #0
+ 80038b0:	d05d      	beq.n	800396e <HAL_TIM_ConfigClockSource+0x166>
+ 80038b2:	2b10      	cmp	r3, #16
+ 80038b4:	d05b      	beq.n	800396e <HAL_TIM_ConfigClockSource+0x166>
+ 80038b6:	e063      	b.n	8003980 <HAL_TIM_ConfigClockSource+0x178>
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+ 80038b8:	687b      	ldr	r3, [r7, #4]
+ 80038ba:	6818      	ldr	r0, [r3, #0]
+ 80038bc:	683b      	ldr	r3, [r7, #0]
+ 80038be:	6899      	ldr	r1, [r3, #8]
+ 80038c0:	683b      	ldr	r3, [r7, #0]
+ 80038c2:	685a      	ldr	r2, [r3, #4]
+ 80038c4:	683b      	ldr	r3, [r7, #0]
+ 80038c6:	68db      	ldr	r3, [r3, #12]
+ 80038c8:	f000 fa3a 	bl	8003d40 <TIM_ETR_SetConfig>
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+ 80038cc:	687b      	ldr	r3, [r7, #4]
+ 80038ce:	681b      	ldr	r3, [r3, #0]
+ 80038d0:	689b      	ldr	r3, [r3, #8]
+ 80038d2:	60bb      	str	r3, [r7, #8]
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 80038d4:	68bb      	ldr	r3, [r7, #8]
+ 80038d6:	2277      	movs	r2, #119	; 0x77
+ 80038d8:	4313      	orrs	r3, r2
+ 80038da:	60bb      	str	r3, [r7, #8]
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+ 80038dc:	687b      	ldr	r3, [r7, #4]
+ 80038de:	681b      	ldr	r3, [r3, #0]
+ 80038e0:	68ba      	ldr	r2, [r7, #8]
+ 80038e2:	609a      	str	r2, [r3, #8]
+      break;
+ 80038e4:	e052      	b.n	800398c <HAL_TIM_ConfigClockSource+0x184>
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+ 80038e6:	687b      	ldr	r3, [r7, #4]
+ 80038e8:	6818      	ldr	r0, [r3, #0]
+ 80038ea:	683b      	ldr	r3, [r7, #0]
+ 80038ec:	6899      	ldr	r1, [r3, #8]
+ 80038ee:	683b      	ldr	r3, [r7, #0]
+ 80038f0:	685a      	ldr	r2, [r3, #4]
+ 80038f2:	683b      	ldr	r3, [r7, #0]
+ 80038f4:	68db      	ldr	r3, [r3, #12]
+ 80038f6:	f000 fa23 	bl	8003d40 <TIM_ETR_SetConfig>
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+ 80038fa:	687b      	ldr	r3, [r7, #4]
+ 80038fc:	681b      	ldr	r3, [r3, #0]
+ 80038fe:	689a      	ldr	r2, [r3, #8]
+ 8003900:	687b      	ldr	r3, [r7, #4]
+ 8003902:	681b      	ldr	r3, [r3, #0]
+ 8003904:	2180      	movs	r1, #128	; 0x80
+ 8003906:	01c9      	lsls	r1, r1, #7
+ 8003908:	430a      	orrs	r2, r1
+ 800390a:	609a      	str	r2, [r3, #8]
+      break;
+ 800390c:	e03e      	b.n	800398c <HAL_TIM_ConfigClockSource+0x184>
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 800390e:	687b      	ldr	r3, [r7, #4]
+ 8003910:	6818      	ldr	r0, [r3, #0]
+ 8003912:	683b      	ldr	r3, [r7, #0]
+ 8003914:	6859      	ldr	r1, [r3, #4]
+ 8003916:	683b      	ldr	r3, [r7, #0]
+ 8003918:	68db      	ldr	r3, [r3, #12]
+ 800391a:	001a      	movs	r2, r3
+ 800391c:	f000 f996 	bl	8003c4c <TIM_TI1_ConfigInputStage>
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ 8003920:	687b      	ldr	r3, [r7, #4]
+ 8003922:	681b      	ldr	r3, [r3, #0]
+ 8003924:	2150      	movs	r1, #80	; 0x50
+ 8003926:	0018      	movs	r0, r3
+ 8003928:	f000 f9f0 	bl	8003d0c <TIM_ITRx_SetConfig>
+      break;
+ 800392c:	e02e      	b.n	800398c <HAL_TIM_ConfigClockSource+0x184>
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+ 800392e:	687b      	ldr	r3, [r7, #4]
+ 8003930:	6818      	ldr	r0, [r3, #0]
+ 8003932:	683b      	ldr	r3, [r7, #0]
+ 8003934:	6859      	ldr	r1, [r3, #4]
+ 8003936:	683b      	ldr	r3, [r7, #0]
+ 8003938:	68db      	ldr	r3, [r3, #12]
+ 800393a:	001a      	movs	r2, r3
+ 800393c:	f000 f9b4 	bl	8003ca8 <TIM_TI2_ConfigInputStage>
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ 8003940:	687b      	ldr	r3, [r7, #4]
+ 8003942:	681b      	ldr	r3, [r3, #0]
+ 8003944:	2160      	movs	r1, #96	; 0x60
+ 8003946:	0018      	movs	r0, r3
+ 8003948:	f000 f9e0 	bl	8003d0c <TIM_ITRx_SetConfig>
+      break;
+ 800394c:	e01e      	b.n	800398c <HAL_TIM_ConfigClockSource+0x184>
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 800394e:	687b      	ldr	r3, [r7, #4]
+ 8003950:	6818      	ldr	r0, [r3, #0]
+ 8003952:	683b      	ldr	r3, [r7, #0]
+ 8003954:	6859      	ldr	r1, [r3, #4]
+ 8003956:	683b      	ldr	r3, [r7, #0]
+ 8003958:	68db      	ldr	r3, [r3, #12]
+ 800395a:	001a      	movs	r2, r3
+ 800395c:	f000 f976 	bl	8003c4c <TIM_TI1_ConfigInputStage>
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ 8003960:	687b      	ldr	r3, [r7, #4]
+ 8003962:	681b      	ldr	r3, [r3, #0]
+ 8003964:	2140      	movs	r1, #64	; 0x40
+ 8003966:	0018      	movs	r0, r3
+ 8003968:	f000 f9d0 	bl	8003d0c <TIM_ITRx_SetConfig>
+      break;
+ 800396c:	e00e      	b.n	800398c <HAL_TIM_ConfigClockSource+0x184>
+    case TIM_CLOCKSOURCE_ITR3:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ 800396e:	687b      	ldr	r3, [r7, #4]
+ 8003970:	681a      	ldr	r2, [r3, #0]
+ 8003972:	683b      	ldr	r3, [r7, #0]
+ 8003974:	681b      	ldr	r3, [r3, #0]
+ 8003976:	0019      	movs	r1, r3
+ 8003978:	0010      	movs	r0, r2
+ 800397a:	f000 f9c7 	bl	8003d0c <TIM_ITRx_SetConfig>
+      break;
+ 800397e:	e005      	b.n	800398c <HAL_TIM_ConfigClockSource+0x184>
+    }
+
+    default:
+      status = HAL_ERROR;
+ 8003980:	230f      	movs	r3, #15
+ 8003982:	18fb      	adds	r3, r7, r3
+ 8003984:	2201      	movs	r2, #1
+ 8003986:	701a      	strb	r2, [r3, #0]
+      break;
+ 8003988:	e000      	b.n	800398c <HAL_TIM_ConfigClockSource+0x184>
+      break;
+ 800398a:	46c0      	nop			; (mov r8, r8)
+  }
+  htim->State = HAL_TIM_STATE_READY;
+ 800398c:	687b      	ldr	r3, [r7, #4]
+ 800398e:	2239      	movs	r2, #57	; 0x39
+ 8003990:	2101      	movs	r1, #1
+ 8003992:	5499      	strb	r1, [r3, r2]
+
+  __HAL_UNLOCK(htim);
+ 8003994:	687b      	ldr	r3, [r7, #4]
+ 8003996:	2238      	movs	r2, #56	; 0x38
+ 8003998:	2100      	movs	r1, #0
+ 800399a:	5499      	strb	r1, [r3, r2]
+
+  return status;
+ 800399c:	230f      	movs	r3, #15
+ 800399e:	18fb      	adds	r3, r7, r3
+ 80039a0:	781b      	ldrb	r3, [r3, #0]
+}
+ 80039a2:	0018      	movs	r0, r3
+ 80039a4:	46bd      	mov	sp, r7
+ 80039a6:	b004      	add	sp, #16
+ 80039a8:	bd80      	pop	{r7, pc}
+ 80039aa:	46c0      	nop			; (mov r8, r8)
+ 80039ac:	ffff00ff 	.word	0xffff00ff
+
+080039b0 <TIM_Base_SetConfig>:
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ 80039b0:	b580      	push	{r7, lr}
+ 80039b2:	b084      	sub	sp, #16
+ 80039b4:	af00      	add	r7, sp, #0
+ 80039b6:	6078      	str	r0, [r7, #4]
+ 80039b8:	6039      	str	r1, [r7, #0]
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+ 80039ba:	687b      	ldr	r3, [r7, #4]
+ 80039bc:	681b      	ldr	r3, [r3, #0]
+ 80039be:	60fb      	str	r3, [r7, #12]
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 80039c0:	687a      	ldr	r2, [r7, #4]
+ 80039c2:	2380      	movs	r3, #128	; 0x80
+ 80039c4:	05db      	lsls	r3, r3, #23
+ 80039c6:	429a      	cmp	r2, r3
+ 80039c8:	d003      	beq.n	80039d2 <TIM_Base_SetConfig+0x22>
+ 80039ca:	687b      	ldr	r3, [r7, #4]
+ 80039cc:	4a1b      	ldr	r2, [pc, #108]	; (8003a3c <TIM_Base_SetConfig+0x8c>)
+ 80039ce:	4293      	cmp	r3, r2
+ 80039d0:	d108      	bne.n	80039e4 <TIM_Base_SetConfig+0x34>
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ 80039d2:	68fb      	ldr	r3, [r7, #12]
+ 80039d4:	2270      	movs	r2, #112	; 0x70
+ 80039d6:	4393      	bics	r3, r2
+ 80039d8:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= Structure->CounterMode;
+ 80039da:	683b      	ldr	r3, [r7, #0]
+ 80039dc:	685b      	ldr	r3, [r3, #4]
+ 80039de:	68fa      	ldr	r2, [r7, #12]
+ 80039e0:	4313      	orrs	r3, r2
+ 80039e2:	60fb      	str	r3, [r7, #12]
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 80039e4:	687a      	ldr	r2, [r7, #4]
+ 80039e6:	2380      	movs	r3, #128	; 0x80
+ 80039e8:	05db      	lsls	r3, r3, #23
+ 80039ea:	429a      	cmp	r2, r3
+ 80039ec:	d003      	beq.n	80039f6 <TIM_Base_SetConfig+0x46>
+ 80039ee:	687b      	ldr	r3, [r7, #4]
+ 80039f0:	4a12      	ldr	r2, [pc, #72]	; (8003a3c <TIM_Base_SetConfig+0x8c>)
+ 80039f2:	4293      	cmp	r3, r2
+ 80039f4:	d108      	bne.n	8003a08 <TIM_Base_SetConfig+0x58>
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+ 80039f6:	68fb      	ldr	r3, [r7, #12]
+ 80039f8:	4a11      	ldr	r2, [pc, #68]	; (8003a40 <TIM_Base_SetConfig+0x90>)
+ 80039fa:	4013      	ands	r3, r2
+ 80039fc:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 80039fe:	683b      	ldr	r3, [r7, #0]
+ 8003a00:	68db      	ldr	r3, [r3, #12]
+ 8003a02:	68fa      	ldr	r2, [r7, #12]
+ 8003a04:	4313      	orrs	r3, r2
+ 8003a06:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+ 8003a08:	68fb      	ldr	r3, [r7, #12]
+ 8003a0a:	2280      	movs	r2, #128	; 0x80
+ 8003a0c:	4393      	bics	r3, r2
+ 8003a0e:	001a      	movs	r2, r3
+ 8003a10:	683b      	ldr	r3, [r7, #0]
+ 8003a12:	691b      	ldr	r3, [r3, #16]
+ 8003a14:	4313      	orrs	r3, r2
+ 8003a16:	60fb      	str	r3, [r7, #12]
+
+  TIMx->CR1 = tmpcr1;
+ 8003a18:	687b      	ldr	r3, [r7, #4]
+ 8003a1a:	68fa      	ldr	r2, [r7, #12]
+ 8003a1c:	601a      	str	r2, [r3, #0]
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+ 8003a1e:	683b      	ldr	r3, [r7, #0]
+ 8003a20:	689a      	ldr	r2, [r3, #8]
+ 8003a22:	687b      	ldr	r3, [r7, #4]
+ 8003a24:	62da      	str	r2, [r3, #44]	; 0x2c
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+ 8003a26:	683b      	ldr	r3, [r7, #0]
+ 8003a28:	681a      	ldr	r2, [r3, #0]
+ 8003a2a:	687b      	ldr	r3, [r7, #4]
+ 8003a2c:	629a      	str	r2, [r3, #40]	; 0x28
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+ 8003a2e:	687b      	ldr	r3, [r7, #4]
+ 8003a30:	2201      	movs	r2, #1
+ 8003a32:	615a      	str	r2, [r3, #20]
+}
+ 8003a34:	46c0      	nop			; (mov r8, r8)
+ 8003a36:	46bd      	mov	sp, r7
+ 8003a38:	b004      	add	sp, #16
+ 8003a3a:	bd80      	pop	{r7, pc}
+ 8003a3c:	40010800 	.word	0x40010800
+ 8003a40:	fffffcff 	.word	0xfffffcff
+
+08003a44 <TIM_OC1_SetConfig>:
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ 8003a44:	b580      	push	{r7, lr}
+ 8003a46:	b086      	sub	sp, #24
+ 8003a48:	af00      	add	r7, sp, #0
+ 8003a4a:	6078      	str	r0, [r7, #4]
+ 8003a4c:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 8003a4e:	687b      	ldr	r3, [r7, #4]
+ 8003a50:	6a1b      	ldr	r3, [r3, #32]
+ 8003a52:	2201      	movs	r2, #1
+ 8003a54:	4393      	bics	r3, r2
+ 8003a56:	001a      	movs	r2, r3
+ 8003a58:	687b      	ldr	r3, [r7, #4]
+ 8003a5a:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 8003a5c:	687b      	ldr	r3, [r7, #4]
+ 8003a5e:	6a1b      	ldr	r3, [r3, #32]
+ 8003a60:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 8003a62:	687b      	ldr	r3, [r7, #4]
+ 8003a64:	685b      	ldr	r3, [r3, #4]
+ 8003a66:	613b      	str	r3, [r7, #16]
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+ 8003a68:	687b      	ldr	r3, [r7, #4]
+ 8003a6a:	699b      	ldr	r3, [r3, #24]
+ 8003a6c:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+ 8003a6e:	68fb      	ldr	r3, [r7, #12]
+ 8003a70:	2270      	movs	r2, #112	; 0x70
+ 8003a72:	4393      	bics	r3, r2
+ 8003a74:	60fb      	str	r3, [r7, #12]
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+ 8003a76:	68fb      	ldr	r3, [r7, #12]
+ 8003a78:	2203      	movs	r2, #3
+ 8003a7a:	4393      	bics	r3, r2
+ 8003a7c:	60fb      	str	r3, [r7, #12]
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+ 8003a7e:	683b      	ldr	r3, [r7, #0]
+ 8003a80:	681b      	ldr	r3, [r3, #0]
+ 8003a82:	68fa      	ldr	r2, [r7, #12]
+ 8003a84:	4313      	orrs	r3, r2
+ 8003a86:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+ 8003a88:	697b      	ldr	r3, [r7, #20]
+ 8003a8a:	2202      	movs	r2, #2
+ 8003a8c:	4393      	bics	r3, r2
+ 8003a8e:	617b      	str	r3, [r7, #20]
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+ 8003a90:	683b      	ldr	r3, [r7, #0]
+ 8003a92:	689b      	ldr	r3, [r3, #8]
+ 8003a94:	697a      	ldr	r2, [r7, #20]
+ 8003a96:	4313      	orrs	r3, r2
+ 8003a98:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 8003a9a:	687b      	ldr	r3, [r7, #4]
+ 8003a9c:	693a      	ldr	r2, [r7, #16]
+ 8003a9e:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+ 8003aa0:	687b      	ldr	r3, [r7, #4]
+ 8003aa2:	68fa      	ldr	r2, [r7, #12]
+ 8003aa4:	619a      	str	r2, [r3, #24]
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+ 8003aa6:	683b      	ldr	r3, [r7, #0]
+ 8003aa8:	685a      	ldr	r2, [r3, #4]
+ 8003aaa:	687b      	ldr	r3, [r7, #4]
+ 8003aac:	635a      	str	r2, [r3, #52]	; 0x34
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8003aae:	687b      	ldr	r3, [r7, #4]
+ 8003ab0:	697a      	ldr	r2, [r7, #20]
+ 8003ab2:	621a      	str	r2, [r3, #32]
+}
+ 8003ab4:	46c0      	nop			; (mov r8, r8)
+ 8003ab6:	46bd      	mov	sp, r7
+ 8003ab8:	b006      	add	sp, #24
+ 8003aba:	bd80      	pop	{r7, pc}
+
+08003abc <TIM_OC2_SetConfig>:
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ 8003abc:	b580      	push	{r7, lr}
+ 8003abe:	b086      	sub	sp, #24
+ 8003ac0:	af00      	add	r7, sp, #0
+ 8003ac2:	6078      	str	r0, [r7, #4]
+ 8003ac4:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 8003ac6:	687b      	ldr	r3, [r7, #4]
+ 8003ac8:	6a1b      	ldr	r3, [r3, #32]
+ 8003aca:	2210      	movs	r2, #16
+ 8003acc:	4393      	bics	r3, r2
+ 8003ace:	001a      	movs	r2, r3
+ 8003ad0:	687b      	ldr	r3, [r7, #4]
+ 8003ad2:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 8003ad4:	687b      	ldr	r3, [r7, #4]
+ 8003ad6:	6a1b      	ldr	r3, [r3, #32]
+ 8003ad8:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 8003ada:	687b      	ldr	r3, [r7, #4]
+ 8003adc:	685b      	ldr	r3, [r3, #4]
+ 8003ade:	613b      	str	r3, [r7, #16]
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+ 8003ae0:	687b      	ldr	r3, [r7, #4]
+ 8003ae2:	699b      	ldr	r3, [r3, #24]
+ 8003ae4:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+ 8003ae6:	68fb      	ldr	r3, [r7, #12]
+ 8003ae8:	4a13      	ldr	r2, [pc, #76]	; (8003b38 <TIM_OC2_SetConfig+0x7c>)
+ 8003aea:	4013      	ands	r3, r2
+ 8003aec:	60fb      	str	r3, [r7, #12]
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+ 8003aee:	68fb      	ldr	r3, [r7, #12]
+ 8003af0:	4a12      	ldr	r2, [pc, #72]	; (8003b3c <TIM_OC2_SetConfig+0x80>)
+ 8003af2:	4013      	ands	r3, r2
+ 8003af4:	60fb      	str	r3, [r7, #12]
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+ 8003af6:	683b      	ldr	r3, [r7, #0]
+ 8003af8:	681b      	ldr	r3, [r3, #0]
+ 8003afa:	021b      	lsls	r3, r3, #8
+ 8003afc:	68fa      	ldr	r2, [r7, #12]
+ 8003afe:	4313      	orrs	r3, r2
+ 8003b00:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+ 8003b02:	697b      	ldr	r3, [r7, #20]
+ 8003b04:	2220      	movs	r2, #32
+ 8003b06:	4393      	bics	r3, r2
+ 8003b08:	617b      	str	r3, [r7, #20]
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+ 8003b0a:	683b      	ldr	r3, [r7, #0]
+ 8003b0c:	689b      	ldr	r3, [r3, #8]
+ 8003b0e:	011b      	lsls	r3, r3, #4
+ 8003b10:	697a      	ldr	r2, [r7, #20]
+ 8003b12:	4313      	orrs	r3, r2
+ 8003b14:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 8003b16:	687b      	ldr	r3, [r7, #4]
+ 8003b18:	693a      	ldr	r2, [r7, #16]
+ 8003b1a:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+ 8003b1c:	687b      	ldr	r3, [r7, #4]
+ 8003b1e:	68fa      	ldr	r2, [r7, #12]
+ 8003b20:	619a      	str	r2, [r3, #24]
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+ 8003b22:	683b      	ldr	r3, [r7, #0]
+ 8003b24:	685a      	ldr	r2, [r3, #4]
+ 8003b26:	687b      	ldr	r3, [r7, #4]
+ 8003b28:	639a      	str	r2, [r3, #56]	; 0x38
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8003b2a:	687b      	ldr	r3, [r7, #4]
+ 8003b2c:	697a      	ldr	r2, [r7, #20]
+ 8003b2e:	621a      	str	r2, [r3, #32]
+}
+ 8003b30:	46c0      	nop			; (mov r8, r8)
+ 8003b32:	46bd      	mov	sp, r7
+ 8003b34:	b006      	add	sp, #24
+ 8003b36:	bd80      	pop	{r7, pc}
+ 8003b38:	ffff8fff 	.word	0xffff8fff
+ 8003b3c:	fffffcff 	.word	0xfffffcff
+
+08003b40 <TIM_OC3_SetConfig>:
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ 8003b40:	b580      	push	{r7, lr}
+ 8003b42:	b086      	sub	sp, #24
+ 8003b44:	af00      	add	r7, sp, #0
+ 8003b46:	6078      	str	r0, [r7, #4]
+ 8003b48:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+ 8003b4a:	687b      	ldr	r3, [r7, #4]
+ 8003b4c:	6a1b      	ldr	r3, [r3, #32]
+ 8003b4e:	4a1a      	ldr	r2, [pc, #104]	; (8003bb8 <TIM_OC3_SetConfig+0x78>)
+ 8003b50:	401a      	ands	r2, r3
+ 8003b52:	687b      	ldr	r3, [r7, #4]
+ 8003b54:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 8003b56:	687b      	ldr	r3, [r7, #4]
+ 8003b58:	6a1b      	ldr	r3, [r3, #32]
+ 8003b5a:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 8003b5c:	687b      	ldr	r3, [r7, #4]
+ 8003b5e:	685b      	ldr	r3, [r3, #4]
+ 8003b60:	613b      	str	r3, [r7, #16]
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+ 8003b62:	687b      	ldr	r3, [r7, #4]
+ 8003b64:	69db      	ldr	r3, [r3, #28]
+ 8003b66:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+ 8003b68:	68fb      	ldr	r3, [r7, #12]
+ 8003b6a:	2270      	movs	r2, #112	; 0x70
+ 8003b6c:	4393      	bics	r3, r2
+ 8003b6e:	60fb      	str	r3, [r7, #12]
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+ 8003b70:	68fb      	ldr	r3, [r7, #12]
+ 8003b72:	2203      	movs	r2, #3
+ 8003b74:	4393      	bics	r3, r2
+ 8003b76:	60fb      	str	r3, [r7, #12]
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+ 8003b78:	683b      	ldr	r3, [r7, #0]
+ 8003b7a:	681b      	ldr	r3, [r3, #0]
+ 8003b7c:	68fa      	ldr	r2, [r7, #12]
+ 8003b7e:	4313      	orrs	r3, r2
+ 8003b80:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+ 8003b82:	697b      	ldr	r3, [r7, #20]
+ 8003b84:	4a0d      	ldr	r2, [pc, #52]	; (8003bbc <TIM_OC3_SetConfig+0x7c>)
+ 8003b86:	4013      	ands	r3, r2
+ 8003b88:	617b      	str	r3, [r7, #20]
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+ 8003b8a:	683b      	ldr	r3, [r7, #0]
+ 8003b8c:	689b      	ldr	r3, [r3, #8]
+ 8003b8e:	021b      	lsls	r3, r3, #8
+ 8003b90:	697a      	ldr	r2, [r7, #20]
+ 8003b92:	4313      	orrs	r3, r2
+ 8003b94:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 8003b96:	687b      	ldr	r3, [r7, #4]
+ 8003b98:	693a      	ldr	r2, [r7, #16]
+ 8003b9a:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+ 8003b9c:	687b      	ldr	r3, [r7, #4]
+ 8003b9e:	68fa      	ldr	r2, [r7, #12]
+ 8003ba0:	61da      	str	r2, [r3, #28]
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+ 8003ba2:	683b      	ldr	r3, [r7, #0]
+ 8003ba4:	685a      	ldr	r2, [r3, #4]
+ 8003ba6:	687b      	ldr	r3, [r7, #4]
+ 8003ba8:	63da      	str	r2, [r3, #60]	; 0x3c
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8003baa:	687b      	ldr	r3, [r7, #4]
+ 8003bac:	697a      	ldr	r2, [r7, #20]
+ 8003bae:	621a      	str	r2, [r3, #32]
+}
+ 8003bb0:	46c0      	nop			; (mov r8, r8)
+ 8003bb2:	46bd      	mov	sp, r7
+ 8003bb4:	b006      	add	sp, #24
+ 8003bb6:	bd80      	pop	{r7, pc}
+ 8003bb8:	fffffeff 	.word	0xfffffeff
+ 8003bbc:	fffffdff 	.word	0xfffffdff
+
+08003bc0 <TIM_OC4_SetConfig>:
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ 8003bc0:	b580      	push	{r7, lr}
+ 8003bc2:	b086      	sub	sp, #24
+ 8003bc4:	af00      	add	r7, sp, #0
+ 8003bc6:	6078      	str	r0, [r7, #4]
+ 8003bc8:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+ 8003bca:	687b      	ldr	r3, [r7, #4]
+ 8003bcc:	6a1b      	ldr	r3, [r3, #32]
+ 8003bce:	4a1b      	ldr	r2, [pc, #108]	; (8003c3c <TIM_OC4_SetConfig+0x7c>)
+ 8003bd0:	401a      	ands	r2, r3
+ 8003bd2:	687b      	ldr	r3, [r7, #4]
+ 8003bd4:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 8003bd6:	687b      	ldr	r3, [r7, #4]
+ 8003bd8:	6a1b      	ldr	r3, [r3, #32]
+ 8003bda:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 8003bdc:	687b      	ldr	r3, [r7, #4]
+ 8003bde:	685b      	ldr	r3, [r3, #4]
+ 8003be0:	613b      	str	r3, [r7, #16]
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+ 8003be2:	687b      	ldr	r3, [r7, #4]
+ 8003be4:	69db      	ldr	r3, [r3, #28]
+ 8003be6:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+ 8003be8:	68fb      	ldr	r3, [r7, #12]
+ 8003bea:	4a15      	ldr	r2, [pc, #84]	; (8003c40 <TIM_OC4_SetConfig+0x80>)
+ 8003bec:	4013      	ands	r3, r2
+ 8003bee:	60fb      	str	r3, [r7, #12]
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+ 8003bf0:	68fb      	ldr	r3, [r7, #12]
+ 8003bf2:	4a14      	ldr	r2, [pc, #80]	; (8003c44 <TIM_OC4_SetConfig+0x84>)
+ 8003bf4:	4013      	ands	r3, r2
+ 8003bf6:	60fb      	str	r3, [r7, #12]
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+ 8003bf8:	683b      	ldr	r3, [r7, #0]
+ 8003bfa:	681b      	ldr	r3, [r3, #0]
+ 8003bfc:	021b      	lsls	r3, r3, #8
+ 8003bfe:	68fa      	ldr	r2, [r7, #12]
+ 8003c00:	4313      	orrs	r3, r2
+ 8003c02:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+ 8003c04:	697b      	ldr	r3, [r7, #20]
+ 8003c06:	4a10      	ldr	r2, [pc, #64]	; (8003c48 <TIM_OC4_SetConfig+0x88>)
+ 8003c08:	4013      	ands	r3, r2
+ 8003c0a:	617b      	str	r3, [r7, #20]
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+ 8003c0c:	683b      	ldr	r3, [r7, #0]
+ 8003c0e:	689b      	ldr	r3, [r3, #8]
+ 8003c10:	031b      	lsls	r3, r3, #12
+ 8003c12:	697a      	ldr	r2, [r7, #20]
+ 8003c14:	4313      	orrs	r3, r2
+ 8003c16:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 8003c18:	687b      	ldr	r3, [r7, #4]
+ 8003c1a:	693a      	ldr	r2, [r7, #16]
+ 8003c1c:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+ 8003c1e:	687b      	ldr	r3, [r7, #4]
+ 8003c20:	68fa      	ldr	r2, [r7, #12]
+ 8003c22:	61da      	str	r2, [r3, #28]
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+ 8003c24:	683b      	ldr	r3, [r7, #0]
+ 8003c26:	685a      	ldr	r2, [r3, #4]
+ 8003c28:	687b      	ldr	r3, [r7, #4]
+ 8003c2a:	641a      	str	r2, [r3, #64]	; 0x40
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8003c2c:	687b      	ldr	r3, [r7, #4]
+ 8003c2e:	697a      	ldr	r2, [r7, #20]
+ 8003c30:	621a      	str	r2, [r3, #32]
+}
+ 8003c32:	46c0      	nop			; (mov r8, r8)
+ 8003c34:	46bd      	mov	sp, r7
+ 8003c36:	b006      	add	sp, #24
+ 8003c38:	bd80      	pop	{r7, pc}
+ 8003c3a:	46c0      	nop			; (mov r8, r8)
+ 8003c3c:	ffffefff 	.word	0xffffefff
+ 8003c40:	ffff8fff 	.word	0xffff8fff
+ 8003c44:	fffffcff 	.word	0xfffffcff
+ 8003c48:	ffffdfff 	.word	0xffffdfff
+
+08003c4c <TIM_TI1_ConfigInputStage>:
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 8003c4c:	b580      	push	{r7, lr}
+ 8003c4e:	b086      	sub	sp, #24
+ 8003c50:	af00      	add	r7, sp, #0
+ 8003c52:	60f8      	str	r0, [r7, #12]
+ 8003c54:	60b9      	str	r1, [r7, #8]
+ 8003c56:	607a      	str	r2, [r7, #4]
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+ 8003c58:	68fb      	ldr	r3, [r7, #12]
+ 8003c5a:	6a1b      	ldr	r3, [r3, #32]
+ 8003c5c:	617b      	str	r3, [r7, #20]
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 8003c5e:	68fb      	ldr	r3, [r7, #12]
+ 8003c60:	6a1b      	ldr	r3, [r3, #32]
+ 8003c62:	2201      	movs	r2, #1
+ 8003c64:	4393      	bics	r3, r2
+ 8003c66:	001a      	movs	r2, r3
+ 8003c68:	68fb      	ldr	r3, [r7, #12]
+ 8003c6a:	621a      	str	r2, [r3, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 8003c6c:	68fb      	ldr	r3, [r7, #12]
+ 8003c6e:	699b      	ldr	r3, [r3, #24]
+ 8003c70:	613b      	str	r3, [r7, #16]
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 8003c72:	693b      	ldr	r3, [r7, #16]
+ 8003c74:	22f0      	movs	r2, #240	; 0xf0
+ 8003c76:	4393      	bics	r3, r2
+ 8003c78:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+ 8003c7a:	687b      	ldr	r3, [r7, #4]
+ 8003c7c:	011b      	lsls	r3, r3, #4
+ 8003c7e:	693a      	ldr	r2, [r7, #16]
+ 8003c80:	4313      	orrs	r3, r2
+ 8003c82:	613b      	str	r3, [r7, #16]
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 8003c84:	697b      	ldr	r3, [r7, #20]
+ 8003c86:	220a      	movs	r2, #10
+ 8003c88:	4393      	bics	r3, r2
+ 8003c8a:	617b      	str	r3, [r7, #20]
+  tmpccer |= TIM_ICPolarity;
+ 8003c8c:	697a      	ldr	r2, [r7, #20]
+ 8003c8e:	68bb      	ldr	r3, [r7, #8]
+ 8003c90:	4313      	orrs	r3, r2
+ 8003c92:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+ 8003c94:	68fb      	ldr	r3, [r7, #12]
+ 8003c96:	693a      	ldr	r2, [r7, #16]
+ 8003c98:	619a      	str	r2, [r3, #24]
+  TIMx->CCER = tmpccer;
+ 8003c9a:	68fb      	ldr	r3, [r7, #12]
+ 8003c9c:	697a      	ldr	r2, [r7, #20]
+ 8003c9e:	621a      	str	r2, [r3, #32]
+}
+ 8003ca0:	46c0      	nop			; (mov r8, r8)
+ 8003ca2:	46bd      	mov	sp, r7
+ 8003ca4:	b006      	add	sp, #24
+ 8003ca6:	bd80      	pop	{r7, pc}
+
+08003ca8 <TIM_TI2_ConfigInputStage>:
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 8003ca8:	b580      	push	{r7, lr}
+ 8003caa:	b086      	sub	sp, #24
+ 8003cac:	af00      	add	r7, sp, #0
+ 8003cae:	60f8      	str	r0, [r7, #12]
+ 8003cb0:	60b9      	str	r1, [r7, #8]
+ 8003cb2:	607a      	str	r2, [r7, #4]
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 8003cb4:	68fb      	ldr	r3, [r7, #12]
+ 8003cb6:	6a1b      	ldr	r3, [r3, #32]
+ 8003cb8:	2210      	movs	r2, #16
+ 8003cba:	4393      	bics	r3, r2
+ 8003cbc:	001a      	movs	r2, r3
+ 8003cbe:	68fb      	ldr	r3, [r7, #12]
+ 8003cc0:	621a      	str	r2, [r3, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 8003cc2:	68fb      	ldr	r3, [r7, #12]
+ 8003cc4:	699b      	ldr	r3, [r3, #24]
+ 8003cc6:	617b      	str	r3, [r7, #20]
+  tmpccer = TIMx->CCER;
+ 8003cc8:	68fb      	ldr	r3, [r7, #12]
+ 8003cca:	6a1b      	ldr	r3, [r3, #32]
+ 8003ccc:	613b      	str	r3, [r7, #16]
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 8003cce:	697b      	ldr	r3, [r7, #20]
+ 8003cd0:	4a0d      	ldr	r2, [pc, #52]	; (8003d08 <TIM_TI2_ConfigInputStage+0x60>)
+ 8003cd2:	4013      	ands	r3, r2
+ 8003cd4:	617b      	str	r3, [r7, #20]
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+ 8003cd6:	687b      	ldr	r3, [r7, #4]
+ 8003cd8:	031b      	lsls	r3, r3, #12
+ 8003cda:	697a      	ldr	r2, [r7, #20]
+ 8003cdc:	4313      	orrs	r3, r2
+ 8003cde:	617b      	str	r3, [r7, #20]
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 8003ce0:	693b      	ldr	r3, [r7, #16]
+ 8003ce2:	22a0      	movs	r2, #160	; 0xa0
+ 8003ce4:	4393      	bics	r3, r2
+ 8003ce6:	613b      	str	r3, [r7, #16]
+  tmpccer |= (TIM_ICPolarity << 4U);
+ 8003ce8:	68bb      	ldr	r3, [r7, #8]
+ 8003cea:	011b      	lsls	r3, r3, #4
+ 8003cec:	693a      	ldr	r2, [r7, #16]
+ 8003cee:	4313      	orrs	r3, r2
+ 8003cf0:	613b      	str	r3, [r7, #16]
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+ 8003cf2:	68fb      	ldr	r3, [r7, #12]
+ 8003cf4:	697a      	ldr	r2, [r7, #20]
+ 8003cf6:	619a      	str	r2, [r3, #24]
+  TIMx->CCER = tmpccer;
+ 8003cf8:	68fb      	ldr	r3, [r7, #12]
+ 8003cfa:	693a      	ldr	r2, [r7, #16]
+ 8003cfc:	621a      	str	r2, [r3, #32]
+}
+ 8003cfe:	46c0      	nop			; (mov r8, r8)
+ 8003d00:	46bd      	mov	sp, r7
+ 8003d02:	b006      	add	sp, #24
+ 8003d04:	bd80      	pop	{r7, pc}
+ 8003d06:	46c0      	nop			; (mov r8, r8)
+ 8003d08:	ffff0fff 	.word	0xffff0fff
+
+08003d0c <TIM_ITRx_SetConfig>:
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+ 8003d0c:	b580      	push	{r7, lr}
+ 8003d0e:	b084      	sub	sp, #16
+ 8003d10:	af00      	add	r7, sp, #0
+ 8003d12:	6078      	str	r0, [r7, #4]
+ 8003d14:	6039      	str	r1, [r7, #0]
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+ 8003d16:	687b      	ldr	r3, [r7, #4]
+ 8003d18:	689b      	ldr	r3, [r3, #8]
+ 8003d1a:	60fb      	str	r3, [r7, #12]
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 8003d1c:	68fb      	ldr	r3, [r7, #12]
+ 8003d1e:	2270      	movs	r2, #112	; 0x70
+ 8003d20:	4393      	bics	r3, r2
+ 8003d22:	60fb      	str	r3, [r7, #12]
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 8003d24:	683a      	ldr	r2, [r7, #0]
+ 8003d26:	68fb      	ldr	r3, [r7, #12]
+ 8003d28:	4313      	orrs	r3, r2
+ 8003d2a:	2207      	movs	r2, #7
+ 8003d2c:	4313      	orrs	r3, r2
+ 8003d2e:	60fb      	str	r3, [r7, #12]
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+ 8003d30:	687b      	ldr	r3, [r7, #4]
+ 8003d32:	68fa      	ldr	r2, [r7, #12]
+ 8003d34:	609a      	str	r2, [r3, #8]
+}
+ 8003d36:	46c0      	nop			; (mov r8, r8)
+ 8003d38:	46bd      	mov	sp, r7
+ 8003d3a:	b004      	add	sp, #16
+ 8003d3c:	bd80      	pop	{r7, pc}
+	...
+
+08003d40 <TIM_ETR_SetConfig>:
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                              uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ 8003d40:	b580      	push	{r7, lr}
+ 8003d42:	b086      	sub	sp, #24
+ 8003d44:	af00      	add	r7, sp, #0
+ 8003d46:	60f8      	str	r0, [r7, #12]
+ 8003d48:	60b9      	str	r1, [r7, #8]
+ 8003d4a:	607a      	str	r2, [r7, #4]
+ 8003d4c:	603b      	str	r3, [r7, #0]
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+ 8003d4e:	68fb      	ldr	r3, [r7, #12]
+ 8003d50:	689b      	ldr	r3, [r3, #8]
+ 8003d52:	617b      	str	r3, [r7, #20]
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8003d54:	697b      	ldr	r3, [r7, #20]
+ 8003d56:	4a09      	ldr	r2, [pc, #36]	; (8003d7c <TIM_ETR_SetConfig+0x3c>)
+ 8003d58:	4013      	ands	r3, r2
+ 8003d5a:	617b      	str	r3, [r7, #20]
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 8003d5c:	683b      	ldr	r3, [r7, #0]
+ 8003d5e:	021a      	lsls	r2, r3, #8
+ 8003d60:	687b      	ldr	r3, [r7, #4]
+ 8003d62:	431a      	orrs	r2, r3
+ 8003d64:	68bb      	ldr	r3, [r7, #8]
+ 8003d66:	4313      	orrs	r3, r2
+ 8003d68:	697a      	ldr	r2, [r7, #20]
+ 8003d6a:	4313      	orrs	r3, r2
+ 8003d6c:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+ 8003d6e:	68fb      	ldr	r3, [r7, #12]
+ 8003d70:	697a      	ldr	r2, [r7, #20]
+ 8003d72:	609a      	str	r2, [r3, #8]
+}
+ 8003d74:	46c0      	nop			; (mov r8, r8)
+ 8003d76:	46bd      	mov	sp, r7
+ 8003d78:	b006      	add	sp, #24
+ 8003d7a:	bd80      	pop	{r7, pc}
+ 8003d7c:	ffff00ff 	.word	0xffff00ff
+
+08003d80 <HAL_TIMEx_MasterConfigSynchronization>:
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ 8003d80:	b580      	push	{r7, lr}
+ 8003d82:	b084      	sub	sp, #16
+ 8003d84:	af00      	add	r7, sp, #0
+ 8003d86:	6078      	str	r0, [r7, #4]
+ 8003d88:	6039      	str	r1, [r7, #0]
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+ 8003d8a:	687b      	ldr	r3, [r7, #4]
+ 8003d8c:	2238      	movs	r2, #56	; 0x38
+ 8003d8e:	5c9b      	ldrb	r3, [r3, r2]
+ 8003d90:	2b01      	cmp	r3, #1
+ 8003d92:	d101      	bne.n	8003d98 <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 8003d94:	2302      	movs	r3, #2
+ 8003d96:	e03d      	b.n	8003e14 <HAL_TIMEx_MasterConfigSynchronization+0x94>
+ 8003d98:	687b      	ldr	r3, [r7, #4]
+ 8003d9a:	2238      	movs	r2, #56	; 0x38
+ 8003d9c:	2101      	movs	r1, #1
+ 8003d9e:	5499      	strb	r1, [r3, r2]
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8003da0:	687b      	ldr	r3, [r7, #4]
+ 8003da2:	2239      	movs	r2, #57	; 0x39
+ 8003da4:	2102      	movs	r1, #2
+ 8003da6:	5499      	strb	r1, [r3, r2]
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+ 8003da8:	687b      	ldr	r3, [r7, #4]
+ 8003daa:	681b      	ldr	r3, [r3, #0]
+ 8003dac:	685b      	ldr	r3, [r3, #4]
+ 8003dae:	60fb      	str	r3, [r7, #12]
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+ 8003db0:	687b      	ldr	r3, [r7, #4]
+ 8003db2:	681b      	ldr	r3, [r3, #0]
+ 8003db4:	689b      	ldr	r3, [r3, #8]
+ 8003db6:	60bb      	str	r3, [r7, #8]
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+ 8003db8:	68fb      	ldr	r3, [r7, #12]
+ 8003dba:	2270      	movs	r2, #112	; 0x70
+ 8003dbc:	4393      	bics	r3, r2
+ 8003dbe:	60fb      	str	r3, [r7, #12]
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+ 8003dc0:	683b      	ldr	r3, [r7, #0]
+ 8003dc2:	681b      	ldr	r3, [r3, #0]
+ 8003dc4:	68fa      	ldr	r2, [r7, #12]
+ 8003dc6:	4313      	orrs	r3, r2
+ 8003dc8:	60fb      	str	r3, [r7, #12]
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+ 8003dca:	687b      	ldr	r3, [r7, #4]
+ 8003dcc:	681b      	ldr	r3, [r3, #0]
+ 8003dce:	68fa      	ldr	r2, [r7, #12]
+ 8003dd0:	605a      	str	r2, [r3, #4]
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 8003dd2:	687b      	ldr	r3, [r7, #4]
+ 8003dd4:	681a      	ldr	r2, [r3, #0]
+ 8003dd6:	2380      	movs	r3, #128	; 0x80
+ 8003dd8:	05db      	lsls	r3, r3, #23
+ 8003dda:	429a      	cmp	r2, r3
+ 8003ddc:	d004      	beq.n	8003de8 <HAL_TIMEx_MasterConfigSynchronization+0x68>
+ 8003dde:	687b      	ldr	r3, [r7, #4]
+ 8003de0:	681b      	ldr	r3, [r3, #0]
+ 8003de2:	4a0e      	ldr	r2, [pc, #56]	; (8003e1c <HAL_TIMEx_MasterConfigSynchronization+0x9c>)
+ 8003de4:	4293      	cmp	r3, r2
+ 8003de6:	d10c      	bne.n	8003e02 <HAL_TIMEx_MasterConfigSynchronization+0x82>
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+ 8003de8:	68bb      	ldr	r3, [r7, #8]
+ 8003dea:	2280      	movs	r2, #128	; 0x80
+ 8003dec:	4393      	bics	r3, r2
+ 8003dee:	60bb      	str	r3, [r7, #8]
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+ 8003df0:	683b      	ldr	r3, [r7, #0]
+ 8003df2:	685b      	ldr	r3, [r3, #4]
+ 8003df4:	68ba      	ldr	r2, [r7, #8]
+ 8003df6:	4313      	orrs	r3, r2
+ 8003df8:	60bb      	str	r3, [r7, #8]
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+ 8003dfa:	687b      	ldr	r3, [r7, #4]
+ 8003dfc:	681b      	ldr	r3, [r3, #0]
+ 8003dfe:	68ba      	ldr	r2, [r7, #8]
+ 8003e00:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+ 8003e02:	687b      	ldr	r3, [r7, #4]
+ 8003e04:	2239      	movs	r2, #57	; 0x39
+ 8003e06:	2101      	movs	r1, #1
+ 8003e08:	5499      	strb	r1, [r3, r2]
+
+  __HAL_UNLOCK(htim);
+ 8003e0a:	687b      	ldr	r3, [r7, #4]
+ 8003e0c:	2238      	movs	r2, #56	; 0x38
+ 8003e0e:	2100      	movs	r1, #0
+ 8003e10:	5499      	strb	r1, [r3, r2]
+
+  return HAL_OK;
+ 8003e12:	2300      	movs	r3, #0
+}
+ 8003e14:	0018      	movs	r0, r3
+ 8003e16:	46bd      	mov	sp, r7
+ 8003e18:	b004      	add	sp, #16
+ 8003e1a:	bd80      	pop	{r7, pc}
+ 8003e1c:	40010800 	.word	0x40010800
+
+08003e20 <HAL_UART_Init>:
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ 8003e20:	b580      	push	{r7, lr}
+ 8003e22:	b082      	sub	sp, #8
+ 8003e24:	af00      	add	r7, sp, #0
+ 8003e26:	6078      	str	r0, [r7, #4]
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+ 8003e28:	687b      	ldr	r3, [r7, #4]
+ 8003e2a:	2b00      	cmp	r3, #0
+ 8003e2c:	d101      	bne.n	8003e32 <HAL_UART_Init+0x12>
+  {
+    return HAL_ERROR;
+ 8003e2e:	2301      	movs	r3, #1
+ 8003e30:	e044      	b.n	8003ebc <HAL_UART_Init+0x9c>
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+ 8003e32:	687b      	ldr	r3, [r7, #4]
+ 8003e34:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 8003e36:	2b00      	cmp	r3, #0
+ 8003e38:	d107      	bne.n	8003e4a <HAL_UART_Init+0x2a>
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+ 8003e3a:	687b      	ldr	r3, [r7, #4]
+ 8003e3c:	2274      	movs	r2, #116	; 0x74
+ 8003e3e:	2100      	movs	r1, #0
+ 8003e40:	5499      	strb	r1, [r3, r2]
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+ 8003e42:	687b      	ldr	r3, [r7, #4]
+ 8003e44:	0018      	movs	r0, r3
+ 8003e46:	f7fd fa3b 	bl	80012c0 <HAL_UART_MspInit>
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 8003e4a:	687b      	ldr	r3, [r7, #4]
+ 8003e4c:	2224      	movs	r2, #36	; 0x24
+ 8003e4e:	679a      	str	r2, [r3, #120]	; 0x78
+
+  __HAL_UART_DISABLE(huart);
+ 8003e50:	687b      	ldr	r3, [r7, #4]
+ 8003e52:	681b      	ldr	r3, [r3, #0]
+ 8003e54:	681a      	ldr	r2, [r3, #0]
+ 8003e56:	687b      	ldr	r3, [r7, #4]
+ 8003e58:	681b      	ldr	r3, [r3, #0]
+ 8003e5a:	2101      	movs	r1, #1
+ 8003e5c:	438a      	bics	r2, r1
+ 8003e5e:	601a      	str	r2, [r3, #0]
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+ 8003e60:	687b      	ldr	r3, [r7, #4]
+ 8003e62:	0018      	movs	r0, r3
+ 8003e64:	f000 fb26 	bl	80044b4 <UART_SetConfig>
+ 8003e68:	0003      	movs	r3, r0
+ 8003e6a:	2b01      	cmp	r3, #1
+ 8003e6c:	d101      	bne.n	8003e72 <HAL_UART_Init+0x52>
+  {
+    return HAL_ERROR;
+ 8003e6e:	2301      	movs	r3, #1
+ 8003e70:	e024      	b.n	8003ebc <HAL_UART_Init+0x9c>
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 8003e72:	687b      	ldr	r3, [r7, #4]
+ 8003e74:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8003e76:	2b00      	cmp	r3, #0
+ 8003e78:	d003      	beq.n	8003e82 <HAL_UART_Init+0x62>
+  {
+    UART_AdvFeatureConfig(huart);
+ 8003e7a:	687b      	ldr	r3, [r7, #4]
+ 8003e7c:	0018      	movs	r0, r3
+ 8003e7e:	f000 fd7b 	bl	8004978 <UART_AdvFeatureConfig>
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 8003e82:	687b      	ldr	r3, [r7, #4]
+ 8003e84:	681b      	ldr	r3, [r3, #0]
+ 8003e86:	685a      	ldr	r2, [r3, #4]
+ 8003e88:	687b      	ldr	r3, [r7, #4]
+ 8003e8a:	681b      	ldr	r3, [r3, #0]
+ 8003e8c:	490d      	ldr	r1, [pc, #52]	; (8003ec4 <HAL_UART_Init+0xa4>)
+ 8003e8e:	400a      	ands	r2, r1
+ 8003e90:	605a      	str	r2, [r3, #4]
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 8003e92:	687b      	ldr	r3, [r7, #4]
+ 8003e94:	681b      	ldr	r3, [r3, #0]
+ 8003e96:	689a      	ldr	r2, [r3, #8]
+ 8003e98:	687b      	ldr	r3, [r7, #4]
+ 8003e9a:	681b      	ldr	r3, [r3, #0]
+ 8003e9c:	212a      	movs	r1, #42	; 0x2a
+ 8003e9e:	438a      	bics	r2, r1
+ 8003ea0:	609a      	str	r2, [r3, #8]
+
+  __HAL_UART_ENABLE(huart);
+ 8003ea2:	687b      	ldr	r3, [r7, #4]
+ 8003ea4:	681b      	ldr	r3, [r3, #0]
+ 8003ea6:	681a      	ldr	r2, [r3, #0]
+ 8003ea8:	687b      	ldr	r3, [r7, #4]
+ 8003eaa:	681b      	ldr	r3, [r3, #0]
+ 8003eac:	2101      	movs	r1, #1
+ 8003eae:	430a      	orrs	r2, r1
+ 8003eb0:	601a      	str	r2, [r3, #0]
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+ 8003eb2:	687b      	ldr	r3, [r7, #4]
+ 8003eb4:	0018      	movs	r0, r3
+ 8003eb6:	f000 fe13 	bl	8004ae0 <UART_CheckIdleState>
+ 8003eba:	0003      	movs	r3, r0
+}
+ 8003ebc:	0018      	movs	r0, r3
+ 8003ebe:	46bd      	mov	sp, r7
+ 8003ec0:	b002      	add	sp, #8
+ 8003ec2:	bd80      	pop	{r7, pc}
+ 8003ec4:	ffffb7ff 	.word	0xffffb7ff
+
+08003ec8 <HAL_UART_IRQHandler>:
+  * @brief Handle UART interrupt request.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ 8003ec8:	b590      	push	{r4, r7, lr}
+ 8003eca:	b0ab      	sub	sp, #172	; 0xac
+ 8003ecc:	af00      	add	r7, sp, #0
+ 8003ece:	6078      	str	r0, [r7, #4]
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+ 8003ed0:	687b      	ldr	r3, [r7, #4]
+ 8003ed2:	681b      	ldr	r3, [r3, #0]
+ 8003ed4:	69db      	ldr	r3, [r3, #28]
+ 8003ed6:	22a4      	movs	r2, #164	; 0xa4
+ 8003ed8:	18b9      	adds	r1, r7, r2
+ 8003eda:	600b      	str	r3, [r1, #0]
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+ 8003edc:	687b      	ldr	r3, [r7, #4]
+ 8003ede:	681b      	ldr	r3, [r3, #0]
+ 8003ee0:	681b      	ldr	r3, [r3, #0]
+ 8003ee2:	20a0      	movs	r0, #160	; 0xa0
+ 8003ee4:	1839      	adds	r1, r7, r0
+ 8003ee6:	600b      	str	r3, [r1, #0]
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+ 8003ee8:	687b      	ldr	r3, [r7, #4]
+ 8003eea:	681b      	ldr	r3, [r3, #0]
+ 8003eec:	689b      	ldr	r3, [r3, #8]
+ 8003eee:	219c      	movs	r1, #156	; 0x9c
+ 8003ef0:	1879      	adds	r1, r7, r1
+ 8003ef2:	600b      	str	r3, [r1, #0]
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ 8003ef4:	0011      	movs	r1, r2
+ 8003ef6:	18bb      	adds	r3, r7, r2
+ 8003ef8:	681b      	ldr	r3, [r3, #0]
+ 8003efa:	4a99      	ldr	r2, [pc, #612]	; (8004160 <HAL_UART_IRQHandler+0x298>)
+ 8003efc:	4013      	ands	r3, r2
+ 8003efe:	2298      	movs	r2, #152	; 0x98
+ 8003f00:	18bc      	adds	r4, r7, r2
+ 8003f02:	6023      	str	r3, [r4, #0]
+  if (errorflags == 0U)
+ 8003f04:	18bb      	adds	r3, r7, r2
+ 8003f06:	681b      	ldr	r3, [r3, #0]
+ 8003f08:	2b00      	cmp	r3, #0
+ 8003f0a:	d114      	bne.n	8003f36 <HAL_UART_IRQHandler+0x6e>
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE) != 0U)
+ 8003f0c:	187b      	adds	r3, r7, r1
+ 8003f0e:	681b      	ldr	r3, [r3, #0]
+ 8003f10:	2220      	movs	r2, #32
+ 8003f12:	4013      	ands	r3, r2
+ 8003f14:	d00f      	beq.n	8003f36 <HAL_UART_IRQHandler+0x6e>
+        && ((cr1its & USART_CR1_RXNEIE) != 0U))
+ 8003f16:	183b      	adds	r3, r7, r0
+ 8003f18:	681b      	ldr	r3, [r3, #0]
+ 8003f1a:	2220      	movs	r2, #32
+ 8003f1c:	4013      	ands	r3, r2
+ 8003f1e:	d00a      	beq.n	8003f36 <HAL_UART_IRQHandler+0x6e>
+    {
+      if (huart->RxISR != NULL)
+ 8003f20:	687b      	ldr	r3, [r7, #4]
+ 8003f22:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 8003f24:	2b00      	cmp	r3, #0
+ 8003f26:	d100      	bne.n	8003f2a <HAL_UART_IRQHandler+0x62>
+ 8003f28:	e298      	b.n	800445c <HAL_UART_IRQHandler+0x594>
+      {
+        huart->RxISR(huart);
+ 8003f2a:	687b      	ldr	r3, [r7, #4]
+ 8003f2c:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 8003f2e:	687a      	ldr	r2, [r7, #4]
+ 8003f30:	0010      	movs	r0, r2
+ 8003f32:	4798      	blx	r3
+      }
+      return;
+ 8003f34:	e292      	b.n	800445c <HAL_UART_IRQHandler+0x594>
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+ 8003f36:	2398      	movs	r3, #152	; 0x98
+ 8003f38:	18fb      	adds	r3, r7, r3
+ 8003f3a:	681b      	ldr	r3, [r3, #0]
+ 8003f3c:	2b00      	cmp	r3, #0
+ 8003f3e:	d100      	bne.n	8003f42 <HAL_UART_IRQHandler+0x7a>
+ 8003f40:	e114      	b.n	800416c <HAL_UART_IRQHandler+0x2a4>
+      && (((cr3its & USART_CR3_EIE) != 0U)
+ 8003f42:	239c      	movs	r3, #156	; 0x9c
+ 8003f44:	18fb      	adds	r3, r7, r3
+ 8003f46:	681b      	ldr	r3, [r3, #0]
+ 8003f48:	2201      	movs	r2, #1
+ 8003f4a:	4013      	ands	r3, r2
+ 8003f4c:	d106      	bne.n	8003f5c <HAL_UART_IRQHandler+0x94>
+          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
+ 8003f4e:	23a0      	movs	r3, #160	; 0xa0
+ 8003f50:	18fb      	adds	r3, r7, r3
+ 8003f52:	681b      	ldr	r3, [r3, #0]
+ 8003f54:	4a83      	ldr	r2, [pc, #524]	; (8004164 <HAL_UART_IRQHandler+0x29c>)
+ 8003f56:	4013      	ands	r3, r2
+ 8003f58:	d100      	bne.n	8003f5c <HAL_UART_IRQHandler+0x94>
+ 8003f5a:	e107      	b.n	800416c <HAL_UART_IRQHandler+0x2a4>
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ 8003f5c:	23a4      	movs	r3, #164	; 0xa4
+ 8003f5e:	18fb      	adds	r3, r7, r3
+ 8003f60:	681b      	ldr	r3, [r3, #0]
+ 8003f62:	2201      	movs	r2, #1
+ 8003f64:	4013      	ands	r3, r2
+ 8003f66:	d012      	beq.n	8003f8e <HAL_UART_IRQHandler+0xc6>
+ 8003f68:	23a0      	movs	r3, #160	; 0xa0
+ 8003f6a:	18fb      	adds	r3, r7, r3
+ 8003f6c:	681a      	ldr	r2, [r3, #0]
+ 8003f6e:	2380      	movs	r3, #128	; 0x80
+ 8003f70:	005b      	lsls	r3, r3, #1
+ 8003f72:	4013      	ands	r3, r2
+ 8003f74:	d00b      	beq.n	8003f8e <HAL_UART_IRQHandler+0xc6>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+ 8003f76:	687b      	ldr	r3, [r7, #4]
+ 8003f78:	681b      	ldr	r3, [r3, #0]
+ 8003f7a:	2201      	movs	r2, #1
+ 8003f7c:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+ 8003f7e:	687b      	ldr	r3, [r7, #4]
+ 8003f80:	2280      	movs	r2, #128	; 0x80
+ 8003f82:	589b      	ldr	r3, [r3, r2]
+ 8003f84:	2201      	movs	r2, #1
+ 8003f86:	431a      	orrs	r2, r3
+ 8003f88:	687b      	ldr	r3, [r7, #4]
+ 8003f8a:	2180      	movs	r1, #128	; 0x80
+ 8003f8c:	505a      	str	r2, [r3, r1]
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 8003f8e:	23a4      	movs	r3, #164	; 0xa4
+ 8003f90:	18fb      	adds	r3, r7, r3
+ 8003f92:	681b      	ldr	r3, [r3, #0]
+ 8003f94:	2202      	movs	r2, #2
+ 8003f96:	4013      	ands	r3, r2
+ 8003f98:	d011      	beq.n	8003fbe <HAL_UART_IRQHandler+0xf6>
+ 8003f9a:	239c      	movs	r3, #156	; 0x9c
+ 8003f9c:	18fb      	adds	r3, r7, r3
+ 8003f9e:	681b      	ldr	r3, [r3, #0]
+ 8003fa0:	2201      	movs	r2, #1
+ 8003fa2:	4013      	ands	r3, r2
+ 8003fa4:	d00b      	beq.n	8003fbe <HAL_UART_IRQHandler+0xf6>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+ 8003fa6:	687b      	ldr	r3, [r7, #4]
+ 8003fa8:	681b      	ldr	r3, [r3, #0]
+ 8003faa:	2202      	movs	r2, #2
+ 8003fac:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+ 8003fae:	687b      	ldr	r3, [r7, #4]
+ 8003fb0:	2280      	movs	r2, #128	; 0x80
+ 8003fb2:	589b      	ldr	r3, [r3, r2]
+ 8003fb4:	2204      	movs	r2, #4
+ 8003fb6:	431a      	orrs	r2, r3
+ 8003fb8:	687b      	ldr	r3, [r7, #4]
+ 8003fba:	2180      	movs	r1, #128	; 0x80
+ 8003fbc:	505a      	str	r2, [r3, r1]
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 8003fbe:	23a4      	movs	r3, #164	; 0xa4
+ 8003fc0:	18fb      	adds	r3, r7, r3
+ 8003fc2:	681b      	ldr	r3, [r3, #0]
+ 8003fc4:	2204      	movs	r2, #4
+ 8003fc6:	4013      	ands	r3, r2
+ 8003fc8:	d011      	beq.n	8003fee <HAL_UART_IRQHandler+0x126>
+ 8003fca:	239c      	movs	r3, #156	; 0x9c
+ 8003fcc:	18fb      	adds	r3, r7, r3
+ 8003fce:	681b      	ldr	r3, [r3, #0]
+ 8003fd0:	2201      	movs	r2, #1
+ 8003fd2:	4013      	ands	r3, r2
+ 8003fd4:	d00b      	beq.n	8003fee <HAL_UART_IRQHandler+0x126>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+ 8003fd6:	687b      	ldr	r3, [r7, #4]
+ 8003fd8:	681b      	ldr	r3, [r3, #0]
+ 8003fda:	2204      	movs	r2, #4
+ 8003fdc:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+ 8003fde:	687b      	ldr	r3, [r7, #4]
+ 8003fe0:	2280      	movs	r2, #128	; 0x80
+ 8003fe2:	589b      	ldr	r3, [r3, r2]
+ 8003fe4:	2202      	movs	r2, #2
+ 8003fe6:	431a      	orrs	r2, r3
+ 8003fe8:	687b      	ldr	r3, [r7, #4]
+ 8003fea:	2180      	movs	r1, #128	; 0x80
+ 8003fec:	505a      	str	r2, [r3, r1]
+    }
+
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+ 8003fee:	23a4      	movs	r3, #164	; 0xa4
+ 8003ff0:	18fb      	adds	r3, r7, r3
+ 8003ff2:	681b      	ldr	r3, [r3, #0]
+ 8003ff4:	2208      	movs	r2, #8
+ 8003ff6:	4013      	ands	r3, r2
+ 8003ff8:	d017      	beq.n	800402a <HAL_UART_IRQHandler+0x162>
+        && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
+ 8003ffa:	23a0      	movs	r3, #160	; 0xa0
+ 8003ffc:	18fb      	adds	r3, r7, r3
+ 8003ffe:	681b      	ldr	r3, [r3, #0]
+ 8004000:	2220      	movs	r2, #32
+ 8004002:	4013      	ands	r3, r2
+ 8004004:	d105      	bne.n	8004012 <HAL_UART_IRQHandler+0x14a>
+            ((cr3its & USART_CR3_EIE) != 0U)))
+ 8004006:	239c      	movs	r3, #156	; 0x9c
+ 8004008:	18fb      	adds	r3, r7, r3
+ 800400a:	681b      	ldr	r3, [r3, #0]
+ 800400c:	2201      	movs	r2, #1
+ 800400e:	4013      	ands	r3, r2
+        && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
+ 8004010:	d00b      	beq.n	800402a <HAL_UART_IRQHandler+0x162>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ 8004012:	687b      	ldr	r3, [r7, #4]
+ 8004014:	681b      	ldr	r3, [r3, #0]
+ 8004016:	2208      	movs	r2, #8
+ 8004018:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ 800401a:	687b      	ldr	r3, [r7, #4]
+ 800401c:	2280      	movs	r2, #128	; 0x80
+ 800401e:	589b      	ldr	r3, [r3, r2]
+ 8004020:	2208      	movs	r2, #8
+ 8004022:	431a      	orrs	r2, r3
+ 8004024:	687b      	ldr	r3, [r7, #4]
+ 8004026:	2180      	movs	r1, #128	; 0x80
+ 8004028:	505a      	str	r2, [r3, r1]
+    }
+
+    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ 800402a:	23a4      	movs	r3, #164	; 0xa4
+ 800402c:	18fb      	adds	r3, r7, r3
+ 800402e:	681a      	ldr	r2, [r3, #0]
+ 8004030:	2380      	movs	r3, #128	; 0x80
+ 8004032:	011b      	lsls	r3, r3, #4
+ 8004034:	4013      	ands	r3, r2
+ 8004036:	d013      	beq.n	8004060 <HAL_UART_IRQHandler+0x198>
+ 8004038:	23a0      	movs	r3, #160	; 0xa0
+ 800403a:	18fb      	adds	r3, r7, r3
+ 800403c:	681a      	ldr	r2, [r3, #0]
+ 800403e:	2380      	movs	r3, #128	; 0x80
+ 8004040:	04db      	lsls	r3, r3, #19
+ 8004042:	4013      	ands	r3, r2
+ 8004044:	d00c      	beq.n	8004060 <HAL_UART_IRQHandler+0x198>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+ 8004046:	687b      	ldr	r3, [r7, #4]
+ 8004048:	681b      	ldr	r3, [r3, #0]
+ 800404a:	2280      	movs	r2, #128	; 0x80
+ 800404c:	0112      	lsls	r2, r2, #4
+ 800404e:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ 8004050:	687b      	ldr	r3, [r7, #4]
+ 8004052:	2280      	movs	r2, #128	; 0x80
+ 8004054:	589b      	ldr	r3, [r3, r2]
+ 8004056:	2220      	movs	r2, #32
+ 8004058:	431a      	orrs	r2, r3
+ 800405a:	687b      	ldr	r3, [r7, #4]
+ 800405c:	2180      	movs	r1, #128	; 0x80
+ 800405e:	505a      	str	r2, [r3, r1]
+    }
+
+    /* Call UART Error Call back function if need be ----------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ 8004060:	687b      	ldr	r3, [r7, #4]
+ 8004062:	2280      	movs	r2, #128	; 0x80
+ 8004064:	589b      	ldr	r3, [r3, r2]
+ 8004066:	2b00      	cmp	r3, #0
+ 8004068:	d100      	bne.n	800406c <HAL_UART_IRQHandler+0x1a4>
+ 800406a:	e1f9      	b.n	8004460 <HAL_UART_IRQHandler+0x598>
+    {
+      /* UART in mode Receiver --------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE) != 0U)
+ 800406c:	23a4      	movs	r3, #164	; 0xa4
+ 800406e:	18fb      	adds	r3, r7, r3
+ 8004070:	681b      	ldr	r3, [r3, #0]
+ 8004072:	2220      	movs	r2, #32
+ 8004074:	4013      	ands	r3, r2
+ 8004076:	d00e      	beq.n	8004096 <HAL_UART_IRQHandler+0x1ce>
+          && ((cr1its & USART_CR1_RXNEIE) != 0U))
+ 8004078:	23a0      	movs	r3, #160	; 0xa0
+ 800407a:	18fb      	adds	r3, r7, r3
+ 800407c:	681b      	ldr	r3, [r3, #0]
+ 800407e:	2220      	movs	r2, #32
+ 8004080:	4013      	ands	r3, r2
+ 8004082:	d008      	beq.n	8004096 <HAL_UART_IRQHandler+0x1ce>
+      {
+        if (huart->RxISR != NULL)
+ 8004084:	687b      	ldr	r3, [r7, #4]
+ 8004086:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 8004088:	2b00      	cmp	r3, #0
+ 800408a:	d004      	beq.n	8004096 <HAL_UART_IRQHandler+0x1ce>
+        {
+          huart->RxISR(huart);
+ 800408c:	687b      	ldr	r3, [r7, #4]
+ 800408e:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 8004090:	687a      	ldr	r2, [r7, #4]
+ 8004092:	0010      	movs	r0, r2
+ 8004094:	4798      	blx	r3
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = huart->ErrorCode;
+ 8004096:	687b      	ldr	r3, [r7, #4]
+ 8004098:	2280      	movs	r2, #128	; 0x80
+ 800409a:	589b      	ldr	r3, [r3, r2]
+ 800409c:	2194      	movs	r1, #148	; 0x94
+ 800409e:	187a      	adds	r2, r7, r1
+ 80040a0:	6013      	str	r3, [r2, #0]
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 80040a2:	687b      	ldr	r3, [r7, #4]
+ 80040a4:	681b      	ldr	r3, [r3, #0]
+ 80040a6:	689b      	ldr	r3, [r3, #8]
+ 80040a8:	2240      	movs	r2, #64	; 0x40
+ 80040aa:	4013      	ands	r3, r2
+ 80040ac:	2b40      	cmp	r3, #64	; 0x40
+ 80040ae:	d004      	beq.n	80040ba <HAL_UART_IRQHandler+0x1f2>
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ 80040b0:	187b      	adds	r3, r7, r1
+ 80040b2:	681b      	ldr	r3, [r3, #0]
+ 80040b4:	2228      	movs	r2, #40	; 0x28
+ 80040b6:	4013      	ands	r3, r2
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 80040b8:	d047      	beq.n	800414a <HAL_UART_IRQHandler+0x282>
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+ 80040ba:	687b      	ldr	r3, [r7, #4]
+ 80040bc:	0018      	movs	r0, r3
+ 80040be:	f000 fe1b 	bl	8004cf8 <UART_EndRxTransfer>
+
+        /* Disable the UART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 80040c2:	687b      	ldr	r3, [r7, #4]
+ 80040c4:	681b      	ldr	r3, [r3, #0]
+ 80040c6:	689b      	ldr	r3, [r3, #8]
+ 80040c8:	2240      	movs	r2, #64	; 0x40
+ 80040ca:	4013      	ands	r3, r2
+ 80040cc:	2b40      	cmp	r3, #64	; 0x40
+ 80040ce:	d137      	bne.n	8004140 <HAL_UART_IRQHandler+0x278>
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 80040d0:	f3ef 8310 	mrs	r3, PRIMASK
+ 80040d4:	663b      	str	r3, [r7, #96]	; 0x60
+  return(result);
+ 80040d6:	6e3b      	ldr	r3, [r7, #96]	; 0x60
+        {
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 80040d8:	2090      	movs	r0, #144	; 0x90
+ 80040da:	183a      	adds	r2, r7, r0
+ 80040dc:	6013      	str	r3, [r2, #0]
+ 80040de:	2301      	movs	r3, #1
+ 80040e0:	667b      	str	r3, [r7, #100]	; 0x64
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80040e2:	6e7b      	ldr	r3, [r7, #100]	; 0x64
+ 80040e4:	f383 8810 	msr	PRIMASK, r3
+}
+ 80040e8:	46c0      	nop			; (mov r8, r8)
+ 80040ea:	687b      	ldr	r3, [r7, #4]
+ 80040ec:	681b      	ldr	r3, [r3, #0]
+ 80040ee:	689a      	ldr	r2, [r3, #8]
+ 80040f0:	687b      	ldr	r3, [r7, #4]
+ 80040f2:	681b      	ldr	r3, [r3, #0]
+ 80040f4:	2140      	movs	r1, #64	; 0x40
+ 80040f6:	438a      	bics	r2, r1
+ 80040f8:	609a      	str	r2, [r3, #8]
+ 80040fa:	183b      	adds	r3, r7, r0
+ 80040fc:	681b      	ldr	r3, [r3, #0]
+ 80040fe:	66bb      	str	r3, [r7, #104]	; 0x68
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004100:	6ebb      	ldr	r3, [r7, #104]	; 0x68
+ 8004102:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004106:	46c0      	nop			; (mov r8, r8)
+
+          /* Abort the UART DMA Rx channel */
+          if (huart->hdmarx != NULL)
+ 8004108:	687b      	ldr	r3, [r7, #4]
+ 800410a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 800410c:	2b00      	cmp	r3, #0
+ 800410e:	d012      	beq.n	8004136 <HAL_UART_IRQHandler+0x26e>
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+ 8004110:	687b      	ldr	r3, [r7, #4]
+ 8004112:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8004114:	4a14      	ldr	r2, [pc, #80]	; (8004168 <HAL_UART_IRQHandler+0x2a0>)
+ 8004116:	639a      	str	r2, [r3, #56]	; 0x38
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ 8004118:	687b      	ldr	r3, [r7, #4]
+ 800411a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 800411c:	0018      	movs	r0, r3
+ 800411e:	f7fd ff8b 	bl	8002038 <HAL_DMA_Abort_IT>
+ 8004122:	1e03      	subs	r3, r0, #0
+ 8004124:	d01a      	beq.n	800415c <HAL_UART_IRQHandler+0x294>
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ 8004126:	687b      	ldr	r3, [r7, #4]
+ 8004128:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 800412a:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 800412c:	687b      	ldr	r3, [r7, #4]
+ 800412e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8004130:	0018      	movs	r0, r3
+ 8004132:	4790      	blx	r2
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8004134:	e012      	b.n	800415c <HAL_UART_IRQHandler+0x294>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+ 8004136:	687b      	ldr	r3, [r7, #4]
+ 8004138:	0018      	movs	r0, r3
+ 800413a:	f000 f9a7 	bl	800448c <HAL_UART_ErrorCallback>
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 800413e:	e00d      	b.n	800415c <HAL_UART_IRQHandler+0x294>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+ 8004140:	687b      	ldr	r3, [r7, #4]
+ 8004142:	0018      	movs	r0, r3
+ 8004144:	f000 f9a2 	bl	800448c <HAL_UART_ErrorCallback>
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8004148:	e008      	b.n	800415c <HAL_UART_IRQHandler+0x294>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+ 800414a:	687b      	ldr	r3, [r7, #4]
+ 800414c:	0018      	movs	r0, r3
+ 800414e:	f000 f99d 	bl	800448c <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004152:	687b      	ldr	r3, [r7, #4]
+ 8004154:	2280      	movs	r2, #128	; 0x80
+ 8004156:	2100      	movs	r1, #0
+ 8004158:	5099      	str	r1, [r3, r2]
+      }
+    }
+    return;
+ 800415a:	e181      	b.n	8004460 <HAL_UART_IRQHandler+0x598>
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 800415c:	46c0      	nop			; (mov r8, r8)
+    return;
+ 800415e:	e17f      	b.n	8004460 <HAL_UART_IRQHandler+0x598>
+ 8004160:	0000080f 	.word	0x0000080f
+ 8004164:	04000120 	.word	0x04000120
+ 8004168:	08004dbd 	.word	0x08004dbd
+
+  } /* End if some error occurs */
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : */
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 800416c:	687b      	ldr	r3, [r7, #4]
+ 800416e:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8004170:	2b01      	cmp	r3, #1
+ 8004172:	d000      	beq.n	8004176 <HAL_UART_IRQHandler+0x2ae>
+ 8004174:	e133      	b.n	80043de <HAL_UART_IRQHandler+0x516>
+      && ((isrflags & USART_ISR_IDLE) != 0U)
+ 8004176:	23a4      	movs	r3, #164	; 0xa4
+ 8004178:	18fb      	adds	r3, r7, r3
+ 800417a:	681b      	ldr	r3, [r3, #0]
+ 800417c:	2210      	movs	r2, #16
+ 800417e:	4013      	ands	r3, r2
+ 8004180:	d100      	bne.n	8004184 <HAL_UART_IRQHandler+0x2bc>
+ 8004182:	e12c      	b.n	80043de <HAL_UART_IRQHandler+0x516>
+      && ((cr1its & USART_ISR_IDLE) != 0U))
+ 8004184:	23a0      	movs	r3, #160	; 0xa0
+ 8004186:	18fb      	adds	r3, r7, r3
+ 8004188:	681b      	ldr	r3, [r3, #0]
+ 800418a:	2210      	movs	r2, #16
+ 800418c:	4013      	ands	r3, r2
+ 800418e:	d100      	bne.n	8004192 <HAL_UART_IRQHandler+0x2ca>
+ 8004190:	e125      	b.n	80043de <HAL_UART_IRQHandler+0x516>
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 8004192:	687b      	ldr	r3, [r7, #4]
+ 8004194:	681b      	ldr	r3, [r3, #0]
+ 8004196:	2210      	movs	r2, #16
+ 8004198:	621a      	str	r2, [r3, #32]
+
+    /* Check if DMA mode is enabled in UART */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 800419a:	687b      	ldr	r3, [r7, #4]
+ 800419c:	681b      	ldr	r3, [r3, #0]
+ 800419e:	689b      	ldr	r3, [r3, #8]
+ 80041a0:	2240      	movs	r2, #64	; 0x40
+ 80041a2:	4013      	ands	r3, r2
+ 80041a4:	2b40      	cmp	r3, #64	; 0x40
+ 80041a6:	d000      	beq.n	80041aa <HAL_UART_IRQHandler+0x2e2>
+ 80041a8:	e09d      	b.n	80042e6 <HAL_UART_IRQHandler+0x41e>
+    {
+      /* DMA mode enabled */
+      /* Check received length : If all expected data are received, do nothing,
+         (DMA cplt callback will be called).
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+ 80041aa:	687b      	ldr	r3, [r7, #4]
+ 80041ac:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80041ae:	681b      	ldr	r3, [r3, #0]
+ 80041b0:	685a      	ldr	r2, [r3, #4]
+ 80041b2:	217e      	movs	r1, #126	; 0x7e
+ 80041b4:	187b      	adds	r3, r7, r1
+ 80041b6:	801a      	strh	r2, [r3, #0]
+      if ((nb_remaining_rx_data > 0U)
+ 80041b8:	187b      	adds	r3, r7, r1
+ 80041ba:	881b      	ldrh	r3, [r3, #0]
+ 80041bc:	2b00      	cmp	r3, #0
+ 80041be:	d100      	bne.n	80041c2 <HAL_UART_IRQHandler+0x2fa>
+ 80041c0:	e150      	b.n	8004464 <HAL_UART_IRQHandler+0x59c>
+          && (nb_remaining_rx_data < huart->RxXferSize))
+ 80041c2:	687b      	ldr	r3, [r7, #4]
+ 80041c4:	2258      	movs	r2, #88	; 0x58
+ 80041c6:	5a9b      	ldrh	r3, [r3, r2]
+ 80041c8:	187a      	adds	r2, r7, r1
+ 80041ca:	8812      	ldrh	r2, [r2, #0]
+ 80041cc:	429a      	cmp	r2, r3
+ 80041ce:	d300      	bcc.n	80041d2 <HAL_UART_IRQHandler+0x30a>
+ 80041d0:	e148      	b.n	8004464 <HAL_UART_IRQHandler+0x59c>
+      {
+        /* Reception is not complete */
+        huart->RxXferCount = nb_remaining_rx_data;
+ 80041d2:	687b      	ldr	r3, [r7, #4]
+ 80041d4:	187a      	adds	r2, r7, r1
+ 80041d6:	215a      	movs	r1, #90	; 0x5a
+ 80041d8:	8812      	ldrh	r2, [r2, #0]
+ 80041da:	525a      	strh	r2, [r3, r1]
+
+        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+        if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ 80041dc:	687b      	ldr	r3, [r7, #4]
+ 80041de:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80041e0:	681b      	ldr	r3, [r3, #0]
+ 80041e2:	681b      	ldr	r3, [r3, #0]
+ 80041e4:	2220      	movs	r2, #32
+ 80041e6:	4013      	ands	r3, r2
+ 80041e8:	d16e      	bne.n	80042c8 <HAL_UART_IRQHandler+0x400>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 80041ea:	f3ef 8310 	mrs	r3, PRIMASK
+ 80041ee:	633b      	str	r3, [r7, #48]	; 0x30
+  return(result);
+ 80041f0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+        {
+          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ 80041f2:	67bb      	str	r3, [r7, #120]	; 0x78
+ 80041f4:	2301      	movs	r3, #1
+ 80041f6:	637b      	str	r3, [r7, #52]	; 0x34
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80041f8:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 80041fa:	f383 8810 	msr	PRIMASK, r3
+}
+ 80041fe:	46c0      	nop			; (mov r8, r8)
+ 8004200:	687b      	ldr	r3, [r7, #4]
+ 8004202:	681b      	ldr	r3, [r3, #0]
+ 8004204:	681a      	ldr	r2, [r3, #0]
+ 8004206:	687b      	ldr	r3, [r7, #4]
+ 8004208:	681b      	ldr	r3, [r3, #0]
+ 800420a:	499a      	ldr	r1, [pc, #616]	; (8004474 <HAL_UART_IRQHandler+0x5ac>)
+ 800420c:	400a      	ands	r2, r1
+ 800420e:	601a      	str	r2, [r3, #0]
+ 8004210:	6fbb      	ldr	r3, [r7, #120]	; 0x78
+ 8004212:	63bb      	str	r3, [r7, #56]	; 0x38
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004214:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8004216:	f383 8810 	msr	PRIMASK, r3
+}
+ 800421a:	46c0      	nop			; (mov r8, r8)
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 800421c:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004220:	63fb      	str	r3, [r7, #60]	; 0x3c
+  return(result);
+ 8004222:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004224:	677b      	str	r3, [r7, #116]	; 0x74
+ 8004226:	2301      	movs	r3, #1
+ 8004228:	643b      	str	r3, [r7, #64]	; 0x40
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 800422a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800422c:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004230:	46c0      	nop			; (mov r8, r8)
+ 8004232:	687b      	ldr	r3, [r7, #4]
+ 8004234:	681b      	ldr	r3, [r3, #0]
+ 8004236:	689a      	ldr	r2, [r3, #8]
+ 8004238:	687b      	ldr	r3, [r7, #4]
+ 800423a:	681b      	ldr	r3, [r3, #0]
+ 800423c:	2101      	movs	r1, #1
+ 800423e:	438a      	bics	r2, r1
+ 8004240:	609a      	str	r2, [r3, #8]
+ 8004242:	6f7b      	ldr	r3, [r7, #116]	; 0x74
+ 8004244:	647b      	str	r3, [r7, #68]	; 0x44
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004246:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 8004248:	f383 8810 	msr	PRIMASK, r3
+}
+ 800424c:	46c0      	nop			; (mov r8, r8)
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 800424e:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004252:	64bb      	str	r3, [r7, #72]	; 0x48
+  return(result);
+ 8004254:	6cbb      	ldr	r3, [r7, #72]	; 0x48
+
+          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+             in the UART CR3 register */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 8004256:	673b      	str	r3, [r7, #112]	; 0x70
+ 8004258:	2301      	movs	r3, #1
+ 800425a:	64fb      	str	r3, [r7, #76]	; 0x4c
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 800425c:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 800425e:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004262:	46c0      	nop			; (mov r8, r8)
+ 8004264:	687b      	ldr	r3, [r7, #4]
+ 8004266:	681b      	ldr	r3, [r3, #0]
+ 8004268:	689a      	ldr	r2, [r3, #8]
+ 800426a:	687b      	ldr	r3, [r7, #4]
+ 800426c:	681b      	ldr	r3, [r3, #0]
+ 800426e:	2140      	movs	r1, #64	; 0x40
+ 8004270:	438a      	bics	r2, r1
+ 8004272:	609a      	str	r2, [r3, #8]
+ 8004274:	6f3b      	ldr	r3, [r7, #112]	; 0x70
+ 8004276:	653b      	str	r3, [r7, #80]	; 0x50
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004278:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 800427a:	f383 8810 	msr	PRIMASK, r3
+}
+ 800427e:	46c0      	nop			; (mov r8, r8)
+
+          /* At end of Rx process, restore huart->RxState to Ready */
+          huart->RxState = HAL_UART_STATE_READY;
+ 8004280:	687b      	ldr	r3, [r7, #4]
+ 8004282:	2220      	movs	r2, #32
+ 8004284:	67da      	str	r2, [r3, #124]	; 0x7c
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 8004286:	687b      	ldr	r3, [r7, #4]
+ 8004288:	2200      	movs	r2, #0
+ 800428a:	661a      	str	r2, [r3, #96]	; 0x60
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 800428c:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004290:	657b      	str	r3, [r7, #84]	; 0x54
+  return(result);
+ 8004292:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 8004294:	66fb      	str	r3, [r7, #108]	; 0x6c
+ 8004296:	2301      	movs	r3, #1
+ 8004298:	65bb      	str	r3, [r7, #88]	; 0x58
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 800429a:	6dbb      	ldr	r3, [r7, #88]	; 0x58
+ 800429c:	f383 8810 	msr	PRIMASK, r3
+}
+ 80042a0:	46c0      	nop			; (mov r8, r8)
+ 80042a2:	687b      	ldr	r3, [r7, #4]
+ 80042a4:	681b      	ldr	r3, [r3, #0]
+ 80042a6:	681a      	ldr	r2, [r3, #0]
+ 80042a8:	687b      	ldr	r3, [r7, #4]
+ 80042aa:	681b      	ldr	r3, [r3, #0]
+ 80042ac:	2110      	movs	r1, #16
+ 80042ae:	438a      	bics	r2, r1
+ 80042b0:	601a      	str	r2, [r3, #0]
+ 80042b2:	6efb      	ldr	r3, [r7, #108]	; 0x6c
+ 80042b4:	65fb      	str	r3, [r7, #92]	; 0x5c
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80042b6:	6dfb      	ldr	r3, [r7, #92]	; 0x5c
+ 80042b8:	f383 8810 	msr	PRIMASK, r3
+}
+ 80042bc:	46c0      	nop			; (mov r8, r8)
+
+          /* Last bytes received, so no need as the abort is immediate */
+          (void)HAL_DMA_Abort(huart->hdmarx);
+ 80042be:	687b      	ldr	r3, [r7, #4]
+ 80042c0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80042c2:	0018      	movs	r0, r3
+ 80042c4:	f7fd fe78 	bl	8001fb8 <HAL_DMA_Abort>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+ 80042c8:	687b      	ldr	r3, [r7, #4]
+ 80042ca:	2258      	movs	r2, #88	; 0x58
+ 80042cc:	5a9a      	ldrh	r2, [r3, r2]
+ 80042ce:	687b      	ldr	r3, [r7, #4]
+ 80042d0:	215a      	movs	r1, #90	; 0x5a
+ 80042d2:	5a5b      	ldrh	r3, [r3, r1]
+ 80042d4:	b29b      	uxth	r3, r3
+ 80042d6:	1ad3      	subs	r3, r2, r3
+ 80042d8:	b29a      	uxth	r2, r3
+ 80042da:	687b      	ldr	r3, [r7, #4]
+ 80042dc:	0011      	movs	r1, r2
+ 80042de:	0018      	movs	r0, r3
+ 80042e0:	f000 f8dc 	bl	800449c <HAL_UARTEx_RxEventCallback>
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+ 80042e4:	e0be      	b.n	8004464 <HAL_UART_IRQHandler+0x59c>
+    else
+    {
+      /* DMA mode not enabled */
+      /* Check received length : If all expected data are received, do nothing.
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ 80042e6:	687b      	ldr	r3, [r7, #4]
+ 80042e8:	2258      	movs	r2, #88	; 0x58
+ 80042ea:	5a99      	ldrh	r1, [r3, r2]
+ 80042ec:	687b      	ldr	r3, [r7, #4]
+ 80042ee:	225a      	movs	r2, #90	; 0x5a
+ 80042f0:	5a9b      	ldrh	r3, [r3, r2]
+ 80042f2:	b29a      	uxth	r2, r3
+ 80042f4:	208e      	movs	r0, #142	; 0x8e
+ 80042f6:	183b      	adds	r3, r7, r0
+ 80042f8:	1a8a      	subs	r2, r1, r2
+ 80042fa:	801a      	strh	r2, [r3, #0]
+      if ((huart->RxXferCount > 0U)
+ 80042fc:	687b      	ldr	r3, [r7, #4]
+ 80042fe:	225a      	movs	r2, #90	; 0x5a
+ 8004300:	5a9b      	ldrh	r3, [r3, r2]
+ 8004302:	b29b      	uxth	r3, r3
+ 8004304:	2b00      	cmp	r3, #0
+ 8004306:	d100      	bne.n	800430a <HAL_UART_IRQHandler+0x442>
+ 8004308:	e0ae      	b.n	8004468 <HAL_UART_IRQHandler+0x5a0>
+          && (nb_rx_data > 0U))
+ 800430a:	183b      	adds	r3, r7, r0
+ 800430c:	881b      	ldrh	r3, [r3, #0]
+ 800430e:	2b00      	cmp	r3, #0
+ 8004310:	d100      	bne.n	8004314 <HAL_UART_IRQHandler+0x44c>
+ 8004312:	e0a9      	b.n	8004468 <HAL_UART_IRQHandler+0x5a0>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004314:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004318:	60fb      	str	r3, [r7, #12]
+  return(result);
+ 800431a:	68fb      	ldr	r3, [r7, #12]
+      {
+        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ 800431c:	2488      	movs	r4, #136	; 0x88
+ 800431e:	193a      	adds	r2, r7, r4
+ 8004320:	6013      	str	r3, [r2, #0]
+ 8004322:	2301      	movs	r3, #1
+ 8004324:	613b      	str	r3, [r7, #16]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004326:	693b      	ldr	r3, [r7, #16]
+ 8004328:	f383 8810 	msr	PRIMASK, r3
+}
+ 800432c:	46c0      	nop			; (mov r8, r8)
+ 800432e:	687b      	ldr	r3, [r7, #4]
+ 8004330:	681b      	ldr	r3, [r3, #0]
+ 8004332:	681a      	ldr	r2, [r3, #0]
+ 8004334:	687b      	ldr	r3, [r7, #4]
+ 8004336:	681b      	ldr	r3, [r3, #0]
+ 8004338:	494f      	ldr	r1, [pc, #316]	; (8004478 <HAL_UART_IRQHandler+0x5b0>)
+ 800433a:	400a      	ands	r2, r1
+ 800433c:	601a      	str	r2, [r3, #0]
+ 800433e:	193b      	adds	r3, r7, r4
+ 8004340:	681b      	ldr	r3, [r3, #0]
+ 8004342:	617b      	str	r3, [r7, #20]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004344:	697b      	ldr	r3, [r7, #20]
+ 8004346:	f383 8810 	msr	PRIMASK, r3
+}
+ 800434a:	46c0      	nop			; (mov r8, r8)
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 800434c:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004350:	61bb      	str	r3, [r7, #24]
+  return(result);
+ 8004352:	69bb      	ldr	r3, [r7, #24]
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004354:	2484      	movs	r4, #132	; 0x84
+ 8004356:	193a      	adds	r2, r7, r4
+ 8004358:	6013      	str	r3, [r2, #0]
+ 800435a:	2301      	movs	r3, #1
+ 800435c:	61fb      	str	r3, [r7, #28]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 800435e:	69fb      	ldr	r3, [r7, #28]
+ 8004360:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004364:	46c0      	nop			; (mov r8, r8)
+ 8004366:	687b      	ldr	r3, [r7, #4]
+ 8004368:	681b      	ldr	r3, [r3, #0]
+ 800436a:	689a      	ldr	r2, [r3, #8]
+ 800436c:	687b      	ldr	r3, [r7, #4]
+ 800436e:	681b      	ldr	r3, [r3, #0]
+ 8004370:	2101      	movs	r1, #1
+ 8004372:	438a      	bics	r2, r1
+ 8004374:	609a      	str	r2, [r3, #8]
+ 8004376:	193b      	adds	r3, r7, r4
+ 8004378:	681b      	ldr	r3, [r3, #0]
+ 800437a:	623b      	str	r3, [r7, #32]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 800437c:	6a3b      	ldr	r3, [r7, #32]
+ 800437e:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004382:	46c0      	nop			; (mov r8, r8)
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+ 8004384:	687b      	ldr	r3, [r7, #4]
+ 8004386:	2220      	movs	r2, #32
+ 8004388:	67da      	str	r2, [r3, #124]	; 0x7c
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 800438a:	687b      	ldr	r3, [r7, #4]
+ 800438c:	2200      	movs	r2, #0
+ 800438e:	661a      	str	r2, [r3, #96]	; 0x60
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+ 8004390:	687b      	ldr	r3, [r7, #4]
+ 8004392:	2200      	movs	r2, #0
+ 8004394:	665a      	str	r2, [r3, #100]	; 0x64
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004396:	f3ef 8310 	mrs	r3, PRIMASK
+ 800439a:	627b      	str	r3, [r7, #36]	; 0x24
+  return(result);
+ 800439c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 800439e:	2480      	movs	r4, #128	; 0x80
+ 80043a0:	193a      	adds	r2, r7, r4
+ 80043a2:	6013      	str	r3, [r2, #0]
+ 80043a4:	2301      	movs	r3, #1
+ 80043a6:	62bb      	str	r3, [r7, #40]	; 0x28
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80043a8:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80043aa:	f383 8810 	msr	PRIMASK, r3
+}
+ 80043ae:	46c0      	nop			; (mov r8, r8)
+ 80043b0:	687b      	ldr	r3, [r7, #4]
+ 80043b2:	681b      	ldr	r3, [r3, #0]
+ 80043b4:	681a      	ldr	r2, [r3, #0]
+ 80043b6:	687b      	ldr	r3, [r7, #4]
+ 80043b8:	681b      	ldr	r3, [r3, #0]
+ 80043ba:	2110      	movs	r1, #16
+ 80043bc:	438a      	bics	r2, r1
+ 80043be:	601a      	str	r2, [r3, #0]
+ 80043c0:	193b      	adds	r3, r7, r4
+ 80043c2:	681b      	ldr	r3, [r3, #0]
+ 80043c4:	62fb      	str	r3, [r7, #44]	; 0x2c
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80043c6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80043c8:	f383 8810 	msr	PRIMASK, r3
+}
+ 80043cc:	46c0      	nop			; (mov r8, r8)
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxEventCallback(huart, nb_rx_data);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+ 80043ce:	183b      	adds	r3, r7, r0
+ 80043d0:	881a      	ldrh	r2, [r3, #0]
+ 80043d2:	687b      	ldr	r3, [r7, #4]
+ 80043d4:	0011      	movs	r1, r2
+ 80043d6:	0018      	movs	r0, r3
+ 80043d8:	f000 f860 	bl	800449c <HAL_UARTEx_RxEventCallback>
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+ 80043dc:	e044      	b.n	8004468 <HAL_UART_IRQHandler+0x5a0>
+    }
+  }
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+ 80043de:	23a4      	movs	r3, #164	; 0xa4
+ 80043e0:	18fb      	adds	r3, r7, r3
+ 80043e2:	681a      	ldr	r2, [r3, #0]
+ 80043e4:	2380      	movs	r3, #128	; 0x80
+ 80043e6:	035b      	lsls	r3, r3, #13
+ 80043e8:	4013      	ands	r3, r2
+ 80043ea:	d010      	beq.n	800440e <HAL_UART_IRQHandler+0x546>
+ 80043ec:	239c      	movs	r3, #156	; 0x9c
+ 80043ee:	18fb      	adds	r3, r7, r3
+ 80043f0:	681a      	ldr	r2, [r3, #0]
+ 80043f2:	2380      	movs	r3, #128	; 0x80
+ 80043f4:	03db      	lsls	r3, r3, #15
+ 80043f6:	4013      	ands	r3, r2
+ 80043f8:	d009      	beq.n	800440e <HAL_UART_IRQHandler+0x546>
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+ 80043fa:	687b      	ldr	r3, [r7, #4]
+ 80043fc:	681b      	ldr	r3, [r3, #0]
+ 80043fe:	2280      	movs	r2, #128	; 0x80
+ 8004400:	0352      	lsls	r2, r2, #13
+ 8004402:	621a      	str	r2, [r3, #32]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Wakeup Callback */
+    huart->WakeupCallback(huart);
+#else
+    /* Call legacy weak Wakeup Callback */
+    HAL_UARTEx_WakeupCallback(huart);
+ 8004404:	687b      	ldr	r3, [r7, #4]
+ 8004406:	0018      	movs	r0, r3
+ 8004408:	f000 fd1a 	bl	8004e40 <HAL_UARTEx_WakeupCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+ 800440c:	e02f      	b.n	800446e <HAL_UART_IRQHandler+0x5a6>
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE) != 0U)
+ 800440e:	23a4      	movs	r3, #164	; 0xa4
+ 8004410:	18fb      	adds	r3, r7, r3
+ 8004412:	681b      	ldr	r3, [r3, #0]
+ 8004414:	2280      	movs	r2, #128	; 0x80
+ 8004416:	4013      	ands	r3, r2
+ 8004418:	d00f      	beq.n	800443a <HAL_UART_IRQHandler+0x572>
+      && ((cr1its & USART_CR1_TXEIE) != 0U))
+ 800441a:	23a0      	movs	r3, #160	; 0xa0
+ 800441c:	18fb      	adds	r3, r7, r3
+ 800441e:	681b      	ldr	r3, [r3, #0]
+ 8004420:	2280      	movs	r2, #128	; 0x80
+ 8004422:	4013      	ands	r3, r2
+ 8004424:	d009      	beq.n	800443a <HAL_UART_IRQHandler+0x572>
+  {
+    if (huart->TxISR != NULL)
+ 8004426:	687b      	ldr	r3, [r7, #4]
+ 8004428:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800442a:	2b00      	cmp	r3, #0
+ 800442c:	d01e      	beq.n	800446c <HAL_UART_IRQHandler+0x5a4>
+    {
+      huart->TxISR(huart);
+ 800442e:	687b      	ldr	r3, [r7, #4]
+ 8004430:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8004432:	687a      	ldr	r2, [r7, #4]
+ 8004434:	0010      	movs	r0, r2
+ 8004436:	4798      	blx	r3
+    }
+    return;
+ 8004438:	e018      	b.n	800446c <HAL_UART_IRQHandler+0x5a4>
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ 800443a:	23a4      	movs	r3, #164	; 0xa4
+ 800443c:	18fb      	adds	r3, r7, r3
+ 800443e:	681b      	ldr	r3, [r3, #0]
+ 8004440:	2240      	movs	r2, #64	; 0x40
+ 8004442:	4013      	ands	r3, r2
+ 8004444:	d013      	beq.n	800446e <HAL_UART_IRQHandler+0x5a6>
+ 8004446:	23a0      	movs	r3, #160	; 0xa0
+ 8004448:	18fb      	adds	r3, r7, r3
+ 800444a:	681b      	ldr	r3, [r3, #0]
+ 800444c:	2240      	movs	r2, #64	; 0x40
+ 800444e:	4013      	ands	r3, r2
+ 8004450:	d00d      	beq.n	800446e <HAL_UART_IRQHandler+0x5a6>
+  {
+    UART_EndTransmit_IT(huart);
+ 8004452:	687b      	ldr	r3, [r7, #4]
+ 8004454:	0018      	movs	r0, r3
+ 8004456:	f000 fcc8 	bl	8004dea <UART_EndTransmit_IT>
+    return;
+ 800445a:	e008      	b.n	800446e <HAL_UART_IRQHandler+0x5a6>
+      return;
+ 800445c:	46c0      	nop			; (mov r8, r8)
+ 800445e:	e006      	b.n	800446e <HAL_UART_IRQHandler+0x5a6>
+    return;
+ 8004460:	46c0      	nop			; (mov r8, r8)
+ 8004462:	e004      	b.n	800446e <HAL_UART_IRQHandler+0x5a6>
+      return;
+ 8004464:	46c0      	nop			; (mov r8, r8)
+ 8004466:	e002      	b.n	800446e <HAL_UART_IRQHandler+0x5a6>
+      return;
+ 8004468:	46c0      	nop			; (mov r8, r8)
+ 800446a:	e000      	b.n	800446e <HAL_UART_IRQHandler+0x5a6>
+    return;
+ 800446c:	46c0      	nop			; (mov r8, r8)
+  }
+
+}
+ 800446e:	46bd      	mov	sp, r7
+ 8004470:	b02b      	add	sp, #172	; 0xac
+ 8004472:	bd90      	pop	{r4, r7, pc}
+ 8004474:	fffffeff 	.word	0xfffffeff
+ 8004478:	fffffedf 	.word	0xfffffedf
+
+0800447c <HAL_UART_TxCpltCallback>:
+  * @brief Tx Transfer completed callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ 800447c:	b580      	push	{r7, lr}
+ 800447e:	b082      	sub	sp, #8
+ 8004480:	af00      	add	r7, sp, #0
+ 8004482:	6078      	str	r0, [r7, #4]
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_TxCpltCallback can be implemented in the user file.
+   */
+}
+ 8004484:	46c0      	nop			; (mov r8, r8)
+ 8004486:	46bd      	mov	sp, r7
+ 8004488:	b002      	add	sp, #8
+ 800448a:	bd80      	pop	{r7, pc}
+
+0800448c <HAL_UART_ErrorCallback>:
+  * @brief  UART error callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ 800448c:	b580      	push	{r7, lr}
+ 800448e:	b082      	sub	sp, #8
+ 8004490:	af00      	add	r7, sp, #0
+ 8004492:	6078      	str	r0, [r7, #4]
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+ 8004494:	46c0      	nop			; (mov r8, r8)
+ 8004496:	46bd      	mov	sp, r7
+ 8004498:	b002      	add	sp, #8
+ 800449a:	bd80      	pop	{r7, pc}
+
+0800449c <HAL_UARTEx_RxEventCallback>:
+  * @param  Size  Number of data available in application reception buffer (indicates a position in
+  *               reception buffer until which, data are available)
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+ 800449c:	b580      	push	{r7, lr}
+ 800449e:	b082      	sub	sp, #8
+ 80044a0:	af00      	add	r7, sp, #0
+ 80044a2:	6078      	str	r0, [r7, #4]
+ 80044a4:	000a      	movs	r2, r1
+ 80044a6:	1cbb      	adds	r3, r7, #2
+ 80044a8:	801a      	strh	r2, [r3, #0]
+  UNUSED(Size);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+   */
+}
+ 80044aa:	46c0      	nop			; (mov r8, r8)
+ 80044ac:	46bd      	mov	sp, r7
+ 80044ae:	b002      	add	sp, #8
+ 80044b0:	bd80      	pop	{r7, pc}
+	...
+
+080044b4 <UART_SetConfig>:
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ 80044b4:	b5b0      	push	{r4, r5, r7, lr}
+ 80044b6:	b08e      	sub	sp, #56	; 0x38
+ 80044b8:	af00      	add	r7, sp, #0
+ 80044ba:	61f8      	str	r0, [r7, #28]
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  UART_ClockSourceTypeDef clocksource;
+  uint32_t usartdiv;
+  HAL_StatusTypeDef ret               = HAL_OK;
+ 80044bc:	231a      	movs	r3, #26
+ 80044be:	2218      	movs	r2, #24
+ 80044c0:	4694      	mov	ip, r2
+ 80044c2:	44bc      	add	ip, r7
+ 80044c4:	4463      	add	r3, ip
+ 80044c6:	2200      	movs	r2, #0
+ 80044c8:	701a      	strb	r2, [r3, #0]
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ 80044ca:	69fb      	ldr	r3, [r7, #28]
+ 80044cc:	689a      	ldr	r2, [r3, #8]
+ 80044ce:	69fb      	ldr	r3, [r7, #28]
+ 80044d0:	691b      	ldr	r3, [r3, #16]
+ 80044d2:	431a      	orrs	r2, r3
+ 80044d4:	69fb      	ldr	r3, [r7, #28]
+ 80044d6:	695b      	ldr	r3, [r3, #20]
+ 80044d8:	431a      	orrs	r2, r3
+ 80044da:	69fb      	ldr	r3, [r7, #28]
+ 80044dc:	69db      	ldr	r3, [r3, #28]
+ 80044de:	4313      	orrs	r3, r2
+ 80044e0:	637b      	str	r3, [r7, #52]	; 0x34
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 80044e2:	69fb      	ldr	r3, [r7, #28]
+ 80044e4:	681b      	ldr	r3, [r3, #0]
+ 80044e6:	681b      	ldr	r3, [r3, #0]
+ 80044e8:	4abc      	ldr	r2, [pc, #752]	; (80047dc <UART_SetConfig+0x328>)
+ 80044ea:	4013      	ands	r3, r2
+ 80044ec:	0019      	movs	r1, r3
+ 80044ee:	69fb      	ldr	r3, [r7, #28]
+ 80044f0:	681b      	ldr	r3, [r3, #0]
+ 80044f2:	6b7a      	ldr	r2, [r7, #52]	; 0x34
+ 80044f4:	430a      	orrs	r2, r1
+ 80044f6:	601a      	str	r2, [r3, #0]
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+ 80044f8:	69fb      	ldr	r3, [r7, #28]
+ 80044fa:	681b      	ldr	r3, [r3, #0]
+ 80044fc:	685b      	ldr	r3, [r3, #4]
+ 80044fe:	4ab8      	ldr	r2, [pc, #736]	; (80047e0 <UART_SetConfig+0x32c>)
+ 8004500:	4013      	ands	r3, r2
+ 8004502:	0019      	movs	r1, r3
+ 8004504:	69fb      	ldr	r3, [r7, #28]
+ 8004506:	68da      	ldr	r2, [r3, #12]
+ 8004508:	69fb      	ldr	r3, [r7, #28]
+ 800450a:	681b      	ldr	r3, [r3, #0]
+ 800450c:	430a      	orrs	r2, r1
+ 800450e:	605a      	str	r2, [r3, #4]
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+ 8004510:	69fb      	ldr	r3, [r7, #28]
+ 8004512:	699b      	ldr	r3, [r3, #24]
+ 8004514:	637b      	str	r3, [r7, #52]	; 0x34
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+ 8004516:	69fb      	ldr	r3, [r7, #28]
+ 8004518:	681b      	ldr	r3, [r3, #0]
+ 800451a:	4ab2      	ldr	r2, [pc, #712]	; (80047e4 <UART_SetConfig+0x330>)
+ 800451c:	4293      	cmp	r3, r2
+ 800451e:	d004      	beq.n	800452a <UART_SetConfig+0x76>
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+ 8004520:	69fb      	ldr	r3, [r7, #28]
+ 8004522:	6a1b      	ldr	r3, [r3, #32]
+ 8004524:	6b7a      	ldr	r2, [r7, #52]	; 0x34
+ 8004526:	4313      	orrs	r3, r2
+ 8004528:	637b      	str	r3, [r7, #52]	; 0x34
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+ 800452a:	69fb      	ldr	r3, [r7, #28]
+ 800452c:	681b      	ldr	r3, [r3, #0]
+ 800452e:	689b      	ldr	r3, [r3, #8]
+ 8004530:	4aad      	ldr	r2, [pc, #692]	; (80047e8 <UART_SetConfig+0x334>)
+ 8004532:	4013      	ands	r3, r2
+ 8004534:	0019      	movs	r1, r3
+ 8004536:	69fb      	ldr	r3, [r7, #28]
+ 8004538:	681b      	ldr	r3, [r3, #0]
+ 800453a:	6b7a      	ldr	r2, [r7, #52]	; 0x34
+ 800453c:	430a      	orrs	r2, r1
+ 800453e:	609a      	str	r2, [r3, #8]
+
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+ 8004540:	69fb      	ldr	r3, [r7, #28]
+ 8004542:	681b      	ldr	r3, [r3, #0]
+ 8004544:	4aa9      	ldr	r2, [pc, #676]	; (80047ec <UART_SetConfig+0x338>)
+ 8004546:	4293      	cmp	r3, r2
+ 8004548:	d136      	bne.n	80045b8 <UART_SetConfig+0x104>
+ 800454a:	4ba9      	ldr	r3, [pc, #676]	; (80047f0 <UART_SetConfig+0x33c>)
+ 800454c:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 800454e:	220c      	movs	r2, #12
+ 8004550:	4013      	ands	r3, r2
+ 8004552:	2b0c      	cmp	r3, #12
+ 8004554:	d020      	beq.n	8004598 <UART_SetConfig+0xe4>
+ 8004556:	d827      	bhi.n	80045a8 <UART_SetConfig+0xf4>
+ 8004558:	2b08      	cmp	r3, #8
+ 800455a:	d00d      	beq.n	8004578 <UART_SetConfig+0xc4>
+ 800455c:	d824      	bhi.n	80045a8 <UART_SetConfig+0xf4>
+ 800455e:	2b00      	cmp	r3, #0
+ 8004560:	d002      	beq.n	8004568 <UART_SetConfig+0xb4>
+ 8004562:	2b04      	cmp	r3, #4
+ 8004564:	d010      	beq.n	8004588 <UART_SetConfig+0xd4>
+ 8004566:	e01f      	b.n	80045a8 <UART_SetConfig+0xf4>
+ 8004568:	231b      	movs	r3, #27
+ 800456a:	2218      	movs	r2, #24
+ 800456c:	4694      	mov	ip, r2
+ 800456e:	44bc      	add	ip, r7
+ 8004570:	4463      	add	r3, ip
+ 8004572:	2200      	movs	r2, #0
+ 8004574:	701a      	strb	r2, [r3, #0]
+ 8004576:	e06f      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 8004578:	231b      	movs	r3, #27
+ 800457a:	2218      	movs	r2, #24
+ 800457c:	4694      	mov	ip, r2
+ 800457e:	44bc      	add	ip, r7
+ 8004580:	4463      	add	r3, ip
+ 8004582:	2202      	movs	r2, #2
+ 8004584:	701a      	strb	r2, [r3, #0]
+ 8004586:	e067      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 8004588:	231b      	movs	r3, #27
+ 800458a:	2218      	movs	r2, #24
+ 800458c:	4694      	mov	ip, r2
+ 800458e:	44bc      	add	ip, r7
+ 8004590:	4463      	add	r3, ip
+ 8004592:	2204      	movs	r2, #4
+ 8004594:	701a      	strb	r2, [r3, #0]
+ 8004596:	e05f      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 8004598:	231b      	movs	r3, #27
+ 800459a:	2218      	movs	r2, #24
+ 800459c:	4694      	mov	ip, r2
+ 800459e:	44bc      	add	ip, r7
+ 80045a0:	4463      	add	r3, ip
+ 80045a2:	2208      	movs	r2, #8
+ 80045a4:	701a      	strb	r2, [r3, #0]
+ 80045a6:	e057      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 80045a8:	231b      	movs	r3, #27
+ 80045aa:	2218      	movs	r2, #24
+ 80045ac:	4694      	mov	ip, r2
+ 80045ae:	44bc      	add	ip, r7
+ 80045b0:	4463      	add	r3, ip
+ 80045b2:	2210      	movs	r2, #16
+ 80045b4:	701a      	strb	r2, [r3, #0]
+ 80045b6:	e04f      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 80045b8:	69fb      	ldr	r3, [r7, #28]
+ 80045ba:	681b      	ldr	r3, [r3, #0]
+ 80045bc:	4a89      	ldr	r2, [pc, #548]	; (80047e4 <UART_SetConfig+0x330>)
+ 80045be:	4293      	cmp	r3, r2
+ 80045c0:	d143      	bne.n	800464a <UART_SetConfig+0x196>
+ 80045c2:	4b8b      	ldr	r3, [pc, #556]	; (80047f0 <UART_SetConfig+0x33c>)
+ 80045c4:	6cda      	ldr	r2, [r3, #76]	; 0x4c
+ 80045c6:	23c0      	movs	r3, #192	; 0xc0
+ 80045c8:	011b      	lsls	r3, r3, #4
+ 80045ca:	4013      	ands	r3, r2
+ 80045cc:	22c0      	movs	r2, #192	; 0xc0
+ 80045ce:	0112      	lsls	r2, r2, #4
+ 80045d0:	4293      	cmp	r3, r2
+ 80045d2:	d02a      	beq.n	800462a <UART_SetConfig+0x176>
+ 80045d4:	22c0      	movs	r2, #192	; 0xc0
+ 80045d6:	0112      	lsls	r2, r2, #4
+ 80045d8:	4293      	cmp	r3, r2
+ 80045da:	d82e      	bhi.n	800463a <UART_SetConfig+0x186>
+ 80045dc:	2280      	movs	r2, #128	; 0x80
+ 80045de:	0112      	lsls	r2, r2, #4
+ 80045e0:	4293      	cmp	r3, r2
+ 80045e2:	d012      	beq.n	800460a <UART_SetConfig+0x156>
+ 80045e4:	2280      	movs	r2, #128	; 0x80
+ 80045e6:	0112      	lsls	r2, r2, #4
+ 80045e8:	4293      	cmp	r3, r2
+ 80045ea:	d826      	bhi.n	800463a <UART_SetConfig+0x186>
+ 80045ec:	2b00      	cmp	r3, #0
+ 80045ee:	d004      	beq.n	80045fa <UART_SetConfig+0x146>
+ 80045f0:	2280      	movs	r2, #128	; 0x80
+ 80045f2:	00d2      	lsls	r2, r2, #3
+ 80045f4:	4293      	cmp	r3, r2
+ 80045f6:	d010      	beq.n	800461a <UART_SetConfig+0x166>
+ 80045f8:	e01f      	b.n	800463a <UART_SetConfig+0x186>
+ 80045fa:	231b      	movs	r3, #27
+ 80045fc:	2218      	movs	r2, #24
+ 80045fe:	4694      	mov	ip, r2
+ 8004600:	44bc      	add	ip, r7
+ 8004602:	4463      	add	r3, ip
+ 8004604:	2200      	movs	r2, #0
+ 8004606:	701a      	strb	r2, [r3, #0]
+ 8004608:	e026      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 800460a:	231b      	movs	r3, #27
+ 800460c:	2218      	movs	r2, #24
+ 800460e:	4694      	mov	ip, r2
+ 8004610:	44bc      	add	ip, r7
+ 8004612:	4463      	add	r3, ip
+ 8004614:	2202      	movs	r2, #2
+ 8004616:	701a      	strb	r2, [r3, #0]
+ 8004618:	e01e      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 800461a:	231b      	movs	r3, #27
+ 800461c:	2218      	movs	r2, #24
+ 800461e:	4694      	mov	ip, r2
+ 8004620:	44bc      	add	ip, r7
+ 8004622:	4463      	add	r3, ip
+ 8004624:	2204      	movs	r2, #4
+ 8004626:	701a      	strb	r2, [r3, #0]
+ 8004628:	e016      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 800462a:	231b      	movs	r3, #27
+ 800462c:	2218      	movs	r2, #24
+ 800462e:	4694      	mov	ip, r2
+ 8004630:	44bc      	add	ip, r7
+ 8004632:	4463      	add	r3, ip
+ 8004634:	2208      	movs	r2, #8
+ 8004636:	701a      	strb	r2, [r3, #0]
+ 8004638:	e00e      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 800463a:	231b      	movs	r3, #27
+ 800463c:	2218      	movs	r2, #24
+ 800463e:	4694      	mov	ip, r2
+ 8004640:	44bc      	add	ip, r7
+ 8004642:	4463      	add	r3, ip
+ 8004644:	2210      	movs	r2, #16
+ 8004646:	701a      	strb	r2, [r3, #0]
+ 8004648:	e006      	b.n	8004658 <UART_SetConfig+0x1a4>
+ 800464a:	231b      	movs	r3, #27
+ 800464c:	2218      	movs	r2, #24
+ 800464e:	4694      	mov	ip, r2
+ 8004650:	44bc      	add	ip, r7
+ 8004652:	4463      	add	r3, ip
+ 8004654:	2210      	movs	r2, #16
+ 8004656:	701a      	strb	r2, [r3, #0]
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+ 8004658:	69fb      	ldr	r3, [r7, #28]
+ 800465a:	681b      	ldr	r3, [r3, #0]
+ 800465c:	4a61      	ldr	r2, [pc, #388]	; (80047e4 <UART_SetConfig+0x330>)
+ 800465e:	4293      	cmp	r3, r2
+ 8004660:	d000      	beq.n	8004664 <UART_SetConfig+0x1b0>
+ 8004662:	e088      	b.n	8004776 <UART_SetConfig+0x2c2>
+  {
+    /* Retrieve frequency clock */
+    switch (clocksource)
+ 8004664:	231b      	movs	r3, #27
+ 8004666:	2218      	movs	r2, #24
+ 8004668:	4694      	mov	ip, r2
+ 800466a:	44bc      	add	ip, r7
+ 800466c:	4463      	add	r3, ip
+ 800466e:	781b      	ldrb	r3, [r3, #0]
+ 8004670:	2b08      	cmp	r3, #8
+ 8004672:	d01d      	beq.n	80046b0 <UART_SetConfig+0x1fc>
+ 8004674:	dc20      	bgt.n	80046b8 <UART_SetConfig+0x204>
+ 8004676:	2b04      	cmp	r3, #4
+ 8004678:	d015      	beq.n	80046a6 <UART_SetConfig+0x1f2>
+ 800467a:	dc1d      	bgt.n	80046b8 <UART_SetConfig+0x204>
+ 800467c:	2b00      	cmp	r3, #0
+ 800467e:	d002      	beq.n	8004686 <UART_SetConfig+0x1d2>
+ 8004680:	2b02      	cmp	r3, #2
+ 8004682:	d005      	beq.n	8004690 <UART_SetConfig+0x1dc>
+ 8004684:	e018      	b.n	80046b8 <UART_SetConfig+0x204>
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 8004686:	f7fe fd7f 	bl	8003188 <HAL_RCC_GetPCLK1Freq>
+ 800468a:	0003      	movs	r3, r0
+ 800468c:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 800468e:	e01d      	b.n	80046cc <UART_SetConfig+0x218>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 8004690:	4b57      	ldr	r3, [pc, #348]	; (80047f0 <UART_SetConfig+0x33c>)
+ 8004692:	681b      	ldr	r3, [r3, #0]
+ 8004694:	2210      	movs	r2, #16
+ 8004696:	4013      	ands	r3, r2
+ 8004698:	d002      	beq.n	80046a0 <UART_SetConfig+0x1ec>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> 2U);
+ 800469a:	4b56      	ldr	r3, [pc, #344]	; (80047f4 <UART_SetConfig+0x340>)
+ 800469c:	62fb      	str	r3, [r7, #44]	; 0x2c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 800469e:	e015      	b.n	80046cc <UART_SetConfig+0x218>
+          pclk = (uint32_t) HSI_VALUE;
+ 80046a0:	4b55      	ldr	r3, [pc, #340]	; (80047f8 <UART_SetConfig+0x344>)
+ 80046a2:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80046a4:	e012      	b.n	80046cc <UART_SetConfig+0x218>
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+ 80046a6:	f7fe fcbf 	bl	8003028 <HAL_RCC_GetSysClockFreq>
+ 80046aa:	0003      	movs	r3, r0
+ 80046ac:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80046ae:	e00d      	b.n	80046cc <UART_SetConfig+0x218>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 80046b0:	2380      	movs	r3, #128	; 0x80
+ 80046b2:	021b      	lsls	r3, r3, #8
+ 80046b4:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80046b6:	e009      	b.n	80046cc <UART_SetConfig+0x218>
+      default:
+        pclk = 0U;
+ 80046b8:	2300      	movs	r3, #0
+ 80046ba:	62fb      	str	r3, [r7, #44]	; 0x2c
+        ret = HAL_ERROR;
+ 80046bc:	231a      	movs	r3, #26
+ 80046be:	2218      	movs	r2, #24
+ 80046c0:	4694      	mov	ip, r2
+ 80046c2:	44bc      	add	ip, r7
+ 80046c4:	4463      	add	r3, ip
+ 80046c6:	2201      	movs	r2, #1
+ 80046c8:	701a      	strb	r2, [r3, #0]
+        break;
+ 80046ca:	46c0      	nop			; (mov r8, r8)
+    }
+
+    /* If proper clock source reported */
+    if (pclk != 0U)
+ 80046cc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80046ce:	2b00      	cmp	r3, #0
+ 80046d0:	d100      	bne.n	80046d4 <UART_SetConfig+0x220>
+ 80046d2:	e139      	b.n	8004948 <UART_SetConfig+0x494>
+    {
+      /* No Prescaler applicable */
+      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((pclk < (3U * huart->Init.BaudRate)) ||
+ 80046d4:	69fb      	ldr	r3, [r7, #28]
+ 80046d6:	685a      	ldr	r2, [r3, #4]
+ 80046d8:	0013      	movs	r3, r2
+ 80046da:	005b      	lsls	r3, r3, #1
+ 80046dc:	189b      	adds	r3, r3, r2
+ 80046de:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80046e0:	429a      	cmp	r2, r3
+ 80046e2:	d305      	bcc.n	80046f0 <UART_SetConfig+0x23c>
+          (pclk > (4096U * huart->Init.BaudRate)))
+ 80046e4:	69fb      	ldr	r3, [r7, #28]
+ 80046e6:	685b      	ldr	r3, [r3, #4]
+ 80046e8:	031b      	lsls	r3, r3, #12
+      if ((pclk < (3U * huart->Init.BaudRate)) ||
+ 80046ea:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80046ec:	429a      	cmp	r2, r3
+ 80046ee:	d907      	bls.n	8004700 <UART_SetConfig+0x24c>
+      {
+        ret = HAL_ERROR;
+ 80046f0:	231a      	movs	r3, #26
+ 80046f2:	2218      	movs	r2, #24
+ 80046f4:	4694      	mov	ip, r2
+ 80046f6:	44bc      	add	ip, r7
+ 80046f8:	4463      	add	r3, ip
+ 80046fa:	2201      	movs	r2, #1
+ 80046fc:	701a      	strb	r2, [r3, #0]
+ 80046fe:	e123      	b.n	8004948 <UART_SetConfig+0x494>
+      }
+      else
+      {
+        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
+ 8004700:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8004702:	613b      	str	r3, [r7, #16]
+ 8004704:	2300      	movs	r3, #0
+ 8004706:	617b      	str	r3, [r7, #20]
+ 8004708:	6939      	ldr	r1, [r7, #16]
+ 800470a:	697a      	ldr	r2, [r7, #20]
+ 800470c:	000b      	movs	r3, r1
+ 800470e:	0e1b      	lsrs	r3, r3, #24
+ 8004710:	0010      	movs	r0, r2
+ 8004712:	0205      	lsls	r5, r0, #8
+ 8004714:	431d      	orrs	r5, r3
+ 8004716:	000b      	movs	r3, r1
+ 8004718:	021c      	lsls	r4, r3, #8
+ 800471a:	69fb      	ldr	r3, [r7, #28]
+ 800471c:	685b      	ldr	r3, [r3, #4]
+ 800471e:	085b      	lsrs	r3, r3, #1
+ 8004720:	60bb      	str	r3, [r7, #8]
+ 8004722:	2300      	movs	r3, #0
+ 8004724:	60fb      	str	r3, [r7, #12]
+ 8004726:	68b8      	ldr	r0, [r7, #8]
+ 8004728:	68f9      	ldr	r1, [r7, #12]
+ 800472a:	1900      	adds	r0, r0, r4
+ 800472c:	4169      	adcs	r1, r5
+ 800472e:	69fb      	ldr	r3, [r7, #28]
+ 8004730:	685b      	ldr	r3, [r3, #4]
+ 8004732:	603b      	str	r3, [r7, #0]
+ 8004734:	2300      	movs	r3, #0
+ 8004736:	607b      	str	r3, [r7, #4]
+ 8004738:	683a      	ldr	r2, [r7, #0]
+ 800473a:	687b      	ldr	r3, [r7, #4]
+ 800473c:	f7fb fd70 	bl	8000220 <__aeabi_uldivmod>
+ 8004740:	0002      	movs	r2, r0
+ 8004742:	000b      	movs	r3, r1
+ 8004744:	0013      	movs	r3, r2
+ 8004746:	62bb      	str	r3, [r7, #40]	; 0x28
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+ 8004748:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 800474a:	23c0      	movs	r3, #192	; 0xc0
+ 800474c:	009b      	lsls	r3, r3, #2
+ 800474e:	429a      	cmp	r2, r3
+ 8004750:	d309      	bcc.n	8004766 <UART_SetConfig+0x2b2>
+ 8004752:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8004754:	2380      	movs	r3, #128	; 0x80
+ 8004756:	035b      	lsls	r3, r3, #13
+ 8004758:	429a      	cmp	r2, r3
+ 800475a:	d204      	bcs.n	8004766 <UART_SetConfig+0x2b2>
+        {
+          huart->Instance->BRR = usartdiv;
+ 800475c:	69fb      	ldr	r3, [r7, #28]
+ 800475e:	681b      	ldr	r3, [r3, #0]
+ 8004760:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8004762:	60da      	str	r2, [r3, #12]
+ 8004764:	e0f0      	b.n	8004948 <UART_SetConfig+0x494>
+        }
+        else
+        {
+          ret = HAL_ERROR;
+ 8004766:	231a      	movs	r3, #26
+ 8004768:	2218      	movs	r2, #24
+ 800476a:	4694      	mov	ip, r2
+ 800476c:	44bc      	add	ip, r7
+ 800476e:	4463      	add	r3, ip
+ 8004770:	2201      	movs	r2, #1
+ 8004772:	701a      	strb	r2, [r3, #0]
+ 8004774:	e0e8      	b.n	8004948 <UART_SetConfig+0x494>
+        }
+      } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
+    } /* if (pclk != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 8004776:	69fb      	ldr	r3, [r7, #28]
+ 8004778:	69da      	ldr	r2, [r3, #28]
+ 800477a:	2380      	movs	r3, #128	; 0x80
+ 800477c:	021b      	lsls	r3, r3, #8
+ 800477e:	429a      	cmp	r2, r3
+ 8004780:	d000      	beq.n	8004784 <UART_SetConfig+0x2d0>
+ 8004782:	e087      	b.n	8004894 <UART_SetConfig+0x3e0>
+  {
+    switch (clocksource)
+ 8004784:	231b      	movs	r3, #27
+ 8004786:	2218      	movs	r2, #24
+ 8004788:	4694      	mov	ip, r2
+ 800478a:	44bc      	add	ip, r7
+ 800478c:	4463      	add	r3, ip
+ 800478e:	781b      	ldrb	r3, [r3, #0]
+ 8004790:	2b08      	cmp	r3, #8
+ 8004792:	d835      	bhi.n	8004800 <UART_SetConfig+0x34c>
+ 8004794:	009a      	lsls	r2, r3, #2
+ 8004796:	4b19      	ldr	r3, [pc, #100]	; (80047fc <UART_SetConfig+0x348>)
+ 8004798:	18d3      	adds	r3, r2, r3
+ 800479a:	681b      	ldr	r3, [r3, #0]
+ 800479c:	469f      	mov	pc, r3
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 800479e:	f7fe fcf3 	bl	8003188 <HAL_RCC_GetPCLK1Freq>
+ 80047a2:	0003      	movs	r3, r0
+ 80047a4:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80047a6:	e035      	b.n	8004814 <UART_SetConfig+0x360>
+      case UART_CLOCKSOURCE_PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+ 80047a8:	f7fe fd04 	bl	80031b4 <HAL_RCC_GetPCLK2Freq>
+ 80047ac:	0003      	movs	r3, r0
+ 80047ae:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80047b0:	e030      	b.n	8004814 <UART_SetConfig+0x360>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 80047b2:	4b0f      	ldr	r3, [pc, #60]	; (80047f0 <UART_SetConfig+0x33c>)
+ 80047b4:	681b      	ldr	r3, [r3, #0]
+ 80047b6:	2210      	movs	r2, #16
+ 80047b8:	4013      	ands	r3, r2
+ 80047ba:	d002      	beq.n	80047c2 <UART_SetConfig+0x30e>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> 2U);
+ 80047bc:	4b0d      	ldr	r3, [pc, #52]	; (80047f4 <UART_SetConfig+0x340>)
+ 80047be:	62fb      	str	r3, [r7, #44]	; 0x2c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 80047c0:	e028      	b.n	8004814 <UART_SetConfig+0x360>
+          pclk = (uint32_t) HSI_VALUE;
+ 80047c2:	4b0d      	ldr	r3, [pc, #52]	; (80047f8 <UART_SetConfig+0x344>)
+ 80047c4:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80047c6:	e025      	b.n	8004814 <UART_SetConfig+0x360>
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+ 80047c8:	f7fe fc2e 	bl	8003028 <HAL_RCC_GetSysClockFreq>
+ 80047cc:	0003      	movs	r3, r0
+ 80047ce:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80047d0:	e020      	b.n	8004814 <UART_SetConfig+0x360>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 80047d2:	2380      	movs	r3, #128	; 0x80
+ 80047d4:	021b      	lsls	r3, r3, #8
+ 80047d6:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80047d8:	e01c      	b.n	8004814 <UART_SetConfig+0x360>
+ 80047da:	46c0      	nop			; (mov r8, r8)
+ 80047dc:	efff69f3 	.word	0xefff69f3
+ 80047e0:	ffffcfff 	.word	0xffffcfff
+ 80047e4:	40004800 	.word	0x40004800
+ 80047e8:	fffff4ff 	.word	0xfffff4ff
+ 80047ec:	40004400 	.word	0x40004400
+ 80047f0:	40021000 	.word	0x40021000
+ 80047f4:	003d0900 	.word	0x003d0900
+ 80047f8:	00f42400 	.word	0x00f42400
+ 80047fc:	080078a8 	.word	0x080078a8
+      default:
+        pclk = 0U;
+ 8004800:	2300      	movs	r3, #0
+ 8004802:	62fb      	str	r3, [r7, #44]	; 0x2c
+        ret = HAL_ERROR;
+ 8004804:	231a      	movs	r3, #26
+ 8004806:	2218      	movs	r2, #24
+ 8004808:	4694      	mov	ip, r2
+ 800480a:	44bc      	add	ip, r7
+ 800480c:	4463      	add	r3, ip
+ 800480e:	2201      	movs	r2, #1
+ 8004810:	701a      	strb	r2, [r3, #0]
+        break;
+ 8004812:	46c0      	nop			; (mov r8, r8)
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if (pclk != 0U)
+ 8004814:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8004816:	2b00      	cmp	r3, #0
+ 8004818:	d100      	bne.n	800481c <UART_SetConfig+0x368>
+ 800481a:	e095      	b.n	8004948 <UART_SetConfig+0x494>
+    {
+      usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
+ 800481c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800481e:	005a      	lsls	r2, r3, #1
+ 8004820:	69fb      	ldr	r3, [r7, #28]
+ 8004822:	685b      	ldr	r3, [r3, #4]
+ 8004824:	085b      	lsrs	r3, r3, #1
+ 8004826:	18d2      	adds	r2, r2, r3
+ 8004828:	69fb      	ldr	r3, [r7, #28]
+ 800482a:	685b      	ldr	r3, [r3, #4]
+ 800482c:	0019      	movs	r1, r3
+ 800482e:	0010      	movs	r0, r2
+ 8004830:	f7fb fc6a 	bl	8000108 <__udivsi3>
+ 8004834:	0003      	movs	r3, r0
+ 8004836:	b29b      	uxth	r3, r3
+ 8004838:	62bb      	str	r3, [r7, #40]	; 0x28
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 800483a:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800483c:	2b0f      	cmp	r3, #15
+ 800483e:	d921      	bls.n	8004884 <UART_SetConfig+0x3d0>
+ 8004840:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8004842:	2380      	movs	r3, #128	; 0x80
+ 8004844:	025b      	lsls	r3, r3, #9
+ 8004846:	429a      	cmp	r2, r3
+ 8004848:	d21c      	bcs.n	8004884 <UART_SetConfig+0x3d0>
+      {
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ 800484a:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800484c:	b29a      	uxth	r2, r3
+ 800484e:	200e      	movs	r0, #14
+ 8004850:	2418      	movs	r4, #24
+ 8004852:	193b      	adds	r3, r7, r4
+ 8004854:	181b      	adds	r3, r3, r0
+ 8004856:	210f      	movs	r1, #15
+ 8004858:	438a      	bics	r2, r1
+ 800485a:	801a      	strh	r2, [r3, #0]
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 800485c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800485e:	085b      	lsrs	r3, r3, #1
+ 8004860:	b29b      	uxth	r3, r3
+ 8004862:	2207      	movs	r2, #7
+ 8004864:	4013      	ands	r3, r2
+ 8004866:	b299      	uxth	r1, r3
+ 8004868:	193b      	adds	r3, r7, r4
+ 800486a:	181b      	adds	r3, r3, r0
+ 800486c:	193a      	adds	r2, r7, r4
+ 800486e:	1812      	adds	r2, r2, r0
+ 8004870:	8812      	ldrh	r2, [r2, #0]
+ 8004872:	430a      	orrs	r2, r1
+ 8004874:	801a      	strh	r2, [r3, #0]
+        huart->Instance->BRR = brrtemp;
+ 8004876:	69fb      	ldr	r3, [r7, #28]
+ 8004878:	681b      	ldr	r3, [r3, #0]
+ 800487a:	193a      	adds	r2, r7, r4
+ 800487c:	1812      	adds	r2, r2, r0
+ 800487e:	8812      	ldrh	r2, [r2, #0]
+ 8004880:	60da      	str	r2, [r3, #12]
+ 8004882:	e061      	b.n	8004948 <UART_SetConfig+0x494>
+      }
+      else
+      {
+        ret = HAL_ERROR;
+ 8004884:	231a      	movs	r3, #26
+ 8004886:	2218      	movs	r2, #24
+ 8004888:	4694      	mov	ip, r2
+ 800488a:	44bc      	add	ip, r7
+ 800488c:	4463      	add	r3, ip
+ 800488e:	2201      	movs	r2, #1
+ 8004890:	701a      	strb	r2, [r3, #0]
+ 8004892:	e059      	b.n	8004948 <UART_SetConfig+0x494>
+      }
+    }
+  }
+  else
+  {
+    switch (clocksource)
+ 8004894:	231b      	movs	r3, #27
+ 8004896:	2218      	movs	r2, #24
+ 8004898:	4694      	mov	ip, r2
+ 800489a:	44bc      	add	ip, r7
+ 800489c:	4463      	add	r3, ip
+ 800489e:	781b      	ldrb	r3, [r3, #0]
+ 80048a0:	2b08      	cmp	r3, #8
+ 80048a2:	d822      	bhi.n	80048ea <UART_SetConfig+0x436>
+ 80048a4:	009a      	lsls	r2, r3, #2
+ 80048a6:	4b30      	ldr	r3, [pc, #192]	; (8004968 <UART_SetConfig+0x4b4>)
+ 80048a8:	18d3      	adds	r3, r2, r3
+ 80048aa:	681b      	ldr	r3, [r3, #0]
+ 80048ac:	469f      	mov	pc, r3
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 80048ae:	f7fe fc6b 	bl	8003188 <HAL_RCC_GetPCLK1Freq>
+ 80048b2:	0003      	movs	r3, r0
+ 80048b4:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80048b6:	e022      	b.n	80048fe <UART_SetConfig+0x44a>
+      case UART_CLOCKSOURCE_PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+ 80048b8:	f7fe fc7c 	bl	80031b4 <HAL_RCC_GetPCLK2Freq>
+ 80048bc:	0003      	movs	r3, r0
+ 80048be:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80048c0:	e01d      	b.n	80048fe <UART_SetConfig+0x44a>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 80048c2:	4b2a      	ldr	r3, [pc, #168]	; (800496c <UART_SetConfig+0x4b8>)
+ 80048c4:	681b      	ldr	r3, [r3, #0]
+ 80048c6:	2210      	movs	r2, #16
+ 80048c8:	4013      	ands	r3, r2
+ 80048ca:	d002      	beq.n	80048d2 <UART_SetConfig+0x41e>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> 2U);
+ 80048cc:	4b28      	ldr	r3, [pc, #160]	; (8004970 <UART_SetConfig+0x4bc>)
+ 80048ce:	62fb      	str	r3, [r7, #44]	; 0x2c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 80048d0:	e015      	b.n	80048fe <UART_SetConfig+0x44a>
+          pclk = (uint32_t) HSI_VALUE;
+ 80048d2:	4b28      	ldr	r3, [pc, #160]	; (8004974 <UART_SetConfig+0x4c0>)
+ 80048d4:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80048d6:	e012      	b.n	80048fe <UART_SetConfig+0x44a>
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+ 80048d8:	f7fe fba6 	bl	8003028 <HAL_RCC_GetSysClockFreq>
+ 80048dc:	0003      	movs	r3, r0
+ 80048de:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80048e0:	e00d      	b.n	80048fe <UART_SetConfig+0x44a>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 80048e2:	2380      	movs	r3, #128	; 0x80
+ 80048e4:	021b      	lsls	r3, r3, #8
+ 80048e6:	62fb      	str	r3, [r7, #44]	; 0x2c
+        break;
+ 80048e8:	e009      	b.n	80048fe <UART_SetConfig+0x44a>
+      default:
+        pclk = 0U;
+ 80048ea:	2300      	movs	r3, #0
+ 80048ec:	62fb      	str	r3, [r7, #44]	; 0x2c
+        ret = HAL_ERROR;
+ 80048ee:	231a      	movs	r3, #26
+ 80048f0:	2218      	movs	r2, #24
+ 80048f2:	4694      	mov	ip, r2
+ 80048f4:	44bc      	add	ip, r7
+ 80048f6:	4463      	add	r3, ip
+ 80048f8:	2201      	movs	r2, #1
+ 80048fa:	701a      	strb	r2, [r3, #0]
+        break;
+ 80048fc:	46c0      	nop			; (mov r8, r8)
+    }
+
+    if (pclk != 0U)
+ 80048fe:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8004900:	2b00      	cmp	r3, #0
+ 8004902:	d021      	beq.n	8004948 <UART_SetConfig+0x494>
+    {
+      /* USARTDIV must be greater than or equal to 0d16 */
+      usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
+ 8004904:	69fb      	ldr	r3, [r7, #28]
+ 8004906:	685b      	ldr	r3, [r3, #4]
+ 8004908:	085a      	lsrs	r2, r3, #1
+ 800490a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800490c:	18d2      	adds	r2, r2, r3
+ 800490e:	69fb      	ldr	r3, [r7, #28]
+ 8004910:	685b      	ldr	r3, [r3, #4]
+ 8004912:	0019      	movs	r1, r3
+ 8004914:	0010      	movs	r0, r2
+ 8004916:	f7fb fbf7 	bl	8000108 <__udivsi3>
+ 800491a:	0003      	movs	r3, r0
+ 800491c:	b29b      	uxth	r3, r3
+ 800491e:	62bb      	str	r3, [r7, #40]	; 0x28
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 8004920:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8004922:	2b0f      	cmp	r3, #15
+ 8004924:	d909      	bls.n	800493a <UART_SetConfig+0x486>
+ 8004926:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8004928:	2380      	movs	r3, #128	; 0x80
+ 800492a:	025b      	lsls	r3, r3, #9
+ 800492c:	429a      	cmp	r2, r3
+ 800492e:	d204      	bcs.n	800493a <UART_SetConfig+0x486>
+      {
+        huart->Instance->BRR = usartdiv;
+ 8004930:	69fb      	ldr	r3, [r7, #28]
+ 8004932:	681b      	ldr	r3, [r3, #0]
+ 8004934:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8004936:	60da      	str	r2, [r3, #12]
+ 8004938:	e006      	b.n	8004948 <UART_SetConfig+0x494>
+      }
+      else
+      {
+        ret = HAL_ERROR;
+ 800493a:	231a      	movs	r3, #26
+ 800493c:	2218      	movs	r2, #24
+ 800493e:	4694      	mov	ip, r2
+ 8004940:	44bc      	add	ip, r7
+ 8004942:	4463      	add	r3, ip
+ 8004944:	2201      	movs	r2, #1
+ 8004946:	701a      	strb	r2, [r3, #0]
+    }
+  }
+
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+ 8004948:	69fb      	ldr	r3, [r7, #28]
+ 800494a:	2200      	movs	r2, #0
+ 800494c:	665a      	str	r2, [r3, #100]	; 0x64
+  huart->TxISR = NULL;
+ 800494e:	69fb      	ldr	r3, [r7, #28]
+ 8004950:	2200      	movs	r2, #0
+ 8004952:	669a      	str	r2, [r3, #104]	; 0x68
+
+  return ret;
+ 8004954:	231a      	movs	r3, #26
+ 8004956:	2218      	movs	r2, #24
+ 8004958:	4694      	mov	ip, r2
+ 800495a:	44bc      	add	ip, r7
+ 800495c:	4463      	add	r3, ip
+ 800495e:	781b      	ldrb	r3, [r3, #0]
+}
+ 8004960:	0018      	movs	r0, r3
+ 8004962:	46bd      	mov	sp, r7
+ 8004964:	b00e      	add	sp, #56	; 0x38
+ 8004966:	bdb0      	pop	{r4, r5, r7, pc}
+ 8004968:	080078cc 	.word	0x080078cc
+ 800496c:	40021000 	.word	0x40021000
+ 8004970:	003d0900 	.word	0x003d0900
+ 8004974:	00f42400 	.word	0x00f42400
+
+08004978 <UART_AdvFeatureConfig>:
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ 8004978:	b580      	push	{r7, lr}
+ 800497a:	b082      	sub	sp, #8
+ 800497c:	af00      	add	r7, sp, #0
+ 800497e:	6078      	str	r0, [r7, #4]
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ 8004980:	687b      	ldr	r3, [r7, #4]
+ 8004982:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8004984:	2201      	movs	r2, #1
+ 8004986:	4013      	ands	r3, r2
+ 8004988:	d00b      	beq.n	80049a2 <UART_AdvFeatureConfig+0x2a>
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ 800498a:	687b      	ldr	r3, [r7, #4]
+ 800498c:	681b      	ldr	r3, [r3, #0]
+ 800498e:	685b      	ldr	r3, [r3, #4]
+ 8004990:	4a4a      	ldr	r2, [pc, #296]	; (8004abc <UART_AdvFeatureConfig+0x144>)
+ 8004992:	4013      	ands	r3, r2
+ 8004994:	0019      	movs	r1, r3
+ 8004996:	687b      	ldr	r3, [r7, #4]
+ 8004998:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 800499a:	687b      	ldr	r3, [r7, #4]
+ 800499c:	681b      	ldr	r3, [r3, #0]
+ 800499e:	430a      	orrs	r2, r1
+ 80049a0:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ 80049a2:	687b      	ldr	r3, [r7, #4]
+ 80049a4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80049a6:	2202      	movs	r2, #2
+ 80049a8:	4013      	ands	r3, r2
+ 80049aa:	d00b      	beq.n	80049c4 <UART_AdvFeatureConfig+0x4c>
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ 80049ac:	687b      	ldr	r3, [r7, #4]
+ 80049ae:	681b      	ldr	r3, [r3, #0]
+ 80049b0:	685b      	ldr	r3, [r3, #4]
+ 80049b2:	4a43      	ldr	r2, [pc, #268]	; (8004ac0 <UART_AdvFeatureConfig+0x148>)
+ 80049b4:	4013      	ands	r3, r2
+ 80049b6:	0019      	movs	r1, r3
+ 80049b8:	687b      	ldr	r3, [r7, #4]
+ 80049ba:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80049bc:	687b      	ldr	r3, [r7, #4]
+ 80049be:	681b      	ldr	r3, [r3, #0]
+ 80049c0:	430a      	orrs	r2, r1
+ 80049c2:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ 80049c4:	687b      	ldr	r3, [r7, #4]
+ 80049c6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80049c8:	2204      	movs	r2, #4
+ 80049ca:	4013      	ands	r3, r2
+ 80049cc:	d00b      	beq.n	80049e6 <UART_AdvFeatureConfig+0x6e>
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ 80049ce:	687b      	ldr	r3, [r7, #4]
+ 80049d0:	681b      	ldr	r3, [r3, #0]
+ 80049d2:	685b      	ldr	r3, [r3, #4]
+ 80049d4:	4a3b      	ldr	r2, [pc, #236]	; (8004ac4 <UART_AdvFeatureConfig+0x14c>)
+ 80049d6:	4013      	ands	r3, r2
+ 80049d8:	0019      	movs	r1, r3
+ 80049da:	687b      	ldr	r3, [r7, #4]
+ 80049dc:	6b1a      	ldr	r2, [r3, #48]	; 0x30
+ 80049de:	687b      	ldr	r3, [r7, #4]
+ 80049e0:	681b      	ldr	r3, [r3, #0]
+ 80049e2:	430a      	orrs	r2, r1
+ 80049e4:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ 80049e6:	687b      	ldr	r3, [r7, #4]
+ 80049e8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80049ea:	2208      	movs	r2, #8
+ 80049ec:	4013      	ands	r3, r2
+ 80049ee:	d00b      	beq.n	8004a08 <UART_AdvFeatureConfig+0x90>
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ 80049f0:	687b      	ldr	r3, [r7, #4]
+ 80049f2:	681b      	ldr	r3, [r3, #0]
+ 80049f4:	685b      	ldr	r3, [r3, #4]
+ 80049f6:	4a34      	ldr	r2, [pc, #208]	; (8004ac8 <UART_AdvFeatureConfig+0x150>)
+ 80049f8:	4013      	ands	r3, r2
+ 80049fa:	0019      	movs	r1, r3
+ 80049fc:	687b      	ldr	r3, [r7, #4]
+ 80049fe:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8004a00:	687b      	ldr	r3, [r7, #4]
+ 8004a02:	681b      	ldr	r3, [r3, #0]
+ 8004a04:	430a      	orrs	r2, r1
+ 8004a06:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ 8004a08:	687b      	ldr	r3, [r7, #4]
+ 8004a0a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8004a0c:	2210      	movs	r2, #16
+ 8004a0e:	4013      	ands	r3, r2
+ 8004a10:	d00b      	beq.n	8004a2a <UART_AdvFeatureConfig+0xb2>
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ 8004a12:	687b      	ldr	r3, [r7, #4]
+ 8004a14:	681b      	ldr	r3, [r3, #0]
+ 8004a16:	689b      	ldr	r3, [r3, #8]
+ 8004a18:	4a2c      	ldr	r2, [pc, #176]	; (8004acc <UART_AdvFeatureConfig+0x154>)
+ 8004a1a:	4013      	ands	r3, r2
+ 8004a1c:	0019      	movs	r1, r3
+ 8004a1e:	687b      	ldr	r3, [r7, #4]
+ 8004a20:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8004a22:	687b      	ldr	r3, [r7, #4]
+ 8004a24:	681b      	ldr	r3, [r3, #0]
+ 8004a26:	430a      	orrs	r2, r1
+ 8004a28:	609a      	str	r2, [r3, #8]
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ 8004a2a:	687b      	ldr	r3, [r7, #4]
+ 8004a2c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8004a2e:	2220      	movs	r2, #32
+ 8004a30:	4013      	ands	r3, r2
+ 8004a32:	d00b      	beq.n	8004a4c <UART_AdvFeatureConfig+0xd4>
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ 8004a34:	687b      	ldr	r3, [r7, #4]
+ 8004a36:	681b      	ldr	r3, [r3, #0]
+ 8004a38:	689b      	ldr	r3, [r3, #8]
+ 8004a3a:	4a25      	ldr	r2, [pc, #148]	; (8004ad0 <UART_AdvFeatureConfig+0x158>)
+ 8004a3c:	4013      	ands	r3, r2
+ 8004a3e:	0019      	movs	r1, r3
+ 8004a40:	687b      	ldr	r3, [r7, #4]
+ 8004a42:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 8004a44:	687b      	ldr	r3, [r7, #4]
+ 8004a46:	681b      	ldr	r3, [r3, #0]
+ 8004a48:	430a      	orrs	r2, r1
+ 8004a4a:	609a      	str	r2, [r3, #8]
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ 8004a4c:	687b      	ldr	r3, [r7, #4]
+ 8004a4e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8004a50:	2240      	movs	r2, #64	; 0x40
+ 8004a52:	4013      	ands	r3, r2
+ 8004a54:	d01d      	beq.n	8004a92 <UART_AdvFeatureConfig+0x11a>
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ 8004a56:	687b      	ldr	r3, [r7, #4]
+ 8004a58:	681b      	ldr	r3, [r3, #0]
+ 8004a5a:	685b      	ldr	r3, [r3, #4]
+ 8004a5c:	4a1d      	ldr	r2, [pc, #116]	; (8004ad4 <UART_AdvFeatureConfig+0x15c>)
+ 8004a5e:	4013      	ands	r3, r2
+ 8004a60:	0019      	movs	r1, r3
+ 8004a62:	687b      	ldr	r3, [r7, #4]
+ 8004a64:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+ 8004a66:	687b      	ldr	r3, [r7, #4]
+ 8004a68:	681b      	ldr	r3, [r3, #0]
+ 8004a6a:	430a      	orrs	r2, r1
+ 8004a6c:	605a      	str	r2, [r3, #4]
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ 8004a6e:	687b      	ldr	r3, [r7, #4]
+ 8004a70:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+ 8004a72:	2380      	movs	r3, #128	; 0x80
+ 8004a74:	035b      	lsls	r3, r3, #13
+ 8004a76:	429a      	cmp	r2, r3
+ 8004a78:	d10b      	bne.n	8004a92 <UART_AdvFeatureConfig+0x11a>
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ 8004a7a:	687b      	ldr	r3, [r7, #4]
+ 8004a7c:	681b      	ldr	r3, [r3, #0]
+ 8004a7e:	685b      	ldr	r3, [r3, #4]
+ 8004a80:	4a15      	ldr	r2, [pc, #84]	; (8004ad8 <UART_AdvFeatureConfig+0x160>)
+ 8004a82:	4013      	ands	r3, r2
+ 8004a84:	0019      	movs	r1, r3
+ 8004a86:	687b      	ldr	r3, [r7, #4]
+ 8004a88:	6c5a      	ldr	r2, [r3, #68]	; 0x44
+ 8004a8a:	687b      	ldr	r3, [r7, #4]
+ 8004a8c:	681b      	ldr	r3, [r3, #0]
+ 8004a8e:	430a      	orrs	r2, r1
+ 8004a90:	605a      	str	r2, [r3, #4]
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ 8004a92:	687b      	ldr	r3, [r7, #4]
+ 8004a94:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8004a96:	2280      	movs	r2, #128	; 0x80
+ 8004a98:	4013      	ands	r3, r2
+ 8004a9a:	d00b      	beq.n	8004ab4 <UART_AdvFeatureConfig+0x13c>
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ 8004a9c:	687b      	ldr	r3, [r7, #4]
+ 8004a9e:	681b      	ldr	r3, [r3, #0]
+ 8004aa0:	685b      	ldr	r3, [r3, #4]
+ 8004aa2:	4a0e      	ldr	r2, [pc, #56]	; (8004adc <UART_AdvFeatureConfig+0x164>)
+ 8004aa4:	4013      	ands	r3, r2
+ 8004aa6:	0019      	movs	r1, r3
+ 8004aa8:	687b      	ldr	r3, [r7, #4]
+ 8004aaa:	6c9a      	ldr	r2, [r3, #72]	; 0x48
+ 8004aac:	687b      	ldr	r3, [r7, #4]
+ 8004aae:	681b      	ldr	r3, [r3, #0]
+ 8004ab0:	430a      	orrs	r2, r1
+ 8004ab2:	605a      	str	r2, [r3, #4]
+  }
+}
+ 8004ab4:	46c0      	nop			; (mov r8, r8)
+ 8004ab6:	46bd      	mov	sp, r7
+ 8004ab8:	b002      	add	sp, #8
+ 8004aba:	bd80      	pop	{r7, pc}
+ 8004abc:	fffdffff 	.word	0xfffdffff
+ 8004ac0:	fffeffff 	.word	0xfffeffff
+ 8004ac4:	fffbffff 	.word	0xfffbffff
+ 8004ac8:	ffff7fff 	.word	0xffff7fff
+ 8004acc:	ffffefff 	.word	0xffffefff
+ 8004ad0:	ffffdfff 	.word	0xffffdfff
+ 8004ad4:	ffefffff 	.word	0xffefffff
+ 8004ad8:	ff9fffff 	.word	0xff9fffff
+ 8004adc:	fff7ffff 	.word	0xfff7ffff
+
+08004ae0 <UART_CheckIdleState>:
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ 8004ae0:	b580      	push	{r7, lr}
+ 8004ae2:	b086      	sub	sp, #24
+ 8004ae4:	af02      	add	r7, sp, #8
+ 8004ae6:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004ae8:	687b      	ldr	r3, [r7, #4]
+ 8004aea:	2280      	movs	r2, #128	; 0x80
+ 8004aec:	2100      	movs	r1, #0
+ 8004aee:	5099      	str	r1, [r3, r2]
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+ 8004af0:	f7fc fe52 	bl	8001798 <HAL_GetTick>
+ 8004af4:	0003      	movs	r3, r0
+ 8004af6:	60fb      	str	r3, [r7, #12]
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ 8004af8:	687b      	ldr	r3, [r7, #4]
+ 8004afa:	681b      	ldr	r3, [r3, #0]
+ 8004afc:	681b      	ldr	r3, [r3, #0]
+ 8004afe:	2208      	movs	r2, #8
+ 8004b00:	4013      	ands	r3, r2
+ 8004b02:	2b08      	cmp	r3, #8
+ 8004b04:	d10c      	bne.n	8004b20 <UART_CheckIdleState+0x40>
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 8004b06:	68fb      	ldr	r3, [r7, #12]
+ 8004b08:	2280      	movs	r2, #128	; 0x80
+ 8004b0a:	0391      	lsls	r1, r2, #14
+ 8004b0c:	6878      	ldr	r0, [r7, #4]
+ 8004b0e:	4a17      	ldr	r2, [pc, #92]	; (8004b6c <UART_CheckIdleState+0x8c>)
+ 8004b10:	9200      	str	r2, [sp, #0]
+ 8004b12:	2200      	movs	r2, #0
+ 8004b14:	f000 f82c 	bl	8004b70 <UART_WaitOnFlagUntilTimeout>
+ 8004b18:	1e03      	subs	r3, r0, #0
+ 8004b1a:	d001      	beq.n	8004b20 <UART_CheckIdleState+0x40>
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+ 8004b1c:	2303      	movs	r3, #3
+ 8004b1e:	e021      	b.n	8004b64 <UART_CheckIdleState+0x84>
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ 8004b20:	687b      	ldr	r3, [r7, #4]
+ 8004b22:	681b      	ldr	r3, [r3, #0]
+ 8004b24:	681b      	ldr	r3, [r3, #0]
+ 8004b26:	2204      	movs	r2, #4
+ 8004b28:	4013      	ands	r3, r2
+ 8004b2a:	2b04      	cmp	r3, #4
+ 8004b2c:	d10c      	bne.n	8004b48 <UART_CheckIdleState+0x68>
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 8004b2e:	68fb      	ldr	r3, [r7, #12]
+ 8004b30:	2280      	movs	r2, #128	; 0x80
+ 8004b32:	03d1      	lsls	r1, r2, #15
+ 8004b34:	6878      	ldr	r0, [r7, #4]
+ 8004b36:	4a0d      	ldr	r2, [pc, #52]	; (8004b6c <UART_CheckIdleState+0x8c>)
+ 8004b38:	9200      	str	r2, [sp, #0]
+ 8004b3a:	2200      	movs	r2, #0
+ 8004b3c:	f000 f818 	bl	8004b70 <UART_WaitOnFlagUntilTimeout>
+ 8004b40:	1e03      	subs	r3, r0, #0
+ 8004b42:	d001      	beq.n	8004b48 <UART_CheckIdleState+0x68>
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+ 8004b44:	2303      	movs	r3, #3
+ 8004b46:	e00d      	b.n	8004b64 <UART_CheckIdleState+0x84>
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+ 8004b48:	687b      	ldr	r3, [r7, #4]
+ 8004b4a:	2220      	movs	r2, #32
+ 8004b4c:	679a      	str	r2, [r3, #120]	; 0x78
+  huart->RxState = HAL_UART_STATE_READY;
+ 8004b4e:	687b      	ldr	r3, [r7, #4]
+ 8004b50:	2220      	movs	r2, #32
+ 8004b52:	67da      	str	r2, [r3, #124]	; 0x7c
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 8004b54:	687b      	ldr	r3, [r7, #4]
+ 8004b56:	2200      	movs	r2, #0
+ 8004b58:	661a      	str	r2, [r3, #96]	; 0x60
+
+  __HAL_UNLOCK(huart);
+ 8004b5a:	687b      	ldr	r3, [r7, #4]
+ 8004b5c:	2274      	movs	r2, #116	; 0x74
+ 8004b5e:	2100      	movs	r1, #0
+ 8004b60:	5499      	strb	r1, [r3, r2]
+
+  return HAL_OK;
+ 8004b62:	2300      	movs	r3, #0
+}
+ 8004b64:	0018      	movs	r0, r3
+ 8004b66:	46bd      	mov	sp, r7
+ 8004b68:	b004      	add	sp, #16
+ 8004b6a:	bd80      	pop	{r7, pc}
+ 8004b6c:	01ffffff 	.word	0x01ffffff
+
+08004b70 <UART_WaitOnFlagUntilTimeout>:
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+ 8004b70:	b580      	push	{r7, lr}
+ 8004b72:	b094      	sub	sp, #80	; 0x50
+ 8004b74:	af00      	add	r7, sp, #0
+ 8004b76:	60f8      	str	r0, [r7, #12]
+ 8004b78:	60b9      	str	r1, [r7, #8]
+ 8004b7a:	603b      	str	r3, [r7, #0]
+ 8004b7c:	1dfb      	adds	r3, r7, #7
+ 8004b7e:	701a      	strb	r2, [r3, #0]
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 8004b80:	e0a3      	b.n	8004cca <UART_WaitOnFlagUntilTimeout+0x15a>
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+ 8004b82:	6dbb      	ldr	r3, [r7, #88]	; 0x58
+ 8004b84:	3301      	adds	r3, #1
+ 8004b86:	d100      	bne.n	8004b8a <UART_WaitOnFlagUntilTimeout+0x1a>
+ 8004b88:	e09f      	b.n	8004cca <UART_WaitOnFlagUntilTimeout+0x15a>
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ 8004b8a:	f7fc fe05 	bl	8001798 <HAL_GetTick>
+ 8004b8e:	0002      	movs	r2, r0
+ 8004b90:	683b      	ldr	r3, [r7, #0]
+ 8004b92:	1ad3      	subs	r3, r2, r3
+ 8004b94:	6dba      	ldr	r2, [r7, #88]	; 0x58
+ 8004b96:	429a      	cmp	r2, r3
+ 8004b98:	d302      	bcc.n	8004ba0 <UART_WaitOnFlagUntilTimeout+0x30>
+ 8004b9a:	6dbb      	ldr	r3, [r7, #88]	; 0x58
+ 8004b9c:	2b00      	cmp	r3, #0
+ 8004b9e:	d13d      	bne.n	8004c1c <UART_WaitOnFlagUntilTimeout+0xac>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004ba0:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004ba4:	62bb      	str	r3, [r7, #40]	; 0x28
+  return(result);
+ 8004ba6:	6abb      	ldr	r3, [r7, #40]	; 0x28
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+           interrupts for the interrupt process */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ 8004ba8:	647b      	str	r3, [r7, #68]	; 0x44
+ 8004baa:	2301      	movs	r3, #1
+ 8004bac:	62fb      	str	r3, [r7, #44]	; 0x2c
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004bae:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8004bb0:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004bb4:	46c0      	nop			; (mov r8, r8)
+ 8004bb6:	68fb      	ldr	r3, [r7, #12]
+ 8004bb8:	681b      	ldr	r3, [r3, #0]
+ 8004bba:	681a      	ldr	r2, [r3, #0]
+ 8004bbc:	68fb      	ldr	r3, [r7, #12]
+ 8004bbe:	681b      	ldr	r3, [r3, #0]
+ 8004bc0:	494c      	ldr	r1, [pc, #304]	; (8004cf4 <UART_WaitOnFlagUntilTimeout+0x184>)
+ 8004bc2:	400a      	ands	r2, r1
+ 8004bc4:	601a      	str	r2, [r3, #0]
+ 8004bc6:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 8004bc8:	633b      	str	r3, [r7, #48]	; 0x30
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004bca:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8004bcc:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004bd0:	46c0      	nop			; (mov r8, r8)
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004bd2:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004bd6:	637b      	str	r3, [r7, #52]	; 0x34
+  return(result);
+ 8004bd8:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004bda:	643b      	str	r3, [r7, #64]	; 0x40
+ 8004bdc:	2301      	movs	r3, #1
+ 8004bde:	63bb      	str	r3, [r7, #56]	; 0x38
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004be0:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8004be2:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004be6:	46c0      	nop			; (mov r8, r8)
+ 8004be8:	68fb      	ldr	r3, [r7, #12]
+ 8004bea:	681b      	ldr	r3, [r3, #0]
+ 8004bec:	689a      	ldr	r2, [r3, #8]
+ 8004bee:	68fb      	ldr	r3, [r7, #12]
+ 8004bf0:	681b      	ldr	r3, [r3, #0]
+ 8004bf2:	2101      	movs	r1, #1
+ 8004bf4:	438a      	bics	r2, r1
+ 8004bf6:	609a      	str	r2, [r3, #8]
+ 8004bf8:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 8004bfa:	63fb      	str	r3, [r7, #60]	; 0x3c
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004bfc:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 8004bfe:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004c02:	46c0      	nop			; (mov r8, r8)
+
+        huart->gState = HAL_UART_STATE_READY;
+ 8004c04:	68fb      	ldr	r3, [r7, #12]
+ 8004c06:	2220      	movs	r2, #32
+ 8004c08:	679a      	str	r2, [r3, #120]	; 0x78
+        huart->RxState = HAL_UART_STATE_READY;
+ 8004c0a:	68fb      	ldr	r3, [r7, #12]
+ 8004c0c:	2220      	movs	r2, #32
+ 8004c0e:	67da      	str	r2, [r3, #124]	; 0x7c
+
+        __HAL_UNLOCK(huart);
+ 8004c10:	68fb      	ldr	r3, [r7, #12]
+ 8004c12:	2274      	movs	r2, #116	; 0x74
+ 8004c14:	2100      	movs	r1, #0
+ 8004c16:	5499      	strb	r1, [r3, r2]
+
+        return HAL_TIMEOUT;
+ 8004c18:	2303      	movs	r3, #3
+ 8004c1a:	e067      	b.n	8004cec <UART_WaitOnFlagUntilTimeout+0x17c>
+      }
+
+      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ 8004c1c:	68fb      	ldr	r3, [r7, #12]
+ 8004c1e:	681b      	ldr	r3, [r3, #0]
+ 8004c20:	681b      	ldr	r3, [r3, #0]
+ 8004c22:	2204      	movs	r2, #4
+ 8004c24:	4013      	ands	r3, r2
+ 8004c26:	d050      	beq.n	8004cca <UART_WaitOnFlagUntilTimeout+0x15a>
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ 8004c28:	68fb      	ldr	r3, [r7, #12]
+ 8004c2a:	681b      	ldr	r3, [r3, #0]
+ 8004c2c:	69da      	ldr	r2, [r3, #28]
+ 8004c2e:	2380      	movs	r3, #128	; 0x80
+ 8004c30:	011b      	lsls	r3, r3, #4
+ 8004c32:	401a      	ands	r2, r3
+ 8004c34:	2380      	movs	r3, #128	; 0x80
+ 8004c36:	011b      	lsls	r3, r3, #4
+ 8004c38:	429a      	cmp	r2, r3
+ 8004c3a:	d146      	bne.n	8004cca <UART_WaitOnFlagUntilTimeout+0x15a>
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+ 8004c3c:	68fb      	ldr	r3, [r7, #12]
+ 8004c3e:	681b      	ldr	r3, [r3, #0]
+ 8004c40:	2280      	movs	r2, #128	; 0x80
+ 8004c42:	0112      	lsls	r2, r2, #4
+ 8004c44:	621a      	str	r2, [r3, #32]
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004c46:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004c4a:	613b      	str	r3, [r7, #16]
+  return(result);
+ 8004c4c:	693b      	ldr	r3, [r7, #16]
+
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+             interrupts for the interrupt process */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ 8004c4e:	64fb      	str	r3, [r7, #76]	; 0x4c
+ 8004c50:	2301      	movs	r3, #1
+ 8004c52:	617b      	str	r3, [r7, #20]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004c54:	697b      	ldr	r3, [r7, #20]
+ 8004c56:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004c5a:	46c0      	nop			; (mov r8, r8)
+ 8004c5c:	68fb      	ldr	r3, [r7, #12]
+ 8004c5e:	681b      	ldr	r3, [r3, #0]
+ 8004c60:	681a      	ldr	r2, [r3, #0]
+ 8004c62:	68fb      	ldr	r3, [r7, #12]
+ 8004c64:	681b      	ldr	r3, [r3, #0]
+ 8004c66:	4923      	ldr	r1, [pc, #140]	; (8004cf4 <UART_WaitOnFlagUntilTimeout+0x184>)
+ 8004c68:	400a      	ands	r2, r1
+ 8004c6a:	601a      	str	r2, [r3, #0]
+ 8004c6c:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 8004c6e:	61bb      	str	r3, [r7, #24]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004c70:	69bb      	ldr	r3, [r7, #24]
+ 8004c72:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004c76:	46c0      	nop			; (mov r8, r8)
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004c78:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004c7c:	61fb      	str	r3, [r7, #28]
+  return(result);
+ 8004c7e:	69fb      	ldr	r3, [r7, #28]
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004c80:	64bb      	str	r3, [r7, #72]	; 0x48
+ 8004c82:	2301      	movs	r3, #1
+ 8004c84:	623b      	str	r3, [r7, #32]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004c86:	6a3b      	ldr	r3, [r7, #32]
+ 8004c88:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004c8c:	46c0      	nop			; (mov r8, r8)
+ 8004c8e:	68fb      	ldr	r3, [r7, #12]
+ 8004c90:	681b      	ldr	r3, [r3, #0]
+ 8004c92:	689a      	ldr	r2, [r3, #8]
+ 8004c94:	68fb      	ldr	r3, [r7, #12]
+ 8004c96:	681b      	ldr	r3, [r3, #0]
+ 8004c98:	2101      	movs	r1, #1
+ 8004c9a:	438a      	bics	r2, r1
+ 8004c9c:	609a      	str	r2, [r3, #8]
+ 8004c9e:	6cbb      	ldr	r3, [r7, #72]	; 0x48
+ 8004ca0:	627b      	str	r3, [r7, #36]	; 0x24
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004ca2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8004ca4:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004ca8:	46c0      	nop			; (mov r8, r8)
+
+          huart->gState = HAL_UART_STATE_READY;
+ 8004caa:	68fb      	ldr	r3, [r7, #12]
+ 8004cac:	2220      	movs	r2, #32
+ 8004cae:	679a      	str	r2, [r3, #120]	; 0x78
+          huart->RxState = HAL_UART_STATE_READY;
+ 8004cb0:	68fb      	ldr	r3, [r7, #12]
+ 8004cb2:	2220      	movs	r2, #32
+ 8004cb4:	67da      	str	r2, [r3, #124]	; 0x7c
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+ 8004cb6:	68fb      	ldr	r3, [r7, #12]
+ 8004cb8:	2280      	movs	r2, #128	; 0x80
+ 8004cba:	2120      	movs	r1, #32
+ 8004cbc:	5099      	str	r1, [r3, r2]
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+ 8004cbe:	68fb      	ldr	r3, [r7, #12]
+ 8004cc0:	2274      	movs	r2, #116	; 0x74
+ 8004cc2:	2100      	movs	r1, #0
+ 8004cc4:	5499      	strb	r1, [r3, r2]
+
+          return HAL_TIMEOUT;
+ 8004cc6:	2303      	movs	r3, #3
+ 8004cc8:	e010      	b.n	8004cec <UART_WaitOnFlagUntilTimeout+0x17c>
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 8004cca:	68fb      	ldr	r3, [r7, #12]
+ 8004ccc:	681b      	ldr	r3, [r3, #0]
+ 8004cce:	69db      	ldr	r3, [r3, #28]
+ 8004cd0:	68ba      	ldr	r2, [r7, #8]
+ 8004cd2:	4013      	ands	r3, r2
+ 8004cd4:	68ba      	ldr	r2, [r7, #8]
+ 8004cd6:	1ad3      	subs	r3, r2, r3
+ 8004cd8:	425a      	negs	r2, r3
+ 8004cda:	4153      	adcs	r3, r2
+ 8004cdc:	b2db      	uxtb	r3, r3
+ 8004cde:	001a      	movs	r2, r3
+ 8004ce0:	1dfb      	adds	r3, r7, #7
+ 8004ce2:	781b      	ldrb	r3, [r3, #0]
+ 8004ce4:	429a      	cmp	r2, r3
+ 8004ce6:	d100      	bne.n	8004cea <UART_WaitOnFlagUntilTimeout+0x17a>
+ 8004ce8:	e74b      	b.n	8004b82 <UART_WaitOnFlagUntilTimeout+0x12>
+        }
+      }
+    }
+  }
+  return HAL_OK;
+ 8004cea:	2300      	movs	r3, #0
+}
+ 8004cec:	0018      	movs	r0, r3
+ 8004cee:	46bd      	mov	sp, r7
+ 8004cf0:	b014      	add	sp, #80	; 0x50
+ 8004cf2:	bd80      	pop	{r7, pc}
+ 8004cf4:	fffffe5f 	.word	0xfffffe5f
+
+08004cf8 <UART_EndRxTransfer>:
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ 8004cf8:	b580      	push	{r7, lr}
+ 8004cfa:	b08e      	sub	sp, #56	; 0x38
+ 8004cfc:	af00      	add	r7, sp, #0
+ 8004cfe:	6078      	str	r0, [r7, #4]
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004d00:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004d04:	617b      	str	r3, [r7, #20]
+  return(result);
+ 8004d06:	697b      	ldr	r3, [r7, #20]
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ 8004d08:	637b      	str	r3, [r7, #52]	; 0x34
+ 8004d0a:	2301      	movs	r3, #1
+ 8004d0c:	61bb      	str	r3, [r7, #24]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004d0e:	69bb      	ldr	r3, [r7, #24]
+ 8004d10:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004d14:	46c0      	nop			; (mov r8, r8)
+ 8004d16:	687b      	ldr	r3, [r7, #4]
+ 8004d18:	681b      	ldr	r3, [r3, #0]
+ 8004d1a:	681a      	ldr	r2, [r3, #0]
+ 8004d1c:	687b      	ldr	r3, [r7, #4]
+ 8004d1e:	681b      	ldr	r3, [r3, #0]
+ 8004d20:	4925      	ldr	r1, [pc, #148]	; (8004db8 <UART_EndRxTransfer+0xc0>)
+ 8004d22:	400a      	ands	r2, r1
+ 8004d24:	601a      	str	r2, [r3, #0]
+ 8004d26:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8004d28:	61fb      	str	r3, [r7, #28]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004d2a:	69fb      	ldr	r3, [r7, #28]
+ 8004d2c:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004d30:	46c0      	nop			; (mov r8, r8)
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004d32:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004d36:	623b      	str	r3, [r7, #32]
+  return(result);
+ 8004d38:	6a3b      	ldr	r3, [r7, #32]
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004d3a:	633b      	str	r3, [r7, #48]	; 0x30
+ 8004d3c:	2301      	movs	r3, #1
+ 8004d3e:	627b      	str	r3, [r7, #36]	; 0x24
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004d40:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8004d42:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004d46:	46c0      	nop			; (mov r8, r8)
+ 8004d48:	687b      	ldr	r3, [r7, #4]
+ 8004d4a:	681b      	ldr	r3, [r3, #0]
+ 8004d4c:	689a      	ldr	r2, [r3, #8]
+ 8004d4e:	687b      	ldr	r3, [r7, #4]
+ 8004d50:	681b      	ldr	r3, [r3, #0]
+ 8004d52:	2101      	movs	r1, #1
+ 8004d54:	438a      	bics	r2, r1
+ 8004d56:	609a      	str	r2, [r3, #8]
+ 8004d58:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8004d5a:	62bb      	str	r3, [r7, #40]	; 0x28
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004d5c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8004d5e:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004d62:	46c0      	nop			; (mov r8, r8)
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 8004d64:	687b      	ldr	r3, [r7, #4]
+ 8004d66:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8004d68:	2b01      	cmp	r3, #1
+ 8004d6a:	d118      	bne.n	8004d9e <UART_EndRxTransfer+0xa6>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004d6c:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004d70:	60bb      	str	r3, [r7, #8]
+  return(result);
+ 8004d72:	68bb      	ldr	r3, [r7, #8]
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 8004d74:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 8004d76:	2301      	movs	r3, #1
+ 8004d78:	60fb      	str	r3, [r7, #12]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004d7a:	68fb      	ldr	r3, [r7, #12]
+ 8004d7c:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004d80:	46c0      	nop			; (mov r8, r8)
+ 8004d82:	687b      	ldr	r3, [r7, #4]
+ 8004d84:	681b      	ldr	r3, [r3, #0]
+ 8004d86:	681a      	ldr	r2, [r3, #0]
+ 8004d88:	687b      	ldr	r3, [r7, #4]
+ 8004d8a:	681b      	ldr	r3, [r3, #0]
+ 8004d8c:	2110      	movs	r1, #16
+ 8004d8e:	438a      	bics	r2, r1
+ 8004d90:	601a      	str	r2, [r3, #0]
+ 8004d92:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8004d94:	613b      	str	r3, [r7, #16]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004d96:	693b      	ldr	r3, [r7, #16]
+ 8004d98:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004d9c:	46c0      	nop			; (mov r8, r8)
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+ 8004d9e:	687b      	ldr	r3, [r7, #4]
+ 8004da0:	2220      	movs	r2, #32
+ 8004da2:	67da      	str	r2, [r3, #124]	; 0x7c
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 8004da4:	687b      	ldr	r3, [r7, #4]
+ 8004da6:	2200      	movs	r2, #0
+ 8004da8:	661a      	str	r2, [r3, #96]	; 0x60
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+ 8004daa:	687b      	ldr	r3, [r7, #4]
+ 8004dac:	2200      	movs	r2, #0
+ 8004dae:	665a      	str	r2, [r3, #100]	; 0x64
+}
+ 8004db0:	46c0      	nop			; (mov r8, r8)
+ 8004db2:	46bd      	mov	sp, r7
+ 8004db4:	b00e      	add	sp, #56	; 0x38
+ 8004db6:	bd80      	pop	{r7, pc}
+ 8004db8:	fffffedf 	.word	0xfffffedf
+
+08004dbc <UART_DMAAbortOnError>:
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ 8004dbc:	b580      	push	{r7, lr}
+ 8004dbe:	b084      	sub	sp, #16
+ 8004dc0:	af00      	add	r7, sp, #0
+ 8004dc2:	6078      	str	r0, [r7, #4]
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 8004dc4:	687b      	ldr	r3, [r7, #4]
+ 8004dc6:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8004dc8:	60fb      	str	r3, [r7, #12]
+  huart->RxXferCount = 0U;
+ 8004dca:	68fb      	ldr	r3, [r7, #12]
+ 8004dcc:	225a      	movs	r2, #90	; 0x5a
+ 8004dce:	2100      	movs	r1, #0
+ 8004dd0:	5299      	strh	r1, [r3, r2]
+  huart->TxXferCount = 0U;
+ 8004dd2:	68fb      	ldr	r3, [r7, #12]
+ 8004dd4:	2252      	movs	r2, #82	; 0x52
+ 8004dd6:	2100      	movs	r1, #0
+ 8004dd8:	5299      	strh	r1, [r3, r2]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+ 8004dda:	68fb      	ldr	r3, [r7, #12]
+ 8004ddc:	0018      	movs	r0, r3
+ 8004dde:	f7ff fb55 	bl	800448c <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 8004de2:	46c0      	nop			; (mov r8, r8)
+ 8004de4:	46bd      	mov	sp, r7
+ 8004de6:	b004      	add	sp, #16
+ 8004de8:	bd80      	pop	{r7, pc}
+
+08004dea <UART_EndTransmit_IT>:
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ 8004dea:	b580      	push	{r7, lr}
+ 8004dec:	b086      	sub	sp, #24
+ 8004dee:	af00      	add	r7, sp, #0
+ 8004df0:	6078      	str	r0, [r7, #4]
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004df2:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004df6:	60bb      	str	r3, [r7, #8]
+  return(result);
+ 8004df8:	68bb      	ldr	r3, [r7, #8]
+  /* Disable the UART Transmit Complete Interrupt */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ 8004dfa:	617b      	str	r3, [r7, #20]
+ 8004dfc:	2301      	movs	r3, #1
+ 8004dfe:	60fb      	str	r3, [r7, #12]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004e00:	68fb      	ldr	r3, [r7, #12]
+ 8004e02:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004e06:	46c0      	nop			; (mov r8, r8)
+ 8004e08:	687b      	ldr	r3, [r7, #4]
+ 8004e0a:	681b      	ldr	r3, [r3, #0]
+ 8004e0c:	681a      	ldr	r2, [r3, #0]
+ 8004e0e:	687b      	ldr	r3, [r7, #4]
+ 8004e10:	681b      	ldr	r3, [r3, #0]
+ 8004e12:	2140      	movs	r1, #64	; 0x40
+ 8004e14:	438a      	bics	r2, r1
+ 8004e16:	601a      	str	r2, [r3, #0]
+ 8004e18:	697b      	ldr	r3, [r7, #20]
+ 8004e1a:	613b      	str	r3, [r7, #16]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004e1c:	693b      	ldr	r3, [r7, #16]
+ 8004e1e:	f383 8810 	msr	PRIMASK, r3
+}
+ 8004e22:	46c0      	nop			; (mov r8, r8)
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+ 8004e24:	687b      	ldr	r3, [r7, #4]
+ 8004e26:	2220      	movs	r2, #32
+ 8004e28:	679a      	str	r2, [r3, #120]	; 0x78
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+ 8004e2a:	687b      	ldr	r3, [r7, #4]
+ 8004e2c:	2200      	movs	r2, #0
+ 8004e2e:	669a      	str	r2, [r3, #104]	; 0x68
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+ 8004e30:	687b      	ldr	r3, [r7, #4]
+ 8004e32:	0018      	movs	r0, r3
+ 8004e34:	f7ff fb22 	bl	800447c <HAL_UART_TxCpltCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 8004e38:	46c0      	nop			; (mov r8, r8)
+ 8004e3a:	46bd      	mov	sp, r7
+ 8004e3c:	b006      	add	sp, #24
+ 8004e3e:	bd80      	pop	{r7, pc}
+
+08004e40 <HAL_UARTEx_WakeupCallback>:
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ 8004e40:	b580      	push	{r7, lr}
+ 8004e42:	b082      	sub	sp, #8
+ 8004e44:	af00      	add	r7, sp, #0
+ 8004e46:	6078      	str	r0, [r7, #4]
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+ 8004e48:	46c0      	nop			; (mov r8, r8)
+ 8004e4a:	46bd      	mov	sp, r7
+ 8004e4c:	b002      	add	sp, #8
+ 8004e4e:	bd80      	pop	{r7, pc}
+
+08004e50 <SVC_Setup>:
+#endif /* SysTick */
+
+/*
+  Setup SVC to reset value.
+*/
+__STATIC_INLINE void SVC_Setup (void) {
+ 8004e50:	b580      	push	{r7, lr}
+ 8004e52:	af00      	add	r7, sp, #0
+  * The issue was logged under:https://github.com/ARM-software/CMSIS-FreeRTOS/issues/35
+  * until it is correctly fixed, the code below is commented
+  */
+/*    NVIC_SetPriority (SVCall_IRQn, 0U); */
+#endif
+}
+ 8004e54:	46c0      	nop			; (mov r8, r8)
+ 8004e56:	46bd      	mov	sp, r7
+ 8004e58:	bd80      	pop	{r7, pc}
+	...
+
+08004e5c <osKernelInitialize>:
+
+/*---------------------------------------------------------------------------*/
+
+osStatus_t osKernelInitialize (void) {
+ 8004e5c:	b580      	push	{r7, lr}
+ 8004e5e:	b084      	sub	sp, #16
+ 8004e60:	af00      	add	r7, sp, #0
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 8004e62:	f3ef 8305 	mrs	r3, IPSR
+ 8004e66:	60bb      	str	r3, [r7, #8]
+  return(result);
+ 8004e68:	68bb      	ldr	r3, [r7, #8]
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+ 8004e6a:	2b00      	cmp	r3, #0
+ 8004e6c:	d109      	bne.n	8004e82 <osKernelInitialize+0x26>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004e6e:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004e72:	607b      	str	r3, [r7, #4]
+  return(result);
+ 8004e74:	687b      	ldr	r3, [r7, #4]
+ 8004e76:	2b00      	cmp	r3, #0
+ 8004e78:	d007      	beq.n	8004e8a <osKernelInitialize+0x2e>
+ 8004e7a:	4b0d      	ldr	r3, [pc, #52]	; (8004eb0 <osKernelInitialize+0x54>)
+ 8004e7c:	681b      	ldr	r3, [r3, #0]
+ 8004e7e:	2b02      	cmp	r3, #2
+ 8004e80:	d103      	bne.n	8004e8a <osKernelInitialize+0x2e>
+    stat = osErrorISR;
+ 8004e82:	2306      	movs	r3, #6
+ 8004e84:	425b      	negs	r3, r3
+ 8004e86:	60fb      	str	r3, [r7, #12]
+ 8004e88:	e00c      	b.n	8004ea4 <osKernelInitialize+0x48>
+  }
+  else {
+    if (KernelState == osKernelInactive) {
+ 8004e8a:	4b09      	ldr	r3, [pc, #36]	; (8004eb0 <osKernelInitialize+0x54>)
+ 8004e8c:	681b      	ldr	r3, [r3, #0]
+ 8004e8e:	2b00      	cmp	r3, #0
+ 8004e90:	d105      	bne.n	8004e9e <osKernelInitialize+0x42>
+      #if defined(USE_FREERTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
+        vPortDefineHeapRegions (configHEAP_5_REGIONS);
+      #endif
+      KernelState = osKernelReady;
+ 8004e92:	4b07      	ldr	r3, [pc, #28]	; (8004eb0 <osKernelInitialize+0x54>)
+ 8004e94:	2201      	movs	r2, #1
+ 8004e96:	601a      	str	r2, [r3, #0]
+      stat = osOK;
+ 8004e98:	2300      	movs	r3, #0
+ 8004e9a:	60fb      	str	r3, [r7, #12]
+ 8004e9c:	e002      	b.n	8004ea4 <osKernelInitialize+0x48>
+    } else {
+      stat = osError;
+ 8004e9e:	2301      	movs	r3, #1
+ 8004ea0:	425b      	negs	r3, r3
+ 8004ea2:	60fb      	str	r3, [r7, #12]
+    }
+  }
+
+  return (stat);
+ 8004ea4:	68fb      	ldr	r3, [r7, #12]
+}
+ 8004ea6:	0018      	movs	r0, r3
+ 8004ea8:	46bd      	mov	sp, r7
+ 8004eaa:	b004      	add	sp, #16
+ 8004eac:	bd80      	pop	{r7, pc}
+ 8004eae:	46c0      	nop			; (mov r8, r8)
+ 8004eb0:	20000030 	.word	0x20000030
+
+08004eb4 <osKernelStart>:
+  }
+
+  return (state);
+}
+
+osStatus_t osKernelStart (void) {
+ 8004eb4:	b580      	push	{r7, lr}
+ 8004eb6:	b084      	sub	sp, #16
+ 8004eb8:	af00      	add	r7, sp, #0
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 8004eba:	f3ef 8305 	mrs	r3, IPSR
+ 8004ebe:	60bb      	str	r3, [r7, #8]
+  return(result);
+ 8004ec0:	68bb      	ldr	r3, [r7, #8]
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+ 8004ec2:	2b00      	cmp	r3, #0
+ 8004ec4:	d109      	bne.n	8004eda <osKernelStart+0x26>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004ec6:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004eca:	607b      	str	r3, [r7, #4]
+  return(result);
+ 8004ecc:	687b      	ldr	r3, [r7, #4]
+ 8004ece:	2b00      	cmp	r3, #0
+ 8004ed0:	d007      	beq.n	8004ee2 <osKernelStart+0x2e>
+ 8004ed2:	4b0f      	ldr	r3, [pc, #60]	; (8004f10 <osKernelStart+0x5c>)
+ 8004ed4:	681b      	ldr	r3, [r3, #0]
+ 8004ed6:	2b02      	cmp	r3, #2
+ 8004ed8:	d103      	bne.n	8004ee2 <osKernelStart+0x2e>
+    stat = osErrorISR;
+ 8004eda:	2306      	movs	r3, #6
+ 8004edc:	425b      	negs	r3, r3
+ 8004ede:	60fb      	str	r3, [r7, #12]
+ 8004ee0:	e010      	b.n	8004f04 <osKernelStart+0x50>
+  }
+  else {
+    if (KernelState == osKernelReady) {
+ 8004ee2:	4b0b      	ldr	r3, [pc, #44]	; (8004f10 <osKernelStart+0x5c>)
+ 8004ee4:	681b      	ldr	r3, [r3, #0]
+ 8004ee6:	2b01      	cmp	r3, #1
+ 8004ee8:	d109      	bne.n	8004efe <osKernelStart+0x4a>
+      /* Ensure SVC priority is at the reset value */
+      SVC_Setup();
+ 8004eea:	f7ff ffb1 	bl	8004e50 <SVC_Setup>
+      /* Change state to enable IRQ masking check */
+      KernelState = osKernelRunning;
+ 8004eee:	4b08      	ldr	r3, [pc, #32]	; (8004f10 <osKernelStart+0x5c>)
+ 8004ef0:	2202      	movs	r2, #2
+ 8004ef2:	601a      	str	r2, [r3, #0]
+      /* Start the kernel scheduler */
+      vTaskStartScheduler();
+ 8004ef4:	f001 f80e 	bl	8005f14 <vTaskStartScheduler>
+      stat = osOK;
+ 8004ef8:	2300      	movs	r3, #0
+ 8004efa:	60fb      	str	r3, [r7, #12]
+ 8004efc:	e002      	b.n	8004f04 <osKernelStart+0x50>
+    } else {
+      stat = osError;
+ 8004efe:	2301      	movs	r3, #1
+ 8004f00:	425b      	negs	r3, r3
+ 8004f02:	60fb      	str	r3, [r7, #12]
+    }
+  }
+
+  return (stat);
+ 8004f04:	68fb      	ldr	r3, [r7, #12]
+}
+ 8004f06:	0018      	movs	r0, r3
+ 8004f08:	46bd      	mov	sp, r7
+ 8004f0a:	b004      	add	sp, #16
+ 8004f0c:	bd80      	pop	{r7, pc}
+ 8004f0e:	46c0      	nop			; (mov r8, r8)
+ 8004f10:	20000030 	.word	0x20000030
+
+08004f14 <osThreadNew>:
+  return (configCPU_CLOCK_HZ);
+}
+
+/*---------------------------------------------------------------------------*/
+
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
+ 8004f14:	b5b0      	push	{r4, r5, r7, lr}
+ 8004f16:	b090      	sub	sp, #64	; 0x40
+ 8004f18:	af04      	add	r7, sp, #16
+ 8004f1a:	60f8      	str	r0, [r7, #12]
+ 8004f1c:	60b9      	str	r1, [r7, #8]
+ 8004f1e:	607a      	str	r2, [r7, #4]
+  uint32_t stack;
+  TaskHandle_t hTask;
+  UBaseType_t prio;
+  int32_t mem;
+
+  hTask = NULL;
+ 8004f20:	2300      	movs	r3, #0
+ 8004f22:	617b      	str	r3, [r7, #20]
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 8004f24:	f3ef 8305 	mrs	r3, IPSR
+ 8004f28:	61fb      	str	r3, [r7, #28]
+  return(result);
+ 8004f2a:	69fb      	ldr	r3, [r7, #28]
+
+  if (!IS_IRQ() && (func != NULL)) {
+ 8004f2c:	2b00      	cmp	r3, #0
+ 8004f2e:	d000      	beq.n	8004f32 <osThreadNew+0x1e>
+ 8004f30:	e08c      	b.n	800504c <osThreadNew+0x138>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 8004f32:	f3ef 8310 	mrs	r3, PRIMASK
+ 8004f36:	61bb      	str	r3, [r7, #24]
+  return(result);
+ 8004f38:	69bb      	ldr	r3, [r7, #24]
+ 8004f3a:	2b00      	cmp	r3, #0
+ 8004f3c:	d004      	beq.n	8004f48 <osThreadNew+0x34>
+ 8004f3e:	4b46      	ldr	r3, [pc, #280]	; (8005058 <osThreadNew+0x144>)
+ 8004f40:	681b      	ldr	r3, [r3, #0]
+ 8004f42:	2b02      	cmp	r3, #2
+ 8004f44:	d100      	bne.n	8004f48 <osThreadNew+0x34>
+ 8004f46:	e081      	b.n	800504c <osThreadNew+0x138>
+ 8004f48:	68fb      	ldr	r3, [r7, #12]
+ 8004f4a:	2b00      	cmp	r3, #0
+ 8004f4c:	d100      	bne.n	8004f50 <osThreadNew+0x3c>
+ 8004f4e:	e07d      	b.n	800504c <osThreadNew+0x138>
+    stack = configMINIMAL_STACK_SIZE;
+ 8004f50:	2380      	movs	r3, #128	; 0x80
+ 8004f52:	62bb      	str	r3, [r7, #40]	; 0x28
+    prio  = (UBaseType_t)osPriorityNormal;
+ 8004f54:	2318      	movs	r3, #24
+ 8004f56:	627b      	str	r3, [r7, #36]	; 0x24
+
+    name = NULL;
+ 8004f58:	2300      	movs	r3, #0
+ 8004f5a:	62fb      	str	r3, [r7, #44]	; 0x2c
+    mem  = -1;
+ 8004f5c:	2301      	movs	r3, #1
+ 8004f5e:	425b      	negs	r3, r3
+ 8004f60:	623b      	str	r3, [r7, #32]
+
+    if (attr != NULL) {
+ 8004f62:	687b      	ldr	r3, [r7, #4]
+ 8004f64:	2b00      	cmp	r3, #0
+ 8004f66:	d044      	beq.n	8004ff2 <osThreadNew+0xde>
+      if (attr->name != NULL) {
+ 8004f68:	687b      	ldr	r3, [r7, #4]
+ 8004f6a:	681b      	ldr	r3, [r3, #0]
+ 8004f6c:	2b00      	cmp	r3, #0
+ 8004f6e:	d002      	beq.n	8004f76 <osThreadNew+0x62>
+        name = attr->name;
+ 8004f70:	687b      	ldr	r3, [r7, #4]
+ 8004f72:	681b      	ldr	r3, [r3, #0]
+ 8004f74:	62fb      	str	r3, [r7, #44]	; 0x2c
+      }
+      if (attr->priority != osPriorityNone) {
+ 8004f76:	687b      	ldr	r3, [r7, #4]
+ 8004f78:	699b      	ldr	r3, [r3, #24]
+ 8004f7a:	2b00      	cmp	r3, #0
+ 8004f7c:	d002      	beq.n	8004f84 <osThreadNew+0x70>
+        prio = (UBaseType_t)attr->priority;
+ 8004f7e:	687b      	ldr	r3, [r7, #4]
+ 8004f80:	699b      	ldr	r3, [r3, #24]
+ 8004f82:	627b      	str	r3, [r7, #36]	; 0x24
+      }
+
+      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
+ 8004f84:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8004f86:	2b00      	cmp	r3, #0
+ 8004f88:	d007      	beq.n	8004f9a <osThreadNew+0x86>
+ 8004f8a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8004f8c:	2b38      	cmp	r3, #56	; 0x38
+ 8004f8e:	d804      	bhi.n	8004f9a <osThreadNew+0x86>
+ 8004f90:	687b      	ldr	r3, [r7, #4]
+ 8004f92:	685b      	ldr	r3, [r3, #4]
+ 8004f94:	2201      	movs	r2, #1
+ 8004f96:	4013      	ands	r3, r2
+ 8004f98:	d001      	beq.n	8004f9e <osThreadNew+0x8a>
+        return (NULL);
+ 8004f9a:	2300      	movs	r3, #0
+ 8004f9c:	e057      	b.n	800504e <osThreadNew+0x13a>
+      }
+
+      if (attr->stack_size > 0U) {
+ 8004f9e:	687b      	ldr	r3, [r7, #4]
+ 8004fa0:	695b      	ldr	r3, [r3, #20]
+ 8004fa2:	2b00      	cmp	r3, #0
+ 8004fa4:	d003      	beq.n	8004fae <osThreadNew+0x9a>
+        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */
+        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
+        stack = attr->stack_size / sizeof(StackType_t);
+ 8004fa6:	687b      	ldr	r3, [r7, #4]
+ 8004fa8:	695b      	ldr	r3, [r3, #20]
+ 8004faa:	089b      	lsrs	r3, r3, #2
+ 8004fac:	62bb      	str	r3, [r7, #40]	; 0x28
+      }
+
+      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
+ 8004fae:	687b      	ldr	r3, [r7, #4]
+ 8004fb0:	689b      	ldr	r3, [r3, #8]
+ 8004fb2:	2b00      	cmp	r3, #0
+ 8004fb4:	d00e      	beq.n	8004fd4 <osThreadNew+0xc0>
+ 8004fb6:	687b      	ldr	r3, [r7, #4]
+ 8004fb8:	68db      	ldr	r3, [r3, #12]
+ 8004fba:	2b5b      	cmp	r3, #91	; 0x5b
+ 8004fbc:	d90a      	bls.n	8004fd4 <osThreadNew+0xc0>
+          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
+ 8004fbe:	687b      	ldr	r3, [r7, #4]
+ 8004fc0:	691b      	ldr	r3, [r3, #16]
+      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
+ 8004fc2:	2b00      	cmp	r3, #0
+ 8004fc4:	d006      	beq.n	8004fd4 <osThreadNew+0xc0>
+          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
+ 8004fc6:	687b      	ldr	r3, [r7, #4]
+ 8004fc8:	695b      	ldr	r3, [r3, #20]
+ 8004fca:	2b00      	cmp	r3, #0
+ 8004fcc:	d002      	beq.n	8004fd4 <osThreadNew+0xc0>
+        mem = 1;
+ 8004fce:	2301      	movs	r3, #1
+ 8004fd0:	623b      	str	r3, [r7, #32]
+ 8004fd2:	e010      	b.n	8004ff6 <osThreadNew+0xe2>
+      }
+      else {
+        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
+ 8004fd4:	687b      	ldr	r3, [r7, #4]
+ 8004fd6:	689b      	ldr	r3, [r3, #8]
+ 8004fd8:	2b00      	cmp	r3, #0
+ 8004fda:	d10c      	bne.n	8004ff6 <osThreadNew+0xe2>
+ 8004fdc:	687b      	ldr	r3, [r7, #4]
+ 8004fde:	68db      	ldr	r3, [r3, #12]
+ 8004fe0:	2b00      	cmp	r3, #0
+ 8004fe2:	d108      	bne.n	8004ff6 <osThreadNew+0xe2>
+ 8004fe4:	687b      	ldr	r3, [r7, #4]
+ 8004fe6:	691b      	ldr	r3, [r3, #16]
+ 8004fe8:	2b00      	cmp	r3, #0
+ 8004fea:	d104      	bne.n	8004ff6 <osThreadNew+0xe2>
+          mem = 0;
+ 8004fec:	2300      	movs	r3, #0
+ 8004fee:	623b      	str	r3, [r7, #32]
+ 8004ff0:	e001      	b.n	8004ff6 <osThreadNew+0xe2>
+        }
+      }
+    }
+    else {
+      mem = 0;
+ 8004ff2:	2300      	movs	r3, #0
+ 8004ff4:	623b      	str	r3, [r7, #32]
+    }
+
+    if (mem == 1) {
+ 8004ff6:	6a3b      	ldr	r3, [r7, #32]
+ 8004ff8:	2b01      	cmp	r3, #1
+ 8004ffa:	d112      	bne.n	8005022 <osThreadNew+0x10e>
+      hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
+ 8004ffc:	687b      	ldr	r3, [r7, #4]
+ 8004ffe:	691a      	ldr	r2, [r3, #16]
+                                                                                    (StaticTask_t *)attr->cb_mem);
+ 8005000:	687b      	ldr	r3, [r7, #4]
+ 8005002:	689b      	ldr	r3, [r3, #8]
+      hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
+ 8005004:	68bd      	ldr	r5, [r7, #8]
+ 8005006:	6abc      	ldr	r4, [r7, #40]	; 0x28
+ 8005008:	6af9      	ldr	r1, [r7, #44]	; 0x2c
+ 800500a:	68f8      	ldr	r0, [r7, #12]
+ 800500c:	9302      	str	r3, [sp, #8]
+ 800500e:	9201      	str	r2, [sp, #4]
+ 8005010:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8005012:	9300      	str	r3, [sp, #0]
+ 8005014:	002b      	movs	r3, r5
+ 8005016:	0022      	movs	r2, r4
+ 8005018:	f000 fd5b 	bl	8005ad2 <xTaskCreateStatic>
+ 800501c:	0003      	movs	r3, r0
+ 800501e:	617b      	str	r3, [r7, #20]
+ 8005020:	e014      	b.n	800504c <osThreadNew+0x138>
+    }
+    else {
+      if (mem == 0) {
+ 8005022:	6a3b      	ldr	r3, [r7, #32]
+ 8005024:	2b00      	cmp	r3, #0
+ 8005026:	d111      	bne.n	800504c <osThreadNew+0x138>
+        if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
+ 8005028:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800502a:	b29a      	uxth	r2, r3
+ 800502c:	68bc      	ldr	r4, [r7, #8]
+ 800502e:	6af9      	ldr	r1, [r7, #44]	; 0x2c
+ 8005030:	68f8      	ldr	r0, [r7, #12]
+ 8005032:	2314      	movs	r3, #20
+ 8005034:	18fb      	adds	r3, r7, r3
+ 8005036:	9301      	str	r3, [sp, #4]
+ 8005038:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800503a:	9300      	str	r3, [sp, #0]
+ 800503c:	0023      	movs	r3, r4
+ 800503e:	f000 fd8c 	bl	8005b5a <xTaskCreate>
+ 8005042:	0003      	movs	r3, r0
+ 8005044:	2b01      	cmp	r3, #1
+ 8005046:	d001      	beq.n	800504c <osThreadNew+0x138>
+          hTask = NULL;
+ 8005048:	2300      	movs	r3, #0
+ 800504a:	617b      	str	r3, [r7, #20]
+        }
+      }
+    }
+  }
+
+  return ((osThreadId_t)hTask);
+ 800504c:	697b      	ldr	r3, [r7, #20]
+}
+ 800504e:	0018      	movs	r0, r3
+ 8005050:	46bd      	mov	sp, r7
+ 8005052:	b00c      	add	sp, #48	; 0x30
+ 8005054:	bdb0      	pop	{r4, r5, r7, pc}
+ 8005056:	46c0      	nop			; (mov r8, r8)
+ 8005058:	20000030 	.word	0x20000030
+
+0800505c <vApplicationGetIdleTaskMemory>:
+
+/*
+  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
+  equals to 1 and is required for static memory allocation support.
+*/
+void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
+ 800505c:	b580      	push	{r7, lr}
+ 800505e:	b084      	sub	sp, #16
+ 8005060:	af00      	add	r7, sp, #0
+ 8005062:	60f8      	str	r0, [r7, #12]
+ 8005064:	60b9      	str	r1, [r7, #8]
+ 8005066:	607a      	str	r2, [r7, #4]
+  *ppxIdleTaskTCBBuffer   = &Idle_TCB;
+ 8005068:	68fb      	ldr	r3, [r7, #12]
+ 800506a:	4a06      	ldr	r2, [pc, #24]	; (8005084 <vApplicationGetIdleTaskMemory+0x28>)
+ 800506c:	601a      	str	r2, [r3, #0]
+  *ppxIdleTaskStackBuffer = &Idle_Stack[0];
+ 800506e:	68bb      	ldr	r3, [r7, #8]
+ 8005070:	4a05      	ldr	r2, [pc, #20]	; (8005088 <vApplicationGetIdleTaskMemory+0x2c>)
+ 8005072:	601a      	str	r2, [r3, #0]
+  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;
+ 8005074:	687b      	ldr	r3, [r7, #4]
+ 8005076:	2280      	movs	r2, #128	; 0x80
+ 8005078:	601a      	str	r2, [r3, #0]
+}
+ 800507a:	46c0      	nop			; (mov r8, r8)
+ 800507c:	46bd      	mov	sp, r7
+ 800507e:	b004      	add	sp, #16
+ 8005080:	bd80      	pop	{r7, pc}
+ 8005082:	46c0      	nop			; (mov r8, r8)
+ 8005084:	20000034 	.word	0x20000034
+ 8005088:	20000090 	.word	0x20000090
+
+0800508c <vApplicationGetTimerTaskMemory>:
+
+/*
+  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
+  equals to 1 and is required for static memory allocation support.
+*/
+void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
+ 800508c:	b580      	push	{r7, lr}
+ 800508e:	b084      	sub	sp, #16
+ 8005090:	af00      	add	r7, sp, #0
+ 8005092:	60f8      	str	r0, [r7, #12]
+ 8005094:	60b9      	str	r1, [r7, #8]
+ 8005096:	607a      	str	r2, [r7, #4]
+  *ppxTimerTaskTCBBuffer   = &Timer_TCB;
+ 8005098:	68fb      	ldr	r3, [r7, #12]
+ 800509a:	4a06      	ldr	r2, [pc, #24]	; (80050b4 <vApplicationGetTimerTaskMemory+0x28>)
+ 800509c:	601a      	str	r2, [r3, #0]
+  *ppxTimerTaskStackBuffer = &Timer_Stack[0];
+ 800509e:	68bb      	ldr	r3, [r7, #8]
+ 80050a0:	4a05      	ldr	r2, [pc, #20]	; (80050b8 <vApplicationGetTimerTaskMemory+0x2c>)
+ 80050a2:	601a      	str	r2, [r3, #0]
+  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;
+ 80050a4:	687b      	ldr	r3, [r7, #4]
+ 80050a6:	2280      	movs	r2, #128	; 0x80
+ 80050a8:	0052      	lsls	r2, r2, #1
+ 80050aa:	601a      	str	r2, [r3, #0]
+}
+ 80050ac:	46c0      	nop			; (mov r8, r8)
+ 80050ae:	46bd      	mov	sp, r7
+ 80050b0:	b004      	add	sp, #16
+ 80050b2:	bd80      	pop	{r7, pc}
+ 80050b4:	20000290 	.word	0x20000290
+ 80050b8:	200002ec 	.word	0x200002ec
+
+080050bc <vListInitialise>:
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+ 80050bc:	b580      	push	{r7, lr}
+ 80050be:	b082      	sub	sp, #8
+ 80050c0:	af00      	add	r7, sp, #0
+ 80050c2:	6078      	str	r0, [r7, #4]
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+ 80050c4:	687b      	ldr	r3, [r7, #4]
+ 80050c6:	3308      	adds	r3, #8
+ 80050c8:	001a      	movs	r2, r3
+ 80050ca:	687b      	ldr	r3, [r7, #4]
+ 80050cc:	605a      	str	r2, [r3, #4]
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+ 80050ce:	687b      	ldr	r3, [r7, #4]
+ 80050d0:	2201      	movs	r2, #1
+ 80050d2:	4252      	negs	r2, r2
+ 80050d4:	609a      	str	r2, [r3, #8]
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+ 80050d6:	687b      	ldr	r3, [r7, #4]
+ 80050d8:	3308      	adds	r3, #8
+ 80050da:	001a      	movs	r2, r3
+ 80050dc:	687b      	ldr	r3, [r7, #4]
+ 80050de:	60da      	str	r2, [r3, #12]
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+ 80050e0:	687b      	ldr	r3, [r7, #4]
+ 80050e2:	3308      	adds	r3, #8
+ 80050e4:	001a      	movs	r2, r3
+ 80050e6:	687b      	ldr	r3, [r7, #4]
+ 80050e8:	611a      	str	r2, [r3, #16]
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+ 80050ea:	687b      	ldr	r3, [r7, #4]
+ 80050ec:	2200      	movs	r2, #0
+ 80050ee:	601a      	str	r2, [r3, #0]
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+ 80050f0:	46c0      	nop			; (mov r8, r8)
+ 80050f2:	46bd      	mov	sp, r7
+ 80050f4:	b002      	add	sp, #8
+ 80050f6:	bd80      	pop	{r7, pc}
+
+080050f8 <vListInitialiseItem>:
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+ 80050f8:	b580      	push	{r7, lr}
+ 80050fa:	b082      	sub	sp, #8
+ 80050fc:	af00      	add	r7, sp, #0
+ 80050fe:	6078      	str	r0, [r7, #4]
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+ 8005100:	687b      	ldr	r3, [r7, #4]
+ 8005102:	2200      	movs	r2, #0
+ 8005104:	611a      	str	r2, [r3, #16]
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+ 8005106:	46c0      	nop			; (mov r8, r8)
+ 8005108:	46bd      	mov	sp, r7
+ 800510a:	b002      	add	sp, #8
+ 800510c:	bd80      	pop	{r7, pc}
+
+0800510e <vListInsertEnd>:
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ 800510e:	b580      	push	{r7, lr}
+ 8005110:	b084      	sub	sp, #16
+ 8005112:	af00      	add	r7, sp, #0
+ 8005114:	6078      	str	r0, [r7, #4]
+ 8005116:	6039      	str	r1, [r7, #0]
+ListItem_t * const pxIndex = pxList->pxIndex;
+ 8005118:	687b      	ldr	r3, [r7, #4]
+ 800511a:	685b      	ldr	r3, [r3, #4]
+ 800511c:	60fb      	str	r3, [r7, #12]
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+ 800511e:	683b      	ldr	r3, [r7, #0]
+ 8005120:	68fa      	ldr	r2, [r7, #12]
+ 8005122:	605a      	str	r2, [r3, #4]
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+ 8005124:	68fb      	ldr	r3, [r7, #12]
+ 8005126:	689a      	ldr	r2, [r3, #8]
+ 8005128:	683b      	ldr	r3, [r7, #0]
+ 800512a:	609a      	str	r2, [r3, #8]
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+ 800512c:	68fb      	ldr	r3, [r7, #12]
+ 800512e:	689b      	ldr	r3, [r3, #8]
+ 8005130:	683a      	ldr	r2, [r7, #0]
+ 8005132:	605a      	str	r2, [r3, #4]
+	pxIndex->pxPrevious = pxNewListItem;
+ 8005134:	68fb      	ldr	r3, [r7, #12]
+ 8005136:	683a      	ldr	r2, [r7, #0]
+ 8005138:	609a      	str	r2, [r3, #8]
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+ 800513a:	683b      	ldr	r3, [r7, #0]
+ 800513c:	687a      	ldr	r2, [r7, #4]
+ 800513e:	611a      	str	r2, [r3, #16]
+
+	( pxList->uxNumberOfItems )++;
+ 8005140:	687b      	ldr	r3, [r7, #4]
+ 8005142:	681b      	ldr	r3, [r3, #0]
+ 8005144:	1c5a      	adds	r2, r3, #1
+ 8005146:	687b      	ldr	r3, [r7, #4]
+ 8005148:	601a      	str	r2, [r3, #0]
+}
+ 800514a:	46c0      	nop			; (mov r8, r8)
+ 800514c:	46bd      	mov	sp, r7
+ 800514e:	b004      	add	sp, #16
+ 8005150:	bd80      	pop	{r7, pc}
+
+08005152 <vListInsert>:
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ 8005152:	b580      	push	{r7, lr}
+ 8005154:	b084      	sub	sp, #16
+ 8005156:	af00      	add	r7, sp, #0
+ 8005158:	6078      	str	r0, [r7, #4]
+ 800515a:	6039      	str	r1, [r7, #0]
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+ 800515c:	683b      	ldr	r3, [r7, #0]
+ 800515e:	681b      	ldr	r3, [r3, #0]
+ 8005160:	60bb      	str	r3, [r7, #8]
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+ 8005162:	68bb      	ldr	r3, [r7, #8]
+ 8005164:	3301      	adds	r3, #1
+ 8005166:	d103      	bne.n	8005170 <vListInsert+0x1e>
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+ 8005168:	687b      	ldr	r3, [r7, #4]
+ 800516a:	691b      	ldr	r3, [r3, #16]
+ 800516c:	60fb      	str	r3, [r7, #12]
+ 800516e:	e00c      	b.n	800518a <vListInsert+0x38>
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+ 8005170:	687b      	ldr	r3, [r7, #4]
+ 8005172:	3308      	adds	r3, #8
+ 8005174:	60fb      	str	r3, [r7, #12]
+ 8005176:	e002      	b.n	800517e <vListInsert+0x2c>
+ 8005178:	68fb      	ldr	r3, [r7, #12]
+ 800517a:	685b      	ldr	r3, [r3, #4]
+ 800517c:	60fb      	str	r3, [r7, #12]
+ 800517e:	68fb      	ldr	r3, [r7, #12]
+ 8005180:	685b      	ldr	r3, [r3, #4]
+ 8005182:	681b      	ldr	r3, [r3, #0]
+ 8005184:	68ba      	ldr	r2, [r7, #8]
+ 8005186:	429a      	cmp	r2, r3
+ 8005188:	d2f6      	bcs.n	8005178 <vListInsert+0x26>
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+ 800518a:	68fb      	ldr	r3, [r7, #12]
+ 800518c:	685a      	ldr	r2, [r3, #4]
+ 800518e:	683b      	ldr	r3, [r7, #0]
+ 8005190:	605a      	str	r2, [r3, #4]
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+ 8005192:	683b      	ldr	r3, [r7, #0]
+ 8005194:	685b      	ldr	r3, [r3, #4]
+ 8005196:	683a      	ldr	r2, [r7, #0]
+ 8005198:	609a      	str	r2, [r3, #8]
+	pxNewListItem->pxPrevious = pxIterator;
+ 800519a:	683b      	ldr	r3, [r7, #0]
+ 800519c:	68fa      	ldr	r2, [r7, #12]
+ 800519e:	609a      	str	r2, [r3, #8]
+	pxIterator->pxNext = pxNewListItem;
+ 80051a0:	68fb      	ldr	r3, [r7, #12]
+ 80051a2:	683a      	ldr	r2, [r7, #0]
+ 80051a4:	605a      	str	r2, [r3, #4]
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+ 80051a6:	683b      	ldr	r3, [r7, #0]
+ 80051a8:	687a      	ldr	r2, [r7, #4]
+ 80051aa:	611a      	str	r2, [r3, #16]
+
+	( pxList->uxNumberOfItems )++;
+ 80051ac:	687b      	ldr	r3, [r7, #4]
+ 80051ae:	681b      	ldr	r3, [r3, #0]
+ 80051b0:	1c5a      	adds	r2, r3, #1
+ 80051b2:	687b      	ldr	r3, [r7, #4]
+ 80051b4:	601a      	str	r2, [r3, #0]
+}
+ 80051b6:	46c0      	nop			; (mov r8, r8)
+ 80051b8:	46bd      	mov	sp, r7
+ 80051ba:	b004      	add	sp, #16
+ 80051bc:	bd80      	pop	{r7, pc}
+
+080051be <uxListRemove>:
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+ 80051be:	b580      	push	{r7, lr}
+ 80051c0:	b084      	sub	sp, #16
+ 80051c2:	af00      	add	r7, sp, #0
+ 80051c4:	6078      	str	r0, [r7, #4]
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+ 80051c6:	687b      	ldr	r3, [r7, #4]
+ 80051c8:	691b      	ldr	r3, [r3, #16]
+ 80051ca:	60fb      	str	r3, [r7, #12]
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+ 80051cc:	687b      	ldr	r3, [r7, #4]
+ 80051ce:	685b      	ldr	r3, [r3, #4]
+ 80051d0:	687a      	ldr	r2, [r7, #4]
+ 80051d2:	6892      	ldr	r2, [r2, #8]
+ 80051d4:	609a      	str	r2, [r3, #8]
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+ 80051d6:	687b      	ldr	r3, [r7, #4]
+ 80051d8:	689b      	ldr	r3, [r3, #8]
+ 80051da:	687a      	ldr	r2, [r7, #4]
+ 80051dc:	6852      	ldr	r2, [r2, #4]
+ 80051de:	605a      	str	r2, [r3, #4]
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+ 80051e0:	68fb      	ldr	r3, [r7, #12]
+ 80051e2:	685b      	ldr	r3, [r3, #4]
+ 80051e4:	687a      	ldr	r2, [r7, #4]
+ 80051e6:	429a      	cmp	r2, r3
+ 80051e8:	d103      	bne.n	80051f2 <uxListRemove+0x34>
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+ 80051ea:	687b      	ldr	r3, [r7, #4]
+ 80051ec:	689a      	ldr	r2, [r3, #8]
+ 80051ee:	68fb      	ldr	r3, [r7, #12]
+ 80051f0:	605a      	str	r2, [r3, #4]
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+ 80051f2:	687b      	ldr	r3, [r7, #4]
+ 80051f4:	2200      	movs	r2, #0
+ 80051f6:	611a      	str	r2, [r3, #16]
+	( pxList->uxNumberOfItems )--;
+ 80051f8:	68fb      	ldr	r3, [r7, #12]
+ 80051fa:	681b      	ldr	r3, [r3, #0]
+ 80051fc:	1e5a      	subs	r2, r3, #1
+ 80051fe:	68fb      	ldr	r3, [r7, #12]
+ 8005200:	601a      	str	r2, [r3, #0]
+
+	return pxList->uxNumberOfItems;
+ 8005202:	68fb      	ldr	r3, [r7, #12]
+ 8005204:	681b      	ldr	r3, [r3, #0]
+}
+ 8005206:	0018      	movs	r0, r3
+ 8005208:	46bd      	mov	sp, r7
+ 800520a:	b004      	add	sp, #16
+ 800520c:	bd80      	pop	{r7, pc}
+
+0800520e <xQueueGenericReset>:
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+ 800520e:	b580      	push	{r7, lr}
+ 8005210:	b084      	sub	sp, #16
+ 8005212:	af00      	add	r7, sp, #0
+ 8005214:	6078      	str	r0, [r7, #4]
+ 8005216:	6039      	str	r1, [r7, #0]
+Queue_t * const pxQueue = xQueue;
+ 8005218:	687b      	ldr	r3, [r7, #4]
+ 800521a:	60fb      	str	r3, [r7, #12]
+
+	configASSERT( pxQueue );
+ 800521c:	68fb      	ldr	r3, [r7, #12]
+ 800521e:	2b00      	cmp	r3, #0
+ 8005220:	d101      	bne.n	8005226 <xQueueGenericReset+0x18>
+ 8005222:	b672      	cpsid	i
+ 8005224:	e7fe      	b.n	8005224 <xQueueGenericReset+0x16>
+
+	taskENTER_CRITICAL();
+ 8005226:	f001 ff7b 	bl	8007120 <vPortEnterCritical>
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ 800522a:	68fb      	ldr	r3, [r7, #12]
+ 800522c:	681a      	ldr	r2, [r3, #0]
+ 800522e:	68fb      	ldr	r3, [r7, #12]
+ 8005230:	6bd9      	ldr	r1, [r3, #60]	; 0x3c
+ 8005232:	68fb      	ldr	r3, [r7, #12]
+ 8005234:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8005236:	434b      	muls	r3, r1
+ 8005238:	18d2      	adds	r2, r2, r3
+ 800523a:	68fb      	ldr	r3, [r7, #12]
+ 800523c:	609a      	str	r2, [r3, #8]
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+ 800523e:	68fb      	ldr	r3, [r7, #12]
+ 8005240:	2200      	movs	r2, #0
+ 8005242:	639a      	str	r2, [r3, #56]	; 0x38
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+ 8005244:	68fb      	ldr	r3, [r7, #12]
+ 8005246:	681a      	ldr	r2, [r3, #0]
+ 8005248:	68fb      	ldr	r3, [r7, #12]
+ 800524a:	605a      	str	r2, [r3, #4]
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ 800524c:	68fb      	ldr	r3, [r7, #12]
+ 800524e:	681a      	ldr	r2, [r3, #0]
+ 8005250:	68fb      	ldr	r3, [r7, #12]
+ 8005252:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8005254:	1e59      	subs	r1, r3, #1
+ 8005256:	68fb      	ldr	r3, [r7, #12]
+ 8005258:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800525a:	434b      	muls	r3, r1
+ 800525c:	18d2      	adds	r2, r2, r3
+ 800525e:	68fb      	ldr	r3, [r7, #12]
+ 8005260:	60da      	str	r2, [r3, #12]
+		pxQueue->cRxLock = queueUNLOCKED;
+ 8005262:	68fb      	ldr	r3, [r7, #12]
+ 8005264:	2244      	movs	r2, #68	; 0x44
+ 8005266:	21ff      	movs	r1, #255	; 0xff
+ 8005268:	5499      	strb	r1, [r3, r2]
+		pxQueue->cTxLock = queueUNLOCKED;
+ 800526a:	68fb      	ldr	r3, [r7, #12]
+ 800526c:	2245      	movs	r2, #69	; 0x45
+ 800526e:	21ff      	movs	r1, #255	; 0xff
+ 8005270:	5499      	strb	r1, [r3, r2]
+
+		if( xNewQueue == pdFALSE )
+ 8005272:	683b      	ldr	r3, [r7, #0]
+ 8005274:	2b00      	cmp	r3, #0
+ 8005276:	d10d      	bne.n	8005294 <xQueueGenericReset+0x86>
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ 8005278:	68fb      	ldr	r3, [r7, #12]
+ 800527a:	691b      	ldr	r3, [r3, #16]
+ 800527c:	2b00      	cmp	r3, #0
+ 800527e:	d013      	beq.n	80052a8 <xQueueGenericReset+0x9a>
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ 8005280:	68fb      	ldr	r3, [r7, #12]
+ 8005282:	3310      	adds	r3, #16
+ 8005284:	0018      	movs	r0, r3
+ 8005286:	f001 f8d7 	bl	8006438 <xTaskRemoveFromEventList>
+ 800528a:	1e03      	subs	r3, r0, #0
+ 800528c:	d00c      	beq.n	80052a8 <xQueueGenericReset+0x9a>
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+ 800528e:	f001 ff37 	bl	8007100 <vPortYield>
+ 8005292:	e009      	b.n	80052a8 <xQueueGenericReset+0x9a>
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+ 8005294:	68fb      	ldr	r3, [r7, #12]
+ 8005296:	3310      	adds	r3, #16
+ 8005298:	0018      	movs	r0, r3
+ 800529a:	f7ff ff0f 	bl	80050bc <vListInitialise>
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+ 800529e:	68fb      	ldr	r3, [r7, #12]
+ 80052a0:	3324      	adds	r3, #36	; 0x24
+ 80052a2:	0018      	movs	r0, r3
+ 80052a4:	f7ff ff0a 	bl	80050bc <vListInitialise>
+		}
+	}
+	taskEXIT_CRITICAL();
+ 80052a8:	f001 ff4c 	bl	8007144 <vPortExitCritical>
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+ 80052ac:	2301      	movs	r3, #1
+}
+ 80052ae:	0018      	movs	r0, r3
+ 80052b0:	46bd      	mov	sp, r7
+ 80052b2:	b004      	add	sp, #16
+ 80052b4:	bd80      	pop	{r7, pc}
+
+080052b6 <xQueueGenericCreateStatic>:
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+ 80052b6:	b590      	push	{r4, r7, lr}
+ 80052b8:	b089      	sub	sp, #36	; 0x24
+ 80052ba:	af02      	add	r7, sp, #8
+ 80052bc:	60f8      	str	r0, [r7, #12]
+ 80052be:	60b9      	str	r1, [r7, #8]
+ 80052c0:	607a      	str	r2, [r7, #4]
+ 80052c2:	603b      	str	r3, [r7, #0]
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+ 80052c4:	68fb      	ldr	r3, [r7, #12]
+ 80052c6:	2b00      	cmp	r3, #0
+ 80052c8:	d101      	bne.n	80052ce <xQueueGenericCreateStatic+0x18>
+ 80052ca:	b672      	cpsid	i
+ 80052cc:	e7fe      	b.n	80052cc <xQueueGenericCreateStatic+0x16>
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+ 80052ce:	683b      	ldr	r3, [r7, #0]
+ 80052d0:	2b00      	cmp	r3, #0
+ 80052d2:	d101      	bne.n	80052d8 <xQueueGenericCreateStatic+0x22>
+ 80052d4:	b672      	cpsid	i
+ 80052d6:	e7fe      	b.n	80052d6 <xQueueGenericCreateStatic+0x20>
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+ 80052d8:	687b      	ldr	r3, [r7, #4]
+ 80052da:	2b00      	cmp	r3, #0
+ 80052dc:	d002      	beq.n	80052e4 <xQueueGenericCreateStatic+0x2e>
+ 80052de:	68bb      	ldr	r3, [r7, #8]
+ 80052e0:	2b00      	cmp	r3, #0
+ 80052e2:	d001      	beq.n	80052e8 <xQueueGenericCreateStatic+0x32>
+ 80052e4:	2301      	movs	r3, #1
+ 80052e6:	e000      	b.n	80052ea <xQueueGenericCreateStatic+0x34>
+ 80052e8:	2300      	movs	r3, #0
+ 80052ea:	2b00      	cmp	r3, #0
+ 80052ec:	d101      	bne.n	80052f2 <xQueueGenericCreateStatic+0x3c>
+ 80052ee:	b672      	cpsid	i
+ 80052f0:	e7fe      	b.n	80052f0 <xQueueGenericCreateStatic+0x3a>
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+ 80052f2:	687b      	ldr	r3, [r7, #4]
+ 80052f4:	2b00      	cmp	r3, #0
+ 80052f6:	d102      	bne.n	80052fe <xQueueGenericCreateStatic+0x48>
+ 80052f8:	68bb      	ldr	r3, [r7, #8]
+ 80052fa:	2b00      	cmp	r3, #0
+ 80052fc:	d101      	bne.n	8005302 <xQueueGenericCreateStatic+0x4c>
+ 80052fe:	2301      	movs	r3, #1
+ 8005300:	e000      	b.n	8005304 <xQueueGenericCreateStatic+0x4e>
+ 8005302:	2300      	movs	r3, #0
+ 8005304:	2b00      	cmp	r3, #0
+ 8005306:	d101      	bne.n	800530c <xQueueGenericCreateStatic+0x56>
+ 8005308:	b672      	cpsid	i
+ 800530a:	e7fe      	b.n	800530a <xQueueGenericCreateStatic+0x54>
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+ 800530c:	2350      	movs	r3, #80	; 0x50
+ 800530e:	613b      	str	r3, [r7, #16]
+			configASSERT( xSize == sizeof( Queue_t ) );
+ 8005310:	693b      	ldr	r3, [r7, #16]
+ 8005312:	2b50      	cmp	r3, #80	; 0x50
+ 8005314:	d001      	beq.n	800531a <xQueueGenericCreateStatic+0x64>
+ 8005316:	b672      	cpsid	i
+ 8005318:	e7fe      	b.n	8005318 <xQueueGenericCreateStatic+0x62>
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+ 800531a:	693b      	ldr	r3, [r7, #16]
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ 800531c:	683b      	ldr	r3, [r7, #0]
+ 800531e:	617b      	str	r3, [r7, #20]
+
+		if( pxNewQueue != NULL )
+ 8005320:	697b      	ldr	r3, [r7, #20]
+ 8005322:	2b00      	cmp	r3, #0
+ 8005324:	d00e      	beq.n	8005344 <xQueueGenericCreateStatic+0x8e>
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+ 8005326:	697b      	ldr	r3, [r7, #20]
+ 8005328:	2246      	movs	r2, #70	; 0x46
+ 800532a:	2101      	movs	r1, #1
+ 800532c:	5499      	strb	r1, [r3, r2]
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+ 800532e:	2328      	movs	r3, #40	; 0x28
+ 8005330:	18fb      	adds	r3, r7, r3
+ 8005332:	781c      	ldrb	r4, [r3, #0]
+ 8005334:	687a      	ldr	r2, [r7, #4]
+ 8005336:	68b9      	ldr	r1, [r7, #8]
+ 8005338:	68f8      	ldr	r0, [r7, #12]
+ 800533a:	697b      	ldr	r3, [r7, #20]
+ 800533c:	9300      	str	r3, [sp, #0]
+ 800533e:	0023      	movs	r3, r4
+ 8005340:	f000 f83d 	bl	80053be <prvInitialiseNewQueue>
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+ 8005344:	697b      	ldr	r3, [r7, #20]
+	}
+ 8005346:	0018      	movs	r0, r3
+ 8005348:	46bd      	mov	sp, r7
+ 800534a:	b007      	add	sp, #28
+ 800534c:	bd90      	pop	{r4, r7, pc}
+
+0800534e <xQueueGenericCreate>:
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+ 800534e:	b590      	push	{r4, r7, lr}
+ 8005350:	b08b      	sub	sp, #44	; 0x2c
+ 8005352:	af02      	add	r7, sp, #8
+ 8005354:	60f8      	str	r0, [r7, #12]
+ 8005356:	60b9      	str	r1, [r7, #8]
+ 8005358:	1dfb      	adds	r3, r7, #7
+ 800535a:	701a      	strb	r2, [r3, #0]
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+ 800535c:	68fb      	ldr	r3, [r7, #12]
+ 800535e:	2b00      	cmp	r3, #0
+ 8005360:	d101      	bne.n	8005366 <xQueueGenericCreate+0x18>
+ 8005362:	b672      	cpsid	i
+ 8005364:	e7fe      	b.n	8005364 <xQueueGenericCreate+0x16>
+
+		if( uxItemSize == ( UBaseType_t ) 0 )
+ 8005366:	68bb      	ldr	r3, [r7, #8]
+ 8005368:	2b00      	cmp	r3, #0
+ 800536a:	d102      	bne.n	8005372 <xQueueGenericCreate+0x24>
+		{
+			/* There is not going to be a queue storage area. */
+			xQueueSizeInBytes = ( size_t ) 0;
+ 800536c:	2300      	movs	r3, #0
+ 800536e:	61fb      	str	r3, [r7, #28]
+ 8005370:	e003      	b.n	800537a <xQueueGenericCreate+0x2c>
+		}
+		else
+		{
+			/* Allocate enough space to hold the maximum number of items that
+			can be in the queue at any time. */
+			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 8005372:	68fb      	ldr	r3, [r7, #12]
+ 8005374:	68ba      	ldr	r2, [r7, #8]
+ 8005376:	4353      	muls	r3, r2
+ 8005378:	61fb      	str	r3, [r7, #28]
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+ 800537a:	69fb      	ldr	r3, [r7, #28]
+ 800537c:	3350      	adds	r3, #80	; 0x50
+ 800537e:	0018      	movs	r0, r3
+ 8005380:	f002 f84a 	bl	8007418 <pvPortMalloc>
+ 8005384:	0003      	movs	r3, r0
+ 8005386:	61bb      	str	r3, [r7, #24]
+
+		if( pxNewQueue != NULL )
+ 8005388:	69bb      	ldr	r3, [r7, #24]
+ 800538a:	2b00      	cmp	r3, #0
+ 800538c:	d012      	beq.n	80053b4 <xQueueGenericCreate+0x66>
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+ 800538e:	69bb      	ldr	r3, [r7, #24]
+ 8005390:	617b      	str	r3, [r7, #20]
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ 8005392:	697b      	ldr	r3, [r7, #20]
+ 8005394:	3350      	adds	r3, #80	; 0x50
+ 8005396:	617b      	str	r3, [r7, #20]
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+ 8005398:	69bb      	ldr	r3, [r7, #24]
+ 800539a:	2246      	movs	r2, #70	; 0x46
+ 800539c:	2100      	movs	r1, #0
+ 800539e:	5499      	strb	r1, [r3, r2]
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+ 80053a0:	1dfb      	adds	r3, r7, #7
+ 80053a2:	781c      	ldrb	r4, [r3, #0]
+ 80053a4:	697a      	ldr	r2, [r7, #20]
+ 80053a6:	68b9      	ldr	r1, [r7, #8]
+ 80053a8:	68f8      	ldr	r0, [r7, #12]
+ 80053aa:	69bb      	ldr	r3, [r7, #24]
+ 80053ac:	9300      	str	r3, [sp, #0]
+ 80053ae:	0023      	movs	r3, r4
+ 80053b0:	f000 f805 	bl	80053be <prvInitialiseNewQueue>
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+ 80053b4:	69bb      	ldr	r3, [r7, #24]
+	}
+ 80053b6:	0018      	movs	r0, r3
+ 80053b8:	46bd      	mov	sp, r7
+ 80053ba:	b009      	add	sp, #36	; 0x24
+ 80053bc:	bd90      	pop	{r4, r7, pc}
+
+080053be <prvInitialiseNewQueue>:
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+ 80053be:	b580      	push	{r7, lr}
+ 80053c0:	b084      	sub	sp, #16
+ 80053c2:	af00      	add	r7, sp, #0
+ 80053c4:	60f8      	str	r0, [r7, #12]
+ 80053c6:	60b9      	str	r1, [r7, #8]
+ 80053c8:	607a      	str	r2, [r7, #4]
+ 80053ca:	001a      	movs	r2, r3
+ 80053cc:	1cfb      	adds	r3, r7, #3
+ 80053ce:	701a      	strb	r2, [r3, #0]
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+ 80053d0:	68bb      	ldr	r3, [r7, #8]
+ 80053d2:	2b00      	cmp	r3, #0
+ 80053d4:	d103      	bne.n	80053de <prvInitialiseNewQueue+0x20>
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+ 80053d6:	69bb      	ldr	r3, [r7, #24]
+ 80053d8:	69ba      	ldr	r2, [r7, #24]
+ 80053da:	601a      	str	r2, [r3, #0]
+ 80053dc:	e002      	b.n	80053e4 <prvInitialiseNewQueue+0x26>
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+ 80053de:	69bb      	ldr	r3, [r7, #24]
+ 80053e0:	687a      	ldr	r2, [r7, #4]
+ 80053e2:	601a      	str	r2, [r3, #0]
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+ 80053e4:	69bb      	ldr	r3, [r7, #24]
+ 80053e6:	68fa      	ldr	r2, [r7, #12]
+ 80053e8:	63da      	str	r2, [r3, #60]	; 0x3c
+	pxNewQueue->uxItemSize = uxItemSize;
+ 80053ea:	69bb      	ldr	r3, [r7, #24]
+ 80053ec:	68ba      	ldr	r2, [r7, #8]
+ 80053ee:	641a      	str	r2, [r3, #64]	; 0x40
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+ 80053f0:	69bb      	ldr	r3, [r7, #24]
+ 80053f2:	2101      	movs	r1, #1
+ 80053f4:	0018      	movs	r0, r3
+ 80053f6:	f7ff ff0a 	bl	800520e <xQueueGenericReset>
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+ 80053fa:	69bb      	ldr	r3, [r7, #24]
+ 80053fc:	1cfa      	adds	r2, r7, #3
+ 80053fe:	214c      	movs	r1, #76	; 0x4c
+ 8005400:	7812      	ldrb	r2, [r2, #0]
+ 8005402:	545a      	strb	r2, [r3, r1]
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+ 8005404:	46c0      	nop			; (mov r8, r8)
+ 8005406:	46bd      	mov	sp, r7
+ 8005408:	b004      	add	sp, #16
+ 800540a:	bd80      	pop	{r7, pc}
+
+0800540c <xQueueGenericSend>:
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+ 800540c:	b580      	push	{r7, lr}
+ 800540e:	b08a      	sub	sp, #40	; 0x28
+ 8005410:	af00      	add	r7, sp, #0
+ 8005412:	60f8      	str	r0, [r7, #12]
+ 8005414:	60b9      	str	r1, [r7, #8]
+ 8005416:	607a      	str	r2, [r7, #4]
+ 8005418:	603b      	str	r3, [r7, #0]
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+ 800541a:	2300      	movs	r3, #0
+ 800541c:	627b      	str	r3, [r7, #36]	; 0x24
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+ 800541e:	68fb      	ldr	r3, [r7, #12]
+ 8005420:	623b      	str	r3, [r7, #32]
+
+	configASSERT( pxQueue );
+ 8005422:	6a3b      	ldr	r3, [r7, #32]
+ 8005424:	2b00      	cmp	r3, #0
+ 8005426:	d101      	bne.n	800542c <xQueueGenericSend+0x20>
+ 8005428:	b672      	cpsid	i
+ 800542a:	e7fe      	b.n	800542a <xQueueGenericSend+0x1e>
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ 800542c:	68bb      	ldr	r3, [r7, #8]
+ 800542e:	2b00      	cmp	r3, #0
+ 8005430:	d103      	bne.n	800543a <xQueueGenericSend+0x2e>
+ 8005432:	6a3b      	ldr	r3, [r7, #32]
+ 8005434:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8005436:	2b00      	cmp	r3, #0
+ 8005438:	d101      	bne.n	800543e <xQueueGenericSend+0x32>
+ 800543a:	2301      	movs	r3, #1
+ 800543c:	e000      	b.n	8005440 <xQueueGenericSend+0x34>
+ 800543e:	2300      	movs	r3, #0
+ 8005440:	2b00      	cmp	r3, #0
+ 8005442:	d101      	bne.n	8005448 <xQueueGenericSend+0x3c>
+ 8005444:	b672      	cpsid	i
+ 8005446:	e7fe      	b.n	8005446 <xQueueGenericSend+0x3a>
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+ 8005448:	683b      	ldr	r3, [r7, #0]
+ 800544a:	2b02      	cmp	r3, #2
+ 800544c:	d103      	bne.n	8005456 <xQueueGenericSend+0x4a>
+ 800544e:	6a3b      	ldr	r3, [r7, #32]
+ 8005450:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8005452:	2b01      	cmp	r3, #1
+ 8005454:	d101      	bne.n	800545a <xQueueGenericSend+0x4e>
+ 8005456:	2301      	movs	r3, #1
+ 8005458:	e000      	b.n	800545c <xQueueGenericSend+0x50>
+ 800545a:	2300      	movs	r3, #0
+ 800545c:	2b00      	cmp	r3, #0
+ 800545e:	d101      	bne.n	8005464 <xQueueGenericSend+0x58>
+ 8005460:	b672      	cpsid	i
+ 8005462:	e7fe      	b.n	8005462 <xQueueGenericSend+0x56>
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ 8005464:	f001 f9e0 	bl	8006828 <xTaskGetSchedulerState>
+ 8005468:	1e03      	subs	r3, r0, #0
+ 800546a:	d102      	bne.n	8005472 <xQueueGenericSend+0x66>
+ 800546c:	687b      	ldr	r3, [r7, #4]
+ 800546e:	2b00      	cmp	r3, #0
+ 8005470:	d101      	bne.n	8005476 <xQueueGenericSend+0x6a>
+ 8005472:	2301      	movs	r3, #1
+ 8005474:	e000      	b.n	8005478 <xQueueGenericSend+0x6c>
+ 8005476:	2300      	movs	r3, #0
+ 8005478:	2b00      	cmp	r3, #0
+ 800547a:	d101      	bne.n	8005480 <xQueueGenericSend+0x74>
+ 800547c:	b672      	cpsid	i
+ 800547e:	e7fe      	b.n	800547e <xQueueGenericSend+0x72>
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+ 8005480:	f001 fe4e 	bl	8007120 <vPortEnterCritical>
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+ 8005484:	6a3b      	ldr	r3, [r7, #32]
+ 8005486:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8005488:	6a3b      	ldr	r3, [r7, #32]
+ 800548a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 800548c:	429a      	cmp	r2, r3
+ 800548e:	d302      	bcc.n	8005496 <xQueueGenericSend+0x8a>
+ 8005490:	683b      	ldr	r3, [r7, #0]
+ 8005492:	2b02      	cmp	r3, #2
+ 8005494:	d11e      	bne.n	80054d4 <xQueueGenericSend+0xc8>
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+ 8005496:	683a      	ldr	r2, [r7, #0]
+ 8005498:	68b9      	ldr	r1, [r7, #8]
+ 800549a:	6a3b      	ldr	r3, [r7, #32]
+ 800549c:	0018      	movs	r0, r3
+ 800549e:	f000 f99f 	bl	80057e0 <prvCopyDataToQueue>
+ 80054a2:	0003      	movs	r3, r0
+ 80054a4:	61fb      	str	r3, [r7, #28]
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ 80054a6:	6a3b      	ldr	r3, [r7, #32]
+ 80054a8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80054aa:	2b00      	cmp	r3, #0
+ 80054ac:	d009      	beq.n	80054c2 <xQueueGenericSend+0xb6>
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ 80054ae:	6a3b      	ldr	r3, [r7, #32]
+ 80054b0:	3324      	adds	r3, #36	; 0x24
+ 80054b2:	0018      	movs	r0, r3
+ 80054b4:	f000 ffc0 	bl	8006438 <xTaskRemoveFromEventList>
+ 80054b8:	1e03      	subs	r3, r0, #0
+ 80054ba:	d007      	beq.n	80054cc <xQueueGenericSend+0xc0>
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+ 80054bc:	f001 fe20 	bl	8007100 <vPortYield>
+ 80054c0:	e004      	b.n	80054cc <xQueueGenericSend+0xc0>
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+ 80054c2:	69fb      	ldr	r3, [r7, #28]
+ 80054c4:	2b00      	cmp	r3, #0
+ 80054c6:	d001      	beq.n	80054cc <xQueueGenericSend+0xc0>
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+ 80054c8:	f001 fe1a 	bl	8007100 <vPortYield>
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+ 80054cc:	f001 fe3a 	bl	8007144 <vPortExitCritical>
+				return pdPASS;
+ 80054d0:	2301      	movs	r3, #1
+ 80054d2:	e05b      	b.n	800558c <xQueueGenericSend+0x180>
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+ 80054d4:	687b      	ldr	r3, [r7, #4]
+ 80054d6:	2b00      	cmp	r3, #0
+ 80054d8:	d103      	bne.n	80054e2 <xQueueGenericSend+0xd6>
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+ 80054da:	f001 fe33 	bl	8007144 <vPortExitCritical>
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+ 80054de:	2300      	movs	r3, #0
+ 80054e0:	e054      	b.n	800558c <xQueueGenericSend+0x180>
+				}
+				else if( xEntryTimeSet == pdFALSE )
+ 80054e2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80054e4:	2b00      	cmp	r3, #0
+ 80054e6:	d106      	bne.n	80054f6 <xQueueGenericSend+0xea>
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+ 80054e8:	2314      	movs	r3, #20
+ 80054ea:	18fb      	adds	r3, r7, r3
+ 80054ec:	0018      	movs	r0, r3
+ 80054ee:	f001 f801 	bl	80064f4 <vTaskInternalSetTimeOutState>
+					xEntryTimeSet = pdTRUE;
+ 80054f2:	2301      	movs	r3, #1
+ 80054f4:	627b      	str	r3, [r7, #36]	; 0x24
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+ 80054f6:	f001 fe25 	bl	8007144 <vPortExitCritical>
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+ 80054fa:	f000 fd5f 	bl	8005fbc <vTaskSuspendAll>
+		prvLockQueue( pxQueue );
+ 80054fe:	f001 fe0f 	bl	8007120 <vPortEnterCritical>
+ 8005502:	6a3b      	ldr	r3, [r7, #32]
+ 8005504:	2244      	movs	r2, #68	; 0x44
+ 8005506:	5c9b      	ldrb	r3, [r3, r2]
+ 8005508:	b25b      	sxtb	r3, r3
+ 800550a:	3301      	adds	r3, #1
+ 800550c:	d103      	bne.n	8005516 <xQueueGenericSend+0x10a>
+ 800550e:	6a3b      	ldr	r3, [r7, #32]
+ 8005510:	2244      	movs	r2, #68	; 0x44
+ 8005512:	2100      	movs	r1, #0
+ 8005514:	5499      	strb	r1, [r3, r2]
+ 8005516:	6a3b      	ldr	r3, [r7, #32]
+ 8005518:	2245      	movs	r2, #69	; 0x45
+ 800551a:	5c9b      	ldrb	r3, [r3, r2]
+ 800551c:	b25b      	sxtb	r3, r3
+ 800551e:	3301      	adds	r3, #1
+ 8005520:	d103      	bne.n	800552a <xQueueGenericSend+0x11e>
+ 8005522:	6a3b      	ldr	r3, [r7, #32]
+ 8005524:	2245      	movs	r2, #69	; 0x45
+ 8005526:	2100      	movs	r1, #0
+ 8005528:	5499      	strb	r1, [r3, r2]
+ 800552a:	f001 fe0b 	bl	8007144 <vPortExitCritical>
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ 800552e:	1d3a      	adds	r2, r7, #4
+ 8005530:	2314      	movs	r3, #20
+ 8005532:	18fb      	adds	r3, r7, r3
+ 8005534:	0011      	movs	r1, r2
+ 8005536:	0018      	movs	r0, r3
+ 8005538:	f000 fff0 	bl	800651c <xTaskCheckForTimeOut>
+ 800553c:	1e03      	subs	r3, r0, #0
+ 800553e:	d11e      	bne.n	800557e <xQueueGenericSend+0x172>
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+ 8005540:	6a3b      	ldr	r3, [r7, #32]
+ 8005542:	0018      	movs	r0, r3
+ 8005544:	f000 fa51 	bl	80059ea <prvIsQueueFull>
+ 8005548:	1e03      	subs	r3, r0, #0
+ 800554a:	d011      	beq.n	8005570 <xQueueGenericSend+0x164>
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+ 800554c:	6a3b      	ldr	r3, [r7, #32]
+ 800554e:	3310      	adds	r3, #16
+ 8005550:	687a      	ldr	r2, [r7, #4]
+ 8005552:	0011      	movs	r1, r2
+ 8005554:	0018      	movs	r0, r3
+ 8005556:	f000 ff2b 	bl	80063b0 <vTaskPlaceOnEventList>
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+ 800555a:	6a3b      	ldr	r3, [r7, #32]
+ 800555c:	0018      	movs	r0, r3
+ 800555e:	f000 f9d0 	bl	8005902 <prvUnlockQueue>
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+ 8005562:	f000 fd6d 	bl	8006040 <xTaskResumeAll>
+ 8005566:	1e03      	subs	r3, r0, #0
+ 8005568:	d18a      	bne.n	8005480 <xQueueGenericSend+0x74>
+				{
+					portYIELD_WITHIN_API();
+ 800556a:	f001 fdc9 	bl	8007100 <vPortYield>
+ 800556e:	e787      	b.n	8005480 <xQueueGenericSend+0x74>
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+ 8005570:	6a3b      	ldr	r3, [r7, #32]
+ 8005572:	0018      	movs	r0, r3
+ 8005574:	f000 f9c5 	bl	8005902 <prvUnlockQueue>
+				( void ) xTaskResumeAll();
+ 8005578:	f000 fd62 	bl	8006040 <xTaskResumeAll>
+ 800557c:	e780      	b.n	8005480 <xQueueGenericSend+0x74>
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+ 800557e:	6a3b      	ldr	r3, [r7, #32]
+ 8005580:	0018      	movs	r0, r3
+ 8005582:	f000 f9be 	bl	8005902 <prvUnlockQueue>
+			( void ) xTaskResumeAll();
+ 8005586:	f000 fd5b 	bl	8006040 <xTaskResumeAll>
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+ 800558a:	2300      	movs	r3, #0
+		}
+	} /*lint -restore */
+}
+ 800558c:	0018      	movs	r0, r3
+ 800558e:	46bd      	mov	sp, r7
+ 8005590:	b00a      	add	sp, #40	; 0x28
+ 8005592:	bd80      	pop	{r7, pc}
+
+08005594 <xQueueGenericSendFromISR>:
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+ 8005594:	b590      	push	{r4, r7, lr}
+ 8005596:	b089      	sub	sp, #36	; 0x24
+ 8005598:	af00      	add	r7, sp, #0
+ 800559a:	60f8      	str	r0, [r7, #12]
+ 800559c:	60b9      	str	r1, [r7, #8]
+ 800559e:	607a      	str	r2, [r7, #4]
+ 80055a0:	603b      	str	r3, [r7, #0]
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+ 80055a2:	68fb      	ldr	r3, [r7, #12]
+ 80055a4:	61bb      	str	r3, [r7, #24]
+
+	configASSERT( pxQueue );
+ 80055a6:	69bb      	ldr	r3, [r7, #24]
+ 80055a8:	2b00      	cmp	r3, #0
+ 80055aa:	d101      	bne.n	80055b0 <xQueueGenericSendFromISR+0x1c>
+ 80055ac:	b672      	cpsid	i
+ 80055ae:	e7fe      	b.n	80055ae <xQueueGenericSendFromISR+0x1a>
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ 80055b0:	68bb      	ldr	r3, [r7, #8]
+ 80055b2:	2b00      	cmp	r3, #0
+ 80055b4:	d103      	bne.n	80055be <xQueueGenericSendFromISR+0x2a>
+ 80055b6:	69bb      	ldr	r3, [r7, #24]
+ 80055b8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80055ba:	2b00      	cmp	r3, #0
+ 80055bc:	d101      	bne.n	80055c2 <xQueueGenericSendFromISR+0x2e>
+ 80055be:	2301      	movs	r3, #1
+ 80055c0:	e000      	b.n	80055c4 <xQueueGenericSendFromISR+0x30>
+ 80055c2:	2300      	movs	r3, #0
+ 80055c4:	2b00      	cmp	r3, #0
+ 80055c6:	d101      	bne.n	80055cc <xQueueGenericSendFromISR+0x38>
+ 80055c8:	b672      	cpsid	i
+ 80055ca:	e7fe      	b.n	80055ca <xQueueGenericSendFromISR+0x36>
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+ 80055cc:	683b      	ldr	r3, [r7, #0]
+ 80055ce:	2b02      	cmp	r3, #2
+ 80055d0:	d103      	bne.n	80055da <xQueueGenericSendFromISR+0x46>
+ 80055d2:	69bb      	ldr	r3, [r7, #24]
+ 80055d4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80055d6:	2b01      	cmp	r3, #1
+ 80055d8:	d101      	bne.n	80055de <xQueueGenericSendFromISR+0x4a>
+ 80055da:	2301      	movs	r3, #1
+ 80055dc:	e000      	b.n	80055e0 <xQueueGenericSendFromISR+0x4c>
+ 80055de:	2300      	movs	r3, #0
+ 80055e0:	2b00      	cmp	r3, #0
+ 80055e2:	d101      	bne.n	80055e8 <xQueueGenericSendFromISR+0x54>
+ 80055e4:	b672      	cpsid	i
+ 80055e6:	e7fe      	b.n	80055e6 <xQueueGenericSendFromISR+0x52>
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ 80055e8:	f001 fdc4 	bl	8007174 <ulSetInterruptMaskFromISR>
+ 80055ec:	0003      	movs	r3, r0
+ 80055ee:	617b      	str	r3, [r7, #20]
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+ 80055f0:	69bb      	ldr	r3, [r7, #24]
+ 80055f2:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 80055f4:	69bb      	ldr	r3, [r7, #24]
+ 80055f6:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80055f8:	429a      	cmp	r2, r3
+ 80055fa:	d302      	bcc.n	8005602 <xQueueGenericSendFromISR+0x6e>
+ 80055fc:	683b      	ldr	r3, [r7, #0]
+ 80055fe:	2b02      	cmp	r3, #2
+ 8005600:	d12e      	bne.n	8005660 <xQueueGenericSendFromISR+0xcc>
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+ 8005602:	2413      	movs	r4, #19
+ 8005604:	193b      	adds	r3, r7, r4
+ 8005606:	69ba      	ldr	r2, [r7, #24]
+ 8005608:	2145      	movs	r1, #69	; 0x45
+ 800560a:	5c52      	ldrb	r2, [r2, r1]
+ 800560c:	701a      	strb	r2, [r3, #0]
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+ 800560e:	683a      	ldr	r2, [r7, #0]
+ 8005610:	68b9      	ldr	r1, [r7, #8]
+ 8005612:	69bb      	ldr	r3, [r7, #24]
+ 8005614:	0018      	movs	r0, r3
+ 8005616:	f000 f8e3 	bl	80057e0 <prvCopyDataToQueue>
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+ 800561a:	193b      	adds	r3, r7, r4
+ 800561c:	781b      	ldrb	r3, [r3, #0]
+ 800561e:	b25b      	sxtb	r3, r3
+ 8005620:	3301      	adds	r3, #1
+ 8005622:	d111      	bne.n	8005648 <xQueueGenericSendFromISR+0xb4>
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ 8005624:	69bb      	ldr	r3, [r7, #24]
+ 8005626:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8005628:	2b00      	cmp	r3, #0
+ 800562a:	d016      	beq.n	800565a <xQueueGenericSendFromISR+0xc6>
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ 800562c:	69bb      	ldr	r3, [r7, #24]
+ 800562e:	3324      	adds	r3, #36	; 0x24
+ 8005630:	0018      	movs	r0, r3
+ 8005632:	f000 ff01 	bl	8006438 <xTaskRemoveFromEventList>
+ 8005636:	1e03      	subs	r3, r0, #0
+ 8005638:	d00f      	beq.n	800565a <xQueueGenericSendFromISR+0xc6>
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+ 800563a:	687b      	ldr	r3, [r7, #4]
+ 800563c:	2b00      	cmp	r3, #0
+ 800563e:	d00c      	beq.n	800565a <xQueueGenericSendFromISR+0xc6>
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+ 8005640:	687b      	ldr	r3, [r7, #4]
+ 8005642:	2201      	movs	r2, #1
+ 8005644:	601a      	str	r2, [r3, #0]
+ 8005646:	e008      	b.n	800565a <xQueueGenericSendFromISR+0xc6>
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ 8005648:	2313      	movs	r3, #19
+ 800564a:	18fb      	adds	r3, r7, r3
+ 800564c:	781b      	ldrb	r3, [r3, #0]
+ 800564e:	3301      	adds	r3, #1
+ 8005650:	b2db      	uxtb	r3, r3
+ 8005652:	b259      	sxtb	r1, r3
+ 8005654:	69bb      	ldr	r3, [r7, #24]
+ 8005656:	2245      	movs	r2, #69	; 0x45
+ 8005658:	5499      	strb	r1, [r3, r2]
+			}
+
+			xReturn = pdPASS;
+ 800565a:	2301      	movs	r3, #1
+ 800565c:	61fb      	str	r3, [r7, #28]
+		{
+ 800565e:	e001      	b.n	8005664 <xQueueGenericSendFromISR+0xd0>
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+ 8005660:	2300      	movs	r3, #0
+ 8005662:	61fb      	str	r3, [r7, #28]
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ 8005664:	697b      	ldr	r3, [r7, #20]
+ 8005666:	0018      	movs	r0, r3
+ 8005668:	f001 fd8a 	bl	8007180 <vClearInterruptMaskFromISR>
+
+	return xReturn;
+ 800566c:	69fb      	ldr	r3, [r7, #28]
+}
+ 800566e:	0018      	movs	r0, r3
+ 8005670:	46bd      	mov	sp, r7
+ 8005672:	b009      	add	sp, #36	; 0x24
+ 8005674:	bd90      	pop	{r4, r7, pc}
+
+08005676 <xQueueReceive>:
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+ 8005676:	b580      	push	{r7, lr}
+ 8005678:	b08a      	sub	sp, #40	; 0x28
+ 800567a:	af00      	add	r7, sp, #0
+ 800567c:	60f8      	str	r0, [r7, #12]
+ 800567e:	60b9      	str	r1, [r7, #8]
+ 8005680:	607a      	str	r2, [r7, #4]
+BaseType_t xEntryTimeSet = pdFALSE;
+ 8005682:	2300      	movs	r3, #0
+ 8005684:	627b      	str	r3, [r7, #36]	; 0x24
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+ 8005686:	68fb      	ldr	r3, [r7, #12]
+ 8005688:	623b      	str	r3, [r7, #32]
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+ 800568a:	6a3b      	ldr	r3, [r7, #32]
+ 800568c:	2b00      	cmp	r3, #0
+ 800568e:	d101      	bne.n	8005694 <xQueueReceive+0x1e>
+ 8005690:	b672      	cpsid	i
+ 8005692:	e7fe      	b.n	8005692 <xQueueReceive+0x1c>
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ 8005694:	68bb      	ldr	r3, [r7, #8]
+ 8005696:	2b00      	cmp	r3, #0
+ 8005698:	d103      	bne.n	80056a2 <xQueueReceive+0x2c>
+ 800569a:	6a3b      	ldr	r3, [r7, #32]
+ 800569c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800569e:	2b00      	cmp	r3, #0
+ 80056a0:	d101      	bne.n	80056a6 <xQueueReceive+0x30>
+ 80056a2:	2301      	movs	r3, #1
+ 80056a4:	e000      	b.n	80056a8 <xQueueReceive+0x32>
+ 80056a6:	2300      	movs	r3, #0
+ 80056a8:	2b00      	cmp	r3, #0
+ 80056aa:	d101      	bne.n	80056b0 <xQueueReceive+0x3a>
+ 80056ac:	b672      	cpsid	i
+ 80056ae:	e7fe      	b.n	80056ae <xQueueReceive+0x38>
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ 80056b0:	f001 f8ba 	bl	8006828 <xTaskGetSchedulerState>
+ 80056b4:	1e03      	subs	r3, r0, #0
+ 80056b6:	d102      	bne.n	80056be <xQueueReceive+0x48>
+ 80056b8:	687b      	ldr	r3, [r7, #4]
+ 80056ba:	2b00      	cmp	r3, #0
+ 80056bc:	d101      	bne.n	80056c2 <xQueueReceive+0x4c>
+ 80056be:	2301      	movs	r3, #1
+ 80056c0:	e000      	b.n	80056c4 <xQueueReceive+0x4e>
+ 80056c2:	2300      	movs	r3, #0
+ 80056c4:	2b00      	cmp	r3, #0
+ 80056c6:	d101      	bne.n	80056cc <xQueueReceive+0x56>
+ 80056c8:	b672      	cpsid	i
+ 80056ca:	e7fe      	b.n	80056ca <xQueueReceive+0x54>
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+ 80056cc:	f001 fd28 	bl	8007120 <vPortEnterCritical>
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+ 80056d0:	6a3b      	ldr	r3, [r7, #32]
+ 80056d2:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80056d4:	61fb      	str	r3, [r7, #28]
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ 80056d6:	69fb      	ldr	r3, [r7, #28]
+ 80056d8:	2b00      	cmp	r3, #0
+ 80056da:	d01a      	beq.n	8005712 <xQueueReceive+0x9c>
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+ 80056dc:	68ba      	ldr	r2, [r7, #8]
+ 80056de:	6a3b      	ldr	r3, [r7, #32]
+ 80056e0:	0011      	movs	r1, r2
+ 80056e2:	0018      	movs	r0, r3
+ 80056e4:	f000 f8e7 	bl	80058b6 <prvCopyDataFromQueue>
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+ 80056e8:	69fb      	ldr	r3, [r7, #28]
+ 80056ea:	1e5a      	subs	r2, r3, #1
+ 80056ec:	6a3b      	ldr	r3, [r7, #32]
+ 80056ee:	639a      	str	r2, [r3, #56]	; 0x38
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ 80056f0:	6a3b      	ldr	r3, [r7, #32]
+ 80056f2:	691b      	ldr	r3, [r3, #16]
+ 80056f4:	2b00      	cmp	r3, #0
+ 80056f6:	d008      	beq.n	800570a <xQueueReceive+0x94>
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ 80056f8:	6a3b      	ldr	r3, [r7, #32]
+ 80056fa:	3310      	adds	r3, #16
+ 80056fc:	0018      	movs	r0, r3
+ 80056fe:	f000 fe9b 	bl	8006438 <xTaskRemoveFromEventList>
+ 8005702:	1e03      	subs	r3, r0, #0
+ 8005704:	d001      	beq.n	800570a <xQueueReceive+0x94>
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+ 8005706:	f001 fcfb 	bl	8007100 <vPortYield>
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+ 800570a:	f001 fd1b 	bl	8007144 <vPortExitCritical>
+				return pdPASS;
+ 800570e:	2301      	movs	r3, #1
+ 8005710:	e062      	b.n	80057d8 <xQueueReceive+0x162>
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+ 8005712:	687b      	ldr	r3, [r7, #4]
+ 8005714:	2b00      	cmp	r3, #0
+ 8005716:	d103      	bne.n	8005720 <xQueueReceive+0xaa>
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+ 8005718:	f001 fd14 	bl	8007144 <vPortExitCritical>
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+ 800571c:	2300      	movs	r3, #0
+ 800571e:	e05b      	b.n	80057d8 <xQueueReceive+0x162>
+				}
+				else if( xEntryTimeSet == pdFALSE )
+ 8005720:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8005722:	2b00      	cmp	r3, #0
+ 8005724:	d106      	bne.n	8005734 <xQueueReceive+0xbe>
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+ 8005726:	2314      	movs	r3, #20
+ 8005728:	18fb      	adds	r3, r7, r3
+ 800572a:	0018      	movs	r0, r3
+ 800572c:	f000 fee2 	bl	80064f4 <vTaskInternalSetTimeOutState>
+					xEntryTimeSet = pdTRUE;
+ 8005730:	2301      	movs	r3, #1
+ 8005732:	627b      	str	r3, [r7, #36]	; 0x24
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+ 8005734:	f001 fd06 	bl	8007144 <vPortExitCritical>
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+ 8005738:	f000 fc40 	bl	8005fbc <vTaskSuspendAll>
+		prvLockQueue( pxQueue );
+ 800573c:	f001 fcf0 	bl	8007120 <vPortEnterCritical>
+ 8005740:	6a3b      	ldr	r3, [r7, #32]
+ 8005742:	2244      	movs	r2, #68	; 0x44
+ 8005744:	5c9b      	ldrb	r3, [r3, r2]
+ 8005746:	b25b      	sxtb	r3, r3
+ 8005748:	3301      	adds	r3, #1
+ 800574a:	d103      	bne.n	8005754 <xQueueReceive+0xde>
+ 800574c:	6a3b      	ldr	r3, [r7, #32]
+ 800574e:	2244      	movs	r2, #68	; 0x44
+ 8005750:	2100      	movs	r1, #0
+ 8005752:	5499      	strb	r1, [r3, r2]
+ 8005754:	6a3b      	ldr	r3, [r7, #32]
+ 8005756:	2245      	movs	r2, #69	; 0x45
+ 8005758:	5c9b      	ldrb	r3, [r3, r2]
+ 800575a:	b25b      	sxtb	r3, r3
+ 800575c:	3301      	adds	r3, #1
+ 800575e:	d103      	bne.n	8005768 <xQueueReceive+0xf2>
+ 8005760:	6a3b      	ldr	r3, [r7, #32]
+ 8005762:	2245      	movs	r2, #69	; 0x45
+ 8005764:	2100      	movs	r1, #0
+ 8005766:	5499      	strb	r1, [r3, r2]
+ 8005768:	f001 fcec 	bl	8007144 <vPortExitCritical>
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ 800576c:	1d3a      	adds	r2, r7, #4
+ 800576e:	2314      	movs	r3, #20
+ 8005770:	18fb      	adds	r3, r7, r3
+ 8005772:	0011      	movs	r1, r2
+ 8005774:	0018      	movs	r0, r3
+ 8005776:	f000 fed1 	bl	800651c <xTaskCheckForTimeOut>
+ 800577a:	1e03      	subs	r3, r0, #0
+ 800577c:	d11e      	bne.n	80057bc <xQueueReceive+0x146>
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ 800577e:	6a3b      	ldr	r3, [r7, #32]
+ 8005780:	0018      	movs	r0, r3
+ 8005782:	f000 f91c 	bl	80059be <prvIsQueueEmpty>
+ 8005786:	1e03      	subs	r3, r0, #0
+ 8005788:	d011      	beq.n	80057ae <xQueueReceive+0x138>
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ 800578a:	6a3b      	ldr	r3, [r7, #32]
+ 800578c:	3324      	adds	r3, #36	; 0x24
+ 800578e:	687a      	ldr	r2, [r7, #4]
+ 8005790:	0011      	movs	r1, r2
+ 8005792:	0018      	movs	r0, r3
+ 8005794:	f000 fe0c 	bl	80063b0 <vTaskPlaceOnEventList>
+				prvUnlockQueue( pxQueue );
+ 8005798:	6a3b      	ldr	r3, [r7, #32]
+ 800579a:	0018      	movs	r0, r3
+ 800579c:	f000 f8b1 	bl	8005902 <prvUnlockQueue>
+				if( xTaskResumeAll() == pdFALSE )
+ 80057a0:	f000 fc4e 	bl	8006040 <xTaskResumeAll>
+ 80057a4:	1e03      	subs	r3, r0, #0
+ 80057a6:	d191      	bne.n	80056cc <xQueueReceive+0x56>
+				{
+					portYIELD_WITHIN_API();
+ 80057a8:	f001 fcaa 	bl	8007100 <vPortYield>
+ 80057ac:	e78e      	b.n	80056cc <xQueueReceive+0x56>
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+ 80057ae:	6a3b      	ldr	r3, [r7, #32]
+ 80057b0:	0018      	movs	r0, r3
+ 80057b2:	f000 f8a6 	bl	8005902 <prvUnlockQueue>
+				( void ) xTaskResumeAll();
+ 80057b6:	f000 fc43 	bl	8006040 <xTaskResumeAll>
+ 80057ba:	e787      	b.n	80056cc <xQueueReceive+0x56>
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+ 80057bc:	6a3b      	ldr	r3, [r7, #32]
+ 80057be:	0018      	movs	r0, r3
+ 80057c0:	f000 f89f 	bl	8005902 <prvUnlockQueue>
+			( void ) xTaskResumeAll();
+ 80057c4:	f000 fc3c 	bl	8006040 <xTaskResumeAll>
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ 80057c8:	6a3b      	ldr	r3, [r7, #32]
+ 80057ca:	0018      	movs	r0, r3
+ 80057cc:	f000 f8f7 	bl	80059be <prvIsQueueEmpty>
+ 80057d0:	1e03      	subs	r3, r0, #0
+ 80057d2:	d100      	bne.n	80057d6 <xQueueReceive+0x160>
+ 80057d4:	e77a      	b.n	80056cc <xQueueReceive+0x56>
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+ 80057d6:	2300      	movs	r3, #0
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+ 80057d8:	0018      	movs	r0, r3
+ 80057da:	46bd      	mov	sp, r7
+ 80057dc:	b00a      	add	sp, #40	; 0x28
+ 80057de:	bd80      	pop	{r7, pc}
+
+080057e0 <prvCopyDataToQueue>:
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+ 80057e0:	b580      	push	{r7, lr}
+ 80057e2:	b086      	sub	sp, #24
+ 80057e4:	af00      	add	r7, sp, #0
+ 80057e6:	60f8      	str	r0, [r7, #12]
+ 80057e8:	60b9      	str	r1, [r7, #8]
+ 80057ea:	607a      	str	r2, [r7, #4]
+BaseType_t xReturn = pdFALSE;
+ 80057ec:	2300      	movs	r3, #0
+ 80057ee:	617b      	str	r3, [r7, #20]
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+ 80057f0:	68fb      	ldr	r3, [r7, #12]
+ 80057f2:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80057f4:	613b      	str	r3, [r7, #16]
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+ 80057f6:	68fb      	ldr	r3, [r7, #12]
+ 80057f8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80057fa:	2b00      	cmp	r3, #0
+ 80057fc:	d10e      	bne.n	800581c <prvCopyDataToQueue+0x3c>
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ 80057fe:	68fb      	ldr	r3, [r7, #12]
+ 8005800:	681b      	ldr	r3, [r3, #0]
+ 8005802:	2b00      	cmp	r3, #0
+ 8005804:	d14e      	bne.n	80058a4 <prvCopyDataToQueue+0xc4>
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+ 8005806:	68fb      	ldr	r3, [r7, #12]
+ 8005808:	689b      	ldr	r3, [r3, #8]
+ 800580a:	0018      	movs	r0, r3
+ 800580c:	f001 f828 	bl	8006860 <xTaskPriorityDisinherit>
+ 8005810:	0003      	movs	r3, r0
+ 8005812:	617b      	str	r3, [r7, #20]
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+ 8005814:	68fb      	ldr	r3, [r7, #12]
+ 8005816:	2200      	movs	r2, #0
+ 8005818:	609a      	str	r2, [r3, #8]
+ 800581a:	e043      	b.n	80058a4 <prvCopyDataToQueue+0xc4>
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+ 800581c:	687b      	ldr	r3, [r7, #4]
+ 800581e:	2b00      	cmp	r3, #0
+ 8005820:	d119      	bne.n	8005856 <prvCopyDataToQueue+0x76>
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+ 8005822:	68fb      	ldr	r3, [r7, #12]
+ 8005824:	6858      	ldr	r0, [r3, #4]
+ 8005826:	68fb      	ldr	r3, [r7, #12]
+ 8005828:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+ 800582a:	68bb      	ldr	r3, [r7, #8]
+ 800582c:	0019      	movs	r1, r3
+ 800582e:	f001 ffbd 	bl	80077ac <memcpy>
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ 8005832:	68fb      	ldr	r3, [r7, #12]
+ 8005834:	685a      	ldr	r2, [r3, #4]
+ 8005836:	68fb      	ldr	r3, [r7, #12]
+ 8005838:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800583a:	18d2      	adds	r2, r2, r3
+ 800583c:	68fb      	ldr	r3, [r7, #12]
+ 800583e:	605a      	str	r2, [r3, #4]
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ 8005840:	68fb      	ldr	r3, [r7, #12]
+ 8005842:	685a      	ldr	r2, [r3, #4]
+ 8005844:	68fb      	ldr	r3, [r7, #12]
+ 8005846:	689b      	ldr	r3, [r3, #8]
+ 8005848:	429a      	cmp	r2, r3
+ 800584a:	d32b      	bcc.n	80058a4 <prvCopyDataToQueue+0xc4>
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+ 800584c:	68fb      	ldr	r3, [r7, #12]
+ 800584e:	681a      	ldr	r2, [r3, #0]
+ 8005850:	68fb      	ldr	r3, [r7, #12]
+ 8005852:	605a      	str	r2, [r3, #4]
+ 8005854:	e026      	b.n	80058a4 <prvCopyDataToQueue+0xc4>
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+ 8005856:	68fb      	ldr	r3, [r7, #12]
+ 8005858:	68d8      	ldr	r0, [r3, #12]
+ 800585a:	68fb      	ldr	r3, [r7, #12]
+ 800585c:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+ 800585e:	68bb      	ldr	r3, [r7, #8]
+ 8005860:	0019      	movs	r1, r3
+ 8005862:	f001 ffa3 	bl	80077ac <memcpy>
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+ 8005866:	68fb      	ldr	r3, [r7, #12]
+ 8005868:	68da      	ldr	r2, [r3, #12]
+ 800586a:	68fb      	ldr	r3, [r7, #12]
+ 800586c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800586e:	425b      	negs	r3, r3
+ 8005870:	18d2      	adds	r2, r2, r3
+ 8005872:	68fb      	ldr	r3, [r7, #12]
+ 8005874:	60da      	str	r2, [r3, #12]
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ 8005876:	68fb      	ldr	r3, [r7, #12]
+ 8005878:	68da      	ldr	r2, [r3, #12]
+ 800587a:	68fb      	ldr	r3, [r7, #12]
+ 800587c:	681b      	ldr	r3, [r3, #0]
+ 800587e:	429a      	cmp	r2, r3
+ 8005880:	d207      	bcs.n	8005892 <prvCopyDataToQueue+0xb2>
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+ 8005882:	68fb      	ldr	r3, [r7, #12]
+ 8005884:	689a      	ldr	r2, [r3, #8]
+ 8005886:	68fb      	ldr	r3, [r7, #12]
+ 8005888:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800588a:	425b      	negs	r3, r3
+ 800588c:	18d2      	adds	r2, r2, r3
+ 800588e:	68fb      	ldr	r3, [r7, #12]
+ 8005890:	60da      	str	r2, [r3, #12]
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+ 8005892:	687b      	ldr	r3, [r7, #4]
+ 8005894:	2b02      	cmp	r3, #2
+ 8005896:	d105      	bne.n	80058a4 <prvCopyDataToQueue+0xc4>
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ 8005898:	693b      	ldr	r3, [r7, #16]
+ 800589a:	2b00      	cmp	r3, #0
+ 800589c:	d002      	beq.n	80058a4 <prvCopyDataToQueue+0xc4>
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+ 800589e:	693b      	ldr	r3, [r7, #16]
+ 80058a0:	3b01      	subs	r3, #1
+ 80058a2:	613b      	str	r3, [r7, #16]
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+ 80058a4:	693b      	ldr	r3, [r7, #16]
+ 80058a6:	1c5a      	adds	r2, r3, #1
+ 80058a8:	68fb      	ldr	r3, [r7, #12]
+ 80058aa:	639a      	str	r2, [r3, #56]	; 0x38
+
+	return xReturn;
+ 80058ac:	697b      	ldr	r3, [r7, #20]
+}
+ 80058ae:	0018      	movs	r0, r3
+ 80058b0:	46bd      	mov	sp, r7
+ 80058b2:	b006      	add	sp, #24
+ 80058b4:	bd80      	pop	{r7, pc}
+
+080058b6 <prvCopyDataFromQueue>:
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+ 80058b6:	b580      	push	{r7, lr}
+ 80058b8:	b082      	sub	sp, #8
+ 80058ba:	af00      	add	r7, sp, #0
+ 80058bc:	6078      	str	r0, [r7, #4]
+ 80058be:	6039      	str	r1, [r7, #0]
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+ 80058c0:	687b      	ldr	r3, [r7, #4]
+ 80058c2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80058c4:	2b00      	cmp	r3, #0
+ 80058c6:	d018      	beq.n	80058fa <prvCopyDataFromQueue+0x44>
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ 80058c8:	687b      	ldr	r3, [r7, #4]
+ 80058ca:	68da      	ldr	r2, [r3, #12]
+ 80058cc:	687b      	ldr	r3, [r7, #4]
+ 80058ce:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80058d0:	18d2      	adds	r2, r2, r3
+ 80058d2:	687b      	ldr	r3, [r7, #4]
+ 80058d4:	60da      	str	r2, [r3, #12]
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+ 80058d6:	687b      	ldr	r3, [r7, #4]
+ 80058d8:	68da      	ldr	r2, [r3, #12]
+ 80058da:	687b      	ldr	r3, [r7, #4]
+ 80058dc:	689b      	ldr	r3, [r3, #8]
+ 80058de:	429a      	cmp	r2, r3
+ 80058e0:	d303      	bcc.n	80058ea <prvCopyDataFromQueue+0x34>
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+ 80058e2:	687b      	ldr	r3, [r7, #4]
+ 80058e4:	681a      	ldr	r2, [r3, #0]
+ 80058e6:	687b      	ldr	r3, [r7, #4]
+ 80058e8:	60da      	str	r2, [r3, #12]
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+ 80058ea:	687b      	ldr	r3, [r7, #4]
+ 80058ec:	68d9      	ldr	r1, [r3, #12]
+ 80058ee:	687b      	ldr	r3, [r7, #4]
+ 80058f0:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+ 80058f2:	683b      	ldr	r3, [r7, #0]
+ 80058f4:	0018      	movs	r0, r3
+ 80058f6:	f001 ff59 	bl	80077ac <memcpy>
+	}
+}
+ 80058fa:	46c0      	nop			; (mov r8, r8)
+ 80058fc:	46bd      	mov	sp, r7
+ 80058fe:	b002      	add	sp, #8
+ 8005900:	bd80      	pop	{r7, pc}
+
+08005902 <prvUnlockQueue>:
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+ 8005902:	b580      	push	{r7, lr}
+ 8005904:	b084      	sub	sp, #16
+ 8005906:	af00      	add	r7, sp, #0
+ 8005908:	6078      	str	r0, [r7, #4]
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+ 800590a:	f001 fc09 	bl	8007120 <vPortEnterCritical>
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+ 800590e:	230f      	movs	r3, #15
+ 8005910:	18fb      	adds	r3, r7, r3
+ 8005912:	687a      	ldr	r2, [r7, #4]
+ 8005914:	2145      	movs	r1, #69	; 0x45
+ 8005916:	5c52      	ldrb	r2, [r2, r1]
+ 8005918:	701a      	strb	r2, [r3, #0]
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+ 800591a:	e013      	b.n	8005944 <prvUnlockQueue+0x42>
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ 800591c:	687b      	ldr	r3, [r7, #4]
+ 800591e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8005920:	2b00      	cmp	r3, #0
+ 8005922:	d016      	beq.n	8005952 <prvUnlockQueue+0x50>
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ 8005924:	687b      	ldr	r3, [r7, #4]
+ 8005926:	3324      	adds	r3, #36	; 0x24
+ 8005928:	0018      	movs	r0, r3
+ 800592a:	f000 fd85 	bl	8006438 <xTaskRemoveFromEventList>
+ 800592e:	1e03      	subs	r3, r0, #0
+ 8005930:	d001      	beq.n	8005936 <prvUnlockQueue+0x34>
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+ 8005932:	f000 fe53 	bl	80065dc <vTaskMissedYield>
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+ 8005936:	210f      	movs	r1, #15
+ 8005938:	187b      	adds	r3, r7, r1
+ 800593a:	781b      	ldrb	r3, [r3, #0]
+ 800593c:	3b01      	subs	r3, #1
+ 800593e:	b2da      	uxtb	r2, r3
+ 8005940:	187b      	adds	r3, r7, r1
+ 8005942:	701a      	strb	r2, [r3, #0]
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+ 8005944:	230f      	movs	r3, #15
+ 8005946:	18fb      	adds	r3, r7, r3
+ 8005948:	781b      	ldrb	r3, [r3, #0]
+ 800594a:	b25b      	sxtb	r3, r3
+ 800594c:	2b00      	cmp	r3, #0
+ 800594e:	dce5      	bgt.n	800591c <prvUnlockQueue+0x1a>
+ 8005950:	e000      	b.n	8005954 <prvUnlockQueue+0x52>
+					break;
+ 8005952:	46c0      	nop			; (mov r8, r8)
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+ 8005954:	687b      	ldr	r3, [r7, #4]
+ 8005956:	2245      	movs	r2, #69	; 0x45
+ 8005958:	21ff      	movs	r1, #255	; 0xff
+ 800595a:	5499      	strb	r1, [r3, r2]
+	}
+	taskEXIT_CRITICAL();
+ 800595c:	f001 fbf2 	bl	8007144 <vPortExitCritical>
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+ 8005960:	f001 fbde 	bl	8007120 <vPortEnterCritical>
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+ 8005964:	230e      	movs	r3, #14
+ 8005966:	18fb      	adds	r3, r7, r3
+ 8005968:	687a      	ldr	r2, [r7, #4]
+ 800596a:	2144      	movs	r1, #68	; 0x44
+ 800596c:	5c52      	ldrb	r2, [r2, r1]
+ 800596e:	701a      	strb	r2, [r3, #0]
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+ 8005970:	e013      	b.n	800599a <prvUnlockQueue+0x98>
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ 8005972:	687b      	ldr	r3, [r7, #4]
+ 8005974:	691b      	ldr	r3, [r3, #16]
+ 8005976:	2b00      	cmp	r3, #0
+ 8005978:	d016      	beq.n	80059a8 <prvUnlockQueue+0xa6>
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ 800597a:	687b      	ldr	r3, [r7, #4]
+ 800597c:	3310      	adds	r3, #16
+ 800597e:	0018      	movs	r0, r3
+ 8005980:	f000 fd5a 	bl	8006438 <xTaskRemoveFromEventList>
+ 8005984:	1e03      	subs	r3, r0, #0
+ 8005986:	d001      	beq.n	800598c <prvUnlockQueue+0x8a>
+				{
+					vTaskMissedYield();
+ 8005988:	f000 fe28 	bl	80065dc <vTaskMissedYield>
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+ 800598c:	210e      	movs	r1, #14
+ 800598e:	187b      	adds	r3, r7, r1
+ 8005990:	781b      	ldrb	r3, [r3, #0]
+ 8005992:	3b01      	subs	r3, #1
+ 8005994:	b2da      	uxtb	r2, r3
+ 8005996:	187b      	adds	r3, r7, r1
+ 8005998:	701a      	strb	r2, [r3, #0]
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+ 800599a:	230e      	movs	r3, #14
+ 800599c:	18fb      	adds	r3, r7, r3
+ 800599e:	781b      	ldrb	r3, [r3, #0]
+ 80059a0:	b25b      	sxtb	r3, r3
+ 80059a2:	2b00      	cmp	r3, #0
+ 80059a4:	dce5      	bgt.n	8005972 <prvUnlockQueue+0x70>
+ 80059a6:	e000      	b.n	80059aa <prvUnlockQueue+0xa8>
+			}
+			else
+			{
+				break;
+ 80059a8:	46c0      	nop			; (mov r8, r8)
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+ 80059aa:	687b      	ldr	r3, [r7, #4]
+ 80059ac:	2244      	movs	r2, #68	; 0x44
+ 80059ae:	21ff      	movs	r1, #255	; 0xff
+ 80059b0:	5499      	strb	r1, [r3, r2]
+	}
+	taskEXIT_CRITICAL();
+ 80059b2:	f001 fbc7 	bl	8007144 <vPortExitCritical>
+}
+ 80059b6:	46c0      	nop			; (mov r8, r8)
+ 80059b8:	46bd      	mov	sp, r7
+ 80059ba:	b004      	add	sp, #16
+ 80059bc:	bd80      	pop	{r7, pc}
+
+080059be <prvIsQueueEmpty>:
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+ 80059be:	b580      	push	{r7, lr}
+ 80059c0:	b084      	sub	sp, #16
+ 80059c2:	af00      	add	r7, sp, #0
+ 80059c4:	6078      	str	r0, [r7, #4]
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+ 80059c6:	f001 fbab 	bl	8007120 <vPortEnterCritical>
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+ 80059ca:	687b      	ldr	r3, [r7, #4]
+ 80059cc:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80059ce:	2b00      	cmp	r3, #0
+ 80059d0:	d102      	bne.n	80059d8 <prvIsQueueEmpty+0x1a>
+		{
+			xReturn = pdTRUE;
+ 80059d2:	2301      	movs	r3, #1
+ 80059d4:	60fb      	str	r3, [r7, #12]
+ 80059d6:	e001      	b.n	80059dc <prvIsQueueEmpty+0x1e>
+		}
+		else
+		{
+			xReturn = pdFALSE;
+ 80059d8:	2300      	movs	r3, #0
+ 80059da:	60fb      	str	r3, [r7, #12]
+		}
+	}
+	taskEXIT_CRITICAL();
+ 80059dc:	f001 fbb2 	bl	8007144 <vPortExitCritical>
+
+	return xReturn;
+ 80059e0:	68fb      	ldr	r3, [r7, #12]
+}
+ 80059e2:	0018      	movs	r0, r3
+ 80059e4:	46bd      	mov	sp, r7
+ 80059e6:	b004      	add	sp, #16
+ 80059e8:	bd80      	pop	{r7, pc}
+
+080059ea <prvIsQueueFull>:
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+ 80059ea:	b580      	push	{r7, lr}
+ 80059ec:	b084      	sub	sp, #16
+ 80059ee:	af00      	add	r7, sp, #0
+ 80059f0:	6078      	str	r0, [r7, #4]
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+ 80059f2:	f001 fb95 	bl	8007120 <vPortEnterCritical>
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+ 80059f6:	687b      	ldr	r3, [r7, #4]
+ 80059f8:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 80059fa:	687b      	ldr	r3, [r7, #4]
+ 80059fc:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80059fe:	429a      	cmp	r2, r3
+ 8005a00:	d102      	bne.n	8005a08 <prvIsQueueFull+0x1e>
+		{
+			xReturn = pdTRUE;
+ 8005a02:	2301      	movs	r3, #1
+ 8005a04:	60fb      	str	r3, [r7, #12]
+ 8005a06:	e001      	b.n	8005a0c <prvIsQueueFull+0x22>
+		}
+		else
+		{
+			xReturn = pdFALSE;
+ 8005a08:	2300      	movs	r3, #0
+ 8005a0a:	60fb      	str	r3, [r7, #12]
+		}
+	}
+	taskEXIT_CRITICAL();
+ 8005a0c:	f001 fb9a 	bl	8007144 <vPortExitCritical>
+
+	return xReturn;
+ 8005a10:	68fb      	ldr	r3, [r7, #12]
+}
+ 8005a12:	0018      	movs	r0, r3
+ 8005a14:	46bd      	mov	sp, r7
+ 8005a16:	b004      	add	sp, #16
+ 8005a18:	bd80      	pop	{r7, pc}
+	...
+
+08005a1c <vQueueAddToRegistry>:
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+ 8005a1c:	b580      	push	{r7, lr}
+ 8005a1e:	b084      	sub	sp, #16
+ 8005a20:	af00      	add	r7, sp, #0
+ 8005a22:	6078      	str	r0, [r7, #4]
+ 8005a24:	6039      	str	r1, [r7, #0]
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ 8005a26:	2300      	movs	r3, #0
+ 8005a28:	60fb      	str	r3, [r7, #12]
+ 8005a2a:	e015      	b.n	8005a58 <vQueueAddToRegistry+0x3c>
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+ 8005a2c:	4b0e      	ldr	r3, [pc, #56]	; (8005a68 <vQueueAddToRegistry+0x4c>)
+ 8005a2e:	68fa      	ldr	r2, [r7, #12]
+ 8005a30:	00d2      	lsls	r2, r2, #3
+ 8005a32:	58d3      	ldr	r3, [r2, r3]
+ 8005a34:	2b00      	cmp	r3, #0
+ 8005a36:	d10c      	bne.n	8005a52 <vQueueAddToRegistry+0x36>
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+ 8005a38:	4b0b      	ldr	r3, [pc, #44]	; (8005a68 <vQueueAddToRegistry+0x4c>)
+ 8005a3a:	68fa      	ldr	r2, [r7, #12]
+ 8005a3c:	00d2      	lsls	r2, r2, #3
+ 8005a3e:	6839      	ldr	r1, [r7, #0]
+ 8005a40:	50d1      	str	r1, [r2, r3]
+				xQueueRegistry[ ux ].xHandle = xQueue;
+ 8005a42:	4a09      	ldr	r2, [pc, #36]	; (8005a68 <vQueueAddToRegistry+0x4c>)
+ 8005a44:	68fb      	ldr	r3, [r7, #12]
+ 8005a46:	00db      	lsls	r3, r3, #3
+ 8005a48:	18d3      	adds	r3, r2, r3
+ 8005a4a:	3304      	adds	r3, #4
+ 8005a4c:	687a      	ldr	r2, [r7, #4]
+ 8005a4e:	601a      	str	r2, [r3, #0]
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+ 8005a50:	e006      	b.n	8005a60 <vQueueAddToRegistry+0x44>
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ 8005a52:	68fb      	ldr	r3, [r7, #12]
+ 8005a54:	3301      	adds	r3, #1
+ 8005a56:	60fb      	str	r3, [r7, #12]
+ 8005a58:	68fb      	ldr	r3, [r7, #12]
+ 8005a5a:	2b07      	cmp	r3, #7
+ 8005a5c:	d9e6      	bls.n	8005a2c <vQueueAddToRegistry+0x10>
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+ 8005a5e:	46c0      	nop			; (mov r8, r8)
+ 8005a60:	46c0      	nop			; (mov r8, r8)
+ 8005a62:	46bd      	mov	sp, r7
+ 8005a64:	b004      	add	sp, #16
+ 8005a66:	bd80      	pop	{r7, pc}
+ 8005a68:	2000196c 	.word	0x2000196c
+
+08005a6c <vQueueWaitForMessageRestricted>:
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+ 8005a6c:	b580      	push	{r7, lr}
+ 8005a6e:	b086      	sub	sp, #24
+ 8005a70:	af00      	add	r7, sp, #0
+ 8005a72:	60f8      	str	r0, [r7, #12]
+ 8005a74:	60b9      	str	r1, [r7, #8]
+ 8005a76:	607a      	str	r2, [r7, #4]
+	Queue_t * const pxQueue = xQueue;
+ 8005a78:	68fb      	ldr	r3, [r7, #12]
+ 8005a7a:	617b      	str	r3, [r7, #20]
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+ 8005a7c:	f001 fb50 	bl	8007120 <vPortEnterCritical>
+ 8005a80:	697b      	ldr	r3, [r7, #20]
+ 8005a82:	2244      	movs	r2, #68	; 0x44
+ 8005a84:	5c9b      	ldrb	r3, [r3, r2]
+ 8005a86:	b25b      	sxtb	r3, r3
+ 8005a88:	3301      	adds	r3, #1
+ 8005a8a:	d103      	bne.n	8005a94 <vQueueWaitForMessageRestricted+0x28>
+ 8005a8c:	697b      	ldr	r3, [r7, #20]
+ 8005a8e:	2244      	movs	r2, #68	; 0x44
+ 8005a90:	2100      	movs	r1, #0
+ 8005a92:	5499      	strb	r1, [r3, r2]
+ 8005a94:	697b      	ldr	r3, [r7, #20]
+ 8005a96:	2245      	movs	r2, #69	; 0x45
+ 8005a98:	5c9b      	ldrb	r3, [r3, r2]
+ 8005a9a:	b25b      	sxtb	r3, r3
+ 8005a9c:	3301      	adds	r3, #1
+ 8005a9e:	d103      	bne.n	8005aa8 <vQueueWaitForMessageRestricted+0x3c>
+ 8005aa0:	697b      	ldr	r3, [r7, #20]
+ 8005aa2:	2245      	movs	r2, #69	; 0x45
+ 8005aa4:	2100      	movs	r1, #0
+ 8005aa6:	5499      	strb	r1, [r3, r2]
+ 8005aa8:	f001 fb4c 	bl	8007144 <vPortExitCritical>
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+ 8005aac:	697b      	ldr	r3, [r7, #20]
+ 8005aae:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8005ab0:	2b00      	cmp	r3, #0
+ 8005ab2:	d106      	bne.n	8005ac2 <vQueueWaitForMessageRestricted+0x56>
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+ 8005ab4:	697b      	ldr	r3, [r7, #20]
+ 8005ab6:	3324      	adds	r3, #36	; 0x24
+ 8005ab8:	687a      	ldr	r2, [r7, #4]
+ 8005aba:	68b9      	ldr	r1, [r7, #8]
+ 8005abc:	0018      	movs	r0, r3
+ 8005abe:	f000 fc95 	bl	80063ec <vTaskPlaceOnEventListRestricted>
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+ 8005ac2:	697b      	ldr	r3, [r7, #20]
+ 8005ac4:	0018      	movs	r0, r3
+ 8005ac6:	f7ff ff1c 	bl	8005902 <prvUnlockQueue>
+	}
+ 8005aca:	46c0      	nop			; (mov r8, r8)
+ 8005acc:	46bd      	mov	sp, r7
+ 8005ace:	b006      	add	sp, #24
+ 8005ad0:	bd80      	pop	{r7, pc}
+
+08005ad2 <xTaskCreateStatic>:
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+ 8005ad2:	b590      	push	{r4, r7, lr}
+ 8005ad4:	b08d      	sub	sp, #52	; 0x34
+ 8005ad6:	af04      	add	r7, sp, #16
+ 8005ad8:	60f8      	str	r0, [r7, #12]
+ 8005ada:	60b9      	str	r1, [r7, #8]
+ 8005adc:	607a      	str	r2, [r7, #4]
+ 8005ade:	603b      	str	r3, [r7, #0]
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+ 8005ae0:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8005ae2:	2b00      	cmp	r3, #0
+ 8005ae4:	d101      	bne.n	8005aea <xTaskCreateStatic+0x18>
+ 8005ae6:	b672      	cpsid	i
+ 8005ae8:	e7fe      	b.n	8005ae8 <xTaskCreateStatic+0x16>
+		configASSERT( pxTaskBuffer != NULL );
+ 8005aea:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8005aec:	2b00      	cmp	r3, #0
+ 8005aee:	d101      	bne.n	8005af4 <xTaskCreateStatic+0x22>
+ 8005af0:	b672      	cpsid	i
+ 8005af2:	e7fe      	b.n	8005af2 <xTaskCreateStatic+0x20>
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+ 8005af4:	235c      	movs	r3, #92	; 0x5c
+ 8005af6:	617b      	str	r3, [r7, #20]
+			configASSERT( xSize == sizeof( TCB_t ) );
+ 8005af8:	697b      	ldr	r3, [r7, #20]
+ 8005afa:	2b5c      	cmp	r3, #92	; 0x5c
+ 8005afc:	d001      	beq.n	8005b02 <xTaskCreateStatic+0x30>
+ 8005afe:	b672      	cpsid	i
+ 8005b00:	e7fe      	b.n	8005b00 <xTaskCreateStatic+0x2e>
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+ 8005b02:	697b      	ldr	r3, [r7, #20]
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+ 8005b04:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8005b06:	2b00      	cmp	r3, #0
+ 8005b08:	d020      	beq.n	8005b4c <xTaskCreateStatic+0x7a>
+ 8005b0a:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8005b0c:	2b00      	cmp	r3, #0
+ 8005b0e:	d01d      	beq.n	8005b4c <xTaskCreateStatic+0x7a>
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ 8005b10:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8005b12:	61fb      	str	r3, [r7, #28]
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+ 8005b14:	69fb      	ldr	r3, [r7, #28]
+ 8005b16:	6b7a      	ldr	r2, [r7, #52]	; 0x34
+ 8005b18:	631a      	str	r2, [r3, #48]	; 0x30
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+ 8005b1a:	69fb      	ldr	r3, [r7, #28]
+ 8005b1c:	2259      	movs	r2, #89	; 0x59
+ 8005b1e:	2102      	movs	r1, #2
+ 8005b20:	5499      	strb	r1, [r3, r2]
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+ 8005b22:	683c      	ldr	r4, [r7, #0]
+ 8005b24:	687a      	ldr	r2, [r7, #4]
+ 8005b26:	68b9      	ldr	r1, [r7, #8]
+ 8005b28:	68f8      	ldr	r0, [r7, #12]
+ 8005b2a:	2300      	movs	r3, #0
+ 8005b2c:	9303      	str	r3, [sp, #12]
+ 8005b2e:	69fb      	ldr	r3, [r7, #28]
+ 8005b30:	9302      	str	r3, [sp, #8]
+ 8005b32:	2318      	movs	r3, #24
+ 8005b34:	18fb      	adds	r3, r7, r3
+ 8005b36:	9301      	str	r3, [sp, #4]
+ 8005b38:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8005b3a:	9300      	str	r3, [sp, #0]
+ 8005b3c:	0023      	movs	r3, r4
+ 8005b3e:	f000 f859 	bl	8005bf4 <prvInitialiseNewTask>
+			prvAddNewTaskToReadyList( pxNewTCB );
+ 8005b42:	69fb      	ldr	r3, [r7, #28]
+ 8005b44:	0018      	movs	r0, r3
+ 8005b46:	f000 f8e3 	bl	8005d10 <prvAddNewTaskToReadyList>
+ 8005b4a:	e001      	b.n	8005b50 <xTaskCreateStatic+0x7e>
+		}
+		else
+		{
+			xReturn = NULL;
+ 8005b4c:	2300      	movs	r3, #0
+ 8005b4e:	61bb      	str	r3, [r7, #24]
+		}
+
+		return xReturn;
+ 8005b50:	69bb      	ldr	r3, [r7, #24]
+	}
+ 8005b52:	0018      	movs	r0, r3
+ 8005b54:	46bd      	mov	sp, r7
+ 8005b56:	b009      	add	sp, #36	; 0x24
+ 8005b58:	bd90      	pop	{r4, r7, pc}
+
+08005b5a <xTaskCreate>:
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+ 8005b5a:	b590      	push	{r4, r7, lr}
+ 8005b5c:	b08d      	sub	sp, #52	; 0x34
+ 8005b5e:	af04      	add	r7, sp, #16
+ 8005b60:	60f8      	str	r0, [r7, #12]
+ 8005b62:	60b9      	str	r1, [r7, #8]
+ 8005b64:	603b      	str	r3, [r7, #0]
+ 8005b66:	1dbb      	adds	r3, r7, #6
+ 8005b68:	801a      	strh	r2, [r3, #0]
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+ 8005b6a:	1dbb      	adds	r3, r7, #6
+ 8005b6c:	881b      	ldrh	r3, [r3, #0]
+ 8005b6e:	009b      	lsls	r3, r3, #2
+ 8005b70:	0018      	movs	r0, r3
+ 8005b72:	f001 fc51 	bl	8007418 <pvPortMalloc>
+ 8005b76:	0003      	movs	r3, r0
+ 8005b78:	617b      	str	r3, [r7, #20]
+
+			if( pxStack != NULL )
+ 8005b7a:	697b      	ldr	r3, [r7, #20]
+ 8005b7c:	2b00      	cmp	r3, #0
+ 8005b7e:	d010      	beq.n	8005ba2 <xTaskCreate+0x48>
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+ 8005b80:	205c      	movs	r0, #92	; 0x5c
+ 8005b82:	f001 fc49 	bl	8007418 <pvPortMalloc>
+ 8005b86:	0003      	movs	r3, r0
+ 8005b88:	61fb      	str	r3, [r7, #28]
+
+				if( pxNewTCB != NULL )
+ 8005b8a:	69fb      	ldr	r3, [r7, #28]
+ 8005b8c:	2b00      	cmp	r3, #0
+ 8005b8e:	d003      	beq.n	8005b98 <xTaskCreate+0x3e>
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+ 8005b90:	69fb      	ldr	r3, [r7, #28]
+ 8005b92:	697a      	ldr	r2, [r7, #20]
+ 8005b94:	631a      	str	r2, [r3, #48]	; 0x30
+ 8005b96:	e006      	b.n	8005ba6 <xTaskCreate+0x4c>
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+ 8005b98:	697b      	ldr	r3, [r7, #20]
+ 8005b9a:	0018      	movs	r0, r3
+ 8005b9c:	f001 fce2 	bl	8007564 <vPortFree>
+ 8005ba0:	e001      	b.n	8005ba6 <xTaskCreate+0x4c>
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+ 8005ba2:	2300      	movs	r3, #0
+ 8005ba4:	61fb      	str	r3, [r7, #28]
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+ 8005ba6:	69fb      	ldr	r3, [r7, #28]
+ 8005ba8:	2b00      	cmp	r3, #0
+ 8005baa:	d01a      	beq.n	8005be2 <xTaskCreate+0x88>
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+ 8005bac:	69fb      	ldr	r3, [r7, #28]
+ 8005bae:	2259      	movs	r2, #89	; 0x59
+ 8005bb0:	2100      	movs	r1, #0
+ 8005bb2:	5499      	strb	r1, [r3, r2]
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+ 8005bb4:	1dbb      	adds	r3, r7, #6
+ 8005bb6:	881a      	ldrh	r2, [r3, #0]
+ 8005bb8:	683c      	ldr	r4, [r7, #0]
+ 8005bba:	68b9      	ldr	r1, [r7, #8]
+ 8005bbc:	68f8      	ldr	r0, [r7, #12]
+ 8005bbe:	2300      	movs	r3, #0
+ 8005bc0:	9303      	str	r3, [sp, #12]
+ 8005bc2:	69fb      	ldr	r3, [r7, #28]
+ 8005bc4:	9302      	str	r3, [sp, #8]
+ 8005bc6:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8005bc8:	9301      	str	r3, [sp, #4]
+ 8005bca:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8005bcc:	9300      	str	r3, [sp, #0]
+ 8005bce:	0023      	movs	r3, r4
+ 8005bd0:	f000 f810 	bl	8005bf4 <prvInitialiseNewTask>
+			prvAddNewTaskToReadyList( pxNewTCB );
+ 8005bd4:	69fb      	ldr	r3, [r7, #28]
+ 8005bd6:	0018      	movs	r0, r3
+ 8005bd8:	f000 f89a 	bl	8005d10 <prvAddNewTaskToReadyList>
+			xReturn = pdPASS;
+ 8005bdc:	2301      	movs	r3, #1
+ 8005bde:	61bb      	str	r3, [r7, #24]
+ 8005be0:	e002      	b.n	8005be8 <xTaskCreate+0x8e>
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ 8005be2:	2301      	movs	r3, #1
+ 8005be4:	425b      	negs	r3, r3
+ 8005be6:	61bb      	str	r3, [r7, #24]
+		}
+
+		return xReturn;
+ 8005be8:	69bb      	ldr	r3, [r7, #24]
+	}
+ 8005bea:	0018      	movs	r0, r3
+ 8005bec:	46bd      	mov	sp, r7
+ 8005bee:	b009      	add	sp, #36	; 0x24
+ 8005bf0:	bd90      	pop	{r4, r7, pc}
+	...
+
+08005bf4 <prvInitialiseNewTask>:
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+ 8005bf4:	b580      	push	{r7, lr}
+ 8005bf6:	b086      	sub	sp, #24
+ 8005bf8:	af00      	add	r7, sp, #0
+ 8005bfa:	60f8      	str	r0, [r7, #12]
+ 8005bfc:	60b9      	str	r1, [r7, #8]
+ 8005bfe:	607a      	str	r2, [r7, #4]
+ 8005c00:	603b      	str	r3, [r7, #0]
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+ 8005c02:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005c04:	6b18      	ldr	r0, [r3, #48]	; 0x30
+ 8005c06:	687b      	ldr	r3, [r7, #4]
+ 8005c08:	009b      	lsls	r3, r3, #2
+ 8005c0a:	001a      	movs	r2, r3
+ 8005c0c:	21a5      	movs	r1, #165	; 0xa5
+ 8005c0e:	f001 fdd6 	bl	80077be <memset>
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+ 8005c12:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005c14:	6b1a      	ldr	r2, [r3, #48]	; 0x30
+ 8005c16:	687b      	ldr	r3, [r7, #4]
+ 8005c18:	493c      	ldr	r1, [pc, #240]	; (8005d0c <prvInitialiseNewTask+0x118>)
+ 8005c1a:	468c      	mov	ip, r1
+ 8005c1c:	4463      	add	r3, ip
+ 8005c1e:	009b      	lsls	r3, r3, #2
+ 8005c20:	18d3      	adds	r3, r2, r3
+ 8005c22:	613b      	str	r3, [r7, #16]
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+ 8005c24:	693b      	ldr	r3, [r7, #16]
+ 8005c26:	2207      	movs	r2, #7
+ 8005c28:	4393      	bics	r3, r2
+ 8005c2a:	613b      	str	r3, [r7, #16]
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+ 8005c2c:	693b      	ldr	r3, [r7, #16]
+ 8005c2e:	2207      	movs	r2, #7
+ 8005c30:	4013      	ands	r3, r2
+ 8005c32:	d001      	beq.n	8005c38 <prvInitialiseNewTask+0x44>
+ 8005c34:	b672      	cpsid	i
+ 8005c36:	e7fe      	b.n	8005c36 <prvInitialiseNewTask+0x42>
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+ 8005c38:	68bb      	ldr	r3, [r7, #8]
+ 8005c3a:	2b00      	cmp	r3, #0
+ 8005c3c:	d020      	beq.n	8005c80 <prvInitialiseNewTask+0x8c>
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ 8005c3e:	2300      	movs	r3, #0
+ 8005c40:	617b      	str	r3, [r7, #20]
+ 8005c42:	e013      	b.n	8005c6c <prvInitialiseNewTask+0x78>
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+ 8005c44:	68ba      	ldr	r2, [r7, #8]
+ 8005c46:	697b      	ldr	r3, [r7, #20]
+ 8005c48:	18d3      	adds	r3, r2, r3
+ 8005c4a:	7818      	ldrb	r0, [r3, #0]
+ 8005c4c:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8005c4e:	2134      	movs	r1, #52	; 0x34
+ 8005c50:	697b      	ldr	r3, [r7, #20]
+ 8005c52:	18d3      	adds	r3, r2, r3
+ 8005c54:	185b      	adds	r3, r3, r1
+ 8005c56:	1c02      	adds	r2, r0, #0
+ 8005c58:	701a      	strb	r2, [r3, #0]
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+ 8005c5a:	68ba      	ldr	r2, [r7, #8]
+ 8005c5c:	697b      	ldr	r3, [r7, #20]
+ 8005c5e:	18d3      	adds	r3, r2, r3
+ 8005c60:	781b      	ldrb	r3, [r3, #0]
+ 8005c62:	2b00      	cmp	r3, #0
+ 8005c64:	d006      	beq.n	8005c74 <prvInitialiseNewTask+0x80>
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ 8005c66:	697b      	ldr	r3, [r7, #20]
+ 8005c68:	3301      	adds	r3, #1
+ 8005c6a:	617b      	str	r3, [r7, #20]
+ 8005c6c:	697b      	ldr	r3, [r7, #20]
+ 8005c6e:	2b0f      	cmp	r3, #15
+ 8005c70:	d9e8      	bls.n	8005c44 <prvInitialiseNewTask+0x50>
+ 8005c72:	e000      	b.n	8005c76 <prvInitialiseNewTask+0x82>
+			{
+				break;
+ 8005c74:	46c0      	nop			; (mov r8, r8)
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+ 8005c76:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005c78:	2243      	movs	r2, #67	; 0x43
+ 8005c7a:	2100      	movs	r1, #0
+ 8005c7c:	5499      	strb	r1, [r3, r2]
+ 8005c7e:	e003      	b.n	8005c88 <prvInitialiseNewTask+0x94>
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+ 8005c80:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005c82:	2234      	movs	r2, #52	; 0x34
+ 8005c84:	2100      	movs	r1, #0
+ 8005c86:	5499      	strb	r1, [r3, r2]
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+ 8005c88:	6a3b      	ldr	r3, [r7, #32]
+ 8005c8a:	2b37      	cmp	r3, #55	; 0x37
+ 8005c8c:	d901      	bls.n	8005c92 <prvInitialiseNewTask+0x9e>
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+ 8005c8e:	2337      	movs	r3, #55	; 0x37
+ 8005c90:	623b      	str	r3, [r7, #32]
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+ 8005c92:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005c94:	6a3a      	ldr	r2, [r7, #32]
+ 8005c96:	62da      	str	r2, [r3, #44]	; 0x2c
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+ 8005c98:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005c9a:	6a3a      	ldr	r2, [r7, #32]
+ 8005c9c:	64da      	str	r2, [r3, #76]	; 0x4c
+		pxNewTCB->uxMutexesHeld = 0;
+ 8005c9e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005ca0:	2200      	movs	r2, #0
+ 8005ca2:	651a      	str	r2, [r3, #80]	; 0x50
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+ 8005ca4:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005ca6:	3304      	adds	r3, #4
+ 8005ca8:	0018      	movs	r0, r3
+ 8005caa:	f7ff fa25 	bl	80050f8 <vListInitialiseItem>
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+ 8005cae:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005cb0:	3318      	adds	r3, #24
+ 8005cb2:	0018      	movs	r0, r3
+ 8005cb4:	f7ff fa20 	bl	80050f8 <vListInitialiseItem>
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+ 8005cb8:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005cba:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8005cbc:	611a      	str	r2, [r3, #16]
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 8005cbe:	6a3b      	ldr	r3, [r7, #32]
+ 8005cc0:	2238      	movs	r2, #56	; 0x38
+ 8005cc2:	1ad2      	subs	r2, r2, r3
+ 8005cc4:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005cc6:	619a      	str	r2, [r3, #24]
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+ 8005cc8:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005cca:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8005ccc:	625a      	str	r2, [r3, #36]	; 0x24
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+ 8005cce:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005cd0:	2200      	movs	r2, #0
+ 8005cd2:	655a      	str	r2, [r3, #84]	; 0x54
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+ 8005cd4:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005cd6:	2258      	movs	r2, #88	; 0x58
+ 8005cd8:	2100      	movs	r1, #0
+ 8005cda:	5499      	strb	r1, [r3, r2]
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+ 8005cdc:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005cde:	225a      	movs	r2, #90	; 0x5a
+ 8005ce0:	2100      	movs	r1, #0
+ 8005ce2:	5499      	strb	r1, [r3, r2]
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+ 8005ce4:	683a      	ldr	r2, [r7, #0]
+ 8005ce6:	68f9      	ldr	r1, [r7, #12]
+ 8005ce8:	693b      	ldr	r3, [r7, #16]
+ 8005cea:	0018      	movs	r0, r3
+ 8005cec:	f001 f980 	bl	8006ff0 <pxPortInitialiseStack>
+ 8005cf0:	0002      	movs	r2, r0
+ 8005cf2:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005cf4:	601a      	str	r2, [r3, #0]
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+ 8005cf6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8005cf8:	2b00      	cmp	r3, #0
+ 8005cfa:	d002      	beq.n	8005d02 <prvInitialiseNewTask+0x10e>
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+ 8005cfc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8005cfe:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8005d00:	601a      	str	r2, [r3, #0]
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+ 8005d02:	46c0      	nop			; (mov r8, r8)
+ 8005d04:	46bd      	mov	sp, r7
+ 8005d06:	b006      	add	sp, #24
+ 8005d08:	bd80      	pop	{r7, pc}
+ 8005d0a:	46c0      	nop			; (mov r8, r8)
+ 8005d0c:	3fffffff 	.word	0x3fffffff
+
+08005d10 <prvAddNewTaskToReadyList>:
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+ 8005d10:	b580      	push	{r7, lr}
+ 8005d12:	b082      	sub	sp, #8
+ 8005d14:	af00      	add	r7, sp, #0
+ 8005d16:	6078      	str	r0, [r7, #4]
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+ 8005d18:	f001 fa02 	bl	8007120 <vPortEnterCritical>
+	{
+		uxCurrentNumberOfTasks++;
+ 8005d1c:	4b2a      	ldr	r3, [pc, #168]	; (8005dc8 <prvAddNewTaskToReadyList+0xb8>)
+ 8005d1e:	681b      	ldr	r3, [r3, #0]
+ 8005d20:	1c5a      	adds	r2, r3, #1
+ 8005d22:	4b29      	ldr	r3, [pc, #164]	; (8005dc8 <prvAddNewTaskToReadyList+0xb8>)
+ 8005d24:	601a      	str	r2, [r3, #0]
+		if( pxCurrentTCB == NULL )
+ 8005d26:	4b29      	ldr	r3, [pc, #164]	; (8005dcc <prvAddNewTaskToReadyList+0xbc>)
+ 8005d28:	681b      	ldr	r3, [r3, #0]
+ 8005d2a:	2b00      	cmp	r3, #0
+ 8005d2c:	d109      	bne.n	8005d42 <prvAddNewTaskToReadyList+0x32>
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+ 8005d2e:	4b27      	ldr	r3, [pc, #156]	; (8005dcc <prvAddNewTaskToReadyList+0xbc>)
+ 8005d30:	687a      	ldr	r2, [r7, #4]
+ 8005d32:	601a      	str	r2, [r3, #0]
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+ 8005d34:	4b24      	ldr	r3, [pc, #144]	; (8005dc8 <prvAddNewTaskToReadyList+0xb8>)
+ 8005d36:	681b      	ldr	r3, [r3, #0]
+ 8005d38:	2b01      	cmp	r3, #1
+ 8005d3a:	d110      	bne.n	8005d5e <prvAddNewTaskToReadyList+0x4e>
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+ 8005d3c:	f000 fcbc 	bl	80066b8 <prvInitialiseTaskLists>
+ 8005d40:	e00d      	b.n	8005d5e <prvAddNewTaskToReadyList+0x4e>
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+ 8005d42:	4b23      	ldr	r3, [pc, #140]	; (8005dd0 <prvAddNewTaskToReadyList+0xc0>)
+ 8005d44:	681b      	ldr	r3, [r3, #0]
+ 8005d46:	2b00      	cmp	r3, #0
+ 8005d48:	d109      	bne.n	8005d5e <prvAddNewTaskToReadyList+0x4e>
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+ 8005d4a:	4b20      	ldr	r3, [pc, #128]	; (8005dcc <prvAddNewTaskToReadyList+0xbc>)
+ 8005d4c:	681b      	ldr	r3, [r3, #0]
+ 8005d4e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005d50:	687b      	ldr	r3, [r7, #4]
+ 8005d52:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8005d54:	429a      	cmp	r2, r3
+ 8005d56:	d802      	bhi.n	8005d5e <prvAddNewTaskToReadyList+0x4e>
+				{
+					pxCurrentTCB = pxNewTCB;
+ 8005d58:	4b1c      	ldr	r3, [pc, #112]	; (8005dcc <prvAddNewTaskToReadyList+0xbc>)
+ 8005d5a:	687a      	ldr	r2, [r7, #4]
+ 8005d5c:	601a      	str	r2, [r3, #0]
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+ 8005d5e:	4b1d      	ldr	r3, [pc, #116]	; (8005dd4 <prvAddNewTaskToReadyList+0xc4>)
+ 8005d60:	681b      	ldr	r3, [r3, #0]
+ 8005d62:	1c5a      	adds	r2, r3, #1
+ 8005d64:	4b1b      	ldr	r3, [pc, #108]	; (8005dd4 <prvAddNewTaskToReadyList+0xc4>)
+ 8005d66:	601a      	str	r2, [r3, #0]
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+ 8005d68:	4b1a      	ldr	r3, [pc, #104]	; (8005dd4 <prvAddNewTaskToReadyList+0xc4>)
+ 8005d6a:	681a      	ldr	r2, [r3, #0]
+ 8005d6c:	687b      	ldr	r3, [r7, #4]
+ 8005d6e:	645a      	str	r2, [r3, #68]	; 0x44
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+ 8005d70:	687b      	ldr	r3, [r7, #4]
+ 8005d72:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005d74:	4b18      	ldr	r3, [pc, #96]	; (8005dd8 <prvAddNewTaskToReadyList+0xc8>)
+ 8005d76:	681b      	ldr	r3, [r3, #0]
+ 8005d78:	429a      	cmp	r2, r3
+ 8005d7a:	d903      	bls.n	8005d84 <prvAddNewTaskToReadyList+0x74>
+ 8005d7c:	687b      	ldr	r3, [r7, #4]
+ 8005d7e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005d80:	4b15      	ldr	r3, [pc, #84]	; (8005dd8 <prvAddNewTaskToReadyList+0xc8>)
+ 8005d82:	601a      	str	r2, [r3, #0]
+ 8005d84:	687b      	ldr	r3, [r7, #4]
+ 8005d86:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005d88:	0013      	movs	r3, r2
+ 8005d8a:	009b      	lsls	r3, r3, #2
+ 8005d8c:	189b      	adds	r3, r3, r2
+ 8005d8e:	009b      	lsls	r3, r3, #2
+ 8005d90:	4a12      	ldr	r2, [pc, #72]	; (8005ddc <prvAddNewTaskToReadyList+0xcc>)
+ 8005d92:	189a      	adds	r2, r3, r2
+ 8005d94:	687b      	ldr	r3, [r7, #4]
+ 8005d96:	3304      	adds	r3, #4
+ 8005d98:	0019      	movs	r1, r3
+ 8005d9a:	0010      	movs	r0, r2
+ 8005d9c:	f7ff f9b7 	bl	800510e <vListInsertEnd>
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+ 8005da0:	f001 f9d0 	bl	8007144 <vPortExitCritical>
+
+	if( xSchedulerRunning != pdFALSE )
+ 8005da4:	4b0a      	ldr	r3, [pc, #40]	; (8005dd0 <prvAddNewTaskToReadyList+0xc0>)
+ 8005da6:	681b      	ldr	r3, [r3, #0]
+ 8005da8:	2b00      	cmp	r3, #0
+ 8005daa:	d008      	beq.n	8005dbe <prvAddNewTaskToReadyList+0xae>
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+ 8005dac:	4b07      	ldr	r3, [pc, #28]	; (8005dcc <prvAddNewTaskToReadyList+0xbc>)
+ 8005dae:	681b      	ldr	r3, [r3, #0]
+ 8005db0:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005db2:	687b      	ldr	r3, [r7, #4]
+ 8005db4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8005db6:	429a      	cmp	r2, r3
+ 8005db8:	d201      	bcs.n	8005dbe <prvAddNewTaskToReadyList+0xae>
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+ 8005dba:	f001 f9a1 	bl	8007100 <vPortYield>
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+ 8005dbe:	46c0      	nop			; (mov r8, r8)
+ 8005dc0:	46bd      	mov	sp, r7
+ 8005dc2:	b002      	add	sp, #8
+ 8005dc4:	bd80      	pop	{r7, pc}
+ 8005dc6:	46c0      	nop			; (mov r8, r8)
+ 8005dc8:	20000bc0 	.word	0x20000bc0
+ 8005dcc:	200006ec 	.word	0x200006ec
+ 8005dd0:	20000bcc 	.word	0x20000bcc
+ 8005dd4:	20000bdc 	.word	0x20000bdc
+ 8005dd8:	20000bc8 	.word	0x20000bc8
+ 8005ddc:	200006f0 	.word	0x200006f0
+
+08005de0 <vTaskDelay>:
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+ 8005de0:	b580      	push	{r7, lr}
+ 8005de2:	b084      	sub	sp, #16
+ 8005de4:	af00      	add	r7, sp, #0
+ 8005de6:	6078      	str	r0, [r7, #4]
+	BaseType_t xAlreadyYielded = pdFALSE;
+ 8005de8:	2300      	movs	r3, #0
+ 8005dea:	60fb      	str	r3, [r7, #12]
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+ 8005dec:	687b      	ldr	r3, [r7, #4]
+ 8005dee:	2b00      	cmp	r3, #0
+ 8005df0:	d010      	beq.n	8005e14 <vTaskDelay+0x34>
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+ 8005df2:	4b0d      	ldr	r3, [pc, #52]	; (8005e28 <vTaskDelay+0x48>)
+ 8005df4:	681b      	ldr	r3, [r3, #0]
+ 8005df6:	2b00      	cmp	r3, #0
+ 8005df8:	d001      	beq.n	8005dfe <vTaskDelay+0x1e>
+ 8005dfa:	b672      	cpsid	i
+ 8005dfc:	e7fe      	b.n	8005dfc <vTaskDelay+0x1c>
+			vTaskSuspendAll();
+ 8005dfe:	f000 f8dd 	bl	8005fbc <vTaskSuspendAll>
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+ 8005e02:	687b      	ldr	r3, [r7, #4]
+ 8005e04:	2100      	movs	r1, #0
+ 8005e06:	0018      	movs	r0, r3
+ 8005e08:	f000 fd86 	bl	8006918 <prvAddCurrentTaskToDelayedList>
+			}
+			xAlreadyYielded = xTaskResumeAll();
+ 8005e0c:	f000 f918 	bl	8006040 <xTaskResumeAll>
+ 8005e10:	0003      	movs	r3, r0
+ 8005e12:	60fb      	str	r3, [r7, #12]
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+ 8005e14:	68fb      	ldr	r3, [r7, #12]
+ 8005e16:	2b00      	cmp	r3, #0
+ 8005e18:	d101      	bne.n	8005e1e <vTaskDelay+0x3e>
+		{
+			portYIELD_WITHIN_API();
+ 8005e1a:	f001 f971 	bl	8007100 <vPortYield>
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+ 8005e1e:	46c0      	nop			; (mov r8, r8)
+ 8005e20:	46bd      	mov	sp, r7
+ 8005e22:	b004      	add	sp, #16
+ 8005e24:	bd80      	pop	{r7, pc}
+ 8005e26:	46c0      	nop			; (mov r8, r8)
+ 8005e28:	20000be8 	.word	0x20000be8
+
+08005e2c <prvTaskIsTaskSuspended>:
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+ 8005e2c:	b580      	push	{r7, lr}
+ 8005e2e:	b084      	sub	sp, #16
+ 8005e30:	af00      	add	r7, sp, #0
+ 8005e32:	6078      	str	r0, [r7, #4]
+	BaseType_t xReturn = pdFALSE;
+ 8005e34:	2300      	movs	r3, #0
+ 8005e36:	60fb      	str	r3, [r7, #12]
+	const TCB_t * const pxTCB = xTask;
+ 8005e38:	687b      	ldr	r3, [r7, #4]
+ 8005e3a:	60bb      	str	r3, [r7, #8]
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+ 8005e3c:	687b      	ldr	r3, [r7, #4]
+ 8005e3e:	2b00      	cmp	r3, #0
+ 8005e40:	d101      	bne.n	8005e46 <prvTaskIsTaskSuspended+0x1a>
+ 8005e42:	b672      	cpsid	i
+ 8005e44:	e7fe      	b.n	8005e44 <prvTaskIsTaskSuspended+0x18>
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+ 8005e46:	68bb      	ldr	r3, [r7, #8]
+ 8005e48:	695a      	ldr	r2, [r3, #20]
+ 8005e4a:	4b09      	ldr	r3, [pc, #36]	; (8005e70 <prvTaskIsTaskSuspended+0x44>)
+ 8005e4c:	429a      	cmp	r2, r3
+ 8005e4e:	d10a      	bne.n	8005e66 <prvTaskIsTaskSuspended+0x3a>
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+ 8005e50:	68bb      	ldr	r3, [r7, #8]
+ 8005e52:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8005e54:	4b07      	ldr	r3, [pc, #28]	; (8005e74 <prvTaskIsTaskSuspended+0x48>)
+ 8005e56:	429a      	cmp	r2, r3
+ 8005e58:	d005      	beq.n	8005e66 <prvTaskIsTaskSuspended+0x3a>
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+ 8005e5a:	68bb      	ldr	r3, [r7, #8]
+ 8005e5c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8005e5e:	2b00      	cmp	r3, #0
+ 8005e60:	d101      	bne.n	8005e66 <prvTaskIsTaskSuspended+0x3a>
+				{
+					xReturn = pdTRUE;
+ 8005e62:	2301      	movs	r3, #1
+ 8005e64:	60fb      	str	r3, [r7, #12]
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+ 8005e66:	68fb      	ldr	r3, [r7, #12]
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+ 8005e68:	0018      	movs	r0, r3
+ 8005e6a:	46bd      	mov	sp, r7
+ 8005e6c:	b004      	add	sp, #16
+ 8005e6e:	bd80      	pop	{r7, pc}
+ 8005e70:	20000bac 	.word	0x20000bac
+ 8005e74:	20000b80 	.word	0x20000b80
+
+08005e78 <vTaskResume>:
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+ 8005e78:	b580      	push	{r7, lr}
+ 8005e7a:	b084      	sub	sp, #16
+ 8005e7c:	af00      	add	r7, sp, #0
+ 8005e7e:	6078      	str	r0, [r7, #4]
+	TCB_t * const pxTCB = xTaskToResume;
+ 8005e80:	687b      	ldr	r3, [r7, #4]
+ 8005e82:	60fb      	str	r3, [r7, #12]
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+ 8005e84:	687b      	ldr	r3, [r7, #4]
+ 8005e86:	2b00      	cmp	r3, #0
+ 8005e88:	d101      	bne.n	8005e8e <vTaskResume+0x16>
+ 8005e8a:	b672      	cpsid	i
+ 8005e8c:	e7fe      	b.n	8005e8c <vTaskResume+0x14>
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+ 8005e8e:	4b1e      	ldr	r3, [pc, #120]	; (8005f08 <vTaskResume+0x90>)
+ 8005e90:	681b      	ldr	r3, [r3, #0]
+ 8005e92:	68fa      	ldr	r2, [r7, #12]
+ 8005e94:	429a      	cmp	r2, r3
+ 8005e96:	d032      	beq.n	8005efe <vTaskResume+0x86>
+ 8005e98:	68fb      	ldr	r3, [r7, #12]
+ 8005e9a:	2b00      	cmp	r3, #0
+ 8005e9c:	d02f      	beq.n	8005efe <vTaskResume+0x86>
+		{
+			taskENTER_CRITICAL();
+ 8005e9e:	f001 f93f 	bl	8007120 <vPortEnterCritical>
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+ 8005ea2:	68fb      	ldr	r3, [r7, #12]
+ 8005ea4:	0018      	movs	r0, r3
+ 8005ea6:	f7ff ffc1 	bl	8005e2c <prvTaskIsTaskSuspended>
+ 8005eaa:	1e03      	subs	r3, r0, #0
+ 8005eac:	d025      	beq.n	8005efa <vTaskResume+0x82>
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+ 8005eae:	68fb      	ldr	r3, [r7, #12]
+ 8005eb0:	3304      	adds	r3, #4
+ 8005eb2:	0018      	movs	r0, r3
+ 8005eb4:	f7ff f983 	bl	80051be <uxListRemove>
+					prvAddTaskToReadyList( pxTCB );
+ 8005eb8:	68fb      	ldr	r3, [r7, #12]
+ 8005eba:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005ebc:	4b13      	ldr	r3, [pc, #76]	; (8005f0c <vTaskResume+0x94>)
+ 8005ebe:	681b      	ldr	r3, [r3, #0]
+ 8005ec0:	429a      	cmp	r2, r3
+ 8005ec2:	d903      	bls.n	8005ecc <vTaskResume+0x54>
+ 8005ec4:	68fb      	ldr	r3, [r7, #12]
+ 8005ec6:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005ec8:	4b10      	ldr	r3, [pc, #64]	; (8005f0c <vTaskResume+0x94>)
+ 8005eca:	601a      	str	r2, [r3, #0]
+ 8005ecc:	68fb      	ldr	r3, [r7, #12]
+ 8005ece:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005ed0:	0013      	movs	r3, r2
+ 8005ed2:	009b      	lsls	r3, r3, #2
+ 8005ed4:	189b      	adds	r3, r3, r2
+ 8005ed6:	009b      	lsls	r3, r3, #2
+ 8005ed8:	4a0d      	ldr	r2, [pc, #52]	; (8005f10 <vTaskResume+0x98>)
+ 8005eda:	189a      	adds	r2, r3, r2
+ 8005edc:	68fb      	ldr	r3, [r7, #12]
+ 8005ede:	3304      	adds	r3, #4
+ 8005ee0:	0019      	movs	r1, r3
+ 8005ee2:	0010      	movs	r0, r2
+ 8005ee4:	f7ff f913 	bl	800510e <vListInsertEnd>
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ 8005ee8:	68fb      	ldr	r3, [r7, #12]
+ 8005eea:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8005eec:	4b06      	ldr	r3, [pc, #24]	; (8005f08 <vTaskResume+0x90>)
+ 8005eee:	681b      	ldr	r3, [r3, #0]
+ 8005ef0:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8005ef2:	429a      	cmp	r2, r3
+ 8005ef4:	d301      	bcc.n	8005efa <vTaskResume+0x82>
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+ 8005ef6:	f001 f903 	bl	8007100 <vPortYield>
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+ 8005efa:	f001 f923 	bl	8007144 <vPortExitCritical>
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+ 8005efe:	46c0      	nop			; (mov r8, r8)
+ 8005f00:	46bd      	mov	sp, r7
+ 8005f02:	b004      	add	sp, #16
+ 8005f04:	bd80      	pop	{r7, pc}
+ 8005f06:	46c0      	nop			; (mov r8, r8)
+ 8005f08:	200006ec 	.word	0x200006ec
+ 8005f0c:	20000bc8 	.word	0x20000bc8
+ 8005f10:	200006f0 	.word	0x200006f0
+
+08005f14 <vTaskStartScheduler>:
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+ 8005f14:	b590      	push	{r4, r7, lr}
+ 8005f16:	b089      	sub	sp, #36	; 0x24
+ 8005f18:	af04      	add	r7, sp, #16
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+ 8005f1a:	2300      	movs	r3, #0
+ 8005f1c:	60bb      	str	r3, [r7, #8]
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+ 8005f1e:	2300      	movs	r3, #0
+ 8005f20:	607b      	str	r3, [r7, #4]
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+ 8005f22:	003a      	movs	r2, r7
+ 8005f24:	1d39      	adds	r1, r7, #4
+ 8005f26:	2308      	movs	r3, #8
+ 8005f28:	18fb      	adds	r3, r7, r3
+ 8005f2a:	0018      	movs	r0, r3
+ 8005f2c:	f7ff f896 	bl	800505c <vApplicationGetIdleTaskMemory>
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+ 8005f30:	683c      	ldr	r4, [r7, #0]
+ 8005f32:	687b      	ldr	r3, [r7, #4]
+ 8005f34:	68ba      	ldr	r2, [r7, #8]
+ 8005f36:	491b      	ldr	r1, [pc, #108]	; (8005fa4 <vTaskStartScheduler+0x90>)
+ 8005f38:	481b      	ldr	r0, [pc, #108]	; (8005fa8 <vTaskStartScheduler+0x94>)
+ 8005f3a:	9202      	str	r2, [sp, #8]
+ 8005f3c:	9301      	str	r3, [sp, #4]
+ 8005f3e:	2300      	movs	r3, #0
+ 8005f40:	9300      	str	r3, [sp, #0]
+ 8005f42:	2300      	movs	r3, #0
+ 8005f44:	0022      	movs	r2, r4
+ 8005f46:	f7ff fdc4 	bl	8005ad2 <xTaskCreateStatic>
+ 8005f4a:	0002      	movs	r2, r0
+ 8005f4c:	4b17      	ldr	r3, [pc, #92]	; (8005fac <vTaskStartScheduler+0x98>)
+ 8005f4e:	601a      	str	r2, [r3, #0]
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+ 8005f50:	4b16      	ldr	r3, [pc, #88]	; (8005fac <vTaskStartScheduler+0x98>)
+ 8005f52:	681b      	ldr	r3, [r3, #0]
+ 8005f54:	2b00      	cmp	r3, #0
+ 8005f56:	d002      	beq.n	8005f5e <vTaskStartScheduler+0x4a>
+		{
+			xReturn = pdPASS;
+ 8005f58:	2301      	movs	r3, #1
+ 8005f5a:	60fb      	str	r3, [r7, #12]
+ 8005f5c:	e001      	b.n	8005f62 <vTaskStartScheduler+0x4e>
+		}
+		else
+		{
+			xReturn = pdFAIL;
+ 8005f5e:	2300      	movs	r3, #0
+ 8005f60:	60fb      	str	r3, [r7, #12]
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+ 8005f62:	68fb      	ldr	r3, [r7, #12]
+ 8005f64:	2b01      	cmp	r3, #1
+ 8005f66:	d103      	bne.n	8005f70 <vTaskStartScheduler+0x5c>
+		{
+			xReturn = xTimerCreateTimerTask();
+ 8005f68:	f000 fd30 	bl	80069cc <xTimerCreateTimerTask>
+ 8005f6c:	0003      	movs	r3, r0
+ 8005f6e:	60fb      	str	r3, [r7, #12]
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+ 8005f70:	68fb      	ldr	r3, [r7, #12]
+ 8005f72:	2b01      	cmp	r3, #1
+ 8005f74:	d10d      	bne.n	8005f92 <vTaskStartScheduler+0x7e>
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+ 8005f76:	b672      	cpsid	i
+			structure specific to the task that will run first. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+ 8005f78:	4b0d      	ldr	r3, [pc, #52]	; (8005fb0 <vTaskStartScheduler+0x9c>)
+ 8005f7a:	2201      	movs	r2, #1
+ 8005f7c:	4252      	negs	r2, r2
+ 8005f7e:	601a      	str	r2, [r3, #0]
+		xSchedulerRunning = pdTRUE;
+ 8005f80:	4b0c      	ldr	r3, [pc, #48]	; (8005fb4 <vTaskStartScheduler+0xa0>)
+ 8005f82:	2201      	movs	r2, #1
+ 8005f84:	601a      	str	r2, [r3, #0]
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+ 8005f86:	4b0c      	ldr	r3, [pc, #48]	; (8005fb8 <vTaskStartScheduler+0xa4>)
+ 8005f88:	2200      	movs	r2, #0
+ 8005f8a:	601a      	str	r2, [r3, #0]
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+ 8005f8c:	f001 f894 	bl	80070b8 <xPortStartScheduler>
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+ 8005f90:	e004      	b.n	8005f9c <vTaskStartScheduler+0x88>
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+ 8005f92:	68fb      	ldr	r3, [r7, #12]
+ 8005f94:	3301      	adds	r3, #1
+ 8005f96:	d101      	bne.n	8005f9c <vTaskStartScheduler+0x88>
+ 8005f98:	b672      	cpsid	i
+ 8005f9a:	e7fe      	b.n	8005f9a <vTaskStartScheduler+0x86>
+}
+ 8005f9c:	46c0      	nop			; (mov r8, r8)
+ 8005f9e:	46bd      	mov	sp, r7
+ 8005fa0:	b005      	add	sp, #20
+ 8005fa2:	bd90      	pop	{r4, r7, pc}
+ 8005fa4:	08007804 	.word	0x08007804
+ 8005fa8:	080065f1 	.word	0x080065f1
+ 8005fac:	20000be4 	.word	0x20000be4
+ 8005fb0:	20000be0 	.word	0x20000be0
+ 8005fb4:	20000bcc 	.word	0x20000bcc
+ 8005fb8:	20000bc4 	.word	0x20000bc4
+
+08005fbc <vTaskSuspendAll>:
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+ 8005fbc:	b580      	push	{r7, lr}
+ 8005fbe:	af00      	add	r7, sp, #0
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+	++uxSchedulerSuspended;
+ 8005fc0:	4b03      	ldr	r3, [pc, #12]	; (8005fd0 <vTaskSuspendAll+0x14>)
+ 8005fc2:	681b      	ldr	r3, [r3, #0]
+ 8005fc4:	1c5a      	adds	r2, r3, #1
+ 8005fc6:	4b02      	ldr	r3, [pc, #8]	; (8005fd0 <vTaskSuspendAll+0x14>)
+ 8005fc8:	601a      	str	r2, [r3, #0]
+	portMEMORY_BARRIER();
+}
+ 8005fca:	46c0      	nop			; (mov r8, r8)
+ 8005fcc:	46bd      	mov	sp, r7
+ 8005fce:	bd80      	pop	{r7, pc}
+ 8005fd0:	20000be8 	.word	0x20000be8
+
+08005fd4 <prvGetExpectedIdleTime>:
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+ 8005fd4:	b580      	push	{r7, lr}
+ 8005fd6:	b082      	sub	sp, #8
+ 8005fd8:	af00      	add	r7, sp, #0
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+ 8005fda:	2300      	movs	r3, #0
+ 8005fdc:	603b      	str	r3, [r7, #0]
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+ 8005fde:	4b13      	ldr	r3, [pc, #76]	; (800602c <prvGetExpectedIdleTime+0x58>)
+ 8005fe0:	681b      	ldr	r3, [r3, #0]
+ 8005fe2:	2b00      	cmp	r3, #0
+ 8005fe4:	d001      	beq.n	8005fea <prvGetExpectedIdleTime+0x16>
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+ 8005fe6:	2301      	movs	r3, #1
+ 8005fe8:	603b      	str	r3, [r7, #0]
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+ 8005fea:	4b11      	ldr	r3, [pc, #68]	; (8006030 <prvGetExpectedIdleTime+0x5c>)
+ 8005fec:	681b      	ldr	r3, [r3, #0]
+ 8005fee:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8005ff0:	2b00      	cmp	r3, #0
+ 8005ff2:	d002      	beq.n	8005ffa <prvGetExpectedIdleTime+0x26>
+		{
+			xReturn = 0;
+ 8005ff4:	2300      	movs	r3, #0
+ 8005ff6:	607b      	str	r3, [r7, #4]
+ 8005ff8:	e012      	b.n	8006020 <prvGetExpectedIdleTime+0x4c>
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+ 8005ffa:	4b0e      	ldr	r3, [pc, #56]	; (8006034 <prvGetExpectedIdleTime+0x60>)
+ 8005ffc:	681b      	ldr	r3, [r3, #0]
+ 8005ffe:	2b01      	cmp	r3, #1
+ 8006000:	d902      	bls.n	8006008 <prvGetExpectedIdleTime+0x34>
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+ 8006002:	2300      	movs	r3, #0
+ 8006004:	607b      	str	r3, [r7, #4]
+ 8006006:	e00b      	b.n	8006020 <prvGetExpectedIdleTime+0x4c>
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+ 8006008:	683b      	ldr	r3, [r7, #0]
+ 800600a:	2b00      	cmp	r3, #0
+ 800600c:	d002      	beq.n	8006014 <prvGetExpectedIdleTime+0x40>
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+ 800600e:	2300      	movs	r3, #0
+ 8006010:	607b      	str	r3, [r7, #4]
+ 8006012:	e005      	b.n	8006020 <prvGetExpectedIdleTime+0x4c>
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+ 8006014:	4b08      	ldr	r3, [pc, #32]	; (8006038 <prvGetExpectedIdleTime+0x64>)
+ 8006016:	681a      	ldr	r2, [r3, #0]
+ 8006018:	4b08      	ldr	r3, [pc, #32]	; (800603c <prvGetExpectedIdleTime+0x68>)
+ 800601a:	681b      	ldr	r3, [r3, #0]
+ 800601c:	1ad3      	subs	r3, r2, r3
+ 800601e:	607b      	str	r3, [r7, #4]
+		}
+
+		return xReturn;
+ 8006020:	687b      	ldr	r3, [r7, #4]
+	}
+ 8006022:	0018      	movs	r0, r3
+ 8006024:	46bd      	mov	sp, r7
+ 8006026:	b002      	add	sp, #8
+ 8006028:	bd80      	pop	{r7, pc}
+ 800602a:	46c0      	nop			; (mov r8, r8)
+ 800602c:	20000bc8 	.word	0x20000bc8
+ 8006030:	200006ec 	.word	0x200006ec
+ 8006034:	200006f0 	.word	0x200006f0
+ 8006038:	20000be0 	.word	0x20000be0
+ 800603c:	20000bc4 	.word	0x20000bc4
+
+08006040 <xTaskResumeAll>:
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+ 8006040:	b580      	push	{r7, lr}
+ 8006042:	b084      	sub	sp, #16
+ 8006044:	af00      	add	r7, sp, #0
+TCB_t *pxTCB = NULL;
+ 8006046:	2300      	movs	r3, #0
+ 8006048:	60fb      	str	r3, [r7, #12]
+BaseType_t xAlreadyYielded = pdFALSE;
+ 800604a:	2300      	movs	r3, #0
+ 800604c:	60bb      	str	r3, [r7, #8]
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+ 800604e:	4b3a      	ldr	r3, [pc, #232]	; (8006138 <xTaskResumeAll+0xf8>)
+ 8006050:	681b      	ldr	r3, [r3, #0]
+ 8006052:	2b00      	cmp	r3, #0
+ 8006054:	d101      	bne.n	800605a <xTaskResumeAll+0x1a>
+ 8006056:	b672      	cpsid	i
+ 8006058:	e7fe      	b.n	8006058 <xTaskResumeAll+0x18>
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+ 800605a:	f001 f861 	bl	8007120 <vPortEnterCritical>
+	{
+		--uxSchedulerSuspended;
+ 800605e:	4b36      	ldr	r3, [pc, #216]	; (8006138 <xTaskResumeAll+0xf8>)
+ 8006060:	681b      	ldr	r3, [r3, #0]
+ 8006062:	1e5a      	subs	r2, r3, #1
+ 8006064:	4b34      	ldr	r3, [pc, #208]	; (8006138 <xTaskResumeAll+0xf8>)
+ 8006066:	601a      	str	r2, [r3, #0]
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ 8006068:	4b33      	ldr	r3, [pc, #204]	; (8006138 <xTaskResumeAll+0xf8>)
+ 800606a:	681b      	ldr	r3, [r3, #0]
+ 800606c:	2b00      	cmp	r3, #0
+ 800606e:	d15b      	bne.n	8006128 <xTaskResumeAll+0xe8>
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+ 8006070:	4b32      	ldr	r3, [pc, #200]	; (800613c <xTaskResumeAll+0xfc>)
+ 8006072:	681b      	ldr	r3, [r3, #0]
+ 8006074:	2b00      	cmp	r3, #0
+ 8006076:	d057      	beq.n	8006128 <xTaskResumeAll+0xe8>
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+ 8006078:	e02f      	b.n	80060da <xTaskResumeAll+0x9a>
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 800607a:	4b31      	ldr	r3, [pc, #196]	; (8006140 <xTaskResumeAll+0x100>)
+ 800607c:	68db      	ldr	r3, [r3, #12]
+ 800607e:	68db      	ldr	r3, [r3, #12]
+ 8006080:	60fb      	str	r3, [r7, #12]
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ 8006082:	68fb      	ldr	r3, [r7, #12]
+ 8006084:	3318      	adds	r3, #24
+ 8006086:	0018      	movs	r0, r3
+ 8006088:	f7ff f899 	bl	80051be <uxListRemove>
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ 800608c:	68fb      	ldr	r3, [r7, #12]
+ 800608e:	3304      	adds	r3, #4
+ 8006090:	0018      	movs	r0, r3
+ 8006092:	f7ff f894 	bl	80051be <uxListRemove>
+					prvAddTaskToReadyList( pxTCB );
+ 8006096:	68fb      	ldr	r3, [r7, #12]
+ 8006098:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 800609a:	4b2a      	ldr	r3, [pc, #168]	; (8006144 <xTaskResumeAll+0x104>)
+ 800609c:	681b      	ldr	r3, [r3, #0]
+ 800609e:	429a      	cmp	r2, r3
+ 80060a0:	d903      	bls.n	80060aa <xTaskResumeAll+0x6a>
+ 80060a2:	68fb      	ldr	r3, [r7, #12]
+ 80060a4:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80060a6:	4b27      	ldr	r3, [pc, #156]	; (8006144 <xTaskResumeAll+0x104>)
+ 80060a8:	601a      	str	r2, [r3, #0]
+ 80060aa:	68fb      	ldr	r3, [r7, #12]
+ 80060ac:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80060ae:	0013      	movs	r3, r2
+ 80060b0:	009b      	lsls	r3, r3, #2
+ 80060b2:	189b      	adds	r3, r3, r2
+ 80060b4:	009b      	lsls	r3, r3, #2
+ 80060b6:	4a24      	ldr	r2, [pc, #144]	; (8006148 <xTaskResumeAll+0x108>)
+ 80060b8:	189a      	adds	r2, r3, r2
+ 80060ba:	68fb      	ldr	r3, [r7, #12]
+ 80060bc:	3304      	adds	r3, #4
+ 80060be:	0019      	movs	r1, r3
+ 80060c0:	0010      	movs	r0, r2
+ 80060c2:	f7ff f824 	bl	800510e <vListInsertEnd>
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ 80060c6:	68fb      	ldr	r3, [r7, #12]
+ 80060c8:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80060ca:	4b20      	ldr	r3, [pc, #128]	; (800614c <xTaskResumeAll+0x10c>)
+ 80060cc:	681b      	ldr	r3, [r3, #0]
+ 80060ce:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80060d0:	429a      	cmp	r2, r3
+ 80060d2:	d302      	bcc.n	80060da <xTaskResumeAll+0x9a>
+					{
+						xYieldPending = pdTRUE;
+ 80060d4:	4b1e      	ldr	r3, [pc, #120]	; (8006150 <xTaskResumeAll+0x110>)
+ 80060d6:	2201      	movs	r2, #1
+ 80060d8:	601a      	str	r2, [r3, #0]
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+ 80060da:	4b19      	ldr	r3, [pc, #100]	; (8006140 <xTaskResumeAll+0x100>)
+ 80060dc:	681b      	ldr	r3, [r3, #0]
+ 80060de:	2b00      	cmp	r3, #0
+ 80060e0:	d1cb      	bne.n	800607a <xTaskResumeAll+0x3a>
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+ 80060e2:	68fb      	ldr	r3, [r7, #12]
+ 80060e4:	2b00      	cmp	r3, #0
+ 80060e6:	d001      	beq.n	80060ec <xTaskResumeAll+0xac>
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+ 80060e8:	f000 fb80 	bl	80067ec <prvResetNextTaskUnblockTime>
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
+ 80060ec:	4b19      	ldr	r3, [pc, #100]	; (8006154 <xTaskResumeAll+0x114>)
+ 80060ee:	681b      	ldr	r3, [r3, #0]
+ 80060f0:	607b      	str	r3, [r7, #4]
+
+					if( uxPendedCounts > ( UBaseType_t ) 0U )
+ 80060f2:	687b      	ldr	r3, [r7, #4]
+ 80060f4:	2b00      	cmp	r3, #0
+ 80060f6:	d00f      	beq.n	8006118 <xTaskResumeAll+0xd8>
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+ 80060f8:	f000 f858 	bl	80061ac <xTaskIncrementTick>
+ 80060fc:	1e03      	subs	r3, r0, #0
+ 80060fe:	d002      	beq.n	8006106 <xTaskResumeAll+0xc6>
+							{
+								xYieldPending = pdTRUE;
+ 8006100:	4b13      	ldr	r3, [pc, #76]	; (8006150 <xTaskResumeAll+0x110>)
+ 8006102:	2201      	movs	r2, #1
+ 8006104:	601a      	str	r2, [r3, #0]
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--uxPendedCounts;
+ 8006106:	687b      	ldr	r3, [r7, #4]
+ 8006108:	3b01      	subs	r3, #1
+ 800610a:	607b      	str	r3, [r7, #4]
+						} while( uxPendedCounts > ( UBaseType_t ) 0U );
+ 800610c:	687b      	ldr	r3, [r7, #4]
+ 800610e:	2b00      	cmp	r3, #0
+ 8006110:	d1f2      	bne.n	80060f8 <xTaskResumeAll+0xb8>
+
+						uxPendedTicks = 0;
+ 8006112:	4b10      	ldr	r3, [pc, #64]	; (8006154 <xTaskResumeAll+0x114>)
+ 8006114:	2200      	movs	r2, #0
+ 8006116:	601a      	str	r2, [r3, #0]
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+ 8006118:	4b0d      	ldr	r3, [pc, #52]	; (8006150 <xTaskResumeAll+0x110>)
+ 800611a:	681b      	ldr	r3, [r3, #0]
+ 800611c:	2b00      	cmp	r3, #0
+ 800611e:	d003      	beq.n	8006128 <xTaskResumeAll+0xe8>
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+ 8006120:	2301      	movs	r3, #1
+ 8006122:	60bb      	str	r3, [r7, #8]
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+ 8006124:	f000 ffec 	bl	8007100 <vPortYield>
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+ 8006128:	f001 f80c 	bl	8007144 <vPortExitCritical>
+
+	return xAlreadyYielded;
+ 800612c:	68bb      	ldr	r3, [r7, #8]
+}
+ 800612e:	0018      	movs	r0, r3
+ 8006130:	46bd      	mov	sp, r7
+ 8006132:	b004      	add	sp, #16
+ 8006134:	bd80      	pop	{r7, pc}
+ 8006136:	46c0      	nop			; (mov r8, r8)
+ 8006138:	20000be8 	.word	0x20000be8
+ 800613c:	20000bc0 	.word	0x20000bc0
+ 8006140:	20000b80 	.word	0x20000b80
+ 8006144:	20000bc8 	.word	0x20000bc8
+ 8006148:	200006f0 	.word	0x200006f0
+ 800614c:	200006ec 	.word	0x200006ec
+ 8006150:	20000bd4 	.word	0x20000bd4
+ 8006154:	20000bd0 	.word	0x20000bd0
+
+08006158 <xTaskGetTickCount>:
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+ 8006158:	b580      	push	{r7, lr}
+ 800615a:	b082      	sub	sp, #8
+ 800615c:	af00      	add	r7, sp, #0
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+ 800615e:	4b04      	ldr	r3, [pc, #16]	; (8006170 <xTaskGetTickCount+0x18>)
+ 8006160:	681b      	ldr	r3, [r3, #0]
+ 8006162:	607b      	str	r3, [r7, #4]
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+ 8006164:	687b      	ldr	r3, [r7, #4]
+}
+ 8006166:	0018      	movs	r0, r3
+ 8006168:	46bd      	mov	sp, r7
+ 800616a:	b002      	add	sp, #8
+ 800616c:	bd80      	pop	{r7, pc}
+ 800616e:	46c0      	nop			; (mov r8, r8)
+ 8006170:	20000bc4 	.word	0x20000bc4
+
+08006174 <vTaskStepTick>:
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+ 8006174:	b580      	push	{r7, lr}
+ 8006176:	b082      	sub	sp, #8
+ 8006178:	af00      	add	r7, sp, #0
+ 800617a:	6078      	str	r0, [r7, #4]
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+ 800617c:	4b09      	ldr	r3, [pc, #36]	; (80061a4 <vTaskStepTick+0x30>)
+ 800617e:	681a      	ldr	r2, [r3, #0]
+ 8006180:	687b      	ldr	r3, [r7, #4]
+ 8006182:	18d2      	adds	r2, r2, r3
+ 8006184:	4b08      	ldr	r3, [pc, #32]	; (80061a8 <vTaskStepTick+0x34>)
+ 8006186:	681b      	ldr	r3, [r3, #0]
+ 8006188:	429a      	cmp	r2, r3
+ 800618a:	d901      	bls.n	8006190 <vTaskStepTick+0x1c>
+ 800618c:	b672      	cpsid	i
+ 800618e:	e7fe      	b.n	800618e <vTaskStepTick+0x1a>
+		xTickCount += xTicksToJump;
+ 8006190:	4b04      	ldr	r3, [pc, #16]	; (80061a4 <vTaskStepTick+0x30>)
+ 8006192:	681a      	ldr	r2, [r3, #0]
+ 8006194:	687b      	ldr	r3, [r7, #4]
+ 8006196:	18d2      	adds	r2, r2, r3
+ 8006198:	4b02      	ldr	r3, [pc, #8]	; (80061a4 <vTaskStepTick+0x30>)
+ 800619a:	601a      	str	r2, [r3, #0]
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+ 800619c:	46c0      	nop			; (mov r8, r8)
+ 800619e:	46bd      	mov	sp, r7
+ 80061a0:	b002      	add	sp, #8
+ 80061a2:	bd80      	pop	{r7, pc}
+ 80061a4:	20000bc4 	.word	0x20000bc4
+ 80061a8:	20000be0 	.word	0x20000be0
+
+080061ac <xTaskIncrementTick>:
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+ 80061ac:	b580      	push	{r7, lr}
+ 80061ae:	b086      	sub	sp, #24
+ 80061b0:	af00      	add	r7, sp, #0
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+ 80061b2:	2300      	movs	r3, #0
+ 80061b4:	617b      	str	r3, [r7, #20]
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ 80061b6:	4b4a      	ldr	r3, [pc, #296]	; (80062e0 <xTaskIncrementTick+0x134>)
+ 80061b8:	681b      	ldr	r3, [r3, #0]
+ 80061ba:	2b00      	cmp	r3, #0
+ 80061bc:	d000      	beq.n	80061c0 <xTaskIncrementTick+0x14>
+ 80061be:	e07e      	b.n	80062be <xTaskIncrementTick+0x112>
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+ 80061c0:	4b48      	ldr	r3, [pc, #288]	; (80062e4 <xTaskIncrementTick+0x138>)
+ 80061c2:	681b      	ldr	r3, [r3, #0]
+ 80061c4:	3301      	adds	r3, #1
+ 80061c6:	613b      	str	r3, [r7, #16]
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+ 80061c8:	4b46      	ldr	r3, [pc, #280]	; (80062e4 <xTaskIncrementTick+0x138>)
+ 80061ca:	693a      	ldr	r2, [r7, #16]
+ 80061cc:	601a      	str	r2, [r3, #0]
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+ 80061ce:	693b      	ldr	r3, [r7, #16]
+ 80061d0:	2b00      	cmp	r3, #0
+ 80061d2:	d117      	bne.n	8006204 <xTaskIncrementTick+0x58>
+		{
+			taskSWITCH_DELAYED_LISTS();
+ 80061d4:	4b44      	ldr	r3, [pc, #272]	; (80062e8 <xTaskIncrementTick+0x13c>)
+ 80061d6:	681b      	ldr	r3, [r3, #0]
+ 80061d8:	681b      	ldr	r3, [r3, #0]
+ 80061da:	2b00      	cmp	r3, #0
+ 80061dc:	d001      	beq.n	80061e2 <xTaskIncrementTick+0x36>
+ 80061de:	b672      	cpsid	i
+ 80061e0:	e7fe      	b.n	80061e0 <xTaskIncrementTick+0x34>
+ 80061e2:	4b41      	ldr	r3, [pc, #260]	; (80062e8 <xTaskIncrementTick+0x13c>)
+ 80061e4:	681b      	ldr	r3, [r3, #0]
+ 80061e6:	60fb      	str	r3, [r7, #12]
+ 80061e8:	4b40      	ldr	r3, [pc, #256]	; (80062ec <xTaskIncrementTick+0x140>)
+ 80061ea:	681a      	ldr	r2, [r3, #0]
+ 80061ec:	4b3e      	ldr	r3, [pc, #248]	; (80062e8 <xTaskIncrementTick+0x13c>)
+ 80061ee:	601a      	str	r2, [r3, #0]
+ 80061f0:	4b3e      	ldr	r3, [pc, #248]	; (80062ec <xTaskIncrementTick+0x140>)
+ 80061f2:	68fa      	ldr	r2, [r7, #12]
+ 80061f4:	601a      	str	r2, [r3, #0]
+ 80061f6:	4b3e      	ldr	r3, [pc, #248]	; (80062f0 <xTaskIncrementTick+0x144>)
+ 80061f8:	681b      	ldr	r3, [r3, #0]
+ 80061fa:	1c5a      	adds	r2, r3, #1
+ 80061fc:	4b3c      	ldr	r3, [pc, #240]	; (80062f0 <xTaskIncrementTick+0x144>)
+ 80061fe:	601a      	str	r2, [r3, #0]
+ 8006200:	f000 faf4 	bl	80067ec <prvResetNextTaskUnblockTime>
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+ 8006204:	4b3b      	ldr	r3, [pc, #236]	; (80062f4 <xTaskIncrementTick+0x148>)
+ 8006206:	681b      	ldr	r3, [r3, #0]
+ 8006208:	693a      	ldr	r2, [r7, #16]
+ 800620a:	429a      	cmp	r2, r3
+ 800620c:	d349      	bcc.n	80062a2 <xTaskIncrementTick+0xf6>
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ 800620e:	4b36      	ldr	r3, [pc, #216]	; (80062e8 <xTaskIncrementTick+0x13c>)
+ 8006210:	681b      	ldr	r3, [r3, #0]
+ 8006212:	681b      	ldr	r3, [r3, #0]
+ 8006214:	2b00      	cmp	r3, #0
+ 8006216:	d104      	bne.n	8006222 <xTaskIncrementTick+0x76>
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 8006218:	4b36      	ldr	r3, [pc, #216]	; (80062f4 <xTaskIncrementTick+0x148>)
+ 800621a:	2201      	movs	r2, #1
+ 800621c:	4252      	negs	r2, r2
+ 800621e:	601a      	str	r2, [r3, #0]
+					break;
+ 8006220:	e03f      	b.n	80062a2 <xTaskIncrementTick+0xf6>
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8006222:	4b31      	ldr	r3, [pc, #196]	; (80062e8 <xTaskIncrementTick+0x13c>)
+ 8006224:	681b      	ldr	r3, [r3, #0]
+ 8006226:	68db      	ldr	r3, [r3, #12]
+ 8006228:	68db      	ldr	r3, [r3, #12]
+ 800622a:	60bb      	str	r3, [r7, #8]
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+ 800622c:	68bb      	ldr	r3, [r7, #8]
+ 800622e:	685b      	ldr	r3, [r3, #4]
+ 8006230:	607b      	str	r3, [r7, #4]
+
+					if( xConstTickCount < xItemValue )
+ 8006232:	693a      	ldr	r2, [r7, #16]
+ 8006234:	687b      	ldr	r3, [r7, #4]
+ 8006236:	429a      	cmp	r2, r3
+ 8006238:	d203      	bcs.n	8006242 <xTaskIncrementTick+0x96>
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+ 800623a:	4b2e      	ldr	r3, [pc, #184]	; (80062f4 <xTaskIncrementTick+0x148>)
+ 800623c:	687a      	ldr	r2, [r7, #4]
+ 800623e:	601a      	str	r2, [r3, #0]
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+ 8006240:	e02f      	b.n	80062a2 <xTaskIncrementTick+0xf6>
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ 8006242:	68bb      	ldr	r3, [r7, #8]
+ 8006244:	3304      	adds	r3, #4
+ 8006246:	0018      	movs	r0, r3
+ 8006248:	f7fe ffb9 	bl	80051be <uxListRemove>
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ 800624c:	68bb      	ldr	r3, [r7, #8]
+ 800624e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8006250:	2b00      	cmp	r3, #0
+ 8006252:	d004      	beq.n	800625e <xTaskIncrementTick+0xb2>
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ 8006254:	68bb      	ldr	r3, [r7, #8]
+ 8006256:	3318      	adds	r3, #24
+ 8006258:	0018      	movs	r0, r3
+ 800625a:	f7fe ffb0 	bl	80051be <uxListRemove>
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+ 800625e:	68bb      	ldr	r3, [r7, #8]
+ 8006260:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8006262:	4b25      	ldr	r3, [pc, #148]	; (80062f8 <xTaskIncrementTick+0x14c>)
+ 8006264:	681b      	ldr	r3, [r3, #0]
+ 8006266:	429a      	cmp	r2, r3
+ 8006268:	d903      	bls.n	8006272 <xTaskIncrementTick+0xc6>
+ 800626a:	68bb      	ldr	r3, [r7, #8]
+ 800626c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 800626e:	4b22      	ldr	r3, [pc, #136]	; (80062f8 <xTaskIncrementTick+0x14c>)
+ 8006270:	601a      	str	r2, [r3, #0]
+ 8006272:	68bb      	ldr	r3, [r7, #8]
+ 8006274:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8006276:	0013      	movs	r3, r2
+ 8006278:	009b      	lsls	r3, r3, #2
+ 800627a:	189b      	adds	r3, r3, r2
+ 800627c:	009b      	lsls	r3, r3, #2
+ 800627e:	4a1f      	ldr	r2, [pc, #124]	; (80062fc <xTaskIncrementTick+0x150>)
+ 8006280:	189a      	adds	r2, r3, r2
+ 8006282:	68bb      	ldr	r3, [r7, #8]
+ 8006284:	3304      	adds	r3, #4
+ 8006286:	0019      	movs	r1, r3
+ 8006288:	0010      	movs	r0, r2
+ 800628a:	f7fe ff40 	bl	800510e <vListInsertEnd>
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ 800628e:	68bb      	ldr	r3, [r7, #8]
+ 8006290:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8006292:	4b1b      	ldr	r3, [pc, #108]	; (8006300 <xTaskIncrementTick+0x154>)
+ 8006294:	681b      	ldr	r3, [r3, #0]
+ 8006296:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8006298:	429a      	cmp	r2, r3
+ 800629a:	d3b8      	bcc.n	800620e <xTaskIncrementTick+0x62>
+						{
+							xSwitchRequired = pdTRUE;
+ 800629c:	2301      	movs	r3, #1
+ 800629e:	617b      	str	r3, [r7, #20]
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ 80062a0:	e7b5      	b.n	800620e <xTaskIncrementTick+0x62>
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+ 80062a2:	4b17      	ldr	r3, [pc, #92]	; (8006300 <xTaskIncrementTick+0x154>)
+ 80062a4:	681b      	ldr	r3, [r3, #0]
+ 80062a6:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80062a8:	4914      	ldr	r1, [pc, #80]	; (80062fc <xTaskIncrementTick+0x150>)
+ 80062aa:	0013      	movs	r3, r2
+ 80062ac:	009b      	lsls	r3, r3, #2
+ 80062ae:	189b      	adds	r3, r3, r2
+ 80062b0:	009b      	lsls	r3, r3, #2
+ 80062b2:	585b      	ldr	r3, [r3, r1]
+ 80062b4:	2b01      	cmp	r3, #1
+ 80062b6:	d907      	bls.n	80062c8 <xTaskIncrementTick+0x11c>
+			{
+				xSwitchRequired = pdTRUE;
+ 80062b8:	2301      	movs	r3, #1
+ 80062ba:	617b      	str	r3, [r7, #20]
+ 80062bc:	e004      	b.n	80062c8 <xTaskIncrementTick+0x11c>
+		}
+		#endif /* configUSE_TICK_HOOK */
+	}
+	else
+	{
+		++uxPendedTicks;
+ 80062be:	4b11      	ldr	r3, [pc, #68]	; (8006304 <xTaskIncrementTick+0x158>)
+ 80062c0:	681b      	ldr	r3, [r3, #0]
+ 80062c2:	1c5a      	adds	r2, r3, #1
+ 80062c4:	4b0f      	ldr	r3, [pc, #60]	; (8006304 <xTaskIncrementTick+0x158>)
+ 80062c6:	601a      	str	r2, [r3, #0]
+		#endif
+	}
+
+	#if ( configUSE_PREEMPTION == 1 )
+	{
+		if( xYieldPending != pdFALSE )
+ 80062c8:	4b0f      	ldr	r3, [pc, #60]	; (8006308 <xTaskIncrementTick+0x15c>)
+ 80062ca:	681b      	ldr	r3, [r3, #0]
+ 80062cc:	2b00      	cmp	r3, #0
+ 80062ce:	d001      	beq.n	80062d4 <xTaskIncrementTick+0x128>
+		{
+			xSwitchRequired = pdTRUE;
+ 80062d0:	2301      	movs	r3, #1
+ 80062d2:	617b      	str	r3, [r7, #20]
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_PREEMPTION */
+
+	return xSwitchRequired;
+ 80062d4:	697b      	ldr	r3, [r7, #20]
+}
+ 80062d6:	0018      	movs	r0, r3
+ 80062d8:	46bd      	mov	sp, r7
+ 80062da:	b006      	add	sp, #24
+ 80062dc:	bd80      	pop	{r7, pc}
+ 80062de:	46c0      	nop			; (mov r8, r8)
+ 80062e0:	20000be8 	.word	0x20000be8
+ 80062e4:	20000bc4 	.word	0x20000bc4
+ 80062e8:	20000b78 	.word	0x20000b78
+ 80062ec:	20000b7c 	.word	0x20000b7c
+ 80062f0:	20000bd8 	.word	0x20000bd8
+ 80062f4:	20000be0 	.word	0x20000be0
+ 80062f8:	20000bc8 	.word	0x20000bc8
+ 80062fc:	200006f0 	.word	0x200006f0
+ 8006300:	200006ec 	.word	0x200006ec
+ 8006304:	20000bd0 	.word	0x20000bd0
+ 8006308:	20000bd4 	.word	0x20000bd4
+
+0800630c <vTaskSwitchContext>:
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+ 800630c:	b580      	push	{r7, lr}
+ 800630e:	b082      	sub	sp, #8
+ 8006310:	af00      	add	r7, sp, #0
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+ 8006312:	4b22      	ldr	r3, [pc, #136]	; (800639c <vTaskSwitchContext+0x90>)
+ 8006314:	681b      	ldr	r3, [r3, #0]
+ 8006316:	2b00      	cmp	r3, #0
+ 8006318:	d003      	beq.n	8006322 <vTaskSwitchContext+0x16>
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+ 800631a:	4b21      	ldr	r3, [pc, #132]	; (80063a0 <vTaskSwitchContext+0x94>)
+ 800631c:	2201      	movs	r2, #1
+ 800631e:	601a      	str	r2, [r3, #0]
+			structure specific to this task. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+ 8006320:	e037      	b.n	8006392 <vTaskSwitchContext+0x86>
+		xYieldPending = pdFALSE;
+ 8006322:	4b1f      	ldr	r3, [pc, #124]	; (80063a0 <vTaskSwitchContext+0x94>)
+ 8006324:	2200      	movs	r2, #0
+ 8006326:	601a      	str	r2, [r3, #0]
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8006328:	4b1e      	ldr	r3, [pc, #120]	; (80063a4 <vTaskSwitchContext+0x98>)
+ 800632a:	681b      	ldr	r3, [r3, #0]
+ 800632c:	607b      	str	r3, [r7, #4]
+ 800632e:	e007      	b.n	8006340 <vTaskSwitchContext+0x34>
+ 8006330:	687b      	ldr	r3, [r7, #4]
+ 8006332:	2b00      	cmp	r3, #0
+ 8006334:	d101      	bne.n	800633a <vTaskSwitchContext+0x2e>
+ 8006336:	b672      	cpsid	i
+ 8006338:	e7fe      	b.n	8006338 <vTaskSwitchContext+0x2c>
+ 800633a:	687b      	ldr	r3, [r7, #4]
+ 800633c:	3b01      	subs	r3, #1
+ 800633e:	607b      	str	r3, [r7, #4]
+ 8006340:	4919      	ldr	r1, [pc, #100]	; (80063a8 <vTaskSwitchContext+0x9c>)
+ 8006342:	687a      	ldr	r2, [r7, #4]
+ 8006344:	0013      	movs	r3, r2
+ 8006346:	009b      	lsls	r3, r3, #2
+ 8006348:	189b      	adds	r3, r3, r2
+ 800634a:	009b      	lsls	r3, r3, #2
+ 800634c:	585b      	ldr	r3, [r3, r1]
+ 800634e:	2b00      	cmp	r3, #0
+ 8006350:	d0ee      	beq.n	8006330 <vTaskSwitchContext+0x24>
+ 8006352:	687a      	ldr	r2, [r7, #4]
+ 8006354:	0013      	movs	r3, r2
+ 8006356:	009b      	lsls	r3, r3, #2
+ 8006358:	189b      	adds	r3, r3, r2
+ 800635a:	009b      	lsls	r3, r3, #2
+ 800635c:	4a12      	ldr	r2, [pc, #72]	; (80063a8 <vTaskSwitchContext+0x9c>)
+ 800635e:	189b      	adds	r3, r3, r2
+ 8006360:	603b      	str	r3, [r7, #0]
+ 8006362:	683b      	ldr	r3, [r7, #0]
+ 8006364:	685b      	ldr	r3, [r3, #4]
+ 8006366:	685a      	ldr	r2, [r3, #4]
+ 8006368:	683b      	ldr	r3, [r7, #0]
+ 800636a:	605a      	str	r2, [r3, #4]
+ 800636c:	683b      	ldr	r3, [r7, #0]
+ 800636e:	685a      	ldr	r2, [r3, #4]
+ 8006370:	683b      	ldr	r3, [r7, #0]
+ 8006372:	3308      	adds	r3, #8
+ 8006374:	429a      	cmp	r2, r3
+ 8006376:	d104      	bne.n	8006382 <vTaskSwitchContext+0x76>
+ 8006378:	683b      	ldr	r3, [r7, #0]
+ 800637a:	685b      	ldr	r3, [r3, #4]
+ 800637c:	685a      	ldr	r2, [r3, #4]
+ 800637e:	683b      	ldr	r3, [r7, #0]
+ 8006380:	605a      	str	r2, [r3, #4]
+ 8006382:	683b      	ldr	r3, [r7, #0]
+ 8006384:	685b      	ldr	r3, [r3, #4]
+ 8006386:	68da      	ldr	r2, [r3, #12]
+ 8006388:	4b08      	ldr	r3, [pc, #32]	; (80063ac <vTaskSwitchContext+0xa0>)
+ 800638a:	601a      	str	r2, [r3, #0]
+ 800638c:	4b05      	ldr	r3, [pc, #20]	; (80063a4 <vTaskSwitchContext+0x98>)
+ 800638e:	687a      	ldr	r2, [r7, #4]
+ 8006390:	601a      	str	r2, [r3, #0]
+}
+ 8006392:	46c0      	nop			; (mov r8, r8)
+ 8006394:	46bd      	mov	sp, r7
+ 8006396:	b002      	add	sp, #8
+ 8006398:	bd80      	pop	{r7, pc}
+ 800639a:	46c0      	nop			; (mov r8, r8)
+ 800639c:	20000be8 	.word	0x20000be8
+ 80063a0:	20000bd4 	.word	0x20000bd4
+ 80063a4:	20000bc8 	.word	0x20000bc8
+ 80063a8:	200006f0 	.word	0x200006f0
+ 80063ac:	200006ec 	.word	0x200006ec
+
+080063b0 <vTaskPlaceOnEventList>:
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+ 80063b0:	b580      	push	{r7, lr}
+ 80063b2:	b082      	sub	sp, #8
+ 80063b4:	af00      	add	r7, sp, #0
+ 80063b6:	6078      	str	r0, [r7, #4]
+ 80063b8:	6039      	str	r1, [r7, #0]
+	configASSERT( pxEventList );
+ 80063ba:	687b      	ldr	r3, [r7, #4]
+ 80063bc:	2b00      	cmp	r3, #0
+ 80063be:	d101      	bne.n	80063c4 <vTaskPlaceOnEventList+0x14>
+ 80063c0:	b672      	cpsid	i
+ 80063c2:	e7fe      	b.n	80063c2 <vTaskPlaceOnEventList+0x12>
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+ 80063c4:	4b08      	ldr	r3, [pc, #32]	; (80063e8 <vTaskPlaceOnEventList+0x38>)
+ 80063c6:	681b      	ldr	r3, [r3, #0]
+ 80063c8:	3318      	adds	r3, #24
+ 80063ca:	001a      	movs	r2, r3
+ 80063cc:	687b      	ldr	r3, [r7, #4]
+ 80063ce:	0011      	movs	r1, r2
+ 80063d0:	0018      	movs	r0, r3
+ 80063d2:	f7fe febe 	bl	8005152 <vListInsert>
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+ 80063d6:	683b      	ldr	r3, [r7, #0]
+ 80063d8:	2101      	movs	r1, #1
+ 80063da:	0018      	movs	r0, r3
+ 80063dc:	f000 fa9c 	bl	8006918 <prvAddCurrentTaskToDelayedList>
+}
+ 80063e0:	46c0      	nop			; (mov r8, r8)
+ 80063e2:	46bd      	mov	sp, r7
+ 80063e4:	b002      	add	sp, #8
+ 80063e6:	bd80      	pop	{r7, pc}
+ 80063e8:	200006ec 	.word	0x200006ec
+
+080063ec <vTaskPlaceOnEventListRestricted>:
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+ 80063ec:	b580      	push	{r7, lr}
+ 80063ee:	b084      	sub	sp, #16
+ 80063f0:	af00      	add	r7, sp, #0
+ 80063f2:	60f8      	str	r0, [r7, #12]
+ 80063f4:	60b9      	str	r1, [r7, #8]
+ 80063f6:	607a      	str	r2, [r7, #4]
+		configASSERT( pxEventList );
+ 80063f8:	68fb      	ldr	r3, [r7, #12]
+ 80063fa:	2b00      	cmp	r3, #0
+ 80063fc:	d101      	bne.n	8006402 <vTaskPlaceOnEventListRestricted+0x16>
+ 80063fe:	b672      	cpsid	i
+ 8006400:	e7fe      	b.n	8006400 <vTaskPlaceOnEventListRestricted+0x14>
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+ 8006402:	4b0c      	ldr	r3, [pc, #48]	; (8006434 <vTaskPlaceOnEventListRestricted+0x48>)
+ 8006404:	681b      	ldr	r3, [r3, #0]
+ 8006406:	3318      	adds	r3, #24
+ 8006408:	001a      	movs	r2, r3
+ 800640a:	68fb      	ldr	r3, [r7, #12]
+ 800640c:	0011      	movs	r1, r2
+ 800640e:	0018      	movs	r0, r3
+ 8006410:	f7fe fe7d 	bl	800510e <vListInsertEnd>
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+ 8006414:	687b      	ldr	r3, [r7, #4]
+ 8006416:	2b00      	cmp	r3, #0
+ 8006418:	d002      	beq.n	8006420 <vTaskPlaceOnEventListRestricted+0x34>
+		{
+			xTicksToWait = portMAX_DELAY;
+ 800641a:	2301      	movs	r3, #1
+ 800641c:	425b      	negs	r3, r3
+ 800641e:	60bb      	str	r3, [r7, #8]
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+ 8006420:	687a      	ldr	r2, [r7, #4]
+ 8006422:	68bb      	ldr	r3, [r7, #8]
+ 8006424:	0011      	movs	r1, r2
+ 8006426:	0018      	movs	r0, r3
+ 8006428:	f000 fa76 	bl	8006918 <prvAddCurrentTaskToDelayedList>
+	}
+ 800642c:	46c0      	nop			; (mov r8, r8)
+ 800642e:	46bd      	mov	sp, r7
+ 8006430:	b004      	add	sp, #16
+ 8006432:	bd80      	pop	{r7, pc}
+ 8006434:	200006ec 	.word	0x200006ec
+
+08006438 <xTaskRemoveFromEventList>:
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+ 8006438:	b580      	push	{r7, lr}
+ 800643a:	b084      	sub	sp, #16
+ 800643c:	af00      	add	r7, sp, #0
+ 800643e:	6078      	str	r0, [r7, #4]
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8006440:	687b      	ldr	r3, [r7, #4]
+ 8006442:	68db      	ldr	r3, [r3, #12]
+ 8006444:	68db      	ldr	r3, [r3, #12]
+ 8006446:	60bb      	str	r3, [r7, #8]
+	configASSERT( pxUnblockedTCB );
+ 8006448:	68bb      	ldr	r3, [r7, #8]
+ 800644a:	2b00      	cmp	r3, #0
+ 800644c:	d101      	bne.n	8006452 <xTaskRemoveFromEventList+0x1a>
+ 800644e:	b672      	cpsid	i
+ 8006450:	e7fe      	b.n	8006450 <xTaskRemoveFromEventList+0x18>
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+ 8006452:	68bb      	ldr	r3, [r7, #8]
+ 8006454:	3318      	adds	r3, #24
+ 8006456:	0018      	movs	r0, r3
+ 8006458:	f7fe feb1 	bl	80051be <uxListRemove>
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ 800645c:	4b1f      	ldr	r3, [pc, #124]	; (80064dc <xTaskRemoveFromEventList+0xa4>)
+ 800645e:	681b      	ldr	r3, [r3, #0]
+ 8006460:	2b00      	cmp	r3, #0
+ 8006462:	d11f      	bne.n	80064a4 <xTaskRemoveFromEventList+0x6c>
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+ 8006464:	68bb      	ldr	r3, [r7, #8]
+ 8006466:	3304      	adds	r3, #4
+ 8006468:	0018      	movs	r0, r3
+ 800646a:	f7fe fea8 	bl	80051be <uxListRemove>
+		prvAddTaskToReadyList( pxUnblockedTCB );
+ 800646e:	68bb      	ldr	r3, [r7, #8]
+ 8006470:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8006472:	4b1b      	ldr	r3, [pc, #108]	; (80064e0 <xTaskRemoveFromEventList+0xa8>)
+ 8006474:	681b      	ldr	r3, [r3, #0]
+ 8006476:	429a      	cmp	r2, r3
+ 8006478:	d903      	bls.n	8006482 <xTaskRemoveFromEventList+0x4a>
+ 800647a:	68bb      	ldr	r3, [r7, #8]
+ 800647c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 800647e:	4b18      	ldr	r3, [pc, #96]	; (80064e0 <xTaskRemoveFromEventList+0xa8>)
+ 8006480:	601a      	str	r2, [r3, #0]
+ 8006482:	68bb      	ldr	r3, [r7, #8]
+ 8006484:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8006486:	0013      	movs	r3, r2
+ 8006488:	009b      	lsls	r3, r3, #2
+ 800648a:	189b      	adds	r3, r3, r2
+ 800648c:	009b      	lsls	r3, r3, #2
+ 800648e:	4a15      	ldr	r2, [pc, #84]	; (80064e4 <xTaskRemoveFromEventList+0xac>)
+ 8006490:	189a      	adds	r2, r3, r2
+ 8006492:	68bb      	ldr	r3, [r7, #8]
+ 8006494:	3304      	adds	r3, #4
+ 8006496:	0019      	movs	r1, r3
+ 8006498:	0010      	movs	r0, r2
+ 800649a:	f7fe fe38 	bl	800510e <vListInsertEnd>
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+ 800649e:	f000 f9a5 	bl	80067ec <prvResetNextTaskUnblockTime>
+ 80064a2:	e007      	b.n	80064b4 <xTaskRemoveFromEventList+0x7c>
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+ 80064a4:	68bb      	ldr	r3, [r7, #8]
+ 80064a6:	3318      	adds	r3, #24
+ 80064a8:	001a      	movs	r2, r3
+ 80064aa:	4b0f      	ldr	r3, [pc, #60]	; (80064e8 <xTaskRemoveFromEventList+0xb0>)
+ 80064ac:	0011      	movs	r1, r2
+ 80064ae:	0018      	movs	r0, r3
+ 80064b0:	f7fe fe2d 	bl	800510e <vListInsertEnd>
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ 80064b4:	68bb      	ldr	r3, [r7, #8]
+ 80064b6:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80064b8:	4b0c      	ldr	r3, [pc, #48]	; (80064ec <xTaskRemoveFromEventList+0xb4>)
+ 80064ba:	681b      	ldr	r3, [r3, #0]
+ 80064bc:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80064be:	429a      	cmp	r2, r3
+ 80064c0:	d905      	bls.n	80064ce <xTaskRemoveFromEventList+0x96>
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+ 80064c2:	2301      	movs	r3, #1
+ 80064c4:	60fb      	str	r3, [r7, #12]
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+ 80064c6:	4b0a      	ldr	r3, [pc, #40]	; (80064f0 <xTaskRemoveFromEventList+0xb8>)
+ 80064c8:	2201      	movs	r2, #1
+ 80064ca:	601a      	str	r2, [r3, #0]
+ 80064cc:	e001      	b.n	80064d2 <xTaskRemoveFromEventList+0x9a>
+	}
+	else
+	{
+		xReturn = pdFALSE;
+ 80064ce:	2300      	movs	r3, #0
+ 80064d0:	60fb      	str	r3, [r7, #12]
+	}
+
+	return xReturn;
+ 80064d2:	68fb      	ldr	r3, [r7, #12]
+}
+ 80064d4:	0018      	movs	r0, r3
+ 80064d6:	46bd      	mov	sp, r7
+ 80064d8:	b004      	add	sp, #16
+ 80064da:	bd80      	pop	{r7, pc}
+ 80064dc:	20000be8 	.word	0x20000be8
+ 80064e0:	20000bc8 	.word	0x20000bc8
+ 80064e4:	200006f0 	.word	0x200006f0
+ 80064e8:	20000b80 	.word	0x20000b80
+ 80064ec:	200006ec 	.word	0x200006ec
+ 80064f0:	20000bd4 	.word	0x20000bd4
+
+080064f4 <vTaskInternalSetTimeOutState>:
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+ 80064f4:	b580      	push	{r7, lr}
+ 80064f6:	b082      	sub	sp, #8
+ 80064f8:	af00      	add	r7, sp, #0
+ 80064fa:	6078      	str	r0, [r7, #4]
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+ 80064fc:	4b05      	ldr	r3, [pc, #20]	; (8006514 <vTaskInternalSetTimeOutState+0x20>)
+ 80064fe:	681a      	ldr	r2, [r3, #0]
+ 8006500:	687b      	ldr	r3, [r7, #4]
+ 8006502:	601a      	str	r2, [r3, #0]
+	pxTimeOut->xTimeOnEntering = xTickCount;
+ 8006504:	4b04      	ldr	r3, [pc, #16]	; (8006518 <vTaskInternalSetTimeOutState+0x24>)
+ 8006506:	681a      	ldr	r2, [r3, #0]
+ 8006508:	687b      	ldr	r3, [r7, #4]
+ 800650a:	605a      	str	r2, [r3, #4]
+}
+ 800650c:	46c0      	nop			; (mov r8, r8)
+ 800650e:	46bd      	mov	sp, r7
+ 8006510:	b002      	add	sp, #8
+ 8006512:	bd80      	pop	{r7, pc}
+ 8006514:	20000bd8 	.word	0x20000bd8
+ 8006518:	20000bc4 	.word	0x20000bc4
+
+0800651c <xTaskCheckForTimeOut>:
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+ 800651c:	b580      	push	{r7, lr}
+ 800651e:	b086      	sub	sp, #24
+ 8006520:	af00      	add	r7, sp, #0
+ 8006522:	6078      	str	r0, [r7, #4]
+ 8006524:	6039      	str	r1, [r7, #0]
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+ 8006526:	687b      	ldr	r3, [r7, #4]
+ 8006528:	2b00      	cmp	r3, #0
+ 800652a:	d101      	bne.n	8006530 <xTaskCheckForTimeOut+0x14>
+ 800652c:	b672      	cpsid	i
+ 800652e:	e7fe      	b.n	800652e <xTaskCheckForTimeOut+0x12>
+	configASSERT( pxTicksToWait );
+ 8006530:	683b      	ldr	r3, [r7, #0]
+ 8006532:	2b00      	cmp	r3, #0
+ 8006534:	d101      	bne.n	800653a <xTaskCheckForTimeOut+0x1e>
+ 8006536:	b672      	cpsid	i
+ 8006538:	e7fe      	b.n	8006538 <xTaskCheckForTimeOut+0x1c>
+
+	taskENTER_CRITICAL();
+ 800653a:	f000 fdf1 	bl	8007120 <vPortEnterCritical>
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+ 800653e:	4b24      	ldr	r3, [pc, #144]	; (80065d0 <xTaskCheckForTimeOut+0xb4>)
+ 8006540:	681b      	ldr	r3, [r3, #0]
+ 8006542:	613b      	str	r3, [r7, #16]
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+ 8006544:	687b      	ldr	r3, [r7, #4]
+ 8006546:	685b      	ldr	r3, [r3, #4]
+ 8006548:	693a      	ldr	r2, [r7, #16]
+ 800654a:	1ad3      	subs	r3, r2, r3
+ 800654c:	60fb      	str	r3, [r7, #12]
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+ 800654e:	4b21      	ldr	r3, [pc, #132]	; (80065d4 <xTaskCheckForTimeOut+0xb8>)
+ 8006550:	681b      	ldr	r3, [r3, #0]
+ 8006552:	225a      	movs	r2, #90	; 0x5a
+ 8006554:	5c9b      	ldrb	r3, [r3, r2]
+ 8006556:	2b00      	cmp	r3, #0
+ 8006558:	d007      	beq.n	800656a <xTaskCheckForTimeOut+0x4e>
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+ 800655a:	4b1e      	ldr	r3, [pc, #120]	; (80065d4 <xTaskCheckForTimeOut+0xb8>)
+ 800655c:	681b      	ldr	r3, [r3, #0]
+ 800655e:	225a      	movs	r2, #90	; 0x5a
+ 8006560:	2100      	movs	r1, #0
+ 8006562:	5499      	strb	r1, [r3, r2]
+				xReturn = pdTRUE;
+ 8006564:	2301      	movs	r3, #1
+ 8006566:	617b      	str	r3, [r7, #20]
+ 8006568:	e02b      	b.n	80065c2 <xTaskCheckForTimeOut+0xa6>
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+ 800656a:	683b      	ldr	r3, [r7, #0]
+ 800656c:	681b      	ldr	r3, [r3, #0]
+ 800656e:	3301      	adds	r3, #1
+ 8006570:	d102      	bne.n	8006578 <xTaskCheckForTimeOut+0x5c>
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+ 8006572:	2300      	movs	r3, #0
+ 8006574:	617b      	str	r3, [r7, #20]
+ 8006576:	e024      	b.n	80065c2 <xTaskCheckForTimeOut+0xa6>
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+ 8006578:	687b      	ldr	r3, [r7, #4]
+ 800657a:	681a      	ldr	r2, [r3, #0]
+ 800657c:	4b16      	ldr	r3, [pc, #88]	; (80065d8 <xTaskCheckForTimeOut+0xbc>)
+ 800657e:	681b      	ldr	r3, [r3, #0]
+ 8006580:	429a      	cmp	r2, r3
+ 8006582:	d007      	beq.n	8006594 <xTaskCheckForTimeOut+0x78>
+ 8006584:	687b      	ldr	r3, [r7, #4]
+ 8006586:	685b      	ldr	r3, [r3, #4]
+ 8006588:	693a      	ldr	r2, [r7, #16]
+ 800658a:	429a      	cmp	r2, r3
+ 800658c:	d302      	bcc.n	8006594 <xTaskCheckForTimeOut+0x78>
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+ 800658e:	2301      	movs	r3, #1
+ 8006590:	617b      	str	r3, [r7, #20]
+ 8006592:	e016      	b.n	80065c2 <xTaskCheckForTimeOut+0xa6>
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+ 8006594:	683b      	ldr	r3, [r7, #0]
+ 8006596:	681b      	ldr	r3, [r3, #0]
+ 8006598:	68fa      	ldr	r2, [r7, #12]
+ 800659a:	429a      	cmp	r2, r3
+ 800659c:	d20c      	bcs.n	80065b8 <xTaskCheckForTimeOut+0x9c>
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+ 800659e:	683b      	ldr	r3, [r7, #0]
+ 80065a0:	681a      	ldr	r2, [r3, #0]
+ 80065a2:	68fb      	ldr	r3, [r7, #12]
+ 80065a4:	1ad2      	subs	r2, r2, r3
+ 80065a6:	683b      	ldr	r3, [r7, #0]
+ 80065a8:	601a      	str	r2, [r3, #0]
+			vTaskInternalSetTimeOutState( pxTimeOut );
+ 80065aa:	687b      	ldr	r3, [r7, #4]
+ 80065ac:	0018      	movs	r0, r3
+ 80065ae:	f7ff ffa1 	bl	80064f4 <vTaskInternalSetTimeOutState>
+			xReturn = pdFALSE;
+ 80065b2:	2300      	movs	r3, #0
+ 80065b4:	617b      	str	r3, [r7, #20]
+ 80065b6:	e004      	b.n	80065c2 <xTaskCheckForTimeOut+0xa6>
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+ 80065b8:	683b      	ldr	r3, [r7, #0]
+ 80065ba:	2200      	movs	r2, #0
+ 80065bc:	601a      	str	r2, [r3, #0]
+			xReturn = pdTRUE;
+ 80065be:	2301      	movs	r3, #1
+ 80065c0:	617b      	str	r3, [r7, #20]
+		}
+	}
+	taskEXIT_CRITICAL();
+ 80065c2:	f000 fdbf 	bl	8007144 <vPortExitCritical>
+
+	return xReturn;
+ 80065c6:	697b      	ldr	r3, [r7, #20]
+}
+ 80065c8:	0018      	movs	r0, r3
+ 80065ca:	46bd      	mov	sp, r7
+ 80065cc:	b006      	add	sp, #24
+ 80065ce:	bd80      	pop	{r7, pc}
+ 80065d0:	20000bc4 	.word	0x20000bc4
+ 80065d4:	200006ec 	.word	0x200006ec
+ 80065d8:	20000bd8 	.word	0x20000bd8
+
+080065dc <vTaskMissedYield>:
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+ 80065dc:	b580      	push	{r7, lr}
+ 80065de:	af00      	add	r7, sp, #0
+	xYieldPending = pdTRUE;
+ 80065e0:	4b02      	ldr	r3, [pc, #8]	; (80065ec <vTaskMissedYield+0x10>)
+ 80065e2:	2201      	movs	r2, #1
+ 80065e4:	601a      	str	r2, [r3, #0]
+}
+ 80065e6:	46c0      	nop			; (mov r8, r8)
+ 80065e8:	46bd      	mov	sp, r7
+ 80065ea:	bd80      	pop	{r7, pc}
+ 80065ec:	20000bd4 	.word	0x20000bd4
+
+080065f0 <prvIdleTask>:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+ 80065f0:	b580      	push	{r7, lr}
+ 80065f2:	b084      	sub	sp, #16
+ 80065f4:	af00      	add	r7, sp, #0
+ 80065f6:	6078      	str	r0, [r7, #4]
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+ 80065f8:	f000 f8a2 	bl	8006740 <prvCheckTasksWaitingTermination>
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+ 80065fc:	4b12      	ldr	r3, [pc, #72]	; (8006648 <prvIdleTask+0x58>)
+ 80065fe:	681b      	ldr	r3, [r3, #0]
+ 8006600:	2b01      	cmp	r3, #1
+ 8006602:	d901      	bls.n	8006608 <prvIdleTask+0x18>
+			{
+				taskYIELD();
+ 8006604:	f000 fd7c 	bl	8007100 <vPortYield>
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+ 8006608:	f7ff fce4 	bl	8005fd4 <prvGetExpectedIdleTime>
+ 800660c:	0003      	movs	r3, r0
+ 800660e:	60fb      	str	r3, [r7, #12]
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ 8006610:	68fb      	ldr	r3, [r7, #12]
+ 8006612:	2b01      	cmp	r3, #1
+ 8006614:	d9f0      	bls.n	80065f8 <prvIdleTask+0x8>
+			{
+				vTaskSuspendAll();
+ 8006616:	f7ff fcd1 	bl	8005fbc <vTaskSuspendAll>
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+ 800661a:	4b0c      	ldr	r3, [pc, #48]	; (800664c <prvIdleTask+0x5c>)
+ 800661c:	681a      	ldr	r2, [r3, #0]
+ 800661e:	4b0c      	ldr	r3, [pc, #48]	; (8006650 <prvIdleTask+0x60>)
+ 8006620:	681b      	ldr	r3, [r3, #0]
+ 8006622:	429a      	cmp	r2, r3
+ 8006624:	d201      	bcs.n	800662a <prvIdleTask+0x3a>
+ 8006626:	b672      	cpsid	i
+ 8006628:	e7fe      	b.n	8006628 <prvIdleTask+0x38>
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+ 800662a:	f7ff fcd3 	bl	8005fd4 <prvGetExpectedIdleTime>
+ 800662e:	0003      	movs	r3, r0
+ 8006630:	60fb      	str	r3, [r7, #12]
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ 8006632:	68fb      	ldr	r3, [r7, #12]
+ 8006634:	2b01      	cmp	r3, #1
+ 8006636:	d903      	bls.n	8006640 <prvIdleTask+0x50>
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+ 8006638:	68fb      	ldr	r3, [r7, #12]
+ 800663a:	0018      	movs	r0, r3
+ 800663c:	f000 fde6 	bl	800720c <vPortSuppressTicksAndSleep>
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+ 8006640:	f7ff fcfe 	bl	8006040 <xTaskResumeAll>
+		prvCheckTasksWaitingTermination();
+ 8006644:	e7d8      	b.n	80065f8 <prvIdleTask+0x8>
+ 8006646:	46c0      	nop			; (mov r8, r8)
+ 8006648:	200006f0 	.word	0x200006f0
+ 800664c:	20000be0 	.word	0x20000be0
+ 8006650:	20000bc4 	.word	0x20000bc4
+
+08006654 <eTaskConfirmSleepModeStatus>:
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+ 8006654:	b580      	push	{r7, lr}
+ 8006656:	b082      	sub	sp, #8
+ 8006658:	af00      	add	r7, sp, #0
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+ 800665a:	2301      	movs	r3, #1
+ 800665c:	603b      	str	r3, [r7, #0]
+	eSleepModeStatus eReturn = eStandardSleep;
+ 800665e:	1dfb      	adds	r3, r7, #7
+ 8006660:	2201      	movs	r2, #1
+ 8006662:	701a      	strb	r2, [r3, #0]
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+ 8006664:	4b10      	ldr	r3, [pc, #64]	; (80066a8 <eTaskConfirmSleepModeStatus+0x54>)
+ 8006666:	681b      	ldr	r3, [r3, #0]
+ 8006668:	2b00      	cmp	r3, #0
+ 800666a:	d003      	beq.n	8006674 <eTaskConfirmSleepModeStatus+0x20>
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+ 800666c:	1dfb      	adds	r3, r7, #7
+ 800666e:	2200      	movs	r2, #0
+ 8006670:	701a      	strb	r2, [r3, #0]
+ 8006672:	e012      	b.n	800669a <eTaskConfirmSleepModeStatus+0x46>
+		}
+		else if( xYieldPending != pdFALSE )
+ 8006674:	4b0d      	ldr	r3, [pc, #52]	; (80066ac <eTaskConfirmSleepModeStatus+0x58>)
+ 8006676:	681b      	ldr	r3, [r3, #0]
+ 8006678:	2b00      	cmp	r3, #0
+ 800667a:	d003      	beq.n	8006684 <eTaskConfirmSleepModeStatus+0x30>
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+ 800667c:	1dfb      	adds	r3, r7, #7
+ 800667e:	2200      	movs	r2, #0
+ 8006680:	701a      	strb	r2, [r3, #0]
+ 8006682:	e00a      	b.n	800669a <eTaskConfirmSleepModeStatus+0x46>
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+ 8006684:	4b0a      	ldr	r3, [pc, #40]	; (80066b0 <eTaskConfirmSleepModeStatus+0x5c>)
+ 8006686:	681a      	ldr	r2, [r3, #0]
+ 8006688:	4b0a      	ldr	r3, [pc, #40]	; (80066b4 <eTaskConfirmSleepModeStatus+0x60>)
+ 800668a:	6819      	ldr	r1, [r3, #0]
+ 800668c:	683b      	ldr	r3, [r7, #0]
+ 800668e:	1acb      	subs	r3, r1, r3
+ 8006690:	429a      	cmp	r2, r3
+ 8006692:	d102      	bne.n	800669a <eTaskConfirmSleepModeStatus+0x46>
+			{
+				eReturn = eNoTasksWaitingTimeout;
+ 8006694:	1dfb      	adds	r3, r7, #7
+ 8006696:	2202      	movs	r2, #2
+ 8006698:	701a      	strb	r2, [r3, #0]
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+ 800669a:	1dfb      	adds	r3, r7, #7
+ 800669c:	781b      	ldrb	r3, [r3, #0]
+	}
+ 800669e:	0018      	movs	r0, r3
+ 80066a0:	46bd      	mov	sp, r7
+ 80066a2:	b002      	add	sp, #8
+ 80066a4:	bd80      	pop	{r7, pc}
+ 80066a6:	46c0      	nop			; (mov r8, r8)
+ 80066a8:	20000b80 	.word	0x20000b80
+ 80066ac:	20000bd4 	.word	0x20000bd4
+ 80066b0:	20000bac 	.word	0x20000bac
+ 80066b4:	20000bc0 	.word	0x20000bc0
+
+080066b8 <prvInitialiseTaskLists>:
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+ 80066b8:	b580      	push	{r7, lr}
+ 80066ba:	b082      	sub	sp, #8
+ 80066bc:	af00      	add	r7, sp, #0
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+ 80066be:	2300      	movs	r3, #0
+ 80066c0:	607b      	str	r3, [r7, #4]
+ 80066c2:	e00c      	b.n	80066de <prvInitialiseTaskLists+0x26>
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+ 80066c4:	687a      	ldr	r2, [r7, #4]
+ 80066c6:	0013      	movs	r3, r2
+ 80066c8:	009b      	lsls	r3, r3, #2
+ 80066ca:	189b      	adds	r3, r3, r2
+ 80066cc:	009b      	lsls	r3, r3, #2
+ 80066ce:	4a14      	ldr	r2, [pc, #80]	; (8006720 <prvInitialiseTaskLists+0x68>)
+ 80066d0:	189b      	adds	r3, r3, r2
+ 80066d2:	0018      	movs	r0, r3
+ 80066d4:	f7fe fcf2 	bl	80050bc <vListInitialise>
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+ 80066d8:	687b      	ldr	r3, [r7, #4]
+ 80066da:	3301      	adds	r3, #1
+ 80066dc:	607b      	str	r3, [r7, #4]
+ 80066de:	687b      	ldr	r3, [r7, #4]
+ 80066e0:	2b37      	cmp	r3, #55	; 0x37
+ 80066e2:	d9ef      	bls.n	80066c4 <prvInitialiseTaskLists+0xc>
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+ 80066e4:	4b0f      	ldr	r3, [pc, #60]	; (8006724 <prvInitialiseTaskLists+0x6c>)
+ 80066e6:	0018      	movs	r0, r3
+ 80066e8:	f7fe fce8 	bl	80050bc <vListInitialise>
+	vListInitialise( &xDelayedTaskList2 );
+ 80066ec:	4b0e      	ldr	r3, [pc, #56]	; (8006728 <prvInitialiseTaskLists+0x70>)
+ 80066ee:	0018      	movs	r0, r3
+ 80066f0:	f7fe fce4 	bl	80050bc <vListInitialise>
+	vListInitialise( &xPendingReadyList );
+ 80066f4:	4b0d      	ldr	r3, [pc, #52]	; (800672c <prvInitialiseTaskLists+0x74>)
+ 80066f6:	0018      	movs	r0, r3
+ 80066f8:	f7fe fce0 	bl	80050bc <vListInitialise>
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+ 80066fc:	4b0c      	ldr	r3, [pc, #48]	; (8006730 <prvInitialiseTaskLists+0x78>)
+ 80066fe:	0018      	movs	r0, r3
+ 8006700:	f7fe fcdc 	bl	80050bc <vListInitialise>
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+ 8006704:	4b0b      	ldr	r3, [pc, #44]	; (8006734 <prvInitialiseTaskLists+0x7c>)
+ 8006706:	0018      	movs	r0, r3
+ 8006708:	f7fe fcd8 	bl	80050bc <vListInitialise>
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+ 800670c:	4b0a      	ldr	r3, [pc, #40]	; (8006738 <prvInitialiseTaskLists+0x80>)
+ 800670e:	4a05      	ldr	r2, [pc, #20]	; (8006724 <prvInitialiseTaskLists+0x6c>)
+ 8006710:	601a      	str	r2, [r3, #0]
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+ 8006712:	4b0a      	ldr	r3, [pc, #40]	; (800673c <prvInitialiseTaskLists+0x84>)
+ 8006714:	4a04      	ldr	r2, [pc, #16]	; (8006728 <prvInitialiseTaskLists+0x70>)
+ 8006716:	601a      	str	r2, [r3, #0]
+}
+ 8006718:	46c0      	nop			; (mov r8, r8)
+ 800671a:	46bd      	mov	sp, r7
+ 800671c:	b002      	add	sp, #8
+ 800671e:	bd80      	pop	{r7, pc}
+ 8006720:	200006f0 	.word	0x200006f0
+ 8006724:	20000b50 	.word	0x20000b50
+ 8006728:	20000b64 	.word	0x20000b64
+ 800672c:	20000b80 	.word	0x20000b80
+ 8006730:	20000b94 	.word	0x20000b94
+ 8006734:	20000bac 	.word	0x20000bac
+ 8006738:	20000b78 	.word	0x20000b78
+ 800673c:	20000b7c 	.word	0x20000b7c
+
+08006740 <prvCheckTasksWaitingTermination>:
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+ 8006740:	b580      	push	{r7, lr}
+ 8006742:	b082      	sub	sp, #8
+ 8006744:	af00      	add	r7, sp, #0
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+ 8006746:	e01a      	b.n	800677e <prvCheckTasksWaitingTermination+0x3e>
+		{
+			taskENTER_CRITICAL();
+ 8006748:	f000 fcea 	bl	8007120 <vPortEnterCritical>
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 800674c:	4b10      	ldr	r3, [pc, #64]	; (8006790 <prvCheckTasksWaitingTermination+0x50>)
+ 800674e:	68db      	ldr	r3, [r3, #12]
+ 8006750:	68db      	ldr	r3, [r3, #12]
+ 8006752:	607b      	str	r3, [r7, #4]
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ 8006754:	687b      	ldr	r3, [r7, #4]
+ 8006756:	3304      	adds	r3, #4
+ 8006758:	0018      	movs	r0, r3
+ 800675a:	f7fe fd30 	bl	80051be <uxListRemove>
+				--uxCurrentNumberOfTasks;
+ 800675e:	4b0d      	ldr	r3, [pc, #52]	; (8006794 <prvCheckTasksWaitingTermination+0x54>)
+ 8006760:	681b      	ldr	r3, [r3, #0]
+ 8006762:	1e5a      	subs	r2, r3, #1
+ 8006764:	4b0b      	ldr	r3, [pc, #44]	; (8006794 <prvCheckTasksWaitingTermination+0x54>)
+ 8006766:	601a      	str	r2, [r3, #0]
+				--uxDeletedTasksWaitingCleanUp;
+ 8006768:	4b0b      	ldr	r3, [pc, #44]	; (8006798 <prvCheckTasksWaitingTermination+0x58>)
+ 800676a:	681b      	ldr	r3, [r3, #0]
+ 800676c:	1e5a      	subs	r2, r3, #1
+ 800676e:	4b0a      	ldr	r3, [pc, #40]	; (8006798 <prvCheckTasksWaitingTermination+0x58>)
+ 8006770:	601a      	str	r2, [r3, #0]
+			}
+			taskEXIT_CRITICAL();
+ 8006772:	f000 fce7 	bl	8007144 <vPortExitCritical>
+
+			prvDeleteTCB( pxTCB );
+ 8006776:	687b      	ldr	r3, [r7, #4]
+ 8006778:	0018      	movs	r0, r3
+ 800677a:	f000 f80f 	bl	800679c <prvDeleteTCB>
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+ 800677e:	4b06      	ldr	r3, [pc, #24]	; (8006798 <prvCheckTasksWaitingTermination+0x58>)
+ 8006780:	681b      	ldr	r3, [r3, #0]
+ 8006782:	2b00      	cmp	r3, #0
+ 8006784:	d1e0      	bne.n	8006748 <prvCheckTasksWaitingTermination+0x8>
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+ 8006786:	46c0      	nop			; (mov r8, r8)
+ 8006788:	46c0      	nop			; (mov r8, r8)
+ 800678a:	46bd      	mov	sp, r7
+ 800678c:	b002      	add	sp, #8
+ 800678e:	bd80      	pop	{r7, pc}
+ 8006790:	20000b94 	.word	0x20000b94
+ 8006794:	20000bc0 	.word	0x20000bc0
+ 8006798:	20000ba8 	.word	0x20000ba8
+
+0800679c <prvDeleteTCB>:
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+ 800679c:	b580      	push	{r7, lr}
+ 800679e:	b082      	sub	sp, #8
+ 80067a0:	af00      	add	r7, sp, #0
+ 80067a2:	6078      	str	r0, [r7, #4]
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+ 80067a4:	687b      	ldr	r3, [r7, #4]
+ 80067a6:	2259      	movs	r2, #89	; 0x59
+ 80067a8:	5c9b      	ldrb	r3, [r3, r2]
+ 80067aa:	2b00      	cmp	r3, #0
+ 80067ac:	d109      	bne.n	80067c2 <prvDeleteTCB+0x26>
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+ 80067ae:	687b      	ldr	r3, [r7, #4]
+ 80067b0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80067b2:	0018      	movs	r0, r3
+ 80067b4:	f000 fed6 	bl	8007564 <vPortFree>
+				vPortFree( pxTCB );
+ 80067b8:	687b      	ldr	r3, [r7, #4]
+ 80067ba:	0018      	movs	r0, r3
+ 80067bc:	f000 fed2 	bl	8007564 <vPortFree>
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+ 80067c0:	e010      	b.n	80067e4 <prvDeleteTCB+0x48>
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+ 80067c2:	687b      	ldr	r3, [r7, #4]
+ 80067c4:	2259      	movs	r2, #89	; 0x59
+ 80067c6:	5c9b      	ldrb	r3, [r3, r2]
+ 80067c8:	2b01      	cmp	r3, #1
+ 80067ca:	d104      	bne.n	80067d6 <prvDeleteTCB+0x3a>
+				vPortFree( pxTCB );
+ 80067cc:	687b      	ldr	r3, [r7, #4]
+ 80067ce:	0018      	movs	r0, r3
+ 80067d0:	f000 fec8 	bl	8007564 <vPortFree>
+	}
+ 80067d4:	e006      	b.n	80067e4 <prvDeleteTCB+0x48>
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+ 80067d6:	687b      	ldr	r3, [r7, #4]
+ 80067d8:	2259      	movs	r2, #89	; 0x59
+ 80067da:	5c9b      	ldrb	r3, [r3, r2]
+ 80067dc:	2b02      	cmp	r3, #2
+ 80067de:	d001      	beq.n	80067e4 <prvDeleteTCB+0x48>
+ 80067e0:	b672      	cpsid	i
+ 80067e2:	e7fe      	b.n	80067e2 <prvDeleteTCB+0x46>
+	}
+ 80067e4:	46c0      	nop			; (mov r8, r8)
+ 80067e6:	46bd      	mov	sp, r7
+ 80067e8:	b002      	add	sp, #8
+ 80067ea:	bd80      	pop	{r7, pc}
+
+080067ec <prvResetNextTaskUnblockTime>:
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+ 80067ec:	b580      	push	{r7, lr}
+ 80067ee:	b082      	sub	sp, #8
+ 80067f0:	af00      	add	r7, sp, #0
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ 80067f2:	4b0b      	ldr	r3, [pc, #44]	; (8006820 <prvResetNextTaskUnblockTime+0x34>)
+ 80067f4:	681b      	ldr	r3, [r3, #0]
+ 80067f6:	681b      	ldr	r3, [r3, #0]
+ 80067f8:	2b00      	cmp	r3, #0
+ 80067fa:	d104      	bne.n	8006806 <prvResetNextTaskUnblockTime+0x1a>
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+ 80067fc:	4b09      	ldr	r3, [pc, #36]	; (8006824 <prvResetNextTaskUnblockTime+0x38>)
+ 80067fe:	2201      	movs	r2, #1
+ 8006800:	4252      	negs	r2, r2
+ 8006802:	601a      	str	r2, [r3, #0]
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+ 8006804:	e008      	b.n	8006818 <prvResetNextTaskUnblockTime+0x2c>
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8006806:	4b06      	ldr	r3, [pc, #24]	; (8006820 <prvResetNextTaskUnblockTime+0x34>)
+ 8006808:	681b      	ldr	r3, [r3, #0]
+ 800680a:	68db      	ldr	r3, [r3, #12]
+ 800680c:	68db      	ldr	r3, [r3, #12]
+ 800680e:	607b      	str	r3, [r7, #4]
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+ 8006810:	687b      	ldr	r3, [r7, #4]
+ 8006812:	685a      	ldr	r2, [r3, #4]
+ 8006814:	4b03      	ldr	r3, [pc, #12]	; (8006824 <prvResetNextTaskUnblockTime+0x38>)
+ 8006816:	601a      	str	r2, [r3, #0]
+}
+ 8006818:	46c0      	nop			; (mov r8, r8)
+ 800681a:	46bd      	mov	sp, r7
+ 800681c:	b002      	add	sp, #8
+ 800681e:	bd80      	pop	{r7, pc}
+ 8006820:	20000b78 	.word	0x20000b78
+ 8006824:	20000be0 	.word	0x20000be0
+
+08006828 <xTaskGetSchedulerState>:
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+ 8006828:	b580      	push	{r7, lr}
+ 800682a:	b082      	sub	sp, #8
+ 800682c:	af00      	add	r7, sp, #0
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+ 800682e:	4b0a      	ldr	r3, [pc, #40]	; (8006858 <xTaskGetSchedulerState+0x30>)
+ 8006830:	681b      	ldr	r3, [r3, #0]
+ 8006832:	2b00      	cmp	r3, #0
+ 8006834:	d102      	bne.n	800683c <xTaskGetSchedulerState+0x14>
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+ 8006836:	2301      	movs	r3, #1
+ 8006838:	607b      	str	r3, [r7, #4]
+ 800683a:	e008      	b.n	800684e <xTaskGetSchedulerState+0x26>
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ 800683c:	4b07      	ldr	r3, [pc, #28]	; (800685c <xTaskGetSchedulerState+0x34>)
+ 800683e:	681b      	ldr	r3, [r3, #0]
+ 8006840:	2b00      	cmp	r3, #0
+ 8006842:	d102      	bne.n	800684a <xTaskGetSchedulerState+0x22>
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+ 8006844:	2302      	movs	r3, #2
+ 8006846:	607b      	str	r3, [r7, #4]
+ 8006848:	e001      	b.n	800684e <xTaskGetSchedulerState+0x26>
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+ 800684a:	2300      	movs	r3, #0
+ 800684c:	607b      	str	r3, [r7, #4]
+			}
+		}
+
+		return xReturn;
+ 800684e:	687b      	ldr	r3, [r7, #4]
+	}
+ 8006850:	0018      	movs	r0, r3
+ 8006852:	46bd      	mov	sp, r7
+ 8006854:	b002      	add	sp, #8
+ 8006856:	bd80      	pop	{r7, pc}
+ 8006858:	20000bcc 	.word	0x20000bcc
+ 800685c:	20000be8 	.word	0x20000be8
+
+08006860 <xTaskPriorityDisinherit>:
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+ 8006860:	b580      	push	{r7, lr}
+ 8006862:	b084      	sub	sp, #16
+ 8006864:	af00      	add	r7, sp, #0
+ 8006866:	6078      	str	r0, [r7, #4]
+	TCB_t * const pxTCB = pxMutexHolder;
+ 8006868:	687b      	ldr	r3, [r7, #4]
+ 800686a:	60bb      	str	r3, [r7, #8]
+	BaseType_t xReturn = pdFALSE;
+ 800686c:	2300      	movs	r3, #0
+ 800686e:	60fb      	str	r3, [r7, #12]
+
+		if( pxMutexHolder != NULL )
+ 8006870:	687b      	ldr	r3, [r7, #4]
+ 8006872:	2b00      	cmp	r3, #0
+ 8006874:	d044      	beq.n	8006900 <xTaskPriorityDisinherit+0xa0>
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+ 8006876:	4b25      	ldr	r3, [pc, #148]	; (800690c <xTaskPriorityDisinherit+0xac>)
+ 8006878:	681b      	ldr	r3, [r3, #0]
+ 800687a:	68ba      	ldr	r2, [r7, #8]
+ 800687c:	429a      	cmp	r2, r3
+ 800687e:	d001      	beq.n	8006884 <xTaskPriorityDisinherit+0x24>
+ 8006880:	b672      	cpsid	i
+ 8006882:	e7fe      	b.n	8006882 <xTaskPriorityDisinherit+0x22>
+			configASSERT( pxTCB->uxMutexesHeld );
+ 8006884:	68bb      	ldr	r3, [r7, #8]
+ 8006886:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8006888:	2b00      	cmp	r3, #0
+ 800688a:	d101      	bne.n	8006890 <xTaskPriorityDisinherit+0x30>
+ 800688c:	b672      	cpsid	i
+ 800688e:	e7fe      	b.n	800688e <xTaskPriorityDisinherit+0x2e>
+			( pxTCB->uxMutexesHeld )--;
+ 8006890:	68bb      	ldr	r3, [r7, #8]
+ 8006892:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8006894:	1e5a      	subs	r2, r3, #1
+ 8006896:	68bb      	ldr	r3, [r7, #8]
+ 8006898:	651a      	str	r2, [r3, #80]	; 0x50
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+ 800689a:	68bb      	ldr	r3, [r7, #8]
+ 800689c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 800689e:	68bb      	ldr	r3, [r7, #8]
+ 80068a0:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 80068a2:	429a      	cmp	r2, r3
+ 80068a4:	d02c      	beq.n	8006900 <xTaskPriorityDisinherit+0xa0>
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+ 80068a6:	68bb      	ldr	r3, [r7, #8]
+ 80068a8:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80068aa:	2b00      	cmp	r3, #0
+ 80068ac:	d128      	bne.n	8006900 <xTaskPriorityDisinherit+0xa0>
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ 80068ae:	68bb      	ldr	r3, [r7, #8]
+ 80068b0:	3304      	adds	r3, #4
+ 80068b2:	0018      	movs	r0, r3
+ 80068b4:	f7fe fc83 	bl	80051be <uxListRemove>
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+ 80068b8:	68bb      	ldr	r3, [r7, #8]
+ 80068ba:	6cda      	ldr	r2, [r3, #76]	; 0x4c
+ 80068bc:	68bb      	ldr	r3, [r7, #8]
+ 80068be:	62da      	str	r2, [r3, #44]	; 0x2c
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 80068c0:	68bb      	ldr	r3, [r7, #8]
+ 80068c2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80068c4:	2238      	movs	r2, #56	; 0x38
+ 80068c6:	1ad2      	subs	r2, r2, r3
+ 80068c8:	68bb      	ldr	r3, [r7, #8]
+ 80068ca:	619a      	str	r2, [r3, #24]
+					prvAddTaskToReadyList( pxTCB );
+ 80068cc:	68bb      	ldr	r3, [r7, #8]
+ 80068ce:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80068d0:	4b0f      	ldr	r3, [pc, #60]	; (8006910 <xTaskPriorityDisinherit+0xb0>)
+ 80068d2:	681b      	ldr	r3, [r3, #0]
+ 80068d4:	429a      	cmp	r2, r3
+ 80068d6:	d903      	bls.n	80068e0 <xTaskPriorityDisinherit+0x80>
+ 80068d8:	68bb      	ldr	r3, [r7, #8]
+ 80068da:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80068dc:	4b0c      	ldr	r3, [pc, #48]	; (8006910 <xTaskPriorityDisinherit+0xb0>)
+ 80068de:	601a      	str	r2, [r3, #0]
+ 80068e0:	68bb      	ldr	r3, [r7, #8]
+ 80068e2:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80068e4:	0013      	movs	r3, r2
+ 80068e6:	009b      	lsls	r3, r3, #2
+ 80068e8:	189b      	adds	r3, r3, r2
+ 80068ea:	009b      	lsls	r3, r3, #2
+ 80068ec:	4a09      	ldr	r2, [pc, #36]	; (8006914 <xTaskPriorityDisinherit+0xb4>)
+ 80068ee:	189a      	adds	r2, r3, r2
+ 80068f0:	68bb      	ldr	r3, [r7, #8]
+ 80068f2:	3304      	adds	r3, #4
+ 80068f4:	0019      	movs	r1, r3
+ 80068f6:	0010      	movs	r0, r2
+ 80068f8:	f7fe fc09 	bl	800510e <vListInsertEnd>
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+ 80068fc:	2301      	movs	r3, #1
+ 80068fe:	60fb      	str	r3, [r7, #12]
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+ 8006900:	68fb      	ldr	r3, [r7, #12]
+	}
+ 8006902:	0018      	movs	r0, r3
+ 8006904:	46bd      	mov	sp, r7
+ 8006906:	b004      	add	sp, #16
+ 8006908:	bd80      	pop	{r7, pc}
+ 800690a:	46c0      	nop			; (mov r8, r8)
+ 800690c:	200006ec 	.word	0x200006ec
+ 8006910:	20000bc8 	.word	0x20000bc8
+ 8006914:	200006f0 	.word	0x200006f0
+
+08006918 <prvAddCurrentTaskToDelayedList>:
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+ 8006918:	b580      	push	{r7, lr}
+ 800691a:	b084      	sub	sp, #16
+ 800691c:	af00      	add	r7, sp, #0
+ 800691e:	6078      	str	r0, [r7, #4]
+ 8006920:	6039      	str	r1, [r7, #0]
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+ 8006922:	4b24      	ldr	r3, [pc, #144]	; (80069b4 <prvAddCurrentTaskToDelayedList+0x9c>)
+ 8006924:	681b      	ldr	r3, [r3, #0]
+ 8006926:	60fb      	str	r3, [r7, #12]
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+ 8006928:	4b23      	ldr	r3, [pc, #140]	; (80069b8 <prvAddCurrentTaskToDelayedList+0xa0>)
+ 800692a:	681b      	ldr	r3, [r3, #0]
+ 800692c:	225a      	movs	r2, #90	; 0x5a
+ 800692e:	2100      	movs	r1, #0
+ 8006930:	5499      	strb	r1, [r3, r2]
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ 8006932:	4b21      	ldr	r3, [pc, #132]	; (80069b8 <prvAddCurrentTaskToDelayedList+0xa0>)
+ 8006934:	681b      	ldr	r3, [r3, #0]
+ 8006936:	3304      	adds	r3, #4
+ 8006938:	0018      	movs	r0, r3
+ 800693a:	f7fe fc40 	bl	80051be <uxListRemove>
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+ 800693e:	687b      	ldr	r3, [r7, #4]
+ 8006940:	3301      	adds	r3, #1
+ 8006942:	d10b      	bne.n	800695c <prvAddCurrentTaskToDelayedList+0x44>
+ 8006944:	683b      	ldr	r3, [r7, #0]
+ 8006946:	2b00      	cmp	r3, #0
+ 8006948:	d008      	beq.n	800695c <prvAddCurrentTaskToDelayedList+0x44>
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ 800694a:	4b1b      	ldr	r3, [pc, #108]	; (80069b8 <prvAddCurrentTaskToDelayedList+0xa0>)
+ 800694c:	681b      	ldr	r3, [r3, #0]
+ 800694e:	1d1a      	adds	r2, r3, #4
+ 8006950:	4b1a      	ldr	r3, [pc, #104]	; (80069bc <prvAddCurrentTaskToDelayedList+0xa4>)
+ 8006952:	0011      	movs	r1, r2
+ 8006954:	0018      	movs	r0, r3
+ 8006956:	f7fe fbda 	bl	800510e <vListInsertEnd>
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+ 800695a:	e026      	b.n	80069aa <prvAddCurrentTaskToDelayedList+0x92>
+			xTimeToWake = xConstTickCount + xTicksToWait;
+ 800695c:	68fa      	ldr	r2, [r7, #12]
+ 800695e:	687b      	ldr	r3, [r7, #4]
+ 8006960:	18d3      	adds	r3, r2, r3
+ 8006962:	60bb      	str	r3, [r7, #8]
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+ 8006964:	4b14      	ldr	r3, [pc, #80]	; (80069b8 <prvAddCurrentTaskToDelayedList+0xa0>)
+ 8006966:	681b      	ldr	r3, [r3, #0]
+ 8006968:	68ba      	ldr	r2, [r7, #8]
+ 800696a:	605a      	str	r2, [r3, #4]
+			if( xTimeToWake < xConstTickCount )
+ 800696c:	68ba      	ldr	r2, [r7, #8]
+ 800696e:	68fb      	ldr	r3, [r7, #12]
+ 8006970:	429a      	cmp	r2, r3
+ 8006972:	d209      	bcs.n	8006988 <prvAddCurrentTaskToDelayedList+0x70>
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ 8006974:	4b12      	ldr	r3, [pc, #72]	; (80069c0 <prvAddCurrentTaskToDelayedList+0xa8>)
+ 8006976:	681a      	ldr	r2, [r3, #0]
+ 8006978:	4b0f      	ldr	r3, [pc, #60]	; (80069b8 <prvAddCurrentTaskToDelayedList+0xa0>)
+ 800697a:	681b      	ldr	r3, [r3, #0]
+ 800697c:	3304      	adds	r3, #4
+ 800697e:	0019      	movs	r1, r3
+ 8006980:	0010      	movs	r0, r2
+ 8006982:	f7fe fbe6 	bl	8005152 <vListInsert>
+}
+ 8006986:	e010      	b.n	80069aa <prvAddCurrentTaskToDelayedList+0x92>
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ 8006988:	4b0e      	ldr	r3, [pc, #56]	; (80069c4 <prvAddCurrentTaskToDelayedList+0xac>)
+ 800698a:	681a      	ldr	r2, [r3, #0]
+ 800698c:	4b0a      	ldr	r3, [pc, #40]	; (80069b8 <prvAddCurrentTaskToDelayedList+0xa0>)
+ 800698e:	681b      	ldr	r3, [r3, #0]
+ 8006990:	3304      	adds	r3, #4
+ 8006992:	0019      	movs	r1, r3
+ 8006994:	0010      	movs	r0, r2
+ 8006996:	f7fe fbdc 	bl	8005152 <vListInsert>
+				if( xTimeToWake < xNextTaskUnblockTime )
+ 800699a:	4b0b      	ldr	r3, [pc, #44]	; (80069c8 <prvAddCurrentTaskToDelayedList+0xb0>)
+ 800699c:	681b      	ldr	r3, [r3, #0]
+ 800699e:	68ba      	ldr	r2, [r7, #8]
+ 80069a0:	429a      	cmp	r2, r3
+ 80069a2:	d202      	bcs.n	80069aa <prvAddCurrentTaskToDelayedList+0x92>
+					xNextTaskUnblockTime = xTimeToWake;
+ 80069a4:	4b08      	ldr	r3, [pc, #32]	; (80069c8 <prvAddCurrentTaskToDelayedList+0xb0>)
+ 80069a6:	68ba      	ldr	r2, [r7, #8]
+ 80069a8:	601a      	str	r2, [r3, #0]
+}
+ 80069aa:	46c0      	nop			; (mov r8, r8)
+ 80069ac:	46bd      	mov	sp, r7
+ 80069ae:	b004      	add	sp, #16
+ 80069b0:	bd80      	pop	{r7, pc}
+ 80069b2:	46c0      	nop			; (mov r8, r8)
+ 80069b4:	20000bc4 	.word	0x20000bc4
+ 80069b8:	200006ec 	.word	0x200006ec
+ 80069bc:	20000bac 	.word	0x20000bac
+ 80069c0:	20000b7c 	.word	0x20000b7c
+ 80069c4:	20000b78 	.word	0x20000b78
+ 80069c8:	20000be0 	.word	0x20000be0
+
+080069cc <xTimerCreateTimerTask>:
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+ 80069cc:	b590      	push	{r4, r7, lr}
+ 80069ce:	b089      	sub	sp, #36	; 0x24
+ 80069d0:	af04      	add	r7, sp, #16
+BaseType_t xReturn = pdFAIL;
+ 80069d2:	2300      	movs	r3, #0
+ 80069d4:	60fb      	str	r3, [r7, #12]
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+ 80069d6:	f000 fac9 	bl	8006f6c <prvCheckForValidListAndQueue>
+
+	if( xTimerQueue != NULL )
+ 80069da:	4b17      	ldr	r3, [pc, #92]	; (8006a38 <xTimerCreateTimerTask+0x6c>)
+ 80069dc:	681b      	ldr	r3, [r3, #0]
+ 80069de:	2b00      	cmp	r3, #0
+ 80069e0:	d020      	beq.n	8006a24 <xTimerCreateTimerTask+0x58>
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+ 80069e2:	2300      	movs	r3, #0
+ 80069e4:	60bb      	str	r3, [r7, #8]
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+ 80069e6:	2300      	movs	r3, #0
+ 80069e8:	607b      	str	r3, [r7, #4]
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+ 80069ea:	003a      	movs	r2, r7
+ 80069ec:	1d39      	adds	r1, r7, #4
+ 80069ee:	2308      	movs	r3, #8
+ 80069f0:	18fb      	adds	r3, r7, r3
+ 80069f2:	0018      	movs	r0, r3
+ 80069f4:	f7fe fb4a 	bl	800508c <vApplicationGetTimerTaskMemory>
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+ 80069f8:	683c      	ldr	r4, [r7, #0]
+ 80069fa:	687b      	ldr	r3, [r7, #4]
+ 80069fc:	68ba      	ldr	r2, [r7, #8]
+ 80069fe:	490f      	ldr	r1, [pc, #60]	; (8006a3c <xTimerCreateTimerTask+0x70>)
+ 8006a00:	480f      	ldr	r0, [pc, #60]	; (8006a40 <xTimerCreateTimerTask+0x74>)
+ 8006a02:	9202      	str	r2, [sp, #8]
+ 8006a04:	9301      	str	r3, [sp, #4]
+ 8006a06:	2302      	movs	r3, #2
+ 8006a08:	9300      	str	r3, [sp, #0]
+ 8006a0a:	2300      	movs	r3, #0
+ 8006a0c:	0022      	movs	r2, r4
+ 8006a0e:	f7ff f860 	bl	8005ad2 <xTaskCreateStatic>
+ 8006a12:	0002      	movs	r2, r0
+ 8006a14:	4b0b      	ldr	r3, [pc, #44]	; (8006a44 <xTimerCreateTimerTask+0x78>)
+ 8006a16:	601a      	str	r2, [r3, #0]
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+ 8006a18:	4b0a      	ldr	r3, [pc, #40]	; (8006a44 <xTimerCreateTimerTask+0x78>)
+ 8006a1a:	681b      	ldr	r3, [r3, #0]
+ 8006a1c:	2b00      	cmp	r3, #0
+ 8006a1e:	d001      	beq.n	8006a24 <xTimerCreateTimerTask+0x58>
+			{
+				xReturn = pdPASS;
+ 8006a20:	2301      	movs	r3, #1
+ 8006a22:	60fb      	str	r3, [r7, #12]
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+ 8006a24:	68fb      	ldr	r3, [r7, #12]
+ 8006a26:	2b00      	cmp	r3, #0
+ 8006a28:	d101      	bne.n	8006a2e <xTimerCreateTimerTask+0x62>
+ 8006a2a:	b672      	cpsid	i
+ 8006a2c:	e7fe      	b.n	8006a2c <xTimerCreateTimerTask+0x60>
+	return xReturn;
+ 8006a2e:	68fb      	ldr	r3, [r7, #12]
+}
+ 8006a30:	0018      	movs	r0, r3
+ 8006a32:	46bd      	mov	sp, r7
+ 8006a34:	b005      	add	sp, #20
+ 8006a36:	bd90      	pop	{r4, r7, pc}
+ 8006a38:	20000c1c 	.word	0x20000c1c
+ 8006a3c:	0800780c 	.word	0x0800780c
+ 8006a40:	08006b65 	.word	0x08006b65
+ 8006a44:	20000c20 	.word	0x20000c20
+
+08006a48 <xTimerGenericCommand>:
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+ 8006a48:	b590      	push	{r4, r7, lr}
+ 8006a4a:	b08b      	sub	sp, #44	; 0x2c
+ 8006a4c:	af00      	add	r7, sp, #0
+ 8006a4e:	60f8      	str	r0, [r7, #12]
+ 8006a50:	60b9      	str	r1, [r7, #8]
+ 8006a52:	607a      	str	r2, [r7, #4]
+ 8006a54:	603b      	str	r3, [r7, #0]
+BaseType_t xReturn = pdFAIL;
+ 8006a56:	2300      	movs	r3, #0
+ 8006a58:	627b      	str	r3, [r7, #36]	; 0x24
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+ 8006a5a:	68fb      	ldr	r3, [r7, #12]
+ 8006a5c:	2b00      	cmp	r3, #0
+ 8006a5e:	d101      	bne.n	8006a64 <xTimerGenericCommand+0x1c>
+ 8006a60:	b672      	cpsid	i
+ 8006a62:	e7fe      	b.n	8006a62 <xTimerGenericCommand+0x1a>
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+ 8006a64:	4b1c      	ldr	r3, [pc, #112]	; (8006ad8 <xTimerGenericCommand+0x90>)
+ 8006a66:	681b      	ldr	r3, [r3, #0]
+ 8006a68:	2b00      	cmp	r3, #0
+ 8006a6a:	d030      	beq.n	8006ace <xTimerGenericCommand+0x86>
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+ 8006a6c:	2414      	movs	r4, #20
+ 8006a6e:	193b      	adds	r3, r7, r4
+ 8006a70:	68ba      	ldr	r2, [r7, #8]
+ 8006a72:	601a      	str	r2, [r3, #0]
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+ 8006a74:	193b      	adds	r3, r7, r4
+ 8006a76:	687a      	ldr	r2, [r7, #4]
+ 8006a78:	605a      	str	r2, [r3, #4]
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+ 8006a7a:	193b      	adds	r3, r7, r4
+ 8006a7c:	68fa      	ldr	r2, [r7, #12]
+ 8006a7e:	609a      	str	r2, [r3, #8]
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+ 8006a80:	68bb      	ldr	r3, [r7, #8]
+ 8006a82:	2b05      	cmp	r3, #5
+ 8006a84:	dc19      	bgt.n	8006aba <xTimerGenericCommand+0x72>
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+ 8006a86:	f7ff fecf 	bl	8006828 <xTaskGetSchedulerState>
+ 8006a8a:	0003      	movs	r3, r0
+ 8006a8c:	2b02      	cmp	r3, #2
+ 8006a8e:	d109      	bne.n	8006aa4 <xTimerGenericCommand+0x5c>
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+ 8006a90:	4b11      	ldr	r3, [pc, #68]	; (8006ad8 <xTimerGenericCommand+0x90>)
+ 8006a92:	6818      	ldr	r0, [r3, #0]
+ 8006a94:	6bba      	ldr	r2, [r7, #56]	; 0x38
+ 8006a96:	1939      	adds	r1, r7, r4
+ 8006a98:	2300      	movs	r3, #0
+ 8006a9a:	f7fe fcb7 	bl	800540c <xQueueGenericSend>
+ 8006a9e:	0003      	movs	r3, r0
+ 8006aa0:	627b      	str	r3, [r7, #36]	; 0x24
+ 8006aa2:	e014      	b.n	8006ace <xTimerGenericCommand+0x86>
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+ 8006aa4:	4b0c      	ldr	r3, [pc, #48]	; (8006ad8 <xTimerGenericCommand+0x90>)
+ 8006aa6:	6818      	ldr	r0, [r3, #0]
+ 8006aa8:	2314      	movs	r3, #20
+ 8006aaa:	18f9      	adds	r1, r7, r3
+ 8006aac:	2300      	movs	r3, #0
+ 8006aae:	2200      	movs	r2, #0
+ 8006ab0:	f7fe fcac 	bl	800540c <xQueueGenericSend>
+ 8006ab4:	0003      	movs	r3, r0
+ 8006ab6:	627b      	str	r3, [r7, #36]	; 0x24
+ 8006ab8:	e009      	b.n	8006ace <xTimerGenericCommand+0x86>
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+ 8006aba:	4b07      	ldr	r3, [pc, #28]	; (8006ad8 <xTimerGenericCommand+0x90>)
+ 8006abc:	6818      	ldr	r0, [r3, #0]
+ 8006abe:	683a      	ldr	r2, [r7, #0]
+ 8006ac0:	2314      	movs	r3, #20
+ 8006ac2:	18f9      	adds	r1, r7, r3
+ 8006ac4:	2300      	movs	r3, #0
+ 8006ac6:	f7fe fd65 	bl	8005594 <xQueueGenericSendFromISR>
+ 8006aca:	0003      	movs	r3, r0
+ 8006acc:	627b      	str	r3, [r7, #36]	; 0x24
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+ 8006ace:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+}
+ 8006ad0:	0018      	movs	r0, r3
+ 8006ad2:	46bd      	mov	sp, r7
+ 8006ad4:	b00b      	add	sp, #44	; 0x2c
+ 8006ad6:	bd90      	pop	{r4, r7, pc}
+ 8006ad8:	20000c1c 	.word	0x20000c1c
+
+08006adc <prvProcessExpiredTimer>:
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+ 8006adc:	b580      	push	{r7, lr}
+ 8006ade:	b086      	sub	sp, #24
+ 8006ae0:	af02      	add	r7, sp, #8
+ 8006ae2:	6078      	str	r0, [r7, #4]
+ 8006ae4:	6039      	str	r1, [r7, #0]
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8006ae6:	4b1e      	ldr	r3, [pc, #120]	; (8006b60 <prvProcessExpiredTimer+0x84>)
+ 8006ae8:	681b      	ldr	r3, [r3, #0]
+ 8006aea:	68db      	ldr	r3, [r3, #12]
+ 8006aec:	68db      	ldr	r3, [r3, #12]
+ 8006aee:	60fb      	str	r3, [r7, #12]
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ 8006af0:	68fb      	ldr	r3, [r7, #12]
+ 8006af2:	3304      	adds	r3, #4
+ 8006af4:	0018      	movs	r0, r3
+ 8006af6:	f7fe fb62 	bl	80051be <uxListRemove>
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ 8006afa:	68fb      	ldr	r3, [r7, #12]
+ 8006afc:	2228      	movs	r2, #40	; 0x28
+ 8006afe:	5c9b      	ldrb	r3, [r3, r2]
+ 8006b00:	001a      	movs	r2, r3
+ 8006b02:	2304      	movs	r3, #4
+ 8006b04:	4013      	ands	r3, r2
+ 8006b06:	d019      	beq.n	8006b3c <prvProcessExpiredTimer+0x60>
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+ 8006b08:	68fb      	ldr	r3, [r7, #12]
+ 8006b0a:	699a      	ldr	r2, [r3, #24]
+ 8006b0c:	687b      	ldr	r3, [r7, #4]
+ 8006b0e:	18d1      	adds	r1, r2, r3
+ 8006b10:	687b      	ldr	r3, [r7, #4]
+ 8006b12:	683a      	ldr	r2, [r7, #0]
+ 8006b14:	68f8      	ldr	r0, [r7, #12]
+ 8006b16:	f000 f8c3 	bl	8006ca0 <prvInsertTimerInActiveList>
+ 8006b1a:	1e03      	subs	r3, r0, #0
+ 8006b1c:	d017      	beq.n	8006b4e <prvProcessExpiredTimer+0x72>
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+ 8006b1e:	687a      	ldr	r2, [r7, #4]
+ 8006b20:	68f8      	ldr	r0, [r7, #12]
+ 8006b22:	2300      	movs	r3, #0
+ 8006b24:	9300      	str	r3, [sp, #0]
+ 8006b26:	2300      	movs	r3, #0
+ 8006b28:	2100      	movs	r1, #0
+ 8006b2a:	f7ff ff8d 	bl	8006a48 <xTimerGenericCommand>
+ 8006b2e:	0003      	movs	r3, r0
+ 8006b30:	60bb      	str	r3, [r7, #8]
+			configASSERT( xResult );
+ 8006b32:	68bb      	ldr	r3, [r7, #8]
+ 8006b34:	2b00      	cmp	r3, #0
+ 8006b36:	d10a      	bne.n	8006b4e <prvProcessExpiredTimer+0x72>
+ 8006b38:	b672      	cpsid	i
+ 8006b3a:	e7fe      	b.n	8006b3a <prvProcessExpiredTimer+0x5e>
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ 8006b3c:	68fb      	ldr	r3, [r7, #12]
+ 8006b3e:	2228      	movs	r2, #40	; 0x28
+ 8006b40:	5c9b      	ldrb	r3, [r3, r2]
+ 8006b42:	2201      	movs	r2, #1
+ 8006b44:	4393      	bics	r3, r2
+ 8006b46:	b2d9      	uxtb	r1, r3
+ 8006b48:	68fb      	ldr	r3, [r7, #12]
+ 8006b4a:	2228      	movs	r2, #40	; 0x28
+ 8006b4c:	5499      	strb	r1, [r3, r2]
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ 8006b4e:	68fb      	ldr	r3, [r7, #12]
+ 8006b50:	6a1b      	ldr	r3, [r3, #32]
+ 8006b52:	68fa      	ldr	r2, [r7, #12]
+ 8006b54:	0010      	movs	r0, r2
+ 8006b56:	4798      	blx	r3
+}
+ 8006b58:	46c0      	nop			; (mov r8, r8)
+ 8006b5a:	46bd      	mov	sp, r7
+ 8006b5c:	b004      	add	sp, #16
+ 8006b5e:	bd80      	pop	{r7, pc}
+ 8006b60:	20000c14 	.word	0x20000c14
+
+08006b64 <prvTimerTask>:
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+ 8006b64:	b580      	push	{r7, lr}
+ 8006b66:	b084      	sub	sp, #16
+ 8006b68:	af00      	add	r7, sp, #0
+ 8006b6a:	6078      	str	r0, [r7, #4]
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+ 8006b6c:	2308      	movs	r3, #8
+ 8006b6e:	18fb      	adds	r3, r7, r3
+ 8006b70:	0018      	movs	r0, r3
+ 8006b72:	f000 f853 	bl	8006c1c <prvGetNextExpireTime>
+ 8006b76:	0003      	movs	r3, r0
+ 8006b78:	60fb      	str	r3, [r7, #12]
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+ 8006b7a:	68ba      	ldr	r2, [r7, #8]
+ 8006b7c:	68fb      	ldr	r3, [r7, #12]
+ 8006b7e:	0011      	movs	r1, r2
+ 8006b80:	0018      	movs	r0, r3
+ 8006b82:	f000 f803 	bl	8006b8c <prvProcessTimerOrBlockTask>
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+ 8006b86:	f000 f8cd 	bl	8006d24 <prvProcessReceivedCommands>
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+ 8006b8a:	e7ef      	b.n	8006b6c <prvTimerTask+0x8>
+
+08006b8c <prvProcessTimerOrBlockTask>:
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+ 8006b8c:	b580      	push	{r7, lr}
+ 8006b8e:	b084      	sub	sp, #16
+ 8006b90:	af00      	add	r7, sp, #0
+ 8006b92:	6078      	str	r0, [r7, #4]
+ 8006b94:	6039      	str	r1, [r7, #0]
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+ 8006b96:	f7ff fa11 	bl	8005fbc <vTaskSuspendAll>
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+ 8006b9a:	2308      	movs	r3, #8
+ 8006b9c:	18fb      	adds	r3, r7, r3
+ 8006b9e:	0018      	movs	r0, r3
+ 8006ba0:	f000 f85e 	bl	8006c60 <prvSampleTimeNow>
+ 8006ba4:	0003      	movs	r3, r0
+ 8006ba6:	60fb      	str	r3, [r7, #12]
+		if( xTimerListsWereSwitched == pdFALSE )
+ 8006ba8:	68bb      	ldr	r3, [r7, #8]
+ 8006baa:	2b00      	cmp	r3, #0
+ 8006bac:	d12b      	bne.n	8006c06 <prvProcessTimerOrBlockTask+0x7a>
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+ 8006bae:	683b      	ldr	r3, [r7, #0]
+ 8006bb0:	2b00      	cmp	r3, #0
+ 8006bb2:	d10c      	bne.n	8006bce <prvProcessTimerOrBlockTask+0x42>
+ 8006bb4:	687a      	ldr	r2, [r7, #4]
+ 8006bb6:	68fb      	ldr	r3, [r7, #12]
+ 8006bb8:	429a      	cmp	r2, r3
+ 8006bba:	d808      	bhi.n	8006bce <prvProcessTimerOrBlockTask+0x42>
+			{
+				( void ) xTaskResumeAll();
+ 8006bbc:	f7ff fa40 	bl	8006040 <xTaskResumeAll>
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+ 8006bc0:	68fa      	ldr	r2, [r7, #12]
+ 8006bc2:	687b      	ldr	r3, [r7, #4]
+ 8006bc4:	0011      	movs	r1, r2
+ 8006bc6:	0018      	movs	r0, r3
+ 8006bc8:	f7ff ff88 	bl	8006adc <prvProcessExpiredTimer>
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+ 8006bcc:	e01d      	b.n	8006c0a <prvProcessTimerOrBlockTask+0x7e>
+				if( xListWasEmpty != pdFALSE )
+ 8006bce:	683b      	ldr	r3, [r7, #0]
+ 8006bd0:	2b00      	cmp	r3, #0
+ 8006bd2:	d008      	beq.n	8006be6 <prvProcessTimerOrBlockTask+0x5a>
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+ 8006bd4:	4b0f      	ldr	r3, [pc, #60]	; (8006c14 <prvProcessTimerOrBlockTask+0x88>)
+ 8006bd6:	681b      	ldr	r3, [r3, #0]
+ 8006bd8:	681b      	ldr	r3, [r3, #0]
+ 8006bda:	2b00      	cmp	r3, #0
+ 8006bdc:	d101      	bne.n	8006be2 <prvProcessTimerOrBlockTask+0x56>
+ 8006bde:	2301      	movs	r3, #1
+ 8006be0:	e000      	b.n	8006be4 <prvProcessTimerOrBlockTask+0x58>
+ 8006be2:	2300      	movs	r3, #0
+ 8006be4:	603b      	str	r3, [r7, #0]
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+ 8006be6:	4b0c      	ldr	r3, [pc, #48]	; (8006c18 <prvProcessTimerOrBlockTask+0x8c>)
+ 8006be8:	6818      	ldr	r0, [r3, #0]
+ 8006bea:	687a      	ldr	r2, [r7, #4]
+ 8006bec:	68fb      	ldr	r3, [r7, #12]
+ 8006bee:	1ad3      	subs	r3, r2, r3
+ 8006bf0:	683a      	ldr	r2, [r7, #0]
+ 8006bf2:	0019      	movs	r1, r3
+ 8006bf4:	f7fe ff3a 	bl	8005a6c <vQueueWaitForMessageRestricted>
+				if( xTaskResumeAll() == pdFALSE )
+ 8006bf8:	f7ff fa22 	bl	8006040 <xTaskResumeAll>
+ 8006bfc:	1e03      	subs	r3, r0, #0
+ 8006bfe:	d104      	bne.n	8006c0a <prvProcessTimerOrBlockTask+0x7e>
+					portYIELD_WITHIN_API();
+ 8006c00:	f000 fa7e 	bl	8007100 <vPortYield>
+}
+ 8006c04:	e001      	b.n	8006c0a <prvProcessTimerOrBlockTask+0x7e>
+			( void ) xTaskResumeAll();
+ 8006c06:	f7ff fa1b 	bl	8006040 <xTaskResumeAll>
+}
+ 8006c0a:	46c0      	nop			; (mov r8, r8)
+ 8006c0c:	46bd      	mov	sp, r7
+ 8006c0e:	b004      	add	sp, #16
+ 8006c10:	bd80      	pop	{r7, pc}
+ 8006c12:	46c0      	nop			; (mov r8, r8)
+ 8006c14:	20000c18 	.word	0x20000c18
+ 8006c18:	20000c1c 	.word	0x20000c1c
+
+08006c1c <prvGetNextExpireTime>:
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+ 8006c1c:	b580      	push	{r7, lr}
+ 8006c1e:	b084      	sub	sp, #16
+ 8006c20:	af00      	add	r7, sp, #0
+ 8006c22:	6078      	str	r0, [r7, #4]
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+ 8006c24:	4b0d      	ldr	r3, [pc, #52]	; (8006c5c <prvGetNextExpireTime+0x40>)
+ 8006c26:	681b      	ldr	r3, [r3, #0]
+ 8006c28:	681b      	ldr	r3, [r3, #0]
+ 8006c2a:	2b00      	cmp	r3, #0
+ 8006c2c:	d101      	bne.n	8006c32 <prvGetNextExpireTime+0x16>
+ 8006c2e:	2201      	movs	r2, #1
+ 8006c30:	e000      	b.n	8006c34 <prvGetNextExpireTime+0x18>
+ 8006c32:	2200      	movs	r2, #0
+ 8006c34:	687b      	ldr	r3, [r7, #4]
+ 8006c36:	601a      	str	r2, [r3, #0]
+	if( *pxListWasEmpty == pdFALSE )
+ 8006c38:	687b      	ldr	r3, [r7, #4]
+ 8006c3a:	681b      	ldr	r3, [r3, #0]
+ 8006c3c:	2b00      	cmp	r3, #0
+ 8006c3e:	d105      	bne.n	8006c4c <prvGetNextExpireTime+0x30>
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+ 8006c40:	4b06      	ldr	r3, [pc, #24]	; (8006c5c <prvGetNextExpireTime+0x40>)
+ 8006c42:	681b      	ldr	r3, [r3, #0]
+ 8006c44:	68db      	ldr	r3, [r3, #12]
+ 8006c46:	681b      	ldr	r3, [r3, #0]
+ 8006c48:	60fb      	str	r3, [r7, #12]
+ 8006c4a:	e001      	b.n	8006c50 <prvGetNextExpireTime+0x34>
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+ 8006c4c:	2300      	movs	r3, #0
+ 8006c4e:	60fb      	str	r3, [r7, #12]
+	}
+
+	return xNextExpireTime;
+ 8006c50:	68fb      	ldr	r3, [r7, #12]
+}
+ 8006c52:	0018      	movs	r0, r3
+ 8006c54:	46bd      	mov	sp, r7
+ 8006c56:	b004      	add	sp, #16
+ 8006c58:	bd80      	pop	{r7, pc}
+ 8006c5a:	46c0      	nop			; (mov r8, r8)
+ 8006c5c:	20000c14 	.word	0x20000c14
+
+08006c60 <prvSampleTimeNow>:
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+ 8006c60:	b580      	push	{r7, lr}
+ 8006c62:	b084      	sub	sp, #16
+ 8006c64:	af00      	add	r7, sp, #0
+ 8006c66:	6078      	str	r0, [r7, #4]
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+ 8006c68:	f7ff fa76 	bl	8006158 <xTaskGetTickCount>
+ 8006c6c:	0003      	movs	r3, r0
+ 8006c6e:	60fb      	str	r3, [r7, #12]
+
+	if( xTimeNow < xLastTime )
+ 8006c70:	4b0a      	ldr	r3, [pc, #40]	; (8006c9c <prvSampleTimeNow+0x3c>)
+ 8006c72:	681b      	ldr	r3, [r3, #0]
+ 8006c74:	68fa      	ldr	r2, [r7, #12]
+ 8006c76:	429a      	cmp	r2, r3
+ 8006c78:	d205      	bcs.n	8006c86 <prvSampleTimeNow+0x26>
+	{
+		prvSwitchTimerLists();
+ 8006c7a:	f000 f919 	bl	8006eb0 <prvSwitchTimerLists>
+		*pxTimerListsWereSwitched = pdTRUE;
+ 8006c7e:	687b      	ldr	r3, [r7, #4]
+ 8006c80:	2201      	movs	r2, #1
+ 8006c82:	601a      	str	r2, [r3, #0]
+ 8006c84:	e002      	b.n	8006c8c <prvSampleTimeNow+0x2c>
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+ 8006c86:	687b      	ldr	r3, [r7, #4]
+ 8006c88:	2200      	movs	r2, #0
+ 8006c8a:	601a      	str	r2, [r3, #0]
+	}
+
+	xLastTime = xTimeNow;
+ 8006c8c:	4b03      	ldr	r3, [pc, #12]	; (8006c9c <prvSampleTimeNow+0x3c>)
+ 8006c8e:	68fa      	ldr	r2, [r7, #12]
+ 8006c90:	601a      	str	r2, [r3, #0]
+
+	return xTimeNow;
+ 8006c92:	68fb      	ldr	r3, [r7, #12]
+}
+ 8006c94:	0018      	movs	r0, r3
+ 8006c96:	46bd      	mov	sp, r7
+ 8006c98:	b004      	add	sp, #16
+ 8006c9a:	bd80      	pop	{r7, pc}
+ 8006c9c:	20000c24 	.word	0x20000c24
+
+08006ca0 <prvInsertTimerInActiveList>:
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+ 8006ca0:	b580      	push	{r7, lr}
+ 8006ca2:	b086      	sub	sp, #24
+ 8006ca4:	af00      	add	r7, sp, #0
+ 8006ca6:	60f8      	str	r0, [r7, #12]
+ 8006ca8:	60b9      	str	r1, [r7, #8]
+ 8006caa:	607a      	str	r2, [r7, #4]
+ 8006cac:	603b      	str	r3, [r7, #0]
+BaseType_t xProcessTimerNow = pdFALSE;
+ 8006cae:	2300      	movs	r3, #0
+ 8006cb0:	617b      	str	r3, [r7, #20]
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+ 8006cb2:	68fb      	ldr	r3, [r7, #12]
+ 8006cb4:	68ba      	ldr	r2, [r7, #8]
+ 8006cb6:	605a      	str	r2, [r3, #4]
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+ 8006cb8:	68fb      	ldr	r3, [r7, #12]
+ 8006cba:	68fa      	ldr	r2, [r7, #12]
+ 8006cbc:	611a      	str	r2, [r3, #16]
+
+	if( xNextExpiryTime <= xTimeNow )
+ 8006cbe:	68ba      	ldr	r2, [r7, #8]
+ 8006cc0:	687b      	ldr	r3, [r7, #4]
+ 8006cc2:	429a      	cmp	r2, r3
+ 8006cc4:	d812      	bhi.n	8006cec <prvInsertTimerInActiveList+0x4c>
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 8006cc6:	687a      	ldr	r2, [r7, #4]
+ 8006cc8:	683b      	ldr	r3, [r7, #0]
+ 8006cca:	1ad2      	subs	r2, r2, r3
+ 8006ccc:	68fb      	ldr	r3, [r7, #12]
+ 8006cce:	699b      	ldr	r3, [r3, #24]
+ 8006cd0:	429a      	cmp	r2, r3
+ 8006cd2:	d302      	bcc.n	8006cda <prvInsertTimerInActiveList+0x3a>
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+ 8006cd4:	2301      	movs	r3, #1
+ 8006cd6:	617b      	str	r3, [r7, #20]
+ 8006cd8:	e01b      	b.n	8006d12 <prvInsertTimerInActiveList+0x72>
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+ 8006cda:	4b10      	ldr	r3, [pc, #64]	; (8006d1c <prvInsertTimerInActiveList+0x7c>)
+ 8006cdc:	681a      	ldr	r2, [r3, #0]
+ 8006cde:	68fb      	ldr	r3, [r7, #12]
+ 8006ce0:	3304      	adds	r3, #4
+ 8006ce2:	0019      	movs	r1, r3
+ 8006ce4:	0010      	movs	r0, r2
+ 8006ce6:	f7fe fa34 	bl	8005152 <vListInsert>
+ 8006cea:	e012      	b.n	8006d12 <prvInsertTimerInActiveList+0x72>
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+ 8006cec:	687a      	ldr	r2, [r7, #4]
+ 8006cee:	683b      	ldr	r3, [r7, #0]
+ 8006cf0:	429a      	cmp	r2, r3
+ 8006cf2:	d206      	bcs.n	8006d02 <prvInsertTimerInActiveList+0x62>
+ 8006cf4:	68ba      	ldr	r2, [r7, #8]
+ 8006cf6:	683b      	ldr	r3, [r7, #0]
+ 8006cf8:	429a      	cmp	r2, r3
+ 8006cfa:	d302      	bcc.n	8006d02 <prvInsertTimerInActiveList+0x62>
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+ 8006cfc:	2301      	movs	r3, #1
+ 8006cfe:	617b      	str	r3, [r7, #20]
+ 8006d00:	e007      	b.n	8006d12 <prvInsertTimerInActiveList+0x72>
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+ 8006d02:	4b07      	ldr	r3, [pc, #28]	; (8006d20 <prvInsertTimerInActiveList+0x80>)
+ 8006d04:	681a      	ldr	r2, [r3, #0]
+ 8006d06:	68fb      	ldr	r3, [r7, #12]
+ 8006d08:	3304      	adds	r3, #4
+ 8006d0a:	0019      	movs	r1, r3
+ 8006d0c:	0010      	movs	r0, r2
+ 8006d0e:	f7fe fa20 	bl	8005152 <vListInsert>
+		}
+	}
+
+	return xProcessTimerNow;
+ 8006d12:	697b      	ldr	r3, [r7, #20]
+}
+ 8006d14:	0018      	movs	r0, r3
+ 8006d16:	46bd      	mov	sp, r7
+ 8006d18:	b006      	add	sp, #24
+ 8006d1a:	bd80      	pop	{r7, pc}
+ 8006d1c:	20000c18 	.word	0x20000c18
+ 8006d20:	20000c14 	.word	0x20000c14
+
+08006d24 <prvProcessReceivedCommands>:
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+ 8006d24:	b590      	push	{r4, r7, lr}
+ 8006d26:	b08d      	sub	sp, #52	; 0x34
+ 8006d28:	af02      	add	r7, sp, #8
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+ 8006d2a:	e0ac      	b.n	8006e86 <prvProcessReceivedCommands+0x162>
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+ 8006d2c:	2208      	movs	r2, #8
+ 8006d2e:	18bb      	adds	r3, r7, r2
+ 8006d30:	681b      	ldr	r3, [r3, #0]
+ 8006d32:	2b00      	cmp	r3, #0
+ 8006d34:	da0f      	bge.n	8006d56 <prvProcessReceivedCommands+0x32>
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+ 8006d36:	18bb      	adds	r3, r7, r2
+ 8006d38:	3304      	adds	r3, #4
+ 8006d3a:	627b      	str	r3, [r7, #36]	; 0x24
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+ 8006d3c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8006d3e:	2b00      	cmp	r3, #0
+ 8006d40:	d101      	bne.n	8006d46 <prvProcessReceivedCommands+0x22>
+ 8006d42:	b672      	cpsid	i
+ 8006d44:	e7fe      	b.n	8006d44 <prvProcessReceivedCommands+0x20>
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+ 8006d46:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8006d48:	681a      	ldr	r2, [r3, #0]
+ 8006d4a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8006d4c:	6858      	ldr	r0, [r3, #4]
+ 8006d4e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8006d50:	689b      	ldr	r3, [r3, #8]
+ 8006d52:	0019      	movs	r1, r3
+ 8006d54:	4790      	blx	r2
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+ 8006d56:	2208      	movs	r2, #8
+ 8006d58:	18bb      	adds	r3, r7, r2
+ 8006d5a:	681b      	ldr	r3, [r3, #0]
+ 8006d5c:	2b00      	cmp	r3, #0
+ 8006d5e:	da00      	bge.n	8006d62 <prvProcessReceivedCommands+0x3e>
+ 8006d60:	e090      	b.n	8006e84 <prvProcessReceivedCommands+0x160>
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+ 8006d62:	18bb      	adds	r3, r7, r2
+ 8006d64:	689b      	ldr	r3, [r3, #8]
+ 8006d66:	623b      	str	r3, [r7, #32]
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+ 8006d68:	6a3b      	ldr	r3, [r7, #32]
+ 8006d6a:	695b      	ldr	r3, [r3, #20]
+ 8006d6c:	2b00      	cmp	r3, #0
+ 8006d6e:	d004      	beq.n	8006d7a <prvProcessReceivedCommands+0x56>
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ 8006d70:	6a3b      	ldr	r3, [r7, #32]
+ 8006d72:	3304      	adds	r3, #4
+ 8006d74:	0018      	movs	r0, r3
+ 8006d76:	f7fe fa22 	bl	80051be <uxListRemove>
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+ 8006d7a:	1d3b      	adds	r3, r7, #4
+ 8006d7c:	0018      	movs	r0, r3
+ 8006d7e:	f7ff ff6f 	bl	8006c60 <prvSampleTimeNow>
+ 8006d82:	0003      	movs	r3, r0
+ 8006d84:	61fb      	str	r3, [r7, #28]
+
+			switch( xMessage.xMessageID )
+ 8006d86:	2308      	movs	r3, #8
+ 8006d88:	18fb      	adds	r3, r7, r3
+ 8006d8a:	681b      	ldr	r3, [r3, #0]
+ 8006d8c:	2b09      	cmp	r3, #9
+ 8006d8e:	d900      	bls.n	8006d92 <prvProcessReceivedCommands+0x6e>
+ 8006d90:	e079      	b.n	8006e86 <prvProcessReceivedCommands+0x162>
+ 8006d92:	009a      	lsls	r2, r3, #2
+ 8006d94:	4b44      	ldr	r3, [pc, #272]	; (8006ea8 <prvProcessReceivedCommands+0x184>)
+ 8006d96:	18d3      	adds	r3, r2, r3
+ 8006d98:	681b      	ldr	r3, [r3, #0]
+ 8006d9a:	469f      	mov	pc, r3
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+ 8006d9c:	6a3b      	ldr	r3, [r7, #32]
+ 8006d9e:	2228      	movs	r2, #40	; 0x28
+ 8006da0:	5c9b      	ldrb	r3, [r3, r2]
+ 8006da2:	2201      	movs	r2, #1
+ 8006da4:	4313      	orrs	r3, r2
+ 8006da6:	b2d9      	uxtb	r1, r3
+ 8006da8:	6a3b      	ldr	r3, [r7, #32]
+ 8006daa:	2228      	movs	r2, #40	; 0x28
+ 8006dac:	5499      	strb	r1, [r3, r2]
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+ 8006dae:	2408      	movs	r4, #8
+ 8006db0:	193b      	adds	r3, r7, r4
+ 8006db2:	685a      	ldr	r2, [r3, #4]
+ 8006db4:	6a3b      	ldr	r3, [r7, #32]
+ 8006db6:	699b      	ldr	r3, [r3, #24]
+ 8006db8:	18d1      	adds	r1, r2, r3
+ 8006dba:	193b      	adds	r3, r7, r4
+ 8006dbc:	685b      	ldr	r3, [r3, #4]
+ 8006dbe:	69fa      	ldr	r2, [r7, #28]
+ 8006dc0:	6a38      	ldr	r0, [r7, #32]
+ 8006dc2:	f7ff ff6d 	bl	8006ca0 <prvInsertTimerInActiveList>
+ 8006dc6:	1e03      	subs	r3, r0, #0
+ 8006dc8:	d05d      	beq.n	8006e86 <prvProcessReceivedCommands+0x162>
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ 8006dca:	6a3b      	ldr	r3, [r7, #32]
+ 8006dcc:	6a1b      	ldr	r3, [r3, #32]
+ 8006dce:	6a3a      	ldr	r2, [r7, #32]
+ 8006dd0:	0010      	movs	r0, r2
+ 8006dd2:	4798      	blx	r3
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ 8006dd4:	6a3b      	ldr	r3, [r7, #32]
+ 8006dd6:	2228      	movs	r2, #40	; 0x28
+ 8006dd8:	5c9b      	ldrb	r3, [r3, r2]
+ 8006dda:	001a      	movs	r2, r3
+ 8006ddc:	2304      	movs	r3, #4
+ 8006dde:	4013      	ands	r3, r2
+ 8006de0:	d051      	beq.n	8006e86 <prvProcessReceivedCommands+0x162>
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+ 8006de2:	193b      	adds	r3, r7, r4
+ 8006de4:	685a      	ldr	r2, [r3, #4]
+ 8006de6:	6a3b      	ldr	r3, [r7, #32]
+ 8006de8:	699b      	ldr	r3, [r3, #24]
+ 8006dea:	18d2      	adds	r2, r2, r3
+ 8006dec:	6a38      	ldr	r0, [r7, #32]
+ 8006dee:	2300      	movs	r3, #0
+ 8006df0:	9300      	str	r3, [sp, #0]
+ 8006df2:	2300      	movs	r3, #0
+ 8006df4:	2100      	movs	r1, #0
+ 8006df6:	f7ff fe27 	bl	8006a48 <xTimerGenericCommand>
+ 8006dfa:	0003      	movs	r3, r0
+ 8006dfc:	61bb      	str	r3, [r7, #24]
+							configASSERT( xResult );
+ 8006dfe:	69bb      	ldr	r3, [r7, #24]
+ 8006e00:	2b00      	cmp	r3, #0
+ 8006e02:	d140      	bne.n	8006e86 <prvProcessReceivedCommands+0x162>
+ 8006e04:	b672      	cpsid	i
+ 8006e06:	e7fe      	b.n	8006e06 <prvProcessReceivedCommands+0xe2>
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ 8006e08:	6a3b      	ldr	r3, [r7, #32]
+ 8006e0a:	2228      	movs	r2, #40	; 0x28
+ 8006e0c:	5c9b      	ldrb	r3, [r3, r2]
+ 8006e0e:	2201      	movs	r2, #1
+ 8006e10:	4393      	bics	r3, r2
+ 8006e12:	b2d9      	uxtb	r1, r3
+ 8006e14:	6a3b      	ldr	r3, [r7, #32]
+ 8006e16:	2228      	movs	r2, #40	; 0x28
+ 8006e18:	5499      	strb	r1, [r3, r2]
+					break;
+ 8006e1a:	e034      	b.n	8006e86 <prvProcessReceivedCommands+0x162>
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+ 8006e1c:	6a3b      	ldr	r3, [r7, #32]
+ 8006e1e:	2228      	movs	r2, #40	; 0x28
+ 8006e20:	5c9b      	ldrb	r3, [r3, r2]
+ 8006e22:	2201      	movs	r2, #1
+ 8006e24:	4313      	orrs	r3, r2
+ 8006e26:	b2d9      	uxtb	r1, r3
+ 8006e28:	6a3b      	ldr	r3, [r7, #32]
+ 8006e2a:	2228      	movs	r2, #40	; 0x28
+ 8006e2c:	5499      	strb	r1, [r3, r2]
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+ 8006e2e:	2308      	movs	r3, #8
+ 8006e30:	18fb      	adds	r3, r7, r3
+ 8006e32:	685a      	ldr	r2, [r3, #4]
+ 8006e34:	6a3b      	ldr	r3, [r7, #32]
+ 8006e36:	619a      	str	r2, [r3, #24]
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+ 8006e38:	6a3b      	ldr	r3, [r7, #32]
+ 8006e3a:	699b      	ldr	r3, [r3, #24]
+ 8006e3c:	2b00      	cmp	r3, #0
+ 8006e3e:	d101      	bne.n	8006e44 <prvProcessReceivedCommands+0x120>
+ 8006e40:	b672      	cpsid	i
+ 8006e42:	e7fe      	b.n	8006e42 <prvProcessReceivedCommands+0x11e>
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+ 8006e44:	6a3b      	ldr	r3, [r7, #32]
+ 8006e46:	699a      	ldr	r2, [r3, #24]
+ 8006e48:	69fb      	ldr	r3, [r7, #28]
+ 8006e4a:	18d1      	adds	r1, r2, r3
+ 8006e4c:	69fb      	ldr	r3, [r7, #28]
+ 8006e4e:	69fa      	ldr	r2, [r7, #28]
+ 8006e50:	6a38      	ldr	r0, [r7, #32]
+ 8006e52:	f7ff ff25 	bl	8006ca0 <prvInsertTimerInActiveList>
+					break;
+ 8006e56:	e016      	b.n	8006e86 <prvProcessReceivedCommands+0x162>
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+ 8006e58:	6a3b      	ldr	r3, [r7, #32]
+ 8006e5a:	2228      	movs	r2, #40	; 0x28
+ 8006e5c:	5c9b      	ldrb	r3, [r3, r2]
+ 8006e5e:	001a      	movs	r2, r3
+ 8006e60:	2302      	movs	r3, #2
+ 8006e62:	4013      	ands	r3, r2
+ 8006e64:	d104      	bne.n	8006e70 <prvProcessReceivedCommands+0x14c>
+						{
+							vPortFree( pxTimer );
+ 8006e66:	6a3b      	ldr	r3, [r7, #32]
+ 8006e68:	0018      	movs	r0, r3
+ 8006e6a:	f000 fb7b 	bl	8007564 <vPortFree>
+ 8006e6e:	e00a      	b.n	8006e86 <prvProcessReceivedCommands+0x162>
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ 8006e70:	6a3b      	ldr	r3, [r7, #32]
+ 8006e72:	2228      	movs	r2, #40	; 0x28
+ 8006e74:	5c9b      	ldrb	r3, [r3, r2]
+ 8006e76:	2201      	movs	r2, #1
+ 8006e78:	4393      	bics	r3, r2
+ 8006e7a:	b2d9      	uxtb	r1, r3
+ 8006e7c:	6a3b      	ldr	r3, [r7, #32]
+ 8006e7e:	2228      	movs	r2, #40	; 0x28
+ 8006e80:	5499      	strb	r1, [r3, r2]
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+ 8006e82:	e000      	b.n	8006e86 <prvProcessReceivedCommands+0x162>
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+ 8006e84:	46c0      	nop			; (mov r8, r8)
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+ 8006e86:	4b09      	ldr	r3, [pc, #36]	; (8006eac <prvProcessReceivedCommands+0x188>)
+ 8006e88:	681b      	ldr	r3, [r3, #0]
+ 8006e8a:	2208      	movs	r2, #8
+ 8006e8c:	18b9      	adds	r1, r7, r2
+ 8006e8e:	2200      	movs	r2, #0
+ 8006e90:	0018      	movs	r0, r3
+ 8006e92:	f7fe fbf0 	bl	8005676 <xQueueReceive>
+ 8006e96:	1e03      	subs	r3, r0, #0
+ 8006e98:	d000      	beq.n	8006e9c <prvProcessReceivedCommands+0x178>
+ 8006e9a:	e747      	b.n	8006d2c <prvProcessReceivedCommands+0x8>
+	}
+}
+ 8006e9c:	46c0      	nop			; (mov r8, r8)
+ 8006e9e:	46c0      	nop			; (mov r8, r8)
+ 8006ea0:	46bd      	mov	sp, r7
+ 8006ea2:	b00b      	add	sp, #44	; 0x2c
+ 8006ea4:	bd90      	pop	{r4, r7, pc}
+ 8006ea6:	46c0      	nop			; (mov r8, r8)
+ 8006ea8:	080078f0 	.word	0x080078f0
+ 8006eac:	20000c1c 	.word	0x20000c1c
+
+08006eb0 <prvSwitchTimerLists>:
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+ 8006eb0:	b580      	push	{r7, lr}
+ 8006eb2:	b088      	sub	sp, #32
+ 8006eb4:	af02      	add	r7, sp, #8
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+ 8006eb6:	e041      	b.n	8006f3c <prvSwitchTimerLists+0x8c>
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+ 8006eb8:	4b2a      	ldr	r3, [pc, #168]	; (8006f64 <prvSwitchTimerLists+0xb4>)
+ 8006eba:	681b      	ldr	r3, [r3, #0]
+ 8006ebc:	68db      	ldr	r3, [r3, #12]
+ 8006ebe:	681b      	ldr	r3, [r3, #0]
+ 8006ec0:	613b      	str	r3, [r7, #16]
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8006ec2:	4b28      	ldr	r3, [pc, #160]	; (8006f64 <prvSwitchTimerLists+0xb4>)
+ 8006ec4:	681b      	ldr	r3, [r3, #0]
+ 8006ec6:	68db      	ldr	r3, [r3, #12]
+ 8006ec8:	68db      	ldr	r3, [r3, #12]
+ 8006eca:	60fb      	str	r3, [r7, #12]
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ 8006ecc:	68fb      	ldr	r3, [r7, #12]
+ 8006ece:	3304      	adds	r3, #4
+ 8006ed0:	0018      	movs	r0, r3
+ 8006ed2:	f7fe f974 	bl	80051be <uxListRemove>
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ 8006ed6:	68fb      	ldr	r3, [r7, #12]
+ 8006ed8:	6a1b      	ldr	r3, [r3, #32]
+ 8006eda:	68fa      	ldr	r2, [r7, #12]
+ 8006edc:	0010      	movs	r0, r2
+ 8006ede:	4798      	blx	r3
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ 8006ee0:	68fb      	ldr	r3, [r7, #12]
+ 8006ee2:	2228      	movs	r2, #40	; 0x28
+ 8006ee4:	5c9b      	ldrb	r3, [r3, r2]
+ 8006ee6:	001a      	movs	r2, r3
+ 8006ee8:	2304      	movs	r3, #4
+ 8006eea:	4013      	ands	r3, r2
+ 8006eec:	d026      	beq.n	8006f3c <prvSwitchTimerLists+0x8c>
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+ 8006eee:	68fb      	ldr	r3, [r7, #12]
+ 8006ef0:	699b      	ldr	r3, [r3, #24]
+ 8006ef2:	693a      	ldr	r2, [r7, #16]
+ 8006ef4:	18d3      	adds	r3, r2, r3
+ 8006ef6:	60bb      	str	r3, [r7, #8]
+			if( xReloadTime > xNextExpireTime )
+ 8006ef8:	68ba      	ldr	r2, [r7, #8]
+ 8006efa:	693b      	ldr	r3, [r7, #16]
+ 8006efc:	429a      	cmp	r2, r3
+ 8006efe:	d90e      	bls.n	8006f1e <prvSwitchTimerLists+0x6e>
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+ 8006f00:	68fb      	ldr	r3, [r7, #12]
+ 8006f02:	68ba      	ldr	r2, [r7, #8]
+ 8006f04:	605a      	str	r2, [r3, #4]
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+ 8006f06:	68fb      	ldr	r3, [r7, #12]
+ 8006f08:	68fa      	ldr	r2, [r7, #12]
+ 8006f0a:	611a      	str	r2, [r3, #16]
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+ 8006f0c:	4b15      	ldr	r3, [pc, #84]	; (8006f64 <prvSwitchTimerLists+0xb4>)
+ 8006f0e:	681a      	ldr	r2, [r3, #0]
+ 8006f10:	68fb      	ldr	r3, [r7, #12]
+ 8006f12:	3304      	adds	r3, #4
+ 8006f14:	0019      	movs	r1, r3
+ 8006f16:	0010      	movs	r0, r2
+ 8006f18:	f7fe f91b 	bl	8005152 <vListInsert>
+ 8006f1c:	e00e      	b.n	8006f3c <prvSwitchTimerLists+0x8c>
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+ 8006f1e:	693a      	ldr	r2, [r7, #16]
+ 8006f20:	68f8      	ldr	r0, [r7, #12]
+ 8006f22:	2300      	movs	r3, #0
+ 8006f24:	9300      	str	r3, [sp, #0]
+ 8006f26:	2300      	movs	r3, #0
+ 8006f28:	2100      	movs	r1, #0
+ 8006f2a:	f7ff fd8d 	bl	8006a48 <xTimerGenericCommand>
+ 8006f2e:	0003      	movs	r3, r0
+ 8006f30:	607b      	str	r3, [r7, #4]
+				configASSERT( xResult );
+ 8006f32:	687b      	ldr	r3, [r7, #4]
+ 8006f34:	2b00      	cmp	r3, #0
+ 8006f36:	d101      	bne.n	8006f3c <prvSwitchTimerLists+0x8c>
+ 8006f38:	b672      	cpsid	i
+ 8006f3a:	e7fe      	b.n	8006f3a <prvSwitchTimerLists+0x8a>
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+ 8006f3c:	4b09      	ldr	r3, [pc, #36]	; (8006f64 <prvSwitchTimerLists+0xb4>)
+ 8006f3e:	681b      	ldr	r3, [r3, #0]
+ 8006f40:	681b      	ldr	r3, [r3, #0]
+ 8006f42:	2b00      	cmp	r3, #0
+ 8006f44:	d1b8      	bne.n	8006eb8 <prvSwitchTimerLists+0x8>
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+ 8006f46:	4b07      	ldr	r3, [pc, #28]	; (8006f64 <prvSwitchTimerLists+0xb4>)
+ 8006f48:	681b      	ldr	r3, [r3, #0]
+ 8006f4a:	617b      	str	r3, [r7, #20]
+	pxCurrentTimerList = pxOverflowTimerList;
+ 8006f4c:	4b06      	ldr	r3, [pc, #24]	; (8006f68 <prvSwitchTimerLists+0xb8>)
+ 8006f4e:	681a      	ldr	r2, [r3, #0]
+ 8006f50:	4b04      	ldr	r3, [pc, #16]	; (8006f64 <prvSwitchTimerLists+0xb4>)
+ 8006f52:	601a      	str	r2, [r3, #0]
+	pxOverflowTimerList = pxTemp;
+ 8006f54:	4b04      	ldr	r3, [pc, #16]	; (8006f68 <prvSwitchTimerLists+0xb8>)
+ 8006f56:	697a      	ldr	r2, [r7, #20]
+ 8006f58:	601a      	str	r2, [r3, #0]
+}
+ 8006f5a:	46c0      	nop			; (mov r8, r8)
+ 8006f5c:	46bd      	mov	sp, r7
+ 8006f5e:	b006      	add	sp, #24
+ 8006f60:	bd80      	pop	{r7, pc}
+ 8006f62:	46c0      	nop			; (mov r8, r8)
+ 8006f64:	20000c14 	.word	0x20000c14
+ 8006f68:	20000c18 	.word	0x20000c18
+
+08006f6c <prvCheckForValidListAndQueue>:
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+ 8006f6c:	b580      	push	{r7, lr}
+ 8006f6e:	b082      	sub	sp, #8
+ 8006f70:	af02      	add	r7, sp, #8
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+ 8006f72:	f000 f8d5 	bl	8007120 <vPortEnterCritical>
+	{
+		if( xTimerQueue == NULL )
+ 8006f76:	4b16      	ldr	r3, [pc, #88]	; (8006fd0 <prvCheckForValidListAndQueue+0x64>)
+ 8006f78:	681b      	ldr	r3, [r3, #0]
+ 8006f7a:	2b00      	cmp	r3, #0
+ 8006f7c:	d123      	bne.n	8006fc6 <prvCheckForValidListAndQueue+0x5a>
+		{
+			vListInitialise( &xActiveTimerList1 );
+ 8006f7e:	4b15      	ldr	r3, [pc, #84]	; (8006fd4 <prvCheckForValidListAndQueue+0x68>)
+ 8006f80:	0018      	movs	r0, r3
+ 8006f82:	f7fe f89b 	bl	80050bc <vListInitialise>
+			vListInitialise( &xActiveTimerList2 );
+ 8006f86:	4b14      	ldr	r3, [pc, #80]	; (8006fd8 <prvCheckForValidListAndQueue+0x6c>)
+ 8006f88:	0018      	movs	r0, r3
+ 8006f8a:	f7fe f897 	bl	80050bc <vListInitialise>
+			pxCurrentTimerList = &xActiveTimerList1;
+ 8006f8e:	4b13      	ldr	r3, [pc, #76]	; (8006fdc <prvCheckForValidListAndQueue+0x70>)
+ 8006f90:	4a10      	ldr	r2, [pc, #64]	; (8006fd4 <prvCheckForValidListAndQueue+0x68>)
+ 8006f92:	601a      	str	r2, [r3, #0]
+			pxOverflowTimerList = &xActiveTimerList2;
+ 8006f94:	4b12      	ldr	r3, [pc, #72]	; (8006fe0 <prvCheckForValidListAndQueue+0x74>)
+ 8006f96:	4a10      	ldr	r2, [pc, #64]	; (8006fd8 <prvCheckForValidListAndQueue+0x6c>)
+ 8006f98:	601a      	str	r2, [r3, #0]
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+ 8006f9a:	4b12      	ldr	r3, [pc, #72]	; (8006fe4 <prvCheckForValidListAndQueue+0x78>)
+ 8006f9c:	4a12      	ldr	r2, [pc, #72]	; (8006fe8 <prvCheckForValidListAndQueue+0x7c>)
+ 8006f9e:	2100      	movs	r1, #0
+ 8006fa0:	9100      	str	r1, [sp, #0]
+ 8006fa2:	2110      	movs	r1, #16
+ 8006fa4:	200a      	movs	r0, #10
+ 8006fa6:	f7fe f986 	bl	80052b6 <xQueueGenericCreateStatic>
+ 8006faa:	0002      	movs	r2, r0
+ 8006fac:	4b08      	ldr	r3, [pc, #32]	; (8006fd0 <prvCheckForValidListAndQueue+0x64>)
+ 8006fae:	601a      	str	r2, [r3, #0]
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+ 8006fb0:	4b07      	ldr	r3, [pc, #28]	; (8006fd0 <prvCheckForValidListAndQueue+0x64>)
+ 8006fb2:	681b      	ldr	r3, [r3, #0]
+ 8006fb4:	2b00      	cmp	r3, #0
+ 8006fb6:	d006      	beq.n	8006fc6 <prvCheckForValidListAndQueue+0x5a>
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+ 8006fb8:	4b05      	ldr	r3, [pc, #20]	; (8006fd0 <prvCheckForValidListAndQueue+0x64>)
+ 8006fba:	681b      	ldr	r3, [r3, #0]
+ 8006fbc:	4a0b      	ldr	r2, [pc, #44]	; (8006fec <prvCheckForValidListAndQueue+0x80>)
+ 8006fbe:	0011      	movs	r1, r2
+ 8006fc0:	0018      	movs	r0, r3
+ 8006fc2:	f7fe fd2b 	bl	8005a1c <vQueueAddToRegistry>
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+ 8006fc6:	f000 f8bd 	bl	8007144 <vPortExitCritical>
+}
+ 8006fca:	46c0      	nop			; (mov r8, r8)
+ 8006fcc:	46bd      	mov	sp, r7
+ 8006fce:	bd80      	pop	{r7, pc}
+ 8006fd0:	20000c1c 	.word	0x20000c1c
+ 8006fd4:	20000bec 	.word	0x20000bec
+ 8006fd8:	20000c00 	.word	0x20000c00
+ 8006fdc:	20000c14 	.word	0x20000c14
+ 8006fe0:	20000c18 	.word	0x20000c18
+ 8006fe4:	20000cc8 	.word	0x20000cc8
+ 8006fe8:	20000c28 	.word	0x20000c28
+ 8006fec:	08007814 	.word	0x08007814
+
+08006ff0 <pxPortInitialiseStack>:
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ 8006ff0:	b580      	push	{r7, lr}
+ 8006ff2:	b084      	sub	sp, #16
+ 8006ff4:	af00      	add	r7, sp, #0
+ 8006ff6:	60f8      	str	r0, [r7, #12]
+ 8006ff8:	60b9      	str	r1, [r7, #8]
+ 8006ffa:	607a      	str	r2, [r7, #4]
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ 8006ffc:	68fb      	ldr	r3, [r7, #12]
+ 8006ffe:	3b04      	subs	r3, #4
+ 8007000:	60fb      	str	r3, [r7, #12]
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+ 8007002:	68fb      	ldr	r3, [r7, #12]
+ 8007004:	2280      	movs	r2, #128	; 0x80
+ 8007006:	0452      	lsls	r2, r2, #17
+ 8007008:	601a      	str	r2, [r3, #0]
+	pxTopOfStack--;
+ 800700a:	68fb      	ldr	r3, [r7, #12]
+ 800700c:	3b04      	subs	r3, #4
+ 800700e:	60fb      	str	r3, [r7, #12]
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
+ 8007010:	68ba      	ldr	r2, [r7, #8]
+ 8007012:	68fb      	ldr	r3, [r7, #12]
+ 8007014:	601a      	str	r2, [r3, #0]
+	pxTopOfStack--;
+ 8007016:	68fb      	ldr	r3, [r7, #12]
+ 8007018:	3b04      	subs	r3, #4
+ 800701a:	60fb      	str	r3, [r7, #12]
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+ 800701c:	4a08      	ldr	r2, [pc, #32]	; (8007040 <pxPortInitialiseStack+0x50>)
+ 800701e:	68fb      	ldr	r3, [r7, #12]
+ 8007020:	601a      	str	r2, [r3, #0]
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+ 8007022:	68fb      	ldr	r3, [r7, #12]
+ 8007024:	3b14      	subs	r3, #20
+ 8007026:	60fb      	str	r3, [r7, #12]
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+ 8007028:	687a      	ldr	r2, [r7, #4]
+ 800702a:	68fb      	ldr	r3, [r7, #12]
+ 800702c:	601a      	str	r2, [r3, #0]
+	pxTopOfStack -= 8; /* R11..R4. */
+ 800702e:	68fb      	ldr	r3, [r7, #12]
+ 8007030:	3b20      	subs	r3, #32
+ 8007032:	60fb      	str	r3, [r7, #12]
+
+	return pxTopOfStack;
+ 8007034:	68fb      	ldr	r3, [r7, #12]
+}
+ 8007036:	0018      	movs	r0, r3
+ 8007038:	46bd      	mov	sp, r7
+ 800703a:	b004      	add	sp, #16
+ 800703c:	bd80      	pop	{r7, pc}
+ 800703e:	46c0      	nop			; (mov r8, r8)
+ 8007040:	08007045 	.word	0x08007045
+
+08007044 <prvTaskExitError>:
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ 8007044:	b580      	push	{r7, lr}
+ 8007046:	b082      	sub	sp, #8
+ 8007048:	af00      	add	r7, sp, #0
+volatile uint32_t ulDummy = 0UL;
+ 800704a:	2300      	movs	r3, #0
+ 800704c:	607b      	str	r3, [r7, #4]
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+ 800704e:	4b08      	ldr	r3, [pc, #32]	; (8007070 <prvTaskExitError+0x2c>)
+ 8007050:	681b      	ldr	r3, [r3, #0]
+ 8007052:	3301      	adds	r3, #1
+ 8007054:	d001      	beq.n	800705a <prvTaskExitError+0x16>
+ 8007056:	b672      	cpsid	i
+ 8007058:	e7fe      	b.n	8007058 <prvTaskExitError+0x14>
+	portDISABLE_INTERRUPTS();
+ 800705a:	b672      	cpsid	i
+	while( ulDummy == 0 )
+ 800705c:	46c0      	nop			; (mov r8, r8)
+ 800705e:	687b      	ldr	r3, [r7, #4]
+ 8007060:	2b00      	cmp	r3, #0
+ 8007062:	d0fc      	beq.n	800705e <prvTaskExitError+0x1a>
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+ 8007064:	46c0      	nop			; (mov r8, r8)
+ 8007066:	46c0      	nop			; (mov r8, r8)
+ 8007068:	46bd      	mov	sp, r7
+ 800706a:	b002      	add	sp, #8
+ 800706c:	bd80      	pop	{r7, pc}
+ 800706e:	46c0      	nop			; (mov r8, r8)
+ 8007070:	2000000c 	.word	0x2000000c
+
+08007074 <SVC_Handler>:
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ 8007074:	b580      	push	{r7, lr}
+ 8007076:	af00      	add	r7, sp, #0
+	/* This function is no longer used, but retained for backward
+	compatibility. */
+}
+ 8007078:	46c0      	nop			; (mov r8, r8)
+ 800707a:	46bd      	mov	sp, r7
+ 800707c:	bd80      	pop	{r7, pc}
+	...
+
+08007080 <vPortStartFirstTask>:
+void vPortStartFirstTask( void )
+{
+	/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
+	table offset register that can be used to locate the initial stack value.
+	Not all M0 parts have the application vector table at address 0. */
+	__asm volatile(
+ 8007080:	4a0b      	ldr	r2, [pc, #44]	; (80070b0 <pxCurrentTCBConst2>)
+ 8007082:	6813      	ldr	r3, [r2, #0]
+ 8007084:	6818      	ldr	r0, [r3, #0]
+ 8007086:	3020      	adds	r0, #32
+ 8007088:	f380 8809 	msr	PSP, r0
+ 800708c:	2002      	movs	r0, #2
+ 800708e:	f380 8814 	msr	CONTROL, r0
+ 8007092:	f3bf 8f6f 	isb	sy
+ 8007096:	bc3f      	pop	{r0, r1, r2, r3, r4, r5}
+ 8007098:	46ae      	mov	lr, r5
+ 800709a:	bc08      	pop	{r3}
+ 800709c:	bc04      	pop	{r2}
+ 800709e:	b662      	cpsie	i
+ 80070a0:	4718      	bx	r3
+ 80070a2:	46c0      	nop			; (mov r8, r8)
+ 80070a4:	46c0      	nop			; (mov r8, r8)
+ 80070a6:	46c0      	nop			; (mov r8, r8)
+ 80070a8:	46c0      	nop			; (mov r8, r8)
+ 80070aa:	46c0      	nop			; (mov r8, r8)
+ 80070ac:	46c0      	nop			; (mov r8, r8)
+ 80070ae:	46c0      	nop			; (mov r8, r8)
+
+080070b0 <pxCurrentTCBConst2>:
+ 80070b0:	200006ec 	.word	0x200006ec
+	"	bx   r3						\n" /* Finally, jump to the user defined task code. */
+	"								\n"
+	"	.align 4					\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB	  "
+				  );
+}
+ 80070b4:	46c0      	nop			; (mov r8, r8)
+ 80070b6:	46c0      	nop			; (mov r8, r8)
+
+080070b8 <xPortStartScheduler>:
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ 80070b8:	b580      	push	{r7, lr}
+ 80070ba:	af00      	add	r7, sp, #0
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
+ 80070bc:	4b0e      	ldr	r3, [pc, #56]	; (80070f8 <xPortStartScheduler+0x40>)
+ 80070be:	681a      	ldr	r2, [r3, #0]
+ 80070c0:	4b0d      	ldr	r3, [pc, #52]	; (80070f8 <xPortStartScheduler+0x40>)
+ 80070c2:	21ff      	movs	r1, #255	; 0xff
+ 80070c4:	0409      	lsls	r1, r1, #16
+ 80070c6:	430a      	orrs	r2, r1
+ 80070c8:	601a      	str	r2, [r3, #0]
+	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
+ 80070ca:	4b0b      	ldr	r3, [pc, #44]	; (80070f8 <xPortStartScheduler+0x40>)
+ 80070cc:	681a      	ldr	r2, [r3, #0]
+ 80070ce:	4b0a      	ldr	r3, [pc, #40]	; (80070f8 <xPortStartScheduler+0x40>)
+ 80070d0:	21ff      	movs	r1, #255	; 0xff
+ 80070d2:	0609      	lsls	r1, r1, #24
+ 80070d4:	430a      	orrs	r2, r1
+ 80070d6:	601a      	str	r2, [r3, #0]
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+ 80070d8:	f000 f95e 	bl	8007398 <prvSetupTimerInterrupt>
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+ 80070dc:	4b07      	ldr	r3, [pc, #28]	; (80070fc <xPortStartScheduler+0x44>)
+ 80070de:	2200      	movs	r2, #0
+ 80070e0:	601a      	str	r2, [r3, #0]
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+ 80070e2:	f7ff ffcd 	bl	8007080 <vPortStartFirstTask>
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+ 80070e6:	f7ff f911 	bl	800630c <vTaskSwitchContext>
+	prvTaskExitError();
+ 80070ea:	f7ff ffab 	bl	8007044 <prvTaskExitError>
+
+	/* Should not get here! */
+	return 0;
+ 80070ee:	2300      	movs	r3, #0
+}
+ 80070f0:	0018      	movs	r0, r3
+ 80070f2:	46bd      	mov	sp, r7
+ 80070f4:	bd80      	pop	{r7, pc}
+ 80070f6:	46c0      	nop			; (mov r8, r8)
+ 80070f8:	e000ed20 	.word	0xe000ed20
+ 80070fc:	2000000c 	.word	0x2000000c
+
+08007100 <vPortYield>:
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+ 8007100:	b580      	push	{r7, lr}
+ 8007102:	af00      	add	r7, sp, #0
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ 8007104:	4b05      	ldr	r3, [pc, #20]	; (800711c <vPortYield+0x1c>)
+ 8007106:	2280      	movs	r2, #128	; 0x80
+ 8007108:	0552      	lsls	r2, r2, #21
+ 800710a:	601a      	str	r2, [r3, #0]
+
+	/* Barriers are normally not required but do ensure the code is completely
+	within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+ 800710c:	f3bf 8f4f 	dsb	sy
+	__asm volatile( "isb" );
+ 8007110:	f3bf 8f6f 	isb	sy
+}
+ 8007114:	46c0      	nop			; (mov r8, r8)
+ 8007116:	46bd      	mov	sp, r7
+ 8007118:	bd80      	pop	{r7, pc}
+ 800711a:	46c0      	nop			; (mov r8, r8)
+ 800711c:	e000ed04 	.word	0xe000ed04
+
+08007120 <vPortEnterCritical>:
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ 8007120:	b580      	push	{r7, lr}
+ 8007122:	af00      	add	r7, sp, #0
+    portDISABLE_INTERRUPTS();
+ 8007124:	b672      	cpsid	i
+    uxCriticalNesting++;
+ 8007126:	4b06      	ldr	r3, [pc, #24]	; (8007140 <vPortEnterCritical+0x20>)
+ 8007128:	681b      	ldr	r3, [r3, #0]
+ 800712a:	1c5a      	adds	r2, r3, #1
+ 800712c:	4b04      	ldr	r3, [pc, #16]	; (8007140 <vPortEnterCritical+0x20>)
+ 800712e:	601a      	str	r2, [r3, #0]
+	__asm volatile( "dsb" ::: "memory" );
+ 8007130:	f3bf 8f4f 	dsb	sy
+	__asm volatile( "isb" );
+ 8007134:	f3bf 8f6f 	isb	sy
+}
+ 8007138:	46c0      	nop			; (mov r8, r8)
+ 800713a:	46bd      	mov	sp, r7
+ 800713c:	bd80      	pop	{r7, pc}
+ 800713e:	46c0      	nop			; (mov r8, r8)
+ 8007140:	2000000c 	.word	0x2000000c
+
+08007144 <vPortExitCritical>:
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ 8007144:	b580      	push	{r7, lr}
+ 8007146:	af00      	add	r7, sp, #0
+	configASSERT( uxCriticalNesting );
+ 8007148:	4b09      	ldr	r3, [pc, #36]	; (8007170 <vPortExitCritical+0x2c>)
+ 800714a:	681b      	ldr	r3, [r3, #0]
+ 800714c:	2b00      	cmp	r3, #0
+ 800714e:	d101      	bne.n	8007154 <vPortExitCritical+0x10>
+ 8007150:	b672      	cpsid	i
+ 8007152:	e7fe      	b.n	8007152 <vPortExitCritical+0xe>
+    uxCriticalNesting--;
+ 8007154:	4b06      	ldr	r3, [pc, #24]	; (8007170 <vPortExitCritical+0x2c>)
+ 8007156:	681b      	ldr	r3, [r3, #0]
+ 8007158:	1e5a      	subs	r2, r3, #1
+ 800715a:	4b05      	ldr	r3, [pc, #20]	; (8007170 <vPortExitCritical+0x2c>)
+ 800715c:	601a      	str	r2, [r3, #0]
+    if( uxCriticalNesting == 0 )
+ 800715e:	4b04      	ldr	r3, [pc, #16]	; (8007170 <vPortExitCritical+0x2c>)
+ 8007160:	681b      	ldr	r3, [r3, #0]
+ 8007162:	2b00      	cmp	r3, #0
+ 8007164:	d100      	bne.n	8007168 <vPortExitCritical+0x24>
+    {
+        portENABLE_INTERRUPTS();
+ 8007166:	b662      	cpsie	i
+    }
+}
+ 8007168:	46c0      	nop			; (mov r8, r8)
+ 800716a:	46bd      	mov	sp, r7
+ 800716c:	bd80      	pop	{r7, pc}
+ 800716e:	46c0      	nop			; (mov r8, r8)
+ 8007170:	2000000c 	.word	0x2000000c
+
+08007174 <ulSetInterruptMaskFromISR>:
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void )
+{
+	__asm volatile(
+ 8007174:	f3ef 8010 	mrs	r0, PRIMASK
+ 8007178:	b672      	cpsid	i
+ 800717a:	4770      	bx	lr
+	/* To avoid compiler warnings.  The return statement will nevere be reached,
+	but some compilers warn if it is not included, while others won't compile if
+	it is. */
+	return 0;
+#endif
+}
+ 800717c:	46c0      	nop			; (mov r8, r8)
+ 800717e:	0018      	movs	r0, r3
+
+08007180 <vClearInterruptMaskFromISR>:
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
+{
+	__asm volatile(
+ 8007180:	f380 8810 	msr	PRIMASK, r0
+ 8007184:	4770      	bx	lr
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	the compiler can't see that.  Some compilers generate warnings without the
+	following line, while others generate warnings if the line is included. */
+	( void ) ulMask;
+#endif
+}
+ 8007186:	46c0      	nop			; (mov r8, r8)
+	...
+
+08007190 <PendSV_Handler>:
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+ 8007190:	f3ef 8009 	mrs	r0, PSP
+ 8007194:	4b0e      	ldr	r3, [pc, #56]	; (80071d0 <pxCurrentTCBConst>)
+ 8007196:	681a      	ldr	r2, [r3, #0]
+ 8007198:	3820      	subs	r0, #32
+ 800719a:	6010      	str	r0, [r2, #0]
+ 800719c:	c0f0      	stmia	r0!, {r4, r5, r6, r7}
+ 800719e:	4644      	mov	r4, r8
+ 80071a0:	464d      	mov	r5, r9
+ 80071a2:	4656      	mov	r6, sl
+ 80071a4:	465f      	mov	r7, fp
+ 80071a6:	c0f0      	stmia	r0!, {r4, r5, r6, r7}
+ 80071a8:	b508      	push	{r3, lr}
+ 80071aa:	b672      	cpsid	i
+ 80071ac:	f7ff f8ae 	bl	800630c <vTaskSwitchContext>
+ 80071b0:	b662      	cpsie	i
+ 80071b2:	bc0c      	pop	{r2, r3}
+ 80071b4:	6811      	ldr	r1, [r2, #0]
+ 80071b6:	6808      	ldr	r0, [r1, #0]
+ 80071b8:	3010      	adds	r0, #16
+ 80071ba:	c8f0      	ldmia	r0!, {r4, r5, r6, r7}
+ 80071bc:	46a0      	mov	r8, r4
+ 80071be:	46a9      	mov	r9, r5
+ 80071c0:	46b2      	mov	sl, r6
+ 80071c2:	46bb      	mov	fp, r7
+ 80071c4:	f380 8809 	msr	PSP, r0
+ 80071c8:	3820      	subs	r0, #32
+ 80071ca:	c8f0      	ldmia	r0!, {r4, r5, r6, r7}
+ 80071cc:	4718      	bx	r3
+ 80071ce:	46c0      	nop			; (mov r8, r8)
+
+080071d0 <pxCurrentTCBConst>:
+ 80071d0:	200006ec 	.word	0x200006ec
+	"	bx r3								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	  "
+	);
+}
+ 80071d4:	46c0      	nop			; (mov r8, r8)
+ 80071d6:	46c0      	nop			; (mov r8, r8)
+
+080071d8 <xPortSysTickHandler>:
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ 80071d8:	b580      	push	{r7, lr}
+ 80071da:	b082      	sub	sp, #8
+ 80071dc:	af00      	add	r7, sp, #0
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ 80071de:	f7ff ffc9 	bl	8007174 <ulSetInterruptMaskFromISR>
+ 80071e2:	0003      	movs	r3, r0
+ 80071e4:	607b      	str	r3, [r7, #4]
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+ 80071e6:	f7fe ffe1 	bl	80061ac <xTaskIncrementTick>
+ 80071ea:	1e03      	subs	r3, r0, #0
+ 80071ec:	d003      	beq.n	80071f6 <xPortSysTickHandler+0x1e>
+		{
+			/* Pend a context switch. */
+			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+ 80071ee:	4b06      	ldr	r3, [pc, #24]	; (8007208 <xPortSysTickHandler+0x30>)
+ 80071f0:	2280      	movs	r2, #128	; 0x80
+ 80071f2:	0552      	lsls	r2, r2, #21
+ 80071f4:	601a      	str	r2, [r3, #0]
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+ 80071f6:	687b      	ldr	r3, [r7, #4]
+ 80071f8:	0018      	movs	r0, r3
+ 80071fa:	f7ff ffc1 	bl	8007180 <vClearInterruptMaskFromISR>
+}
+ 80071fe:	46c0      	nop			; (mov r8, r8)
+ 8007200:	46bd      	mov	sp, r7
+ 8007202:	b002      	add	sp, #8
+ 8007204:	bd80      	pop	{r7, pc}
+ 8007206:	46c0      	nop			; (mov r8, r8)
+ 8007208:	e000ed04 	.word	0xe000ed04
+
+0800720c <vPortSuppressTicksAndSleep>:
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+ 800720c:	b580      	push	{r7, lr}
+ 800720e:	b088      	sub	sp, #32
+ 8007210:	af00      	add	r7, sp, #0
+ 8007212:	6078      	str	r0, [r7, #4]
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ 8007214:	687a      	ldr	r2, [r7, #4]
+ 8007216:	4b5a      	ldr	r3, [pc, #360]	; (8007380 <vPortSuppressTicksAndSleep+0x174>)
+ 8007218:	681b      	ldr	r3, [r3, #0]
+ 800721a:	429a      	cmp	r2, r3
+ 800721c:	d902      	bls.n	8007224 <vPortSuppressTicksAndSleep+0x18>
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ 800721e:	4b58      	ldr	r3, [pc, #352]	; (8007380 <vPortSuppressTicksAndSleep+0x174>)
+ 8007220:	681b      	ldr	r3, [r3, #0]
+ 8007222:	607b      	str	r3, [r7, #4]
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL &= ~portNVIC_SYSTICK_ENABLE;
+ 8007224:	4b57      	ldr	r3, [pc, #348]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 8007226:	681a      	ldr	r2, [r3, #0]
+ 8007228:	4b56      	ldr	r3, [pc, #344]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 800722a:	2101      	movs	r1, #1
+ 800722c:	438a      	bics	r2, r1
+ 800722e:	601a      	str	r2, [r3, #0]
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+ 8007230:	4b55      	ldr	r3, [pc, #340]	; (8007388 <vPortSuppressTicksAndSleep+0x17c>)
+ 8007232:	681a      	ldr	r2, [r3, #0]
+ 8007234:	687b      	ldr	r3, [r7, #4]
+ 8007236:	1e59      	subs	r1, r3, #1
+ 8007238:	4b54      	ldr	r3, [pc, #336]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 800723a:	681b      	ldr	r3, [r3, #0]
+ 800723c:	434b      	muls	r3, r1
+ 800723e:	18d3      	adds	r3, r2, r3
+ 8007240:	61fb      	str	r3, [r7, #28]
+		if( ulReloadValue > ulStoppedTimerCompensation )
+ 8007242:	4b53      	ldr	r3, [pc, #332]	; (8007390 <vPortSuppressTicksAndSleep+0x184>)
+ 8007244:	681b      	ldr	r3, [r3, #0]
+ 8007246:	69fa      	ldr	r2, [r7, #28]
+ 8007248:	429a      	cmp	r2, r3
+ 800724a:	d904      	bls.n	8007256 <vPortSuppressTicksAndSleep+0x4a>
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+ 800724c:	4b50      	ldr	r3, [pc, #320]	; (8007390 <vPortSuppressTicksAndSleep+0x184>)
+ 800724e:	681b      	ldr	r3, [r3, #0]
+ 8007250:	69fa      	ldr	r2, [r7, #28]
+ 8007252:	1ad3      	subs	r3, r2, r3
+ 8007254:	61fb      	str	r3, [r7, #28]
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" );
+ 8007256:	b672      	cpsid	i
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ 8007258:	f7ff f9fc 	bl	8006654 <eTaskConfirmSleepModeStatus>
+ 800725c:	1e03      	subs	r3, r0, #0
+ 800725e:	d110      	bne.n	8007282 <vPortSuppressTicksAndSleep+0x76>
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD = portNVIC_SYSTICK_CURRENT_VALUE;
+ 8007260:	4a49      	ldr	r2, [pc, #292]	; (8007388 <vPortSuppressTicksAndSleep+0x17c>)
+ 8007262:	4b4c      	ldr	r3, [pc, #304]	; (8007394 <vPortSuppressTicksAndSleep+0x188>)
+ 8007264:	6812      	ldr	r2, [r2, #0]
+ 8007266:	601a      	str	r2, [r3, #0]
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL |= portNVIC_SYSTICK_ENABLE;
+ 8007268:	4b46      	ldr	r3, [pc, #280]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 800726a:	681a      	ldr	r2, [r3, #0]
+ 800726c:	4b45      	ldr	r3, [pc, #276]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 800726e:	2101      	movs	r1, #1
+ 8007270:	430a      	orrs	r2, r1
+ 8007272:	601a      	str	r2, [r3, #0]
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD = ulTimerCountsForOneTick - 1UL;
+ 8007274:	4b45      	ldr	r3, [pc, #276]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 8007276:	681a      	ldr	r2, [r3, #0]
+ 8007278:	4b46      	ldr	r3, [pc, #280]	; (8007394 <vPortSuppressTicksAndSleep+0x188>)
+ 800727a:	3a01      	subs	r2, #1
+ 800727c:	601a      	str	r2, [r3, #0]
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" );
+ 800727e:	b662      	cpsie	i
+				vTaskStepTick( ulCompleteTickPeriods );
+				portNVIC_SYSTICK_LOAD = ulTimerCountsForOneTick - 1UL;
+			}
+			portEXIT_CRITICAL();
+		}
+	}
+ 8007280:	e07a      	b.n	8007378 <vPortSuppressTicksAndSleep+0x16c>
+			portNVIC_SYSTICK_LOAD = ulReloadValue;
+ 8007282:	4b44      	ldr	r3, [pc, #272]	; (8007394 <vPortSuppressTicksAndSleep+0x188>)
+ 8007284:	69fa      	ldr	r2, [r7, #28]
+ 8007286:	601a      	str	r2, [r3, #0]
+			portNVIC_SYSTICK_CURRENT_VALUE = 0UL;
+ 8007288:	4b3f      	ldr	r3, [pc, #252]	; (8007388 <vPortSuppressTicksAndSleep+0x17c>)
+ 800728a:	2200      	movs	r2, #0
+ 800728c:	601a      	str	r2, [r3, #0]
+			portNVIC_SYSTICK_CTRL |= portNVIC_SYSTICK_ENABLE;
+ 800728e:	4b3d      	ldr	r3, [pc, #244]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 8007290:	681a      	ldr	r2, [r3, #0]
+ 8007292:	4b3c      	ldr	r3, [pc, #240]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 8007294:	2101      	movs	r1, #1
+ 8007296:	430a      	orrs	r2, r1
+ 8007298:	601a      	str	r2, [r3, #0]
+			xModifiableIdleTime = xExpectedIdleTime;
+ 800729a:	687b      	ldr	r3, [r7, #4]
+ 800729c:	60bb      	str	r3, [r7, #8]
+			configPRE_SLEEP_PROCESSING( &xModifiableIdleTime );
+ 800729e:	2308      	movs	r3, #8
+ 80072a0:	18fb      	adds	r3, r7, r3
+ 80072a2:	0018      	movs	r0, r3
+ 80072a4:	f7f9 f8fa 	bl	800049c <PreSleepProcessing>
+			if( xModifiableIdleTime > 0 )
+ 80072a8:	68bb      	ldr	r3, [r7, #8]
+ 80072aa:	2b00      	cmp	r3, #0
+ 80072ac:	d004      	beq.n	80072b8 <vPortSuppressTicksAndSleep+0xac>
+				__asm volatile( "dsb" );
+ 80072ae:	f3bf 8f4f 	dsb	sy
+				__asm volatile( "wfi" );
+ 80072b2:	bf30      	wfi
+				__asm volatile( "isb" );
+ 80072b4:	f3bf 8f6f 	isb	sy
+			configPOST_SLEEP_PROCESSING( &xExpectedIdleTime );
+ 80072b8:	1d3b      	adds	r3, r7, #4
+ 80072ba:	0018      	movs	r0, r3
+ 80072bc:	f7f9 f8f6 	bl	80004ac <PostSleepProcessing>
+			ulSysTickCTRL = portNVIC_SYSTICK_CTRL;
+ 80072c0:	4b30      	ldr	r3, [pc, #192]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 80072c2:	681b      	ldr	r3, [r3, #0]
+ 80072c4:	613b      	str	r3, [r7, #16]
+			portNVIC_SYSTICK_CTRL = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE );
+ 80072c6:	4b2f      	ldr	r3, [pc, #188]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 80072c8:	693a      	ldr	r2, [r7, #16]
+ 80072ca:	2101      	movs	r1, #1
+ 80072cc:	438a      	bics	r2, r1
+ 80072ce:	601a      	str	r2, [r3, #0]
+			__asm volatile( "cpsie i" );
+ 80072d0:	b662      	cpsie	i
+			if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG ) != 0 )
+ 80072d2:	693a      	ldr	r2, [r7, #16]
+ 80072d4:	2380      	movs	r3, #128	; 0x80
+ 80072d6:	025b      	lsls	r3, r3, #9
+ 80072d8:	4013      	ands	r3, r2
+ 80072da:	d01d      	beq.n	8007318 <vPortSuppressTicksAndSleep+0x10c>
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE );
+ 80072dc:	4b2b      	ldr	r3, [pc, #172]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 80072de:	681a      	ldr	r2, [r3, #0]
+ 80072e0:	4b29      	ldr	r3, [pc, #164]	; (8007388 <vPortSuppressTicksAndSleep+0x17c>)
+ 80072e2:	6819      	ldr	r1, [r3, #0]
+ 80072e4:	69fb      	ldr	r3, [r7, #28]
+ 80072e6:	1acb      	subs	r3, r1, r3
+ 80072e8:	18d3      	adds	r3, r2, r3
+ 80072ea:	3b01      	subs	r3, #1
+ 80072ec:	617b      	str	r3, [r7, #20]
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ 80072ee:	4b28      	ldr	r3, [pc, #160]	; (8007390 <vPortSuppressTicksAndSleep+0x184>)
+ 80072f0:	681b      	ldr	r3, [r3, #0]
+ 80072f2:	697a      	ldr	r2, [r7, #20]
+ 80072f4:	429a      	cmp	r2, r3
+ 80072f6:	d304      	bcc.n	8007302 <vPortSuppressTicksAndSleep+0xf6>
+ 80072f8:	4b24      	ldr	r3, [pc, #144]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 80072fa:	681b      	ldr	r3, [r3, #0]
+ 80072fc:	697a      	ldr	r2, [r7, #20]
+ 80072fe:	429a      	cmp	r2, r3
+ 8007300:	d903      	bls.n	800730a <vPortSuppressTicksAndSleep+0xfe>
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ 8007302:	4b22      	ldr	r3, [pc, #136]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 8007304:	681b      	ldr	r3, [r3, #0]
+ 8007306:	3b01      	subs	r3, #1
+ 8007308:	617b      	str	r3, [r7, #20]
+				portNVIC_SYSTICK_LOAD = ulCalculatedLoadValue;
+ 800730a:	4b22      	ldr	r3, [pc, #136]	; (8007394 <vPortSuppressTicksAndSleep+0x188>)
+ 800730c:	697a      	ldr	r2, [r7, #20]
+ 800730e:	601a      	str	r2, [r3, #0]
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ 8007310:	687b      	ldr	r3, [r7, #4]
+ 8007312:	3b01      	subs	r3, #1
+ 8007314:	61bb      	str	r3, [r7, #24]
+ 8007316:	e019      	b.n	800734c <vPortSuppressTicksAndSleep+0x140>
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE;
+ 8007318:	687a      	ldr	r2, [r7, #4]
+ 800731a:	4b1c      	ldr	r3, [pc, #112]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 800731c:	681b      	ldr	r3, [r3, #0]
+ 800731e:	435a      	muls	r2, r3
+ 8007320:	4b19      	ldr	r3, [pc, #100]	; (8007388 <vPortSuppressTicksAndSleep+0x17c>)
+ 8007322:	681b      	ldr	r3, [r3, #0]
+ 8007324:	1ad3      	subs	r3, r2, r3
+ 8007326:	60fb      	str	r3, [r7, #12]
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+ 8007328:	4b18      	ldr	r3, [pc, #96]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 800732a:	681b      	ldr	r3, [r3, #0]
+ 800732c:	0019      	movs	r1, r3
+ 800732e:	68f8      	ldr	r0, [r7, #12]
+ 8007330:	f7f8 feea 	bl	8000108 <__udivsi3>
+ 8007334:	0003      	movs	r3, r0
+ 8007336:	61bb      	str	r3, [r7, #24]
+				portNVIC_SYSTICK_LOAD = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ 8007338:	69bb      	ldr	r3, [r7, #24]
+ 800733a:	1c5a      	adds	r2, r3, #1
+ 800733c:	4b13      	ldr	r3, [pc, #76]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 800733e:	681b      	ldr	r3, [r3, #0]
+ 8007340:	4353      	muls	r3, r2
+ 8007342:	0019      	movs	r1, r3
+ 8007344:	4b13      	ldr	r3, [pc, #76]	; (8007394 <vPortSuppressTicksAndSleep+0x188>)
+ 8007346:	68fa      	ldr	r2, [r7, #12]
+ 8007348:	1a8a      	subs	r2, r1, r2
+ 800734a:	601a      	str	r2, [r3, #0]
+			portNVIC_SYSTICK_CURRENT_VALUE = 0UL;
+ 800734c:	4b0e      	ldr	r3, [pc, #56]	; (8007388 <vPortSuppressTicksAndSleep+0x17c>)
+ 800734e:	2200      	movs	r2, #0
+ 8007350:	601a      	str	r2, [r3, #0]
+			portENTER_CRITICAL();
+ 8007352:	f7ff fee5 	bl	8007120 <vPortEnterCritical>
+				portNVIC_SYSTICK_CTRL |= portNVIC_SYSTICK_ENABLE;
+ 8007356:	4b0b      	ldr	r3, [pc, #44]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 8007358:	681a      	ldr	r2, [r3, #0]
+ 800735a:	4b0a      	ldr	r3, [pc, #40]	; (8007384 <vPortSuppressTicksAndSleep+0x178>)
+ 800735c:	2101      	movs	r1, #1
+ 800735e:	430a      	orrs	r2, r1
+ 8007360:	601a      	str	r2, [r3, #0]
+				vTaskStepTick( ulCompleteTickPeriods );
+ 8007362:	69bb      	ldr	r3, [r7, #24]
+ 8007364:	0018      	movs	r0, r3
+ 8007366:	f7fe ff05 	bl	8006174 <vTaskStepTick>
+				portNVIC_SYSTICK_LOAD = ulTimerCountsForOneTick - 1UL;
+ 800736a:	4b08      	ldr	r3, [pc, #32]	; (800738c <vPortSuppressTicksAndSleep+0x180>)
+ 800736c:	681a      	ldr	r2, [r3, #0]
+ 800736e:	4b09      	ldr	r3, [pc, #36]	; (8007394 <vPortSuppressTicksAndSleep+0x188>)
+ 8007370:	3a01      	subs	r2, #1
+ 8007372:	601a      	str	r2, [r3, #0]
+			portEXIT_CRITICAL();
+ 8007374:	f7ff fee6 	bl	8007144 <vPortExitCritical>
+	}
+ 8007378:	46c0      	nop			; (mov r8, r8)
+ 800737a:	46bd      	mov	sp, r7
+ 800737c:	b008      	add	sp, #32
+ 800737e:	bd80      	pop	{r7, pc}
+ 8007380:	20000d1c 	.word	0x20000d1c
+ 8007384:	e000e010 	.word	0xe000e010
+ 8007388:	e000e018 	.word	0xe000e018
+ 800738c:	20000d18 	.word	0x20000d18
+ 8007390:	20000d20 	.word	0x20000d20
+ 8007394:	e000e014 	.word	0xe000e014
+
+08007398 <prvSetupTimerInterrupt>:
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+ 8007398:	b580      	push	{r7, lr}
+ 800739a:	af00      	add	r7, sp, #0
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if configUSE_TICKLESS_IDLE == 1
+ {
+   ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ 800739c:	4b16      	ldr	r3, [pc, #88]	; (80073f8 <prvSetupTimerInterrupt+0x60>)
+ 800739e:	681b      	ldr	r3, [r3, #0]
+ 80073a0:	2164      	movs	r1, #100	; 0x64
+ 80073a2:	0018      	movs	r0, r3
+ 80073a4:	f7f8 feb0 	bl	8000108 <__udivsi3>
+ 80073a8:	0003      	movs	r3, r0
+ 80073aa:	001a      	movs	r2, r3
+ 80073ac:	4b13      	ldr	r3, [pc, #76]	; (80073fc <prvSetupTimerInterrupt+0x64>)
+ 80073ae:	601a      	str	r2, [r3, #0]
+   xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ 80073b0:	4b12      	ldr	r3, [pc, #72]	; (80073fc <prvSetupTimerInterrupt+0x64>)
+ 80073b2:	681b      	ldr	r3, [r3, #0]
+ 80073b4:	0019      	movs	r1, r3
+ 80073b6:	4812      	ldr	r0, [pc, #72]	; (8007400 <prvSetupTimerInterrupt+0x68>)
+ 80073b8:	f7f8 fea6 	bl	8000108 <__udivsi3>
+ 80073bc:	0003      	movs	r3, r0
+ 80073be:	001a      	movs	r2, r3
+ 80073c0:	4b10      	ldr	r3, [pc, #64]	; (8007404 <prvSetupTimerInterrupt+0x6c>)
+ 80073c2:	601a      	str	r2, [r3, #0]
+   ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ 80073c4:	4b10      	ldr	r3, [pc, #64]	; (8007408 <prvSetupTimerInterrupt+0x70>)
+ 80073c6:	222d      	movs	r2, #45	; 0x2d
+ 80073c8:	601a      	str	r2, [r3, #0]
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+/* Stop and reset the SysTick. */
+	portNVIC_SYSTICK_CTRL = 0UL;
+ 80073ca:	4b10      	ldr	r3, [pc, #64]	; (800740c <prvSetupTimerInterrupt+0x74>)
+ 80073cc:	2200      	movs	r2, #0
+ 80073ce:	601a      	str	r2, [r3, #0]
+	portNVIC_SYSTICK_CURRENT_VALUE = 0UL;
+ 80073d0:	4b0f      	ldr	r3, [pc, #60]	; (8007410 <prvSetupTimerInterrupt+0x78>)
+ 80073d2:	2200      	movs	r2, #0
+ 80073d4:	601a      	str	r2, [r3, #0]
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ 80073d6:	4b08      	ldr	r3, [pc, #32]	; (80073f8 <prvSetupTimerInterrupt+0x60>)
+ 80073d8:	681b      	ldr	r3, [r3, #0]
+ 80073da:	2164      	movs	r1, #100	; 0x64
+ 80073dc:	0018      	movs	r0, r3
+ 80073de:	f7f8 fe93 	bl	8000108 <__udivsi3>
+ 80073e2:	0003      	movs	r3, r0
+ 80073e4:	001a      	movs	r2, r3
+ 80073e6:	4b0b      	ldr	r3, [pc, #44]	; (8007414 <prvSetupTimerInterrupt+0x7c>)
+ 80073e8:	3a01      	subs	r2, #1
+ 80073ea:	601a      	str	r2, [r3, #0]
+ portNVIC_SYSTICK_CTRL = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+ 80073ec:	4b07      	ldr	r3, [pc, #28]	; (800740c <prvSetupTimerInterrupt+0x74>)
+ 80073ee:	2207      	movs	r2, #7
+ 80073f0:	601a      	str	r2, [r3, #0]
+}
+ 80073f2:	46c0      	nop			; (mov r8, r8)
+ 80073f4:	46bd      	mov	sp, r7
+ 80073f6:	bd80      	pop	{r7, pc}
+ 80073f8:	20000000 	.word	0x20000000
+ 80073fc:	20000d18 	.word	0x20000d18
+ 8007400:	00ffffff 	.word	0x00ffffff
+ 8007404:	20000d1c 	.word	0x20000d1c
+ 8007408:	20000d20 	.word	0x20000d20
+ 800740c:	e000e010 	.word	0xe000e010
+ 8007410:	e000e018 	.word	0xe000e018
+ 8007414:	e000e014 	.word	0xe000e014
+
+08007418 <pvPortMalloc>:
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+ 8007418:	b580      	push	{r7, lr}
+ 800741a:	b086      	sub	sp, #24
+ 800741c:	af00      	add	r7, sp, #0
+ 800741e:	6078      	str	r0, [r7, #4]
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+ 8007420:	2300      	movs	r3, #0
+ 8007422:	60fb      	str	r3, [r7, #12]
+
+	vTaskSuspendAll();
+ 8007424:	f7fe fdca 	bl	8005fbc <vTaskSuspendAll>
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+ 8007428:	4b49      	ldr	r3, [pc, #292]	; (8007550 <pvPortMalloc+0x138>)
+ 800742a:	681b      	ldr	r3, [r3, #0]
+ 800742c:	2b00      	cmp	r3, #0
+ 800742e:	d101      	bne.n	8007434 <pvPortMalloc+0x1c>
+		{
+			prvHeapInit();
+ 8007430:	f000 f8e0 	bl	80075f4 <prvHeapInit>
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ 8007434:	4b47      	ldr	r3, [pc, #284]	; (8007554 <pvPortMalloc+0x13c>)
+ 8007436:	681b      	ldr	r3, [r3, #0]
+ 8007438:	687a      	ldr	r2, [r7, #4]
+ 800743a:	4013      	ands	r3, r2
+ 800743c:	d000      	beq.n	8007440 <pvPortMalloc+0x28>
+ 800743e:	e079      	b.n	8007534 <pvPortMalloc+0x11c>
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+ 8007440:	687b      	ldr	r3, [r7, #4]
+ 8007442:	2b00      	cmp	r3, #0
+ 8007444:	d012      	beq.n	800746c <pvPortMalloc+0x54>
+			{
+				xWantedSize += xHeapStructSize;
+ 8007446:	2208      	movs	r2, #8
+ 8007448:	687b      	ldr	r3, [r7, #4]
+ 800744a:	189b      	adds	r3, r3, r2
+ 800744c:	607b      	str	r3, [r7, #4]
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+ 800744e:	687b      	ldr	r3, [r7, #4]
+ 8007450:	2207      	movs	r2, #7
+ 8007452:	4013      	ands	r3, r2
+ 8007454:	d00a      	beq.n	800746c <pvPortMalloc+0x54>
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+ 8007456:	687b      	ldr	r3, [r7, #4]
+ 8007458:	2207      	movs	r2, #7
+ 800745a:	4393      	bics	r3, r2
+ 800745c:	3308      	adds	r3, #8
+ 800745e:	607b      	str	r3, [r7, #4]
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+ 8007460:	687b      	ldr	r3, [r7, #4]
+ 8007462:	2207      	movs	r2, #7
+ 8007464:	4013      	ands	r3, r2
+ 8007466:	d001      	beq.n	800746c <pvPortMalloc+0x54>
+ 8007468:	b672      	cpsid	i
+ 800746a:	e7fe      	b.n	800746a <pvPortMalloc+0x52>
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ 800746c:	687b      	ldr	r3, [r7, #4]
+ 800746e:	2b00      	cmp	r3, #0
+ 8007470:	d060      	beq.n	8007534 <pvPortMalloc+0x11c>
+ 8007472:	4b39      	ldr	r3, [pc, #228]	; (8007558 <pvPortMalloc+0x140>)
+ 8007474:	681b      	ldr	r3, [r3, #0]
+ 8007476:	687a      	ldr	r2, [r7, #4]
+ 8007478:	429a      	cmp	r2, r3
+ 800747a:	d85b      	bhi.n	8007534 <pvPortMalloc+0x11c>
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+ 800747c:	4b37      	ldr	r3, [pc, #220]	; (800755c <pvPortMalloc+0x144>)
+ 800747e:	613b      	str	r3, [r7, #16]
+				pxBlock = xStart.pxNextFreeBlock;
+ 8007480:	4b36      	ldr	r3, [pc, #216]	; (800755c <pvPortMalloc+0x144>)
+ 8007482:	681b      	ldr	r3, [r3, #0]
+ 8007484:	617b      	str	r3, [r7, #20]
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ 8007486:	e004      	b.n	8007492 <pvPortMalloc+0x7a>
+				{
+					pxPreviousBlock = pxBlock;
+ 8007488:	697b      	ldr	r3, [r7, #20]
+ 800748a:	613b      	str	r3, [r7, #16]
+					pxBlock = pxBlock->pxNextFreeBlock;
+ 800748c:	697b      	ldr	r3, [r7, #20]
+ 800748e:	681b      	ldr	r3, [r3, #0]
+ 8007490:	617b      	str	r3, [r7, #20]
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ 8007492:	697b      	ldr	r3, [r7, #20]
+ 8007494:	685b      	ldr	r3, [r3, #4]
+ 8007496:	687a      	ldr	r2, [r7, #4]
+ 8007498:	429a      	cmp	r2, r3
+ 800749a:	d903      	bls.n	80074a4 <pvPortMalloc+0x8c>
+ 800749c:	697b      	ldr	r3, [r7, #20]
+ 800749e:	681b      	ldr	r3, [r3, #0]
+ 80074a0:	2b00      	cmp	r3, #0
+ 80074a2:	d1f1      	bne.n	8007488 <pvPortMalloc+0x70>
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+ 80074a4:	4b2a      	ldr	r3, [pc, #168]	; (8007550 <pvPortMalloc+0x138>)
+ 80074a6:	681b      	ldr	r3, [r3, #0]
+ 80074a8:	697a      	ldr	r2, [r7, #20]
+ 80074aa:	429a      	cmp	r2, r3
+ 80074ac:	d042      	beq.n	8007534 <pvPortMalloc+0x11c>
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+ 80074ae:	693b      	ldr	r3, [r7, #16]
+ 80074b0:	681b      	ldr	r3, [r3, #0]
+ 80074b2:	2208      	movs	r2, #8
+ 80074b4:	189b      	adds	r3, r3, r2
+ 80074b6:	60fb      	str	r3, [r7, #12]
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+ 80074b8:	697b      	ldr	r3, [r7, #20]
+ 80074ba:	681a      	ldr	r2, [r3, #0]
+ 80074bc:	693b      	ldr	r3, [r7, #16]
+ 80074be:	601a      	str	r2, [r3, #0]
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+ 80074c0:	697b      	ldr	r3, [r7, #20]
+ 80074c2:	685a      	ldr	r2, [r3, #4]
+ 80074c4:	687b      	ldr	r3, [r7, #4]
+ 80074c6:	1ad2      	subs	r2, r2, r3
+ 80074c8:	2308      	movs	r3, #8
+ 80074ca:	005b      	lsls	r3, r3, #1
+ 80074cc:	429a      	cmp	r2, r3
+ 80074ce:	d916      	bls.n	80074fe <pvPortMalloc+0xe6>
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ 80074d0:	697a      	ldr	r2, [r7, #20]
+ 80074d2:	687b      	ldr	r3, [r7, #4]
+ 80074d4:	18d3      	adds	r3, r2, r3
+ 80074d6:	60bb      	str	r3, [r7, #8]
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+ 80074d8:	68bb      	ldr	r3, [r7, #8]
+ 80074da:	2207      	movs	r2, #7
+ 80074dc:	4013      	ands	r3, r2
+ 80074de:	d001      	beq.n	80074e4 <pvPortMalloc+0xcc>
+ 80074e0:	b672      	cpsid	i
+ 80074e2:	e7fe      	b.n	80074e2 <pvPortMalloc+0xca>
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ 80074e4:	697b      	ldr	r3, [r7, #20]
+ 80074e6:	685a      	ldr	r2, [r3, #4]
+ 80074e8:	687b      	ldr	r3, [r7, #4]
+ 80074ea:	1ad2      	subs	r2, r2, r3
+ 80074ec:	68bb      	ldr	r3, [r7, #8]
+ 80074ee:	605a      	str	r2, [r3, #4]
+						pxBlock->xBlockSize = xWantedSize;
+ 80074f0:	697b      	ldr	r3, [r7, #20]
+ 80074f2:	687a      	ldr	r2, [r7, #4]
+ 80074f4:	605a      	str	r2, [r3, #4]
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+ 80074f6:	68bb      	ldr	r3, [r7, #8]
+ 80074f8:	0018      	movs	r0, r3
+ 80074fa:	f000 f8db 	bl	80076b4 <prvInsertBlockIntoFreeList>
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+ 80074fe:	4b16      	ldr	r3, [pc, #88]	; (8007558 <pvPortMalloc+0x140>)
+ 8007500:	681a      	ldr	r2, [r3, #0]
+ 8007502:	697b      	ldr	r3, [r7, #20]
+ 8007504:	685b      	ldr	r3, [r3, #4]
+ 8007506:	1ad2      	subs	r2, r2, r3
+ 8007508:	4b13      	ldr	r3, [pc, #76]	; (8007558 <pvPortMalloc+0x140>)
+ 800750a:	601a      	str	r2, [r3, #0]
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ 800750c:	4b12      	ldr	r3, [pc, #72]	; (8007558 <pvPortMalloc+0x140>)
+ 800750e:	681a      	ldr	r2, [r3, #0]
+ 8007510:	4b13      	ldr	r3, [pc, #76]	; (8007560 <pvPortMalloc+0x148>)
+ 8007512:	681b      	ldr	r3, [r3, #0]
+ 8007514:	429a      	cmp	r2, r3
+ 8007516:	d203      	bcs.n	8007520 <pvPortMalloc+0x108>
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ 8007518:	4b0f      	ldr	r3, [pc, #60]	; (8007558 <pvPortMalloc+0x140>)
+ 800751a:	681a      	ldr	r2, [r3, #0]
+ 800751c:	4b10      	ldr	r3, [pc, #64]	; (8007560 <pvPortMalloc+0x148>)
+ 800751e:	601a      	str	r2, [r3, #0]
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+ 8007520:	697b      	ldr	r3, [r7, #20]
+ 8007522:	685a      	ldr	r2, [r3, #4]
+ 8007524:	4b0b      	ldr	r3, [pc, #44]	; (8007554 <pvPortMalloc+0x13c>)
+ 8007526:	681b      	ldr	r3, [r3, #0]
+ 8007528:	431a      	orrs	r2, r3
+ 800752a:	697b      	ldr	r3, [r7, #20]
+ 800752c:	605a      	str	r2, [r3, #4]
+					pxBlock->pxNextFreeBlock = NULL;
+ 800752e:	697b      	ldr	r3, [r7, #20]
+ 8007530:	2200      	movs	r2, #0
+ 8007532:	601a      	str	r2, [r3, #0]
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+ 8007534:	f7fe fd84 	bl	8006040 <xTaskResumeAll>
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+ 8007538:	68fb      	ldr	r3, [r7, #12]
+ 800753a:	2207      	movs	r2, #7
+ 800753c:	4013      	ands	r3, r2
+ 800753e:	d001      	beq.n	8007544 <pvPortMalloc+0x12c>
+ 8007540:	b672      	cpsid	i
+ 8007542:	e7fe      	b.n	8007542 <pvPortMalloc+0x12a>
+	return pvReturn;
+ 8007544:	68fb      	ldr	r3, [r7, #12]
+}
+ 8007546:	0018      	movs	r0, r3
+ 8007548:	46bd      	mov	sp, r7
+ 800754a:	b006      	add	sp, #24
+ 800754c:	bd80      	pop	{r7, pc}
+ 800754e:	46c0      	nop			; (mov r8, r8)
+ 8007550:	2000152c 	.word	0x2000152c
+ 8007554:	20001538 	.word	0x20001538
+ 8007558:	20001530 	.word	0x20001530
+ 800755c:	20001524 	.word	0x20001524
+ 8007560:	20001534 	.word	0x20001534
+
+08007564 <vPortFree>:
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+ 8007564:	b580      	push	{r7, lr}
+ 8007566:	b084      	sub	sp, #16
+ 8007568:	af00      	add	r7, sp, #0
+ 800756a:	6078      	str	r0, [r7, #4]
+uint8_t *puc = ( uint8_t * ) pv;
+ 800756c:	687b      	ldr	r3, [r7, #4]
+ 800756e:	60fb      	str	r3, [r7, #12]
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+ 8007570:	687b      	ldr	r3, [r7, #4]
+ 8007572:	2b00      	cmp	r3, #0
+ 8007574:	d035      	beq.n	80075e2 <vPortFree+0x7e>
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+ 8007576:	2308      	movs	r3, #8
+ 8007578:	425b      	negs	r3, r3
+ 800757a:	68fa      	ldr	r2, [r7, #12]
+ 800757c:	18d3      	adds	r3, r2, r3
+ 800757e:	60fb      	str	r3, [r7, #12]
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+ 8007580:	68fb      	ldr	r3, [r7, #12]
+ 8007582:	60bb      	str	r3, [r7, #8]
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ 8007584:	68bb      	ldr	r3, [r7, #8]
+ 8007586:	685a      	ldr	r2, [r3, #4]
+ 8007588:	4b18      	ldr	r3, [pc, #96]	; (80075ec <vPortFree+0x88>)
+ 800758a:	681b      	ldr	r3, [r3, #0]
+ 800758c:	4013      	ands	r3, r2
+ 800758e:	d101      	bne.n	8007594 <vPortFree+0x30>
+ 8007590:	b672      	cpsid	i
+ 8007592:	e7fe      	b.n	8007592 <vPortFree+0x2e>
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+ 8007594:	68bb      	ldr	r3, [r7, #8]
+ 8007596:	681b      	ldr	r3, [r3, #0]
+ 8007598:	2b00      	cmp	r3, #0
+ 800759a:	d001      	beq.n	80075a0 <vPortFree+0x3c>
+ 800759c:	b672      	cpsid	i
+ 800759e:	e7fe      	b.n	800759e <vPortFree+0x3a>
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ 80075a0:	68bb      	ldr	r3, [r7, #8]
+ 80075a2:	685a      	ldr	r2, [r3, #4]
+ 80075a4:	4b11      	ldr	r3, [pc, #68]	; (80075ec <vPortFree+0x88>)
+ 80075a6:	681b      	ldr	r3, [r3, #0]
+ 80075a8:	4013      	ands	r3, r2
+ 80075aa:	d01a      	beq.n	80075e2 <vPortFree+0x7e>
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+ 80075ac:	68bb      	ldr	r3, [r7, #8]
+ 80075ae:	681b      	ldr	r3, [r3, #0]
+ 80075b0:	2b00      	cmp	r3, #0
+ 80075b2:	d116      	bne.n	80075e2 <vPortFree+0x7e>
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ 80075b4:	68bb      	ldr	r3, [r7, #8]
+ 80075b6:	685a      	ldr	r2, [r3, #4]
+ 80075b8:	4b0c      	ldr	r3, [pc, #48]	; (80075ec <vPortFree+0x88>)
+ 80075ba:	681b      	ldr	r3, [r3, #0]
+ 80075bc:	43db      	mvns	r3, r3
+ 80075be:	401a      	ands	r2, r3
+ 80075c0:	68bb      	ldr	r3, [r7, #8]
+ 80075c2:	605a      	str	r2, [r3, #4]
+
+				vTaskSuspendAll();
+ 80075c4:	f7fe fcfa 	bl	8005fbc <vTaskSuspendAll>
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+ 80075c8:	68bb      	ldr	r3, [r7, #8]
+ 80075ca:	685a      	ldr	r2, [r3, #4]
+ 80075cc:	4b08      	ldr	r3, [pc, #32]	; (80075f0 <vPortFree+0x8c>)
+ 80075ce:	681b      	ldr	r3, [r3, #0]
+ 80075d0:	18d2      	adds	r2, r2, r3
+ 80075d2:	4b07      	ldr	r3, [pc, #28]	; (80075f0 <vPortFree+0x8c>)
+ 80075d4:	601a      	str	r2, [r3, #0]
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ 80075d6:	68bb      	ldr	r3, [r7, #8]
+ 80075d8:	0018      	movs	r0, r3
+ 80075da:	f000 f86b 	bl	80076b4 <prvInsertBlockIntoFreeList>
+				}
+				( void ) xTaskResumeAll();
+ 80075de:	f7fe fd2f 	bl	8006040 <xTaskResumeAll>
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+ 80075e2:	46c0      	nop			; (mov r8, r8)
+ 80075e4:	46bd      	mov	sp, r7
+ 80075e6:	b004      	add	sp, #16
+ 80075e8:	bd80      	pop	{r7, pc}
+ 80075ea:	46c0      	nop			; (mov r8, r8)
+ 80075ec:	20001538 	.word	0x20001538
+ 80075f0:	20001530 	.word	0x20001530
+
+080075f4 <prvHeapInit>:
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+ 80075f4:	b580      	push	{r7, lr}
+ 80075f6:	b084      	sub	sp, #16
+ 80075f8:	af00      	add	r7, sp, #0
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+ 80075fa:	2380      	movs	r3, #128	; 0x80
+ 80075fc:	011b      	lsls	r3, r3, #4
+ 80075fe:	60bb      	str	r3, [r7, #8]
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+ 8007600:	4b26      	ldr	r3, [pc, #152]	; (800769c <prvHeapInit+0xa8>)
+ 8007602:	60fb      	str	r3, [r7, #12]
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+ 8007604:	68fb      	ldr	r3, [r7, #12]
+ 8007606:	2207      	movs	r2, #7
+ 8007608:	4013      	ands	r3, r2
+ 800760a:	d00c      	beq.n	8007626 <prvHeapInit+0x32>
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+ 800760c:	68fb      	ldr	r3, [r7, #12]
+ 800760e:	3307      	adds	r3, #7
+ 8007610:	60fb      	str	r3, [r7, #12]
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+ 8007612:	68fb      	ldr	r3, [r7, #12]
+ 8007614:	2207      	movs	r2, #7
+ 8007616:	4393      	bics	r3, r2
+ 8007618:	60fb      	str	r3, [r7, #12]
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ 800761a:	68ba      	ldr	r2, [r7, #8]
+ 800761c:	68fb      	ldr	r3, [r7, #12]
+ 800761e:	1ad2      	subs	r2, r2, r3
+ 8007620:	4b1e      	ldr	r3, [pc, #120]	; (800769c <prvHeapInit+0xa8>)
+ 8007622:	18d3      	adds	r3, r2, r3
+ 8007624:	60bb      	str	r3, [r7, #8]
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+ 8007626:	68fb      	ldr	r3, [r7, #12]
+ 8007628:	607b      	str	r3, [r7, #4]
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ 800762a:	4b1d      	ldr	r3, [pc, #116]	; (80076a0 <prvHeapInit+0xac>)
+ 800762c:	687a      	ldr	r2, [r7, #4]
+ 800762e:	601a      	str	r2, [r3, #0]
+	xStart.xBlockSize = ( size_t ) 0;
+ 8007630:	4b1b      	ldr	r3, [pc, #108]	; (80076a0 <prvHeapInit+0xac>)
+ 8007632:	2200      	movs	r2, #0
+ 8007634:	605a      	str	r2, [r3, #4]
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ 8007636:	687b      	ldr	r3, [r7, #4]
+ 8007638:	68ba      	ldr	r2, [r7, #8]
+ 800763a:	18d3      	adds	r3, r2, r3
+ 800763c:	60fb      	str	r3, [r7, #12]
+	uxAddress -= xHeapStructSize;
+ 800763e:	2208      	movs	r2, #8
+ 8007640:	68fb      	ldr	r3, [r7, #12]
+ 8007642:	1a9b      	subs	r3, r3, r2
+ 8007644:	60fb      	str	r3, [r7, #12]
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+ 8007646:	68fb      	ldr	r3, [r7, #12]
+ 8007648:	2207      	movs	r2, #7
+ 800764a:	4393      	bics	r3, r2
+ 800764c:	60fb      	str	r3, [r7, #12]
+	pxEnd = ( void * ) uxAddress;
+ 800764e:	68fa      	ldr	r2, [r7, #12]
+ 8007650:	4b14      	ldr	r3, [pc, #80]	; (80076a4 <prvHeapInit+0xb0>)
+ 8007652:	601a      	str	r2, [r3, #0]
+	pxEnd->xBlockSize = 0;
+ 8007654:	4b13      	ldr	r3, [pc, #76]	; (80076a4 <prvHeapInit+0xb0>)
+ 8007656:	681b      	ldr	r3, [r3, #0]
+ 8007658:	2200      	movs	r2, #0
+ 800765a:	605a      	str	r2, [r3, #4]
+	pxEnd->pxNextFreeBlock = NULL;
+ 800765c:	4b11      	ldr	r3, [pc, #68]	; (80076a4 <prvHeapInit+0xb0>)
+ 800765e:	681b      	ldr	r3, [r3, #0]
+ 8007660:	2200      	movs	r2, #0
+ 8007662:	601a      	str	r2, [r3, #0]
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ 8007664:	687b      	ldr	r3, [r7, #4]
+ 8007666:	603b      	str	r3, [r7, #0]
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ 8007668:	683b      	ldr	r3, [r7, #0]
+ 800766a:	68fa      	ldr	r2, [r7, #12]
+ 800766c:	1ad2      	subs	r2, r2, r3
+ 800766e:	683b      	ldr	r3, [r7, #0]
+ 8007670:	605a      	str	r2, [r3, #4]
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+ 8007672:	4b0c      	ldr	r3, [pc, #48]	; (80076a4 <prvHeapInit+0xb0>)
+ 8007674:	681a      	ldr	r2, [r3, #0]
+ 8007676:	683b      	ldr	r3, [r7, #0]
+ 8007678:	601a      	str	r2, [r3, #0]
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ 800767a:	683b      	ldr	r3, [r7, #0]
+ 800767c:	685a      	ldr	r2, [r3, #4]
+ 800767e:	4b0a      	ldr	r3, [pc, #40]	; (80076a8 <prvHeapInit+0xb4>)
+ 8007680:	601a      	str	r2, [r3, #0]
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ 8007682:	683b      	ldr	r3, [r7, #0]
+ 8007684:	685a      	ldr	r2, [r3, #4]
+ 8007686:	4b09      	ldr	r3, [pc, #36]	; (80076ac <prvHeapInit+0xb8>)
+ 8007688:	601a      	str	r2, [r3, #0]
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+ 800768a:	4b09      	ldr	r3, [pc, #36]	; (80076b0 <prvHeapInit+0xbc>)
+ 800768c:	2280      	movs	r2, #128	; 0x80
+ 800768e:	0612      	lsls	r2, r2, #24
+ 8007690:	601a      	str	r2, [r3, #0]
+}
+ 8007692:	46c0      	nop			; (mov r8, r8)
+ 8007694:	46bd      	mov	sp, r7
+ 8007696:	b004      	add	sp, #16
+ 8007698:	bd80      	pop	{r7, pc}
+ 800769a:	46c0      	nop			; (mov r8, r8)
+ 800769c:	20000d24 	.word	0x20000d24
+ 80076a0:	20001524 	.word	0x20001524
+ 80076a4:	2000152c 	.word	0x2000152c
+ 80076a8:	20001534 	.word	0x20001534
+ 80076ac:	20001530 	.word	0x20001530
+ 80076b0:	20001538 	.word	0x20001538
+
+080076b4 <prvInsertBlockIntoFreeList>:
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+ 80076b4:	b580      	push	{r7, lr}
+ 80076b6:	b084      	sub	sp, #16
+ 80076b8:	af00      	add	r7, sp, #0
+ 80076ba:	6078      	str	r0, [r7, #4]
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ 80076bc:	4b27      	ldr	r3, [pc, #156]	; (800775c <prvInsertBlockIntoFreeList+0xa8>)
+ 80076be:	60fb      	str	r3, [r7, #12]
+ 80076c0:	e002      	b.n	80076c8 <prvInsertBlockIntoFreeList+0x14>
+ 80076c2:	68fb      	ldr	r3, [r7, #12]
+ 80076c4:	681b      	ldr	r3, [r3, #0]
+ 80076c6:	60fb      	str	r3, [r7, #12]
+ 80076c8:	68fb      	ldr	r3, [r7, #12]
+ 80076ca:	681b      	ldr	r3, [r3, #0]
+ 80076cc:	687a      	ldr	r2, [r7, #4]
+ 80076ce:	429a      	cmp	r2, r3
+ 80076d0:	d8f7      	bhi.n	80076c2 <prvInsertBlockIntoFreeList+0xe>
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+ 80076d2:	68fb      	ldr	r3, [r7, #12]
+ 80076d4:	60bb      	str	r3, [r7, #8]
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ 80076d6:	68fb      	ldr	r3, [r7, #12]
+ 80076d8:	685b      	ldr	r3, [r3, #4]
+ 80076da:	68ba      	ldr	r2, [r7, #8]
+ 80076dc:	18d3      	adds	r3, r2, r3
+ 80076de:	687a      	ldr	r2, [r7, #4]
+ 80076e0:	429a      	cmp	r2, r3
+ 80076e2:	d108      	bne.n	80076f6 <prvInsertBlockIntoFreeList+0x42>
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ 80076e4:	68fb      	ldr	r3, [r7, #12]
+ 80076e6:	685a      	ldr	r2, [r3, #4]
+ 80076e8:	687b      	ldr	r3, [r7, #4]
+ 80076ea:	685b      	ldr	r3, [r3, #4]
+ 80076ec:	18d2      	adds	r2, r2, r3
+ 80076ee:	68fb      	ldr	r3, [r7, #12]
+ 80076f0:	605a      	str	r2, [r3, #4]
+		pxBlockToInsert = pxIterator;
+ 80076f2:	68fb      	ldr	r3, [r7, #12]
+ 80076f4:	607b      	str	r3, [r7, #4]
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+ 80076f6:	687b      	ldr	r3, [r7, #4]
+ 80076f8:	60bb      	str	r3, [r7, #8]
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ 80076fa:	687b      	ldr	r3, [r7, #4]
+ 80076fc:	685b      	ldr	r3, [r3, #4]
+ 80076fe:	68ba      	ldr	r2, [r7, #8]
+ 8007700:	18d2      	adds	r2, r2, r3
+ 8007702:	68fb      	ldr	r3, [r7, #12]
+ 8007704:	681b      	ldr	r3, [r3, #0]
+ 8007706:	429a      	cmp	r2, r3
+ 8007708:	d118      	bne.n	800773c <prvInsertBlockIntoFreeList+0x88>
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+ 800770a:	68fb      	ldr	r3, [r7, #12]
+ 800770c:	681a      	ldr	r2, [r3, #0]
+ 800770e:	4b14      	ldr	r3, [pc, #80]	; (8007760 <prvInsertBlockIntoFreeList+0xac>)
+ 8007710:	681b      	ldr	r3, [r3, #0]
+ 8007712:	429a      	cmp	r2, r3
+ 8007714:	d00d      	beq.n	8007732 <prvInsertBlockIntoFreeList+0x7e>
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ 8007716:	687b      	ldr	r3, [r7, #4]
+ 8007718:	685a      	ldr	r2, [r3, #4]
+ 800771a:	68fb      	ldr	r3, [r7, #12]
+ 800771c:	681b      	ldr	r3, [r3, #0]
+ 800771e:	685b      	ldr	r3, [r3, #4]
+ 8007720:	18d2      	adds	r2, r2, r3
+ 8007722:	687b      	ldr	r3, [r7, #4]
+ 8007724:	605a      	str	r2, [r3, #4]
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ 8007726:	68fb      	ldr	r3, [r7, #12]
+ 8007728:	681b      	ldr	r3, [r3, #0]
+ 800772a:	681a      	ldr	r2, [r3, #0]
+ 800772c:	687b      	ldr	r3, [r7, #4]
+ 800772e:	601a      	str	r2, [r3, #0]
+ 8007730:	e008      	b.n	8007744 <prvInsertBlockIntoFreeList+0x90>
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ 8007732:	4b0b      	ldr	r3, [pc, #44]	; (8007760 <prvInsertBlockIntoFreeList+0xac>)
+ 8007734:	681a      	ldr	r2, [r3, #0]
+ 8007736:	687b      	ldr	r3, [r7, #4]
+ 8007738:	601a      	str	r2, [r3, #0]
+ 800773a:	e003      	b.n	8007744 <prvInsertBlockIntoFreeList+0x90>
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ 800773c:	68fb      	ldr	r3, [r7, #12]
+ 800773e:	681a      	ldr	r2, [r3, #0]
+ 8007740:	687b      	ldr	r3, [r7, #4]
+ 8007742:	601a      	str	r2, [r3, #0]
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+ 8007744:	68fa      	ldr	r2, [r7, #12]
+ 8007746:	687b      	ldr	r3, [r7, #4]
+ 8007748:	429a      	cmp	r2, r3
+ 800774a:	d002      	beq.n	8007752 <prvInsertBlockIntoFreeList+0x9e>
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ 800774c:	68fb      	ldr	r3, [r7, #12]
+ 800774e:	687a      	ldr	r2, [r7, #4]
+ 8007750:	601a      	str	r2, [r3, #0]
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+ 8007752:	46c0      	nop			; (mov r8, r8)
+ 8007754:	46bd      	mov	sp, r7
+ 8007756:	b004      	add	sp, #16
+ 8007758:	bd80      	pop	{r7, pc}
+ 800775a:	46c0      	nop			; (mov r8, r8)
+ 800775c:	20001524 	.word	0x20001524
+ 8007760:	2000152c 	.word	0x2000152c
+
+08007764 <__libc_init_array>:
+ 8007764:	b570      	push	{r4, r5, r6, lr}
+ 8007766:	2600      	movs	r6, #0
+ 8007768:	4d0c      	ldr	r5, [pc, #48]	; (800779c <__libc_init_array+0x38>)
+ 800776a:	4c0d      	ldr	r4, [pc, #52]	; (80077a0 <__libc_init_array+0x3c>)
+ 800776c:	1b64      	subs	r4, r4, r5
+ 800776e:	10a4      	asrs	r4, r4, #2
+ 8007770:	42a6      	cmp	r6, r4
+ 8007772:	d109      	bne.n	8007788 <__libc_init_array+0x24>
+ 8007774:	2600      	movs	r6, #0
+ 8007776:	f000 f82b 	bl	80077d0 <_init>
+ 800777a:	4d0a      	ldr	r5, [pc, #40]	; (80077a4 <__libc_init_array+0x40>)
+ 800777c:	4c0a      	ldr	r4, [pc, #40]	; (80077a8 <__libc_init_array+0x44>)
+ 800777e:	1b64      	subs	r4, r4, r5
+ 8007780:	10a4      	asrs	r4, r4, #2
+ 8007782:	42a6      	cmp	r6, r4
+ 8007784:	d105      	bne.n	8007792 <__libc_init_array+0x2e>
+ 8007786:	bd70      	pop	{r4, r5, r6, pc}
+ 8007788:	00b3      	lsls	r3, r6, #2
+ 800778a:	58eb      	ldr	r3, [r5, r3]
+ 800778c:	4798      	blx	r3
+ 800778e:	3601      	adds	r6, #1
+ 8007790:	e7ee      	b.n	8007770 <__libc_init_array+0xc>
+ 8007792:	00b3      	lsls	r3, r6, #2
+ 8007794:	58eb      	ldr	r3, [r5, r3]
+ 8007796:	4798      	blx	r3
+ 8007798:	3601      	adds	r6, #1
+ 800779a:	e7f2      	b.n	8007782 <__libc_init_array+0x1e>
+ 800779c:	08007920 	.word	0x08007920
+ 80077a0:	08007920 	.word	0x08007920
+ 80077a4:	08007920 	.word	0x08007920
+ 80077a8:	08007924 	.word	0x08007924
+
+080077ac <memcpy>:
+ 80077ac:	2300      	movs	r3, #0
+ 80077ae:	b510      	push	{r4, lr}
+ 80077b0:	429a      	cmp	r2, r3
+ 80077b2:	d100      	bne.n	80077b6 <memcpy+0xa>
+ 80077b4:	bd10      	pop	{r4, pc}
+ 80077b6:	5ccc      	ldrb	r4, [r1, r3]
+ 80077b8:	54c4      	strb	r4, [r0, r3]
+ 80077ba:	3301      	adds	r3, #1
+ 80077bc:	e7f8      	b.n	80077b0 <memcpy+0x4>
+
+080077be <memset>:
+ 80077be:	0003      	movs	r3, r0
+ 80077c0:	1882      	adds	r2, r0, r2
+ 80077c2:	4293      	cmp	r3, r2
+ 80077c4:	d100      	bne.n	80077c8 <memset+0xa>
+ 80077c6:	4770      	bx	lr
+ 80077c8:	7019      	strb	r1, [r3, #0]
+ 80077ca:	3301      	adds	r3, #1
+ 80077cc:	e7f9      	b.n	80077c2 <memset+0x4>
+	...
+
+080077d0 <_init>:
+ 80077d0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80077d2:	46c0      	nop			; (mov r8, r8)
+ 80077d4:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 80077d6:	bc08      	pop	{r3}
+ 80077d8:	469e      	mov	lr, r3
+ 80077da:	4770      	bx	lr
+
+080077dc <_fini>:
+ 80077dc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80077de:	46c0      	nop			; (mov r8, r8)
+ 80077e0:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 80077e2:	bc08      	pop	{r3}
+ 80077e4:	469e      	mov	lr, r3
+ 80077e6:	4770      	bx	lr
diff --git a/software/dumber3/Debug/Dumber3.map b/software/dumber3/Debug/Dumber3.map
new file mode 100644
index 0000000..20dbc87
--- /dev/null
+++ b/software/dumber3/Debug/Dumber3.map
@@ -0,0 +1,6594 @@
+Archive member included to satisfy reference by file (symbol)
+
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o)
+                              ./Core/Src/syscalls.o (__errno)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o)
+                              /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (exit)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o)
+                              /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) (_global_impure_ptr)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+                              /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (__libc_init_array)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o)
+                              ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o (memcpy)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+                              /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (memset)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-strlen.o)
+                              ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o (strlen)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+                              ./Core/Src/main.o (__aeabi_uidiv)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+                              /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o)
+                              ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o (__aeabi_uldivmod)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o)
+                              ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o (__aeabi_lmul)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o)
+                              /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o)
+                              /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) (__clzdi2)
+/opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o)
+                              /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) (__clzsi2)
+
+Allocating common symbols
+Common symbol       size              file
+
+defaultTaskHandle   0x4               ./Core/Src/main.o
+MOTEUR_NBImpulsionsD
+                    0x2               ./Core/Src/moteurs.o
+XBEE_Mailbox        0x4               ./Core/Src/messages.o
+MOTEUR_DerniereValEncodeursD
+                    0x2               ./Core/Src/moteurs.o
+uwTick              0x4               ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+xQueueRegistry      0x40              ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+pFlash              0x18              ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o
+hlpuart1            0x84              ./Core/Src/main.o
+MOTEUR_DerniereValEncodeursG
+                    0x2               ./Core/Src/moteurs.o
+MOTEUR_CmdMoteurD   0x2               ./Core/Src/moteurs.o
+MOTEUR_ConsigneMoteurG
+                    0x2               ./Core/Src/moteurs.o
+MOTEURS_Mailbox     0x4               ./Core/Src/messages.o
+LEDS_Animation      0x1               ./Core/Src/leds.o
+hlptim1             0x30              ./Core/Src/main.o
+MOTEUR_NBImpulsionsG
+                    0x2               ./Core/Src/moteurs.o
+BATTERIE_Mailbox    0x4               ./Core/Src/messages.o
+MOTEUR_ConsigneMoteurD
+                    0x2               ./Core/Src/moteurs.o
+hdma_lpuart1_tx     0x48              ./Core/Src/main.o
+hdma_lpuart1_rx     0x48              ./Core/Src/main.o
+xStackLeds          0x190             ./Core/Src/leds.o
+htim2               0x40              ./Core/Src/main.o
+MOTEUR_CmdMoteurG   0x2               ./Core/Src/moteurs.o
+SEQUENCEUR_Mailbox  0x4               ./Core/Src/messages.o
+LEDS_Mailbox        0x4               ./Core/Src/messages.o
+hadc                0x5c              ./Core/Src/main.o
+LEDS_AnimationAncien
+                    0x1               ./Core/Src/leds.o
+xTaskLeds           0x5c              ./Core/Src/leds.o
+htim21              0x40              ./Core/Src/main.o
+
+Discarded input sections
+
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+ .text          0x0000000000000000        0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o
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+ .eh_frame      0x0000000000000000        0x4 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o
+ .ARM.attributes
+                0x0000000000000000       0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o
+ .text          0x0000000000000000        0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+ .data          0x0000000000000000        0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+ .bss           0x0000000000000000        0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+RAM              0x0000000020000000 0x0000000000002000 xrw
+FLASH            0x0000000008000000 0x0000000000008000 xr
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+LOAD ./Core/Src/batterie.o
+LOAD ./Core/Src/freertos.o
+LOAD ./Core/Src/leds.o
+LOAD ./Core/Src/main.o
+LOAD ./Core/Src/messages.o
+LOAD ./Core/Src/moteurs.o
+LOAD ./Core/Src/sequenceur.o
+LOAD ./Core/Src/stm32l0xx_hal_msp.o
+LOAD ./Core/Src/stm32l0xx_it.o
+LOAD ./Core/Src/syscalls.o
+LOAD ./Core/Src/sysmem.o
+LOAD ./Core/Src/system_stm32l0xx.o
+LOAD ./Core/Src/xbee.o
+LOAD ./Core/Startup/startup_stm32l010c6tx.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+LOAD ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/list.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+START GROUP
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a
+END GROUP
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+                0x0000000020002000                _estack = (ORIGIN (RAM) + LENGTH (RAM))
+                0x0000000000000200                _Min_Heap_Size = 0x200
+                0x0000000000000400                _Min_Stack_Size = 0x400
+
+.isr_vector     0x0000000008000000       0xc0
+                0x0000000008000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x0000000008000000       0xc0 ./Core/Startup/startup_stm32l010c6tx.o
+                0x0000000008000000                g_pfnVectors
+                0x00000000080000c0                . = ALIGN (0x4)
+
+.text           0x00000000080000c0     0x7728
+                0x00000000080000c0                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000000080000c0       0x48 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
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+                0x0000000020000008        0x1 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+                0x0000000020000008                uwTickFreq
+ *fill*         0x0000000020000009        0x3 
+ .data.uxCriticalNesting
+                0x000000002000000c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ *(.RamFunc)
+ *(.RamFunc*)
+                0x0000000020000010                . = ALIGN (0x4)
+                0x0000000020000010                _edata = .
+
+.igot.plt       0x0000000020000010        0x0 load address 0x0000000008007938
+ .igot.plt      0x0000000020000010        0x0 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+                0x0000000020000010                . = ALIGN (0x4)
+
+.bss            0x0000000020000010     0x199c load address 0x0000000008007938
+                0x0000000020000010                _sbss = .
+                0x0000000020000010                __bss_start__ = _sbss
+ *(.bss)
+ .bss           0x0000000020000010       0x1c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+ *(.bss*)
+ .bss.xHandleLeds
+                0x000000002000002c        0x4 ./Core/Src/leds.o
+                0x000000002000002c                xHandleLeds
+ .bss.KernelState
+                0x0000000020000030        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .bss.Idle_TCB  0x0000000020000034       0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .bss.Idle_Stack
+                0x0000000020000090      0x200 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .bss.Timer_TCB
+                0x0000000020000290       0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .bss.Timer_Stack
+                0x00000000200002ec      0x400 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .bss.pxCurrentTCB
+                0x00000000200006ec        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+                0x00000000200006ec                pxCurrentTCB
+ .bss.pxReadyTasksLists
+                0x00000000200006f0      0x460 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xDelayedTaskList1
+                0x0000000020000b50       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xDelayedTaskList2
+                0x0000000020000b64       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.pxDelayedTaskList
+                0x0000000020000b78        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.pxOverflowDelayedTaskList
+                0x0000000020000b7c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xPendingReadyList
+                0x0000000020000b80       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xTasksWaitingTermination
+                0x0000000020000b94       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxDeletedTasksWaitingCleanUp
+                0x0000000020000ba8        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xSuspendedTaskList
+                0x0000000020000bac       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxCurrentNumberOfTasks
+                0x0000000020000bc0        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xTickCount
+                0x0000000020000bc4        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxTopReadyPriority
+                0x0000000020000bc8        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xSchedulerRunning
+                0x0000000020000bcc        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxPendedTicks
+                0x0000000020000bd0        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xYieldPending
+                0x0000000020000bd4        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xNumOfOverflows
+                0x0000000020000bd8        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxTaskNumber
+                0x0000000020000bdc        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xNextTaskUnblockTime
+                0x0000000020000be0        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xIdleTaskHandle
+                0x0000000020000be4        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxSchedulerSuspended
+                0x0000000020000be8        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xActiveTimerList1
+                0x0000000020000bec       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xActiveTimerList2
+                0x0000000020000c00       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.pxCurrentTimerList
+                0x0000000020000c14        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.pxOverflowTimerList
+                0x0000000020000c18        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xTimerQueue
+                0x0000000020000c1c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xTimerTaskHandle
+                0x0000000020000c20        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xLastTime.5532
+                0x0000000020000c24        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.ucStaticTimerQueueStorage.5583
+                0x0000000020000c28       0xa0 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xStaticTimerQueue.5582
+                0x0000000020000cc8       0x50 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.ulTimerCountsForOneTick
+                0x0000000020000d18        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ .bss.xMaximumPossibleSuppressedTicks
+                0x0000000020000d1c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ .bss.ulStoppedTimerCompensation
+                0x0000000020000d20        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ .bss.ucHeap    0x0000000020000d24      0x800 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xStart    0x0000000020001524        0x8 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.pxEnd     0x000000002000152c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xFreeBytesRemaining
+                0x0000000020001530        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xMinimumEverFreeBytesRemaining
+                0x0000000020001534        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xBlockAllocatedBit
+                0x0000000020001538        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ *(COMMON)
+ COMMON         0x000000002000153c      0x1f4 ./Core/Src/leds.o
+                0x000000002000153c                LEDS_Animation
+                0x0000000020001540                xStackLeds
+                0x00000000200016d0                LEDS_AnimationAncien
+                0x00000000200016d4                xTaskLeds
+ COMMON         0x0000000020001730      0x224 ./Core/Src/main.o
+                0x0000000020001730                defaultTaskHandle
+                0x0000000020001734                hlpuart1
+                0x00000000200017b8                hlptim1
+                0x00000000200017e8                hdma_lpuart1_tx
+                0x0000000020001830                hdma_lpuart1_rx
+                0x0000000020001878                htim2
+                0x00000000200018b8                hadc
+                0x0000000020001914                htim21
+ COMMON         0x0000000020001954       0x14 ./Core/Src/messages.o
+                0x0000000020001954                XBEE_Mailbox
+                0x0000000020001958                MOTEURS_Mailbox
+                0x000000002000195c                BATTERIE_Mailbox
+                0x0000000020001960                SEQUENCEUR_Mailbox
+                0x0000000020001964                LEDS_Mailbox
+ COMMON         0x0000000020001968        0x4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+                0x0000000020001968                uwTick
+ COMMON         0x000000002000196c       0x40 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+                0x000000002000196c                xQueueRegistry
+                0x00000000200019ac                . = ALIGN (0x4)
+                0x00000000200019ac                _ebss = .
+                0x00000000200019ac                __bss_end__ = _ebss
+
+._user_heap_stack
+                0x00000000200019ac      0x604 load address 0x0000000008007938
+                0x00000000200019b0                . = ALIGN (0x8)
+ *fill*         0x00000000200019ac        0x4 
+                [!provide]                        PROVIDE (end = .)
+                0x00000000200019b0                PROVIDE (_end = .)
+                0x0000000020001bb0                . = (. + _Min_Heap_Size)
+ *fill*         0x00000000200019b0      0x200 
+                0x0000000020001fb0                . = (. + _Min_Stack_Size)
+ *fill*         0x0000000020001bb0      0x400 
+                0x0000000020001fb0                . = ALIGN (0x8)
+
+/DISCARD/
+ libc.a(*)
+ libm.a(*)
+ libgcc.a(*)
+
+.ARM.attributes
+                0x0000000000000000       0x28
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x0000000000000000       0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
+ .ARM.attributes
+                0x000000000000001e       0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+ .ARM.attributes
+                0x000000000000004a       0x2c ./Core/Src/freertos.o
+ .ARM.attributes
+                0x0000000000000076       0x2c ./Core/Src/leds.o
+ .ARM.attributes
+                0x00000000000000a2       0x2c ./Core/Src/main.o
+ .ARM.attributes
+                0x00000000000000ce       0x2c ./Core/Src/messages.o
+ .ARM.attributes
+                0x00000000000000fa       0x2c ./Core/Src/stm32l0xx_hal_msp.o
+ .ARM.attributes
+                0x0000000000000126       0x2c ./Core/Src/stm32l0xx_it.o
+ .ARM.attributes
+                0x0000000000000152       0x2c ./Core/Src/system_stm32l0xx.o
+ .ARM.attributes
+                0x000000000000017e       0x22 ./Core/Startup/startup_stm32l010c6tx.o
+ .ARM.attributes
+                0x00000000000001a0       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ .ARM.attributes
+                0x00000000000001cc       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o
+ .ARM.attributes
+                0x00000000000001f8       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+ .ARM.attributes
+                0x0000000000000224       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o
+ .ARM.attributes
+                0x0000000000000250       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o
+ .ARM.attributes
+                0x000000000000027c       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o
+ .ARM.attributes
+                0x00000000000002a8       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ .ARM.attributes
+                0x00000000000002d4       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o
+ .ARM.attributes
+                0x0000000000000300       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ .ARM.attributes
+                0x000000000000032c       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o
+ .ARM.attributes
+                0x0000000000000358       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ .ARM.attributes
+                0x0000000000000384       0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o
+ .ARM.attributes
+                0x00000000000003b0       0x2c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .ARM.attributes
+                0x00000000000003dc       0x2c ./Middlewares/Third_Party/FreeRTOS/Source/list.o
+ .ARM.attributes
+                0x0000000000000408       0x2c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+ .ARM.attributes
+                0x0000000000000434       0x2c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .ARM.attributes
+                0x0000000000000460       0x2c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .ARM.attributes
+                0x000000000000048c       0x2c ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ .ARM.attributes
+                0x00000000000004b8       0x2c ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .ARM.attributes
+                0x00000000000004e4       0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+ .ARM.attributes
+                0x0000000000000510       0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o)
+ .ARM.attributes
+                0x000000000000053c       0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+ .ARM.attributes
+                0x0000000000000568       0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .ARM.attributes
+                0x0000000000000586       0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .ARM.attributes
+                0x00000000000005a4       0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o)
+ .ARM.attributes
+                0x00000000000005c2       0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o)
+ .ARM.attributes
+                0x00000000000005ee       0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o)
+ .ARM.attributes
+                0x000000000000061a       0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o)
+ .ARM.attributes
+                0x0000000000000638       0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o)
+ .ARM.attributes
+                0x0000000000000656       0x1e /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+OUTPUT(Dumber3.elf elf32-littlearm)
+LOAD linker stubs
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc.a
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a
+LOAD /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
+
+.debug_info     0x0000000000000000    0x1c98c
+ .debug_info    0x0000000000000000      0x222 ./Core/Src/freertos.o
+ .debug_info    0x0000000000000222      0x5c8 ./Core/Src/leds.o
+ .debug_info    0x00000000000007ea     0x1b91 ./Core/Src/main.o
+ .debug_info    0x000000000000237b      0xc27 ./Core/Src/messages.o
+ .debug_info    0x0000000000002fa2     0x1556 ./Core/Src/stm32l0xx_hal_msp.o
+ .debug_info    0x00000000000044f8      0xac5 ./Core/Src/stm32l0xx_it.o
+ .debug_info    0x0000000000004fbd      0x363 ./Core/Src/system_stm32l0xx.o
+ .debug_info    0x0000000000005320       0x22 ./Core/Startup/startup_stm32l010c6tx.o
+ .debug_info    0x0000000000005342      0x8a5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ .debug_info    0x0000000000005be7      0xe01 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o
+ .debug_info    0x00000000000069e8      0x7b3 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+ .debug_info    0x000000000000719b      0x834 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o
+ .debug_info    0x00000000000079cf      0x77c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o
+ .debug_info    0x000000000000814b      0xee5 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o
+ .debug_info    0x0000000000009030      0x98e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ .debug_info    0x00000000000099be      0x567 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o
+ .debug_info    0x0000000000009f25     0x2a96 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ .debug_info    0x000000000000c9bb      0x7d8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o
+ .debug_info    0x000000000000d193     0x3ca7 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ .debug_info    0x0000000000010e3a      0xdcd ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o
+ .debug_info    0x0000000000011c07     0x35df ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .debug_info    0x00000000000151e6      0xb82 ./Middlewares/Third_Party/FreeRTOS/Source/list.o
+ .debug_info    0x0000000000015d68     0x1d2e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+ .debug_info    0x0000000000017a96     0x2630 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .debug_info    0x000000000001a0c6     0x1984 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .debug_info    0x000000000001ba4a      0x371 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ .debug_info    0x000000000001bdbb      0xbd1 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+
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+ .debug_line    0x0000000000015968     0x1bf4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .debug_line    0x000000000001755c      0xbea ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .debug_line    0x0000000000018146      0x774 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ .debug_line    0x00000000000188ba      0x867 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+
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+ .debug_str     0x000000000006df91      0x4ae ./Core/Src/leds.o
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+ .debug_str     0x000000000006e43f     0x13bd ./Core/Src/main.o
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+ .debug_str     0x000000000006f7fc     0x327e ./Core/Src/messages.o
+                                      0x715bd (size before relaxing)
+ .debug_str     0x0000000000072a7a      0x133 ./Core/Src/stm32l0xx_hal_msp.o
+                                      0x6f074 (size before relaxing)
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+ .debug_str     0x0000000000072c97       0x36 ./Core/Startup/startup_stm32l010c6tx.o
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+ .debug_str     0x00000000000730c5      0x33e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o
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+ .debug_str     0x0000000000073842      0x137 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o
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+ .debug_str     0x0000000000073979      0x460 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o
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+ .debug_str     0x0000000000073dd9      0x284 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
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+ .debug_str     0x000000000007405d      0x13a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o
+                                      0x6900d (size before relaxing)
+ .debug_str     0x0000000000074197      0xc98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+                                      0x6a0fa (size before relaxing)
+ .debug_str     0x0000000000074e2f       0x7d ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o
+                                      0x692d1 (size before relaxing)
+ .debug_str     0x0000000000074eac      0x8c3 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+                                      0x69b31 (size before relaxing)
+ .debug_str     0x000000000007576f      0x1dd ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o
+                                      0x693cb (size before relaxing)
+ .debug_str     0x000000000007594c     0x1fa8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+                                       0xe0bd (size before relaxing)
+ .debug_str     0x00000000000778f4      0x12d ./Middlewares/Third_Party/FreeRTOS/Source/list.o
+                                       0xa76f (size before relaxing)
+ .debug_str     0x0000000000077a21      0x91c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+                                       0xc06f (size before relaxing)
+ .debug_str     0x000000000007833d     0x13af ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+                                       0xccff (size before relaxing)
+ .debug_str     0x00000000000796ec      0x60b ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+                                       0xc636 (size before relaxing)
+ .debug_str     0x0000000000079cf7      0x583 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+                                       0x8012 (size before relaxing)
+ .debug_str     0x000000000007a27a      0x251 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+                                       0xaf43 (size before relaxing)
+
+.comment        0x0000000000000000       0x53
+ .comment       0x0000000000000000       0x53 ./Core/Src/freertos.o
+                                         0x54 (size before relaxing)
+ .comment       0x0000000000000053       0x54 ./Core/Src/leds.o
+ .comment       0x0000000000000053       0x54 ./Core/Src/main.o
+ .comment       0x0000000000000053       0x54 ./Core/Src/messages.o
+ .comment       0x0000000000000053       0x54 ./Core/Src/stm32l0xx_hal_msp.o
+ .comment       0x0000000000000053       0x54 ./Core/Src/stm32l0xx_it.o
+ .comment       0x0000000000000053       0x54 ./Core/Src/system_stm32l0xx.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o
+ .comment       0x0000000000000053       0x54 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .comment       0x0000000000000053       0x54 ./Middlewares/Third_Party/FreeRTOS/Source/list.o
+ .comment       0x0000000000000053       0x54 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+ .comment       0x0000000000000053       0x54 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .comment       0x0000000000000053       0x54 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .comment       0x0000000000000053       0x54 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ .comment       0x0000000000000053       0x54 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+
+.debug_frame    0x0000000000000000     0x5064
+ .debug_frame   0x0000000000000000       0x50 ./Core/Src/freertos.o
+ .debug_frame   0x0000000000000050       0x74 ./Core/Src/leds.o
+ .debug_frame   0x00000000000000c4      0x180 ./Core/Src/main.o
+ .debug_frame   0x0000000000000244       0x8c ./Core/Src/messages.o
+ .debug_frame   0x00000000000002d0      0x18c ./Core/Src/stm32l0xx_hal_msp.o
+ .debug_frame   0x000000000000045c       0xd4 ./Core/Src/stm32l0xx_it.o
+ .debug_frame   0x0000000000000530       0x4c ./Core/Src/system_stm32l0xx.o
+ .debug_frame   0x000000000000057c      0x394 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ .debug_frame   0x0000000000000910      0x3c0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o
+ .debug_frame   0x0000000000000cd0      0x2a0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+ .debug_frame   0x0000000000000f70      0x1b0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o
+ .debug_frame   0x0000000000001120      0x110 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o
+ .debug_frame   0x0000000000001230      0x550 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o
+ .debug_frame   0x0000000000001780      0x1a8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ .debug_frame   0x0000000000001928       0xfc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o
+ .debug_frame   0x0000000000001a24      0xef8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ .debug_frame   0x000000000000291c       0x50 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o
+ .debug_frame   0x000000000000296c      0x854 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ .debug_frame   0x00000000000031c0      0x198 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o
+ .debug_frame   0x0000000000003358      0x848 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o
+ .debug_frame   0x0000000000003ba0       0xb0 ./Middlewares/Third_Party/FreeRTOS/Source/list.o
+ .debug_frame   0x0000000000003c50      0x510 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+ .debug_frame   0x0000000000004160      0x83c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .debug_frame   0x000000000000499c      0x34c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .debug_frame   0x0000000000004ce8      0x194 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o
+ .debug_frame   0x0000000000004e7c       0xe4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .debug_frame   0x0000000000004f60       0x2c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+ .debug_frame   0x0000000000004f8c       0x28 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memcpy-stub.o)
+ .debug_frame   0x0000000000004fb4       0x20 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+ .debug_frame   0x0000000000004fd4       0x20 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_frame   0x0000000000004ff4       0x34 /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o)
+ .debug_frame   0x0000000000005028       0x3c /opt/st/stm32cubeide_1.7.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o)
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su
new file mode 100644
index 0000000..2e82ff7
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su
@@ -0,0 +1,66 @@
+cmsis_os2.c:168:22:SVC_Setup	8	static
+cmsis_os2.c:185:12:osKernelInitialize	24	static,ignoring_inline_asm
+cmsis_os2.c:206:12:osKernelGetInfo	24	static
+cmsis_os2.c:224:17:osKernelGetState	16	static
+cmsis_os2.c:249:12:osKernelStart	24	static,ignoring_inline_asm
+cmsis_os2.c:272:9:osKernelLock	24	static,ignoring_inline_asm
+cmsis_os2.c:299:9:osKernelUnlock	24	static,ignoring_inline_asm
+cmsis_os2.c:331:9:osKernelRestoreLock	24	static,ignoring_inline_asm
+cmsis_os2.c:367:10:osKernelGetTickCount	24	static,ignoring_inline_asm
+cmsis_os2.c:379:10:osKernelGetTickFreq	8	static
+cmsis_os2.c:383:10:osKernelGetSysTimerCount	24	static,ignoring_inline_asm
+cmsis_os2.c:400:10:osKernelGetSysTimerFreq	8	static
+cmsis_os2.c:406:14:osThreadNew	80	static,ignoring_inline_asm
+cmsis_os2.c:470:13:osThreadGetName	32	static,ignoring_inline_asm
+cmsis_os2.c:483:14:osThreadGetId	16	static
+cmsis_os2.c:491:17:osThreadGetState	32	static,ignoring_inline_asm
+cmsis_os2.c:513:10:osThreadGetStackSpace	32	static,ignoring_inline_asm
+cmsis_os2.c:526:12:osThreadSetPriority	32	static,ignoring_inline_asm
+cmsis_os2.c:544:14:osThreadGetPriority	32	static,ignoring_inline_asm
+cmsis_os2.c:557:12:osThreadYield	24	static,ignoring_inline_asm
+cmsis_os2.c:570:12:osThreadSuspend	32	static,ignoring_inline_asm
+cmsis_os2.c:588:12:osThreadResume	32	static,ignoring_inline_asm
+cmsis_os2.c:606:18:osThreadExit	8	static
+cmsis_os2.c:613:12:osThreadTerminate	48	static,ignoring_inline_asm
+cmsis_os2.c:642:10:osThreadGetCount	24	static,ignoring_inline_asm
+cmsis_os2.c:654:10:osThreadEnumerate	40	static,ignoring_inline_asm
+cmsis_os2.c:682:10:osThreadFlagsSet	48	static,ignoring_inline_asm
+cmsis_os2.c:710:10:osThreadFlagsClear	40	static,ignoring_inline_asm
+cmsis_os2.c:740:10:osThreadFlagsGet	24	static,ignoring_inline_asm
+cmsis_os2.c:758:10:osThreadFlagsWait	64	static,ignoring_inline_asm
+cmsis_os2.c:833:12:osDelay	32	static,ignoring_inline_asm
+cmsis_os2.c:850:12:osDelayUntil	40	static,ignoring_inline_asm
+cmsis_os2.c:880:13:TimerCallback	24	static
+cmsis_os2.c:890:13:osTimerNew	64	static,ignoring_inline_asm
+cmsis_os2.c:948:13:osTimerGetName	32	static,ignoring_inline_asm
+cmsis_os2.c:961:12:osTimerStart	40	static,ignoring_inline_asm
+cmsis_os2.c:982:12:osTimerStop	40	static,ignoring_inline_asm
+cmsis_os2.c:1008:10:osTimerIsRunning	32	static,ignoring_inline_asm
+cmsis_os2.c:1021:12:osTimerDelete	48	static,ignoring_inline_asm
+cmsis_os2.c:1052:18:osEventFlagsNew	32	static,ignoring_inline_asm
+cmsis_os2.c:1088:10:osEventFlagsSet	40	static,ignoring_inline_asm
+cmsis_os2.c:1113:10:osEventFlagsClear	32	static,ignoring_inline_asm
+cmsis_os2.c:1134:10:osEventFlagsGet	32	static,ignoring_inline_asm
+cmsis_os2.c:1151:10:osEventFlagsWait	64	static,ignoring_inline_asm
+cmsis_os2.c:1201:12:osEventFlagsDelete	32	static,ignoring_inline_asm
+cmsis_os2.c:1225:13:osMutexNew	48	static,ignoring_inline_asm
+cmsis_os2.c:1304:12:osMutexAcquire	40	static,ignoring_inline_asm
+cmsis_os2.c:1345:12:osMutexRelease	40	static,ignoring_inline_asm
+cmsis_os2.c:1378:14:osMutexGetOwner	32	static,ignoring_inline_asm
+cmsis_os2.c:1393:12:osMutexDelete	32	static,ignoring_inline_asm
+cmsis_os2.c:1422:17:osSemaphoreNew	56	static,ignoring_inline_asm
+cmsis_os2.c:1489:12:osSemaphoreAcquire	40	static,ignoring_inline_asm
+cmsis_os2.c:1526:12:osSemaphoreRelease	40	static,ignoring_inline_asm
+cmsis_os2.c:1554:10:osSemaphoreGetCount	32	static,ignoring_inline_asm
+cmsis_os2.c:1570:12:osSemaphoreDelete	32	static,ignoring_inline_asm
+cmsis_os2.c:1598:20:osMessageQueueNew	64	static,ignoring_inline_asm
+cmsis_os2.c:1651:12:osMessageQueuePut	48	static,ignoring_inline_asm
+cmsis_os2.c:1692:12:osMessageQueueGet	48	static,ignoring_inline_asm
+cmsis_os2.c:1733:10:osMessageQueueGetCapacity	24	static
+cmsis_os2.c:1747:10:osMessageQueueGetMsgSize	24	static
+cmsis_os2.c:1761:10:osMessageQueueGetCount	32	static,ignoring_inline_asm
+cmsis_os2.c:1778:10:osMessageQueueGetSpace	40	static,ignoring_inline_asm
+cmsis_os2.c:1801:12:osMessageQueueReset	32	static,ignoring_inline_asm
+cmsis_os2.c:1819:12:osMessageQueueDelete	32	static,ignoring_inline_asm
+cmsis_os2.c:1910:6:vApplicationGetIdleTaskMemory	24	static
+cmsis_os2.c:1920:6:vApplicationGetTimerTaskMemory	24	static
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk
new file mode 100644
index 0000000..c277b0a
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su
new file mode 100644
index 0000000..e69de29
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su
new file mode 100644
index 0000000..cada37b
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su
@@ -0,0 +1,15 @@
+event_groups.c:93:21:xEventGroupCreateStatic	24	static,ignoring_inline_asm
+event_groups.c:145:21:xEventGroupCreate	16	static
+event_groups.c:191:13:xEventGroupSync	48	static,ignoring_inline_asm
+event_groups.c:311:13:xEventGroupWaitBits	56	static,ignoring_inline_asm
+event_groups.c:461:13:xEventGroupClearBits	24	static,ignoring_inline_asm
+event_groups.c:490:13:xEventGroupClearBitsFromISR	24	static
+event_groups.c:503:13:xEventGroupGetBitsFromISR	32	static
+event_groups.c:519:13:xEventGroupSetBits	56	static,ignoring_inline_asm
+event_groups.c:613:6:vEventGroupDelete	24	static,ignoring_inline_asm
+event_groups.c:657:6:vEventGroupSetBitsCallback	16	static
+event_groups.c:665:6:vEventGroupClearBitsCallback	16	static
+event_groups.c:671:19:prvTestWaitCondition	32	static
+event_groups.c:708:13:xEventGroupSetBitsFromISR	32	static
+event_groups.c:723:14:uxEventGroupGetNumber	24	static
+event_groups.c:745:7:vEventGroupSetNumber	16	static
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su
new file mode 100644
index 0000000..e840c82
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su
@@ -0,0 +1,5 @@
+list.c:37:6:vListInitialise	16	static
+list.c:62:6:vListInitialiseItem	16	static
+list.c:74:6:vListInsertEnd	24	static
+list.c:103:6:vListInsert	24	static
+list.c:170:13:uxListRemove	24	static
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.su
new file mode 100644
index 0000000..54cd2bd
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.su
@@ -0,0 +1,15 @@
+port.c:133:14:pxPortInitialiseStack	24	static
+port.c:151:13:prvTaskExitError	16	static,ignoring_inline_asm
+port.c:176:6:SVC_Handler	8	static
+port.c:183:6:vPortStartFirstTask	0	static,ignoring_inline_asm
+port.c:214:12:xPortStartScheduler	8	static
+port.c:244:6:vPortEndScheduler	8	static,ignoring_inline_asm
+port.c:252:6:vPortYield	8	static,ignoring_inline_asm
+port.c:264:6:vPortEnterCritical	8	static,ignoring_inline_asm
+port.c:273:6:vPortExitCritical	8	static,ignoring_inline_asm
+port.c:284:10:ulSetInterruptMaskFromISR	0	static,ignoring_inline_asm
+port.c:302:6:vClearInterruptMaskFromISR	0	static,ignoring_inline_asm
+port.c:319:6:PendSV_Handler	0	static,ignoring_inline_asm
+port.c:368:6:xPortSysTickHandler	16	static
+port.c:387:29:vPortSuppressTicksAndSleep	40	static,ignoring_inline_asm
+port.c:541:6:prvSetupTimerInterrupt	8	static
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk
new file mode 100644
index 0000000..ef52c34
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/%.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su
new file mode 100644
index 0000000..34bb535
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su
@@ -0,0 +1,7 @@
+heap_4.c:113:7:pvPortMalloc	32	static,ignoring_inline_asm
+heap_4.c:263:6:vPortFree	24	static,ignoring_inline_asm
+heap_4.c:311:8:xPortGetFreeHeapSize	8	static
+heap_4.c:317:8:xPortGetMinimumEverFreeHeapSize	8	static
+heap_4.c:323:6:vPortInitialiseBlocks	8	static
+heap_4.c:329:13:prvHeapInit	24	static
+heap_4.c:377:13:prvInsertBlockIntoFreeList	24	static
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
new file mode 100644
index 0000000..407be28
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su
new file mode 100644
index 0000000..9df0fdc
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su
@@ -0,0 +1,40 @@
+queue.c:255:12:xQueueGenericReset	24	static,ignoring_inline_asm
+queue.c:310:16:xQueueGenericCreateStatic	48	static,ignoring_inline_asm
+queue.c:368:16:xQueueGenericCreate	56	static,ignoring_inline_asm
+queue.c:429:13:prvInitialiseNewQueue	24	static
+queue.c:473:14:prvInitialiseMutex	16	static
+queue.c:503:16:xQueueCreateMutex	32	static
+queue.c:519:16:xQueueCreateMutexStatic	40	static
+queue.c:539:15:xQueueGetMutexHolder	24	static
+queue.c:570:15:xQueueGetMutexHolderFromISR	24	static,ignoring_inline_asm
+queue.c:596:13:xQueueGiveMutexRecursive	32	static,ignoring_inline_asm
+queue.c:651:13:xQueueTakeMutexRecursive	32	static,ignoring_inline_asm
+queue.c:693:16:xQueueCreateCountingSemaphoreStatic	40	static,ignoring_inline_asm
+queue.c:721:16:xQueueCreateCountingSemaphore	24	static,ignoring_inline_asm
+queue.c:747:12:xQueueGenericSend	48	static,ignoring_inline_asm
+queue.c:957:12:xQueueGenericSendFromISR	48	static,ignoring_inline_asm
+queue.c:1108:12:xQueueGiveFromISR	40	static,ignoring_inline_asm
+queue.c:1273:12:xQueueReceive	48	static,ignoring_inline_asm
+queue.c:1414:12:xQueueSemaphoreTake	48	static,ignoring_inline_asm
+queue.c:1632:12:xQueuePeek	48	static,ignoring_inline_asm
+queue.c:1781:12:xQueueReceiveFromISR	56	static,ignoring_inline_asm
+queue.c:1872:12:xQueuePeekFromISR	32	static,ignoring_inline_asm
+queue.c:1926:13:uxQueueMessagesWaiting	24	static,ignoring_inline_asm
+queue.c:1942:13:uxQueueSpacesAvailable	24	static,ignoring_inline_asm
+queue.c:1959:13:uxQueueMessagesWaitingFromISR	24	static,ignoring_inline_asm
+queue.c:1971:6:vQueueDelete	24	static,ignoring_inline_asm
+queue.c:2015:14:uxQueueGetQueueNumber	16	static
+queue.c:2025:7:vQueueSetQueueNumber	16	static
+queue.c:2035:10:ucQueueGetQueueType	16	static
+queue.c:2045:21:prvGetDisinheritPriorityAfterTimeout	24	static
+queue.c:2070:19:prvCopyDataToQueue	32	static
+queue.c:2149:13:prvCopyDataFromQueue	16	static
+queue.c:2167:13:prvUnlockQueue	24	static
+queue.c:2287:19:prvIsQueueEmpty	24	static
+queue.c:2308:12:xQueueIsQueueEmptyFromISR	24	static,ignoring_inline_asm
+queue.c:2327:19:prvIsQueueFull	24	static
+queue.c:2348:12:xQueueIsQueueFullFromISR	24	static,ignoring_inline_asm
+queue.c:2644:7:vQueueAddToRegistry	24	static
+queue.c:2673:14:pcQueueGetName	24	static
+queue.c:2701:7:vQueueUnregisterQueue	24	static
+queue.c:2733:7:vQueueWaitForMessageRestricted	32	static
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su
new file mode 100644
index 0000000..cb2f2ed
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su
@@ -0,0 +1,25 @@
+stream_buffer.c:219:23:xStreamBufferGenericCreate	48	static,ignoring_inline_asm
+stream_buffer.c:283:23:xStreamBufferGenericCreateStatic	56	static,ignoring_inline_asm
+stream_buffer.c:359:6:vStreamBufferDelete	24	static,ignoring_inline_asm
+stream_buffer.c:392:12:xStreamBufferReset	48	static,ignoring_inline_asm
+stream_buffer.c:441:12:xStreamBufferSetTriggerLevel	24	static,ignoring_inline_asm
+stream_buffer.c:470:8:xStreamBufferSpacesAvailable	24	static,ignoring_inline_asm
+stream_buffer.c:494:8:xStreamBufferBytesAvailable	24	static,ignoring_inline_asm
+stream_buffer.c:506:8:xStreamBufferSend	64	static,ignoring_inline_asm
+stream_buffer.c:610:8:xStreamBufferSendFromISR	64	static,ignoring_inline_asm
+stream_buffer.c:661:15:prvWriteMessageToBuffer	32	static
+stream_buffer.c:713:8:xStreamBufferReceive	56	static,ignoring_inline_asm
+stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes	40	static,ignoring_inline_asm
+stream_buffer.c:861:8:xStreamBufferReceiveFromISR	64	static,ignoring_inline_asm
+stream_buffer.c:918:15:prvReadMessageFromBuffer	40	static
+stream_buffer.c:970:12:xStreamBufferIsEmpty	32	static,ignoring_inline_asm
+stream_buffer.c:993:12:xStreamBufferIsFull	32	static,ignoring_inline_asm
+stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR	40	static,ignoring_inline_asm
+stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR	40	static,ignoring_inline_asm
+stream_buffer.c:1088:15:prvWriteBytesToBuffer	32	static,ignoring_inline_asm
+stream_buffer.c:1134:15:prvReadBytesFromBuffer	40	static,ignoring_inline_asm
+stream_buffer.c:1189:15:prvBytesInBuffer	24	static
+stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer	32	static,ignoring_inline_asm
+stream_buffer.c:1237:14:uxStreamBufferGetStreamBufferNumber	16	static
+stream_buffer.c:1247:7:vStreamBufferSetStreamBufferNumber	16	static
+stream_buffer.c:1257:10:ucStreamBufferGetStreamBufferType	16	static
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
new file mode 100644
index 0000000..83df1cc
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
@@ -0,0 +1,38 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \
+../Middlewares/Third_Party/FreeRTOS/Source/list.c \
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c \
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/croutine.o \
+./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o \
+./Middlewares/Third_Party/FreeRTOS/Source/list.o \
+./Middlewares/Third_Party/FreeRTOS/Source/queue.o \
+./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o \
+./Middlewares/Third_Party/FreeRTOS/Source/tasks.o \
+./Middlewares/Third_Party/FreeRTOS/Source/timers.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/croutine.d \
+./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d \
+./Middlewares/Third_Party/FreeRTOS/Source/list.d \
+./Middlewares/Third_Party/FreeRTOS/Source/queue.d \
+./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d \
+./Middlewares/Third_Party/FreeRTOS/Source/tasks.d \
+./Middlewares/Third_Party/FreeRTOS/Source/timers.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/%.o: ../Middlewares/Third_Party/FreeRTOS/Source/%.c Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L010x6 -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su
new file mode 100644
index 0000000..5422d3b
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su
@@ -0,0 +1,66 @@
+tasks.c:578:15:xTaskCreateStatic	64	static,ignoring_inline_asm
+tasks.c:730:13:xTaskCreate	64	static
+tasks.c:821:13:prvInitialiseNewTask	32	static,ignoring_inline_asm
+tasks.c:1072:13:prvAddNewTaskToReadyList	16	static
+tasks.c:1157:7:vTaskDelete	24	static,ignoring_inline_asm
+tasks.c:1249:7:vTaskDelayUntil	32	static,ignoring_inline_asm
+tasks.c:1333:7:vTaskDelay	24	static,ignoring_inline_asm
+tasks.c:1378:13:eTaskGetState	40	static,ignoring_inline_asm
+tasks.c:1470:14:uxTaskPriorityGet	24	static
+tasks.c:1492:14:uxTaskPriorityGetFromISR	32	static
+tasks.c:1532:7:vTaskPrioritySet	32	static,ignoring_inline_asm
+tasks.c:1696:7:vTaskSuspend	24	static,ignoring_inline_asm
+tasks.c:1797:20:prvTaskIsTaskSuspended	24	static,ignoring_inline_asm
+tasks.c:1843:7:vTaskResume	24	static,ignoring_inline_asm
+tasks.c:1897:13:xTaskResumeFromISR	32	static,ignoring_inline_asm
+tasks.c:1967:6:vTaskStartScheduler	48	static,ignoring_inline_asm
+tasks.c:2089:6:vTaskEndScheduler	8	static,ignoring_inline_asm
+tasks.c:2100:6:vTaskSuspendAll	8	static,ignoring_inline_asm
+tasks.c:2113:20:prvGetExpectedIdleTime	16	static
+tasks.c:2174:12:xTaskResumeAll	24	static,ignoring_inline_asm
+tasks.c:2284:12:xTaskGetTickCount	16	static
+tasks.c:2299:12:xTaskGetTickCountFromISR	16	static
+tasks.c:2330:13:uxTaskGetNumberOfTasks	8	static
+tasks.c:2338:7:pcTaskGetName	24	static,ignoring_inline_asm
+tasks.c:2352:16:prvSearchForNameWithinSingleList	56	static
+tasks.c:2420:15:xTaskGetHandle	24	static,ignoring_inline_asm
+tasks.c:2485:14:uxTaskGetSystemState	32	static
+tasks.c:2576:7:vTaskStepTick	16	static,ignoring_inline_asm
+tasks.c:2591:13:xTaskAbortDelay	24	static,ignoring_inline_asm
+tasks.c:2665:12:xTaskIncrementTick	32	static,ignoring_inline_asm
+tasks.c:2947:6:vTaskSwitchContext	16	static,ignoring_inline_asm
+tasks.c:3020:6:vTaskPlaceOnEventList	16	static,ignoring_inline_asm
+tasks.c:3037:6:vTaskPlaceOnUnorderedEventList	24	static,ignoring_inline_asm
+tasks.c:3063:7:vTaskPlaceOnEventListRestricted	24	static,ignoring_inline_asm
+tasks.c:3094:12:xTaskRemoveFromEventList	24	static,ignoring_inline_asm
+tasks.c:3162:6:vTaskRemoveFromUnorderedEventList	24	static,ignoring_inline_asm
+tasks.c:3196:6:vTaskSetTimeOutState	16	static,ignoring_inline_asm
+tasks.c:3208:6:vTaskInternalSetTimeOutState	16	static
+tasks.c:3216:12:xTaskCheckForTimeOut	32	static,ignoring_inline_asm
+tasks.c:3279:6:vTaskMissedYield	8	static
+tasks.c:3287:14:uxTaskGetTaskNumber	24	static
+tasks.c:3310:7:vTaskSetTaskNumber	24	static
+tasks.c:3334:8:prvIdleTask	24	static,ignoring_inline_asm
+tasks.c:3453:19:eTaskConfirmSleepModeStatus	16	static
+tasks.c:3546:13:prvInitialiseTaskLists	16	static
+tasks.c:3578:13:prvCheckTasksWaitingTermination	16	static
+tasks.c:3609:7:vTaskGetInfo	32	static
+tasks.c:3705:21:prvListTasksWithinSingleList	48	static
+tasks.c:3738:32:prvTaskCheckFreeStackSpace	24	static
+tasks.c:3798:14:uxTaskGetStackHighWaterMark	32	static
+tasks.c:3826:14:prvDeleteTCB	16	static,ignoring_inline_asm
+tasks.c:3880:13:prvResetNextTaskUnblockTime	16	static
+tasks.c:3906:15:xTaskGetCurrentTaskHandle	16	static
+tasks.c:3923:13:xTaskGetSchedulerState	16	static
+tasks.c:3951:13:xTaskPriorityInherit	24	static
+tasks.c:4038:13:xTaskPriorityDisinherit	24	static,ignoring_inline_asm
+tasks.c:4118:7:vTaskPriorityDisinheritAfterTimeout	32	static,ignoring_inline_asm
+tasks.c:4533:12:uxTaskResetEventItemValue	16	static
+tasks.c:4549:15:pvTaskIncrementMutexHeldCount	8	static
+tasks.c:4566:11:ulTaskNotifyTake	24	static
+tasks.c:4634:13:xTaskNotifyWait	32	static
+tasks.c:4714:13:xTaskGenericNotify	40	static,ignoring_inline_asm
+tasks.c:4828:13:xTaskGenericNotifyFromISR	40	static,ignoring_inline_asm
+tasks.c:4957:7:vTaskNotifyGiveFromISR	32	static,ignoring_inline_asm
+tasks.c:5044:13:xTaskNotifyStateClear	24	static
+tasks.c:5081:13:prvAddCurrentTaskToDelayedList	24	static
diff --git a/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su
new file mode 100644
index 0000000..c32c525
--- /dev/null
+++ b/software/dumber3/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su
@@ -0,0 +1,26 @@
+timers.c:227:12:xTimerCreateTimerTask	48	static,ignoring_inline_asm
+timers.c:282:16:xTimerCreate	48	static
+timers.c:309:16:xTimerCreateStatic	48	static,ignoring_inline_asm
+timers.c:349:13:prvInitialiseNewTimer	24	static,ignoring_inline_asm
+timers.c:381:12:xTimerGenericCommand	56	static,ignoring_inline_asm
+timers.c:424:14:xTimerGetTimerDaemonTaskHandle	8	static,ignoring_inline_asm
+timers.c:433:12:xTimerGetPeriod	24	static,ignoring_inline_asm
+timers.c:442:6:vTimerSetReloadMode	24	static,ignoring_inline_asm
+timers.c:462:12:xTimerGetExpiryTime	24	static,ignoring_inline_asm
+timers.c:473:14:pcTimerGetName	24	static,ignoring_inline_asm
+timers.c:482:13:prvProcessExpiredTimer	32	static,ignoring_inline_asm
+timers.c:523:8:prvTimerTask	24	static
+timers.c:559:13:prvProcessTimerOrBlockTask	24	static
+timers.c:619:19:prvGetNextExpireTime	24	static
+timers.c:645:19:prvSampleTimeNow	24	static
+timers.c:668:19:prvInsertTimerInActiveList	32	static
+timers.c:709:13:prvProcessReceivedCommands	64	static,ignoring_inline_asm
+timers.c:857:13:prvSwitchTimerLists	40	static,ignoring_inline_asm
+timers.c:916:13:prvCheckForValidListAndQueue	16	static
+timers.c:967:12:xTimerIsTimerActive	24	static,ignoring_inline_asm
+timers.c:992:7:pvTimerGetTimerID	24	static,ignoring_inline_asm
+timers.c:1009:6:vTimerSetTimerID	24	static,ignoring_inline_asm
+timers.c:1025:13:xTimerPendFunctionCallFromISR	48	static
+timers.c:1049:13:xTimerPendFunctionCall	48	static,ignoring_inline_asm
+timers.c:1078:14:uxTimerGetTimerNumber	16	static
+timers.c:1088:7:vTimerSetTimerNumber	16	static
diff --git a/software/dumber3/Debug/makefile b/software/dumber3/Debug/makefile
new file mode 100644
index 0000000..5bc3254
--- /dev/null
+++ b/software/dumber3/Debug/makefile
@@ -0,0 +1,104 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
+-include Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+-include Core/Startup/subdir.mk
+-include Core/Src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(S_DEPS)),)
+-include $(S_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := Dumber3
+BUILD_ARTIFACT_EXTENSION := elf
+BUILD_ARTIFACT_PREFIX :=
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
+
+# Add inputs and outputs from these tool invocations to the build variables 
+EXECUTABLES += \
+Dumber3.elf \
+
+SIZE_OUTPUT += \
+default.size.stdout \
+
+OBJDUMP_LIST += \
+Dumber3.list \
+
+OBJCOPY_BIN += \
+Dumber3.bin \
+
+
+# All Target
+all: main-build
+
+# Main-build Target
+main-build: Dumber3.elf secondary-outputs
+
+# Tool invocations
+Dumber3.elf: $(OBJS) $(USER_OBJS) /home/dimercur/Travail/git/dumber/software/dumber3/STM32L010C6TX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-gcc -o "Dumber3.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0plus -T"/home/dimercur/Travail/git/dumber/software/dumber3/STM32L010C6TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="Dumber3.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-size  $(EXECUTABLES)
+	@echo 'Finished building: $@'
+	@echo ' '
+
+Dumber3.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objdump -h -S $(EXECUTABLES) > "Dumber3.list"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+Dumber3.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objcopy  -O binary $(EXECUTABLES) "Dumber3.bin"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) $(SIZE_OUTPUT)$(OBJDUMP_LIST)$(EXECUTABLES)$(OBJS)$(S_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(OBJCOPY_BIN) Dumber3.elf
+	-@echo ' '
+
+secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN)
+
+fail-specified-linker-script-missing:
+	@echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.'
+	@exit 2
+
+warn-no-linker-script-specified:
+	@echo 'Warning: No linker script specified. Check the linker settings in the build configuration.'
+
+.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified
+
+-include ../makefile.targets
diff --git a/software/dumber3/Debug/objects.list b/software/dumber3/Debug/objects.list
new file mode 100644
index 0000000..ee00853
--- /dev/null
+++ b/software/dumber3/Debug/objects.list
@@ -0,0 +1,45 @@
+"./Core/Src/batterie.o"
+"./Core/Src/freertos.o"
+"./Core/Src/leds.o"
+"./Core/Src/main.o"
+"./Core/Src/messages.o"
+"./Core/Src/moteurs.o"
+"./Core/Src/sequenceur.o"
+"./Core/Src/stm32l0xx_hal_msp.o"
+"./Core/Src/stm32l0xx_it.o"
+"./Core/Src/syscalls.o"
+"./Core/Src/sysmem.o"
+"./Core/Src/system_stm32l0xx.o"
+"./Core/Src/xbee.o"
+"./Core/Startup/startup_stm32l010c6tx.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o"
+"./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/croutine.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/list.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/queue.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/tasks.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/timers.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o"
diff --git a/software/dumber3/Debug/objects.mk b/software/dumber3/Debug/objects.mk
new file mode 100644
index 0000000..e12976d
--- /dev/null
+++ b/software/dumber3/Debug/objects.mk
@@ -0,0 +1,9 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/software/dumber3/Debug/sources.mk b/software/dumber3/Debug/sources.mk
new file mode 100644
index 0000000..1160961
--- /dev/null
+++ b/software/dumber3/Debug/sources.mk
@@ -0,0 +1,30 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+ELF_SRCS := 
+OBJ_SRCS := 
+S_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+O_SRCS := 
+SIZE_OUTPUT := 
+OBJDUMP_LIST := 
+EXECUTABLES := 
+OBJS := 
+S_DEPS := 
+S_UPPER_DEPS := 
+C_DEPS := 
+OBJCOPY_BIN := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Core/Src \
+Core/Startup \
+Drivers/STM32L0xx_HAL_Driver/Src \
+Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 \
+Middlewares/Third_Party/FreeRTOS/Source \
+Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0 \
+Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang \
+
diff --git a/software/dumber3/Dumber3 Debug.launch b/software/dumber3/Dumber3 Debug.launch
new file mode 100644
index 0000000..85840ce
--- /dev/null
+++ b/software/dumber3/Dumber3 Debug.launch	
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.access_port_id" value="0"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_live_expr" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
+    <intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.enabled" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.value" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{&quot;fItems&quot;:[{&quot;fIsFromMainTab&quot;:true,&quot;fPath&quot;:&quot;Debug/Dumber3.elf&quot;,&quot;fProjectName&quot;:&quot;Dumber3&quot;,&quot;fPerformBuild&quot;:true,&quot;fDownload&quot;:true,&quot;fLoadSymbols&quot;:true}]}"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.override_start_address_mode" value="default"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.divby0" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.unaligned" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.haltonexception" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.vector_table" value=""/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.verify_flash_download" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_allow_halt" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_signal_halt" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_external_loader" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_max_halt_delay" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader_init" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="0"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/home/dimercur/Travail/git/dumber/software/dumber3/Debug/st-link_gdbserver_log.txt"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="hardware_reset"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.watchdog_config" value="none"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkenable_rtos" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkrestart_configurations" value="{&quot;fItems&quot;:[{&quot;fDisplayName&quot;:&quot;Reset&quot;,&quot;fIsSuppressible&quot;:false,&quot;fResetAttribute&quot;:&quot;Software system reset&quot;,&quot;fResetStrategies&quot;:[{&quot;fDisplayName&quot;:&quot;Software system reset&quot;,&quot;fLaunchAttribute&quot;:&quot;system_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Hardware reset&quot;,&quot;fLaunchAttribute&quot;:&quot;hardware_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset hardware\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Core reset&quot;,&quot;fLaunchAttribute&quot;:&quot;core_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset core\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;None&quot;,&quot;fLaunchAttribute&quot;:&quot;no_reset&quot;,&quot;fGdbCommands&quot;:[],&quot;fCmdOptions&quot;:[&quot;-g&quot;]}],&quot;fGdbCommandGroup&quot;:{&quot;name&quot;:&quot;Additional commands&quot;,&quot;commands&quot;:[]}}]}"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.enableRtosProxy" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyCustomProperties" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriver" value="threadx"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverAuto" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverPort" value="cortex_m0"/>
+    <intAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyPort" value="60000"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="com.st.stm32cube.ide.mcu.debug.stlink"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/Dumber3.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="Dumber3"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1504381080"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/Dumber3"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;"/>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/software/dumber3/Dumber3.ioc b/software/dumber3/Dumber3.ioc
index f260514..35f5cab 100644
--- a/software/dumber3/Dumber3.ioc
+++ b/software/dumber3/Dumber3.ioc
@@ -1,5 +1,6 @@
 #MicroXplorer Configuration settings - do not modify
-ADC.IPParameters=SamplingTime
+ADC.IPParameters=SamplingTime,Resolution
+ADC.Resolution=ADC_RESOLUTION_8B
 ADC.SamplingTime=ADC_SAMPLETIME_160CYCLES_5
 Dma.LPUART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
 Dma.LPUART1_RX.0.Instance=DMA1_Channel3
@@ -27,9 +28,10 @@ FREERTOS.INCLUDE_xEventGroupSetBitFromISR=1
 FREERTOS.INCLUDE_xTaskAbortDelay=1
 FREERTOS.INCLUDE_xTaskGetCurrentTaskHandle=1
 FREERTOS.INCLUDE_xTaskGetHandle=1
-FREERTOS.IPParameters=Tasks01,configTICK_RATE_HZ,configUSE_TICKLESS_IDLE,INCLUDE_xTaskGetHandle,INCLUDE_xTaskAbortDelay,INCLUDE_xEventGroupSetBitFromISR,INCLUDE_pcTaskGetTaskName,INCLUDE_xTaskGetCurrentTaskHandle
+FREERTOS.IPParameters=Tasks01,configTICK_RATE_HZ,configUSE_TICKLESS_IDLE,INCLUDE_xTaskGetHandle,INCLUDE_xTaskAbortDelay,INCLUDE_xEventGroupSetBitFromISR,INCLUDE_pcTaskGetTaskName,INCLUDE_xTaskGetCurrentTaskHandle,configTOTAL_HEAP_SIZE
 FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
 FREERTOS.configTICK_RATE_HZ=100
+FREERTOS.configTOTAL_HEAP_SIZE=2048
 FREERTOS.configUSE_TICKLESS_IDLE=1
 File.Version=6
 GPIO.groupedBy=Group By Peripherals
@@ -85,7 +87,7 @@ MxCube.Version=6.3.0
 MxDb.Version=DB.6.0.30
 NVIC.ADC1_IRQn=true\:3\:0\:false\:false\:true\:true\:true\:true
 NVIC.DMA1_Channel2_3_IRQn=true\:3\:0\:false\:false\:true\:true\:false\:true
-NVIC.EXTI2_3_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.EXTI2_3_IRQn=true\:3\:0\:false\:false\:true\:false\:true\:true
 NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.LPUART1_IRQn=true\:3\:0\:false\:false\:true\:true\:true\:true
@@ -130,16 +132,19 @@ PB10.Mode=Asynchronous
 PB10.Signal=LPUART1_TX
 PB11.Mode=Asynchronous
 PB11.Signal=LPUART1_RX
-PB12.GPIOParameters=GPIO_Label
+PB12.GPIOParameters=GPIO_Speed,GPIO_Label
 PB12.GPIO_Label=LED_ROUGE
+PB12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
 PB12.Locked=true
 PB12.Signal=GPIO_Output
-PB13.GPIOParameters=GPIO_Label
+PB13.GPIOParameters=GPIO_Speed,GPIO_Label
 PB13.GPIO_Label=LED_ORANGE
+PB13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
 PB13.Locked=true
 PB13.Signal=GPIO_Output
-PB14.GPIOParameters=GPIO_Label
+PB14.GPIOParameters=GPIO_Speed,GPIO_Label
 PB14.GPIO_Label=LED_VERTE
+PB14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
 PB14.Signal=GPIO_Output
 PB15.GPIOParameters=GPIO_Label
 PB15.GPIO_Label=SHUTDOWN_ENCODERS
@@ -165,9 +170,10 @@ PB8.GPIOParameters=GPIO_Label
 PB8.GPIO_Label=SHUTDOWN_5V
 PB8.Locked=true
 PB8.Signal=GPIO_Output
-PB9.GPIOParameters=GPIO_Label
+PB9.GPIOParameters=PinState,GPIO_Label
 PB9.GPIO_Label=SHUTDOWN
 PB9.Locked=true
+PB9.PinState=GPIO_PIN_SET
 PB9.Signal=GPIO_Output
 PC0.GPIOParameters=GPIO_Label
 PC0.GPIO_Label=ENC_PHA_GAUCHE
@@ -202,31 +208,39 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=STM32CubeIDE
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_LPTIM1_Init-LPTIM1-false-HAL-true,5-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_TIM21_Init-TIM21-false-HAL-true
-RCC.AHBFreq_Value=2097000
-RCC.APB1Freq_Value=2097000
-RCC.APB1TimFreq_Value=2097000
-RCC.APB2Freq_Value=2097000
-RCC.APB2TimFreq_Value=2097000
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_LPTIM1_Init-LPTIM1-false-HAL-true,5-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_TIM21_Init-TIM21-false-HAL-true,8-MX_ADC_Init-ADC-false-HAL-true
+RCC.ADCFreq_Value=4000000
+RCC.AHBFreq_Value=6000000
+RCC.APB1Freq_Value=6000000
+RCC.APB1TimFreq_Value=6000000
+RCC.APB2Freq_Value=6000000
+RCC.APB2TimFreq_Value=6000000
+RCC.FCLKCortexFreq_Value=6000000
 RCC.FamilyName=M
+RCC.HCLKFreq_Value=6000000
 RCC.HSE_VALUE=8000000
 RCC.HSI16_VALUE=16000000
-RCC.HSI_VALUE=16000000
-RCC.I2C1Freq_Value=2097000
-RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FamilyName,HSE_VALUE,HSI16_VALUE,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSE_VALUE,LSI_VALUE,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,TIMFreq_Value,USART2Freq_Value,VCOOutputFreq_Value,WatchDogFreq_Value
-RCC.LPTIMFreq_Value=2097000
-RCC.LPUARTFreq_Value=2097000
+RCC.HSIRCDiv=4
+RCC.HSI_VALUE=4000000
+RCC.I2C1Freq_Value=6000000
+RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI16_VALUE,HSIRCDiv,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSE_VALUE,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,WatchDogFreq_Value
+RCC.LPTIMFreq_Value=6000000
+RCC.LPUARTFreq_Value=6000000
 RCC.LSE_VALUE=32768
 RCC.LSI_VALUE=37000
+RCC.MCOPinFreq_Value=6000000
 RCC.MSI_VALUE=2097000
-RCC.PLLCLKFreq_Value=24000000
-RCC.PWRFreq_Value=2097000
+RCC.PLLCLKFreq_Value=6000000
+RCC.PWRFreq_Value=6000000
 RCC.RTCFreq_Value=37000
 RCC.RTCHSEDivFreq_Value=4000000
-RCC.SYSCLKFreq_VALUE=2097000
-RCC.TIMFreq_Value=2097000
-RCC.USART2Freq_Value=2097000
-RCC.VCOOutputFreq_Value=48000000
+RCC.SYSCLKFreq_VALUE=6000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TIMFreq_Value=6000000
+RCC.TimerFreq_Value=6000000
+RCC.USART2Freq_Value=6000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=12000000
 RCC.WatchDogFreq_Value=37000
 SH.GPXTI3.0=GPIO_EXTI3
 SH.GPXTI3.ConfNb=1
@@ -248,7 +262,8 @@ TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
 TIM2.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
 TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
 TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
-TIM2.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4
+TIM2.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4,Period
+TIM2.Period=255
 VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
 VP_SYS_VS_Systick.Mode=SysTick