From f81610a89a62d3937db336c749da2a688b35fd1e Mon Sep 17 00:00:00 2001 From: alejeune Date: Fri, 21 Oct 2022 17:04:57 +0200 Subject: [PATCH 1/5] =?UTF-8?q?D=C3=A9but=20de=20la=20config=20du=20platea?= =?UTF-8?q?u?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- FileInclude/Plateau.c | 23 +++ FileInclude/Plateau.h | 7 + FileInclude/Telecommande.c | 0 FileInclude/Telecommande.h | 0 Listings/Projet1_Simulation.map | 176 ++++++++++++----------- Objects/Projet1_SImulation.dep | 57 +++++--- Objects/Projet1_Simulation.axf | Bin 231060 -> 232724 bytes Objects/Projet1_Simulation.build_log.htm | 27 ++-- Objects/Projet1_Simulation.htm | 14 +- Objects/Projet1_Simulation.lnp | 4 +- Objects/driver_gpio.crf | Bin 238776 -> 238776 bytes Objects/driver_gpio.o | Bin 260664 -> 260664 bytes Objects/main.crf | Bin 0 -> 239465 bytes Objects/main.d | 12 ++ Objects/{prinicpal.o => main.o} | Bin 258576 -> 258424 bytes Objects/myadc.crf | Bin 239353 -> 239520 bytes Objects/myadc.o | Bin 258608 -> 258596 bytes Objects/mytimer.crf | Bin 242217 -> 242626 bytes Objects/mytimer.o | Bin 269868 -> 272596 bytes Objects/plateau.crf | Bin 0 -> 239450 bytes Objects/plateau.d | 12 ++ Objects/plateau.o | Bin 0 -> 256696 bytes Objects/prinicpal.d | 12 -- Objects/system_stm32f10x.crf | Bin 239297 -> 239297 bytes Objects/system_stm32f10x.o | Bin 258552 -> 258552 bytes Objects/telecommande.crf | Bin 0 -> 18 bytes Objects/telecommande.d | 1 + Objects/telecommande.o | Bin 0 -> 4560 bytes Projet1.uvguix.alejeune | 127 ++++++++-------- Projet1.uvoptx | 54 ++++++- Projet1.uvprojx | 48 ++++++- 31 files changed, 368 insertions(+), 206 deletions(-) create mode 100644 FileInclude/Plateau.c create mode 100644 FileInclude/Plateau.h create mode 100644 FileInclude/Telecommande.c create mode 100644 FileInclude/Telecommande.h create mode 100644 Objects/main.crf create mode 100644 Objects/main.d rename Objects/{prinicpal.o => main.o} (93%) create mode 100644 Objects/plateau.crf create mode 100644 Objects/plateau.d create mode 100644 Objects/plateau.o create mode 100644 Objects/telecommande.crf create mode 100644 Objects/telecommande.d create mode 100644 Objects/telecommande.o diff --git a/FileInclude/Plateau.c b/FileInclude/Plateau.c new file mode 100644 index 0000000..bdd64cc --- /dev/null +++ b/FileInclude/Plateau.c @@ -0,0 +1,23 @@ +#include "MyTimer.h" +#include "stm32f10x.h" +#include "Driver_GPIO.h" +#include "Plateau.h" + +/* Permet de diriger le plateau du voilier */ +void Set_Moteur_Plateau(char sens, char vitesse){ // -1 gauche et 1 droite + /* Declarations */ + MyTimer_Struct_TypeDef TIM; + MyGPIO_Struct_TypeDef GPI0A5; // pin direction + MyGPIO_Struct_TypeDef GPIOA6; // pin moteur + + /* Configuration du Timer */ + MyTimer_Struct_TypeDef * Data = &TIM; + Data->Timer = TIM3; + Data->ARR = 65535; + Data->PSC = 548; + + Set_Duty_Cycle(Data->Timer, 1, Get_Max_Duty(Data->Timer)*vitesse); + MyTimer_Base_Init(Data); + + +} \ No newline at end of file diff --git a/FileInclude/Plateau.h b/FileInclude/Plateau.h new file mode 100644 index 0000000..6ccc648 --- /dev/null +++ b/FileInclude/Plateau.h @@ -0,0 +1,7 @@ +#ifndef MYPLATEAU_H +#define MYPLATEAU_H +#include "stm32f10x.h" + +void Set_Moteur_Plateau(char sens, char vitesse); // -1 gauche et 1 droite + +#endif \ No newline at end of file diff --git a/FileInclude/Telecommande.c b/FileInclude/Telecommande.c new file mode 100644 index 0000000..e69de29 diff --git a/FileInclude/Telecommande.h b/FileInclude/Telecommande.h new file mode 100644 index 0000000..e69de29 diff --git a/Listings/Projet1_Simulation.map b/Listings/Projet1_Simulation.map index 61228a5..824d2e4 100644 --- a/Listings/Projet1_Simulation.map +++ b/Listings/Projet1_Simulation.map @@ -4,20 +4,23 @@ Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601] Section Cross References - prinicpal.o(i.Callback) refers to myadc.o(i.startADC) for startADC - prinicpal.o(i.Callback) refers to myadc.o(i.read) for read - prinicpal.o(i.Callback) refers to prinicpal.o(.data) for a - prinicpal.o(i.main) refers to mytimer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init - prinicpal.o(i.main) refers to myadc.o(i.initADC) for initADC - prinicpal.o(i.main) refers to mytimer.o(i.MyTimer_ActiveIT) for MyTimer_ActiveIT - prinicpal.o(i.main) refers to mytimer.o(i.MyTimer_Base_Start) for MyTimer_Base_Start - prinicpal.o(i.main) refers to prinicpal.o(i.Callback) for Callback + main.o(i.Callback) refers to myadc.o(i.startADC) for startADC + main.o(i.Callback) refers to myadc.o(i.read) for read + main.o(i.Callback) refers to main.o(.data) for a + main.o(i.main) refers to mytimer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init + main.o(i.main) refers to myadc.o(i.initADC) for initADC + main.o(i.main) refers to mytimer.o(i.MyTimer_ActiveIT) for MyTimer_ActiveIT + main.o(i.main) refers to mytimer.o(i.MyTimer_Base_Start) for MyTimer_Base_Start + main.o(i.main) refers to main.o(i.Callback) for Callback mytimer.o(i.MyTimer_ActiveIT) refers to mytimer.o(.data) for ptr1 mytimer.o(i.MyTimer_PWM) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(.data) for ptr1 mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(.data) for ptr2 mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(.data) for ptr3 mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(.data) for ptr4 + plateau.o(i.Set_Moteur_Plateau) refers to mytimer.o(i.Get_Max_Duty) for Get_Max_Duty + plateau.o(i.Set_Moteur_Plateau) refers to mytimer.o(i.Set_Duty_Cycle) for Set_Duty_Cycle + plateau.o(i.Set_Moteur_Plateau) refers to mytimer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler @@ -42,8 +45,8 @@ Section Cross References entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_md.o(STACK) for __initial_sp entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload - entry9a.o(.ARM.Collect$$$$0000000B) refers to prinicpal.o(i.main) for main - entry9b.o(.ARM.Collect$$$$0000000C) refers to prinicpal.o(i.main) for main + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload @@ -51,9 +54,9 @@ Section Cross References Removing Unused input sections from the image. - Removing prinicpal.o(.rev16_text), (4 bytes). - Removing prinicpal.o(.revsh_text), (4 bytes). - Removing prinicpal.o(.rrx_text), (6 bytes). + Removing main.o(.rev16_text), (4 bytes). + Removing main.o(.revsh_text), (4 bytes). + Removing main.o(.rrx_text), (6 bytes). Removing driver_gpio.o(.rev16_text), (4 bytes). Removing driver_gpio.o(.revsh_text), (4 bytes). Removing driver_gpio.o(.rrx_text), (6 bytes). @@ -65,12 +68,18 @@ Removing Unused input sections from the image. Removing mytimer.o(.rev16_text), (4 bytes). Removing mytimer.o(.revsh_text), (4 bytes). Removing mytimer.o(.rrx_text), (6 bytes). + Removing mytimer.o(i.Get_Max_Duty), (6 bytes). Removing mytimer.o(i.MyTimer_Base_Stop), (10 bytes). Removing mytimer.o(i.MyTimer_PWM), (464 bytes). + Removing mytimer.o(i.Set_Duty_Cycle), (40 bytes). Removing mytimer.o(i.Set_PWM_PRCT), (56 bytes). Removing myadc.o(.rev16_text), (4 bytes). Removing myadc.o(.revsh_text), (4 bytes). Removing myadc.o(.rrx_text), (6 bytes). + Removing plateau.o(.rev16_text), (4 bytes). + Removing plateau.o(.revsh_text), (4 bytes). + Removing plateau.o(.rrx_text), (6 bytes). + Removing plateau.o(i.Set_Moteur_Plateau), (60 bytes). Removing startup_stm32f10x_md.o(HEAP), (512 bytes). Removing system_stm32f10x.o(.rev16_text), (4 bytes). Removing system_stm32f10x.o(.revsh_text), (4 bytes). @@ -78,7 +87,7 @@ Removing Unused input sections from the image. Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes). Removing system_stm32f10x.o(.data), (20 bytes). -26 unused section(s) (total 1526 bytes) removed from the image. +32 unused section(s) (total 1646 bytes) removed from the image. ============================================================================== @@ -88,30 +97,33 @@ Image Symbol Table Symbol Name Value Ov Type Size Object(Section) - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE FileInclude\MyADC.c 0x00000000 Number 0 myadc.o ABSOLUTE FileInclude\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE + FileInclude\Plateau.c 0x00000000 Number 0 plateau.o ABSOLUTE + FileInclude\Telecommande.c 0x00000000 Number 0 telecommande.o ABSOLUTE FileInclude\\MyADC.c 0x00000000 Number 0 myadc.o ABSOLUTE FileInclude\\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE + FileInclude\\Plateau.c 0x00000000 Number 0 plateau.o ABSOLUTE RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE - Sources\\prinicpal.c 0x00000000 Number 0 prinicpal.o ABSOLUTE - Sources\prinicpal.c 0x00000000 Number 0 prinicpal.o ABSOLUTE + Sources\\main.c 0x00000000 Number 0 main.o ABSOLUTE + Sources\main.c 0x00000000 Number 0 main.o ABSOLUTE U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE U:\\Documents\\4ir\\S1\\Microcontroleur\\Drivers\\FileInclude\\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE dc.s 0x00000000 Number 0 dc.o ABSOLUTE @@ -131,7 +143,7 @@ Image Symbol Table __lit__00000000 0x08000100 Data 4 entry2.o(.ARM.Collect$$$$00002712) .text 0x08000104 Section 36 startup_stm32f10x_md.o(.text) .text 0x08000128 Section 36 init.o(.text) - i.Callback 0x0800014c Section 0 prinicpal.o(i.Callback) + i.Callback 0x0800014c Section 0 main.o(i.Callback) i.MyTimer_ActiveIT 0x08000160 Section 0 mytimer.o(i.MyTimer_ActiveIT) i.MyTimer_Base_Init 0x08000210 Section 0 mytimer.o(i.MyTimer_Base_Init) i.MyTimer_Base_Start 0x0800027c Section 0 mytimer.o(i.MyTimer_Base_Start) @@ -148,10 +160,10 @@ Image Symbol Table i.__scatterload_null 0x0800046e Section 2 handlers.o(i.__scatterload_null) i.__scatterload_zeroinit 0x08000470 Section 14 handlers.o(i.__scatterload_zeroinit) i.initADC 0x08000480 Section 0 myadc.o(i.initADC) - i.main 0x080004bc Section 0 prinicpal.o(i.main) + i.main 0x080004bc Section 0 main.o(i.main) i.read 0x080004f8 Section 0 myadc.o(i.read) - i.startADC 0x08000520 Section 0 myadc.o(i.startADC) - .data 0x20000000 Section 4 prinicpal.o(.data) + i.startADC 0x08000518 Section 0 myadc.o(i.startADC) + .data 0x20000000 Section 4 main.o(.data) .data 0x20000004 Section 16 mytimer.o(.data) STACK 0x20000018 Section 1024 startup_stm32f10x_md.o(STACK) @@ -160,7 +172,7 @@ Image Symbol Table Symbol Name Value Ov Type Size Object(Section) BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE - __ARM_use_no_argv 0x00000000 Number 0 prinicpal.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE __arm_fini_ - Undefined Weak Reference __cpp_initialize__aeabi_ - Undefined Weak Reference __cxa_finalize - Undefined Weak Reference @@ -231,7 +243,7 @@ Image Symbol Table WWDG_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) __scatterload 0x08000129 Thumb Code 28 init.o(.text) __scatterload_rt2 0x08000129 Thumb Code 0 init.o(.text) - Callback 0x0800014d Thumb Code 16 prinicpal.o(i.Callback) + Callback 0x0800014d Thumb Code 16 main.o(i.Callback) MyTimer_ActiveIT 0x08000161 Thumb Code 148 mytimer.o(i.MyTimer_ActiveIT) MyTimer_Base_Init 0x08000211 Thumb Code 98 mytimer.o(i.MyTimer_Base_Init) MyTimer_Base_Start 0x0800027d Thumb Code 10 mytimer.o(i.MyTimer_Base_Start) @@ -244,12 +256,12 @@ Image Symbol Table __scatterload_null 0x0800046f Thumb Code 2 handlers.o(i.__scatterload_null) __scatterload_zeroinit 0x08000471 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) initADC 0x08000481 Thumb Code 50 myadc.o(i.initADC) - main 0x080004bd Thumb Code 56 prinicpal.o(i.main) - read 0x080004f9 Thumb Code 36 myadc.o(i.read) - startADC 0x08000521 Thumb Code 14 myadc.o(i.startADC) - Region$$Table$$Base 0x08000534 Number 0 anon$$obj.o(Region$$Table) - Region$$Table$$Limit 0x08000554 Number 0 anon$$obj.o(Region$$Table) - a 0x20000000 Data 4 prinicpal.o(.data) + main 0x080004bd Thumb Code 56 main.o(i.main) + read 0x080004f9 Thumb Code 26 myadc.o(i.read) + startADC 0x08000519 Thumb Code 14 myadc.o(i.startADC) + Region$$Table$$Base 0x0800052c Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0800054c Number 0 anon$$obj.o(Region$$Table) + a 0x20000000 Data 4 main.o(.data) ptr1 0x20000004 Data 4 mytimer.o(.data) ptr2 0x20000008 Data 4 mytimer.o(.data) ptr3 0x2000000c Data 4 mytimer.o(.data) @@ -264,62 +276,62 @@ Memory Map of the image Image Entry point : 0x08000105 - Load Region LR_1 (Base: 0x08000000, Size: 0x00000568, Max: 0xffffffff, ABSOLUTE) + Load Region LR_1 (Base: 0x08000000, Size: 0x00000560, Max: 0xffffffff, ABSOLUTE) - Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000554, Max: 0xffffffff, ABSOLUTE) + Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000054c, Max: 0xffffffff, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object - 0x08000000 0x08000000 0x000000ec Data RO 251 RESET startup_stm32f10x_md.o - 0x080000ec 0x080000ec 0x00000000 Code RO 302 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) - 0x080000ec 0x080000ec 0x00000004 Code RO 305 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) - 0x080000f0 0x080000f0 0x00000004 Code RO 308 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) - 0x080000f4 0x080000f4 0x00000000 Code RO 310 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) - 0x080000f4 0x080000f4 0x00000000 Code RO 312 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) - 0x080000f4 0x080000f4 0x00000008 Code RO 313 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) - 0x080000fc 0x080000fc 0x00000004 Code RO 320 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o) - 0x08000100 0x08000100 0x00000000 Code RO 315 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o) - 0x08000100 0x08000100 0x00000000 Code RO 317 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o) - 0x08000100 0x08000100 0x00000004 Code RO 306 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) - 0x08000104 0x08000104 0x00000024 Code RO 252 * .text startup_stm32f10x_md.o - 0x08000128 0x08000128 0x00000024 Code RO 321 .text mc_w.l(init.o) - 0x0800014c 0x0800014c 0x00000014 Code RO 4 i.Callback prinicpal.o - 0x08000160 0x08000160 0x000000b0 Code RO 126 i.MyTimer_ActiveIT mytimer.o - 0x08000210 0x08000210 0x0000006c Code RO 127 i.MyTimer_Base_Init mytimer.o - 0x0800027c 0x0800027c 0x0000000a Code RO 128 i.MyTimer_Base_Start mytimer.o - 0x08000286 0x08000286 0x00000008 Code RO 259 i.SetSysClock system_stm32f10x.o + 0x08000000 0x08000000 0x000000ec Data RO 293 RESET startup_stm32f10x_md.o + 0x080000ec 0x080000ec 0x00000000 Code RO 344 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x080000ec 0x080000ec 0x00000004 Code RO 347 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x080000f0 0x080000f0 0x00000004 Code RO 350 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x080000f4 0x080000f4 0x00000000 Code RO 352 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x080000f4 0x080000f4 0x00000000 Code RO 354 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x080000f4 0x080000f4 0x00000008 Code RO 355 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x080000fc 0x080000fc 0x00000004 Code RO 362 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o) + 0x08000100 0x08000100 0x00000000 Code RO 357 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o) + 0x08000100 0x08000100 0x00000000 Code RO 359 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o) + 0x08000100 0x08000100 0x00000004 Code RO 348 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x08000104 0x08000104 0x00000024 Code RO 294 * .text startup_stm32f10x_md.o + 0x08000128 0x08000128 0x00000024 Code RO 363 .text mc_w.l(init.o) + 0x0800014c 0x0800014c 0x00000014 Code RO 4 i.Callback main.o + 0x08000160 0x08000160 0x000000b0 Code RO 127 i.MyTimer_ActiveIT mytimer.o + 0x08000210 0x08000210 0x0000006c Code RO 128 i.MyTimer_Base_Init mytimer.o + 0x0800027c 0x0800027c 0x0000000a Code RO 129 i.MyTimer_Base_Start mytimer.o + 0x08000286 0x08000286 0x00000008 Code RO 301 i.SetSysClock system_stm32f10x.o 0x0800028e 0x0800028e 0x00000002 PAD - 0x08000290 0x08000290 0x000000e0 Code RO 260 i.SetSysClockTo72 system_stm32f10x.o - 0x08000370 0x08000370 0x00000060 Code RO 262 i.SystemInit system_stm32f10x.o - 0x080003d0 0x080003d0 0x00000024 Code RO 132 i.TIM1_UP_IRQHandler mytimer.o - 0x080003f4 0x080003f4 0x00000024 Code RO 133 i.TIM2_IRQHandler mytimer.o - 0x08000418 0x08000418 0x00000024 Code RO 134 i.TIM3_IRQHandler mytimer.o - 0x0800043c 0x0800043c 0x00000024 Code RO 135 i.TIM4_IRQHandler mytimer.o - 0x08000460 0x08000460 0x0000000e Code RO 325 i.__scatterload_copy mc_w.l(handlers.o) - 0x0800046e 0x0800046e 0x00000002 Code RO 326 i.__scatterload_null mc_w.l(handlers.o) - 0x08000470 0x08000470 0x0000000e Code RO 327 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x08000290 0x08000290 0x000000e0 Code RO 302 i.SetSysClockTo72 system_stm32f10x.o + 0x08000370 0x08000370 0x00000060 Code RO 304 i.SystemInit system_stm32f10x.o + 0x080003d0 0x080003d0 0x00000024 Code RO 134 i.TIM1_UP_IRQHandler mytimer.o + 0x080003f4 0x080003f4 0x00000024 Code RO 135 i.TIM2_IRQHandler mytimer.o + 0x08000418 0x08000418 0x00000024 Code RO 136 i.TIM3_IRQHandler mytimer.o + 0x0800043c 0x0800043c 0x00000024 Code RO 137 i.TIM4_IRQHandler mytimer.o + 0x08000460 0x08000460 0x0000000e Code RO 367 i.__scatterload_copy mc_w.l(handlers.o) + 0x0800046e 0x0800046e 0x00000002 Code RO 368 i.__scatterload_null mc_w.l(handlers.o) + 0x08000470 0x08000470 0x0000000e Code RO 369 i.__scatterload_zeroinit mc_w.l(handlers.o) 0x0800047e 0x0800047e 0x00000002 PAD - 0x08000480 0x08000480 0x0000003c Code RO 213 i.initADC myadc.o - 0x080004bc 0x080004bc 0x0000003c Code RO 5 i.main prinicpal.o - 0x080004f8 0x080004f8 0x00000028 Code RO 214 i.read myadc.o - 0x08000520 0x08000520 0x00000014 Code RO 215 i.startADC myadc.o - 0x08000534 0x08000534 0x00000020 Data RO 323 Region$$Table anon$$obj.o + 0x08000480 0x08000480 0x0000003c Code RO 225 i.initADC myadc.o + 0x080004bc 0x080004bc 0x0000003c Code RO 5 i.main main.o + 0x080004f8 0x080004f8 0x00000020 Code RO 226 i.read myadc.o + 0x08000518 0x08000518 0x00000014 Code RO 227 i.startADC myadc.o + 0x0800052c 0x0800052c 0x00000020 Data RO 365 Region$$Table anon$$obj.o - Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000554, Size: 0x00000014, Max: 0xffffffff, ABSOLUTE) + Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x0800054c, Size: 0x00000014, Max: 0xffffffff, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object - 0x20000000 0x08000554 0x00000004 Data RW 6 .data prinicpal.o - 0x20000004 0x08000558 0x00000010 Data RW 136 .data mytimer.o + 0x20000000 0x0800054c 0x00000004 Data RW 6 .data main.o + 0x20000004 0x08000550 0x00000010 Data RW 138 .data mytimer.o - Execution Region ER_ZI (Exec base: 0x20000014, Load base: 0x08000568, Size: 0x00000404, Max: 0xffffffff, ABSOLUTE) + Execution Region ER_ZI (Exec base: 0x20000014, Load base: 0x08000560, Size: 0x00000404, Max: 0xffffffff, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object - 0x20000014 0x08000568 0x00000004 PAD - 0x20000018 - 0x00000400 Zero RW 249 STACK startup_stm32f10x_md.o + 0x20000014 0x08000560 0x00000004 PAD + 0x20000018 - 0x00000400 Zero RW 291 STACK startup_stm32f10x_md.o ============================================================================== @@ -329,14 +341,14 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug Object Name - 120 20 0 0 0 1284 myadc.o + 80 8 0 4 0 208294 main.o + 112 22 0 0 0 1280 myadc.o 438 66 0 16 0 4557 mytimer.o - 80 8 0 4 0 208330 prinicpal.o 36 8 236 0 1024 808 startup_stm32f10x_md.o 328 28 0 0 0 1973 system_stm32f10x.o ---------------------------------------------------------------------- - 1004 130 268 20 1028 216952 Object Totals + 996 132 268 20 1028 216912 Object Totals 0 0 32 0 0 0 (incl. Generated) 2 0 0 0 4 0 (incl. Padding) @@ -376,15 +388,15 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug - 1096 146 268 20 1028 216548 Grand Totals - 1096 146 268 20 1028 216548 ELF Image Totals - 1096 146 268 20 0 0 ROM Totals + 1088 148 268 20 1028 216508 Grand Totals + 1088 148 268 20 1028 216508 ELF Image Totals + 1088 148 268 20 0 0 ROM Totals ============================================================================== - Total RO Size (Code + RO Data) 1364 ( 1.33kB) + Total RO Size (Code + RO Data) 1356 ( 1.32kB) Total RW Size (RW Data + ZI Data) 1048 ( 1.02kB) - Total ROM Size (Code + RO Data + RW Data) 1384 ( 1.35kB) + Total ROM Size (Code + RO Data + RW Data) 1376 ( 1.34kB) ============================================================================== diff --git a/Objects/Projet1_SImulation.dep b/Objects/Projet1_SImulation.dep index 1351e48..70ab3f3 100644 --- a/Objects/Projet1_SImulation.dep +++ b/Objects/Projet1_SImulation.dep @@ -1,57 +1,72 @@ Dependencies for Project 'Projet1', Target 'SImulation': (DO NOT MODIFY !) CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC -F (.\Sources\prinicpal.c)(0x63495DAA)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\prinicpal.o --omf_browse .\objects\prinicpal.crf --depend .\objects\prinicpal.d) +F (.\Sources\main.c)(0x6352ACB6)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_SImulation\RTE_Components.h)(0x63284DB0) +I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -I (.\FileInclude\Driver_GPIO.h)(0x63315001) -I (.\FileInclude\MyTimer.h)(0x6340244A) -I (.\FileInclude\MyADC.h)(0x63495643) +I (.\FileInclude\Driver_GPIO.h)(0x6352AB58) +I (.\FileInclude\MyTimer.h)(0x6352ACB6) +I (.\FileInclude\MyADC.h)(0x6352AB58) F (U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c)(0x633153E6)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d) I (U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.h)(0x63315001) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_SImulation\RTE_Components.h)(0x63284DB0) +I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -F (.\FileInclude\MyTimer.c)(0x63402350)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d) -I (FileInclude\MyTimer.h)(0x6340244A) +F (.\FileInclude\MyTimer.c)(0x6352ACB6)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d) +I (FileInclude\MyTimer.h)(0x6352ACB6) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_SImulation\RTE_Components.h)(0x63284DB0) +I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -I (FileInclude\Driver_GPIO.h)(0x63315001) -F (.\FileInclude\MyTimer.h)(0x6340244A)() -F (.\FileInclude\MyADC.c)(0x63495C37)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\myadc.o --omf_browse .\objects\myadc.crf --depend .\objects\myadc.d) -I (FileInclude\MyADC.h)(0x63495643) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +F (.\FileInclude\MyTimer.h)(0x6352ACB6)() +F (.\FileInclude\MyADC.c)(0x6352AB58)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\myadc.o --omf_browse .\objects\myadc.crf --depend .\objects\myadc.d) +I (FileInclude\MyADC.h)(0x6352AB58) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_SImulation\RTE_Components.h)(0x63284DB0) +I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -I (FileInclude\MyTimer.h)(0x6340244A) -I (FileInclude\Driver_GPIO.h)(0x63315001) -F (.\FileInclude\MyADC.h)(0x63495643)() -F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59283406)() -F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58258CCC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d) -F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58258CCC)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d) +I (FileInclude\MyTimer.h)(0x6352ACB6) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +F (.\FileInclude\MyADC.h)(0x6352AB58)() +F (.\FileInclude\Plateau.c)(0x6352B4DB)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\plateau.o --omf_browse .\objects\plateau.crf --depend .\objects\plateau.d) +I (FileInclude\MyTimer.h)(0x6352ACB6) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_SImulation\RTE_Components.h)(0x63284DB0) +I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +I (FileInclude\Plateau.h)(0x6352B148) +F (.\FileInclude\Telecommande.c)(0x6352ADB2)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\telecommande.o --omf_browse .\objects\telecommande.crf --depend .\objects\telecommande.d) +F (.\FileInclude\Plateau.h)(0x6352B148)() +F (.\FileInclude\Telecommande.h)(0x6352ADB2)() +F (RTE\Device\STM32F103RB\RTE_Device.h)(0x6352AB59)() +F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x6352AB59)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d) +F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x6352AB59)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) +I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) diff --git a/Objects/Projet1_Simulation.axf b/Objects/Projet1_Simulation.axf index 7c66e8ea6d28842f27976c7601ed474ebcee6d27..14307a0fc443f865fa7397d53c54d11aad10e43f 100644 GIT binary patch delta 4146 zcmZ{ne^8Xi8OL|uy*mygcz~Kij2wuHW1t+8R!mg<$w1JNgMw9}oX08Z@%tD{OLDX# zr1>$Cz9eswnT$!x7;9Ra%;}ty&}p1#+8NsndT3UO;Qi54nU@ywgY-@EBEJ{GO4^wKQ4swU&tT~*F( z+kKN!e#v>doo0t9kLunk_oAZ+iGQcQYBQs`F>R!C`v!m5&s+`57`ub?p^Q%%G`)s1 zXA^2C23|9+&#hjN&5pwiQ$evg>pFV71HqmqGmEv=Lo;+{C!L40=;i8b8Y2Gv=G8OZ z4sK7)a%9;xN0FYhWuuekZP!Gm-n!*6UL1XYOSLU!9Q_1~>Q}3G=-qYh_{!*YYoZtH za9 zsu>ghGy1%ZTG!VT4z^Xb@1qUC*!`#)yY&smuHfzsRCA@#vK&;6T{eDMD;DrEn)caT_bB`P|s)6NUVgG3*nI`8nex(U|ckpIE|2jk`YaP~~^a8M}e; zj-i^1gw}G9y^4jjAwXuo2rMRPICxJlMRcOcYTqSq|-7w~{ z;UW-EwTbZy^*0p$RNR6JJvLUsqV*EJ+kw1P&L- z0&or3jR+}Bfj?hd@4RL?+y=HGV+9uPRQf-y@M-Xnl)?AF!(f^L=Fi!O5FC*V{sJBW zUxESYC%~OjioXUY3T13Qo_Pe9%*aFW^T9MBy=uSGvd8=)W(w=517-w)$svh36zTx| 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Project:

U:\Documents\4ir\S1\Microcontroleur\TP_Voilier\Projet1.uvprojx -Project File Date: 10/14/2022 +Project File Date: 10/21/2022

Output:

*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin' Rebuild target 'SImulation' assembling startup_stm32f10x_md.s... -compiling Driver_GPIO.c... -compiling system_stm32f10x.c... -compiling MyTimer.c... -compiling prinicpal.c... +compiling Telecommande.c... +compiling main.c... compiling MyADC.c... +compiling Driver_GPIO.c... +compiling MyTimer.c... +compiling Plateau.c... +FileInclude\Plateau.h(7): warning: #1-D: last line of file ends without a newline + #endif +FileInclude\Plateau.c(23): warning: #1-D: last line of file ends without a newline + } +FileInclude\Plateau.c(10): warning: #177-D: variable "GPI0A5" was declared but never referenced + MyGPIO_Struct_TypeDef GPI0A5; // pin direction +FileInclude\Plateau.c(11): warning: #177-D: variable "GPIOA6" was declared but never referenced + MyGPIO_Struct_TypeDef GPIOA6; // pin moteur +FileInclude\Plateau.c: 4 warnings, 0 errors +compiling system_stm32f10x.c... linking... -Program Size: Code=1096 RO-data=268 RW-data=20 ZI-data=1028 -".\Objects\Projet1_Simulation.axf" - 0 Error(s), 0 Warning(s). +Program Size: Code=1088 RO-data=268 RW-data=20 ZI-data=1028 +".\Objects\Projet1_Simulation.axf" - 0 Error(s), 4 Warning(s).

Software Packages used:

@@ -62,10 +73,10 @@ Package Vendor: Keil * Component: ARM::CMSIS:CORE:5.4.0 * Component: Keil::Device:Startup:1.0.0 - Source file: Device\Source\ARM\STM32F1xx_OPT.s Source file: Device\Source\system_stm32f10x.c Include file: RTE_Driver\Config\RTE_Device.h Source file: Device\Source\ARM\startup_stm32f10x_md.s + Source file: Device\Source\ARM\STM32F1xx_OPT.s Build Time Elapsed: 00:00:02 diff --git a/Objects/Projet1_Simulation.htm b/Objects/Projet1_Simulation.htm index 29be12b..6c7780a 100644 --- a/Objects/Projet1_Simulation.htm +++ b/Objects/Projet1_Simulation.htm @@ -3,7 +3,7 @@ Static Call Graph - [.\Objects\Projet1_Simulation.axf]

Static Call Graph for image .\Objects\Projet1_Simulation.axf

-

#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Fri Oct 14 15:01:44 2022 +

#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Fri Oct 21 17:03:57 2022

Maximum Stack Usage = 28 bytes + Unknown(Cycles, Untraceable Function Pointers)

Call chain for Maximum Stack Depth:

@@ -30,7 +30,7 @@ Function Pointers
  • BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
  • Callback from prinicpal.o(i.Callback) referenced from prinicpal.o(i.main) +
  • Callback from main.o(i.Callback) referenced from main.o(i.main)
  • DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) @@ -82,7 +82,7 @@ Function Pointers
  • UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text) -
  • main from prinicpal.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B) +
  • main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)

    @@ -307,13 +307,13 @@ Global Symbols

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) -

    Callback (Thumb, 16 bytes, Stack size 8 bytes, prinicpal.o(i.Callback)) +

    Callback (Thumb, 16 bytes, Stack size 8 bytes, main.o(i.Callback))

    [Stack]

    • Max Depth = 8
    • Call Chain = Callback

    [Calls]
    • >>   startADC
    • >>   read
    -
    [Address Reference Count : 1]
    • prinicpal.o(i.main) +
      [Address Reference Count : 1]
      • main.o(i.main)

      MyTimer_ActiveIT (Thumb, 148 bytes, Stack size 8 bytes, mytimer.o(i.MyTimer_ActiveIT))

      [Stack]

      • Max Depth = 8
      • Call Chain = MyTimer_ActiveIT @@ -366,7 +366,7 @@ Global Symbols

        [Called By]
        • >>   main
        -

        main (Thumb, 56 bytes, Stack size 16 bytes, prinicpal.o(i.main)) +

        main (Thumb, 56 bytes, Stack size 16 bytes, main.o(i.main))

        [Stack]

        • Max Depth = 24
        • Call Chain = main ⇒ MyTimer_ActiveIT

        [Calls]
        • >>   initADC @@ -376,7 +376,7 @@ Global Symbols

        [Address Reference Count : 1]
        • entry9a.o(.ARM.Collect$$$$0000000B)
        -

        read (Thumb, 36 bytes, Stack size 0 bytes, myadc.o(i.read)) +

        read (Thumb, 26 bytes, Stack size 0 bytes, myadc.o(i.read))

        [Called By]

        • >>   Callback
        diff --git a/Objects/Projet1_Simulation.lnp b/Objects/Projet1_Simulation.lnp index f8455d5..f0dacfa 100644 --- a/Objects/Projet1_Simulation.lnp +++ b/Objects/Projet1_Simulation.lnp @@ -1,8 +1,10 @@ --cpu Cortex-M3 -".\objects\prinicpal.o" +".\objects\main.o" ".\objects\driver_gpio.o" ".\objects\mytimer.o" ".\objects\myadc.o" +".\objects\plateau.o" +".\objects\telecommande.o" ".\objects\startup_stm32f10x_md.o" ".\objects\system_stm32f10x.o" --library_type=microlib --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols diff --git a/Objects/driver_gpio.crf b/Objects/driver_gpio.crf index 3a8d96b64be3cdf12c7e931b01caa64af46eaea5..2be9dd338eee306ab28489bf48b2c98c325f9d88 100644 GIT binary patch delta 45 xcmdmSl5fXJz6r1RZ(ch!i;V#Yly62bF!@XlWO8b@W^A`+1YxG_){M-xivf|q4(R{@ delta 45 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583 @@ -1851,8 +1851,8 @@ 0 - 1920 - 1200 + 2048 + 1152 @@ -3604,36 +3604,27 @@ 100 7 - - .\Sources\prinicpal.c - 21 - 1 - 8 - 1 - - 0 - .\FileInclude\MyTimer.h - 0 + 41 1 - 33 + 39 1 0 .\FileInclude\MyTimer.c - 41 - 229 - 258 + 0 + 13 + 1 1 0 U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c - 38 + 42 1 25 1 @@ -3641,7 +3632,7 @@ 0 - RTE\Device\STM32F103RB\RTE_Device.h + .\FileInclude\Driver_GPIO.h 0 1 1 @@ -3649,24 +3640,6 @@ 0 - - RTE\Device\STM32F103RB\startup_stm32f10x_md.s - 0 - 122 - 133 - 1 - - 0 - - - .\FileInclude\Driver_GPIO.h - 26 - 1 - 19 - 1 - - 0 - .\FileInclude\MyADC.c 16 @@ -3678,9 +3651,27 @@ .\FileInclude\MyADC.h - 13 + 0 1 - 10 + 13 + 1 + + 0 + + + .\FileInclude\Plateau.h + 74 + 1 + 5 + 1 + + 0 + + + .\FileInclude\Plateau.c + 1 + 1 + 23 1 0 diff --git a/Projet1.uvoptx b/Projet1.uvoptx index 4c8f635..ca2c1c6 100644 --- a/Projet1.uvoptx +++ b/Projet1.uvoptx @@ -398,11 +398,11 @@ 1 1 1 - 1 + 0 0 0 - .\Sources\prinicpal.c - prinicpal.c + .\Sources\main.c + main.c 0 0 @@ -474,6 +474,54 @@ 0 0 + + 2 + 7 + 1 + 0 + 0 + 0 + .\FileInclude\Plateau.c + Plateau.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + .\FileInclude\Telecommande.c + Telecommande.c + 0 + 0 + + + 2 + 9 + 5 + 0 + 0 + 0 + .\FileInclude\Plateau.h + Plateau.h + 0 + 0 + + + 2 + 10 + 5 + 0 + 0 + 0 + .\FileInclude\Telecommande.h + Telecommande.h + 0 + 0 + diff --git a/Projet1.uvprojx b/Projet1.uvprojx index e678204..98937af 100644 --- a/Projet1.uvprojx +++ b/Projet1.uvprojx @@ -384,9 +384,9 @@ MesSources - prinicpal.c + main.c 1 - .\Sources\prinicpal.c + .\Sources\main.c @@ -418,6 +418,26 @@ 5 .\FileInclude\MyADC.h + + Plateau.c + 1 + .\FileInclude\Plateau.c + + + Telecommande.c + 1 + .\FileInclude\Telecommande.c + + + Plateau.h + 5 + .\FileInclude\Plateau.h + + + Telecommande.h + 5 + .\FileInclude\Telecommande.h + @@ -806,9 +826,9 @@ MesSources - prinicpal.c + main.c 1 - .\Sources\prinicpal.c + .\Sources\main.c @@ -840,6 +860,26 @@ 5 .\FileInclude\MyADC.h + + Plateau.c + 1 + .\FileInclude\Plateau.c + + + Telecommande.c + 1 + .\FileInclude\Telecommande.c + + + Plateau.h + 5 + .\FileInclude\Plateau.h + + + Telecommande.h + 5 + .\FileInclude\Telecommande.h + From f2db597d973a9b1049989f51570abec564f546fb Mon Sep 17 00:00:00 2001 From: alejeune Date: Fri, 21 Oct 2022 18:13:51 +0200 Subject: [PATCH 2/5] =?UTF-8?q?Avancement=20du=20d=C3=A9but=20de=20la=20co?= =?UTF-8?q?nfig=20du=20plateau?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- FileInclude/Plateau.c | 32 ++++++++++++++++++++++++++++---- Projet1.uvguix.alejeune | 34 +++++++++++++++++----------------- 2 files changed, 45 insertions(+), 21 deletions(-) diff --git a/FileInclude/Plateau.c b/FileInclude/Plateau.c index bdd64cc..4b448ec 100644 --- a/FileInclude/Plateau.c +++ b/FileInclude/Plateau.c @@ -3,21 +3,45 @@ #include "Driver_GPIO.h" #include "Plateau.h" + /* Permet de diriger le plateau du voilier */ void Set_Moteur_Plateau(char sens, char vitesse){ // -1 gauche et 1 droite /* Declarations */ + char channel; MyTimer_Struct_TypeDef TIM; - MyGPIO_Struct_TypeDef GPI0A5; // pin direction + MyGPIO_Struct_TypeDef GPIOA5; // pin direction MyGPIO_Struct_TypeDef GPIOA6; // pin moteur + channel =1; /* Configuration du Timer */ MyTimer_Struct_TypeDef * Data = &TIM; Data->Timer = TIM3; - Data->ARR = 65535; - Data->PSC = 548; + Data->ARR = 300; + Data->PSC = 11; // pas sur de la valeur car on veut 20kHz au max - Set_Duty_Cycle(Data->Timer, 1, Get_Max_Duty(Data->Timer)*vitesse); + Set_Duty_Cycle(Data->Timer, channel, Get_Max_Duty(Data->Timer)*vitesse); MyTimer_Base_Init(Data); + /* Configuration des GPIOs */ + GPIOA5.GPIO = GPIOA; + GPIOA5.GPIO_Pin = 5; + GPIOA5.GPIO_Conf = Out_Ppull; + + GPIOA6.GPIO = GPIOA; + GPIOA6.GPIO_Pin = 6; + GPIOA6.GPIO_Conf = AltOut_Ppull; + + MyTimer_Base_Start(TIM3); + MyTimer_PWM(Data->Timer,channel); + + /* Rotation */ + if (sens == 1){ + MyGPIO_Reset(GPIOA5.GPIO, GPIOA5.GPIO_Pin); // on met à 0 + } + else { + MyGPIO_Set(GPIOA5.GPIO, GPIOA5.GPIO_Pin); // on met à 1 + } + + } \ No newline at end of file diff --git a/Projet1.uvguix.alejeune b/Projet1.uvguix.alejeune index 3f4b290..5fa0aba 100644 --- a/Projet1.uvguix.alejeune +++ b/Projet1.uvguix.alejeune @@ -93,25 +93,25 @@ 0 1 - -1 - -1 + -32000 + -32000 -1 -1 - 182 - 182 - 1718 - 991 + 75 + -412 + 1124 + 884 0 937 - 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898 @@ -3615,18 +3615,18 @@ .\FileInclude\MyTimer.c - 0 - 13 - 1 + 52 + 264 + 106 1 0 U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c - 42 - 1 - 25 + 51 + 7 + 43 1 0 @@ -3669,9 +3669,9 @@ .\FileInclude\Plateau.c - 1 + 8 1 - 23 + 32 1 0 From 207ee64a7f1fd9741c33fa506178be65a223d94f Mon Sep 17 00:00:00 2001 From: alejeune Date: Fri, 28 Oct 2022 10:04:14 +0200 Subject: [PATCH 3/5] Driver plateau done untested --- DebugConfig/R_el_STM32F103RB_1.0.0.dbgconf | 72 +- .../SImulation_STM32F103RB_1.0.0.dbgconf | 72 +- .../Target_1_STM32F103RB_1.0.0.dbgconf | 72 +- EventRecorderStub.scvd | 18 +- FileInclude/Driver_GPIO.c | 104 +- FileInclude/Driver_GPIO.h | 58 +- FileInclude/MyADC.c | 72 +- FileInclude/MyADC.h | 24 +- FileInclude/MyTimer.c | 616 +- FileInclude/MyTimer.h | 88 +- FileInclude/Plateau.c | 106 +- FileInclude/Plateau.h | 20 +- LICENSE | 6 +- Listings/Projet1.map | 286 +- Listings/Projet1_Simulation.map | 825 +- Listings/startup_stm32f10x_md.lst | 2360 +++--- Objects/ExtDll.iex | 4 +- Objects/Projet1.build_log.htm | 158 +- Objects/Projet1.lnp | 10 +- Objects/Projet1_SImulation.dep | 25 +- Objects/Projet1_Simulation.axf | Bin 232724 -> 237584 bytes Objects/Projet1_Simulation.build_log.htm | 157 +- Objects/Projet1_Simulation.htm | 849 +- Objects/Projet1_Simulation.lnp | 22 +- Objects/Projet1_Simulation.sct | 32 +- Objects/driver_gpio.d | 20 +- Objects/driver_gpio.o | Bin 260664 -> 260664 bytes Objects/main.crf | Bin 239465 -> 239625 bytes Objects/main.d | 25 +- Objects/main.o | Bin 258424 -> 257112 bytes Objects/myadc.crf | Bin 239520 -> 239520 bytes Objects/myadc.d | 24 +- Objects/myadc.o | Bin 258596 -> 258596 bytes Objects/mytimer.crf | Bin 242626 -> 242626 bytes Objects/mytimer.d | 22 +- Objects/mytimer.o | Bin 272596 -> 272596 bytes Objects/plateau.crf | Bin 239450 -> 239960 bytes Objects/plateau.d | 24 +- Objects/plateau.o | Bin 256696 -> 262080 bytes Objects/startup_stm32f10x_md.d | 2 +- Objects/system_stm32f10x.d | 18 +- Objects/system_stm32f10x.o | Bin 258552 -> 258552 bytes Objects/telecommande.d | 2 +- Objects/telecommande.o | Bin 4560 -> 4560 bytes Projet1 (2).uvguix | 7292 ++++++++--------- Projet1.uvguix | 7274 ++++++++-------- Projet1.uvguix - Copie.alejeune | 7274 ++++++++-------- Projet1.uvguix.alejeune | 176 +- Projet1.uvoptx | 13 +- README.md | 10 +- RTE/Device/STM32F103RB/RTE_Device.h | 3656 ++++----- RTE/Device/STM32F103RB/startup_stm32f10x_md.s | 614 +- RTE/Device/STM32F103RB/system_stm32f10x.c | 2188 ++--- RTE/_R_el/RTE_Components.h | 42 +- RTE/_SImulation/RTE_Components.h | 42 +- RTE/_Target_1/RTE_Components.h | 42 +- Sources/main.c | 66 +- 57 files changed, 17469 insertions(+), 17413 deletions(-) diff --git a/DebugConfig/R_el_STM32F103RB_1.0.0.dbgconf b/DebugConfig/R_el_STM32F103RB_1.0.0.dbgconf index 66e10b6..9c4804d 100644 --- a/DebugConfig/R_el_STM32F103RB_1.0.0.dbgconf +++ b/DebugConfig/R_el_STM32F103RB_1.0.0.dbgconf @@ -1,36 +1,36 @@ -// File: STM32F101_102_103_105_107.dbgconf -// Version: 1.0.0 -// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) -// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets - -// <<< Use Configuration Wizard in Context Menu >>> - -// Debug MCU configuration register (DBGMCU_CR) -// Reserved bits must be kept at reset value -// DBG_TIM11_STOP TIM11 counter stopped when core is halted -// DBG_TIM10_STOP TIM10 counter stopped when core is halted -// DBG_TIM9_STOP TIM9 counter stopped when core is halted -// DBG_TIM14_STOP TIM14 counter stopped when core is halted -// DBG_TIM13_STOP TIM13 counter stopped when core is halted -// DBG_TIM12_STOP TIM12 counter stopped when core is halted -// DBG_CAN2_STOP Debug CAN2 stopped when core is halted -// DBG_TIM7_STOP TIM7 counter stopped when core is halted -// DBG_TIM6_STOP TIM6 counter stopped when core is halted -// DBG_TIM5_STOP TIM5 counter stopped when core is halted -// DBG_TIM8_STOP TIM8 counter stopped when core is halted -// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted -// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted -// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted -// DBG_TIM4_STOP TIM4 counter stopped when core is halted -// DBG_TIM3_STOP TIM3 counter stopped when core is halted -// DBG_TIM2_STOP TIM2 counter stopped when core is halted -// DBG_TIM1_STOP TIM1 counter stopped when core is halted -// DBG_WWDG_STOP Debug window watchdog stopped when core is halted -// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted -// DBG_STANDBY Debug standby mode -// DBG_STOP Debug stop mode -// DBG_SLEEP Debug sleep mode -// -DbgMCU_CR = 0x00000007; - -// <<< end of configuration section >>> +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/DebugConfig/SImulation_STM32F103RB_1.0.0.dbgconf b/DebugConfig/SImulation_STM32F103RB_1.0.0.dbgconf index 66e10b6..9c4804d 100644 --- a/DebugConfig/SImulation_STM32F103RB_1.0.0.dbgconf +++ b/DebugConfig/SImulation_STM32F103RB_1.0.0.dbgconf @@ -1,36 +1,36 @@ -// File: STM32F101_102_103_105_107.dbgconf -// Version: 1.0.0 -// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) -// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets - -// <<< Use Configuration Wizard in Context Menu >>> - -// Debug MCU configuration register (DBGMCU_CR) -// Reserved bits must be kept at reset value -// DBG_TIM11_STOP TIM11 counter stopped when core is halted -// DBG_TIM10_STOP TIM10 counter stopped when core is halted -// DBG_TIM9_STOP TIM9 counter stopped when core is halted -// DBG_TIM14_STOP TIM14 counter stopped when core is halted -// DBG_TIM13_STOP TIM13 counter stopped when core is halted -// DBG_TIM12_STOP TIM12 counter stopped when core is halted -// DBG_CAN2_STOP Debug CAN2 stopped when core is halted -// DBG_TIM7_STOP TIM7 counter stopped when core is halted -// DBG_TIM6_STOP TIM6 counter stopped when core is halted -// DBG_TIM5_STOP TIM5 counter stopped when core is halted -// DBG_TIM8_STOP TIM8 counter stopped when core is halted -// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted -// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted -// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted -// DBG_TIM4_STOP TIM4 counter stopped when core is halted -// DBG_TIM3_STOP TIM3 counter stopped when core is halted -// DBG_TIM2_STOP TIM2 counter stopped when core is halted -// DBG_TIM1_STOP TIM1 counter stopped when core is halted -// DBG_WWDG_STOP Debug window watchdog stopped when core is halted -// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted -// DBG_STANDBY Debug standby mode -// DBG_STOP Debug stop mode -// DBG_SLEEP Debug sleep mode -// -DbgMCU_CR = 0x00000007; - -// <<< end of configuration section >>> +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf b/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf index 66e10b6..9c4804d 100644 --- a/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf +++ b/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf @@ -1,36 +1,36 @@ -// File: STM32F101_102_103_105_107.dbgconf -// Version: 1.0.0 -// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) -// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets - -// <<< Use Configuration Wizard in Context Menu >>> - -// Debug MCU configuration register (DBGMCU_CR) -// Reserved bits must be kept at reset value -// DBG_TIM11_STOP TIM11 counter stopped when core is halted -// DBG_TIM10_STOP TIM10 counter stopped when core is halted -// DBG_TIM9_STOP TIM9 counter stopped when core is halted -// DBG_TIM14_STOP TIM14 counter stopped when core is halted -// DBG_TIM13_STOP TIM13 counter stopped when core is halted -// DBG_TIM12_STOP TIM12 counter stopped when core is halted -// DBG_CAN2_STOP Debug CAN2 stopped when core is halted -// DBG_TIM7_STOP TIM7 counter stopped when core is halted -// DBG_TIM6_STOP TIM6 counter stopped when core is halted -// DBG_TIM5_STOP TIM5 counter stopped when core is halted -// DBG_TIM8_STOP TIM8 counter stopped when core is halted -// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted -// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted -// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted -// DBG_TIM4_STOP TIM4 counter stopped when core is halted -// DBG_TIM3_STOP TIM3 counter stopped when core is halted -// DBG_TIM2_STOP TIM2 counter stopped when core is halted -// DBG_TIM1_STOP TIM1 counter stopped when core is halted -// DBG_WWDG_STOP Debug window watchdog stopped when core is halted -// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted -// DBG_STANDBY Debug standby mode -// DBG_STOP Debug stop mode -// DBG_SLEEP Debug sleep mode -// -DbgMCU_CR = 0x00000007; - -// <<< end of configuration section >>> +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/EventRecorderStub.scvd b/EventRecorderStub.scvd index 2956b29..0fb3ee5 100644 --- a/EventRecorderStub.scvd +++ b/EventRecorderStub.scvd @@ -1,9 +1,9 @@ - - - - - - - - - + + + + + + + + + diff --git a/FileInclude/Driver_GPIO.c b/FileInclude/Driver_GPIO.c index 96d4d27..39423c6 100644 --- a/FileInclude/Driver_GPIO.c +++ b/FileInclude/Driver_GPIO.c @@ -1,52 +1,52 @@ -#include "Driver_GPIO.h" - -void MyGPIO_Init(MyGPIO_Struct_TypeDef * Data){ - char finalConf = Data->GPIO_Conf; - GPIO_TypeDef * GPIO; - GPIO = Data->GPIO; - - // Mise en place de la clock - if (GPIO==GPIOA){ - RCC->APB2ENR |= (0x01 << 2) ; - } else if (GPIO==GPIOB){ - RCC->APB2ENR |= (0x01 << 3) ; - } else { - RCC->APB2ENR |= (0x01 << 4) ; - } - - // On regarde si on est en pull_up - if (finalConf == 0x18){ - Data->GPIO->ODR |= 0x01 << Data->GPIO_Pin; - finalConf = 0x08; - } - - // Initialisation de la bonne pin - if (Data->GPIO_Pin < 8){ - Data->GPIO->CRL &= ~(0xF << 4*Data->GPIO_Pin); // shifté de 4*numPin - Data->GPIO->CRL |= (Data->GPIO_Conf << 4*Data->GPIO_Pin); - } - else { - Data->GPIO->CRH &= ~(0xF << 4*(Data->GPIO_Pin -8)); // shifté de 4*numPin - Data->GPIO->CRH |= (Data->GPIO_Conf << 4*(Data->GPIO_Pin -8)); - } -} - - -int MyGPIO_Read(GPIO_TypeDef* GPIO, int GPIO_Pin) {// renvoie 0 ou autre chose different de 0 - return ((GPIO->IDR >> GPIO_Pin) & 1); -} - -void MyGPIO_Set(GPIO_TypeDef* GPIO, int GPIO_Pin){ // Bit 0 à 15 de BSRR c'est le set - GPIO->BSRR |= 0x01 << GPIO_Pin; -} - -void MyGPIO_Reset(GPIO_TypeDef* GPIO, int GPIO_Pin){ // Bit 16 à 31 de BSRR c'est le reset - GPIO->BSRR |= ((0x01 << GPIO_Pin) << 0x10); -} - - -void MyGPIO_Toggle(GPIO_TypeDef* GPIO, int GPIO_Pin){ // Toggle : changer la valeur du ODR - GPIO->ODR ^= 0x01 << GPIO_Pin; -} - - +#include "Driver_GPIO.h" + +void MyGPIO_Init(MyGPIO_Struct_TypeDef * Data){ + char finalConf = Data->GPIO_Conf; + GPIO_TypeDef * GPIO; + GPIO = Data->GPIO; + + // Mise en place de la clock + if (GPIO==GPIOA){ + RCC->APB2ENR |= (0x01 << 2) ; + } else if (GPIO==GPIOB){ + RCC->APB2ENR |= (0x01 << 3) ; + } else { + RCC->APB2ENR |= (0x01 << 4) ; + } + + // On regarde si on est en pull_up + if (finalConf == 0x18){ + Data->GPIO->ODR |= 0x01 << Data->GPIO_Pin; + finalConf = 0x08; + } + + // Initialisation de la bonne pin + if (Data->GPIO_Pin < 8){ + Data->GPIO->CRL &= ~(0xF << 4*Data->GPIO_Pin); // shifté de 4*numPin + Data->GPIO->CRL |= (Data->GPIO_Conf << 4*Data->GPIO_Pin); + } + else { + Data->GPIO->CRH &= ~(0xF << 4*(Data->GPIO_Pin -8)); // shifté de 4*numPin + Data->GPIO->CRH |= (Data->GPIO_Conf << 4*(Data->GPIO_Pin -8)); + } +} + + +int MyGPIO_Read(GPIO_TypeDef* GPIO, int GPIO_Pin) {// renvoie 0 ou autre chose different de 0 + return ((GPIO->IDR >> GPIO_Pin) & 1); +} + +void MyGPIO_Set(GPIO_TypeDef* GPIO, int GPIO_Pin){ // Bit 0 à 15 de BSRR c'est le set + GPIO->BSRR |= 0x01 << GPIO_Pin; +} + +void MyGPIO_Reset(GPIO_TypeDef* GPIO, int GPIO_Pin){ // Bit 16 à 31 de BSRR c'est le reset + GPIO->BSRR |= ((0x01 << GPIO_Pin) << 0x10); +} + + +void MyGPIO_Toggle(GPIO_TypeDef* GPIO, int GPIO_Pin){ // Toggle : changer la valeur du ODR + GPIO->ODR ^= 0x01 << GPIO_Pin; +} + + diff --git a/FileInclude/Driver_GPIO.h b/FileInclude/Driver_GPIO.h index a04763e..bc434da 100644 --- a/FileInclude/Driver_GPIO.h +++ b/FileInclude/Driver_GPIO.h @@ -1,29 +1,29 @@ -#ifndef MYGPIO_H -#define MYGPIO_H -#include "stm32f10x.h" - -typedef struct -{ - GPIO_TypeDef* GPIO; - int GPIO_Pin; //numero de 0 a 15 - int GPIO_Conf; //voir ci dessous -} MyGPIO_Struct_TypeDef; - - -#define In_Floating 0x04 -#define In_PullDown 0x08 -#define In_PullUp 0x18 // le 1 représente le fait qu'on est en pull up -#define In_Analog 0x00 -#define Out_Ppull 0x02 -#define Out_OD 0x05 -#define AltOut_Ppull 0x0A -#define AltOut_OD 0x0D - -void MyGPIO_Init(MyGPIO_Struct_TypeDef * Data); -int MyGPIO_Read(GPIO_TypeDef* GPIO, int GPIO_Pin);// renvoie 0 ou autre chose different de 0 -void MyGPIO_Set(GPIO_TypeDef* GPIO, int GPIO_Pin); -void MyGPIO_Reset(GPIO_TypeDef* GPIO, int GPIO_Pin); -void MyGPIO_Toggle(GPIO_TypeDef* GPIO, int GPIO_Pin); - -#endif - +#ifndef MYGPIO_H +#define MYGPIO_H +#include "stm32f10x.h" + +typedef struct +{ + GPIO_TypeDef* GPIO; + int GPIO_Pin; //numero de 0 a 15 + int GPIO_Conf; //voir ci dessous +} MyGPIO_Struct_TypeDef; + + +#define In_Floating 0x04 +#define In_PullDown 0x08 +#define In_PullUp 0x18 // le 1 représente le fait qu'on est en pull up +#define In_Analog 0x00 +#define Out_Ppull 0x02 +#define Out_OD 0x05 +#define AltOut_Ppull 0x0A +#define AltOut_OD 0x0D + +void MyGPIO_Init(MyGPIO_Struct_TypeDef * Data); +int MyGPIO_Read(GPIO_TypeDef* GPIO, int GPIO_Pin);// renvoie 0 ou autre chose different de 0 +void MyGPIO_Set(GPIO_TypeDef* GPIO, int GPIO_Pin); +void MyGPIO_Reset(GPIO_TypeDef* GPIO, int GPIO_Pin); +void MyGPIO_Toggle(GPIO_TypeDef* GPIO, int GPIO_Pin); + +#endif + diff --git a/FileInclude/MyADC.c b/FileInclude/MyADC.c index 8a772f8..6532fff 100644 --- a/FileInclude/MyADC.c +++ b/FileInclude/MyADC.c @@ -1,36 +1,36 @@ -#include "MyADC.h" -#include "MyTimer.h" -#include "Driver_GPIO.h" -#define NULL 0 -//#define nombreChannel 1 - -void initADC(int channel){ - - // activer la clock de l'ADC 1 - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; - RCC->CFGR |= 0x8000; - ADC1->CR2 |= ADC_CR2_ADON; - - // Choix du channel - ADC1->SQR3 |= channel << 0;// on est sur le premier car on a qu'un seul channel -} - -void startADC(void) { - ADC1->CR2 |= ADC_CR2_ADON; -} - -int read(void) { - int value ; - // Recuperer le bit de End of conversion - while (!(ADC1->SR & (0x01 << 1))); - //on veut masquer les 12 bits les plus bas donc on prend le not de 0x0f >> 12 (111000000000) - value = ADC1->DR & (~(0x0f << 12)); - return value; -} - - - - - - - +#include "MyADC.h" +#include "MyTimer.h" +#include "Driver_GPIO.h" +#define NULL 0 +//#define nombreChannel 1 + +void initADC(int channel){ + + // activer la clock de l'ADC 1 + RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; + RCC->CFGR |= 0x8000; + ADC1->CR2 |= ADC_CR2_ADON; + + // Choix du channel + ADC1->SQR3 |= channel << 0;// on est sur le premier car on a qu'un seul channel +} + +void startADC(void) { + ADC1->CR2 |= ADC_CR2_ADON; +} + +int read(void) { + int value ; + // Recuperer le bit de End of conversion + while (!(ADC1->SR & (0x01 << 1))); + //on veut masquer les 12 bits les plus bas donc on prend le not de 0x0f >> 12 (111000000000) + value = ADC1->DR & (~(0x0f << 12)); + return value; +} + + + + + + + diff --git a/FileInclude/MyADC.h b/FileInclude/MyADC.h index c3202fd..62ff113 100644 --- a/FileInclude/MyADC.h +++ b/FileInclude/MyADC.h @@ -1,12 +1,12 @@ -#ifndef __MYADC_H -#define __MYADC_H -#include "stm32f10x.h" - -// initialise tout ce au'il y a a faire pour l'ADC: -void initADC(int channel); - -void startADC(void); - -int read(void); - -#endif +#ifndef __MYADC_H +#define __MYADC_H +#include "stm32f10x.h" + +// initialise tout ce au'il y a a faire pour l'ADC: +void initADC(int channel); + +void startADC(void); + +int read(void); + +#endif diff --git a/FileInclude/MyTimer.c b/FileInclude/MyTimer.c index fc4a163..36d338d 100644 --- a/FileInclude/MyTimer.c +++ b/FileInclude/MyTimer.c @@ -1,308 +1,308 @@ -#include "MyTimer.h" -#include "stm32f10x.h" -#include "Driver_GPIO.h" -#define NULL 0 - -// Déclaration des fonctions utilisées lors de handlers -void (* ptr1) (void) = NULL; -void (* ptr2) (void) = NULL; -void (* ptr3) (void) = NULL; -void (* ptr4) (void) = NULL; - -void MyTimer_Base_Init (MyTimer_Struct_TypeDef* Data){ - TIM_TypeDef * numTimer ; - numTimer = Data->Timer ; - switch ((int)numTimer) { // on cast le pointeur vers le timer pour le comparer au pointeur des timers existants - case (int)TIM1 : - RCC->APB2ENR |= RCC_APB2ENR_TIM1EN ; // masque pour activer le timer (0xOB, pin 11) - break ; - - case (int)TIM2: - RCC->APB1ENR |= RCC_APB1ENR_TIM2EN ; // masque pour activer le timer2 (0x01) - break ; - - case (int)TIM3: - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN ; // masque pour activer le timer2 (0x02) - break ; - - case (int)TIM4: - RCC->APB1ENR |= RCC_APB1ENR_TIM4EN ; // masque pour activer le timer2 (0x03) - break ; - } - // on parametre ARR et PSC sur le timer - Data->Timer->ARR = Data->ARR ; - Data->Timer->PSC = Data->PSC ; -} - -void MyTimer_Base_Start(TIM_TypeDef * Timer ) { - Timer -> CR1 |= TIM_CR1_CEN ; // on active la clock du timer -} - -void MyTimer_Base_Stop(TIM_TypeDef * Timer ) { - Timer -> CR1 &= ~TIM_CR1_CEN ; // on désactive la clock du timer -} - - -void MyTimer_ActiveIT ( TIM_TypeDef * Timer , char Prio, void (* IT_function) (void)){ - Timer->DIER |= 0x01; // on autorise l'interuption au niveau du timer - - switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants - case (int)TIM1 : - NVIC->ISER[0] |= NVIC_ISER_SETENA_25; // on autorise l'interuption au niveau du coeur par le timer 1 - NVIC->IP[25] = Prio; // on parametre la prio du timer - ptr1 = IT_function; //fonction à appeler par le handler - break ; - - case (int)TIM2: - NVIC->ISER[0] |= NVIC_ISER_SETENA_28; // on autorise l'interuption au niveau du coeur par le timer 2 - NVIC->IP[28] = Prio; // on parametre la prio du timer - ptr2 = IT_function; //fonction à appeler par le handler - break ; - - case (int)TIM3: - NVIC->ISER[0] |= NVIC_ISER_SETENA_29; // on autorise l'interuption au niveau du coeur par le timer 3 - NVIC->IP[29] = Prio; // on parametre la prio du timer - ptr3 = IT_function; //fonction à appeler par le handler - break ; - - case (int)TIM4: - NVIC->ISER[0] |= NVIC_ISER_SETENA_30; // on autorise l'interuption au niveau du coeur par le timer 4 - NVIC->IP[30] = Prio; // on parametre la prio du timer - ptr4 = IT_function; //fonction à appeler par le handler - break ; - } -} - - - -void TIM1_UP_IRQHandler(void){ - if (ptr1 != NULL){ // si la fonction a bien été initialisée - (*ptr1)(); // on appelle la fonction en cas de handler1 - } - TIM1->SR &= ~(1<<0); // on baisse le flag d'activation -} - -void TIM2_IRQHandler(void){ - if (ptr2 != NULL){ // si la fonction a bien été initialisée - (*ptr2)(); // on appelle la fonction en cas de handler2 - } - TIM2->SR &= ~(1<<0); // on baisse le flag d'activation -} - -void TIM3_IRQHandler(void){ - if (ptr3 != NULL){ // si la fonction a bien été initialisée - (*ptr3)(); // on appelle la fonction en cas de handler3 - } - TIM3->SR &= ~(1<<0); // on baisse le flag d'activation -} - -void TIM4_IRQHandler(void){ - if (ptr4 != NULL){ // si la fonction a bien été initialisée - (*ptr4)(); // on appelle la fonction en cas de handler4 - } - TIM4->SR &= ~(1<<0); // on baisse le flag d'activation -} - -void MyTimer_PWM(TIM_TypeDef * Timer, char Channel){ - MyGPIO_Struct_TypeDef gpio; - gpio.GPIO_Conf = AltOut_Ppull; - - // Activation la capture du compteur (CNT) dans le registre capture register - Timer->CCER |= TIM_CCER_CC1E; - - - - switch ((int)Channel) { // on cast le timer pour le comparer au pointeur des timers existants - /* ============== - === Channel 1 === - ============== */ - - case 1 : - // On veut mettre les bits 4 à 6 de OC1M à 110 (PWM mode 1 p 349) - Timer->CCMR1 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; - Timer->CCMR1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC1S); // mettre 00 - Timer->CCR1 = 0; - - switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants - case (int)TIM1 : - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 8; - TIM1->BDTR |= TIM_BDTR_MOE ; // bit MOE pour activer le timer généralement (main output enable) - break ; - - case (int)TIM2: - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 0; - break ; - - case (int)TIM3: - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 6; - break ; - - case (int)TIM4: - gpio.GPIO = GPIOB; - gpio.GPIO_Pin = 6; - break ; - } - break ; - - - /* ============== - === Channel 2 === - ============== */ - - case 2 : - - // On veut mettre les bits 12 à 14 de OC1M à 110 (PWM mode 1 p 349) - Timer->CCMR1 |= TIM_CCMR1_OC2M_1| TIM_CCMR1_OC2M_2; - Timer->CCMR1 &= ~(TIM_CCMR1_CC2S | TIM_CCMR1_CC2S); // mettre 00 - Timer->CCR2 = 0; - - switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants - case (int)TIM1 : - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 9; - TIM1->BDTR |= TIM_BDTR_MOE ; // bit MOE pour activer le timer généralement (main output enable) - break ; - - case (int)TIM2: - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 1; - break ; - - case (int)TIM3: - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 7; - break ; - - case (int)TIM4: - gpio.GPIO = GPIOB; - gpio.GPIO_Pin = 7; - break ; - } - break ; - - - /* ============== - === Channel 3 === - ============== */ - case 3 : - - // On veut mettre les bits 4 à 6 de OC2M à 110 (PWM mode 1 p 349) - Timer->CCMR2 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; - Timer->CCMR2 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC1S); // mettre 00 - Timer->CCR3 = 0; - - switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants - case (int)TIM1 : - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 10; - TIM1->BDTR |= TIM_BDTR_MOE ; // bit MOE pour activer le timer généralement (main output enable) - break ; - - case (int)TIM2: - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 2; - break ; - - case (int)TIM3: - gpio.GPIO = GPIOB; - gpio.GPIO_Pin = 0; - break ; - - case (int)TIM4: - gpio.GPIO = GPIOB; - gpio.GPIO_Pin = 8; - break ; - } - break ; - - /* ============== - === Channel 4 === - ============== */ - case 4 : - - // On veut mettre les bits 12 à 14 de OC2M à 110 (PWM mode 1 p 349) - Timer->CCMR2 |= TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; - Timer->CCMR2 &= ~(TIM_CCMR1_CC2S | TIM_CCMR1_CC2S); // mettre 00 - Timer->CCR4 = 0; - - switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants - case (int)TIM1 : - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 11; - TIM1->BDTR |= TIM_BDTR_MOE ; // bit MOE pour activer le timer généralement (main output enable) - break ; - - case (int)TIM2: - gpio.GPIO = GPIOA; - gpio.GPIO_Pin = 3; - break ; - - case (int)TIM3: - gpio.GPIO = GPIOB; - gpio.GPIO_Pin = 1; - break ; - - case (int)TIM4: - gpio.GPIO = GPIOB; - gpio.GPIO_Pin = 9; - break ; - } - break ; - } - MyGPIO_Init(&gpio); -} - -// calculer et definir les valeurs de CRR -void Set_PWM_PRCT(TIM_TypeDef * Timer, char Channel, int percent){ - short value = Timer->ARR*percent/100; - - switch (Channel){ - case 1: - Timer->CCR1 = value; - break; - case 2: - Timer->CCR2 = value; - break; - case 3: - Timer->CCR3 = value; - break; - case 4: - Timer->CCR4 = value; - break; - } - - - - -} -void Set_Duty_Cycle(TIM_TypeDef * Timer , char Channel,uint16_t crr){ - switch(Channel){ - case 1: - Timer->CCR1 = crr; - break; - case 2: - Timer->CCR2 = crr; - break; - case 3: - Timer->CCR3 = crr; - break; - case 4: - Timer->CCR4 = crr; - break; - } -} - - -uint16_t Get_Max_Duty(TIM_TypeDef * Timer){ - return Timer->ARR; -} - - - - - - - +#include "MyTimer.h" +#include "stm32f10x.h" +#include "Driver_GPIO.h" +#define NULL 0 + +// Déclaration des fonctions utilisées lors de handlers +void (* ptr1) (void) = NULL; +void (* ptr2) (void) = NULL; +void (* ptr3) (void) = NULL; +void (* ptr4) (void) = NULL; + +void MyTimer_Base_Init (MyTimer_Struct_TypeDef* Data){ + TIM_TypeDef * numTimer ; + numTimer = Data->Timer ; + switch ((int)numTimer) { // on cast le pointeur vers le timer pour le comparer au pointeur des timers existants + case (int)TIM1 : + RCC->APB2ENR |= RCC_APB2ENR_TIM1EN ; // masque pour activer le timer (0xOB, pin 11) + break ; + + case (int)TIM2: + RCC->APB1ENR |= RCC_APB1ENR_TIM2EN ; // masque pour activer le timer2 (0x01) + break ; + + case (int)TIM3: + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN ; // masque pour activer le timer2 (0x02) + break ; + + case (int)TIM4: + RCC->APB1ENR |= RCC_APB1ENR_TIM4EN ; // masque pour activer le timer2 (0x03) + break ; + } + // on parametre ARR et PSC sur le timer + Data->Timer->ARR = Data->ARR ; + Data->Timer->PSC = Data->PSC ; +} + +void MyTimer_Base_Start(TIM_TypeDef * Timer ) { + Timer -> CR1 |= TIM_CR1_CEN ; // on active la clock du timer +} + +void MyTimer_Base_Stop(TIM_TypeDef * Timer ) { + Timer -> CR1 &= ~TIM_CR1_CEN ; // on désactive la clock du timer +} + + +void MyTimer_ActiveIT ( TIM_TypeDef * Timer , char Prio, void (* IT_function) (void)){ + Timer->DIER |= 0x01; // on autorise l'interuption au niveau du timer + + switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants + case (int)TIM1 : + NVIC->ISER[0] |= NVIC_ISER_SETENA_25; // on autorise l'interuption au niveau du coeur par le timer 1 + NVIC->IP[25] = Prio; // on parametre la prio du timer + ptr1 = IT_function; //fonction à appeler par le handler + break ; + + case (int)TIM2: + NVIC->ISER[0] |= NVIC_ISER_SETENA_28; // on autorise l'interuption au niveau du coeur par le timer 2 + NVIC->IP[28] = Prio; // on parametre la prio du timer + ptr2 = IT_function; //fonction à appeler par le handler + break ; + + case (int)TIM3: + NVIC->ISER[0] |= NVIC_ISER_SETENA_29; // on autorise l'interuption au niveau du coeur par le timer 3 + NVIC->IP[29] = Prio; // on parametre la prio du timer + ptr3 = IT_function; //fonction à appeler par le handler + break ; + + case (int)TIM4: + NVIC->ISER[0] |= NVIC_ISER_SETENA_30; // on autorise l'interuption au niveau du coeur par le timer 4 + NVIC->IP[30] = Prio; // on parametre la prio du timer + ptr4 = IT_function; //fonction à appeler par le handler + break ; + } +} + + + +void TIM1_UP_IRQHandler(void){ + if (ptr1 != NULL){ // si la fonction a bien été initialisée + (*ptr1)(); // on appelle la fonction en cas de handler1 + } + TIM1->SR &= ~(1<<0); // on baisse le flag d'activation +} + +void TIM2_IRQHandler(void){ + if (ptr2 != NULL){ // si la fonction a bien été initialisée + (*ptr2)(); // on appelle la fonction en cas de handler2 + } + TIM2->SR &= ~(1<<0); // on baisse le flag d'activation +} + +void TIM3_IRQHandler(void){ + if (ptr3 != NULL){ // si la fonction a bien été initialisée + (*ptr3)(); // on appelle la fonction en cas de handler3 + } + TIM3->SR &= ~(1<<0); // on baisse le flag d'activation +} + +void TIM4_IRQHandler(void){ + if (ptr4 != NULL){ // si la fonction a bien été initialisée + (*ptr4)(); // on appelle la fonction en cas de handler4 + } + TIM4->SR &= ~(1<<0); // on baisse le flag d'activation +} + +void MyTimer_PWM(TIM_TypeDef * Timer, char Channel){ + MyGPIO_Struct_TypeDef gpio; + gpio.GPIO_Conf = AltOut_Ppull; + + // Activation la capture du compteur (CNT) dans le registre capture register + Timer->CCER |= TIM_CCER_CC1E; + + + + switch ((int)Channel) { // on cast le timer pour le comparer au pointeur des timers existants + /* ============== + === Channel 1 === + ============== */ + + case 1 : + // On veut mettre les bits 4 à 6 de OC1M à 110 (PWM mode 1 p 349) + Timer->CCMR1 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; + Timer->CCMR1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC1S); // mettre 00 + Timer->CCR1 = 0; + + switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants + case (int)TIM1 : + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 8; + TIM1->BDTR |= TIM_BDTR_MOE ; // bit MOE pour activer le timer généralement (main output enable) + break ; + + case (int)TIM2: + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 0; + break ; + + case (int)TIM3: + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 6; + break ; + + case (int)TIM4: + gpio.GPIO = GPIOB; + gpio.GPIO_Pin = 6; + break ; + } + break ; + + + /* ============== + === Channel 2 === + ============== */ + + case 2 : + + // On veut mettre les bits 12 à 14 de OC1M à 110 (PWM mode 1 p 349) + Timer->CCMR1 |= TIM_CCMR1_OC2M_1| TIM_CCMR1_OC2M_2; + Timer->CCMR1 &= ~(TIM_CCMR1_CC2S | TIM_CCMR1_CC2S); // mettre 00 + Timer->CCR2 = 0; + + switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants + case (int)TIM1 : + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 9; + TIM1->BDTR |= TIM_BDTR_MOE ; // bit MOE pour activer le timer généralement (main output enable) + break ; + + case (int)TIM2: + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 1; + break ; + + case (int)TIM3: + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 7; + break ; + + case (int)TIM4: + gpio.GPIO = GPIOB; + gpio.GPIO_Pin = 7; + break ; + } + break ; + + + /* ============== + === Channel 3 === + ============== */ + case 3 : + + // On veut mettre les bits 4 à 6 de OC2M à 110 (PWM mode 1 p 349) + Timer->CCMR2 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; + Timer->CCMR2 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC1S); // mettre 00 + Timer->CCR3 = 0; + + switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants + case (int)TIM1 : + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 10; + TIM1->BDTR |= TIM_BDTR_MOE ; // bit MOE pour activer le timer généralement (main output enable) + break ; + + case (int)TIM2: + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 2; + break ; + + case (int)TIM3: + gpio.GPIO = GPIOB; + gpio.GPIO_Pin = 0; + break ; + + case (int)TIM4: + gpio.GPIO = GPIOB; + gpio.GPIO_Pin = 8; + break ; + } + break ; + + /* ============== + === Channel 4 === + ============== */ + case 4 : + + // On veut mettre les bits 12 à 14 de OC2M à 110 (PWM mode 1 p 349) + Timer->CCMR2 |= TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; + Timer->CCMR2 &= ~(TIM_CCMR1_CC2S | TIM_CCMR1_CC2S); // mettre 00 + Timer->CCR4 = 0; + + switch ((int)Timer) { // on cast le timer pour le comparer au pointeur des timers existants + case (int)TIM1 : + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 11; + TIM1->BDTR |= TIM_BDTR_MOE ; // bit MOE pour activer le timer généralement (main output enable) + break ; + + case (int)TIM2: + gpio.GPIO = GPIOA; + gpio.GPIO_Pin = 3; + break ; + + case (int)TIM3: + gpio.GPIO = GPIOB; + gpio.GPIO_Pin = 1; + break ; + + case (int)TIM4: + gpio.GPIO = GPIOB; + gpio.GPIO_Pin = 9; + break ; + } + break ; + } + MyGPIO_Init(&gpio); +} + +// calculer et definir les valeurs de CRR +void Set_PWM_PRCT(TIM_TypeDef * Timer, char Channel, int percent){ + short value = Timer->ARR*percent/100; + + switch (Channel){ + case 1: + Timer->CCR1 = value; + break; + case 2: + Timer->CCR2 = value; + break; + case 3: + Timer->CCR3 = value; + break; + case 4: + Timer->CCR4 = value; + break; + } + + + + +} +void Set_Duty_Cycle(TIM_TypeDef * Timer , char Channel,uint16_t crr){ + switch(Channel){ + case 1: + Timer->CCR1 = crr; + break; + case 2: + Timer->CCR2 = crr; + break; + case 3: + Timer->CCR3 = crr; + break; + case 4: + Timer->CCR4 = crr; + break; + } +} + + +uint16_t Get_Max_Duty(TIM_TypeDef * Timer){ + return Timer->ARR; +} + + + + + + + diff --git a/FileInclude/MyTimer.h b/FileInclude/MyTimer.h index b460eb2..2a47e54 100644 --- a/FileInclude/MyTimer.h +++ b/FileInclude/MyTimer.h @@ -1,44 +1,44 @@ -#ifndef __MYTIMER_H -#define __MYTIMER_H -#include "stm32f10x.h" - -typedef struct -{ - TIM_TypeDef * Timer ; // TIM1 à TIM4 - unsigned short ARR ; - unsigned short PSC ; -} MyTimer_Struct_TypeDef ; - -/* -***************************************************************************************** -* @brief -* @param -> Paramètre sous forme d’une structure (son adresse) contenant les -informations de base -* @Note -> Fonction à lancer systématiquement avant d’aller plus en détail dans les -conf plus fines (PWM, codeur inc ...) -************************************************************************************************* -*/ - - -void MyTimer_Base_Init (MyTimer_Struct_TypeDef* Data) ; - -void MyTimer_Base_Start(TIM_TypeDef * Timer ); -void MyTimer_Base_Stop(TIM_TypeDef * Timer ); - -void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (* IT_function) (void)); - -void MyTimer_PWM(TIM_TypeDef * Timer, char Channel); -/** -* alpha = CRR/ARR, use Get_Max_Duty(Timer) to get ARR -*/ -void Set_Duty_Cycle(TIM_TypeDef * Timer , char Channel,uint16_t crr); - -/** -* Returns ARR -*/ -uint16_t Get_Max_Duty(TIM_TypeDef * Timer); - - -void Set_PWM_PRCT(TIM_TypeDef * Timer, char Channel, int percent); - -#endif +#ifndef __MYTIMER_H +#define __MYTIMER_H +#include "stm32f10x.h" + +typedef struct +{ + TIM_TypeDef * Timer ; // TIM1 à TIM4 + unsigned short ARR ; + unsigned short PSC ; +} MyTimer_Struct_TypeDef ; + +/* +***************************************************************************************** +* @brief +* @param -> Paramètre sous forme d’une structure (son adresse) contenant les +informations de base +* @Note -> Fonction à lancer systématiquement avant d’aller plus en détail dans les +conf plus fines (PWM, codeur inc ...) +************************************************************************************************* +*/ + + +void MyTimer_Base_Init (MyTimer_Struct_TypeDef* Data) ; + +void MyTimer_Base_Start(TIM_TypeDef * Timer ); +void MyTimer_Base_Stop(TIM_TypeDef * Timer ); + +void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (* IT_function) (void)); + +void MyTimer_PWM(TIM_TypeDef * Timer, char Channel); +/** +* alpha = CRR/ARR, use Get_Max_Duty(Timer) to get ARR +*/ +void Set_Duty_Cycle(TIM_TypeDef * Timer , char Channel,uint16_t crr); + +/** +* Returns ARR +*/ +uint16_t Get_Max_Duty(TIM_TypeDef * Timer); + + +void Set_PWM_PRCT(TIM_TypeDef * Timer, char Channel, int percent); + +#endif diff --git a/FileInclude/Plateau.c b/FileInclude/Plateau.c index 4b448ec..b2ece7e 100644 --- a/FileInclude/Plateau.c +++ b/FileInclude/Plateau.c @@ -1,47 +1,59 @@ -#include "MyTimer.h" -#include "stm32f10x.h" -#include "Driver_GPIO.h" -#include "Plateau.h" - - -/* Permet de diriger le plateau du voilier */ -void Set_Moteur_Plateau(char sens, char vitesse){ // -1 gauche et 1 droite - /* Declarations */ - char channel; - MyTimer_Struct_TypeDef TIM; - MyGPIO_Struct_TypeDef GPIOA5; // pin direction - MyGPIO_Struct_TypeDef GPIOA6; // pin moteur - channel =1; - - /* Configuration du Timer */ - MyTimer_Struct_TypeDef * Data = &TIM; - Data->Timer = TIM3; - Data->ARR = 300; - Data->PSC = 11; // pas sur de la valeur car on veut 20kHz au max - - Set_Duty_Cycle(Data->Timer, channel, Get_Max_Duty(Data->Timer)*vitesse); - MyTimer_Base_Init(Data); - - /* Configuration des GPIOs */ - GPIOA5.GPIO = GPIOA; - GPIOA5.GPIO_Pin = 5; - GPIOA5.GPIO_Conf = Out_Ppull; - - GPIOA6.GPIO = GPIOA; - GPIOA6.GPIO_Pin = 6; - GPIOA6.GPIO_Conf = AltOut_Ppull; - - MyTimer_Base_Start(TIM3); - MyTimer_PWM(Data->Timer,channel); - - /* Rotation */ - if (sens == 1){ - MyGPIO_Reset(GPIOA5.GPIO, GPIOA5.GPIO_Pin); // on met à 0 - } - else { - MyGPIO_Set(GPIOA5.GPIO, GPIOA5.GPIO_Pin); // on met à 1 - } - - - -} \ No newline at end of file +#include "MyTimer.h" +#include "stm32f10x.h" +#include "Driver_GPIO.h" +#include "Plateau.h" + +/* Declarations */ + +char channel = 1 ; +MyTimer_Struct_TypeDef TIM; +MyTimer_Struct_TypeDef * Data = &TIM; +MyGPIO_Struct_TypeDef GPIOA5; // pin direction +MyGPIO_Struct_TypeDef GPIOA6; // pin moteur + +void Init_Plateau (void) { + + /* Configuration du Timer */ + Data->Timer = TIM3; + Data->ARR = 300; + Data->PSC = 11; + + MyTimer_Base_Init(Data); + + /* Configuration des GPIOs */ + GPIOA5.GPIO = GPIOA; + GPIOA5.GPIO_Pin = 5; + GPIOA5.GPIO_Conf = Out_Ppull; + MyGPIO_Init(&GPIOA5); + + GPIOA6.GPIO = GPIOA; + GPIOA6.GPIO_Pin = 6; + GPIOA6.GPIO_Conf = AltOut_Ppull; + MyGPIO_Init(&GPIOA6); + + MyTimer_Base_Start(TIM3); + MyTimer_PWM(Data->Timer,channel); +} + +void Set_Direction (char sens) { + /* Rotation */ + if (sens == HORRAIRE){ + MyGPIO_Reset(GPIOA5.GPIO, GPIOA5.GPIO_Pin); // on met à 0 + } + else if (sens == ANTI_HORRAIRE) { + MyGPIO_Set(GPIOA5.GPIO, GPIOA5.GPIO_Pin); // on met à 1 + } +} + +void Set_Vitesse (char vitesse) { + + Set_PWM_PRCT(Data->Timer, channel, vitesse); + +} +/* Permet de diriger le plateau du voilier */ +void Set_Moteur_Plateau(char sens, char vitesse){ // -1 gauche et 1 droite + Init_Plateau(); + Set_Direction(sens); + Set_Vitesse(vitesse); + +} diff --git a/FileInclude/Plateau.h b/FileInclude/Plateau.h index 6ccc648..94cbceb 100644 --- a/FileInclude/Plateau.h +++ b/FileInclude/Plateau.h @@ -1,7 +1,13 @@ -#ifndef MYPLATEAU_H -#define MYPLATEAU_H -#include "stm32f10x.h" - -void Set_Moteur_Plateau(char sens, char vitesse); // -1 gauche et 1 droite - -#endif \ No newline at end of file +#ifndef MYPLATEAU_H +#define MYPLATEAU_H +#define HORRAIRE 0 +#define ANTI_HORRAIRE 1 +#include "stm32f10x.h" + +void Init_Plateau (void); +void Set_Direction (char sens); +void Set_Vitesse (char vitesse); + +void Set_Moteur_Plateau(char sens, char vitesse); // -1 gauche et 1 droite + +#endif diff --git a/LICENSE b/LICENSE index 3db68ad..b9da49b 100644 --- a/LICENSE +++ b/LICENSE @@ -1,3 +1,3 @@ -Copyright (C) 2006 by Rob Landley -Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted. -THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +Copyright (C) 2006 by Rob Landley +Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted. +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. diff --git a/Listings/Projet1.map b/Listings/Projet1.map index 793527d..36263db 100644 --- a/Listings/Projet1.map +++ b/Listings/Projet1.map @@ -1,143 +1,143 @@ -Component: ARM Compiler 6.16 Tool: armlink [5dfeaa00] - -============================================================================== - -Section Cross References - - startup_stm32f10x_md.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory - startup_stm32f10x_md.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory - startup_stm32f10x_md.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory - startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp - startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler - startup_stm32f10x_md.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory - startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(.text.SystemInit) for SystemInit - startup_stm32f10x_md.o(.text) refers to __main.o(!!!main) for __main - startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(HEAP) for Heap_Mem - startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(STACK) for Stack_Mem - system_stm32f10x.o(.text.SystemInit) refers to system_stm32f10x.o(.text.SetSysClock) for SetSysClock - system_stm32f10x.o(.ARM.exidx.text.SystemInit) refers to system_stm32f10x.o(.text.SystemInit) for [Anonymous Symbol] - system_stm32f10x.o(.text.SetSysClock) refers to system_stm32f10x.o(.text.SetSysClockTo72) for SetSysClockTo72 - system_stm32f10x.o(.ARM.exidx.text.SetSysClock) refers to system_stm32f10x.o(.text.SetSysClock) for [Anonymous Symbol] - system_stm32f10x.o(.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data.SystemCoreClock) for SystemCoreClock - system_stm32f10x.o(.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.rodata.AHBPrescTable) for AHBPrescTable - system_stm32f10x.o(.ARM.exidx.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.text.SystemCoreClockUpdate) for [Anonymous Symbol] - system_stm32f10x.o(.ARM.exidx.text.SetSysClockTo72) refers to system_stm32f10x.o(.text.SetSysClockTo72) for [Anonymous Symbol] - __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry - __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li - __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main - __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to 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.ARM.Collect$$rtentry$$00000001 - __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 - __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A - __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B - __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D - __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap - __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 - sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace - sys_stackheap_outer.o(.text) refers to startup_stm32f10x_md.o(.text) for __user_initial_stackheap - exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for 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refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit - rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls - rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 - rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit - rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls - rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 - rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 - libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F - libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F - libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F - libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F - libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F - libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer - libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer - rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown - rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit - rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 - rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 - rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 - argv_veneer.o(.emb_text) refers to _get_argv_nomalloc.o(.text) for __ARM_get_argv - sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting - sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function - sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting - sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function - _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard - _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM - _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string - libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 - libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 - libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 - libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return - libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 - libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 - libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 - sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting - sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function - sys_command_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting - sys_command_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function - defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner - defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit - defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise - rt_raise.o(.text) refers to __raise.o(.text) for __raise - rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit - defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit - defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display - __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler - defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch - sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting - sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function - sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting - sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function - defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner - defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display - defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display - defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display - defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display - defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display - defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display - defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display - defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display - - -============================================================================== - -Removing Unused input sections from the image. - - Removing system_stm32f10x.o(.text), (0 bytes). - Removing system_stm32f10x.o(.ARM.exidx.text.SystemInit), (8 bytes). - Removing system_stm32f10x.o(.ARM.exidx.text.SetSysClock), (8 bytes). - Removing system_stm32f10x.o(.text.SystemCoreClockUpdate), (110 bytes). - Removing system_stm32f10x.o(.ARM.exidx.text.SystemCoreClockUpdate), (8 bytes). - Removing system_stm32f10x.o(.ARM.exidx.text.SetSysClockTo72), (8 bytes). - Removing system_stm32f10x.o(.data.SystemCoreClock), (4 bytes). - Removing system_stm32f10x.o(.rodata.AHBPrescTable), (16 bytes). - -8 unused section(s) (total 162 bytes) removed from the image. +Component: ARM Compiler 6.16 Tool: armlink [5dfeaa00] + +============================================================================== + +Section Cross References + + startup_stm32f10x_md.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp + startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler + startup_stm32f10x_md.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(.text.SystemInit) for SystemInit + startup_stm32f10x_md.o(.text) refers to __main.o(!!!main) for __main + startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(HEAP) for Heap_Mem + startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(STACK) for Stack_Mem + system_stm32f10x.o(.text.SystemInit) refers to system_stm32f10x.o(.text.SetSysClock) for SetSysClock + system_stm32f10x.o(.ARM.exidx.text.SystemInit) refers to system_stm32f10x.o(.text.SystemInit) for [Anonymous Symbol] + system_stm32f10x.o(.text.SetSysClock) refers to system_stm32f10x.o(.text.SetSysClockTo72) for SetSysClockTo72 + system_stm32f10x.o(.ARM.exidx.text.SetSysClock) refers to system_stm32f10x.o(.text.SetSysClock) for [Anonymous Symbol] + system_stm32f10x.o(.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data.SystemCoreClock) for SystemCoreClock + system_stm32f10x.o(.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.rodata.AHBPrescTable) for AHBPrescTable + system_stm32f10x.o(.ARM.exidx.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.text.SystemCoreClockUpdate) for [Anonymous Symbol] + system_stm32f10x.o(.ARM.exidx.text.SetSysClockTo72) refers to system_stm32f10x.o(.text.SetSysClockTo72) for [Anonymous Symbol] + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32f10x_md.o(.text) for __user_initial_stackheap + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000027) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + argv_veneer.o(.emb_text) refers to _get_argv_nomalloc.o(.text) for __ARM_get_argv + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_command_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing system_stm32f10x.o(.text), (0 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SystemInit), (8 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SetSysClock), (8 bytes). + Removing system_stm32f10x.o(.text.SystemCoreClockUpdate), (110 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SystemCoreClockUpdate), (8 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SetSysClockTo72), (8 bytes). + Removing system_stm32f10x.o(.data.SystemCoreClock), (4 bytes). + Removing system_stm32f10x.o(.rodata.AHBPrescTable), (16 bytes). + +8 unused section(s) (total 162 bytes) removed from the image. diff --git a/Listings/Projet1_Simulation.map b/Listings/Projet1_Simulation.map index 824d2e4..5285229 100644 --- a/Listings/Projet1_Simulation.map +++ b/Listings/Projet1_Simulation.map @@ -1,402 +1,423 @@ -Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601] - -============================================================================== - -Section Cross References - - main.o(i.Callback) refers to myadc.o(i.startADC) for startADC - main.o(i.Callback) refers to myadc.o(i.read) for read - main.o(i.Callback) refers to main.o(.data) for a - main.o(i.main) refers to mytimer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init - main.o(i.main) refers to myadc.o(i.initADC) for initADC - main.o(i.main) refers to mytimer.o(i.MyTimer_ActiveIT) for MyTimer_ActiveIT - main.o(i.main) refers to mytimer.o(i.MyTimer_Base_Start) for MyTimer_Base_Start - main.o(i.main) refers to main.o(i.Callback) for Callback - mytimer.o(i.MyTimer_ActiveIT) refers to mytimer.o(.data) for ptr1 - mytimer.o(i.MyTimer_PWM) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init - mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(.data) for ptr1 - mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(.data) for ptr2 - mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(.data) for ptr3 - mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(.data) for ptr4 - plateau.o(i.Set_Moteur_Plateau) refers to mytimer.o(i.Get_Max_Duty) for Get_Max_Duty - plateau.o(i.Set_Moteur_Plateau) refers to mytimer.o(i.Set_Duty_Cycle) for Set_Duty_Cycle - plateau.o(i.Set_Moteur_Plateau) refers to mytimer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init - startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp - startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler - startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler - startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler - startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler - startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler - startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit - startup_stm32f10x_md.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main - system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72 - system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock - system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000F) for __rt_final_cpp - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$00000011) for __rt_final_exit - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry12b.o(.ARM.Collect$$$$0000000E) for __rt_lib_shutdown_fini - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk - entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 - entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_md.o(STACK) for __initial_sp - entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_md.o(STACK) for __initial_sp - entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main - entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload - entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main - entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main - init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload - - -============================================================================== - -Removing Unused input sections from the image. - - Removing main.o(.rev16_text), (4 bytes). - Removing main.o(.revsh_text), (4 bytes). - Removing main.o(.rrx_text), (6 bytes). - Removing driver_gpio.o(.rev16_text), (4 bytes). - Removing driver_gpio.o(.revsh_text), (4 bytes). - Removing driver_gpio.o(.rrx_text), (6 bytes). - Removing driver_gpio.o(i.MyGPIO_Init), (180 bytes). - Removing driver_gpio.o(i.MyGPIO_Read), (12 bytes). - Removing driver_gpio.o(i.MyGPIO_Reset), (14 bytes). - Removing driver_gpio.o(i.MyGPIO_Set), (12 bytes). - Removing driver_gpio.o(i.MyGPIO_Toggle), (12 bytes). - Removing mytimer.o(.rev16_text), (4 bytes). - Removing mytimer.o(.revsh_text), (4 bytes). - Removing mytimer.o(.rrx_text), (6 bytes). - Removing mytimer.o(i.Get_Max_Duty), (6 bytes). - Removing mytimer.o(i.MyTimer_Base_Stop), (10 bytes). - Removing mytimer.o(i.MyTimer_PWM), (464 bytes). - Removing mytimer.o(i.Set_Duty_Cycle), (40 bytes). - Removing mytimer.o(i.Set_PWM_PRCT), (56 bytes). - Removing myadc.o(.rev16_text), (4 bytes). - Removing myadc.o(.revsh_text), (4 bytes). - Removing myadc.o(.rrx_text), (6 bytes). - Removing plateau.o(.rev16_text), (4 bytes). - Removing plateau.o(.revsh_text), (4 bytes). - Removing plateau.o(.rrx_text), (6 bytes). - Removing plateau.o(i.Set_Moteur_Plateau), (60 bytes). - Removing startup_stm32f10x_md.o(HEAP), (512 bytes). - Removing system_stm32f10x.o(.rev16_text), (4 bytes). - Removing system_stm32f10x.o(.revsh_text), (4 bytes). - Removing system_stm32f10x.o(.rrx_text), (6 bytes). - Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes). - Removing system_stm32f10x.o(.data), (20 bytes). - -32 unused section(s) (total 1646 bytes) removed from the image. - -============================================================================== - -Image Symbol Table - - Local Symbols - - Symbol Name Value Ov Type Size Object(Section) - - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE - FileInclude\MyADC.c 0x00000000 Number 0 myadc.o ABSOLUTE - FileInclude\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE - FileInclude\Plateau.c 0x00000000 Number 0 plateau.o ABSOLUTE - FileInclude\Telecommande.c 0x00000000 Number 0 telecommande.o ABSOLUTE - FileInclude\\MyADC.c 0x00000000 Number 0 myadc.o ABSOLUTE - FileInclude\\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE - FileInclude\\Plateau.c 0x00000000 Number 0 plateau.o ABSOLUTE - RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE - RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE - RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE - Sources\\main.c 0x00000000 Number 0 main.o ABSOLUTE - Sources\main.c 0x00000000 Number 0 main.o ABSOLUTE - U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE - U:\\Documents\\4ir\\S1\\Microcontroleur\\Drivers\\FileInclude\\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE - dc.s 0x00000000 Number 0 dc.o ABSOLUTE - handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE - init.s 0x00000000 Number 0 init.o ABSOLUTE - RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET) - .ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000) - .ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001) - .ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004) - .ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008) - .ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) - .ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) - .ARM.Collect$$$$0000000E 0x080000fc Section 4 entry12b.o(.ARM.Collect$$$$0000000E) - .ARM.Collect$$$$0000000F 0x08000100 Section 0 entry10a.o(.ARM.Collect$$$$0000000F) - .ARM.Collect$$$$00000011 0x08000100 Section 0 entry11a.o(.ARM.Collect$$$$00000011) - .ARM.Collect$$$$00002712 0x08000100 Section 4 entry2.o(.ARM.Collect$$$$00002712) - __lit__00000000 0x08000100 Data 4 entry2.o(.ARM.Collect$$$$00002712) - .text 0x08000104 Section 36 startup_stm32f10x_md.o(.text) - .text 0x08000128 Section 36 init.o(.text) - i.Callback 0x0800014c Section 0 main.o(i.Callback) - i.MyTimer_ActiveIT 0x08000160 Section 0 mytimer.o(i.MyTimer_ActiveIT) - i.MyTimer_Base_Init 0x08000210 Section 0 mytimer.o(i.MyTimer_Base_Init) - i.MyTimer_Base_Start 0x0800027c Section 0 mytimer.o(i.MyTimer_Base_Start) - i.SetSysClock 0x08000286 Section 0 system_stm32f10x.o(i.SetSysClock) - SetSysClock 0x08000287 Thumb Code 8 system_stm32f10x.o(i.SetSysClock) - i.SetSysClockTo72 0x08000290 Section 0 system_stm32f10x.o(i.SetSysClockTo72) - SetSysClockTo72 0x08000291 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72) - i.SystemInit 0x08000370 Section 0 system_stm32f10x.o(i.SystemInit) - i.TIM1_UP_IRQHandler 0x080003d0 Section 0 mytimer.o(i.TIM1_UP_IRQHandler) - i.TIM2_IRQHandler 0x080003f4 Section 0 mytimer.o(i.TIM2_IRQHandler) - i.TIM3_IRQHandler 0x08000418 Section 0 mytimer.o(i.TIM3_IRQHandler) - i.TIM4_IRQHandler 0x0800043c Section 0 mytimer.o(i.TIM4_IRQHandler) - i.__scatterload_copy 0x08000460 Section 14 handlers.o(i.__scatterload_copy) - i.__scatterload_null 0x0800046e Section 2 handlers.o(i.__scatterload_null) - i.__scatterload_zeroinit 0x08000470 Section 14 handlers.o(i.__scatterload_zeroinit) - i.initADC 0x08000480 Section 0 myadc.o(i.initADC) - i.main 0x080004bc Section 0 main.o(i.main) - i.read 0x080004f8 Section 0 myadc.o(i.read) - i.startADC 0x08000518 Section 0 myadc.o(i.startADC) - .data 0x20000000 Section 4 main.o(.data) - .data 0x20000004 Section 16 mytimer.o(.data) - STACK 0x20000018 Section 1024 startup_stm32f10x_md.o(STACK) - - Global Symbols - - Symbol Name Value Ov Type Size Object(Section) - - BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE - __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE - __arm_fini_ - Undefined Weak Reference - __cpp_initialize__aeabi_ - Undefined Weak Reference - __cxa_finalize - Undefined Weak Reference - __decompress - Undefined Weak Reference - _clock_init - Undefined Weak Reference - _microlib_exit - Undefined Weak Reference - __Vectors_Size 0x000000ec Number 0 startup_stm32f10x_md.o ABSOLUTE - __Vectors 0x08000000 Data 4 startup_stm32f10x_md.o(RESET) - __Vectors_End 0x080000ec Data 0 startup_stm32f10x_md.o(RESET) - __main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) - _main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) - _main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) - __main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) - _main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) - _main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) - _main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) - __rt_lib_shutdown_fini 0x080000fd Thumb Code 0 entry12b.o(.ARM.Collect$$$$0000000E) - __rt_final_cpp 0x08000101 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000F) - __rt_final_exit 0x08000101 Thumb Code 0 entry11a.o(.ARM.Collect$$$$00000011) - Reset_Handler 0x08000105 Thumb Code 8 startup_stm32f10x_md.o(.text) - NMI_Handler 0x0800010d Thumb Code 2 startup_stm32f10x_md.o(.text) - HardFault_Handler 0x0800010f Thumb Code 2 startup_stm32f10x_md.o(.text) - MemManage_Handler 0x08000111 Thumb Code 2 startup_stm32f10x_md.o(.text) - BusFault_Handler 0x08000113 Thumb Code 2 startup_stm32f10x_md.o(.text) - UsageFault_Handler 0x08000115 Thumb Code 2 startup_stm32f10x_md.o(.text) - SVC_Handler 0x08000117 Thumb Code 2 startup_stm32f10x_md.o(.text) - DebugMon_Handler 0x08000119 Thumb Code 2 startup_stm32f10x_md.o(.text) - PendSV_Handler 0x0800011b Thumb Code 2 startup_stm32f10x_md.o(.text) - SysTick_Handler 0x0800011d Thumb Code 2 startup_stm32f10x_md.o(.text) - ADC1_2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - CAN1_RX1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - CAN1_SCE_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel6_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel7_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI15_10_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI9_5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - FLASH_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - I2C1_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - I2C1_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - I2C2_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - I2C2_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - PVD_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - RCC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - RTCAlarm_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - RTC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - SPI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - SPI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - TAMPER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - TIM1_BRK_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - TIM1_CC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - TIM1_TRG_COM_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USART1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USART2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USART3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USBWakeUp_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USB_HP_CAN1_TX_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USB_LP_CAN1_RX0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - WWDG_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - __scatterload 0x08000129 Thumb Code 28 init.o(.text) - __scatterload_rt2 0x08000129 Thumb Code 0 init.o(.text) - Callback 0x0800014d Thumb Code 16 main.o(i.Callback) - MyTimer_ActiveIT 0x08000161 Thumb Code 148 mytimer.o(i.MyTimer_ActiveIT) - MyTimer_Base_Init 0x08000211 Thumb Code 98 mytimer.o(i.MyTimer_Base_Init) - MyTimer_Base_Start 0x0800027d Thumb Code 10 mytimer.o(i.MyTimer_Base_Start) - SystemInit 0x08000371 Thumb Code 78 system_stm32f10x.o(i.SystemInit) - TIM1_UP_IRQHandler 0x080003d1 Thumb Code 28 mytimer.o(i.TIM1_UP_IRQHandler) - TIM2_IRQHandler 0x080003f5 Thumb Code 32 mytimer.o(i.TIM2_IRQHandler) - TIM3_IRQHandler 0x08000419 Thumb Code 28 mytimer.o(i.TIM3_IRQHandler) - TIM4_IRQHandler 0x0800043d Thumb Code 28 mytimer.o(i.TIM4_IRQHandler) - __scatterload_copy 0x08000461 Thumb Code 14 handlers.o(i.__scatterload_copy) - __scatterload_null 0x0800046f Thumb Code 2 handlers.o(i.__scatterload_null) - __scatterload_zeroinit 0x08000471 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) - initADC 0x08000481 Thumb Code 50 myadc.o(i.initADC) - main 0x080004bd Thumb Code 56 main.o(i.main) - read 0x080004f9 Thumb Code 26 myadc.o(i.read) - startADC 0x08000519 Thumb Code 14 myadc.o(i.startADC) - Region$$Table$$Base 0x0800052c Number 0 anon$$obj.o(Region$$Table) - Region$$Table$$Limit 0x0800054c Number 0 anon$$obj.o(Region$$Table) - a 0x20000000 Data 4 main.o(.data) - ptr1 0x20000004 Data 4 mytimer.o(.data) - ptr2 0x20000008 Data 4 mytimer.o(.data) - ptr3 0x2000000c Data 4 mytimer.o(.data) - ptr4 0x20000010 Data 4 mytimer.o(.data) - __initial_sp 0x20000418 Data 0 startup_stm32f10x_md.o(STACK) - - - -============================================================================== - -Memory Map of the image - - Image Entry point : 0x08000105 - - Load Region LR_1 (Base: 0x08000000, Size: 0x00000560, Max: 0xffffffff, ABSOLUTE) - - Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000054c, Max: 0xffffffff, ABSOLUTE) - - Exec Addr Load Addr Size Type Attr Idx E Section Name Object - - 0x08000000 0x08000000 0x000000ec Data RO 293 RESET startup_stm32f10x_md.o - 0x080000ec 0x080000ec 0x00000000 Code RO 344 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) - 0x080000ec 0x080000ec 0x00000004 Code RO 347 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) - 0x080000f0 0x080000f0 0x00000004 Code RO 350 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) - 0x080000f4 0x080000f4 0x00000000 Code RO 352 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) - 0x080000f4 0x080000f4 0x00000000 Code RO 354 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) - 0x080000f4 0x080000f4 0x00000008 Code RO 355 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) - 0x080000fc 0x080000fc 0x00000004 Code RO 362 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o) - 0x08000100 0x08000100 0x00000000 Code RO 357 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o) - 0x08000100 0x08000100 0x00000000 Code RO 359 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o) - 0x08000100 0x08000100 0x00000004 Code RO 348 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) - 0x08000104 0x08000104 0x00000024 Code RO 294 * .text startup_stm32f10x_md.o - 0x08000128 0x08000128 0x00000024 Code RO 363 .text mc_w.l(init.o) - 0x0800014c 0x0800014c 0x00000014 Code RO 4 i.Callback main.o - 0x08000160 0x08000160 0x000000b0 Code RO 127 i.MyTimer_ActiveIT mytimer.o - 0x08000210 0x08000210 0x0000006c Code RO 128 i.MyTimer_Base_Init mytimer.o - 0x0800027c 0x0800027c 0x0000000a Code RO 129 i.MyTimer_Base_Start mytimer.o - 0x08000286 0x08000286 0x00000008 Code RO 301 i.SetSysClock system_stm32f10x.o - 0x0800028e 0x0800028e 0x00000002 PAD - 0x08000290 0x08000290 0x000000e0 Code RO 302 i.SetSysClockTo72 system_stm32f10x.o - 0x08000370 0x08000370 0x00000060 Code RO 304 i.SystemInit system_stm32f10x.o - 0x080003d0 0x080003d0 0x00000024 Code RO 134 i.TIM1_UP_IRQHandler mytimer.o - 0x080003f4 0x080003f4 0x00000024 Code RO 135 i.TIM2_IRQHandler mytimer.o - 0x08000418 0x08000418 0x00000024 Code RO 136 i.TIM3_IRQHandler mytimer.o - 0x0800043c 0x0800043c 0x00000024 Code RO 137 i.TIM4_IRQHandler mytimer.o - 0x08000460 0x08000460 0x0000000e Code RO 367 i.__scatterload_copy mc_w.l(handlers.o) - 0x0800046e 0x0800046e 0x00000002 Code RO 368 i.__scatterload_null mc_w.l(handlers.o) - 0x08000470 0x08000470 0x0000000e Code RO 369 i.__scatterload_zeroinit mc_w.l(handlers.o) - 0x0800047e 0x0800047e 0x00000002 PAD - 0x08000480 0x08000480 0x0000003c Code RO 225 i.initADC myadc.o - 0x080004bc 0x080004bc 0x0000003c Code RO 5 i.main main.o - 0x080004f8 0x080004f8 0x00000020 Code RO 226 i.read myadc.o - 0x08000518 0x08000518 0x00000014 Code RO 227 i.startADC myadc.o - 0x0800052c 0x0800052c 0x00000020 Data RO 365 Region$$Table anon$$obj.o - - - Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x0800054c, Size: 0x00000014, Max: 0xffffffff, ABSOLUTE) - - Exec Addr Load Addr Size Type Attr Idx E Section Name Object - - 0x20000000 0x0800054c 0x00000004 Data RW 6 .data main.o - 0x20000004 0x08000550 0x00000010 Data RW 138 .data mytimer.o - - - Execution Region ER_ZI (Exec base: 0x20000014, Load base: 0x08000560, Size: 0x00000404, Max: 0xffffffff, ABSOLUTE) - - Exec Addr Load Addr Size Type Attr Idx E Section Name Object - - 0x20000014 0x08000560 0x00000004 PAD - 0x20000018 - 0x00000400 Zero RW 291 STACK startup_stm32f10x_md.o - - -============================================================================== - -Image component sizes - - - Code (inc. data) RO Data RW Data ZI Data Debug Object Name - - 80 8 0 4 0 208294 main.o - 112 22 0 0 0 1280 myadc.o - 438 66 0 16 0 4557 mytimer.o - 36 8 236 0 1024 808 startup_stm32f10x_md.o - 328 28 0 0 0 1973 system_stm32f10x.o - - ---------------------------------------------------------------------- - 996 132 268 20 1028 216912 Object Totals - 0 0 32 0 0 0 (incl. Generated) - 2 0 0 0 4 0 (incl. Padding) - - ---------------------------------------------------------------------- - - Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name - - 0 0 0 0 0 0 entry.o - 0 0 0 0 0 0 entry10a.o - 0 0 0 0 0 0 entry11a.o - 4 0 0 0 0 0 entry12b.o - 8 4 0 0 0 0 entry2.o - 4 0 0 0 0 0 entry5.o - 0 0 0 0 0 0 entry7b.o - 0 0 0 0 0 0 entry8b.o - 8 4 0 0 0 0 entry9a.o - 30 0 0 0 0 0 handlers.o - 36 8 0 0 0 68 init.o - - ---------------------------------------------------------------------- - 92 16 0 0 0 68 Library Totals - 2 0 0 0 0 0 (incl. Padding) - - ---------------------------------------------------------------------- - - Code (inc. data) RO Data RW Data ZI Data Debug Library Name - - 90 16 0 0 0 68 mc_w.l - - ---------------------------------------------------------------------- - 92 16 0 0 0 68 Library Totals - - ---------------------------------------------------------------------- - -============================================================================== - - - Code (inc. data) RO Data RW Data ZI Data Debug - - 1088 148 268 20 1028 216508 Grand Totals - 1088 148 268 20 1028 216508 ELF Image Totals - 1088 148 268 20 0 0 ROM Totals - -============================================================================== - - Total RO Size (Code + RO Data) 1356 ( 1.32kB) - Total RW Size (RW Data + ZI Data) 1048 ( 1.02kB) - Total ROM Size (Code + RO Data + RW Data) 1376 ( 1.34kB) - -============================================================================== - +Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601] + +============================================================================== + +Section Cross References + + main.o(i.main) refers to plateau.o(i.Set_Moteur_Plateau) for Set_Moteur_Plateau + mytimer.o(i.MyTimer_ActiveIT) refers to mytimer.o(.data) for ptr1 + mytimer.o(i.MyTimer_PWM) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init + mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(.data) for ptr1 + mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(.data) for ptr2 + mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(.data) for ptr3 + mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(.data) for ptr4 + plateau.o(i.Init_Plateau) refers to mytimer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init + plateau.o(i.Init_Plateau) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init + plateau.o(i.Init_Plateau) refers to mytimer.o(i.MyTimer_Base_Start) for MyTimer_Base_Start + plateau.o(i.Init_Plateau) refers to mytimer.o(i.MyTimer_PWM) for MyTimer_PWM + plateau.o(i.Init_Plateau) refers to plateau.o(.data) for Data + plateau.o(i.Init_Plateau) refers to plateau.o(.bss) for GPIOA5 + plateau.o(i.Set_Direction) refers to driver_gpio.o(i.MyGPIO_Reset) for MyGPIO_Reset + plateau.o(i.Set_Direction) refers to driver_gpio.o(i.MyGPIO_Set) for MyGPIO_Set + plateau.o(i.Set_Direction) refers to plateau.o(.bss) for GPIOA5 + plateau.o(i.Set_Moteur_Plateau) refers to plateau.o(i.Init_Plateau) for Init_Plateau + plateau.o(i.Set_Moteur_Plateau) refers to plateau.o(i.Set_Direction) for Set_Direction + plateau.o(i.Set_Moteur_Plateau) refers to plateau.o(i.Set_Vitesse) for Set_Vitesse + plateau.o(i.Set_Vitesse) refers to mytimer.o(i.Set_PWM_PRCT) for Set_PWM_PRCT + plateau.o(i.Set_Vitesse) refers to plateau.o(.data) for Data + startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp + startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler + startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler + startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler + startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler + startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler + startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit + startup_stm32f10x_md.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main + system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72 + system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock + system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000F) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$00000011) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry12b.o(.ARM.Collect$$$$0000000E) for __rt_lib_shutdown_fini + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_md.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_md.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main + init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.rev16_text), (4 bytes). + Removing main.o(.revsh_text), (4 bytes). + Removing main.o(.rrx_text), (6 bytes). + Removing driver_gpio.o(.rev16_text), (4 bytes). + Removing driver_gpio.o(.revsh_text), (4 bytes). + Removing driver_gpio.o(.rrx_text), (6 bytes). + Removing driver_gpio.o(i.MyGPIO_Read), (12 bytes). + Removing driver_gpio.o(i.MyGPIO_Toggle), (12 bytes). + Removing mytimer.o(.rev16_text), (4 bytes). + Removing mytimer.o(.revsh_text), (4 bytes). + Removing mytimer.o(.rrx_text), (6 bytes). + Removing mytimer.o(i.Get_Max_Duty), (6 bytes). + Removing mytimer.o(i.MyTimer_ActiveIT), (176 bytes). + Removing mytimer.o(i.MyTimer_Base_Stop), (10 bytes). + Removing mytimer.o(i.Set_Duty_Cycle), (40 bytes). + Removing myadc.o(.rev16_text), (4 bytes). + Removing myadc.o(.revsh_text), (4 bytes). + Removing myadc.o(.rrx_text), (6 bytes). + Removing myadc.o(i.initADC), (60 bytes). + Removing myadc.o(i.read), (32 bytes). + Removing myadc.o(i.startADC), (20 bytes). + Removing plateau.o(.rev16_text), (4 bytes). + Removing plateau.o(.revsh_text), (4 bytes). + Removing plateau.o(.rrx_text), (6 bytes). + Removing startup_stm32f10x_md.o(HEAP), (512 bytes). + Removing system_stm32f10x.o(.rev16_text), (4 bytes). + Removing system_stm32f10x.o(.revsh_text), (4 bytes). + Removing system_stm32f10x.o(.rrx_text), (6 bytes). + Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes). + Removing system_stm32f10x.o(.data), (20 bytes). + +30 unused section(s) (total 1148 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + FileInclude\MyADC.c 0x00000000 Number 0 myadc.o ABSOLUTE + FileInclude\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE + FileInclude\Plateau.c 0x00000000 Number 0 plateau.o ABSOLUTE + FileInclude\Telecommande.c 0x00000000 Number 0 telecommande.o ABSOLUTE + FileInclude\\MyADC.c 0x00000000 Number 0 myadc.o ABSOLUTE + FileInclude\\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE + FileInclude\\Plateau.c 0x00000000 Number 0 plateau.o ABSOLUTE + RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE + RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + Sources\\main.c 0x00000000 Number 0 main.o ABSOLUTE + Sources\main.c 0x00000000 Number 0 main.o ABSOLUTE + U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE + U:\\Documents\\4ir\\S1\\Microcontroleur\\Drivers\\FileInclude\\Driver_GPIO.c 0x00000000 Number 0 driver_gpio.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + init.s 0x00000000 Number 0 init.o ABSOLUTE + RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET) + .ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000) + .ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001) + .ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004) + .ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008) + .ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) + .ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) + .ARM.Collect$$$$0000000E 0x080000fc Section 4 entry12b.o(.ARM.Collect$$$$0000000E) + .ARM.Collect$$$$0000000F 0x08000100 Section 0 entry10a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$00000011 0x08000100 Section 0 entry11a.o(.ARM.Collect$$$$00000011) + .ARM.Collect$$$$00002712 0x08000100 Section 4 entry2.o(.ARM.Collect$$$$00002712) + __lit__00000000 0x08000100 Data 4 entry2.o(.ARM.Collect$$$$00002712) + .text 0x08000104 Section 36 startup_stm32f10x_md.o(.text) + .text 0x08000128 Section 36 init.o(.text) + i.Init_Plateau 0x0800014c Section 0 plateau.o(i.Init_Plateau) + i.MyGPIO_Init 0x080001c8 Section 0 driver_gpio.o(i.MyGPIO_Init) + i.MyGPIO_Reset 0x0800027c Section 0 driver_gpio.o(i.MyGPIO_Reset) + i.MyGPIO_Set 0x0800028a Section 0 driver_gpio.o(i.MyGPIO_Set) + i.MyTimer_Base_Init 0x08000298 Section 0 mytimer.o(i.MyTimer_Base_Init) + i.MyTimer_Base_Start 0x08000304 Section 0 mytimer.o(i.MyTimer_Base_Start) + i.MyTimer_PWM 0x08000310 Section 0 mytimer.o(i.MyTimer_PWM) + i.SetSysClock 0x080004e0 Section 0 system_stm32f10x.o(i.SetSysClock) + SetSysClock 0x080004e1 Thumb Code 8 system_stm32f10x.o(i.SetSysClock) + i.SetSysClockTo72 0x080004e8 Section 0 system_stm32f10x.o(i.SetSysClockTo72) + SetSysClockTo72 0x080004e9 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72) + i.Set_Direction 0x080005c8 Section 0 plateau.o(i.Set_Direction) + i.Set_Moteur_Plateau 0x080005f0 Section 0 plateau.o(i.Set_Moteur_Plateau) + i.Set_PWM_PRCT 0x08000608 Section 0 mytimer.o(i.Set_PWM_PRCT) + i.Set_Vitesse 0x08000640 Section 0 plateau.o(i.Set_Vitesse) + i.SystemInit 0x08000660 Section 0 system_stm32f10x.o(i.SystemInit) + i.TIM1_UP_IRQHandler 0x080006c0 Section 0 mytimer.o(i.TIM1_UP_IRQHandler) + i.TIM2_IRQHandler 0x080006e4 Section 0 mytimer.o(i.TIM2_IRQHandler) + i.TIM3_IRQHandler 0x08000708 Section 0 mytimer.o(i.TIM3_IRQHandler) + i.TIM4_IRQHandler 0x0800072c Section 0 mytimer.o(i.TIM4_IRQHandler) + i.__scatterload_copy 0x08000750 Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x0800075e Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x08000760 Section 14 handlers.o(i.__scatterload_zeroinit) + i.main 0x0800076e Section 0 main.o(i.main) + .data 0x20000000 Section 16 mytimer.o(.data) + .data 0x20000010 Section 16 plateau.o(.data) + .bss 0x20000020 Section 24 plateau.o(.bss) + STACK 0x20000038 Section 1024 startup_stm32f10x_md.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + __arm_fini_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __decompress - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + __Vectors_Size 0x000000ec Number 0 startup_stm32f10x_md.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f10x_md.o(RESET) + __Vectors_End 0x080000ec Data 0 startup_stm32f10x_md.o(RESET) + __main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + __main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + _main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) + __rt_lib_shutdown_fini 0x080000fd Thumb Code 0 entry12b.o(.ARM.Collect$$$$0000000E) + __rt_final_cpp 0x08000101 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000F) + __rt_final_exit 0x08000101 Thumb Code 0 entry11a.o(.ARM.Collect$$$$00000011) + Reset_Handler 0x08000105 Thumb Code 8 startup_stm32f10x_md.o(.text) + NMI_Handler 0x0800010d Thumb Code 2 startup_stm32f10x_md.o(.text) + HardFault_Handler 0x0800010f Thumb Code 2 startup_stm32f10x_md.o(.text) + MemManage_Handler 0x08000111 Thumb Code 2 startup_stm32f10x_md.o(.text) + BusFault_Handler 0x08000113 Thumb Code 2 startup_stm32f10x_md.o(.text) + UsageFault_Handler 0x08000115 Thumb Code 2 startup_stm32f10x_md.o(.text) + SVC_Handler 0x08000117 Thumb Code 2 startup_stm32f10x_md.o(.text) + DebugMon_Handler 0x08000119 Thumb Code 2 startup_stm32f10x_md.o(.text) + PendSV_Handler 0x0800011b Thumb Code 2 startup_stm32f10x_md.o(.text) + SysTick_Handler 0x0800011d Thumb Code 2 startup_stm32f10x_md.o(.text) + ADC1_2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + CAN1_RX1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + CAN1_SCE_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel6_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel7_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI15_10_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI9_5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + FLASH_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C1_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C1_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C2_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C2_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + PVD_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + RCC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + RTCAlarm_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + RTC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + SPI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + SPI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + TAMPER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_BRK_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_CC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_TRG_COM_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + USART1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + USART2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + USART3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + USBWakeUp_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + USB_HP_CAN1_TX_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + USB_LP_CAN1_RX0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + WWDG_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) + __scatterload 0x08000129 Thumb Code 28 init.o(.text) + __scatterload_rt2 0x08000129 Thumb Code 0 init.o(.text) + Init_Plateau 0x0800014d Thumb Code 98 plateau.o(i.Init_Plateau) + MyGPIO_Init 0x080001c9 Thumb Code 166 driver_gpio.o(i.MyGPIO_Init) + MyGPIO_Reset 0x0800027d Thumb Code 14 driver_gpio.o(i.MyGPIO_Reset) + MyGPIO_Set 0x0800028b Thumb Code 12 driver_gpio.o(i.MyGPIO_Set) + MyTimer_Base_Init 0x08000299 Thumb Code 98 mytimer.o(i.MyTimer_Base_Init) + MyTimer_Base_Start 0x08000305 Thumb Code 10 mytimer.o(i.MyTimer_Base_Start) + MyTimer_PWM 0x08000311 Thumb Code 448 mytimer.o(i.MyTimer_PWM) + Set_Direction 0x080005c9 Thumb Code 34 plateau.o(i.Set_Direction) + Set_Moteur_Plateau 0x080005f1 Thumb Code 24 plateau.o(i.Set_Moteur_Plateau) + Set_PWM_PRCT 0x08000609 Thumb Code 56 mytimer.o(i.Set_PWM_PRCT) + Set_Vitesse 0x08000641 Thumb Code 22 plateau.o(i.Set_Vitesse) + SystemInit 0x08000661 Thumb Code 78 system_stm32f10x.o(i.SystemInit) + TIM1_UP_IRQHandler 0x080006c1 Thumb Code 28 mytimer.o(i.TIM1_UP_IRQHandler) + TIM2_IRQHandler 0x080006e5 Thumb Code 32 mytimer.o(i.TIM2_IRQHandler) + TIM3_IRQHandler 0x08000709 Thumb Code 28 mytimer.o(i.TIM3_IRQHandler) + TIM4_IRQHandler 0x0800072d Thumb Code 28 mytimer.o(i.TIM4_IRQHandler) + __scatterload_copy 0x08000751 Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x0800075f Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x08000761 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + main 0x0800076f Thumb Code 12 main.o(i.main) + Region$$Table$$Base 0x0800077c Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0800079c Number 0 anon$$obj.o(Region$$Table) + ptr1 0x20000000 Data 4 mytimer.o(.data) + ptr2 0x20000004 Data 4 mytimer.o(.data) + ptr3 0x20000008 Data 4 mytimer.o(.data) + ptr4 0x2000000c Data 4 mytimer.o(.data) + channel 0x20000010 Data 1 plateau.o(.data) + TIM 0x20000014 Data 8 plateau.o(.data) + Data 0x2000001c Data 4 plateau.o(.data) + GPIOA5 0x20000020 Data 12 plateau.o(.bss) + GPIOA6 0x2000002c Data 12 plateau.o(.bss) + __initial_sp 0x20000438 Data 0 startup_stm32f10x_md.o(STACK) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000105 + + Load Region LR_1 (Base: 0x08000000, Size: 0x000007bc, Max: 0xffffffff, ABSOLUTE) + + Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000079c, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x000000ec Data RO 309 RESET startup_stm32f10x_md.o + 0x080000ec 0x080000ec 0x00000000 Code RO 360 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x080000ec 0x080000ec 0x00000004 Code RO 363 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x080000f0 0x080000f0 0x00000004 Code RO 366 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x080000f4 0x080000f4 0x00000000 Code RO 368 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x080000f4 0x080000f4 0x00000000 Code RO 370 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x080000f4 0x080000f4 0x00000008 Code RO 371 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x080000fc 0x080000fc 0x00000004 Code RO 378 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o) + 0x08000100 0x08000100 0x00000000 Code RO 373 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o) + 0x08000100 0x08000100 0x00000000 Code RO 375 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o) + 0x08000100 0x08000100 0x00000004 Code RO 364 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x08000104 0x08000104 0x00000024 Code RO 310 * .text startup_stm32f10x_md.o + 0x08000128 0x08000128 0x00000024 Code RO 379 .text mc_w.l(init.o) + 0x0800014c 0x0800014c 0x0000007c Code RO 258 i.Init_Plateau plateau.o + 0x080001c8 0x080001c8 0x000000b4 Code RO 69 i.MyGPIO_Init driver_gpio.o + 0x0800027c 0x0800027c 0x0000000e Code RO 71 i.MyGPIO_Reset driver_gpio.o + 0x0800028a 0x0800028a 0x0000000c Code RO 72 i.MyGPIO_Set driver_gpio.o + 0x08000296 0x08000296 0x00000002 PAD + 0x08000298 0x08000298 0x0000006c Code RO 122 i.MyTimer_Base_Init mytimer.o + 0x08000304 0x08000304 0x0000000a Code RO 123 i.MyTimer_Base_Start mytimer.o + 0x0800030e 0x0800030e 0x00000002 PAD + 0x08000310 0x08000310 0x000001d0 Code RO 125 i.MyTimer_PWM mytimer.o + 0x080004e0 0x080004e0 0x00000008 Code RO 317 i.SetSysClock system_stm32f10x.o + 0x080004e8 0x080004e8 0x000000e0 Code RO 318 i.SetSysClockTo72 system_stm32f10x.o + 0x080005c8 0x080005c8 0x00000028 Code RO 259 i.Set_Direction plateau.o + 0x080005f0 0x080005f0 0x00000018 Code RO 260 i.Set_Moteur_Plateau plateau.o + 0x08000608 0x08000608 0x00000038 Code RO 127 i.Set_PWM_PRCT mytimer.o + 0x08000640 0x08000640 0x00000020 Code RO 261 i.Set_Vitesse plateau.o + 0x08000660 0x08000660 0x00000060 Code RO 320 i.SystemInit system_stm32f10x.o + 0x080006c0 0x080006c0 0x00000024 Code RO 128 i.TIM1_UP_IRQHandler mytimer.o + 0x080006e4 0x080006e4 0x00000024 Code RO 129 i.TIM2_IRQHandler mytimer.o + 0x08000708 0x08000708 0x00000024 Code RO 130 i.TIM3_IRQHandler mytimer.o + 0x0800072c 0x0800072c 0x00000024 Code RO 131 i.TIM4_IRQHandler mytimer.o + 0x08000750 0x08000750 0x0000000e Code RO 383 i.__scatterload_copy mc_w.l(handlers.o) + 0x0800075e 0x0800075e 0x00000002 Code RO 384 i.__scatterload_null mc_w.l(handlers.o) + 0x08000760 0x08000760 0x0000000e Code RO 385 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x0800076e 0x0800076e 0x0000000c Code RO 4 i.main main.o + 0x0800077a 0x0800077a 0x00000002 PAD + 0x0800077c 0x0800077c 0x00000020 Data RO 381 Region$$Table anon$$obj.o + + + Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x0800079c, Size: 0x00000020, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x0800079c 0x00000010 Data RW 132 .data mytimer.o + 0x20000010 0x080007ac 0x00000010 Data RW 263 .data plateau.o + + + Execution Region ER_ZI (Exec base: 0x20000020, Load base: 0x080007bc, Size: 0x00000418, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000020 - 0x00000018 Zero RW 262 .bss plateau.o + 0x20000038 - 0x00000400 Zero RW 307 STACK startup_stm32f10x_md.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 206 14 0 0 0 2722 driver_gpio.o + 12 0 0 0 0 206767 main.o + 782 54 0 16 0 6027 mytimer.o + 220 42 0 16 24 2755 plateau.o + 36 8 236 0 1024 808 startup_stm32f10x_md.o + 328 28 0 0 0 1973 system_stm32f10x.o + + ---------------------------------------------------------------------- + 1590 146 268 32 1048 221052 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 6 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 4 0 0 0 0 0 entry12b.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 8 4 0 0 0 0 entry9a.o + 30 0 0 0 0 0 handlers.o + 36 8 0 0 0 68 init.o + + ---------------------------------------------------------------------- + 90 16 0 0 0 68 Library Totals + 0 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 90 16 0 0 0 68 mc_w.l + + ---------------------------------------------------------------------- + 90 16 0 0 0 68 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 1680 162 268 32 1048 220388 Grand Totals + 1680 162 268 32 1048 220388 ELF Image Totals + 1680 162 268 32 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 1948 ( 1.90kB) + Total RW Size (RW Data + ZI Data) 1080 ( 1.05kB) + Total ROM Size (Code + RO Data + RW Data) 1980 ( 1.93kB) + +============================================================================== + diff --git a/Listings/startup_stm32f10x_md.lst b/Listings/startup_stm32f10x_md.lst index 7398f8f..37414f5 100644 --- a/Listings/startup_stm32f10x_md.lst +++ b/Listings/startup_stm32f10x_md.lst @@ -1,1180 +1,1180 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron - ics ******************** - 2 00000000 ;* File Name : startup_stm32f10x_md.s - 3 00000000 ;* Author : MCD Application Team - 4 00000000 ;* Version : V3.5.0 - 5 00000000 ;* Date : 11-March-2011 - 6 00000000 ;* Description : STM32F10x Medium Density Devices - vector table for MDK-ARM - 7 00000000 ;* toolchain. - 8 00000000 ;* This module performs: - 9 00000000 ;* - Set the initial SP - 10 00000000 ;* - Set the initial PC == Reset_Ha - ndler - 11 00000000 ;* - Set the vector table entries w - ith the exceptions ISR address - 12 00000000 ;* - Configure the clock system - 13 00000000 ;* - Branches to __main in the C li - brary (which eventually - 14 00000000 ;* calls main()). - 15 00000000 ;* After Reset the CortexM3 process - or is in Thread mode, - 16 00000000 ;* priority is Privileged, and the - Stack is set to Main. - 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> - 18 00000000 ;******************************************************* - ************************ - 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A - T PROVIDING CUSTOMERS - 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR - DER FOR THEM TO SAVE TIME. - 21 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB - LE FOR ANY DIRECT, - 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY - CLAIMS ARISING FROM THE - 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM - ERS OF THE CODING - 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR - PRODUCTS. - 25 00000000 ;******************************************************* - ************************ - 26 00000000 - 27 00000000 ; Amount of memory (in bytes) allocated for Stack - 28 00000000 ; Tailor this value to your application needs - 29 00000000 ; Stack Configuration - 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - 31 00000000 ; - 32 00000000 - 33 00000000 00000400 - Stack_Size - EQU 0x00000400 - 34 00000000 - 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN -=3 - 36 00000000 Stack_Mem - SPACE Stack_Size - 37 00000400 __initial_sp - 38 00000400 - 39 00000400 - 40 00000400 ; Heap Configuration - - - -ARM Macro Assembler Page 2 - - - 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - 42 00000400 ; - 43 00000400 - 44 00000400 00000200 - Heap_Size - EQU 0x00000200 - 45 00000400 - 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= -3 - 47 00000000 __heap_base - 48 00000000 Heap_Mem - SPACE Heap_Size - 49 00000200 __heap_limit - 50 00000200 - 51 00000200 PRESERVE8 - 52 00000200 THUMB - 53 00000200 - 54 00000200 - 55 00000200 ; Vector Table Mapped to Address 0 at Reset - 56 00000200 AREA RESET, DATA, READONLY - 57 00000000 EXPORT __Vectors - 58 00000000 EXPORT __Vectors_End - 59 00000000 EXPORT __Vectors_Size - 60 00000000 - 61 00000000 00000000 - __Vectors - DCD __initial_sp ; Top of Stack - 62 00000004 00000000 DCD Reset_Handler ; Reset Handler - 63 00000008 00000000 DCD NMI_Handler ; NMI Handler - 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault - Handler - 65 00000010 00000000 DCD MemManage_Handler - ; MPU Fault Handler - - 66 00000014 00000000 DCD BusFault_Handler - ; Bus Fault Handler - - 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul - t Handler - 68 0000001C 00000000 DCD 0 ; Reserved - 69 00000020 00000000 DCD 0 ; Reserved - 70 00000024 00000000 DCD 0 ; Reserved - 71 00000028 00000000 DCD 0 ; Reserved - 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler - 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito - r Handler - 74 00000034 00000000 DCD 0 ; Reserved - 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler - - 76 0000003C 00000000 DCD SysTick_Handler - ; SysTick Handler - 77 00000040 - 78 00000040 ; External Interrupts - 79 00000040 00000000 DCD WWDG_IRQHandler - ; Window Watchdog - 80 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX - TI Line detect - 81 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper - 82 0000004C 00000000 DCD RTC_IRQHandler ; RTC - - - -ARM Macro Assembler Page 3 - - - 83 00000050 00000000 DCD FLASH_IRQHandler ; Flash - 84 00000054 00000000 DCD RCC_IRQHandler ; RCC - 85 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0 - 86 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1 - 87 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2 - 88 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3 - 89 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4 - 90 0000006C 00000000 DCD DMA1_Channel1_IRQHandler - ; DMA1 Channel 1 - 91 00000070 00000000 DCD DMA1_Channel2_IRQHandler - ; DMA1 Channel 2 - 92 00000074 00000000 DCD DMA1_Channel3_IRQHandler - ; DMA1 Channel 3 - 93 00000078 00000000 DCD DMA1_Channel4_IRQHandler - ; DMA1 Channel 4 - 94 0000007C 00000000 DCD DMA1_Channel5_IRQHandler - ; DMA1 Channel 5 - 95 00000080 00000000 DCD DMA1_Channel6_IRQHandler - ; DMA1 Channel 6 - 96 00000084 00000000 DCD DMA1_Channel7_IRQHandler - ; DMA1 Channel 7 - 97 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1_2 - 98 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB - High Priority or C - AN1 TX - 99 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US - B Low Priority or - CAN1 RX0 - 100 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - 101 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE - 102 0000009C 00000000 DCD EXTI9_5_IRQHandler - ; EXTI Line 9..5 - 103 000000A0 00000000 DCD TIM1_BRK_IRQHandler - ; TIM1 Break - 104 000000A4 00000000 DCD TIM1_UP_IRQHandler - ; TIM1 Update - 105 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 - Trigger and Commuta - tion - 106 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu - re Compare - 107 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 - 108 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 - 109 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 - 110 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event - - 111 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error - - 112 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event - - 113 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error - - 114 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 - 115 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 - 116 000000D4 00000000 DCD USART1_IRQHandler ; USART1 - 117 000000D8 00000000 DCD USART2_IRQHandler ; USART2 - 118 000000DC 00000000 DCD USART3_IRQHandler ; USART3 - 119 000000E0 00000000 DCD EXTI15_10_IRQHandler - ; EXTI Line 15..10 - - - -ARM Macro Assembler Page 4 - - - 120 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm - through EXTI Line - 121 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake - up from suspend - 122 000000EC __Vectors_End - 123 000000EC - 124 000000EC 000000EC - __Vectors_Size - EQU __Vectors_End - __Vectors - 125 000000EC - 126 000000EC AREA |.text|, CODE, READONLY - 127 00000000 - 128 00000000 ; Reset handler - 129 00000000 Reset_Handler - PROC - 130 00000000 EXPORT Reset_Handler [WEAK -] - 131 00000000 IMPORT __main - 132 00000000 IMPORT SystemInit - 133 00000000 4806 LDR R0, =SystemInit - 134 00000002 4780 BLX R0 - 135 00000004 4806 LDR R0, =__main - 136 00000006 4700 BX R0 - 137 00000008 ENDP - 138 00000008 - 139 00000008 ; Dummy Exception Handlers (infinite loops which can be - modified) - 140 00000008 - 141 00000008 NMI_Handler - PROC - 142 00000008 EXPORT NMI_Handler [WEA -K] - 143 00000008 E7FE B . - 144 0000000A ENDP - 146 0000000A HardFault_Handler - PROC - 147 0000000A EXPORT HardFault_Handler [WEA -K] - 148 0000000A E7FE B . - 149 0000000C ENDP - 151 0000000C MemManage_Handler - PROC - 152 0000000C EXPORT MemManage_Handler [WEA -K] - 153 0000000C E7FE B . - 154 0000000E ENDP - 156 0000000E BusFault_Handler - PROC - 157 0000000E EXPORT BusFault_Handler [WEA -K] - 158 0000000E E7FE B . - 159 00000010 ENDP - 161 00000010 UsageFault_Handler - PROC - 162 00000010 EXPORT UsageFault_Handler [WEA -K] - 163 00000010 E7FE B . - 164 00000012 ENDP - 165 00000012 SVC_Handler - - - -ARM Macro Assembler Page 5 - - - PROC - 166 00000012 EXPORT SVC_Handler [WEA -K] - 167 00000012 E7FE B . - 168 00000014 ENDP - 170 00000014 DebugMon_Handler - PROC - 171 00000014 EXPORT DebugMon_Handler [WEA -K] - 172 00000014 E7FE B . - 173 00000016 ENDP - 174 00000016 PendSV_Handler - PROC - 175 00000016 EXPORT PendSV_Handler [WEA -K] - 176 00000016 E7FE B . - 177 00000018 ENDP - 178 00000018 SysTick_Handler - PROC - 179 00000018 EXPORT SysTick_Handler [WEA -K] - 180 00000018 E7FE B . - 181 0000001A ENDP - 182 0000001A - 183 0000001A Default_Handler - PROC - 184 0000001A - 185 0000001A EXPORT WWDG_IRQHandler [WEA -K] - 186 0000001A EXPORT PVD_IRQHandler [WEA -K] - 187 0000001A EXPORT TAMPER_IRQHandler [WEA -K] - 188 0000001A EXPORT RTC_IRQHandler [WEA -K] - 189 0000001A EXPORT FLASH_IRQHandler [WEA -K] - 190 0000001A EXPORT RCC_IRQHandler [WEA -K] - 191 0000001A EXPORT EXTI0_IRQHandler [WEA -K] - 192 0000001A EXPORT EXTI1_IRQHandler [WEA -K] - 193 0000001A EXPORT EXTI2_IRQHandler [WEA -K] - 194 0000001A EXPORT EXTI3_IRQHandler [WEA -K] - 195 0000001A EXPORT EXTI4_IRQHandler [WEA -K] - 196 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA -K] - 197 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA -K] - 198 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA -K] - 199 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA -K] - 200 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA -K] - - - -ARM Macro Assembler Page 6 - - - 201 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA -K] - 202 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA -K] - 203 0000001A EXPORT ADC1_2_IRQHandler [WEA -K] - 204 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA -K] - 205 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA -K] - 206 0000001A EXPORT CAN1_RX1_IRQHandler [WEA -K] - 207 0000001A EXPORT CAN1_SCE_IRQHandler [WEA -K] - 208 0000001A EXPORT EXTI9_5_IRQHandler [WEA -K] - 209 0000001A EXPORT TIM1_BRK_IRQHandler [WEA -K] - 210 0000001A EXPORT TIM1_UP_IRQHandler [WEA -K] - 211 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA -K] - 212 0000001A EXPORT TIM1_CC_IRQHandler [WEA -K] - 213 0000001A EXPORT TIM2_IRQHandler [WEA -K] - 214 0000001A EXPORT TIM3_IRQHandler [WEA -K] - 215 0000001A EXPORT TIM4_IRQHandler [WEA -K] - 216 0000001A EXPORT I2C1_EV_IRQHandler [WEA -K] - 217 0000001A EXPORT I2C1_ER_IRQHandler [WEA -K] - 218 0000001A EXPORT I2C2_EV_IRQHandler [WEA -K] - 219 0000001A EXPORT I2C2_ER_IRQHandler [WEA -K] - 220 0000001A EXPORT SPI1_IRQHandler [WEA -K] - 221 0000001A EXPORT SPI2_IRQHandler [WEA -K] - 222 0000001A EXPORT USART1_IRQHandler [WEA -K] - 223 0000001A EXPORT USART2_IRQHandler [WEA -K] - 224 0000001A EXPORT USART3_IRQHandler [WEA -K] - 225 0000001A EXPORT EXTI15_10_IRQHandler [WEA -K] - 226 0000001A EXPORT RTCAlarm_IRQHandler [WEA -K] - 227 0000001A EXPORT USBWakeUp_IRQHandler [WEA -K] - 228 0000001A - 229 0000001A WWDG_IRQHandler - 230 0000001A PVD_IRQHandler - 231 0000001A TAMPER_IRQHandler - 232 0000001A RTC_IRQHandler - - - -ARM Macro Assembler Page 7 - - - 233 0000001A FLASH_IRQHandler - 234 0000001A RCC_IRQHandler - 235 0000001A EXTI0_IRQHandler - 236 0000001A EXTI1_IRQHandler - 237 0000001A EXTI2_IRQHandler - 238 0000001A EXTI3_IRQHandler - 239 0000001A EXTI4_IRQHandler - 240 0000001A DMA1_Channel1_IRQHandler - 241 0000001A DMA1_Channel2_IRQHandler - 242 0000001A DMA1_Channel3_IRQHandler - 243 0000001A DMA1_Channel4_IRQHandler - 244 0000001A DMA1_Channel5_IRQHandler - 245 0000001A DMA1_Channel6_IRQHandler - 246 0000001A DMA1_Channel7_IRQHandler - 247 0000001A ADC1_2_IRQHandler - 248 0000001A USB_HP_CAN1_TX_IRQHandler - 249 0000001A USB_LP_CAN1_RX0_IRQHandler - 250 0000001A CAN1_RX1_IRQHandler - 251 0000001A CAN1_SCE_IRQHandler - 252 0000001A EXTI9_5_IRQHandler - 253 0000001A TIM1_BRK_IRQHandler - 254 0000001A TIM1_UP_IRQHandler - 255 0000001A TIM1_TRG_COM_IRQHandler - 256 0000001A TIM1_CC_IRQHandler - 257 0000001A TIM2_IRQHandler - 258 0000001A TIM3_IRQHandler - 259 0000001A TIM4_IRQHandler - 260 0000001A I2C1_EV_IRQHandler - 261 0000001A I2C1_ER_IRQHandler - 262 0000001A I2C2_EV_IRQHandler - 263 0000001A I2C2_ER_IRQHandler - 264 0000001A SPI1_IRQHandler - 265 0000001A SPI2_IRQHandler - 266 0000001A USART1_IRQHandler - 267 0000001A USART2_IRQHandler - 268 0000001A USART3_IRQHandler - 269 0000001A EXTI15_10_IRQHandler - 270 0000001A RTCAlarm_IRQHandler - 271 0000001A USBWakeUp_IRQHandler - 272 0000001A - 273 0000001A E7FE B . - 274 0000001C - 275 0000001C ENDP - 276 0000001C - 277 0000001C ALIGN - 278 0000001C - 279 0000001C ;******************************************************* - ************************ - 280 0000001C ; User Stack and Heap initialization - 281 0000001C ;******************************************************* - ************************ - 282 0000001C IF :DEF:__MICROLIB - 283 0000001C - 284 0000001C EXPORT __initial_sp - 285 0000001C EXPORT __heap_base - 286 0000001C EXPORT __heap_limit - 287 0000001C - 288 0000001C ELSE - 303 ENDIF - - - -ARM Macro Assembler Page 8 - - - 304 0000001C - 305 0000001C END - 00000000 - 00000000 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw -ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md. -o -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Pack -s\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32 -F1xx_DFP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROL -IB SETA 1" --predefine="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" ---predefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --list=.\listings\ -startup_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32f10x_md.s - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -STACK 00000000 - -Symbol: STACK - Definitions - At line 35 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - None -Comment: STACK unused -Stack_Mem 00000000 - -Symbol: Stack_Mem - Definitions - At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - None -Comment: Stack_Mem unused -__initial_sp 00000400 - -Symbol: __initial_sp - Definitions - At line 37 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 284 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -HEAP 00000000 - -Symbol: HEAP - Definitions - At line 46 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - None -Comment: HEAP unused -Heap_Mem 00000000 - -Symbol: Heap_Mem - Definitions - At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - None -Comment: Heap_Mem unused -__heap_base 00000000 - -Symbol: __heap_base - Definitions - At line 47 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 285 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s -Comment: __heap_base used once -__heap_limit 00000200 - -Symbol: __heap_limit - Definitions - At line 49 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 286 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s -Comment: __heap_limit used once -4 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -RESET 00000000 - -Symbol: RESET - Definitions - At line 56 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - None -Comment: RESET unused -__Vectors 00000000 - -Symbol: __Vectors - Definitions - At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 57 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -__Vectors_End 000000EC - -Symbol: __Vectors_End - Definitions - At line 122 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 58 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 126 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - None -Comment: .text unused -ADC1_2_IRQHandler 0000001A - -Symbol: ADC1_2_IRQHandler - Definitions - At line 247 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 97 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 203 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -BusFault_Handler 0000000E - -Symbol: BusFault_Handler - Definitions - At line 156 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 66 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 157 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -CAN1_RX1_IRQHandler 0000001A - -Symbol: CAN1_RX1_IRQHandler - Definitions - At line 250 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 100 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 206 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -CAN1_SCE_IRQHandler 0000001A - -Symbol: CAN1_SCE_IRQHandler - Definitions - At line 251 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 101 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 207 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -DMA1_Channel1_IRQHandler 0000001A - -Symbol: DMA1_Channel1_IRQHandler - Definitions - At line 240 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 90 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 196 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -DMA1_Channel2_IRQHandler 0000001A - -Symbol: DMA1_Channel2_IRQHandler - Definitions - At line 241 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - - At line 91 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 197 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -DMA1_Channel3_IRQHandler 0000001A - -Symbol: DMA1_Channel3_IRQHandler - Definitions - At line 242 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 92 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 198 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -DMA1_Channel4_IRQHandler 0000001A - -Symbol: DMA1_Channel4_IRQHandler - Definitions - At line 243 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 93 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 199 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -DMA1_Channel5_IRQHandler 0000001A - -Symbol: DMA1_Channel5_IRQHandler - Definitions - At line 244 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 94 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 200 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -DMA1_Channel6_IRQHandler 0000001A - -Symbol: DMA1_Channel6_IRQHandler - Definitions - At line 245 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 95 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 201 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -DMA1_Channel7_IRQHandler 0000001A - -Symbol: DMA1_Channel7_IRQHandler - Definitions - At line 246 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 96 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 202 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -DebugMon_Handler 00000014 - -Symbol: DebugMon_Handler - Definitions - At line 170 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 73 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 171 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -Default_Handler 0000001A - - - - -ARM Macro Assembler Page 3 Alphabetic symbol ordering -Relocatable symbols - -Symbol: Default_Handler - Definitions - At line 183 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - None -Comment: Default_Handler unused -EXTI0_IRQHandler 0000001A - -Symbol: EXTI0_IRQHandler - Definitions - At line 235 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 85 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 191 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -EXTI15_10_IRQHandler 0000001A - -Symbol: EXTI15_10_IRQHandler - Definitions - At line 269 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 119 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 225 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -EXTI1_IRQHandler 0000001A - -Symbol: EXTI1_IRQHandler - Definitions - At line 236 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 86 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 192 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -EXTI2_IRQHandler 0000001A - -Symbol: EXTI2_IRQHandler - Definitions - At line 237 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 87 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 193 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -EXTI3_IRQHandler 0000001A - -Symbol: EXTI3_IRQHandler - Definitions - At line 238 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 88 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 194 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -EXTI4_IRQHandler 0000001A - -Symbol: EXTI4_IRQHandler - Definitions - At line 239 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 89 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 195 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - - - -ARM Macro Assembler Page 4 Alphabetic symbol ordering -Relocatable symbols - - -EXTI9_5_IRQHandler 0000001A - -Symbol: EXTI9_5_IRQHandler - Definitions - At line 252 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 102 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 208 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -FLASH_IRQHandler 0000001A - -Symbol: FLASH_IRQHandler - Definitions - At line 233 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 83 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 189 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -HardFault_Handler 0000000A - -Symbol: HardFault_Handler - Definitions - At line 146 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 64 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 147 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -I2C1_ER_IRQHandler 0000001A - -Symbol: I2C1_ER_IRQHandler - Definitions - At line 261 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 111 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 217 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -I2C1_EV_IRQHandler 0000001A - -Symbol: I2C1_EV_IRQHandler - Definitions - At line 260 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 110 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 216 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -I2C2_ER_IRQHandler 0000001A - -Symbol: I2C2_ER_IRQHandler - Definitions - At line 263 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 113 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 219 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -I2C2_EV_IRQHandler 0000001A - -Symbol: I2C2_EV_IRQHandler - Definitions - - - -ARM Macro Assembler Page 5 Alphabetic symbol ordering -Relocatable symbols - - At line 262 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 112 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 218 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -MemManage_Handler 0000000C - -Symbol: MemManage_Handler - Definitions - At line 151 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 65 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 152 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -NMI_Handler 00000008 - -Symbol: NMI_Handler - Definitions - At line 141 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 63 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 142 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -PVD_IRQHandler 0000001A - -Symbol: PVD_IRQHandler - Definitions - At line 230 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 80 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 186 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -PendSV_Handler 00000016 - -Symbol: PendSV_Handler - Definitions - At line 174 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 75 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 175 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -RCC_IRQHandler 0000001A - -Symbol: RCC_IRQHandler - Definitions - At line 234 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 84 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 190 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -RTCAlarm_IRQHandler 0000001A - -Symbol: RTCAlarm_IRQHandler - Definitions - At line 270 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 120 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 226 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - - - - -ARM Macro Assembler Page 6 Alphabetic symbol ordering -Relocatable symbols - -RTC_IRQHandler 0000001A - -Symbol: RTC_IRQHandler - Definitions - At line 232 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 82 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 188 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -Reset_Handler 00000000 - -Symbol: Reset_Handler - Definitions - At line 129 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 62 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 130 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -SPI1_IRQHandler 0000001A - -Symbol: SPI1_IRQHandler - Definitions - At line 264 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 114 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 220 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -SPI2_IRQHandler 0000001A - -Symbol: SPI2_IRQHandler - Definitions - At line 265 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 115 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 221 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -SVC_Handler 00000012 - -Symbol: SVC_Handler - Definitions - At line 165 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 72 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 166 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -SysTick_Handler 00000018 - -Symbol: SysTick_Handler - Definitions - At line 178 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 76 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 179 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -TAMPER_IRQHandler 0000001A - -Symbol: TAMPER_IRQHandler - Definitions - At line 231 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - - - -ARM Macro Assembler Page 7 Alphabetic symbol ordering -Relocatable symbols - - Uses - At line 81 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 187 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -TIM1_BRK_IRQHandler 0000001A - -Symbol: TIM1_BRK_IRQHandler - Definitions - At line 253 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 103 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 209 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -TIM1_CC_IRQHandler 0000001A - -Symbol: TIM1_CC_IRQHandler - Definitions - At line 256 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 106 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 212 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -TIM1_TRG_COM_IRQHandler 0000001A - -Symbol: TIM1_TRG_COM_IRQHandler - Definitions - At line 255 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 105 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 211 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -TIM1_UP_IRQHandler 0000001A - -Symbol: TIM1_UP_IRQHandler - Definitions - At line 254 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 104 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 210 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -TIM2_IRQHandler 0000001A - -Symbol: TIM2_IRQHandler - Definitions - At line 257 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 107 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 213 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -TIM3_IRQHandler 0000001A - -Symbol: TIM3_IRQHandler - Definitions - At line 258 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 108 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 214 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -TIM4_IRQHandler 0000001A - - - -ARM Macro Assembler Page 8 Alphabetic symbol ordering -Relocatable symbols - - -Symbol: TIM4_IRQHandler - Definitions - At line 259 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 109 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 215 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -USART1_IRQHandler 0000001A - -Symbol: USART1_IRQHandler - Definitions - At line 266 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 116 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 222 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -USART2_IRQHandler 0000001A - -Symbol: USART2_IRQHandler - Definitions - At line 267 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 117 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 223 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -USART3_IRQHandler 0000001A - -Symbol: USART3_IRQHandler - Definitions - At line 268 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 118 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 224 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -USBWakeUp_IRQHandler 0000001A - -Symbol: USBWakeUp_IRQHandler - Definitions - At line 271 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 121 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 227 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -USB_HP_CAN1_TX_IRQHandler 0000001A - -Symbol: USB_HP_CAN1_TX_IRQHandler - Definitions - At line 248 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 98 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 204 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -USB_LP_CAN1_RX0_IRQHandler 0000001A - -Symbol: USB_LP_CAN1_RX0_IRQHandler - Definitions - At line 249 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - - - -ARM Macro Assembler Page 9 Alphabetic symbol ordering -Relocatable symbols - - At line 99 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 205 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -UsageFault_Handler 00000010 - -Symbol: UsageFault_Handler - Definitions - At line 161 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 67 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 162 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -WWDG_IRQHandler 0000001A - -Symbol: WWDG_IRQHandler - Definitions - At line 229 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 79 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 185 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - -55 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -Heap_Size 00000200 - -Symbol: Heap_Size - Definitions - At line 44 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s -Comment: Heap_Size used once -Stack_Size 00000400 - -Symbol: Stack_Size - Definitions - At line 33 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s -Comment: Stack_Size used once -__Vectors_Size 000000EC - -Symbol: __Vectors_Size - Definitions - At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 59 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s -Comment: __Vectors_Size used once -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -SystemInit 00000000 - -Symbol: SystemInit - Definitions - At line 132 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 133 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s -Comment: SystemInit used once -__main 00000000 - -Symbol: __main - Definitions - At line 131 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - Uses - At line 135 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s -Comment: __main used once -2 symbols -407 symbols in table + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f10x_md.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V3.5.0 + 5 00000000 ;* Date : 11-March-2011 + 6 00000000 ;* Description : STM32F10x Medium Density Devices + vector table for MDK-ARM + 7 00000000 ;* toolchain. + 8 00000000 ;* This module performs: + 9 00000000 ;* - Set the initial SP + 10 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 11 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 12 00000000 ;* - Configure the clock system + 13 00000000 ;* - Branches to __main in the C li + brary (which eventually + 14 00000000 ;* calls main()). + 15 00000000 ;* After Reset the CortexM3 process + or is in Thread mode, + 16 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 18 00000000 ;******************************************************* + ************************ + 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A + T PROVIDING CUSTOMERS + 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR + DER FOR THEM TO SAVE TIME. + 21 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB + LE FOR ANY DIRECT, + 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY + CLAIMS ARISING FROM THE + 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM + ERS OF THE CODING + 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR + PRODUCTS. + 25 00000000 ;******************************************************* + ************************ + 26 00000000 + 27 00000000 ; Amount of memory (in bytes) allocated for Stack + 28 00000000 ; Tailor this value to your application needs + 29 00000000 ; Stack Configuration + 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 31 00000000 ; + 32 00000000 + 33 00000000 00000400 + Stack_Size + EQU 0x00000400 + 34 00000000 + 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 36 00000000 Stack_Mem + SPACE Stack_Size + 37 00000400 __initial_sp + 38 00000400 + 39 00000400 + 40 00000400 ; Heap Configuration + + + +ARM Macro Assembler Page 2 + + + 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 42 00000400 ; + 43 00000400 + 44 00000400 00000200 + Heap_Size + EQU 0x00000200 + 45 00000400 + 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 47 00000000 __heap_base + 48 00000000 Heap_Mem + SPACE Heap_Size + 49 00000200 __heap_limit + 50 00000200 + 51 00000200 PRESERVE8 + 52 00000200 THUMB + 53 00000200 + 54 00000200 + 55 00000200 ; Vector Table Mapped to Address 0 at Reset + 56 00000200 AREA RESET, DATA, READONLY + 57 00000000 EXPORT __Vectors + 58 00000000 EXPORT __Vectors_End + 59 00000000 EXPORT __Vectors_Size + 60 00000000 + 61 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 62 00000004 00000000 DCD Reset_Handler ; Reset Handler + 63 00000008 00000000 DCD NMI_Handler ; NMI Handler + 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 65 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 66 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 68 0000001C 00000000 DCD 0 ; Reserved + 69 00000020 00000000 DCD 0 ; Reserved + 70 00000024 00000000 DCD 0 ; Reserved + 71 00000028 00000000 DCD 0 ; Reserved + 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 74 00000034 00000000 DCD 0 ; Reserved + 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 76 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 77 00000040 + 78 00000040 ; External Interrupts + 79 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + 80 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detect + 81 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper + 82 0000004C 00000000 DCD RTC_IRQHandler ; RTC + + + +ARM Macro Assembler Page 3 + + + 83 00000050 00000000 DCD FLASH_IRQHandler ; Flash + 84 00000054 00000000 DCD RCC_IRQHandler ; RCC + 85 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0 + 86 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1 + 87 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2 + 88 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3 + 89 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4 + 90 0000006C 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 91 00000070 00000000 DCD DMA1_Channel2_IRQHandler + ; DMA1 Channel 2 + 92 00000074 00000000 DCD DMA1_Channel3_IRQHandler + ; DMA1 Channel 3 + 93 00000078 00000000 DCD DMA1_Channel4_IRQHandler + ; DMA1 Channel 4 + 94 0000007C 00000000 DCD DMA1_Channel5_IRQHandler + ; DMA1 Channel 5 + 95 00000080 00000000 DCD DMA1_Channel6_IRQHandler + ; DMA1 Channel 6 + 96 00000084 00000000 DCD DMA1_Channel7_IRQHandler + ; DMA1 Channel 7 + 97 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1_2 + 98 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB + High Priority or C + AN1 TX + 99 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US + B Low Priority or + CAN1 RX0 + 100 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + 101 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE + 102 0000009C 00000000 DCD EXTI9_5_IRQHandler + ; EXTI Line 9..5 + 103 000000A0 00000000 DCD TIM1_BRK_IRQHandler + ; TIM1 Break + 104 000000A4 00000000 DCD TIM1_UP_IRQHandler + ; TIM1 Update + 105 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 + Trigger and Commuta + tion + 106 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 107 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + 108 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + 109 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + 110 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + 111 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + 112 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + 113 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error + + 114 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + 115 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + 116 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + 117 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + 118 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + 119 000000E0 00000000 DCD EXTI15_10_IRQHandler + ; EXTI Line 15..10 + + + +ARM Macro Assembler Page 4 + + + 120 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm + through EXTI Line + 121 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake + up from suspend + 122 000000EC __Vectors_End + 123 000000EC + 124 000000EC 000000EC + __Vectors_Size + EQU __Vectors_End - __Vectors + 125 000000EC + 126 000000EC AREA |.text|, CODE, READONLY + 127 00000000 + 128 00000000 ; Reset handler + 129 00000000 Reset_Handler + PROC + 130 00000000 EXPORT Reset_Handler [WEAK +] + 131 00000000 IMPORT __main + 132 00000000 IMPORT SystemInit + 133 00000000 4806 LDR R0, =SystemInit + 134 00000002 4780 BLX R0 + 135 00000004 4806 LDR R0, =__main + 136 00000006 4700 BX R0 + 137 00000008 ENDP + 138 00000008 + 139 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 140 00000008 + 141 00000008 NMI_Handler + PROC + 142 00000008 EXPORT NMI_Handler [WEA +K] + 143 00000008 E7FE B . + 144 0000000A ENDP + 146 0000000A HardFault_Handler + PROC + 147 0000000A EXPORT HardFault_Handler [WEA +K] + 148 0000000A E7FE B . + 149 0000000C ENDP + 151 0000000C MemManage_Handler + PROC + 152 0000000C EXPORT MemManage_Handler [WEA +K] + 153 0000000C E7FE B . + 154 0000000E ENDP + 156 0000000E BusFault_Handler + PROC + 157 0000000E EXPORT BusFault_Handler [WEA +K] + 158 0000000E E7FE B . + 159 00000010 ENDP + 161 00000010 UsageFault_Handler + PROC + 162 00000010 EXPORT UsageFault_Handler [WEA +K] + 163 00000010 E7FE B . + 164 00000012 ENDP + 165 00000012 SVC_Handler + + + +ARM Macro Assembler Page 5 + + + PROC + 166 00000012 EXPORT SVC_Handler [WEA +K] + 167 00000012 E7FE B . + 168 00000014 ENDP + 170 00000014 DebugMon_Handler + PROC + 171 00000014 EXPORT DebugMon_Handler [WEA +K] + 172 00000014 E7FE B . + 173 00000016 ENDP + 174 00000016 PendSV_Handler + PROC + 175 00000016 EXPORT PendSV_Handler [WEA +K] + 176 00000016 E7FE B . + 177 00000018 ENDP + 178 00000018 SysTick_Handler + PROC + 179 00000018 EXPORT SysTick_Handler [WEA +K] + 180 00000018 E7FE B . + 181 0000001A ENDP + 182 0000001A + 183 0000001A Default_Handler + PROC + 184 0000001A + 185 0000001A EXPORT WWDG_IRQHandler [WEA +K] + 186 0000001A EXPORT PVD_IRQHandler [WEA +K] + 187 0000001A EXPORT TAMPER_IRQHandler [WEA +K] + 188 0000001A EXPORT RTC_IRQHandler [WEA +K] + 189 0000001A EXPORT FLASH_IRQHandler [WEA +K] + 190 0000001A EXPORT RCC_IRQHandler [WEA +K] + 191 0000001A EXPORT EXTI0_IRQHandler [WEA +K] + 192 0000001A EXPORT EXTI1_IRQHandler [WEA +K] + 193 0000001A EXPORT EXTI2_IRQHandler [WEA +K] + 194 0000001A EXPORT EXTI3_IRQHandler [WEA +K] + 195 0000001A EXPORT EXTI4_IRQHandler [WEA +K] + 196 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA +K] + 197 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA +K] + 198 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA +K] + 199 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA +K] + 200 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA +K] + + + +ARM Macro Assembler Page 6 + + + 201 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA +K] + 202 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA +K] + 203 0000001A EXPORT ADC1_2_IRQHandler [WEA +K] + 204 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA +K] + 205 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA +K] + 206 0000001A EXPORT CAN1_RX1_IRQHandler [WEA +K] + 207 0000001A EXPORT CAN1_SCE_IRQHandler [WEA +K] + 208 0000001A EXPORT EXTI9_5_IRQHandler [WEA +K] + 209 0000001A EXPORT TIM1_BRK_IRQHandler [WEA +K] + 210 0000001A EXPORT TIM1_UP_IRQHandler [WEA +K] + 211 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA +K] + 212 0000001A EXPORT TIM1_CC_IRQHandler [WEA +K] + 213 0000001A EXPORT TIM2_IRQHandler [WEA +K] + 214 0000001A EXPORT TIM3_IRQHandler [WEA +K] + 215 0000001A EXPORT TIM4_IRQHandler [WEA +K] + 216 0000001A EXPORT I2C1_EV_IRQHandler [WEA +K] + 217 0000001A EXPORT I2C1_ER_IRQHandler [WEA +K] + 218 0000001A EXPORT I2C2_EV_IRQHandler [WEA +K] + 219 0000001A EXPORT I2C2_ER_IRQHandler [WEA +K] + 220 0000001A EXPORT SPI1_IRQHandler [WEA +K] + 221 0000001A EXPORT SPI2_IRQHandler [WEA +K] + 222 0000001A EXPORT USART1_IRQHandler [WEA +K] + 223 0000001A EXPORT USART2_IRQHandler [WEA +K] + 224 0000001A EXPORT USART3_IRQHandler [WEA +K] + 225 0000001A EXPORT EXTI15_10_IRQHandler [WEA +K] + 226 0000001A EXPORT RTCAlarm_IRQHandler [WEA +K] + 227 0000001A EXPORT USBWakeUp_IRQHandler [WEA +K] + 228 0000001A + 229 0000001A WWDG_IRQHandler + 230 0000001A PVD_IRQHandler + 231 0000001A TAMPER_IRQHandler + 232 0000001A RTC_IRQHandler + + + +ARM Macro Assembler Page 7 + + + 233 0000001A FLASH_IRQHandler + 234 0000001A RCC_IRQHandler + 235 0000001A EXTI0_IRQHandler + 236 0000001A EXTI1_IRQHandler + 237 0000001A EXTI2_IRQHandler + 238 0000001A EXTI3_IRQHandler + 239 0000001A EXTI4_IRQHandler + 240 0000001A DMA1_Channel1_IRQHandler + 241 0000001A DMA1_Channel2_IRQHandler + 242 0000001A DMA1_Channel3_IRQHandler + 243 0000001A DMA1_Channel4_IRQHandler + 244 0000001A DMA1_Channel5_IRQHandler + 245 0000001A DMA1_Channel6_IRQHandler + 246 0000001A DMA1_Channel7_IRQHandler + 247 0000001A ADC1_2_IRQHandler + 248 0000001A USB_HP_CAN1_TX_IRQHandler + 249 0000001A USB_LP_CAN1_RX0_IRQHandler + 250 0000001A CAN1_RX1_IRQHandler + 251 0000001A CAN1_SCE_IRQHandler + 252 0000001A EXTI9_5_IRQHandler + 253 0000001A TIM1_BRK_IRQHandler + 254 0000001A TIM1_UP_IRQHandler + 255 0000001A TIM1_TRG_COM_IRQHandler + 256 0000001A TIM1_CC_IRQHandler + 257 0000001A TIM2_IRQHandler + 258 0000001A TIM3_IRQHandler + 259 0000001A TIM4_IRQHandler + 260 0000001A I2C1_EV_IRQHandler + 261 0000001A I2C1_ER_IRQHandler + 262 0000001A I2C2_EV_IRQHandler + 263 0000001A I2C2_ER_IRQHandler + 264 0000001A SPI1_IRQHandler + 265 0000001A SPI2_IRQHandler + 266 0000001A USART1_IRQHandler + 267 0000001A USART2_IRQHandler + 268 0000001A USART3_IRQHandler + 269 0000001A EXTI15_10_IRQHandler + 270 0000001A RTCAlarm_IRQHandler + 271 0000001A USBWakeUp_IRQHandler + 272 0000001A + 273 0000001A E7FE B . + 274 0000001C + 275 0000001C ENDP + 276 0000001C + 277 0000001C ALIGN + 278 0000001C + 279 0000001C ;******************************************************* + ************************ + 280 0000001C ; User Stack and Heap initialization + 281 0000001C ;******************************************************* + ************************ + 282 0000001C IF :DEF:__MICROLIB + 283 0000001C + 284 0000001C EXPORT __initial_sp + 285 0000001C EXPORT __heap_base + 286 0000001C EXPORT __heap_limit + 287 0000001C + 288 0000001C ELSE + 303 ENDIF + + + +ARM Macro Assembler Page 8 + + + 304 0000001C + 305 0000001C END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md. +o -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Pack +s\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32 +F1xx_DFP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROL +IB SETA 1" --predefine="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" +--predefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --list=.\listings\ +startup_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 35 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 37 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 284 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 46 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 47 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 285 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: __heap_base used once +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 49 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 286 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 56 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 57 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +__Vectors_End 000000EC + +Symbol: __Vectors_End + Definitions + At line 122 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 58 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 126 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: .text unused +ADC1_2_IRQHandler 0000001A + +Symbol: ADC1_2_IRQHandler + Definitions + At line 247 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 97 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 203 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 156 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 66 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 157 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 250 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 100 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 206 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +CAN1_SCE_IRQHandler 0000001A + +Symbol: CAN1_SCE_IRQHandler + Definitions + At line 251 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 101 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 207 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel1_IRQHandler 0000001A + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 240 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 90 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 196 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel2_IRQHandler 0000001A + +Symbol: DMA1_Channel2_IRQHandler + Definitions + At line 241 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 91 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 197 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel3_IRQHandler 0000001A + +Symbol: DMA1_Channel3_IRQHandler + Definitions + At line 242 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 92 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 198 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel4_IRQHandler 0000001A + +Symbol: DMA1_Channel4_IRQHandler + Definitions + At line 243 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 93 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 199 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel5_IRQHandler 0000001A + +Symbol: DMA1_Channel5_IRQHandler + Definitions + At line 244 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 94 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 200 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel6_IRQHandler 0000001A + +Symbol: DMA1_Channel6_IRQHandler + Definitions + At line 245 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 95 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 201 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel7_IRQHandler 0000001A + +Symbol: DMA1_Channel7_IRQHandler + Definitions + At line 246 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 96 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 202 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 170 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 73 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 171 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +Default_Handler 0000001A + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +Symbol: Default_Handler + Definitions + At line 183 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: Default_Handler unused +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 235 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 85 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 191 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI15_10_IRQHandler 0000001A + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 269 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 119 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 225 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 236 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 86 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 192 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 237 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 87 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 193 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 238 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 88 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 194 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 239 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 89 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 195 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +EXTI9_5_IRQHandler 0000001A + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 252 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 102 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 208 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +FLASH_IRQHandler 0000001A + +Symbol: FLASH_IRQHandler + Definitions + At line 233 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 83 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 189 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 146 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 64 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 147 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 261 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 111 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 217 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 260 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 110 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 216 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +I2C2_ER_IRQHandler 0000001A + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 263 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 113 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 219 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +I2C2_EV_IRQHandler 0000001A + +Symbol: I2C2_EV_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 262 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 112 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 218 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 151 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 65 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 152 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 141 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 63 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 142 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +PVD_IRQHandler 0000001A + +Symbol: PVD_IRQHandler + Definitions + At line 230 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 80 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 186 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 174 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 75 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 175 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +RCC_IRQHandler 0000001A + +Symbol: RCC_IRQHandler + Definitions + At line 234 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 84 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 190 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +RTCAlarm_IRQHandler 0000001A + +Symbol: RTCAlarm_IRQHandler + Definitions + At line 270 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 120 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 226 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 232 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 82 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 188 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 129 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 62 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 130 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 264 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 114 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 220 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 265 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 115 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 221 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 165 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 72 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 166 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 178 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 76 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 179 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TAMPER_IRQHandler 0000001A + +Symbol: TAMPER_IRQHandler + Definitions + At line 231 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 81 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 187 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM1_BRK_IRQHandler 0000001A + +Symbol: TIM1_BRK_IRQHandler + Definitions + At line 253 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 103 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 209 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM1_CC_IRQHandler 0000001A + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 256 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 106 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 212 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM1_TRG_COM_IRQHandler 0000001A + +Symbol: TIM1_TRG_COM_IRQHandler + Definitions + At line 255 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 105 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 211 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM1_UP_IRQHandler 0000001A + +Symbol: TIM1_UP_IRQHandler + Definitions + At line 254 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 104 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 210 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM2_IRQHandler 0000001A + +Symbol: TIM2_IRQHandler + Definitions + At line 257 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 107 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 213 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM3_IRQHandler 0000001A + +Symbol: TIM3_IRQHandler + Definitions + At line 258 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 108 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 214 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM4_IRQHandler 0000001A + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: TIM4_IRQHandler + Definitions + At line 259 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 109 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 215 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 266 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 116 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 222 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 267 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 117 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 223 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USART3_IRQHandler 0000001A + +Symbol: USART3_IRQHandler + Definitions + At line 268 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 118 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 224 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USBWakeUp_IRQHandler 0000001A + +Symbol: USBWakeUp_IRQHandler + Definitions + At line 271 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 121 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 227 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USB_HP_CAN1_TX_IRQHandler 0000001A + +Symbol: USB_HP_CAN1_TX_IRQHandler + Definitions + At line 248 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 98 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 204 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USB_LP_CAN1_RX0_IRQHandler 0000001A + +Symbol: USB_LP_CAN1_RX0_IRQHandler + Definitions + At line 249 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + At line 99 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 205 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 161 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 67 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 162 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +WWDG_IRQHandler 0000001A + +Symbol: WWDG_IRQHandler + Definitions + At line 229 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 79 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 185 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +55 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 44 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: Heap_Size used once +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 33 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: Stack_Size used once +__Vectors_Size 000000EC + +Symbol: __Vectors_Size + Definitions + At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 59 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 132 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 133 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 131 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 135 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: __main used once +2 symbols +407 symbols in table diff --git a/Objects/ExtDll.iex b/Objects/ExtDll.iex index 6c0896e..b661f48 100644 --- a/Objects/ExtDll.iex +++ b/Objects/ExtDll.iex @@ -1,2 +1,2 @@ -[EXTDLL] -Count=0 +[EXTDLL] +Count=0 diff --git a/Objects/Projet1.build_log.htm b/Objects/Projet1.build_log.htm index 071913c..a6c70db 100644 --- a/Objects/Projet1.build_log.htm +++ b/Objects/Projet1.build_log.htm @@ -1,79 +1,79 @@ - - -

        -
        µVision Build Log
        
-
        Tool Versions:
        
-IDE-Version: µVision V5.34.0.0
-Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: CSN CSN, INSA de Toulouse, LIC=----
- 
-Tool Versions:
-Toolchain:       MDK-Lite  Version: 5.34.0.0
-Toolchain Path:  C:\Keil_v5\ARM\ARMCLANG\Bin
-C Compiler:      ArmClang.exe V6.16
-Assembler:       Armasm.exe V6.16
-Linker/Locator:  ArmLink.exe V6.16
-Library Manager: ArmAr.exe V6.16
-Hex Converter:   FromElf.exe V6.16
-CPU DLL:         SARMCM3.DLL V5.34.0.0
-Dialog DLL:      DARMSTM.DLL V1.68.0.0
-Target DLL:      UL2CM3.DLL V1.163.9.0
-Dialog DLL:      TARMSTM.DLL V1.66.0.0
- 
-
        Project:
        
-U:\Documents\4MIC\S1\Microcontroleur\Activite1\Projet1.uvprojx
-Project File Date:  09/19/2022
-
-
        Output:
        
-*** Using Compiler 'V6.16', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
-Build target 'Target 1'
-assembling startup_stm32f10x_md.s...
-RTE/Device/STM32F103RB/system_stm32f10x.c(167): warning: no previous extern declaration for non-static variable 'AHBPrescTable' [-Wmissing-variable-declarations]
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-            ^
-RTE/Device/STM32F103RB/system_stm32f10x.c(167): note: declare 'static' if the variable is not intended to be used outside of this translation unit
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-    ^
-1 warning generated.
-compiling system_stm32f10x.c...
-linking...
-.\Objects\Projet1.axf: Error: L6218E: Undefined symbol main (referred from __rtentry2.o).
-Not enough information to list image symbols.
-Not enough information to list load addresses in the image map.
-Finished: 2 information, 0 warning and 1 error messages.
-".\Objects\Projet1.axf" - 1 Error(s), 1 Warning(s).
-
-
        Software Packages used:
        
-
-Package Vendor: ARM
-                http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
-                ARM.CMSIS.5.7.0
-                CMSIS (Cortex Microcontroller Software Interface Standard)
-   * Component: CORE Version: 5.4.0
-
-Package Vendor: Keil
-                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
-                Keil.STM32F1xx_DFP.2.3.0
-                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
-   * Component: Startup Version: 1.0.0
-
-
        Collection of Component include folders:
        
-  .\RTE\Device\STM32F103RB
-  .\RTE\_Target_1
-  C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-  C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-
-
        Collection of Component Files used:
        
-
-   * Component: ARM::CMSIS:CORE:5.4.0
-
-   * Component: Keil::Device:Startup:1.0.0
-      Source file:   Device\Source\system_stm32f10x.c
-      Include file:  RTE_Driver\Config\RTE_Device.h
-      Source file:   Device\Source\ARM\STM32F1xx_OPT.s
-      Source file:   Device\Source\ARM\startup_stm32f10x_md.s
-Target not created.
-Build Time Elapsed:  00:00:01
-
        - - + + +
        +
        µVision Build Log
        
+
        Tool Versions:
        
+IDE-Version: µVision V5.34.0.0
+Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: CSN CSN, INSA de Toulouse, LIC=----
+ 
+Tool Versions:
+Toolchain:       MDK-Lite  Version: 5.34.0.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCLANG\Bin
+C Compiler:      ArmClang.exe V6.16
+Assembler:       Armasm.exe V6.16
+Linker/Locator:  ArmLink.exe V6.16
+Library Manager: ArmAr.exe V6.16
+Hex Converter:   FromElf.exe V6.16
+CPU DLL:         SARMCM3.DLL V5.34.0.0
+Dialog DLL:      DARMSTM.DLL V1.68.0.0
+Target DLL:      UL2CM3.DLL V1.163.9.0
+Dialog DLL:      TARMSTM.DLL V1.66.0.0
+ 
+
        Project:
        
+U:\Documents\4MIC\S1\Microcontroleur\Activite1\Projet1.uvprojx
+Project File Date:  09/19/2022
+
+
        Output:
        
+*** Using Compiler 'V6.16', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
+Build target 'Target 1'
+assembling startup_stm32f10x_md.s...
+RTE/Device/STM32F103RB/system_stm32f10x.c(167): warning: no previous extern declaration for non-static variable 'AHBPrescTable' [-Wmissing-variable-declarations]
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+            ^
+RTE/Device/STM32F103RB/system_stm32f10x.c(167): note: declare 'static' if the variable is not intended to be used outside of this translation unit
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+    ^
+1 warning generated.
+compiling system_stm32f10x.c...
+linking...
+.\Objects\Projet1.axf: Error: L6218E: Undefined symbol main (referred from __rtentry2.o).
+Not enough information to list image symbols.
+Not enough information to list load addresses in the image map.
+Finished: 2 information, 0 warning and 1 error messages.
+".\Objects\Projet1.axf" - 1 Error(s), 1 Warning(s).
+
+
        Software Packages used:
        
+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
+                ARM.CMSIS.5.7.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.4.0
+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
+                Keil.STM32F1xx_DFP.2.3.0
+                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
+   * Component: Startup Version: 1.0.0
+
+
        Collection of Component include folders:
        
+  .\RTE\Device\STM32F103RB
+  .\RTE\_Target_1
+  C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
+  C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
+
+
        Collection of Component Files used:
        
+
+   * Component: ARM::CMSIS:CORE:5.4.0
+
+   * Component: Keil::Device:Startup:1.0.0
+      Source file:   Device\Source\system_stm32f10x.c
+      Include file:  RTE_Driver\Config\RTE_Device.h
+      Source file:   Device\Source\ARM\STM32F1xx_OPT.s
+      Source file:   Device\Source\ARM\startup_stm32f10x_md.s
+Target not created.
+Build Time Elapsed:  00:00:01
+
        + + diff --git a/Objects/Projet1.lnp b/Objects/Projet1.lnp index 48022ea..20f0acb 100644 --- a/Objects/Projet1.lnp +++ b/Objects/Projet1.lnp @@ -1,6 +1,6 @@ ---cpu Cortex-M3 -".\objects\startup_stm32f10x_md.o" -".\objects\system_stm32f10x.o" ---ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols ---info sizes --info totals --info unused --info veneers +--cpu Cortex-M3 +".\objects\startup_stm32f10x_md.o" +".\objects\system_stm32f10x.o" +--ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers --list ".\Listings\Projet1.map" -o .\Objects\Projet1.axf \ No newline at end of file diff --git a/Objects/Projet1_SImulation.dep b/Objects/Projet1_SImulation.dep index 70ab3f3..bad3036 100644 --- a/Objects/Projet1_SImulation.dep +++ b/Objects/Projet1_SImulation.dep @@ -1,6 +1,6 @@ Dependencies for Project 'Projet1', Target 'SImulation': (DO NOT MODIFY !) CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC -F (.\Sources\main.c)(0x6352ACB6)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d) +F (.\Sources\main.c)(0x635B8BB4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) @@ -10,8 +10,9 @@ I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compil I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) I (.\FileInclude\Driver_GPIO.h)(0x6352AB58) -I (.\FileInclude\MyTimer.h)(0x6352ACB6) +I (.\FileInclude\MyTimer.h)(0x6352B8A4) I (.\FileInclude\MyADC.h)(0x6352AB58) +I (.\FileInclude\Plateau.h)(0x635B8BB4) F (U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c)(0x633153E6)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d) I (U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.h)(0x63315001) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) @@ -22,8 +23,8 @@ I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_versio I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -F (.\FileInclude\MyTimer.c)(0x6352ACB6)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d) -I (FileInclude\MyTimer.h)(0x6352ACB6) +F (.\FileInclude\MyTimer.c)(0x6352B8A4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d) +I (FileInclude\MyTimer.h)(0x6352B8A4) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) @@ -33,7 +34,7 @@ I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compil I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) I (FileInclude\Driver_GPIO.h)(0x6352AB58) -F (.\FileInclude\MyTimer.h)(0x6352ACB6)() +F (.\FileInclude\MyTimer.h)(0x6352B8A4)() F (.\FileInclude\MyADC.c)(0x6352AB58)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\myadc.o --omf_browse .\objects\myadc.crf --depend .\objects\myadc.d) I (FileInclude\MyADC.h)(0x6352AB58) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) @@ -44,11 +45,11 @@ I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_versio I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -I (FileInclude\MyTimer.h)(0x6352ACB6) +I (FileInclude\MyTimer.h)(0x6352B8A4) I (FileInclude\Driver_GPIO.h)(0x6352AB58) F (.\FileInclude\MyADC.h)(0x6352AB58)() -F (.\FileInclude\Plateau.c)(0x6352B4DB)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\plateau.o --omf_browse .\objects\plateau.crf --depend .\objects\plateau.d) -I (FileInclude\MyTimer.h)(0x6352ACB6) +F (.\FileInclude\Plateau.c)(0x635B8BB4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\plateau.o --omf_browse .\objects\plateau.crf --depend .\objects\plateau.d) +I (FileInclude\MyTimer.h)(0x6352B8A4) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) @@ -58,10 +59,10 @@ I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compil I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) I (FileInclude\Driver_GPIO.h)(0x6352AB58) -I (FileInclude\Plateau.h)(0x6352B148) -F (.\FileInclude\Telecommande.c)(0x6352ADB2)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\telecommande.o --omf_browse .\objects\telecommande.crf --depend .\objects\telecommande.d) -F (.\FileInclude\Plateau.h)(0x6352B148)() -F (.\FileInclude\Telecommande.h)(0x6352ADB2)() +I (FileInclude\Plateau.h)(0x635B8BB4) +F (.\FileInclude\Telecommande.c)(0x6352B81B)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\telecommande.o --omf_browse .\objects\telecommande.crf --depend .\objects\telecommande.d) +F (.\FileInclude\Plateau.h)(0x635B8BB4)() +F (.\FileInclude\Telecommande.h)(0x6352B81B)() F (RTE\Device\STM32F103RB\RTE_Device.h)(0x6352AB59)() F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x6352AB59)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d) F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x6352AB59)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d) diff --git a/Objects/Projet1_Simulation.axf b/Objects/Projet1_Simulation.axf index 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        -
        µVision Build Log
        
-
        Tool Versions:
        
-IDE-Version: µVision V5.34.0.0
-Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: CSN CSN, INSA de Toulouse, LIC=----
- 
-Tool Versions:
-Toolchain:       MDK-Lite  Version: 5.34.0.0
-Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler:      Armcc.exe V5.06 update 7 (build 960)
-Assembler:       Armasm.exe V5.06 update 7 (build 960)
-Linker/Locator:  ArmLink.exe V5.06 update 7 (build 960)
-Library Manager: ArmAr.exe V5.06 update 7 (build 960)
-Hex Converter:   FromElf.exe V5.06 update 7 (build 960)
-CPU DLL:         SARMCM3.DLL V5.34.0.0
-Dialog DLL:      DARMSTM.DLL V1.68.0.0
-Target DLL:      UL2CM3.DLL V1.163.9.0
-Dialog DLL:      TARMSTM.DLL V1.66.0.0
- 
-
        Project:
        
-U:\Documents\4ir\S1\Microcontroleur\TP_Voilier\Projet1.uvprojx
-Project File Date:  10/21/2022
-
-
        Output:
        
-*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Rebuild target 'SImulation'
-assembling startup_stm32f10x_md.s...
-compiling Telecommande.c...
-compiling main.c...
-compiling MyADC.c...
-compiling Driver_GPIO.c...
-compiling MyTimer.c...
-compiling Plateau.c...
-FileInclude\Plateau.h(7): warning:  #1-D: last line of file ends without a newline
-  #endif 
-FileInclude\Plateau.c(23): warning:  #1-D: last line of file ends without a newline
-  }
-FileInclude\Plateau.c(10): warning:  #177-D: variable "GPI0A5"  was declared but never referenced
-  	MyGPIO_Struct_TypeDef GPI0A5; // pin direction
-FileInclude\Plateau.c(11): warning:  #177-D: variable "GPIOA6"  was declared but never referenced
-  	MyGPIO_Struct_TypeDef GPIOA6; // pin moteur
-FileInclude\Plateau.c: 4 warnings, 0 errors
-compiling system_stm32f10x.c...
-linking...
-Program Size: Code=1088 RO-data=268 RW-data=20 ZI-data=1028  
-".\Objects\Projet1_Simulation.axf" - 0 Error(s), 4 Warning(s).
-
-
        Software Packages used:
        
-
-Package Vendor: ARM
-                http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
-                ARM.CMSIS.5.7.0
-                CMSIS (Cortex Microcontroller Software Interface Standard)
-   * Component: CORE Version: 5.4.0
-
-Package Vendor: Keil
-                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
-                Keil.STM32F1xx_DFP.2.3.0
-                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
-   * Component: Startup Version: 1.0.0
-
-
        Collection of Component include folders:
        
-  .\RTE\Device\STM32F103RB
-  .\RTE\_SImulation
-  C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-  C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
-
-
        Collection of Component Files used:
        
-
-   * Component: ARM::CMSIS:CORE:5.4.0
-
-   * Component: Keil::Device:Startup:1.0.0
-      Source file:   Device\Source\system_stm32f10x.c
-      Include file:  RTE_Driver\Config\RTE_Device.h
-      Source file:   Device\Source\ARM\startup_stm32f10x_md.s
-      Source file:   Device\Source\ARM\STM32F1xx_OPT.s
-Build Time Elapsed:  00:00:02
-
        - - + + +
        +
        µVision Build Log
        
+
        Tool Versions:
        
+IDE-Version: µVision V5.34.0.0
+Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: CSN CSN, INSA de Toulouse, LIC=----
+ 
+Tool Versions:
+Toolchain:       MDK-Lite  Version: 5.34.0.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 7 (build 960)
+Assembler:       Armasm.exe V5.06 update 7 (build 960)
+Linker/Locator:  ArmLink.exe V5.06 update 7 (build 960)
+Library Manager: ArmAr.exe V5.06 update 7 (build 960)
+Hex Converter:   FromElf.exe V5.06 update 7 (build 960)
+CPU DLL:         SARMCM3.DLL V5.34.0.0
+Dialog DLL:      DARMSTM.DLL V1.68.0.0
+Target DLL:      UL2CM3.DLL V1.163.9.0
+Dialog DLL:      TARMSTM.DLL V1.66.0.0
+ 
+
        Project:
        
+U:\Documents\4ir\S1\Microcontroleur\TP_Voilier\Projet1.uvprojx
+Project File Date:  10/21/2022
+
+
        Output:
        
+*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Rebuild target 'SImulation'
+assembling startup_stm32f10x_md.s...
+compiling Telecommande.c...
+compiling Driver_GPIO.c...
+compiling main.c...
+compiling MyADC.c...
+compiling Plateau.c...
+compiling system_stm32f10x.c...
+compiling MyTimer.c...
+linking...
+Program Size: Code=1680 RO-data=268 RW-data=32 ZI-data=1048  
+".\Objects\Projet1_Simulation.axf" - 0 Error(s), 0 Warning(s).
+
+
        Software Packages used:
        
+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
+                ARM.CMSIS.5.7.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.4.0
+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
+                Keil.STM32F1xx_DFP.2.3.0
+                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
+   * Component: Startup Version: 1.0.0
+
+
        Collection of Component include folders:
        
+  .\RTE\Device\STM32F103RB
+  .\RTE\_SImulation
+  C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
+  C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
+
+
        Collection of Component Files used:
        
+
+   * Component: ARM::CMSIS:CORE:5.4.0
+
+   * Component: Keil::Device:Startup:1.0.0
+      Source file:   Device\Source\ARM\startup_stm32f10x_md.s
+      Source file:   Device\Source\system_stm32f10x.c
+      Source file:   Device\Source\ARM\STM32F1xx_OPT.s
+      Include file:  RTE_Driver\Config\RTE_Device.h
+Build Time Elapsed:  00:00:01
+
        + + diff --git a/Objects/Projet1_Simulation.htm b/Objects/Projet1_Simulation.htm index 6c7780a..9715776 100644 --- a/Objects/Projet1_Simulation.htm +++ b/Objects/Projet1_Simulation.htm @@ -1,406 +1,443 @@ - - -Static Call Graph - [.\Objects\Projet1_Simulation.axf] -
        -

        Static Call Graph for image .\Objects\Projet1_Simulation.axf

        -

        #<CALLGRAPH># ARM Linker, 5060960: Last Updated: Fri Oct 21 17:03:57 2022 -

        -

        Maximum Stack Usage = 28 bytes + Unknown(Cycles, Untraceable Function Pointers)

        -Call chain for Maximum Stack Depth:

        -SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72 -

        -

        -Mutually Recursive functions -

      • NMI_Handler   ⇒   NMI_Handler
        -
      • HardFault_Handler   ⇒   HardFault_Handler
        -
      • MemManage_Handler   ⇒   MemManage_Handler
        -
      • BusFault_Handler   ⇒   BusFault_Handler
        -
      • UsageFault_Handler   ⇒   UsageFault_Handler
        -
      • SVC_Handler   ⇒   SVC_Handler
        -
      • DebugMon_Handler   ⇒   DebugMon_Handler
        -
      • PendSV_Handler   ⇒   PendSV_Handler
        -
      • SysTick_Handler   ⇒   SysTick_Handler
        -
      • ADC1_2_IRQHandler   ⇒   ADC1_2_IRQHandler
        -
      -

      -

      -Function Pointers -

        -
      • ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • Callback from main.o(i.Callback) referenced from main.o(i.main) -
      • DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • EXTI4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • EXTI9_5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text) -
      • TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • TIM1_TRG_COM_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • TIM1_UP_IRQHandler from mytimer.o(i.TIM1_UP_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) -
      • TIM2_IRQHandler from mytimer.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) -
      • TIM3_IRQHandler from mytimer.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) -
      • TIM4_IRQHandler from mytimer.o(i.TIM4_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) -
      • USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
      • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text) -
      • main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B) -
      -

      -

      -Global Symbols -

      -

      __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(.text) -
      -

      _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) - -

      _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) -

      [Calls]

      • >>   __scatterload -
      - -

      __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) -

      [Called By]

      • >>   __scatterload -
      - -

      _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) - -

      _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) - -

      _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) - -

      __rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E)) - -

      __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F)) - -

      __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011)) - -

      Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) - -

      NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   NMI_Handler -
      -
      [Called By]
      • >>   NMI_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   HardFault_Handler -
      -
      [Called By]
      • >>   HardFault_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   MemManage_Handler -
      -
      [Called By]
      • >>   MemManage_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   BusFault_Handler -
      -
      [Called By]
      • >>   BusFault_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   UsageFault_Handler -
      -
      [Called By]
      • >>   UsageFault_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   SVC_Handler -
      -
      [Called By]
      • >>   SVC_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   DebugMon_Handler -
      -
      [Called By]
      • >>   DebugMon_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   PendSV_Handler -
      -
      [Called By]
      • >>   PendSV_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   SysTick_Handler -
      -
      [Called By]
      • >>   SysTick_Handler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -

      [Calls]

      • >>   ADC1_2_IRQHandler -
      -
      [Called By]
      • >>   ADC1_2_IRQHandler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) -
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) -
      -

      __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text)) -

      [Calls]

      • >>   __main_after_scatterload -
      -
      [Called By]
      • >>   _main_scatterload -
      - -

      __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) - -

      Callback (Thumb, 16 bytes, Stack size 8 bytes, main.o(i.Callback)) -

      [Stack]

      • Max Depth = 8
      • Call Chain = Callback -
      -
      [Calls]
      • >>   startADC -
      • >>   read -
      -
      [Address Reference Count : 1]
      • main.o(i.main) -
      -

      MyTimer_ActiveIT (Thumb, 148 bytes, Stack size 8 bytes, mytimer.o(i.MyTimer_ActiveIT)) -

      [Stack]

      • Max Depth = 8
      • Call Chain = MyTimer_ActiveIT -
      -
      [Called By]
      • >>   main -
      - -

      MyTimer_Base_Init (Thumb, 98 bytes, Stack size 0 bytes, mytimer.o(i.MyTimer_Base_Init)) -

      [Called By]

      • >>   main -
      - -

      MyTimer_Base_Start (Thumb, 10 bytes, Stack size 0 bytes, mytimer.o(i.MyTimer_Base_Start)) -

      [Called By]

      • >>   main -
      - -

      SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit)) -

      [Stack]

      • Max Depth = 28
      • Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72 -
      -
      [Calls]
      • >>   SetSysClock -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(.text) -
      -

      TIM1_UP_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM1_UP_IRQHandler)) -

      [Stack]

      • Max Depth = 8
      • Call Chain = TIM1_UP_IRQHandler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      TIM2_IRQHandler (Thumb, 32 bytes, Stack size 8 bytes, mytimer.o(i.TIM2_IRQHandler)) -

      [Stack]

      • Max Depth = 8
      • Call Chain = TIM2_IRQHandler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      TIM3_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM3_IRQHandler)) -

      [Stack]

      • Max Depth = 8
      • Call Chain = TIM3_IRQHandler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      TIM4_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM4_IRQHandler)) -

      [Stack]

      • Max Depth = 8
      • Call Chain = TIM4_IRQHandler -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET) -
      -

      __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) - -

      __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) - -

      __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) - -

      initADC (Thumb, 50 bytes, Stack size 0 bytes, myadc.o(i.initADC)) -

      [Called By]

      • >>   main -
      - -

      main (Thumb, 56 bytes, Stack size 16 bytes, main.o(i.main)) -

      [Stack]

      • Max Depth = 24
      • Call Chain = main ⇒ MyTimer_ActiveIT -
      -
      [Calls]
      • >>   initADC -
      • >>   MyTimer_Base_Start -
      • >>   MyTimer_Base_Init -
      • >>   MyTimer_ActiveIT -
      -
      [Address Reference Count : 1]
      • entry9a.o(.ARM.Collect$$$$0000000B) -
      -

      read (Thumb, 26 bytes, Stack size 0 bytes, myadc.o(i.read)) -

      [Called By]

      • >>   Callback -
      - -

      startADC (Thumb, 14 bytes, Stack size 0 bytes, myadc.o(i.startADC)) -

      [Called By]

      • >>   Callback -
      -

      -

      -Local Symbols -

      -

      SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock)) -

      [Stack]

      • Max Depth = 20
      • Call Chain = SetSysClock ⇒ SetSysClockTo72 -
      -
      [Calls]
      • >>   SetSysClockTo72 -
      -
      [Called By]
      • >>   SystemInit -
      - -

      SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72)) -

      [Stack]

      • Max Depth = 12
      • Call Chain = SetSysClockTo72 -
      -
      [Called By]
      • >>   SetSysClock -
      -

      -

      -Undefined Global Symbols -

      + + +Static Call Graph - [.\Objects\Projet1_Simulation.axf] +
      +

      Static Call Graph for image .\Objects\Projet1_Simulation.axf

      +

      #<CALLGRAPH># ARM Linker, 5060960: Last Updated: Fri Oct 28 09:58:45 2022 +

      +

      Maximum Stack Usage = 60 bytes + Unknown(Cycles, Untraceable Function Pointers)

      +Call chain for Maximum Stack Depth:

      +main ⇒ Set_Moteur_Plateau ⇒ Init_Plateau ⇒ MyTimer_PWM ⇒ MyGPIO_Init +

      +

      +Mutually Recursive functions +

    • NMI_Handler   ⇒   NMI_Handler
      +
    • HardFault_Handler   ⇒   HardFault_Handler
      +
    • MemManage_Handler   ⇒   MemManage_Handler
      +
    • BusFault_Handler   ⇒   BusFault_Handler
      +
    • UsageFault_Handler   ⇒   UsageFault_Handler
      +
    • SVC_Handler   ⇒   SVC_Handler
      +
    • DebugMon_Handler   ⇒   DebugMon_Handler
      +
    • PendSV_Handler   ⇒   PendSV_Handler
      +
    • SysTick_Handler   ⇒   SysTick_Handler
      +
    • ADC1_2_IRQHandler   ⇒   ADC1_2_IRQHandler
      +
    +

    +

    +Function Pointers +

      +
    • ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI9_5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text) +
    • TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM1_TRG_COM_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM1_UP_IRQHandler from mytimer.o(i.TIM1_UP_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM2_IRQHandler from mytimer.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM3_IRQHandler from mytimer.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM4_IRQHandler from mytimer.o(i.TIM4_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) +
    • USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text) +
    • main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(.text) +
    +

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) + +

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Calls]

    • >>   __scatterload +
    + +

    __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Called By]

    • >>   __scatterload +
    + +

    _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) + +

    _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) + +

    _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) + +

    __rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E)) + +

    __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F)) + +

    __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011)) + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) + +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   NMI_Handler +
    +
    [Called By]
    • >>   NMI_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   HardFault_Handler +
    +
    [Called By]
    • >>   HardFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   MemManage_Handler +
    +
    [Called By]
    • >>   MemManage_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   BusFault_Handler +
    +
    [Called By]
    • >>   BusFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   UsageFault_Handler +
    +
    [Called By]
    • >>   UsageFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   SVC_Handler +
    +
    [Called By]
    • >>   SVC_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   DebugMon_Handler +
    +
    [Called By]
    • >>   DebugMon_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   PendSV_Handler +
    +
    [Called By]
    • >>   PendSV_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   SysTick_Handler +
    +
    [Called By]
    • >>   SysTick_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   ADC1_2_IRQHandler +
    +
    [Called By]
    • >>   ADC1_2_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text)) +

    [Calls]

    • >>   __main_after_scatterload +
    +
    [Called By]
    • >>   _main_scatterload +
    + +

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) + +

    Init_Plateau (Thumb, 98 bytes, Stack size 8 bytes, plateau.o(i.Init_Plateau)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = Init_Plateau ⇒ MyTimer_PWM ⇒ MyGPIO_Init +
    +
    [Calls]
    • >>   MyTimer_PWM +
    • >>   MyTimer_Base_Start +
    • >>   MyTimer_Base_Init +
    • >>   MyGPIO_Init +
    +
    [Called By]
    • >>   Set_Moteur_Plateau +
    + +

    MyGPIO_Init (Thumb, 166 bytes, Stack size 12 bytes, driver_gpio.o(i.MyGPIO_Init)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = MyGPIO_Init +
    +
    [Called By]
    • >>   Init_Plateau +
    • >>   MyTimer_PWM +
    + +

    MyGPIO_Reset (Thumb, 14 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Reset)) +

    [Called By]

    • >>   Set_Direction +
    + +

    MyGPIO_Set (Thumb, 12 bytes, Stack size 0 bytes, driver_gpio.o(i.MyGPIO_Set)) +

    [Called By]

    • >>   Set_Direction +
    + +

    MyTimer_Base_Init (Thumb, 98 bytes, Stack size 0 bytes, mytimer.o(i.MyTimer_Base_Init)) +

    [Called By]

    • >>   Init_Plateau +
    + +

    MyTimer_Base_Start (Thumb, 10 bytes, Stack size 0 bytes, mytimer.o(i.MyTimer_Base_Start)) +

    [Called By]

    • >>   Init_Plateau +
    + +

    MyTimer_PWM (Thumb, 448 bytes, Stack size 24 bytes, mytimer.o(i.MyTimer_PWM)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = MyTimer_PWM ⇒ MyGPIO_Init +
    +
    [Calls]
    • >>   MyGPIO_Init +
    +
    [Called By]
    • >>   Init_Plateau +
    + +

    Set_Direction (Thumb, 34 bytes, Stack size 8 bytes, plateau.o(i.Set_Direction)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = Set_Direction +
    +
    [Calls]
    • >>   MyGPIO_Set +
    • >>   MyGPIO_Reset +
    +
    [Called By]
    • >>   Set_Moteur_Plateau +
    + +

    Set_Moteur_Plateau (Thumb, 24 bytes, Stack size 16 bytes, plateau.o(i.Set_Moteur_Plateau)) +

    [Stack]

    • Max Depth = 60
    • Call Chain = Set_Moteur_Plateau ⇒ Init_Plateau ⇒ MyTimer_PWM ⇒ MyGPIO_Init +
    +
    [Calls]
    • >>   Set_Vitesse +
    • >>   Set_Direction +
    • >>   Init_Plateau +
    +
    [Called By]
    • >>   main +
    + +

    Set_PWM_PRCT (Thumb, 56 bytes, Stack size 12 bytes, mytimer.o(i.Set_PWM_PRCT)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = Set_PWM_PRCT +
    +
    [Called By]
    • >>   Set_Vitesse +
    + +

    Set_Vitesse (Thumb, 22 bytes, Stack size 8 bytes, plateau.o(i.Set_Vitesse)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Set_Vitesse ⇒ Set_PWM_PRCT +
    +
    [Calls]
    • >>   Set_PWM_PRCT +
    +
    [Called By]
    • >>   Set_Moteur_Plateau +
    + +

    SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72 +
    +
    [Calls]
    • >>   SetSysClock +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(.text) +
    +

    TIM1_UP_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM1_UP_IRQHandler)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = TIM1_UP_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    TIM2_IRQHandler (Thumb, 32 bytes, Stack size 8 bytes, mytimer.o(i.TIM2_IRQHandler)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = TIM2_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    TIM3_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM3_IRQHandler)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = TIM3_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    TIM4_IRQHandler (Thumb, 28 bytes, Stack size 8 bytes, mytimer.o(i.TIM4_IRQHandler)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = TIM4_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) + +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) + +

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) + +

    main (Thumb, 12 bytes, Stack size 0 bytes, main.o(i.main)) +

    [Stack]

    • Max Depth = 60
    • Call Chain = main ⇒ Set_Moteur_Plateau ⇒ Init_Plateau ⇒ MyTimer_PWM ⇒ MyGPIO_Init +
    +
    [Calls]
    • >>   Set_Moteur_Plateau +
    +
    [Address Reference Count : 1]
    • entry9a.o(.ARM.Collect$$$$0000000B) +

    +

    +Local Symbols +

    +

    SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = SetSysClock ⇒ SetSysClockTo72 +
    +
    [Calls]
    • >>   SetSysClockTo72 +
    +
    [Called By]
    • >>   SystemInit +
    + +

    SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = SetSysClockTo72 +
    +
    [Called By]
    • >>   SetSysClock +
    +

    +

    +Undefined Global Symbols +

    diff --git a/Objects/Projet1_Simulation.lnp b/Objects/Projet1_Simulation.lnp index f0dacfa..4345d6b 100644 --- a/Objects/Projet1_Simulation.lnp +++ b/Objects/Projet1_Simulation.lnp @@ -1,12 +1,12 @@ ---cpu Cortex-M3 -".\objects\main.o" -".\objects\driver_gpio.o" -".\objects\mytimer.o" -".\objects\myadc.o" -".\objects\plateau.o" -".\objects\telecommande.o" -".\objects\startup_stm32f10x_md.o" -".\objects\system_stm32f10x.o" ---library_type=microlib --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols ---info sizes --info totals --info unused --info veneers +--cpu Cortex-M3 +".\objects\main.o" +".\objects\driver_gpio.o" +".\objects\mytimer.o" +".\objects\myadc.o" +".\objects\plateau.o" +".\objects\telecommande.o" +".\objects\startup_stm32f10x_md.o" +".\objects\system_stm32f10x.o" +--library_type=microlib --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers --list ".\Listings\Projet1_Simulation.map" -o .\Objects\Projet1_Simulation.axf \ No newline at end of file diff --git a/Objects/Projet1_Simulation.sct b/Objects/Projet1_Simulation.sct index bbacbc6..418dc4b 100644 --- a/Objects/Projet1_Simulation.sct +++ b/Objects/Projet1_Simulation.sct @@ -1,16 +1,16 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00020000 { ; load region size_region - ER_IROM1 0x08000000 0x00020000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - RW_IRAM1 0x20000000 0x00005000 { ; RW data - .ANY (+RW +ZI) - } -} - +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00005000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/Objects/driver_gpio.d b/Objects/driver_gpio.d index 58fa7a7..01975b2 100644 --- a/Objects/driver_gpio.d +++ b/Objects/driver_gpio.d @@ -1,10 +1,10 @@ -.\objects\driver_gpio.o: U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c -.\objects\driver_gpio.o: U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.h -.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h -.\objects\driver_gpio.o: .\RTE\_SImulation\RTE_Components.h -.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h -.\objects\driver_gpio.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h -.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h -.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h -.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h -.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h +.\objects\driver_gpio.o: U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c +.\objects\driver_gpio.o: U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.h +.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h +.\objects\driver_gpio.o: .\RTE\_SImulation\RTE_Components.h +.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h +.\objects\driver_gpio.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h +.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h +.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h +.\objects\driver_gpio.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h diff --git a/Objects/driver_gpio.o b/Objects/driver_gpio.o index 1a7264750b9d90315bb765e8f8b660377f0f600e..84d401cf8357f117cd706a8165070373db7a51fa 100644 GIT binary patch delta 79 zcmdn-g@4Bv{teMWG8PI(21Z6o42%r%@gbhRuJQ2-N(PozrWRHvCe7tS?d3v@K+Lqg iT!=YmDZ7bziixf+ELcu?GOBG8T3K delta 78 zcmdn-g@4Bv{teMWGKLC921Z6o42%r%@gbhRuJQ2-N`~fE2F6yVX3gb7?d3v@K+Lqg hT!=YmDO+lqg|0Ef?`Gz;2LO|R7H0qe diff --git a/Objects/main.crf b/Objects/main.crf index c5c87a002f0b04fd8ff50478d80344f3dff66e83..b3e75dd39cd60af9c9b4d47137fbfc9272730880 100644 GIT binary patch delta 756 zcmZvaUr5tY6vxlGKi&4byPFQzKdiijCP>JI9(w3$pyeP_rU}7f$ox@*HNkB?=8ufb zio`5_Y4#FfL0K8Wdg!4Dv8>GgD7y7ngh83$OHXyS{ji6+Pan?tp6~bE%Uz!J4$OJQ zq7J|iJPQi+N%4#Eo2xUU4xkeqF4J~4R0G>wAKn*>8^J_0p6)Wjt?|y3(V4D429K;C zMd|6KO2D$V?sQMoNQRGh#uD|>zuk$xkk%j4FcZ>PVzAc_tpErhnh&=g2(&i_4n>+E zob}mdy{RP>3Is!q5Xo+|Yu>=Y_F!baF_YZ@<=aci!xK!zQW1M2@MS%)%R#rn(xj0{ zLJb)db>2236={g|7|~R3tUCcWvgNkYbt0BBl1T&RvwmAF^5PD=-1U#=eaBrq!m@WCS&ia0f)#0a1^=%g4kG0m&3aiB@*3=67sypF| zz~8!Tx1RlERkcnS5!lb=bj}H*0?%?eMRZNz0GH2+#sr?{@@b}Om1!Cce-pUOr9ZQ0 zjh&oqaljqLow6e5fV+yjq>o@iab1?>INVd5OTNj(qvUg6<>@-ng942aO)9>{#1W#0 z1-fc&8`pMI$YaH~nmA}38P`U8o$x}r9VT8T-Am6 zmC)oGRo^I4B0VJOAn~jcP7^N>y;Xt?&JoQOXn^RQ61s`~MDGi9hUkM5ZWH^6YCab5 ZRL%|a1_c*OE=h|v zfI^^ohOQd@PBUlYK2alhC#EQex)=ECYNb03 zw+MgP?*CN>gNqw#*P%2_5{~M&&~(%R6~gPT2z*4fk1h$N=>PiEKK9Az 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.\RTE\_SImulation\RTE_Components.h -.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h -.\objects\mytimer.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h -.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h -.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h -.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h -.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h -.\objects\mytimer.o: FileInclude\Driver_GPIO.h +.\objects\mytimer.o: FileInclude\MyTimer.c +.\objects\mytimer.o: FileInclude\MyTimer.h +.\objects\mytimer.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h +.\objects\mytimer.o: .\RTE\_SImulation\RTE_Components.h +.\objects\mytimer.o: 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C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h -.\objects\plateau.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h -.\objects\plateau.o: FileInclude\Driver_GPIO.h -.\objects\plateau.o: FileInclude\Plateau.h +.\objects\plateau.o: FileInclude\Plateau.c +.\objects\plateau.o: FileInclude\MyTimer.h +.\objects\plateau.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h +.\objects\plateau.o: .\RTE\_SImulation\RTE_Components.h +.\objects\plateau.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h +.\objects\plateau.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\plateau.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h +.\objects\plateau.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h +.\objects\plateau.o: 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    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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898 @@ -3593,7 +3593,7 @@ 0 1920 - 1200 + 1080 @@ -3603,11 +3603,11 @@ 0 100 - 7 + 8 .\FileInclude\MyTimer.h 41 - 1 + 6 39 1 @@ -3615,9 +3615,9 @@ .\FileInclude\MyTimer.c - 52 - 264 - 106 + 17 + 247 + 259 1 0 @@ -3625,7 +3625,7 @@ U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c 51 - 7 + 10 43 1 @@ -3660,18 +3660,36 @@ .\FileInclude\Plateau.h - 74 + 22 1 - 5 + 4 1 0 .\FileInclude\Plateau.c - 8 + 30 + 17 + 43 + 1 + + 0 + + + .\Sources\main.c + 0 1 - 32 + 16 + 1 + + 0 + + + RTE\Device\STM32F103RB\startup_stm32f10x_md.s + 0 + 130 + 133 1 0 diff --git a/Projet1.uvoptx b/Projet1.uvoptx index ca2c1c6..0d951a5 100644 --- a/Projet1.uvoptx +++ b/Projet1.uvoptx @@ -125,7 +125,7 @@ 0 DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=61,96,281,556,0)(111=60,88,280,548,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=676,514,1097,941,0)(121=-1,-1,-1,-1,0)(122=704,251,1125,678,0)(123=-1,-1,-1,-1,0)(140=848,409,1536,749,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=885,128,1479,879,0)(131=1134,338,1728,1089,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=1246,187,1849,938,0)(151=-1,-1,-1,-1,0) + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=61,96,281,556,0)(111=60,88,280,548,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1116,169,1537,596,0)(121=-1,-1,-1,-1,0)(122=704,251,1125,678,0)(123=-1,-1,-1,-1,0)(140=848,409,1536,749,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=885,128,1479,879,0)(131=1134,244,1728,995,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=1246,187,1849,938,0)(151=-1,-1,-1,-1,0) 0 @@ -185,12 +185,17 @@ 0 ((PORTC & 0x00000400) >> 10 & 0x400) >> 10 - FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028504F5254432026203078303030303034303029203E3E2031300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000E03F170000000000000000000000000000000000000030040008 + FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028504F5254432026203078303030303034303029203E3E2031300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000565555555555D53F0B0000000000000000000000000000000000000030040008 1 - ((PORTA & 0x00000008) >> 3 & 0x8) >> 3 - 00800000000000000000000000000000E0FFEF400100000000000000000000000000000028504F5254412026203078303030303030303829203E3E2033000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000002000000000000000000E03F17000000000000000000000000000000000000007E050008 + ((PORTA & 0x00000008) >> 3 & 0x40) >> 5 + 00800000000000000000000000000000E0FFEF400100000000000000000000000000000028504F5254412026203078303030303030303829203E3E2033000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000002000000565555555555D53F0B000000000000000000000000000000000000007E050008 + + + 2 + ((PORTA & 0x00000040) >> 5 & 0x40) >> 5 + 00008000000000000000000000000000E0FFEF400000000000000000000000000000000028504F5254412026203078303030303030343029203E3E2035000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000003000000555555555555D53F0B000000000000000000000000000000000000006A070008 diff --git a/README.md b/README.md index 29ad09b..ca3f1f5 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ -# TP_Voilier - -TP du Voilier de 4A IR SI - -## Partie 1 Drivers: +# TP_Voilier + +TP du Voilier de 4A IR SI + +## Partie 1 Drivers: diff --git a/RTE/Device/STM32F103RB/RTE_Device.h b/RTE/Device/STM32F103RB/RTE_Device.h index 22d1da2..d4c8526 100644 --- a/RTE/Device/STM32F103RB/RTE_Device.h +++ b/RTE/Device/STM32F103RB/RTE_Device.h @@ -1,1828 +1,1828 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 09. September 2016 - * $Revision: V1.1.2 - * - * Project: RTE Device Configuration for STMicroelectronics STM32F1xx - * - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 8000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 72000000 -// HCLK Clock <1-999999999> -#define RTE_HCLK 72000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 36000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 72000000 -// ADC Clock <1-999999999> -#define RTE_ADCCLK 36000000 -// USB Clock -#define RTE_USBCLK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>Not Used <1=>PA9 -#define RTE_USART1_TX_PORT_ID_DEF 0 -#if (RTE_USART1_TX_PORT_ID_DEF == 0) -#define RTE_USART1_TX_DEF 0 -#elif (RTE_USART1_TX_PORT_ID_DEF == 1) -#define RTE_USART1_TX_DEF 1 -#define RTE_USART1_TX_PORT_DEF GPIOA -#define RTE_USART1_TX_BIT_DEF 9 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>Not Used <1=>PA10 -#define RTE_USART1_RX_PORT_ID_DEF 0 -#if (RTE_USART1_RX_PORT_ID_DEF == 0) -#define RTE_USART1_RX_DEF 0 -#elif (RTE_USART1_RX_PORT_ID_DEF == 1) -#define RTE_USART1_RX_DEF 1 -#define RTE_USART1_RX_PORT_DEF GPIOA -#define RTE_USART1_RX_BIT_DEF 10 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// USART1_CK Pin <0=>Not Used <1=>PA8 -#define RTE_USART1_CK_PORT_ID_DEF 0 -#if (RTE_USART1_CK_PORT_ID_DEF == 0) -#define RTE_USART1_CK 0 -#elif (RTE_USART1_CK_PORT_ID_DEF == 1) -#define RTE_USART1_CK 1 -#define RTE_USART1_CK_PORT_DEF GPIOA -#define RTE_USART1_CK_BIT_DEF 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// USART1_CTS Pin <0=>Not Used <1=>PA11 -#define RTE_USART1_CTS_PORT_ID_DEF 0 -#if (RTE_USART1_CTS_PORT_ID_DEF == 0) -#define RTE_USART1_CTS 0 -#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) -#define RTE_USART1_CTS 1 -#define RTE_USART1_CTS_PORT_DEF GPIOA -#define RTE_USART1_CTS_BIT_DEF 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif - -// USART1_RTS Pin <0=>Not Used <1=>PA12 -#define RTE_USART1_RTS_PORT_ID_DEF 0 -#if (RTE_USART1_RTS_PORT_ID_DEF == 0) -#define RTE_USART1_RTS 0 -#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) -#define RTE_USART1_RTS 1 -#define RTE_USART1_RTS_PORT_DEF GPIOA -#define RTE_USART1_RTS_BIT_DEF 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// USART1 Pin Remap -// Enable USART1 Pin Remapping -#define RTE_USART1_REMAP_FULL 0 - -// USART1_TX Pin <0=>Not Used <1=>PB6 -#define RTE_USART1_TX_PORT_ID_FULL 0 -#if (RTE_USART1_TX_PORT_ID_FULL == 0) -#define RTE_USART1_TX_FULL 0 -#elif (RTE_USART1_TX_PORT_ID_FULL == 1) -#define RTE_USART1_TX_FULL 1 -#define RTE_USART1_TX_PORT_FULL GPIOB -#define RTE_USART1_TX_BIT_FULL 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>Not Used <1=>PB7 -#define RTE_USART1_RX_PORT_ID_FULL 0 -#if (RTE_USART1_RX_PORT_ID_FULL == 0) -#define RTE_USART1_RX_FULL 0 -#elif (RTE_USART1_RX_PORT_ID_FULL == 1) -#define RTE_USART1_RX_FULL 1 -#define RTE_USART1_RX_PORT_FULL GPIOB -#define RTE_USART1_RX_BIT_FULL 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif -// - -#if (RTE_USART1_REMAP_FULL) -#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP -#define RTE_USART1_TX RTE_USART1_TX_FULL -#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL -#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL -#define RTE_USART1_RX RTE_USART1_RX_FULL -#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL -#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL -#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF -#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF -#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF -#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF -#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF -#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF -#else -#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP -#define RTE_USART1_TX RTE_USART1_TX_DEF -#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF -#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF -#define RTE_USART1_RX RTE_USART1_RX_DEF -#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF -#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF -#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF -#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF -#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF -#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF -#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF -#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Set DMA Channel priority -// -#define RTE_USART1_RX_DMA 0 -#define RTE_USART1_RX_DMA_NUMBER 1 -#define RTE_USART1_RX_DMA_CHANNEL 5 -#define RTE_USART1_RX_DMA_PRIORITY 0 -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Set DMA Channel priority -// -#define RTE_USART1_TX_DMA 0 -#define RTE_USART1_TX_DMA_NUMBER 1 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>Not Used <1=>PA2 -#define RTE_USART2_TX_PORT_ID_DEF 0 -#if (RTE_USART2_TX_PORT_ID_DEF == 0) -#define RTE_USART2_TX_DEF 0 -#elif (RTE_USART2_TX_PORT_ID_DEF == 1) -#define RTE_USART2_TX_DEF 1 -#define RTE_USART2_TX_PORT_DEF GPIOA -#define RTE_USART2_TX_BIT_DEF 2 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>Not Used <1=>PA3 -#define RTE_USART2_RX_PORT_ID_DEF 0 -#if (RTE_USART2_RX_PORT_ID_DEF == 0) -#define RTE_USART2_RX_DEF 0 -#elif (RTE_USART2_RX_PORT_ID_DEF == 1) -#define RTE_USART2_RX_DEF 1 -#define RTE_USART2_RX_PORT_DEF GPIOA -#define RTE_USART2_RX_BIT_DEF 3 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// USART2_CK Pin <0=>Not Used <1=>PA4 -#define RTE_USART2_CK_PORT_ID_DEF 0 -#if (RTE_USART2_CK_PORT_ID_DEF == 0) -#define RTE_USART2_CK_DEF 0 -#elif (RTE_USART2_CK_PORT_ID_DEF == 1) -#define RTE_USART2_CK_DEF 1 -#define RTE_USART2_CK_PORT_DEF GPIOA -#define RTE_USART2_CK_BIT_DEF 4 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// USART2_CTS Pin <0=>Not Used <1=>PA0 -#define RTE_USART2_CTS_PORT_ID_DEF 0 -#if (RTE_USART2_CTS_PORT_ID_DEF == 0) -#define RTE_USART2_CTS_DEF 0 -#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) -#define RTE_USART2_CTS_DEF 1 -#define RTE_USART2_CTS_PORT_DEF GPIOA -#define RTE_USART2_CTS_BIT_DEF 0 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif - -// USART2_RTS Pin <0=>Not Used <1=>PA1 -#define RTE_USART2_RTS_PORT_ID_DEF 0 -#if (RTE_USART2_RTS_PORT_ID_DEF == 0) -#define RTE_USART2_RTS_DEF 0 -#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) -#define RTE_USART2_RTS_DEF 1 -#define RTE_USART2_RTS_PORT_DEF GPIOA -#define RTE_USART2_RTS_BIT_DEF 1 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// USART2 Pin Remap -// Enable USART2 Pin Remapping -#define RTE_USART2_REMAP_FULL 0 - -// USART2_TX Pin <0=>Not Used <1=>PD5 -#define RTE_USART2_TX_PORT_ID_FULL 0 -#if (RTE_USART2_TX_PORT_ID_FULL == 0) -#define RTE_USART2_TX_FULL 0 -#elif (RTE_USART2_TX_PORT_ID_FULL == 1) -#define RTE_USART2_TX_FULL 1 -#define RTE_USART2_TX_PORT_FULL GPIOD -#define RTE_USART2_TX_BIT_FULL 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>Not Used <1=>PD6 -#define RTE_USART2_RX_PORT_ID_FULL 0 -#if (RTE_USART2_RX_PORT_ID_FULL == 0) -#define RTE_USART2_RX_FULL 0 -#elif (RTE_USART2_RX_PORT_ID_FULL == 1) -#define RTE_USART2_RX_FULL 1 -#define RTE_USART2_RX_PORT_FULL GPIOD -#define RTE_USART2_RX_BIT_FULL 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// USART2_CK Pin <0=>Not Used <1=>PD7 -#define RTE_USART2_CK_PORT_ID_FULL 0 -#if (RTE_USART2_CK_PORT_ID_FULL == 0) -#define RTE_USART2_CK_FULL 0 -#elif (RTE_USART2_CK_PORT_ID_FULL == 1) -#define RTE_USART2_CK_FULL 1 -#define RTE_USART2_CK_PORT_FULL GPIOD -#define RTE_USART2_CK_BIT_FULL 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// USART2_CTS Pin <0=>Not Used <1=>PD3 -#define RTE_USART2_CTS_PORT_ID_FULL 0 -#if (RTE_USART2_CTS_PORT_ID_FULL == 0) -#define RTE_USART2_CTS_FULL 0 -#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) -#define RTE_USART2_CTS_FULL 1 -#define RTE_USART2_CTS_PORT_FULL GPIOD -#define RTE_USART2_CTS_BIT_FULL 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif - -// USART2_RTS Pin <0=>Not Used <1=>PD4 -#define RTE_USART2_RTS_PORT_ID_FULL 0 -#if (RTE_USART2_RTS_PORT_ID_FULL == 0) -#define RTE_USART2_RTS_FULL 0 -#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) -#define RTE_USART2_RTS_FULL 1 -#define RTE_USART2_RTS_PORT_FULL GPIOD -#define RTE_USART2_RTS_BIT_FULL 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif -// - -#if (RTE_USART2_REMAP_FULL) -#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP -#define RTE_USART2_TX RTE_USART2_TX_FULL -#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL -#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL -#define RTE_USART2_RX RTE_USART2_RX_FULL -#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL -#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL -#define RTE_USART2_CK RTE_USART2_CK_FULL -#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL -#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL -#define RTE_USART2_CTS RTE_USART2_CTS_FULL -#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL -#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL -#define RTE_USART2_RTS RTE_USART2_RTS_FULL -#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL -#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL -#else -#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP -#define RTE_USART2_TX RTE_USART2_TX_DEF -#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF -#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF -#define RTE_USART2_RX RTE_USART2_RX_DEF -#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF -#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF -#define RTE_USART2_CK RTE_USART2_CK_DEF -#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF -#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF -#define RTE_USART2_CTS RTE_USART2_CTS_DEF -#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF -#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF -#define RTE_USART2_RTS RTE_USART2_RTS_DEF -#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF -#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <6=>6 -// Selects DMA Channel (only Channel 6 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Set DMA Channel priority -// -#define RTE_USART2_RX_DMA 0 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_CHANNEL 6 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Set DMA Channel priority -// -#define RTE_USART2_TX_DMA 0 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_CHANNEL 7 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>Not Used <1=>PB10 -#define RTE_USART3_TX_PORT_ID_DEF 0 -#if (RTE_USART3_TX_PORT_ID_DEF == 0) -#define RTE_USART3_TX_DEF 0 -#elif (RTE_USART3_TX_PORT_ID_DEF == 1) -#define RTE_USART3_TX_DEF 1 -#define RTE_USART3_TX_PORT_DEF GPIOB -#define RTE_USART3_TX_BIT_DEF 10 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PB11 -#define RTE_USART3_RX_PORT_ID_DEF 0 -#if (RTE_USART3_RX_PORT_ID_DEF == 0) -#define RTE_USART3_RX_DEF 0 -#elif (RTE_USART3_RX_PORT_ID_DEF == 1) -#define RTE_USART3_RX_DEF 1 -#define RTE_USART3_RX_PORT_DEF GPIOB -#define RTE_USART3_RX_BIT_DEF 11 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PB12 -#define RTE_USART3_CK_PORT_ID_DEF 0 -#if (RTE_USART3_CK_PORT_ID_DEF == 0) -#define RTE_USART3_CK_DEF 0 -#elif (RTE_USART3_CK_PORT_ID_DEF == 1) -#define RTE_USART3_CK_DEF 1 -#define RTE_USART3_CK_PORT_DEF GPIOB -#define RTE_USART3_CK_BIT_DEF 12 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// USART3_CTS Pin <0=>Not Used <1=>PB13 -#define RTE_USART3_CTS_PORT_ID_DEF 0 -#if (RTE_USART3_CTS_PORT_ID_DEF == 0) -#define RTE_USART3_CTS_DEF 0 -#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) -#define RTE_USART3_CTS_DEF 1 -#define RTE_USART3_CTS_PORT_DEF GPIOB -#define RTE_USART3_CTS_BIT_DEF 13 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif - -// USART3_RTS Pin <0=>Not Used <1=>PB14 -#define RTE_USART3_RTS_PORT_ID_DEF 0 -#if (RTE_USART3_RTS_PORT_ID_DEF == 0) -#define RTE_USART3_RTS_DEF 0 -#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) -#define RTE_USART3_RTS_DEF 1 -#define RTE_USART3_RTS_PORT_DEF GPIOB -#define RTE_USART3_RTS_BIT_DEF 14 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// USART3 Partial Pin Remap -// Enable USART3 Partial Pin Remapping -#define RTE_USART3_REMAP_PARTIAL 0 - -// USART3_TX Pin <0=>Not Used <1=>PC10 -#define RTE_USART3_TX_PORT_ID_PARTIAL 0 -#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) -#define RTE_USART3_TX_PARTIAL 0 -#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) -#define RTE_USART3_TX_PARTIAL 1 -#define RTE_USART3_TX_PORT_PARTIAL GPIOC -#define RTE_USART3_TX_BIT_PARTIAL 10 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PC11 -#define RTE_USART3_RX_PORT_ID_PARTIAL 0 -#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) -#define RTE_USART3_RX_PARTIAL 0 -#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) -#define RTE_USART3_RX_PARTIAL 1 -#define RTE_USART3_RX_PORT_PARTIAL GPIOC -#define RTE_USART3_RX_BIT_PARTIAL 11 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PC12 -#define RTE_USART3_CK_PORT_ID_PARTIAL 0 -#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) -#define RTE_USART3_CK_PARTIAL 0 -#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) -#define RTE_USART3_CK_PARTIAL 1 -#define RTE_USART3_CK_PORT_PARTIAL GPIOC -#define RTE_USART3_CK_BIT_PARTIAL 12 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif -// - -// USART3 Full Pin Remap -// Enable USART3 Full Pin Remapping -#define RTE_USART3_REMAP_FULL 0 - -// USART3_TX Pin <0=>Not Used <1=>PD8 -#define RTE_USART3_TX_PORT_ID_FULL 0 -#if (RTE_USART3_TX_PORT_ID_FULL == 0) -#define RTE_USART3_TX_FULL 0 -#elif (RTE_USART3_TX_PORT_ID_FULL == 1) -#define RTE_USART3_TX_FULL 1 -#define RTE_USART3_TX_PORT_FULL GPIOD -#define RTE_USART3_TX_BIT_FULL 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PD9 -#define RTE_USART3_RX_PORT_ID_FULL 0 -#if (RTE_USART3_RX_PORT_ID_FULL == 0) -#define RTE_USART3_RX_FULL 0 -#elif (RTE_USART3_RX_PORT_ID_FULL == 1) -#define RTE_USART3_RX_FULL 1 -#define RTE_USART3_RX_PORT_FULL GPIOD -#define RTE_USART3_RX_BIT_FULL 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PD10 -#define RTE_USART3_CK_PORT_ID_FULL 0 -#if (RTE_USART3_CK_PORT_ID_FULL == 0) -#define RTE_USART3_CK_FULL 0 -#elif (RTE_USART3_CK_PORT_ID_FULL == 1) -#define RTE_USART3_CK_FULL 1 -#define RTE_USART3_CK_PORT_FULL GPIOD -#define RTE_USART3_CK_BIT_FULL 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// USART3_CTS Pin <0=>Not Used <1=>PD11 -#define RTE_USART3_CTS_PORT_ID_FULL 0 -#if (RTE_USART3_CTS_PORT_ID_FULL == 0) -#define RTE_USART3_CTS_FULL 0 -#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) -#define RTE_USART3_CTS_FULL 1 -#define RTE_USART3_CTS_PORT_FULL GPIOD -#define RTE_USART3_CTS_BIT_FULL 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif - -// USART3_RTS Pin <0=>Not Used <1=>PD12 -#define RTE_USART3_RTS_PORT_ID_FULL 0 -#if (RTE_USART3_RTS_PORT_ID_FULL == 0) -#define RTE_USART3_RTS_FULL 0 -#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) -#define RTE_USART3_RTS_FULL 1 -#define RTE_USART3_RTS_PORT_FULL GPIOD -#define RTE_USART3_RTS_BIT_FULL 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif -// - -#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) -#error "Invalid USART3 Pin Remap Configuration!" -#endif - -#if (RTE_USART3_REMAP_FULL) -#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL -#define RTE_USART3_TX RTE_USART3_TX_FULL -#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL -#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL -#define RTE_USART3_RX RTE_USART3_RX_FULL -#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL -#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL -#define RTE_USART3_CK RTE_USART3_CK_FULL -#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL -#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL -#define RTE_USART3_CTS RTE_USART3_CTS_FULL -#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL -#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL -#define RTE_USART3_RTS RTE_USART3_RTS_FULL -#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL -#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL -#elif (RTE_USART3_REMAP_PARTIAL) -#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL -#define RTE_USART3_TX RTE_USART3_TX_PARTIAL -#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL -#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL -#define RTE_USART3_RX RTE_USART3_RX_PARTIAL -#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL -#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL -#define RTE_USART3_CK RTE_USART3_CK_PARTIAL -#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL -#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL -#define RTE_USART3_CTS RTE_USART3_CTS_DEF -#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF -#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF -#define RTE_USART3_RTS RTE_USART3_RTS_DEF -#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF -#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF -#else -#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP -#define RTE_USART3_TX RTE_USART3_TX_DEF -#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF -#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF -#define RTE_USART3_RX RTE_USART3_RX_DEF -#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF -#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF -#define RTE_USART3_CK RTE_USART3_CK_DEF -#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF -#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF -#define RTE_USART3_CTS RTE_USART3_CTS_DEF -#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF -#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF -#define RTE_USART3_RTS RTE_USART3_RTS_DEF -#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF -#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Sets DMA Channel priority -// -#define RTE_USART3_RX_DMA 0 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_CHANNEL 3 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <2=>2 -// Selects DMA Channel (only Channel 2 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Sets DMA Channel priority -// -#define RTE_USART3_TX_DMA 0 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_CHANNEL 2 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) -// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART -#define RTE_UART4 0 -#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP - -// UART4_TX Pin <0=>Not Used <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>Not Used <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX 0 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Sets DMA Channel priority -// -#define RTE_UART4_RX_DMA 0 -#define RTE_UART4_RX_DMA_NUMBER 2 -#define RTE_UART4_RX_DMA_CHANNEL 3 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Sets DMA Channel priority -// -#define RTE_UART4_TX_DMA 0 -#define RTE_UART4_TX_DMA_NUMBER 2 -#define RTE_UART4_TX_DMA_CHANNEL 5 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) -// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART -#define RTE_UART5 0 -#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP - -// UART5_TX Pin <0=>Not Used <1=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX 0 -#elif (RTE_UART5_TX_ID == 1) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>Not Used <1=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX 0 -#elif (RTE_UART5_RX_ID == 1) -#define RTE_UART5_RX 1 -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif -// - - -// I2C1 (Inter-integrated Circuit Interface 1) -// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 -#define RTE_I2C1_SCL_PORT_ID_DEF 0 -#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) -#define RTE_I2C1_SCL_PORT_DEF GPIOB -#define RTE_I2C1_SCL_BIT_DEF 6 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 -#define RTE_I2C1_SDA_PORT_ID_DEF 0 -#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) -#define RTE_I2C1_SDA_PORT_DEF GPIOB -#define RTE_I2C1_SDA_BIT_DEF 7 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1 Pin Remap -// Enable I2C1 Pin Remapping -#define RTE_I2C1_REMAP_FULL 0 - -// I2C1_SCL Pin <0=>PB8 -#define RTE_I2C1_SCL_PORT_ID_FULL 0 -#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) -#define RTE_I2C1_SCL_PORT_FULL GPIOB -#define RTE_I2C1_SCL_BIT_FULL 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB9 -#define RTE_I2C1_SDA_PORT_ID_FULL 0 -#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) -#define RTE_I2C1_SDA_PORT_FULL GPIOB -#define RTE_I2C1_SDA_BIT_FULL 9 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// - -#if (RTE_I2C1_REMAP_FULL) -#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP -#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL -#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL -#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL -#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL -#else -#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP -#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF -#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF -#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF -#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF -#endif - - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 0 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_CHANNEL 7 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <6=>6 -// Selects DMA Channel (only Channel 6 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 0 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_CHANNEL 6 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) -// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C -#define RTE_I2C2 0 -#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP - -// I2C2_SCL Pin <0=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_CHANNEL 5 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_CHANNEL 4 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..G, y = 0..15) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 -#define RTE_SPI1_SCK_PORT_ID_DEF 0 -#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) -#define RTE_SPI1_SCK_PORT_DEF GPIOA -#define RTE_SPI1_SCK_BIT_DEF 5 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>Not Used <1=>PA6 -#define RTE_SPI1_MISO_PORT_ID_DEF 0 -#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) -#define RTE_SPI1_MISO_DEF 0 -#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) -#define RTE_SPI1_MISO_DEF 1 -#define RTE_SPI1_MISO_PORT_DEF GPIOA -#define RTE_SPI1_MISO_BIT_DEF 6 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>Not Used <1=>PA7 -#define RTE_SPI1_MOSI_PORT_ID_DEF 0 -#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) -#define RTE_SPI1_MOSI_DEF 0 -#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) -#define RTE_SPI1_MOSI_DEF 1 -#define RTE_SPI1_MOSI_PORT_DEF GPIOA -#define RTE_SPI1_MOSI_BIT_DEF 7 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1 Pin Remap -// Enable SPI1 Pin Remapping. -#define RTE_SPI1_REMAP 0 - -// SPI1_SCK Pin <0=>PB3 -#define RTE_SPI1_SCK_PORT_ID_FULL 0 -#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) -#define RTE_SPI1_SCK_PORT_FULL GPIOB -#define RTE_SPI1_SCK_BIT_FULL 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>Not Used <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID_FULL 0 -#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) -#define RTE_SPI1_MISO_FULL 0 -#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) -#define RTE_SPI1_MISO_FULL 1 -#define RTE_SPI1_MISO_PORT_FULL GPIOB -#define RTE_SPI1_MISO_BIT_FULL 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif -// SPI1_MOSI Pin <0=>Not Used <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID_FULL 0 -#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) -#define RTE_SPI1_MOSI_FULL 0 -#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) -#define RTE_SPI1_MOSI_FULL 1 -#define RTE_SPI1_MOSI_PORT_FULL GPIOB -#define RTE_SPI1_MOSI_BIT_FULL 5 -#else -#error "Invalid SPI1_MOSI Pin Configuration!" -#endif - -// - -#if (RTE_SPI1_REMAP) -#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP -#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL -#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL -#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL -#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL -#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL -#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL -#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL -#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL -#else -#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP -#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF -#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF -#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF -#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF -#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF -#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF -#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF -#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <2=>2 -// Selects DMA Channel (only Channel 2 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 0 -#define RTE_SPI1_RX_DMA_NUMBER 1 -#define RTE_SPI1_RX_DMA_CHANNEL 2 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 0 -#define RTE_SPI1_TX_DMA_NUMBER 1 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..G, y = 0..15) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB13 -#define RTE_SPI2_SCK_PORT_ID 0 -#if (RTE_SPI2_SCK_PORT_ID == 0) -#define RTE_SPI2_SCK_PORT GPIOB -#define RTE_SPI2_SCK_BIT 13 -#define RTE_SPI2_SCK_REMAP 0 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>Not Used <1=>PB14 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO 0 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#define RTE_SPI2_MISO_REMAP 0 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>Not Used <1=>PB15 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI 0 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#define RTE_SPI2_MOSI_REMAP 0 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 0 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_CHANNEL 4 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 0 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_CHANNEL 5 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..G, y = 0..15) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 -#define RTE_SPI3_SCK_PORT_ID_DEF 0 -#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) -#define RTE_SPI3_SCK_PORT_DEF GPIOB -#define RTE_SPI3_SCK_BIT_DEF 3 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>Not Used <1=>PB4 -#define RTE_SPI3_MISO_PORT_ID_DEF 0 -#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) -#define RTE_SPI3_MISO_DEF 0 -#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) -#define RTE_SPI3_MISO_DEF 1 -#define RTE_SPI3_MISO_PORT_DEF GPIOB -#define RTE_SPI3_MISO_BIT_DEF 4 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI <0=>Not Used Pin <1=>PB5 -#define RTE_SPI3_MOSI_PORT_ID_DEF 0 -#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) -#define RTE_SPI3_MOSI_DEF 0 -#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) -#define RTE_SPI3_MOSI_DEF 1 -#define RTE_SPI3_MOSI_PORT_DEF GPIOB -#define RTE_SPI3_MOSI_BIT_DEF 5 -#else -#error "Invalid SPI3_MOSI Pin Configuration!" -#endif - -// SPI3 Pin Remap -// Enable SPI3 Pin Remapping. -// SPI 3 Pin Remapping is available only in connectivity line devices! -#define RTE_SPI3_REMAP 0 - -// SPI3_SCK Pin <0=>PC10 -#define RTE_SPI3_SCK_PORT_ID_FULL 0 -#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) -#define RTE_SPI3_SCK_PORT_FULL GPIOC -#define RTE_SPI3_SCK_BIT_FULL 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>Not Used <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID_FULL 0 -#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) -#define RTE_SPI3_MISO_FULL 0 -#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) -#define RTE_SPI3_MISO_FULL 1 -#define RTE_SPI3_MISO_PORT_FULL GPIOC -#define RTE_SPI3_MISO_BIT_FULL 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif -// SPI3_MOSI Pin <0=>Not Used <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID_FULL 0 -#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) -#define RTE_SPI3_MOSI_FULL 0 -#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) -#define RTE_SPI3_MOSI_FULL 1 -#define RTE_SPI3_MOSI_PORT_FULL GPIOC -#define RTE_SPI3_MOSI_BIT_FULL 12 -#else -#error "Invalid SPI3_MOSI Pin Configuration!" -#endif - -// - -#if (RTE_SPI3_REMAP) -#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP -#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL -#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL -#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL -#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL -#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL -#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL -#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL -#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL -#else -#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP -#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF -#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF -#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF -#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF -#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF -#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF -#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF -#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 0 -#define RTE_SPI3_RX_DMA_NUMBER 2 -#define RTE_SPI3_RX_DMA_CHANNEL 1 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <2=>2 -// Selects DMA Channel (only Channel 2 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 0 -#define RTE_SPI3_TX_DMA_NUMBER 2 -#define RTE_SPI3_TX_DMA_CHANNEL 2 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI -#define RTE_SDIO 0 - -// SDIO Peripheral Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) - #define RTE_SDIO_CK_PORT GPIOC - #define RTE_SDIO_CK_PIN 12 -#else - #error "Invalid SDIO_CLK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) - #define RTE_SDIO_CMD_PORT GPIOD - #define RTE_SDIO_CMD_PIN 2 -#else - #error "Invalid SDIO_CMD Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) - #define RTE_SDIO_D0_PORT GPIOC - #define RTE_SDIO_D0_PIN 8 -#else - #error "Invalid SDIO_DAT0 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -#define RTE_SDIO_BUS_WIDTH_4 1 -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) - #define RTE_SDIO_D1_PORT GPIOC - #define RTE_SDIO_D1_PIN 9 -#else - #error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) - #define RTE_SDIO_D2_PORT GPIOC - #define RTE_SDIO_D2_PIN 10 -#else - #error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) - #define RTE_SDIO_D3_PORT GPIOC - #define RTE_SDIO_D3_PIN 11 -#else - #error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -// SDIO_D[4 .. 7] -#define RTE_SDIO_BUS_WIDTH_8 0 -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) - #define RTE_SDIO_D4_PORT GPIOB - #define RTE_SDIO_D4_PIN 8 -#else - #error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) - #define RTE_SDIO_D5_PORT GPIOB - #define RTE_SDIO_D5_PIN 9 -#else - #error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) - #define RTE_SDIO_D6_PORT GPIOC - #define RTE_SDIO_D6_PIN 6 -#else - #error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) - #define RTE_SDIO_D7_PORT GPIOC - #define RTE_SDIO_D7_PIN 7 -#else - #error "Invalid SDIO_D7 Pin Configuration!" -#endif -// SDIO_D[4 .. 7] -// SDIO Peripheral Bus - -// Card Detect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_EN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(5) -#define RTE_SDIO_CD_PIN 11 - -// Write Protect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_EN 0 -#define RTE_SDIO_WP_ACTIVE 1 -#define RTE_SDIO_WP_PORT GPIO_PORT(0) -#define RTE_SDIO_WP_PIN 10 - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// CAN1 (Controller Area Network 1) [Driver_CAN1] -// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN -#define RTE_CAN1 0 - -// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 -#define RTE_CAN1_RX_PORT_ID 0 -#if (RTE_CAN1_RX_PORT_ID == 0) -#define RTE_CAN1_RX_PORT GPIOA -#define RTE_CAN1_RX_BIT 11 -#elif (RTE_CAN1_RX_PORT_ID == 1) -#define RTE_CAN1_RX_PORT GPIOB -#define RTE_CAN1_RX_BIT 8 -#elif (RTE_CAN1_RX_PORT_ID == 2) -#define RTE_CAN1_RX_PORT GPIOD -#define RTE_CAN1_RX_BIT 0 -#else -#error "Invalid CAN1_RX Pin Configuration!" -#endif - -// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 -#define RTE_CAN1_TX_PORT_ID 0 -#if (RTE_CAN1_TX_PORT_ID == 0) -#define RTE_CAN1_TX_PORT GPIOA -#define RTE_CAN1_TX_BIT 12 -#elif (RTE_CAN1_TX_PORT_ID == 1) -#define RTE_CAN1_TX_PORT GPIOB -#define RTE_CAN1_TX_BIT 9 -#elif (RTE_CAN1_TX_PORT_ID == 2) -#define RTE_CAN1_TX_PORT GPIOD -#define RTE_CAN1_TX_BIT 1 -#else -#error "Invalid CAN1_TX Pin Configuration!" -#endif - -// - - -// CAN2 (Controller Area Network 2) [Driver_CAN2] -// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN -#define RTE_CAN2 0 - -// CAN2_RX Pin <0=>PB5 <1=>PB12 -#define RTE_CAN2_RX_PORT_ID 0 -#if (RTE_CAN2_RX_PORT_ID == 0) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT 5 -#elif (RTE_CAN2_RX_PORT_ID == 1) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT 12 -#else -#error "Invalid CAN2_RX Pin Configuration!" -#endif - -// CAN2_TX Pin <0=>PB6 <1=>PB13 -#define RTE_CAN2_TX_PORT_ID 0 -#if (RTE_CAN2_TX_PORT_ID == 0) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT 6 -#elif (RTE_CAN2_TX_PORT_ID == 1) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT 13 -#else -#error "Invalid CAN2_TX Pin Configuration!" -#endif - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC -#define RTE_ETH 0 - -// MII (Media Independent Interface) -// Enable Media Independent Interface pin configuration -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_DEF 0 - -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_DEF 0 - -// ETH_MII_RXD2 Pin <0=>PB0 -#define RTE_ETH_MII_RXD2_DEF 0 - -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 -#define RTE_ETH_MII_RXD3_DEF 0 - -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_DEF 0 - -// ETH_MII_RX_ER Pin <0=>PB10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// Ethernet MAC I/O remapping -// Remap Ethernet pins -#define RTE_ETH_MII_REMAP 0 - -// ETH_MII_RXD0 Pin <1=>PD9 -#define RTE_ETH_MII_RXD0_REMAP 1 - -// ETH_MII_RXD1 Pin <1=>PD10 -#define RTE_ETH_MII_RXD1_REMAP 1 - -// ETH_MII_RXD2 Pin <1=>PD11 -#define RTE_ETH_MII_RXD2_REMAP 1 - -// ETH_MII_RXD3 Pin <1=>PD12 -#define RTE_ETH_MII_RXD3_REMAP 1 - -// ETH_MII_RX_DV Pin <1=>PD8 -#define RTE_ETH_MII_RX_DV_REMAP 1 -// - -// - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) -#define RTE_ETH_MII_RXD0_PORT GPIOD -#define RTE_ETH_MII_RXD0_PIN 9 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) -#define RTE_ETH_MII_RXD1_PORT GPIOD -#define RTE_ETH_MII_RXD1_PIN 10 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) -#define RTE_ETH_MII_RXD2_PORT GPIOD -#define RTE_ETH_MII_RXD2_PIN 11 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) -#define RTE_ETH_MII_RXD3_PORT GPIOD -#define RTE_ETH_MII_RXD3_PIN 12 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) -#define RTE_ETH_MII_RX_DV_PORT GPIOD -#define RTE_ETH_MII_RX_DV_PIN 8 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 0 - -// ETH_RMII_TXD0 Pin <0=>PB12 -#define RTE_ETH_RMII_TXD0_PORT_ID 0 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 -#define RTE_ETH_RMII_TXD1_PORT_ID 0 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 0 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_DEF 0 - -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_DEF 0 - -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_DEF 0 - -// Ethernet MAC I/O remapping -// Remap Ethernet pins -#define RTE_ETH_RMII_REMAP 0 -// ETH_RMII_RXD0 Pin <1=>PD9 -#define RTE_ETH_RMII_RXD0_REMAP 1 - -// ETH_RMII_RXD1 Pin <1=>PD10 -#define RTE_ETH_RMII_RXD1_REMAP 1 - -// ETH_RMII_CRS_DV Pin <1=>PD8 -#define RTE_ETH_RMII_CRS_DV_REMAP 1 -// - -#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) -#define RTE_ETH_RMII_RXD0_PORT GPIOD -#define RTE_ETH_RMII_RXD0_PIN 9 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif - -#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) -#define RTE_ETH_RMII_RXD1_PORT GPIOD -#define RTE_ETH_RMII_RXD1_PIN 10 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif - -#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOD -#define RTE_ETH_RMII_CRS_DV_PIN 8 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled -#define RTE_ETH_REF_CLOCK_ID 0 -#if (RTE_ETH_REF_CLOCK_ID == 0) -#define RTE_ETH_REF_CLOCK 0 -#elif (RTE_ETH_REF_CLOCK_ID == 1) -#define RTE_ETH_REF_CLOCK 1 -#else -#error "Invalid MCO Ethernet Reference Clock Configuration!" -#endif -// - - -// USB Device Full-speed -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_DEVICE 0 - -// CON On/Off Pin -// Configure Pin for driving D+ pull-up -// GPIO Pxy (x = A..G, y = 0..15) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_USB_DEVICE_CON_PIN 1 -#define RTE_USB_DEVICE_CON_ACTIVE 0 -#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) -#define RTE_USB_DEVICE_CON_BIT 14 - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 0 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..G, y = 0..15) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_FS_VBUS_BIT 9 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..G, y = 0..15) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) -#define RTE_OTG_FS_OC_BIT 1 -// - -// - - -#endif /* __RTE_DEVICE_H */ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/RTE/Device/STM32F103RB/startup_stm32f10x_md.s index 74da96c..3223fc9 100644 --- a/RTE/Device/STM32F103RB/startup_stm32f10x_md.s +++ b/RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -1,307 +1,307 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_md.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1_2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT USBWakeUp_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_2_IRQHandler -USB_HP_CAN1_TX_IRQHandler -USB_LP_CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -USBWakeUp_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/RTE/Device/STM32F103RB/system_stm32f10x.c b/RTE/Device/STM32F103RB/system_stm32f10x.c index 71efc85..6fb4579 100644 --- a/RTE/Device/STM32F103RB/system_stm32f10x.c +++ b/RTE/Device/STM32F103RB/system_stm32f10x.c @@ -1,1094 +1,1094 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * factors, AHB/APBx prescalers and Flash settings). - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f10x_xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on - * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. - * When HSE is used as system clock source, directly or through PLL, and you - * are using different crystal you have to adapt the HSE value to your own - * configuration. - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

    © COPYRIGHT 2011 STMicroelectronics

    - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** @addtogroup STM32F10x_System_Private_Includes - * @{ - */ - -#include "stm32f10x.h" - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Defines - * @{ - */ - -/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) - frequency (after reset the HSI is used as SYSCLK source) - - IMPORTANT NOTE: - ============== - 1. After each device reset the HSI is used as System clock source. - - 2. Please make sure that the selected System clock doesn't exceed your device's - maximum frequency. - - 3. If none of the define below is enabled, the HSI is used as System clock - source. - - 4. The System clock configuration functions provided within this file assume that: - - For Low, Medium and High density Value line devices an external 8MHz - crystal is used to drive the System clock. - - For Low, Medium and High density devices an external 8MHz crystal is - used to drive the System clock. - - For Connectivity line devices an external 25MHz crystal is used to drive - the System clock. - If you are using different crystal you have to adapt those functions accordingly. - */ - -#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ - #define SYSCLK_FREQ_24MHz 24000000 -#else -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ -/* #define SYSCLK_FREQ_24MHz 24000000 */ -/* #define SYSCLK_FREQ_36MHz 36000000 */ -/* #define SYSCLK_FREQ_48MHz 48000000 */ -/* #define SYSCLK_FREQ_56MHz 56000000 */ -#define SYSCLK_FREQ_72MHz 72000000 -#endif - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM3210E-EVAL board (STM32 High density and XL-density devices) or on - STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) -/* #define DATA_IN_ExtSRAM */ -#endif - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif - -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#endif - -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) - #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); - #endif /* DATA_IN_ExtSRAM */ -#endif - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz or 25 MHz, depedning on the product used), user has to ensure - * that HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - SystemCoreClock = HSI_VALUE; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f10x.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f10x_xx.s/.c before jump to main. - * This function configures the external SRAM mounted on STM3210E-EVAL - * board (STM32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is - required, then adjust the Register Addresses */ - - /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; - -/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ -/*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ -/*---------------- NE3 configuration ----------------------------------------*/ -/*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; - - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; - - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; - - GPIOG->CRL = 0x44BBBBBB; - GPIOG->CRH = 0x44444B44; - -/*---------------- FSMC Configuration ---------------------------------------*/ -/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000200; -} -#endif /* DATA_IN_ExtSRAM */ - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - -#ifndef STM32F10X_CL - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#else - if (HSE_VALUE <= 24000000) - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; - } - else - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - } -#endif /* STM32F10X_CL */ -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); - - /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - -#else - /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL7); -#else - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); - -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); -#else - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | - RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2011 STMicroelectronics

    + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/RTE/_R_el/RTE_Components.h b/RTE/_R_el/RTE_Components.h index 3fec98e..f2bc09e 100644 --- a/RTE/_R_el/RTE_Components.h +++ b/RTE/_R_el/RTE_Components.h @@ -1,21 +1,21 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'Projet1' - * Target: 'Réel' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "stm32f10x.h" - - - -#endif /* RTE_COMPONENTS_H */ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Projet1' + * Target: 'Réel' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_SImulation/RTE_Components.h b/RTE/_SImulation/RTE_Components.h index cb38ff3..026f7e0 100644 --- a/RTE/_SImulation/RTE_Components.h +++ b/RTE/_SImulation/RTE_Components.h @@ -1,21 +1,21 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'Projet1' - * Target: 'SImulation' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "stm32f10x.h" - - - -#endif /* RTE_COMPONENTS_H */ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Projet1' + * Target: 'SImulation' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Target_1/RTE_Components.h b/RTE/_Target_1/RTE_Components.h index 4962829..d227377 100644 --- a/RTE/_Target_1/RTE_Components.h +++ b/RTE/_Target_1/RTE_Components.h @@ -1,21 +1,21 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'Projet1' - * Target: 'Target 1' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "stm32f10x.h" - - - -#endif /* RTE_COMPONENTS_H */ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Projet1' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Sources/main.c b/Sources/main.c index e4aeb20..7d4631d 100644 --- a/Sources/main.c +++ b/Sources/main.c @@ -1,51 +1,15 @@ -#include "stm32f10x.h" -#include -#include -#include - -int a ; - - void Callback(void){ - startADC(); - a=read(); - } - - -int main (void) -{ - //char channel = 1; - - // Configuration du timer - MyTimer_Struct_TypeDef TIM; - MyTimer_Struct_TypeDef * Data = &TIM; - Data->Timer = TIM2; - Data->ARR = 65535; - Data->PSC = 548; - MyTimer_Base_Init(Data); - - //MyTimer_PWM(Data->Timer, channel); - - - -// Set_PWM_PRCT(Data->Timer, channel, 20); - - - - initADC(1); - - - - - MyTimer_ActiveIT ( TIM2 , 1, &Callback); - - MyTimer_Base_Start(TIM2); - - - - - - - do { - } - while (1); -} +#include "stm32f10x.h" +#include +#include +#include +#include + + +int main (void) +{ + Set_Moteur_Plateau(ANTI_HORRAIRE,10); + + do { + } + while (1); +} From 43cb31a9ac826c55ba41e813cc84e06a05c8f2c1 Mon Sep 17 00:00:00 2001 From: alejeune Date: Fri, 28 Oct 2022 10:34:41 +0200 Subject: [PATCH 4/5] Init du .h de la telecommande --- FileInclude/Telecommande.c | 6 ++++ FileInclude/Telecommande.h | 20 +++++++++++ Projet1.uvguix.alejeune | 70 ++++++++++++++++++++++++-------------- 3 files changed, 70 insertions(+), 26 deletions(-) diff --git a/FileInclude/Telecommande.c b/FileInclude/Telecommande.c index e69de29..d66f23b 100644 --- a/FileInclude/Telecommande.c +++ b/FileInclude/Telecommande.c @@ -0,0 +1,6 @@ +#include "MyTimer.h" +#include "stm32f10x.h" +#include "Driver_GPIO.h" +#include "Plateau.h" +#include "Telecommande.h" + diff --git a/FileInclude/Telecommande.h b/FileInclude/Telecommande.h index e69de29..030bc72 100644 --- a/FileInclude/Telecommande.h +++ b/FileInclude/Telecommande.h @@ -0,0 +1,20 @@ +#ifndef MYTELCOMMANDE_H +#define MYTELCOMMANDE_H +#include "stm32f10x.h" + +/* Configuration de l'UART */ +void Init_UART (USART_TypeDef * UART); + +/* Envoie de messages */ +void Send_Message (char message[]); + +/* Reception de message */ +void Receive_Message (void (* pFonction) (char)); +//pFonction traitera le message + + + + + + +#endif diff --git a/Projet1.uvguix.alejeune b/Projet1.uvguix.alejeune index 358df9e..823aa34 100644 --- a/Projet1.uvguix.alejeune +++ b/Projet1.uvguix.alejeune @@ -90,8 +90,8 @@ 44 - 2 - 3 + 0 + 1 -1 -1 @@ -110,8 +110,8 @@ 0 - 1154 - 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898 @@ -3603,7 +3603,7 @@ 0 100 - 8 + 11 .\FileInclude\MyTimer.h 41 @@ -3662,16 +3662,16 @@ .\FileInclude\Plateau.h 22 1 - 4 + 5 1 0 .\FileInclude\Plateau.c - 30 - 17 - 43 + 0 + 1 + 1 1 0 @@ -3694,6 +3694,24 @@ 0 + + .\FileInclude\Telecommande.c + 0 + 1 + 7 + 1 + + 0 + + + .\FileInclude\Telecommande.h + 0 + 1 + 21 + 1 + + 0 + From 37c422237478c087252ce05bdbe172a737b486ff Mon Sep 17 00:00:00 2001 From: alejeune Date: Mon, 14 Nov 2022 17:50:04 +0100 Subject: [PATCH 5/5] fin UART telecommande et batterie et moteur plateau --- FileInclude/Batterie.c | 31 + FileInclude/Batterie.h | 11 + FileInclude/MyADC.c | 1 + FileInclude/Plateau.c | 4 +- FileInclude/Plateau.h | 2 +- FileInclude/Telecommande.c | 79 + FileInclude/Telecommande.h | 12 +- Listings/Projet1_Simulation.map | 323 +- Listings/startup_stm32f10x_md.lst | 12 +- Objects/Projet1_Réel.dep | 86 +- Objects/Projet1_SImulation.dep | 44 +- Objects/Projet1_Simulation.axf | Bin 237584 -> 238472 bytes Objects/Projet1_Simulation.build_log.htm | 27 +- Objects/Projet1_Simulation.htm | 189 +- Objects/Projet1_Simulation.lnp | 4 +- Objects/batterie.crf | Bin 0 -> 239510 bytes Objects/batterie.d | 13 + Objects/batterie.o | Bin 0 -> 259472 bytes Objects/driver_gpio.crf | Bin 238776 -> 238770 bytes Objects/driver_gpio.d | 2 +- Objects/driver_gpio.o | Bin 260664 -> 260644 bytes Objects/main.crf | Bin 239625 -> 240353 bytes Objects/main.d | 4 +- Objects/main.o | Bin 257112 -> 261704 bytes Objects/myadc.crf | Bin 239520 -> 239518 bytes Objects/myadc.d | 2 +- Objects/myadc.o | Bin 258596 -> 258664 bytes Objects/mytimer.crf | Bin 242626 -> 242620 bytes Objects/mytimer.d | 2 +- Objects/mytimer.o | Bin 272596 -> 272576 bytes Objects/plateau.crf | Bin 239960 -> 239954 bytes Objects/plateau.d | 2 +- Objects/plateau.o | Bin 262080 -> 262060 bytes Objects/startup_stm32f10x_md.o | Bin 5916 -> 5916 bytes Objects/system_stm32f10x.crf | Bin 239297 -> 239291 bytes Objects/system_stm32f10x.d | 2 +- Objects/system_stm32f10x.o | Bin 258552 -> 258528 bytes Objects/telecommande.crf | Bin 18 -> 240690 bytes Objects/telecommande.d | 12 + Objects/telecommande.o | Bin 4560 -> 264320 bytes Projet1.uvguix.alejeune | 3645 +++++++++++----------- Projet1.uvoptx | 89 +- Projet1.uvprojx | 20 + Sources/main.c | 53 +- 44 files changed, 2521 insertions(+), 2150 deletions(-) create mode 100644 FileInclude/Batterie.c create mode 100644 FileInclude/Batterie.h create mode 100644 Objects/batterie.crf create mode 100644 Objects/batterie.d create mode 100644 Objects/batterie.o diff --git a/FileInclude/Batterie.c b/FileInclude/Batterie.c new file mode 100644 index 0000000..cf33df4 --- /dev/null +++ b/FileInclude/Batterie.c @@ -0,0 +1,31 @@ +#include "Batterie.h" +#define NULL 0 + + + + +/* Delarations */ +MyGPIO_Struct_TypeDef GPIOC0; /* Les pins sont a remappés */ +int nivBatterie = 0; + +void Init_Batterie (void){ + + /* Configuration des GPIOs */ + GPIOC0.GPIO = GPIOC; + GPIOC0.GPIO_Pin = 0; + GPIOC0.GPIO_Conf = In_Analog; + MyGPIO_Init(&GPIOC0); + + /* On configure l'ADC */ + initADC(10); + startADC(); +} + + +int Get_Batterie (void){ + + nivBatterie = read(); // sur 12 bits + nivBatterie *= 100; + return (nivBatterie / 4095); // pour avoir le niveau sur 100% + +} diff --git a/FileInclude/Batterie.h b/FileInclude/Batterie.h new file mode 100644 index 0000000..4adbf03 --- /dev/null +++ b/FileInclude/Batterie.h @@ -0,0 +1,11 @@ +#ifndef MYBATTERIE_H +#define MYBATTERIE_H +#include "stm32f10x.h" +#include "MyADC.h" +#include "MyTimer.h" +#include "Driver_GPIO.h" + +void Init_Batterie (void); +int Get_Batterie (void); + +#endif diff --git a/FileInclude/MyADC.c b/FileInclude/MyADC.c index 6532fff..76955b8 100644 --- a/FileInclude/MyADC.c +++ b/FileInclude/MyADC.c @@ -21,6 +21,7 @@ void startADC(void) { int read(void) { int value ; + startADC(); // Recuperer le bit de End of conversion while (!(ADC1->SR & (0x01 << 1))); //on veut masquer les 12 bits les plus bas donc on prend le not de 0x0f >> 12 (111000000000) diff --git a/FileInclude/Plateau.c b/FileInclude/Plateau.c index b2ece7e..19a1ea2 100644 --- a/FileInclude/Plateau.c +++ b/FileInclude/Plateau.c @@ -37,10 +37,10 @@ void Init_Plateau (void) { void Set_Direction (char sens) { /* Rotation */ - if (sens == HORRAIRE){ + if (sens == ANTI_HORRAIRE){ MyGPIO_Reset(GPIOA5.GPIO, GPIOA5.GPIO_Pin); // on met à 0 } - else if (sens == ANTI_HORRAIRE) { + else if (sens == HORRAIRE) { MyGPIO_Set(GPIOA5.GPIO, GPIOA5.GPIO_Pin); // on met à 1 } } diff --git a/FileInclude/Plateau.h b/FileInclude/Plateau.h index 94cbceb..9ef064a 100644 --- a/FileInclude/Plateau.h +++ b/FileInclude/Plateau.h @@ -8,6 +8,6 @@ void Init_Plateau (void); void Set_Direction (char sens); void Set_Vitesse (char vitesse); -void Set_Moteur_Plateau(char sens, char vitesse); // -1 gauche et 1 droite +void Set_Moteur_Plateau(char sens, char vitesse); #endif diff --git a/FileInclude/Telecommande.c b/FileInclude/Telecommande.c index d66f23b..0bf148e 100644 --- a/FileInclude/Telecommande.c +++ b/FileInclude/Telecommande.c @@ -3,4 +3,83 @@ #include "Driver_GPIO.h" #include "Plateau.h" #include "Telecommande.h" +#define NULL 0 + +/* Declaration */ +USART_TypeDef USART ; +USART_TypeDef * Usart = &USART; +MyGPIO_Struct_TypeDef GPIOA10; // pin rx = reception +MyGPIO_Struct_TypeDef GPIOA9; // pin tx = envoie +void (* ptr) (char) = NULL; + +/* Configuration de l'UART */ +void Init_USART (USART_TypeDef * USART){ + + /* Configuration des GPIOs */ + GPIOA10.GPIO = GPIOA; + GPIOA10.GPIO_Pin = 10; + GPIOA10.GPIO_Conf = In_Floating; + MyGPIO_Init(&GPIOA10); + + GPIOA9.GPIO = GPIOA; + GPIOA9.GPIO_Pin = 9; + GPIOA9.GPIO_Conf = AltOut_Ppull; + MyGPIO_Init(&GPIOA9); + + /* Configuration de l'USART */ + RCC->APB2ENR |= RCC_APB2ENR_USART1EN ; // activation de la clock + USART1->CR1 |= USART_CR1_UE ; // rendre usart enable + USART1->CR1 &= ~(USART_CR1_M); // mettre à 8 la longueur du mot + + // bd 9600 (cf. prof) puis calcul de la mantisse et de la fraction (cf. p 804) + USART1->BRR |= 0x0C; // mantisse + USART1->BRR |= (0x01D4 << 4) ; // fraction + + // Active la reception et l'emission + USART1->CR1 |= USART_CR1_RE; + USART1->CR1 |= USART_CR1_TE; + + /* On active les interruptions pour l'usart1 */ + USART1->CR1 |= USART_CR1_RXNEIE; +} + +/* Envoie d'un character */ +void Send_Char (char c) { + while (((USART1->SR >> 6) & 0x1) == 0);// tant que la transmission n'est pas finie + USART1->DR = c; +} + +/* Envoie de messages */ +void Send_Message (char message[]){ + int i = 0; + while (message[i] != '\0') { + Send_Char(message[i]); + i+=1; + } +} + + + +void USART1_IRQHandler() { + char input; + input = USART1->DR ; // on récupère ce qu'il y a dans le registre + (*ptr) (input); // on execute la fonction +} + +/* Reception de message */ +void Init_Message_Reception(void (* pFonction) (char)){ //(void (* pFonction) (char)){ + + /* Configuration de l'interruption */ + //!\\ A revoir cette partie ! p 198 + NVIC->ISER[1] |= NVIC_ISER_SETENA_5 ;//NVIC_IABR_ACTIVE_5 ; // on autorise l'interuption au niveau du coeur par le usart1 + NVIC->IP[37] = 7; // on parametre la prio de l'usart + + /* Activation de la réception */ + USART1->CR1 |= USART_CR1_RE ; + ptr = pFonction; //fonction à appeler par le handler + + +} + + diff --git a/FileInclude/Telecommande.h b/FileInclude/Telecommande.h index 030bc72..675cbdf 100644 --- a/FileInclude/Telecommande.h +++ b/FileInclude/Telecommande.h @@ -2,19 +2,15 @@ #define MYTELCOMMANDE_H #include "stm32f10x.h" -/* Configuration de l'UART */ -void Init_UART (USART_TypeDef * UART); +/* Configuration de l'USART */ +void Init_USART (USART_TypeDef * USART); /* Envoie de messages */ void Send_Message (char message[]); /* Reception de message */ -void Receive_Message (void (* pFonction) (char)); + +void Init_Message_Reception(void (* pFonction) (char)); //pFonction traitera le message - - - - - #endif diff --git a/Listings/Projet1_Simulation.map b/Listings/Projet1_Simulation.map index 5285229..f6c4d0b 100644 --- a/Listings/Projet1_Simulation.map +++ b/Listings/Projet1_Simulation.map @@ -4,13 +4,20 @@ Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601] Section Cross References - main.o(i.main) refers to plateau.o(i.Set_Moteur_Plateau) for Set_Moteur_Plateau + main.o(i.f) refers to plateau.o(i.Set_Moteur_Plateau) for Set_Moteur_Plateau + main.o(i.f) refers to main.o(.data) for droite + main.o(i.main) refers to telecommande.o(i.Init_USART) for Init_USART + main.o(i.main) refers to batterie.o(i.Init_Batterie) for Init_Batterie + main.o(i.main) refers to batterie.o(i.Get_Batterie) for Get_Batterie + main.o(i.main) refers to telecommande.o(i.Send_Message) for Send_Message + main.o(i.main) refers to main.o(.data) for bat mytimer.o(i.MyTimer_ActiveIT) refers to mytimer.o(.data) for ptr1 mytimer.o(i.MyTimer_PWM) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(.data) for ptr1 mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(.data) for ptr2 mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(.data) for ptr3 mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(.data) for ptr4 + myadc.o(i.read) refers to myadc.o(i.startADC) for startADC plateau.o(i.Init_Plateau) refers to mytimer.o(i.MyTimer_Base_Init) for MyTimer_Base_Init plateau.o(i.Init_Plateau) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init plateau.o(i.Init_Plateau) refers to mytimer.o(i.MyTimer_Base_Start) for MyTimer_Base_Start @@ -25,12 +32,25 @@ Section Cross References plateau.o(i.Set_Moteur_Plateau) refers to plateau.o(i.Set_Vitesse) for Set_Vitesse plateau.o(i.Set_Vitesse) refers to mytimer.o(i.Set_PWM_PRCT) for Set_PWM_PRCT plateau.o(i.Set_Vitesse) refers to plateau.o(.data) for Data + telecommande.o(i.Init_Message_Reception) refers to telecommande.o(.data) for ptr + telecommande.o(i.Init_USART) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init + telecommande.o(i.Init_USART) refers to telecommande.o(.bss) for GPIOA10 + telecommande.o(i.Send_Message) refers to telecommande.o(i.Send_Char) for Send_Char + telecommande.o(i.USART1_IRQHandler) refers to telecommande.o(.data) for ptr + telecommande.o(.data) refers to telecommande.o(.bss) for USART + batterie.o(i.Get_Batterie) refers to myadc.o(i.read) for read + batterie.o(i.Get_Batterie) refers to batterie.o(.data) for nivBatterie + batterie.o(i.Init_Batterie) refers to driver_gpio.o(i.MyGPIO_Init) for MyGPIO_Init + batterie.o(i.Init_Batterie) refers to myadc.o(i.initADC) for initADC + batterie.o(i.Init_Batterie) refers to myadc.o(i.startADC) for startADC + batterie.o(i.Init_Batterie) refers to batterie.o(.bss) for GPIOC0 startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler startup_stm32f10x_md.o(RESET) refers to mytimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler + startup_stm32f10x_md.o(RESET) refers to telecommande.o(i.USART1_IRQHandler) for USART1_IRQHandler startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit startup_stm32f10x_md.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72 @@ -61,27 +81,44 @@ Removing Unused input sections from the image. Removing main.o(.rev16_text), (4 bytes). Removing main.o(.revsh_text), (4 bytes). Removing main.o(.rrx_text), (6 bytes). + Removing main.o(i.f), (64 bytes). Removing driver_gpio.o(.rev16_text), (4 bytes). Removing driver_gpio.o(.revsh_text), (4 bytes). Removing driver_gpio.o(.rrx_text), (6 bytes). Removing driver_gpio.o(i.MyGPIO_Read), (12 bytes). + Removing driver_gpio.o(i.MyGPIO_Reset), (14 bytes). + Removing driver_gpio.o(i.MyGPIO_Set), (12 bytes). Removing driver_gpio.o(i.MyGPIO_Toggle), (12 bytes). Removing mytimer.o(.rev16_text), (4 bytes). Removing mytimer.o(.revsh_text), (4 bytes). Removing mytimer.o(.rrx_text), (6 bytes). Removing mytimer.o(i.Get_Max_Duty), (6 bytes). Removing mytimer.o(i.MyTimer_ActiveIT), (176 bytes). + Removing mytimer.o(i.MyTimer_Base_Init), (108 bytes). + Removing mytimer.o(i.MyTimer_Base_Start), (10 bytes). Removing mytimer.o(i.MyTimer_Base_Stop), (10 bytes). + Removing mytimer.o(i.MyTimer_PWM), (464 bytes). Removing mytimer.o(i.Set_Duty_Cycle), (40 bytes). + Removing mytimer.o(i.Set_PWM_PRCT), (56 bytes). Removing myadc.o(.rev16_text), (4 bytes). Removing myadc.o(.revsh_text), (4 bytes). Removing myadc.o(.rrx_text), (6 bytes). - Removing myadc.o(i.initADC), (60 bytes). - Removing myadc.o(i.read), (32 bytes). - Removing myadc.o(i.startADC), (20 bytes). Removing plateau.o(.rev16_text), (4 bytes). Removing plateau.o(.revsh_text), (4 bytes). Removing plateau.o(.rrx_text), (6 bytes). + Removing plateau.o(i.Init_Plateau), (124 bytes). + Removing plateau.o(i.Set_Direction), (40 bytes). + Removing plateau.o(i.Set_Moteur_Plateau), (24 bytes). + Removing plateau.o(i.Set_Vitesse), (32 bytes). + Removing plateau.o(.bss), (24 bytes). + Removing plateau.o(.data), (16 bytes). + Removing telecommande.o(.rev16_text), (4 bytes). + Removing telecommande.o(.revsh_text), (4 bytes). + Removing telecommande.o(.rrx_text), (6 bytes). + Removing telecommande.o(i.Init_Message_Reception), (56 bytes). + Removing batterie.o(.rev16_text), (4 bytes). + Removing batterie.o(.revsh_text), (4 bytes). + Removing batterie.o(.rrx_text), (6 bytes). Removing startup_stm32f10x_md.o(HEAP), (512 bytes). Removing system_stm32f10x.o(.rev16_text), (4 bytes). Removing system_stm32f10x.o(.revsh_text), (4 bytes). @@ -89,7 +126,7 @@ Removing Unused input sections from the image. Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes). Removing system_stm32f10x.o(.data), (20 bytes). -30 unused section(s) (total 1148 bytes) removed from the image. +47 unused section(s) (total 2108 bytes) removed from the image. ============================================================================== @@ -99,28 +136,31 @@ Image Symbol Table Symbol Name Value Ov Type Size Object(Section) - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + FileInclude\Batterie.c 0x00000000 Number 0 batterie.o ABSOLUTE FileInclude\MyADC.c 0x00000000 Number 0 myadc.o ABSOLUTE FileInclude\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE FileInclude\Plateau.c 0x00000000 Number 0 plateau.o ABSOLUTE FileInclude\Telecommande.c 0x00000000 Number 0 telecommande.o ABSOLUTE + FileInclude\\Batterie.c 0x00000000 Number 0 batterie.o ABSOLUTE FileInclude\\MyADC.c 0x00000000 Number 0 myadc.o ABSOLUTE FileInclude\\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE FileInclude\\Plateau.c 0x00000000 Number 0 plateau.o ABSOLUTE + FileInclude\\Telecommande.c 0x00000000 Number 0 telecommande.o ABSOLUTE RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE @@ -145,34 +185,36 @@ Image Symbol Table __lit__00000000 0x08000100 Data 4 entry2.o(.ARM.Collect$$$$00002712) .text 0x08000104 Section 36 startup_stm32f10x_md.o(.text) .text 0x08000128 Section 36 init.o(.text) - i.Init_Plateau 0x0800014c Section 0 plateau.o(i.Init_Plateau) - i.MyGPIO_Init 0x080001c8 Section 0 driver_gpio.o(i.MyGPIO_Init) - i.MyGPIO_Reset 0x0800027c Section 0 driver_gpio.o(i.MyGPIO_Reset) - i.MyGPIO_Set 0x0800028a Section 0 driver_gpio.o(i.MyGPIO_Set) - i.MyTimer_Base_Init 0x08000298 Section 0 mytimer.o(i.MyTimer_Base_Init) - i.MyTimer_Base_Start 0x08000304 Section 0 mytimer.o(i.MyTimer_Base_Start) - i.MyTimer_PWM 0x08000310 Section 0 mytimer.o(i.MyTimer_PWM) - i.SetSysClock 0x080004e0 Section 0 system_stm32f10x.o(i.SetSysClock) - SetSysClock 0x080004e1 Thumb Code 8 system_stm32f10x.o(i.SetSysClock) - i.SetSysClockTo72 0x080004e8 Section 0 system_stm32f10x.o(i.SetSysClockTo72) - SetSysClockTo72 0x080004e9 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72) - i.Set_Direction 0x080005c8 Section 0 plateau.o(i.Set_Direction) - i.Set_Moteur_Plateau 0x080005f0 Section 0 plateau.o(i.Set_Moteur_Plateau) - i.Set_PWM_PRCT 0x08000608 Section 0 mytimer.o(i.Set_PWM_PRCT) - i.Set_Vitesse 0x08000640 Section 0 plateau.o(i.Set_Vitesse) - i.SystemInit 0x08000660 Section 0 system_stm32f10x.o(i.SystemInit) - i.TIM1_UP_IRQHandler 0x080006c0 Section 0 mytimer.o(i.TIM1_UP_IRQHandler) - i.TIM2_IRQHandler 0x080006e4 Section 0 mytimer.o(i.TIM2_IRQHandler) - i.TIM3_IRQHandler 0x08000708 Section 0 mytimer.o(i.TIM3_IRQHandler) - i.TIM4_IRQHandler 0x0800072c Section 0 mytimer.o(i.TIM4_IRQHandler) - i.__scatterload_copy 0x08000750 Section 14 handlers.o(i.__scatterload_copy) - i.__scatterload_null 0x0800075e Section 2 handlers.o(i.__scatterload_null) - i.__scatterload_zeroinit 0x08000760 Section 14 handlers.o(i.__scatterload_zeroinit) - i.main 0x0800076e Section 0 main.o(i.main) - .data 0x20000000 Section 16 mytimer.o(.data) - .data 0x20000010 Section 16 plateau.o(.data) - .bss 0x20000020 Section 24 plateau.o(.bss) - STACK 0x20000038 Section 1024 startup_stm32f10x_md.o(STACK) + i.Get_Batterie 0x0800014c Section 0 batterie.o(i.Get_Batterie) + i.Init_Batterie 0x08000174 Section 0 batterie.o(i.Init_Batterie) + i.Init_USART 0x0800019c Section 0 telecommande.o(i.Init_USART) + i.MyGPIO_Init 0x08000238 Section 0 driver_gpio.o(i.MyGPIO_Init) + i.Send_Char 0x080002ec Section 0 telecommande.o(i.Send_Char) + i.Send_Message 0x08000308 Section 0 telecommande.o(i.Send_Message) + i.SetSysClock 0x08000320 Section 0 system_stm32f10x.o(i.SetSysClock) + SetSysClock 0x08000321 Thumb Code 8 system_stm32f10x.o(i.SetSysClock) + i.SetSysClockTo72 0x08000328 Section 0 system_stm32f10x.o(i.SetSysClockTo72) + SetSysClockTo72 0x08000329 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72) + i.SystemInit 0x08000408 Section 0 system_stm32f10x.o(i.SystemInit) + i.TIM1_UP_IRQHandler 0x08000468 Section 0 mytimer.o(i.TIM1_UP_IRQHandler) + i.TIM2_IRQHandler 0x0800048c Section 0 mytimer.o(i.TIM2_IRQHandler) + i.TIM3_IRQHandler 0x080004b0 Section 0 mytimer.o(i.TIM3_IRQHandler) + i.TIM4_IRQHandler 0x080004d4 Section 0 mytimer.o(i.TIM4_IRQHandler) + i.USART1_IRQHandler 0x080004f8 Section 0 telecommande.o(i.USART1_IRQHandler) + i.__scatterload_copy 0x08000514 Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x08000522 Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x08000524 Section 14 handlers.o(i.__scatterload_zeroinit) + i.initADC 0x08000534 Section 0 myadc.o(i.initADC) + i.main 0x08000570 Section 0 main.o(i.main) + i.read 0x0800060c Section 0 myadc.o(i.read) + i.startADC 0x08000634 Section 0 myadc.o(i.startADC) + .data 0x20000000 Section 16 main.o(.data) + .data 0x20000010 Section 16 mytimer.o(.data) + .data 0x20000020 Section 8 telecommande.o(.data) + .data 0x20000028 Section 4 batterie.o(.data) + .bss 0x2000002c Section 52 telecommande.o(.bss) + .bss 0x20000060 Section 12 batterie.o(.bss) + STACK 0x20000070 Section 1024 startup_stm32f10x_md.o(STACK) Global Symbols @@ -241,7 +283,6 @@ Image Symbol Table TIM1_BRK_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) TIM1_CC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) TIM1_TRG_COM_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USART1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) USART2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) USART3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) USBWakeUp_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) @@ -250,38 +291,43 @@ Image Symbol Table WWDG_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) __scatterload 0x08000129 Thumb Code 28 init.o(.text) __scatterload_rt2 0x08000129 Thumb Code 0 init.o(.text) - Init_Plateau 0x0800014d Thumb Code 98 plateau.o(i.Init_Plateau) - MyGPIO_Init 0x080001c9 Thumb Code 166 driver_gpio.o(i.MyGPIO_Init) - MyGPIO_Reset 0x0800027d Thumb Code 14 driver_gpio.o(i.MyGPIO_Reset) - MyGPIO_Set 0x0800028b Thumb Code 12 driver_gpio.o(i.MyGPIO_Set) - MyTimer_Base_Init 0x08000299 Thumb Code 98 mytimer.o(i.MyTimer_Base_Init) - MyTimer_Base_Start 0x08000305 Thumb Code 10 mytimer.o(i.MyTimer_Base_Start) - MyTimer_PWM 0x08000311 Thumb Code 448 mytimer.o(i.MyTimer_PWM) - Set_Direction 0x080005c9 Thumb Code 34 plateau.o(i.Set_Direction) - Set_Moteur_Plateau 0x080005f1 Thumb Code 24 plateau.o(i.Set_Moteur_Plateau) - Set_PWM_PRCT 0x08000609 Thumb Code 56 mytimer.o(i.Set_PWM_PRCT) - Set_Vitesse 0x08000641 Thumb Code 22 plateau.o(i.Set_Vitesse) - SystemInit 0x08000661 Thumb Code 78 system_stm32f10x.o(i.SystemInit) - TIM1_UP_IRQHandler 0x080006c1 Thumb Code 28 mytimer.o(i.TIM1_UP_IRQHandler) - TIM2_IRQHandler 0x080006e5 Thumb Code 32 mytimer.o(i.TIM2_IRQHandler) - TIM3_IRQHandler 0x08000709 Thumb Code 28 mytimer.o(i.TIM3_IRQHandler) - TIM4_IRQHandler 0x0800072d Thumb Code 28 mytimer.o(i.TIM4_IRQHandler) - __scatterload_copy 0x08000751 Thumb Code 14 handlers.o(i.__scatterload_copy) - __scatterload_null 0x0800075f Thumb Code 2 handlers.o(i.__scatterload_null) - __scatterload_zeroinit 0x08000761 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) - main 0x0800076f Thumb Code 12 main.o(i.main) - Region$$Table$$Base 0x0800077c Number 0 anon$$obj.o(Region$$Table) - Region$$Table$$Limit 0x0800079c Number 0 anon$$obj.o(Region$$Table) - ptr1 0x20000000 Data 4 mytimer.o(.data) - ptr2 0x20000004 Data 4 mytimer.o(.data) - ptr3 0x20000008 Data 4 mytimer.o(.data) - ptr4 0x2000000c Data 4 mytimer.o(.data) - channel 0x20000010 Data 1 plateau.o(.data) - TIM 0x20000014 Data 8 plateau.o(.data) - Data 0x2000001c Data 4 plateau.o(.data) - GPIOA5 0x20000020 Data 12 plateau.o(.bss) - GPIOA6 0x2000002c Data 12 plateau.o(.bss) - __initial_sp 0x20000438 Data 0 startup_stm32f10x_md.o(STACK) + Get_Batterie 0x0800014d Thumb Code 36 batterie.o(i.Get_Batterie) + Init_Batterie 0x08000175 Thumb Code 32 batterie.o(i.Init_Batterie) + Init_USART 0x0800019d Thumb Code 134 telecommande.o(i.Init_USART) + MyGPIO_Init 0x08000239 Thumb Code 166 driver_gpio.o(i.MyGPIO_Init) + Send_Char 0x080002ed Thumb Code 22 telecommande.o(i.Send_Char) + Send_Message 0x08000309 Thumb Code 24 telecommande.o(i.Send_Message) + SystemInit 0x08000409 Thumb Code 78 system_stm32f10x.o(i.SystemInit) + TIM1_UP_IRQHandler 0x08000469 Thumb Code 28 mytimer.o(i.TIM1_UP_IRQHandler) + TIM2_IRQHandler 0x0800048d Thumb Code 32 mytimer.o(i.TIM2_IRQHandler) + TIM3_IRQHandler 0x080004b1 Thumb Code 28 mytimer.o(i.TIM3_IRQHandler) + TIM4_IRQHandler 0x080004d5 Thumb Code 28 mytimer.o(i.TIM4_IRQHandler) + USART1_IRQHandler 0x080004f9 Thumb Code 18 telecommande.o(i.USART1_IRQHandler) + __scatterload_copy 0x08000515 Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x08000523 Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x08000525 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + initADC 0x08000535 Thumb Code 50 myadc.o(i.initADC) + main 0x08000571 Thumb Code 92 main.o(i.main) + read 0x0800060d Thumb Code 34 myadc.o(i.read) + startADC 0x08000635 Thumb Code 14 myadc.o(i.startADC) + Region$$Table$$Base 0x08000648 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08000668 Number 0 anon$$obj.o(Region$$Table) + droite 0x20000000 Data 4 main.o(.data) + b 0x20000004 Data 4 main.o(.data) + testBatterie 0x20000008 Data 4 main.o(.data) + bat 0x2000000c Data 4 main.o(.data) + ptr1 0x20000010 Data 4 mytimer.o(.data) + ptr2 0x20000014 Data 4 mytimer.o(.data) + ptr3 0x20000018 Data 4 mytimer.o(.data) + ptr4 0x2000001c Data 4 mytimer.o(.data) + Usart 0x20000020 Data 4 telecommande.o(.data) + ptr 0x20000024 Data 4 telecommande.o(.data) + nivBatterie 0x20000028 Data 4 batterie.o(.data) + USART 0x2000002c Data 28 telecommande.o(.bss) + GPIOA10 0x20000048 Data 12 telecommande.o(.bss) + GPIOA9 0x20000054 Data 12 telecommande.o(.bss) + GPIOC0 0x20000060 Data 12 batterie.o(.bss) + __initial_sp 0x20000470 Data 0 startup_stm32f10x_md.o(STACK) @@ -289,69 +335,64 @@ Image Symbol Table Memory Map of the image - Image Entry point : 0x08000105 + Image Entry point : 0x080000ed - Load Region LR_1 (Base: 0x08000000, Size: 0x000007bc, Max: 0xffffffff, ABSOLUTE) + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00000694, Max: 0x00020000, ABSOLUTE) - Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000079c, Max: 0xffffffff, ABSOLUTE) + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000668, Max: 0x00020000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object - 0x08000000 0x08000000 0x000000ec Data RO 309 RESET startup_stm32f10x_md.o - 0x080000ec 0x080000ec 0x00000000 Code RO 360 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) - 0x080000ec 0x080000ec 0x00000004 Code RO 363 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) - 0x080000f0 0x080000f0 0x00000004 Code RO 366 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) - 0x080000f4 0x080000f4 0x00000000 Code RO 368 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) - 0x080000f4 0x080000f4 0x00000000 Code RO 370 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) - 0x080000f4 0x080000f4 0x00000008 Code RO 371 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) - 0x080000fc 0x080000fc 0x00000004 Code RO 378 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o) - 0x08000100 0x08000100 0x00000000 Code RO 373 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o) - 0x08000100 0x08000100 0x00000000 Code RO 375 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o) - 0x08000100 0x08000100 0x00000004 Code RO 364 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) - 0x08000104 0x08000104 0x00000024 Code RO 310 * .text startup_stm32f10x_md.o - 0x08000128 0x08000128 0x00000024 Code RO 379 .text mc_w.l(init.o) - 0x0800014c 0x0800014c 0x0000007c Code RO 258 i.Init_Plateau plateau.o - 0x080001c8 0x080001c8 0x000000b4 Code RO 69 i.MyGPIO_Init driver_gpio.o - 0x0800027c 0x0800027c 0x0000000e Code RO 71 i.MyGPIO_Reset driver_gpio.o - 0x0800028a 0x0800028a 0x0000000c Code RO 72 i.MyGPIO_Set driver_gpio.o - 0x08000296 0x08000296 0x00000002 PAD - 0x08000298 0x08000298 0x0000006c Code RO 122 i.MyTimer_Base_Init mytimer.o - 0x08000304 0x08000304 0x0000000a Code RO 123 i.MyTimer_Base_Start mytimer.o - 0x0800030e 0x0800030e 0x00000002 PAD - 0x08000310 0x08000310 0x000001d0 Code RO 125 i.MyTimer_PWM mytimer.o - 0x080004e0 0x080004e0 0x00000008 Code RO 317 i.SetSysClock system_stm32f10x.o - 0x080004e8 0x080004e8 0x000000e0 Code RO 318 i.SetSysClockTo72 system_stm32f10x.o - 0x080005c8 0x080005c8 0x00000028 Code RO 259 i.Set_Direction plateau.o - 0x080005f0 0x080005f0 0x00000018 Code RO 260 i.Set_Moteur_Plateau plateau.o - 0x08000608 0x08000608 0x00000038 Code RO 127 i.Set_PWM_PRCT mytimer.o - 0x08000640 0x08000640 0x00000020 Code RO 261 i.Set_Vitesse plateau.o - 0x08000660 0x08000660 0x00000060 Code RO 320 i.SystemInit system_stm32f10x.o - 0x080006c0 0x080006c0 0x00000024 Code RO 128 i.TIM1_UP_IRQHandler mytimer.o - 0x080006e4 0x080006e4 0x00000024 Code RO 129 i.TIM2_IRQHandler mytimer.o - 0x08000708 0x08000708 0x00000024 Code RO 130 i.TIM3_IRQHandler mytimer.o - 0x0800072c 0x0800072c 0x00000024 Code RO 131 i.TIM4_IRQHandler mytimer.o - 0x08000750 0x08000750 0x0000000e Code RO 383 i.__scatterload_copy mc_w.l(handlers.o) - 0x0800075e 0x0800075e 0x00000002 Code RO 384 i.__scatterload_null mc_w.l(handlers.o) - 0x08000760 0x08000760 0x0000000e Code RO 385 i.__scatterload_zeroinit mc_w.l(handlers.o) - 0x0800076e 0x0800076e 0x0000000c Code RO 4 i.main main.o - 0x0800077a 0x0800077a 0x00000002 PAD - 0x0800077c 0x0800077c 0x00000020 Data RO 381 Region$$Table anon$$obj.o + 0x08000000 0x08000000 0x000000ec Data RO 413 RESET startup_stm32f10x_md.o + 0x080000ec 0x080000ec 0x00000000 Code RO 464 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x080000ec 0x080000ec 0x00000004 Code RO 467 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x080000f0 0x080000f0 0x00000004 Code RO 470 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x080000f4 0x080000f4 0x00000000 Code RO 472 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x080000f4 0x080000f4 0x00000000 Code RO 474 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x080000f4 0x080000f4 0x00000008 Code RO 475 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x080000fc 0x080000fc 0x00000004 Code RO 482 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o) + 0x08000100 0x08000100 0x00000000 Code RO 477 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o) + 0x08000100 0x08000100 0x00000000 Code RO 479 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o) + 0x08000100 0x08000100 0x00000004 Code RO 468 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x08000104 0x08000104 0x00000024 Code RO 414 .text startup_stm32f10x_md.o + 0x08000128 0x08000128 0x00000024 Code RO 483 .text mc_w.l(init.o) + 0x0800014c 0x0800014c 0x00000028 Code RO 377 i.Get_Batterie batterie.o + 0x08000174 0x08000174 0x00000028 Code RO 378 i.Init_Batterie batterie.o + 0x0800019c 0x0800019c 0x0000009c Code RO 323 i.Init_USART telecommande.o + 0x08000238 0x08000238 0x000000b4 Code RO 84 i.MyGPIO_Init driver_gpio.o + 0x080002ec 0x080002ec 0x0000001c Code RO 324 i.Send_Char telecommande.o + 0x08000308 0x08000308 0x00000018 Code RO 325 i.Send_Message telecommande.o + 0x08000320 0x08000320 0x00000008 Code RO 421 i.SetSysClock system_stm32f10x.o + 0x08000328 0x08000328 0x000000e0 Code RO 422 i.SetSysClockTo72 system_stm32f10x.o + 0x08000408 0x08000408 0x00000060 Code RO 424 i.SystemInit system_stm32f10x.o + 0x08000468 0x08000468 0x00000024 Code RO 143 i.TIM1_UP_IRQHandler mytimer.o + 0x0800048c 0x0800048c 0x00000024 Code RO 144 i.TIM2_IRQHandler mytimer.o + 0x080004b0 0x080004b0 0x00000024 Code RO 145 i.TIM3_IRQHandler mytimer.o + 0x080004d4 0x080004d4 0x00000024 Code RO 146 i.TIM4_IRQHandler mytimer.o + 0x080004f8 0x080004f8 0x0000001c Code RO 326 i.USART1_IRQHandler telecommande.o + 0x08000514 0x08000514 0x0000000e Code RO 487 i.__scatterload_copy mc_w.l(handlers.o) + 0x08000522 0x08000522 0x00000002 Code RO 488 i.__scatterload_null mc_w.l(handlers.o) + 0x08000524 0x08000524 0x0000000e Code RO 489 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x08000532 0x08000532 0x00000002 PAD + 0x08000534 0x08000534 0x0000003c Code RO 234 i.initADC myadc.o + 0x08000570 0x08000570 0x0000009c Code RO 5 i.main main.o + 0x0800060c 0x0800060c 0x00000028 Code RO 235 i.read myadc.o + 0x08000634 0x08000634 0x00000014 Code RO 236 i.startADC myadc.o + 0x08000648 0x08000648 0x00000020 Data RO 485 Region$$Table anon$$obj.o - Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x0800079c, Size: 0x00000020, Max: 0xffffffff, ABSOLUTE) + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08000668, Size: 0x00000470, Max: 0x00005000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object - 0x20000000 0x0800079c 0x00000010 Data RW 132 .data mytimer.o - 0x20000010 0x080007ac 0x00000010 Data RW 263 .data plateau.o - - - Execution Region ER_ZI (Exec base: 0x20000020, Load base: 0x080007bc, Size: 0x00000418, Max: 0xffffffff, ABSOLUTE) - - Exec Addr Load Addr Size Type Attr Idx E Section Name Object - - 0x20000020 - 0x00000018 Zero RW 262 .bss plateau.o - 0x20000038 - 0x00000400 Zero RW 307 STACK startup_stm32f10x_md.o + 0x20000000 0x08000668 0x00000010 Data RW 6 .data main.o + 0x20000010 0x08000678 0x00000010 Data RW 147 .data mytimer.o + 0x20000020 0x08000688 0x00000008 Data RW 328 .data telecommande.o + 0x20000028 0x08000690 0x00000004 Data RW 380 .data batterie.o + 0x2000002c - 0x00000034 Zero RW 327 .bss telecommande.o + 0x20000060 - 0x0000000c Zero RW 379 .bss batterie.o + 0x2000006c 0x08000694 0x00000004 PAD + 0x20000070 - 0x00000400 Zero RW 411 STACK startup_stm32f10x_md.o ============================================================================== @@ -361,17 +402,19 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug Object Name - 206 14 0 0 0 2722 driver_gpio.o - 12 0 0 0 0 206767 main.o - 782 54 0 16 0 6027 mytimer.o - 220 42 0 16 24 2755 plateau.o + 80 12 0 4 12 1168 batterie.o + 180 14 0 0 0 1658 driver_gpio.o + 156 64 0 16 0 207163 main.o + 120 22 0 0 0 1308 myadc.o + 144 28 0 16 0 3521 mytimer.o 36 8 236 0 1024 808 startup_stm32f10x_md.o 328 28 0 0 0 1973 system_stm32f10x.o + 236 38 0 8 52 2809 telecommande.o ---------------------------------------------------------------------- - 1590 146 268 32 1048 221052 Object Totals + 1280 214 268 44 1092 220408 Object Totals 0 0 32 0 0 0 (incl. Generated) - 6 0 0 0 0 0 (incl. Padding) + 0 0 0 0 4 0 (incl. Padding) ---------------------------------------------------------------------- @@ -390,8 +433,8 @@ Image component sizes 36 8 0 0 0 68 init.o ---------------------------------------------------------------------- - 90 16 0 0 0 68 Library Totals - 0 0 0 0 0 0 (incl. Padding) + 92 16 0 0 0 68 Library Totals + 2 0 0 0 0 0 (incl. Padding) ---------------------------------------------------------------------- @@ -400,7 +443,7 @@ Image component sizes 90 16 0 0 0 68 mc_w.l ---------------------------------------------------------------------- - 90 16 0 0 0 68 Library Totals + 92 16 0 0 0 68 Library Totals ---------------------------------------------------------------------- @@ -409,15 +452,15 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug - 1680 162 268 32 1048 220388 Grand Totals - 1680 162 268 32 1048 220388 ELF Image Totals - 1680 162 268 32 0 0 ROM Totals + 1372 230 268 44 1092 219848 Grand Totals + 1372 230 268 44 1092 219848 ELF Image Totals + 1372 230 268 44 0 0 ROM Totals ============================================================================== - Total RO Size (Code + RO Data) 1948 ( 1.90kB) - Total RW Size (RW Data + ZI Data) 1080 ( 1.05kB) - Total ROM Size (Code + RO Data + RW Data) 1980 ( 1.93kB) + Total RO Size (Code + RO Data) 1640 ( 1.60kB) + Total RW Size (RW Data + ZI Data) 1136 ( 1.11kB) + Total ROM Size (Code + RO Data + RW Data) 1684 ( 1.64kB) ============================================================================== diff --git a/Listings/startup_stm32f10x_md.lst b/Listings/startup_stm32f10x_md.lst index 37414f5..45d2bb2 100644 --- a/Listings/startup_stm32f10x_md.lst +++ b/Listings/startup_stm32f10x_md.lst @@ -465,12 +465,12 @@ ARM Macro Assembler Page 8 00000000 Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md. -o -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Pack -s\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32 -F1xx_DFP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROL -IB SETA 1" --predefine="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" ---predefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --list=.\listings\ -startup_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32f10x_md.s +o -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\ +CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_D +FP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB SET +A 1" --predefine="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" --pred +efine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --list=.\listings\startu +p_stm32f10x_md.lst RTE\Device\STM32F103RB\startup_stm32f10x_md.s diff --git a/Objects/Projet1_Réel.dep b/Objects/Projet1_Réel.dep index d5b327d..c0af0f8 100644 --- a/Objects/Projet1_Réel.dep +++ b/Objects/Projet1_Réel.dep @@ -1,43 +1,101 @@ Dependencies for Project 'Projet1', Target 'Réel': (DO NOT MODIFY !) CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC -F (.\Sources\prinicpal.c)(0x6340254D)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\prinicpal.o --omf_browse .\objects\prinicpal.crf --depend .\objects\prinicpal.d) +F (.\Sources\main.c)(0x6372704A)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_R_el\RTE_Components.h)(0x63285003) +I (.\RTE\_R_el\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -I (.\FileInclude\Driver_GPIO.h)(0x63315001) -I (.\FileInclude\MyTimer.h)(0x6340244A) +I (.\FileInclude\Driver_GPIO.h)(0x6352AB58) +I (.\FileInclude\MyTimer.h)(0x6352B8A4) +I (.\FileInclude\MyADC.h)(0x6352AB58) +I (.\FileInclude\Plateau.h)(0x63725F44) +I (.\FileInclude\Telecommande.h)(0x6368CE08) +I (.\FileInclude\Batterie.h)(0x63712E97) F (U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c)(0x633153E6)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d) I (U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.h)(0x63315001) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_R_el\RTE_Components.h)(0x63285003) +I (.\RTE\_R_el\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -F (.\FileInclude\MyTimer.c)(0x63402350)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d) -I (FileInclude\MyTimer.h)(0x6340244A) +F (.\FileInclude\MyTimer.c)(0x635EAD7F)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d) +I (FileInclude\MyTimer.h)(0x6352B8A4) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_R_el\RTE_Components.h)(0x63285003) +I (.\RTE\_R_el\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -I (FileInclude\Driver_GPIO.h)(0x63315001) -F (.\FileInclude\MyTimer.h)(0x6340244A)() -F (RTE\Device\STM32F103RB\RTE_Device.h)(0x59283406)() -F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58258CCC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d) -F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58258CCC)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +F (.\FileInclude\MyTimer.h)(0x6352B8A4)() +F (.\FileInclude\MyADC.c)(0x63726E79)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\myadc.o --omf_browse .\objects\myadc.crf --depend .\objects\myadc.d) +I (FileInclude\MyADC.h)(0x6352AB58) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_R_el\RTE_Components.h)(0x63285003) +I (.\RTE\_R_el\RTE_Components.h)(0x6352AB59) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) +I (FileInclude\MyTimer.h)(0x6352B8A4) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +F (.\FileInclude\MyADC.h)(0x6352AB58)() +F (.\FileInclude\Plateau.c)(0x635BB6D1)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\plateau.o --omf_browse .\objects\plateau.crf --depend .\objects\plateau.d) +I (FileInclude\MyTimer.h)(0x6352B8A4) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) +I (.\RTE\_R_el\RTE_Components.h)(0x6352AB59) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +I (FileInclude\Plateau.h)(0x63725F44) +F (.\FileInclude\Telecommande.c)(0x6368E779)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\telecommande.o --omf_browse .\objects\telecommande.crf --depend .\objects\telecommande.d) +I (FileInclude\MyTimer.h)(0x6352B8A4) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) +I (.\RTE\_R_el\RTE_Components.h)(0x6352AB59) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +I (FileInclude\Plateau.h)(0x63725F44) +I (FileInclude\Telecommande.h)(0x6368CE08) +F (.\FileInclude\Plateau.h)(0x63725F44)() +F (.\FileInclude\Telecommande.h)(0x6368CE08)() +F (.\FileInclude\Batterie.c)(0x637268C7)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\batterie.o --omf_browse .\objects\batterie.crf --depend .\objects\batterie.d) +I (FileInclude\Batterie.h)(0x63712E97) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) +I (.\RTE\_R_el\RTE_Components.h)(0x6352AB59) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) +I (FileInclude\MyADC.h)(0x6352AB58) +I (FileInclude\MyTimer.h)(0x6352B8A4) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +F (.\FileInclude\Batterie.h)(0x63712E97)() +F (RTE\Device\STM32F103RB\RTE_Device.h)(0x6352AB59)() +F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x6352AB59)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d) +F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x6352AB59)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_R_el -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) +I (.\RTE\_R_el\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) diff --git a/Objects/Projet1_SImulation.dep b/Objects/Projet1_SImulation.dep index bad3036..4cb5eb9 100644 --- a/Objects/Projet1_SImulation.dep +++ b/Objects/Projet1_SImulation.dep @@ -1,6 +1,6 @@ Dependencies for Project 'Projet1', Target 'SImulation': (DO NOT MODIFY !) CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC -F (.\Sources\main.c)(0x635B8BB4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d) +F (.\Sources\main.c)(0x63725877)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) @@ -12,7 +12,9 @@ I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_ I (.\FileInclude\Driver_GPIO.h)(0x6352AB58) I (.\FileInclude\MyTimer.h)(0x6352B8A4) I (.\FileInclude\MyADC.h)(0x6352AB58) -I (.\FileInclude\Plateau.h)(0x635B8BB4) +I (.\FileInclude\Plateau.h)(0x635B93E6) +I (.\FileInclude\Telecommande.h)(0x6368CE08) +I (.\FileInclude\Batterie.h)(0x63712E97) F (U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.c)(0x633153E6)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\driver_gpio.o --omf_browse .\objects\driver_gpio.crf --depend .\objects\driver_gpio.d) I (U:\Documents\4ir\S1\Microcontroleur\Drivers\FileInclude\Driver_GPIO.h)(0x63315001) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) @@ -23,7 +25,7 @@ I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_versio I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -F (.\FileInclude\MyTimer.c)(0x6352B8A4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d) +F (.\FileInclude\MyTimer.c)(0x635EAD7F)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\mytimer.o --omf_browse .\objects\mytimer.crf --depend .\objects\mytimer.d) I (FileInclude\MyTimer.h)(0x6352B8A4) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) @@ -48,7 +50,7 @@ I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_ I (FileInclude\MyTimer.h)(0x6352B8A4) I (FileInclude\Driver_GPIO.h)(0x6352AB58) F (.\FileInclude\MyADC.h)(0x6352AB58)() -F (.\FileInclude\Plateau.c)(0x635B8BB4)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\plateau.o --omf_browse .\objects\plateau.crf --depend .\objects\plateau.d) +F (.\FileInclude\Plateau.c)(0x635BB6D1)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\plateau.o --omf_browse .\objects\plateau.crf --depend .\objects\plateau.d) I (FileInclude\MyTimer.h)(0x6352B8A4) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) @@ -59,10 +61,36 @@ I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compil I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) I (FileInclude\Driver_GPIO.h)(0x6352AB58) -I (FileInclude\Plateau.h)(0x635B8BB4) -F (.\FileInclude\Telecommande.c)(0x6352B81B)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\telecommande.o --omf_browse .\objects\telecommande.crf --depend .\objects\telecommande.d) -F (.\FileInclude\Plateau.h)(0x635B8BB4)() -F (.\FileInclude\Telecommande.h)(0x6352B81B)() +I (FileInclude\Plateau.h)(0x635B93E6) +F (.\FileInclude\Telecommande.c)(0x6368E779)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\telecommande.o --omf_browse .\objects\telecommande.crf --depend .\objects\telecommande.d) +I (FileInclude\MyTimer.h)(0x6352B8A4) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) +I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +I (FileInclude\Plateau.h)(0x635B93E6) +I (FileInclude\Telecommande.h)(0x6368CE08) +F (.\FileInclude\Plateau.h)(0x635B93E6)() +F (.\FileInclude\Telecommande.h)(0x6368CE08)() +F (.\FileInclude\Batterie.c)(0x63712DDE)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\batterie.o --omf_browse .\objects\batterie.crf --depend .\objects\batterie.d) +I (FileInclude\Batterie.h)(0x63712E97) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) +I (.\RTE\_SImulation\RTE_Components.h)(0x6352AB59) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) +I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) +I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) +I (FileInclude\MyADC.h)(0x6352AB58) +I (FileInclude\MyTimer.h)(0x6352B8A4) +I (FileInclude\Driver_GPIO.h)(0x6352AB58) +F (.\FileInclude\Batterie.h)(0x63712E97)() F (RTE\Device\STM32F103RB\RTE_Device.h)(0x6352AB59)() F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x6352AB59)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d) F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x6352AB59)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\FileInclude -I.\RTE\Device\STM32F103RB -I.\RTE\_SImulation -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d) diff --git a/Objects/Projet1_Simulation.axf b/Objects/Projet1_Simulation.axf index 70958d2d9c78cbffb9c926cba7b9788574c633cc..379cda53ce22d2036150d2795a78a441dc84405a 100644 GIT binary patch delta 9514 zcma)?3shCtnaB4&`<}xE5iT!96uBZAG)M$75vy`Ri$K&MKEfyp7r4r85fLz}snN@% z>X6h}_1K)6#9$Kgm?q04H5q2Q@^aNqlPuEcO!H{d>7vs#P4imVkP*`=^Z)ie=iYOV z&a9rb_GSOR@7v%0_T%ic_cSG zbm3!Df-dIH;o)>2^3Nl^L$ag0CaagjnKa$Y6XSQO%>C?_thZBN$a9oq6YtD5@AcBFnR z!OKSe^D-M*`?cp~=Hb33Y3Hi+R?UEA0xVtLux-WI)T(UA;vq{QSqKgmjZLZQ4f;lV zeUq#E{FAF#pKp}aW>mX-;l9s1+FOfU4x}TAEIubJ^^JZ)(rl8tSbVlA9dR=&=S2?T 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zC6@Nt9xklO?gVJB(-0OC5svj6_6&5SDE<(p=k4a3@695AN7b>?c!r1 zLo8~%UAwvqfq{7wSBnpbS=#*vM5#JhHc@MPO5|wgpA|2UOVxi+WNWV<5`T1X3eNoQ zMX{L6xedVu*^3Vz7Av%;_K7`bF25uejE^$9R}|x+W_MNkE7$428|b&DOxx5e4$1iI z3U+aVcB5C6RA6$6T-IieNHjl~+hc_mXeA=0PdGZ#&$gx<_{tFElC|ev5i_NsDDCZ6 z#2hz$nz^K12Fcx%fSE{(J0fPvhw(n{eXq9kh{%-d8WD`pHlgm$ZNj-vdz?gu1A+}o z+A)yhF5=6J0z)(hwP~Lm5!2nnTkr>F+INtY_UzO$UlnuY-kpNwrfX|o6`9Ew4-0l! LkJ0#{Z0P!LdNRYY diff --git a/Objects/Projet1_Simulation.build_log.htm b/Objects/Projet1_Simulation.build_log.htm index 0923277..0949ca2 100644 --- a/Objects/Projet1_Simulation.build_log.htm +++ b/Objects/Projet1_Simulation.build_log.htm @@ -17,26 +17,27 @@ Library Manager: ArmAr.exe V5.06 update 7 (build 960) Hex Converter: FromElf.exe V5.06 update 7 (build 960) CPU DLL: SARMCM3.DLL V5.34.0.0 Dialog DLL: DARMSTM.DLL V1.68.0.0 -Target DLL: UL2CM3.DLL V1.163.9.0 +Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.8.0 Dialog DLL: TARMSTM.DLL V1.66.0.0

    Project:

    U:\Documents\4ir\S1\Microcontroleur\TP_Voilier\Projet1.uvprojx -Project File Date: 10/21/2022 +Project File Date: 11/13/2022

    Output:

    *** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin' -Rebuild target 'SImulation' -assembling startup_stm32f10x_md.s... -compiling Telecommande.c... -compiling Driver_GPIO.c... -compiling main.c... +Rebuild target 'Réel' compiling MyADC.c... compiling Plateau.c... -compiling system_stm32f10x.c... +compiling Batterie.c... +compiling Driver_GPIO.c... +compiling Telecommande.c... +compiling main.c... compiling MyTimer.c... +assembling startup_stm32f10x_md.s... +compiling system_stm32f10x.c... linking... -Program Size: Code=1680 RO-data=268 RW-data=32 ZI-data=1048 +Program Size: Code=1372 RO-data=268 RW-data=44 ZI-data=1092 ".\Objects\Projet1_Simulation.axf" - 0 Error(s), 0 Warning(s).

    Software Packages used:

    @@ -55,7 +56,7 @@ Package Vendor: Keil

    Collection of Component include folders:

    .\RTE\Device\STM32F103RB - .\RTE\_SImulation + .\RTE\_R_el C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include @@ -64,11 +65,11 @@ Package Vendor: Keil * Component: ARM::CMSIS:CORE:5.4.0 * Component: Keil::Device:Startup:1.0.0 - Source file: Device\Source\ARM\startup_stm32f10x_md.s Source file: Device\Source\system_stm32f10x.c - Source file: Device\Source\ARM\STM32F1xx_OPT.s Include file: RTE_Driver\Config\RTE_Device.h -Build Time Elapsed: 00:00:01 + Source file: Device\Source\ARM\STM32F1xx_OPT.s + Source file: Device\Source\ARM\startup_stm32f10x_md.s +Build Time Elapsed: 00:00:02 diff --git a/Objects/Projet1_Simulation.htm b/Objects/Projet1_Simulation.htm index 9715776..283008a 100644 --- a/Objects/Projet1_Simulation.htm +++ b/Objects/Projet1_Simulation.htm @@ -3,11 +3,11 @@ Static Call Graph - [.\Objects\Projet1_Simulation.axf]

    Static Call Graph for image .\Objects\Projet1_Simulation.axf

    -

    #<CALLGRAPH># ARM Linker, 5060960: Last Updated: Fri Oct 28 09:58:45 2022 +

    #<CALLGRAPH># ARM Linker, 5060960: Last Updated: Mon Nov 14 17:43:57 2022

    -

    Maximum Stack Usage = 60 bytes + Unknown(Cycles, Untraceable Function Pointers)

    +

    Maximum Stack Usage = 28 bytes + Unknown(Cycles, Untraceable Function Pointers)

    Call chain for Maximum Stack Depth:

    -main ⇒ Set_Moteur_Plateau ⇒ Init_Plateau ⇒ MyTimer_PWM ⇒ MyGPIO_Init +SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72

    Mutually Recursive functions @@ -58,7 +58,7 @@ Function Pointers
  • RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) -
  • Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
  • Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) @@ -72,7 +72,7 @@ Function Pointers
  • TIM2_IRQHandler from mytimer.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
  • TIM3_IRQHandler from mytimer.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
  • TIM4_IRQHandler from mytimer.o(i.TIM4_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) -
  • USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
  • USART1_IRQHandler from telecommande.o(i.USART1_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
  • USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) @@ -90,30 +90,31 @@ Global Symbols

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(.text)
    -

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) +

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) -

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) -

    [Calls]