From e6a35c80062945ebf605fb03578444586d6785d4 Mon Sep 17 00:00:00 2001 From: brunetto Date: Wed, 19 Apr 2023 12:45:06 +0200 Subject: [PATCH] =?UTF-8?q?Step=5FDFT=20-=20=C3=A9tapes=201=20et=202=20fon?= =?UTF-8?q?ctionnelles,=20=C3=A9tape=203=20non=20test=C3=A9e?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- soft/PjtKEIL_StepDFT/Src/DFT.s | 55 ++++++++++++++++--------- soft/PjtKEIL_StepDFT/Src/principal.c | 18 ++++++--- soft/PjtKEIL_StepDFT/StepDFT.uvoptx | 60 ++++++++++++++++++++++++++-- 3 files changed, 104 insertions(+), 29 deletions(-) diff --git a/soft/PjtKEIL_StepDFT/Src/DFT.s b/soft/PjtKEIL_StepDFT/Src/DFT.s index 273ec79..7ad12ab 100644 --- a/soft/PjtKEIL_StepDFT/Src/DFT.s +++ b/soft/PjtKEIL_StepDFT/Src/DFT.s @@ -13,37 +13,54 @@ ; =============================================================================================== - + EXPORT DFT_ModuleAuCarre ;Section ROM code (read only) : area moncode,code,readonly ; écrire le code ici - DFT_ModuleAuCarre proc + push {lr} + ;partie reelle + ;push {r0} + ldr r2,=TabCos + bl DFT_Partie + ;mov r3 ,r0 + ;partie imaginaire + ;pop {r0} + ;ldr r2,=TabSin + ;bl DFT_Partie + ; calcul dft + ;mul r0, r0 + ;mul r3, r3 + ;add r0, r3 + pop {pc} + endp + +; ====================== DFT Partie ====================================== + +DFT_Partie proc push {lr, r4, r5, r6} - mov r2, #0 ;Compteur de boucle + mov r5, #0 ;Compteur de boucle mov r3, #0 ;Partie Réelle - ldr r5, =TabCos -BOUCLER - cmp r2, #63 - bgt FINBOUCLER - mul r4, r1, r2 +BOUCLERR + cmp r5, #63 + bgt FINBOUCLERR + mul r4, r1, r5 ; k*n and r4, #63 ; p - ldrh r4, [r5, r4, LSL #1] ; TabCos(p) - ldrh r6, [r0, r2, LSL #1] ; LeSignal(n) - mul r4, r6 - add r3, r4 - add r2, #1 - bl BOUCLER -FINBOUCLER - mov r0, r3 + ldrsh r4, [r2, r4, LSL #1] ; TabCos(p) 1.15 + ldrh r6, [r0, r5, LSL #1] ; LeSignal(n) 1.12 + mul r4, r6 ; 2.27 + asr r4, #2 ; 4.25 + add r3, r4 ; 7.25 + add r5, #1 + b BOUCLERR +FINBOUCLERR + mov r0, r3 pop {pc, r4, r5, r6} endp - - - + ;Section ROM code (read only) : AREA Trigo, DATA, READONLY diff --git a/soft/PjtKEIL_StepDFT/Src/principal.c b/soft/PjtKEIL_StepDFT/Src/principal.c index 44e9fdd..1f7621d 100644 --- a/soft/PjtKEIL_StepDFT/Src/principal.c +++ b/soft/PjtKEIL_StepDFT/Src/principal.c @@ -4,6 +4,10 @@ int DFT_ModuleAuCarre( short int * Signal64ech, char k); +extern short int LeSignal; + +int tab [64]; + int main(void) { @@ -12,16 +16,18 @@ int main(void) // =========================================================================== // Après exécution : le coeur CPU est clocké à 72MHz ainsi que tous les timers -CLOCK_Configure(); - - +//CLOCK_Configure(); //============================================================================ - - + +for (int i=0;i<64;i++) +{ + char k = (char)i; + tab[i]= DFT_ModuleAuCarre( &LeSignal, k); +} + while (1) { - //DFT_ModuleAuCarre( LeSignal, 17); } } diff --git a/soft/PjtKEIL_StepDFT/StepDFT.uvoptx b/soft/PjtKEIL_StepDFT/StepDFT.uvoptx index f6e9a5b..c68e1b7 100644 --- a/soft/PjtKEIL_StepDFT/StepDFT.uvoptx +++ b/soft/PjtKEIL_StepDFT/StepDFT.uvoptx @@ -153,14 +153,66 @@ -U066CFF574857847167074929 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) - + + + 0 + 0 + 29 + 1 +
134218158
+ 0 + 0 + 0 + 0 + 0 + 1 + .\Src\principal.c + + \\\Src/principal.c\29 +
+
+ + + 0 + 1 + r4,0x0A + + + 1 + 1 + r6,0x0A + + + 2 + 1 + r0,0x0A + + + 3 + 1 + i,0x0A + + + 4 + 1 + k,0x0A + + + + + 1 + 0 + tab + 0 + + 0 0 1 - 1 + 0 0 0 0 @@ -174,7 +226,7 @@ 0 0 0 - 0 + 1 0 0 0 @@ -200,7 +252,7 @@ 0 ((portb & 0x00000002) >> 1 & 0x2) >> 1 - FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028706F7274622026203078303030303030303229203E3E2031000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F160000000000000000000000000000000000000096020008 + FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028706F7274622026203078303030303030303229203E3E2031000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F140000000000000000000000000000000000000096020008